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library ieee;
use ieee.std_logic_1164.all;
entity A_tb is
end entity;
architecture A_tb_impl of A_tb is
begin
a : work.a(a) port map(a => a); -- syntax error here, missing 'entity'
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity A_tb is
end entity;
architecture A_tb_impl of A_tb is
begin
a : work.a(a) port map(a => a); -- syntax error here, missing 'entity'
end architecture;
|
-- This block extracts the GPStudio header and gets flags Start of Frame and End of Frame.
-- It outputs a flow depending on this header (generate Flow valid and Data valid according to the flags).
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.com_package.all;
entity com_to_flow is
generic (
ID_FIFO : std_logic_vector(5 downto 0):="000001";
FLOW_OUT_SIZE : integer := 8;
DATA_WIDTH : integer := 8;
FIFO_DEPTH : integer := 2048
);
port (
clk_hal : in std_logic;
clk_proc : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
flow_out_data : out std_logic_vector(FLOW_OUT_SIZE-1 downto 0);
flow_out_fv : out std_logic;
flow_out_dv : out std_logic;
write_data : in std_logic;
data_in : in std_logic_vector(7 downto 0)
);
end com_to_flow;
architecture RTL of com_to_flow is
type fsm_com_to_flow is (idle, header, wr_data_st);
signal state : fsm_com_to_flow;
signal reset : std_logic;
signal empty_fifo : std_logic;
signal empty_fifo_dl : std_logic;
signal wrreq : std_logic;
signal set_wrreq : std_logic;
signal rdreq,rdreq_dl : std_logic;
signal sof : std_logic;
signal eof : std_logic;
signal write_data_dl : std_logic;
signal id_detected : std_logic_vector(5 downto 0);
begin
reset <= not reset_n;
--- Fifo that synchronizes data of the flow on clk_proc
fifo_data_inst : entity work.gp_dcfifo
generic map (DATA_WIDTH => 8,
FIFO_DEPTH => FIFO_DEPTH)
port map(
aclr => reset,
data => data_in,
rdclk => clk_proc,
rdreq => rdreq,
wrclk => clk_hal,
wrreq => wrreq,
q => flow_out_data,
rdempty => empty_fifo
);
--- Filter and remove GPStudio header to get flags and write only the data in the FIFO
process(clk_hal, reset_n)
begin
if reset_n='0' then
sof <= '0';
eof <= '0';
id_detected <= "000000";
elsif clk_hal'event and clk_hal='1' then
write_data_dl <= write_data;
case(state) is
when idle =>
set_wrreq <= '0';
if write_data='1' and write_data_dl='0' then
sof <= data_in(1);
eof <= data_in(0);
id_detected <= data_in(7 downto 2);
state <= header;
end if;
when header =>
if write_data='1' then
if id_detected=ID_FIFO then
state <= wr_data_st;
set_wrreq <= '1';
else
state <= idle;
set_wrreq <= '0';
end if;
end if;
when wr_data_st =>
if write_data='0' and write_data_dl='0' then
state <= idle;
end if;
when others =>
state <= idle;
end case;
end if;
end process;
wrreq <= set_wrreq when state=idle or state=header else
write_data;
--- Set data valid, flow valid and control the read request of the fifo
process(clk_proc, reset_n)
begin
if reset_n='0' then
rdreq <= '0';
flow_out_fv <= '0';
elsif clk_proc'event and clk_proc='1' then
rdreq <= not empty_fifo;
rdreq_dl <= rdreq;
empty_fifo_dl <= empty_fifo;
if rdreq='1' and rdreq_dl='0' then
if sof='1' then
flow_out_fv <= '1';
end if;
elsif empty_fifo='1' and empty_fifo_dl='0' then
if eof='1' then
flow_out_fv <= '0';
end if;
end if;
end if;
end process;
flow_out_dv <= rdreq_dl and not empty_fifo;
end RTL;
|
----------------------------------------------------------------------------------------------------
-- serial_multiplier.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Serial multiplier for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: The input buses need to have valid data when Reset signal is asserted
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
entity serial_multiplier_131 is
generic (
NUM_BITS : positive := 131 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_131;
-----------------------------------------------------------
architecture behave of serial_multiplier_131 is
-----------------------------------------------------------
-- m = 131 f (x) = x^131 + x^8 + x^3 + x^2 + 1
constant Fx: std_logic_vector(NUM_BITS-1 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001101";
-----------------------------------------------------------
signal Op1 : std_logic_vector(NUM_BITS-1 downto 0); -- Multiplexers for ax and cx depending upon b_i and c_m
signal Op2 : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal cx_shift : std_logic_vector(NUM_BITS-1 downto 0);
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
type CurrentState_type is (END_STATE, MUL_STATE);
signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
cx <= cx_int; -- Result of the multiplication
Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx and Cx to left one position
Cx_shift <= cx_int(NUM_BITS-2 downto 0)& '0';
-- Multiplexer to determine what value is added to C_x in each iteration
Op1 <= ax when bx_int(NUM_BITS-1) = '1' else -- The selector for these multiplexors are the most significant bits of B_x and C_x
(others => '0');
Op2 <= Fx when cx_int(NUM_BITS-1) = '1' else
(others => '0');
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "10000010"; -- m-1 value, in this case, it is 162, be sure to set the correct value
bx_int <= bx;
cx_int <= (others => '0');
Done <= '0';
CurrentState <= MUL_STATE;
else
case CurrentState is
when MUL_STATE => -- processes a bit of bx
Cx_int <= cx_shift xor Op1 xor Op2;
counter <= counter - 1;
if counter = "00000000" then -- The done signal is asserted at the same time that the result is computed.
CurrentState <= END_STATE;
Done <= '1';
else
bx_int <= bx_shift;
end if;
when END_STATE =>
CurrentState <= END_STATE;
Done <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
end behave;
|
-------------------------------------------------------------------------------
--
-- File: SyncBase.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes a signal (iIn) in one clock domain (InClk) with
-- another clock domain (OutClk) and provides it on oOut.
-- The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous resets (aiReset, aoReset) are always
-- active-high, and they should not be asserted independently.
-- Changelog:
-- 2020-Dec-14: Changed the single asynchronous reset source (aReset)
-- with 2 RSD reset (asynchronous assertion, synchronous de-assertion)
-- signals (aiReset, aoReset).
-- 2022-Oct-05: Added Constraints section to header. Added keep_hierarchy
-- attribute to entity.
--
-- Constraints:
-- # Replace <InstSyncBase> with path to SyncAsync instance, keep rest unchanged
-- # Begin scope to SyncBase instance
-- current_instance [get_cells <InstSyncBase>]
-- # Input to synchronizer ignored for timing analysis
-- set_false_path -through [get_pins SyncAsyncx/aIn]
-- # Constrain internal synchronizer paths to half-period, which is expected to be easily met with ASYNC_REG=true
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_ports -scoped_to_current_instance OutClk]]]
-- set_max_delay -from [get_cells SyncAsyncx/oSyncStages_reg[*]] -to [get_cells SyncAsyncx/oSyncStages_reg[*]] [expr $ClkPeriod/2]
-- current_instance -quiet
-- # End scope to SyncBase instance
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncBase is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aiReset : in STD_LOGIC; -- active-high asynchronous reset
InClk : in std_logic;
iIn : in STD_LOGIC;
aoReset : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
attribute keep_hierarchy : string;
attribute keep_hierarchy of SyncBase : entity is "yes";
end SyncBase;
architecture Behavioral of SyncBase is
signal iIn_q : std_logic;
begin
--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free
SyncSource: process(aiReset, InClk)
begin
if (aiReset = '1') then
iIn_q <= kResetTo;
elsif Rising_Edge(InClk) then
iIn_q <= iIn;
end if;
end process SyncSource;
--Crossing clock boundary here
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kResetTo,
kStages => kStages)
port map (
aoReset => aoReset,
aIn => iIn_q,
OutClk => OutClk,
oOut => oOut);
end Behavioral; |
-------------------------------------------------------------------------------
--
-- File: SyncBase.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 20 October 2014
-- Last modification date: 05 October 2022
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module synchronizes a signal (iIn) in one clock domain (InClk) with
-- another clock domain (OutClk) and provides it on oOut.
-- The number of FFs in the synchronizer chain
-- can be configured with kStages. The reset value for oOut can be configured
-- with kResetTo. The asynchronous resets (aiReset, aoReset) are always
-- active-high, and they should not be asserted independently.
-- Changelog:
-- 2020-Dec-14: Changed the single asynchronous reset source (aReset)
-- with 2 RSD reset (asynchronous assertion, synchronous de-assertion)
-- signals (aiReset, aoReset).
-- 2022-Oct-05: Added Constraints section to header. Added keep_hierarchy
-- attribute to entity.
--
-- Constraints:
-- # Replace <InstSyncBase> with path to SyncAsync instance, keep rest unchanged
-- # Begin scope to SyncBase instance
-- current_instance [get_cells <InstSyncBase>]
-- # Input to synchronizer ignored for timing analysis
-- set_false_path -through [get_pins SyncAsyncx/aIn]
-- # Constrain internal synchronizer paths to half-period, which is expected to be easily met with ASYNC_REG=true
-- set ClkPeriod [get_property PERIOD [get_clocks -of_objects [get_ports -scoped_to_current_instance OutClk]]]
-- set_max_delay -from [get_cells SyncAsyncx/oSyncStages_reg[*]] -to [get_cells SyncAsyncx/oSyncStages_reg[*]] [expr $ClkPeriod/2]
-- current_instance -quiet
-- # End scope to SyncBase instance
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SyncBase is
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
Port (
aiReset : in STD_LOGIC; -- active-high asynchronous reset
InClk : in std_logic;
iIn : in STD_LOGIC;
aoReset : in STD_LOGIC;
OutClk : in STD_LOGIC;
oOut : out STD_LOGIC);
attribute keep_hierarchy : string;
attribute keep_hierarchy of SyncBase : entity is "yes";
end SyncBase;
architecture Behavioral of SyncBase is
signal iIn_q : std_logic;
begin
--By re-registering iIn on its own domain, we make sure iIn_q is glitch-free
SyncSource: process(aiReset, InClk)
begin
if (aiReset = '1') then
iIn_q <= kResetTo;
elsif Rising_Edge(InClk) then
iIn_q <= iIn;
end if;
end process SyncSource;
--Crossing clock boundary here
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => kResetTo,
kStages => kStages)
port map (
aoReset => aoReset,
aIn => iIn_q,
OutClk => OutClk,
oOut => oOut);
end Behavioral; |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_pkg.ALL;
ENTITY system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:system_axi_interconnect_1_wrapper_fifo_generator_v9_1_3_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--!
--! @file: exercise8_1.vhd
--! @brief: mux with compenent and generate
--! @author: Antonio Gutierrez
--! @date: 2013-11-26
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity mux4to1 is
--generic declarations
port (
a, b, c, d: in std_logic;
sel: in std_logic_vector(1 downto 0);
x: out std_logic);
end entity mux4to1;
--------------------------------------
architecture circuit of mux4to1 is
--signals and declarations
begin
with sel select
x <= a when "00",
b when "01",
c when "10",
d when others;
end architecture circuit;
--------------------------------------
--------------------------------------
--------------------------------------
entity exercise8_1 is
generic (N: integer := 5);
port (
a, b, c, d: in std_logic_vector(N-1 downto 0);
sel: in std_logic_vector(1 downto 0);
x: out std_logic_vector(N-1 downto 0));
end entity exercise8_1;
--------------------------------------
architecture circuit of exercise8_1 is
component mux4to1 is
port (
a, b, c, d: in std_logic;
sel: in std_logic_vector(1 downto 0);
x: out std_logic);
end component mux4to1;
begin
gen1: for i in 0 to N-1 generate
mux1: mux port map (
a => a(i),
b => b(i),
c => c(i),
d => d(i)
);
end generate gen1;
end architecture circuit;
--------------------------------------
|
entity min01 is
port (a, b : natural;
o : out natural);
end min01;
architecture behav of min01 is
begin
o <= minimum (a, b);
end behav;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_k1_k2_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_k1_k2_e-c.vhd,v 1.2 2005/07/15 16:19:59 wig Exp $
-- $Date: 2005/07/15 16:19:59 $
-- $Log: inst_shadow_k1_k2_e-c.vhd,v $
-- Revision 1.2 2005/07/15 16:19:59 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_k1_k2_rtl_conf / inst_shadow_k1_k2_e
--
configuration inst_shadow_k1_k2_rtl_conf of inst_shadow_k1_k2_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_k1_k2_rtl_conf;
--
-- End of Generated Configuration inst_shadow_k1_k2_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
------------------------------------------------------------------------
-- RS232RefCom.vhd
------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description: This file defines a UART which tranfers data from
-- serial form to parallel form and vice versa.
------------------------------------------------------------------------
-- Revision History:
-- 07/15/04 (Created) DanP
-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
-- in the Clock Dividing Processes
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Rs232RefComp is
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock
DBIN : in std_logic_vector (7 downto 0); --Data Bus in
DBOUT : out std_logic_vector (7 downto 0); --Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Empty
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end Rs232RefComp;
architecture Behavioral of Rs232RefComp is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
--Receive state machine
type rstate is (
strIdle, --Idle state
strEightDelay, --Delays for 8 clock cycles
strGetData, --Shifts in the 8 data bits, and checks parity
strCheckStop --Sets framing error flag if Stop bit is wrong
);
type tstate is (
sttIdle, --Idle state
sttTransfer, --Move data into shift register
sttShift --Shift out data
);
type TBEstate is (
stbeIdle,
stbeSetTBE,
stbeWaitLoad,
stbeWaitWrite
);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
constant baudDivide : std_logic_vector(7 downto 0) := "10100011"; --Baud Rate dividor, set now for a rate of 9600.
--Found by dividing 50MHz by 9600 and 16.
signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register
signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register
signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register
signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register
signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk
signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk
signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times
signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer
signal rClk : std_logic := '0'; --Receiving Clock
signal tClk : std_logic; --Transfering Clock
signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits
signal parError: std_logic; --Parity error bit
signal frameError: std_logic; --Frame error bit
signal CE : std_logic; --Clock enable for the latch
signal ctRst : std_logic := '0';
signal load : std_logic := '0';
signal shift : std_logic := '0';
signal par : std_logic;
signal tClkRST : std_logic := '0';
signal rShift : std_logic := '0';
signal dataRST : std_logic := '0';
signal dataIncr: std_logic := '0';
signal strCur : rstate := strIdle; --Current state in the Receive state machine
signal strNext : rstate; --Next state in the Receive state machine
signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine
signal sttNext : tstate; --Next state in the Transfer staet machine
signal stbeCur : TBEstate := stbeIdle;
signal stbeNext: TBEstate;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
frameError <= not rdSReg(9);
parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
DBOUT <= rdReg;
tfReg <= DBIN;
par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
--Clock Dividing Functions--
process (CLK, clkDiv) --set up clock divide for rClk
begin
if (Clk = '1' and Clk'event) then
if (clkDiv = baudDivide) then
clkDiv <= "000000000";
else
clkDiv <= clkDiv +1;
end if;
end if;
end process;
process (clkDiv, rClk, CLK) --Define rClk
begin
if CLK = '1' and CLK'Event then
if clkDiv = baudDivide then
rClk <= not rClk;
else
rClk <= rClk;
end if;
end if;
end process;
process (rClk) --set up clock divide for tClk
begin
if (rClk = '1' and rClk'event) then
rClkDiv <= rClkDiv +1;
end if;
end process;
tClk <= rClkDiv(3); --define tClk
process (rClk, ctRst) --set up a counter based on rClk
begin
if rClk = '1' and rClk'Event then
if ctRst = '1' then
ctr <= "0000";
else
ctr <= ctr +1;
end if;
end if;
end process;
process (tClk, tClkRST) --set up a counter based on tClk
begin
if (tClk = '1' and tClk'event) then
if tClkRST = '1' then
tfCtr <= "0000";
else
tfCtr <= tfCtr +1;
end if;
end if;
end process;
--This process controls the error flags--
process (rClk, RST, RD, CE)
begin
if RD = '1' or RST = '1' then
FE <= '0';
OE <= '0';
RDA <= '0';
PE <= '0';
elsif rClk = '1' and rClk'event then
if CE = '1' then
FE <= frameError;
OE <= RDA;
RDA <= '1';
PE <= parError;
rdReg(7 downto 0) <= rdSReg (7 downto 0);
end if;
end if;
end process;
--This process controls the receiving shift register--
process (rClk, rShift)
begin
if rClk = '1' and rClk'Event then
if rShift = '1' then
rdSReg <= (RXD & rdSReg(9 downto 1));
end if;
end if;
end process;
--This process controls the dataCtr to keep track of shifted values--
process (rClk, dataRST)
begin
if (rClk = '1' and rClk'event) then
if dataRST = '1' then
dataCtr <= "0000";
elsif dataIncr = '1' then
dataCtr <= dataCtr +1;
end if;
end if;
end process;
--Receiving State Machine--
process (rClk, RST)
begin
if rClk = '1' and rClk'Event then
if RST = '1' then
strCur <= strIdle;
else
strCur <= strNext;
end if;
end if;
end process;
--This process generates the sequence of steps needed receive the data
process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
begin
case strCur is
when strIdle =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
CE <= '0';
if RXD = '0' then
ctRst <= '1';
strNext <= strEightDelay;
else
ctRst <= '0';
strNext <= strIdle;
end if;
when strEightDelay =>
dataIncr <= '0';
rShift <= '0';
CE <= '0';
if ctr(2 downto 0) = "111" then
ctRst <= '1';
dataRST <= '1';
strNext <= strGetData;
else
ctRst <= '0';
dataRST <= '0';
strNext <= strEightDelay;
end if;
when strGetData =>
CE <= '0';
dataRst <= '0';
if ctr(3 downto 0) = "1111" then
ctRst <= '1';
dataIncr <= '1';
rShift <= '1';
else
ctRst <= '0';
dataIncr <= '0';
rShift <= '0';
end if;
if dataCtr = "1010" then
strNext <= strCheckStop;
else
strNext <= strGetData;
end if;
when strCheckStop =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
ctRst <= '0';
CE <= '1';
strNext <= strIdle;
end case;
end process;
--TBE State Machine--
process (CLK, RST)
begin
if CLK = '1' and CLK'Event then
if RST = '1' then
stbeCur <= stbeIdle;
else
stbeCur <= stbeNext;
end if;
end if;
end process;
--This process gererates the sequence of events needed to control the TBE flag--
process (stbeCur, CLK, WR, DBIN, load)
begin
case stbeCur is
when stbeIdle =>
TBE <= '1';
if WR = '1' then
stbeNext <= stbeSetTBE;
else
stbeNext <= stbeIdle;
end if;
when stbeSetTBE =>
TBE <= '0';
if load = '1' then
stbeNext <= stbeWaitLoad;
else
stbeNext <= stbeSetTBE;
end if;
when stbeWaitLoad =>
if load = '0' then
stbeNext <= stbeWaitWrite;
else
stbeNext <= stbeWaitLoad;
end if;
when stbeWaitWrite =>
if WR = '0' then
stbeNext <= stbeIdle;
else
stbeNext <= stbeWaitWrite;
end if;
end case;
end process;
--This process loads and shifts out the transfer shift register--
process (load, shift, tClk, tfSReg)
begin
TXD <= tfsReg(0);
if tClk = '1' and tClk'Event then
if load = '1' then
tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
end if;
if shift = '1' then
tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
end if;
end if;
end process;
-- Transfer State Machine--
process (tClk, RST)
begin
if (tClk = '1' and tClk'Event) then
if RST = '1' then
sttCur <= sttIdle;
else
sttCur <= sttNext;
end if;
end if;
end process;
-- This process generates the sequence of steps needed transfer the data--
process (sttCur, tfCtr, tfReg, TBE, tclk)
begin
case sttCur is
when sttIdle =>
tClkRST <= '0';
shift <= '0';
load <= '0';
if TBE = '1' then
sttNext <= sttIdle;
else
sttNext <= sttTransfer;
end if;
when sttTransfer =>
shift <= '0';
load <= '1';
tClkRST <= '1';
sttNext <= sttShift;
when sttShift =>
shift <= '1';
load <= '0';
tClkRST <= '0';
if tfCtr = "1100" then
sttNext <= sttIdle;
else
sttNext <= sttShift;
end if;
end case;
end process;
end Behavioral; |
------------------------------------------------------------------------
-- RS232RefCom.vhd
------------------------------------------------------------------------
-- Author: Dan Pederson
-- Copyright 2004 Digilent, Inc.
------------------------------------------------------------------------
-- Description: This file defines a UART which tranfers data from
-- serial form to parallel form and vice versa.
------------------------------------------------------------------------
-- Revision History:
-- 07/15/04 (Created) DanP
-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
-- in the Clock Dividing Processes
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Rs232RefComp is
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock
DBIN : in std_logic_vector (7 downto 0); --Data Bus in
DBOUT : out std_logic_vector (7 downto 0); --Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Empty
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end Rs232RefComp;
architecture Behavioral of Rs232RefComp is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
--Receive state machine
type rstate is (
strIdle, --Idle state
strEightDelay, --Delays for 8 clock cycles
strGetData, --Shifts in the 8 data bits, and checks parity
strCheckStop --Sets framing error flag if Stop bit is wrong
);
type tstate is (
sttIdle, --Idle state
sttTransfer, --Move data into shift register
sttShift --Shift out data
);
type TBEstate is (
stbeIdle,
stbeSetTBE,
stbeWaitLoad,
stbeWaitWrite
);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
constant baudDivide : std_logic_vector(7 downto 0) := "10100011"; --Baud Rate dividor, set now for a rate of 9600.
--Found by dividing 50MHz by 9600 and 16.
signal rdReg : std_logic_vector(7 downto 0) := "00000000"; --Receive holding register
signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register
signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register
signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register
signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk
signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk
signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times
signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer
signal rClk : std_logic := '0'; --Receiving Clock
signal tClk : std_logic; --Transfering Clock
signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits
signal parError: std_logic; --Parity error bit
signal frameError: std_logic; --Frame error bit
signal CE : std_logic; --Clock enable for the latch
signal ctRst : std_logic := '0';
signal load : std_logic := '0';
signal shift : std_logic := '0';
signal par : std_logic;
signal tClkRST : std_logic := '0';
signal rShift : std_logic := '0';
signal dataRST : std_logic := '0';
signal dataIncr: std_logic := '0';
signal strCur : rstate := strIdle; --Current state in the Receive state machine
signal strNext : rstate; --Next state in the Receive state machine
signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine
signal sttNext : tstate; --Next state in the Transfer staet machine
signal stbeCur : TBEstate := stbeIdle;
signal stbeNext: TBEstate;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
frameError <= not rdSReg(9);
parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
DBOUT <= rdReg;
tfReg <= DBIN;
par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
--Clock Dividing Functions--
process (CLK, clkDiv) --set up clock divide for rClk
begin
if (Clk = '1' and Clk'event) then
if (clkDiv = baudDivide) then
clkDiv <= "000000000";
else
clkDiv <= clkDiv +1;
end if;
end if;
end process;
process (clkDiv, rClk, CLK) --Define rClk
begin
if CLK = '1' and CLK'Event then
if clkDiv = baudDivide then
rClk <= not rClk;
else
rClk <= rClk;
end if;
end if;
end process;
process (rClk) --set up clock divide for tClk
begin
if (rClk = '1' and rClk'event) then
rClkDiv <= rClkDiv +1;
end if;
end process;
tClk <= rClkDiv(3); --define tClk
process (rClk, ctRst) --set up a counter based on rClk
begin
if rClk = '1' and rClk'Event then
if ctRst = '1' then
ctr <= "0000";
else
ctr <= ctr +1;
end if;
end if;
end process;
process (tClk, tClkRST) --set up a counter based on tClk
begin
if (tClk = '1' and tClk'event) then
if tClkRST = '1' then
tfCtr <= "0000";
else
tfCtr <= tfCtr +1;
end if;
end if;
end process;
--This process controls the error flags--
process (rClk, RST, RD, CE)
begin
if RD = '1' or RST = '1' then
FE <= '0';
OE <= '0';
RDA <= '0';
PE <= '0';
elsif rClk = '1' and rClk'event then
if CE = '1' then
FE <= frameError;
OE <= RDA;
RDA <= '1';
PE <= parError;
rdReg(7 downto 0) <= rdSReg (7 downto 0);
end if;
end if;
end process;
--This process controls the receiving shift register--
process (rClk, rShift)
begin
if rClk = '1' and rClk'Event then
if rShift = '1' then
rdSReg <= (RXD & rdSReg(9 downto 1));
end if;
end if;
end process;
--This process controls the dataCtr to keep track of shifted values--
process (rClk, dataRST)
begin
if (rClk = '1' and rClk'event) then
if dataRST = '1' then
dataCtr <= "0000";
elsif dataIncr = '1' then
dataCtr <= dataCtr +1;
end if;
end if;
end process;
--Receiving State Machine--
process (rClk, RST)
begin
if rClk = '1' and rClk'Event then
if RST = '1' then
strCur <= strIdle;
else
strCur <= strNext;
end if;
end if;
end process;
--This process generates the sequence of steps needed receive the data
process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
begin
case strCur is
when strIdle =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
CE <= '0';
if RXD = '0' then
ctRst <= '1';
strNext <= strEightDelay;
else
ctRst <= '0';
strNext <= strIdle;
end if;
when strEightDelay =>
dataIncr <= '0';
rShift <= '0';
CE <= '0';
if ctr(2 downto 0) = "111" then
ctRst <= '1';
dataRST <= '1';
strNext <= strGetData;
else
ctRst <= '0';
dataRST <= '0';
strNext <= strEightDelay;
end if;
when strGetData =>
CE <= '0';
dataRst <= '0';
if ctr(3 downto 0) = "1111" then
ctRst <= '1';
dataIncr <= '1';
rShift <= '1';
else
ctRst <= '0';
dataIncr <= '0';
rShift <= '0';
end if;
if dataCtr = "1010" then
strNext <= strCheckStop;
else
strNext <= strGetData;
end if;
when strCheckStop =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
ctRst <= '0';
CE <= '1';
strNext <= strIdle;
end case;
end process;
--TBE State Machine--
process (CLK, RST)
begin
if CLK = '1' and CLK'Event then
if RST = '1' then
stbeCur <= stbeIdle;
else
stbeCur <= stbeNext;
end if;
end if;
end process;
--This process gererates the sequence of events needed to control the TBE flag--
process (stbeCur, CLK, WR, DBIN, load)
begin
case stbeCur is
when stbeIdle =>
TBE <= '1';
if WR = '1' then
stbeNext <= stbeSetTBE;
else
stbeNext <= stbeIdle;
end if;
when stbeSetTBE =>
TBE <= '0';
if load = '1' then
stbeNext <= stbeWaitLoad;
else
stbeNext <= stbeSetTBE;
end if;
when stbeWaitLoad =>
if load = '0' then
stbeNext <= stbeWaitWrite;
else
stbeNext <= stbeWaitLoad;
end if;
when stbeWaitWrite =>
if WR = '0' then
stbeNext <= stbeIdle;
else
stbeNext <= stbeWaitWrite;
end if;
end case;
end process;
--This process loads and shifts out the transfer shift register--
process (load, shift, tClk, tfSReg)
begin
TXD <= tfsReg(0);
if tClk = '1' and tClk'Event then
if load = '1' then
tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
end if;
if shift = '1' then
tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
end if;
end if;
end process;
-- Transfer State Machine--
process (tClk, RST)
begin
if (tClk = '1' and tClk'Event) then
if RST = '1' then
sttCur <= sttIdle;
else
sttCur <= sttNext;
end if;
end if;
end process;
-- This process generates the sequence of steps needed transfer the data--
process (sttCur, tfCtr, tfReg, TBE, tclk)
begin
case sttCur is
when sttIdle =>
tClkRST <= '0';
shift <= '0';
load <= '0';
if TBE = '1' then
sttNext <= sttIdle;
else
sttNext <= sttTransfer;
end if;
when sttTransfer =>
shift <= '0';
load <= '1';
tClkRST <= '1';
sttNext <= sttShift;
when sttShift =>
shift <= '1';
load <= '0';
tClkRST <= '0';
if tfCtr = "1100" then
sttNext <= sttIdle;
else
sttNext <= sttShift;
end if;
end case;
end process;
end Behavioral; |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(6-1 DOWNTO 0);
DOUT : OUT std_logic_vector(6-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes;
architecture xilinx of system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1_exdes is
signal clk_i : std_logic;
component system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(6-1 DOWNTO 0);
DOUT : OUT std_logic_vector(6-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : system_axi_interconnect_1_wrapper_fifo_generator_v9_1_1
PORT MAP (
CLK => clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
package eclipse_components is
component RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end component;
component RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end component;
component RAM512X4_25um
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end component;
component RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end component;
end eclipse_components;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity eclipse_sim_ram is
generic (abits : integer := 8; dbits : integer := 16);
port (WA, RA : in std_logic_vector (abits-1 downto 0);
WD : in std_logic_vector (dbits-1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (dbits-1 downto 0) );
end;
architecture arch of eclipse_sim_ram is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
begin
rp : process(rclk, wclk, re, ra, asyncrd)
variable rfd : dregtype;
begin
if rising_edge(wclk) then
if we = '1' then rfd(conv_integer(wa)) := WD; end if;
end if;
if (re = '1') and (ASYNCRD = '1') then
RD <= rfd(conv_integer(ra));
end if;
if rising_edge(rclk) and (re = '1') and (ASYNCRD = '0') then
RD <= rfd(conv_integer(ra));
end if;
end process;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM128X18_25um is
port (WA, RA : in std_logic_vector (6 downto 0);
WD : in std_logic_vector (17 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (17 downto 0) );
end RAM128X18_25um;
architecture arch of RAM128X18_25um is
begin
x : entity work.eclipse_sim_ram generic map (7, 18)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM256X9_25um is
port (WA, RA : in std_logic_vector (7 downto 0);
WD : in std_logic_vector (8 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (8 downto 0) );
end RAM256X9_25um;
architecture arch of RAM256X9_25um is
begin
x : entity work.eclipse_sim_ram generic map (8, 9)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM512X4_25um is
port (WA, RA : in std_logic_vector (8 downto 0);
WD : in std_logic_vector (3 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (3 downto 0));
end RAM512X4_25um;
architecture arch of RAM512X4_25um is
begin
x : entity work.eclipse_sim_ram generic map (9, 4)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity RAM1024X2_25um is
port (WA, RA : in std_logic_vector (9 downto 0);
WD : in std_logic_vector (1 downto 0);
WE, RE, WCLK, RCLK, ASYNCRD : in std_logic;
RD : out std_logic_vector (1 downto 0) );
end RAM1024X2_25um;
architecture arch of RAM1024X2_25um is
begin
x : entity work.eclipse_sim_ram generic map (10, 2)
port map (wa, ra, wd, we, re, wclk, rclk, asyncrd, rd);
end arch;
|
-------------------------------------------------------------------------------
--! @file dpRamSplx-e.vhd
--
--! @brief Simplex Dual Port Ram Entity
--
--! @details This is the Simplex DPRAM entity.
--! The DPRAM has one write and one read port only.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity dpRamSplx is
generic (
--! Word width port A [bit]
gWordWidthA : natural := 16;
--! Byteenable width port A [bit]
gByteenableWidthA : natural := 2;
--! Number of words (reference is port A)
gNumberOfWordsA : natural := 1024;
--! Word width port B [bit]
gWordWidthB : natural := 32;
--! Number of words (reference is port B)
gNumberOfWordsB : natural := 512;
--! Initialization file
gInitFile : string := "UNUSED"
);
port (
-- PORT A
--! Clock of port A
iClk_A : in std_logic;
--! Enable of port A
iEnable_A : in std_logic;
--! Write enable of port A
iWriteEnable_A : in std_logic;
--! Address of port A
iAddress_A : in std_logic_vector(logDualis(gNumberOfWordsA)-1 downto 0);
--! Byteenable of port A
iByteenable_A : in std_logic_vector(gByteenableWidthA-1 downto 0);
--! Writedata of port A
iWritedata_A : in std_logic_vector(gWordWidthA-1 downto 0);
-- PORT B
--! Clock of port B
iClk_B : in std_logic;
--! Enable of port B
iEnable_B : in std_logic;
--! Address of port B
iAddress_B : in std_logic_vector(logDualis(gNumberOfWordsB)-1 downto 0);
--! Readdata of port B
oReaddata_B : out std_logic_vector(gWordWidthB-1 downto 0)
);
end dpRamSplx;
|
--
-- This file is part of top_wireworld
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.my_package.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_wireworld is
port(
clk : in std_logic;
w1a : inout std_logic_vector(15 downto 0);
w1b : inout std_logic_vector(15 downto 0);
w2c : inout std_logic_vector(15 downto 0);
rx : in std_logic;
tx : inout std_logic
);
end top_wireworld;
architecture Behavioral of top_wireworld is
-- component wireworld_cell is
-- generic (
-- init_state : state_type := t_copper
-- );
-- Port ( clk : in STD_LOGIC;
-- reset : in STD_LOGIC;
-- neighbours : in STD_LOGIC_VECTOR (7 downto 0);
-- electron_head : out STD_LOGIC;
-- electron_queue : out STD_LOGIC);
-- end component;
signal reset : std_logic;
signal to_0 : std_logic_vector (7 downto 0);
signal to_1 : std_logic_vector (7 downto 0);
signal to_2 : std_logic_vector (7 downto 0);
signal from_0 : std_logic;
signal from_1 : std_logic;
signal from_2 : std_logic;
begin
-- to_0 <= (0 => from_1,others => '0');
-- to_1 <= (0 => from_0,others => '0');
to_0 <= (0=> from_2, others => '0');
to_1 <= (0=> from_0, others => '0');
to_2 <= (0=> from_1, others => '0');
cell_0 : entity work.wireworld_cell
generic map( init_state => t_electron_head )
port map (
clk => clk,
reset => reset,
neighbours => to_0,
electron_head => from_0,
electron_queue => w1a(2)
);
cell_1 : entity work.wireworld_cell
port map (
clk => clk,
reset => reset,
neighbours => to_1,
electron_head => from_1,
electron_queue => w1a(6)
);
cell_2 : entity work.wireworld_cell
port map (
clk => clk,
reset => reset,
neighbours => to_2,
electron_head => from_2,
electron_queue => w1a(10)
);
w1a(0) <= from_0;
w1a(4) <= from_1;
w1a(8) <= from_2;
reset <= '0';
end Behavioral;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY DIGDUG_ROM IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END DIGDUG_ROM;
ARCHITECTURE DIGDUG_ROM_arch OF DIGDUG_ROM IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DIGDUG_ROM_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF DIGDUG_ROM_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF DIGDUG_ROM_arch : ARCHITECTURE IS "DIGDUG_ROM,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF DIGDUG_ROM_arch: ARCHITECTURE IS "DIGDUG_ROM,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=DIGDUG_ROM.mif,C_INIT_FILE=DIGDUG_ROM.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=4,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.326399 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "DIGDUG_ROM.mif",
C_INIT_FILE => "DIGDUG_ROM.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 16384,
C_READ_DEPTH_A => 16384,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 16384,
C_READ_DEPTH_B => 16384,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "4",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.326399 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 14)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END DIGDUG_ROM_arch;
|
----------------------------------------------------------------------------------
-- Module Name: test_source - Behavioral
--
-- Description: Provides a valid stream of DisplayPort Video data
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-10-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test_source is
Port ( clk : in STD_LOGIC;
stream_channel_count : out std_logic_vector(2 downto 0);
ready : out STD_LOGIC;
data : out STD_LOGIC_VECTOR (72 downto 0));
end test_source;
architecture Behavioral of test_source is
component test_source_800_600_RGB_444_colourbars_ch1 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component test_source_800_600_RGB_444_ch1 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component test_source_3840_2160_YCC_422_ch2 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component test_source_800_600_RGB_444_ch2 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component test_source_800_600_RGB_444_ch4 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end component;
component insert_main_stream_attrbutes_one_channel is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_YCC_colour_709 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0));
end component;
component insert_main_stream_attrbutes_two_channels is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_YCC_colour_709 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0));
end component;
component insert_main_stream_attrbutes_four_channels is
port (
clk : std_logic;
-----------------------------------------------------
-- This determines how the MSA is packed
-----------------------------------------------------
active : std_logic;
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : in std_logic_vector(23 downto 0);
N_value : in std_logic_vector(23 downto 0);
H_visible : in std_logic_vector(11 downto 0);
V_visible : in std_logic_vector(11 downto 0);
H_total : in std_logic_vector(11 downto 0);
V_total : in std_logic_vector(11 downto 0);
H_sync_width : in std_logic_vector(11 downto 0);
V_sync_width : in std_logic_vector(11 downto 0);
H_start : in std_logic_vector(11 downto 0);
V_start : in std_logic_vector(11 downto 0);
H_vsync_active_high : in std_logic;
V_vsync_active_high : in std_logic;
flag_sync_clock : in std_logic;
flag_YCCnRGB : in std_logic;
flag_422n444 : in std_logic;
flag_YCC_colour_709 : in std_logic;
flag_range_reduced : in std_logic;
flag_interlaced_even : in std_logic;
flags_3d_Indicators : in std_logic_vector(1 downto 0);
bits_per_colour : in std_logic_vector(4 downto 0);
-----------------------------------------------------
-- The stream of pixel data coming in and out
-----------------------------------------------------
in_data : in std_logic_vector(72 downto 0);
out_data : out std_logic_vector(72 downto 0));
end component;
signal M_value : std_logic_vector(23 downto 0);
signal N_value : std_logic_vector(23 downto 0);
signal H_visible : std_logic_vector(11 downto 0);
signal V_visible : std_logic_vector(11 downto 0);
signal H_total : std_logic_vector(11 downto 0);
signal V_total : std_logic_vector(11 downto 0);
signal H_sync_width : std_logic_vector(11 downto 0);
signal V_sync_width : std_logic_vector(11 downto 0);
signal H_start : std_logic_vector(11 downto 0);
signal V_start : std_logic_vector(11 downto 0);
signal H_vsync_active_high : std_logic;
signal V_vsync_active_high : std_logic;
signal flag_sync_clock : std_logic;
signal flag_YCCnRGB : std_logic;
signal flag_422n444 : std_logic;
signal flag_YCC_colour_709 : std_logic;
signal flag_range_reduced : std_logic;
signal flag_interlaced_even : std_logic;
signal flags_3d_Indicators : std_logic_vector(1 downto 0);
signal bits_per_colour : std_logic_vector(4 downto 0);
signal raw_data : std_logic_vector(72 downto 0) := (others => '0'); -- With switching point
begin
--i_test_source: test_source_3840_2160_YCC_422_ch2 port map (
--i_test_source: test_source_800_600_RGB_444_ch1 port map (
--i_test_source: test_source_800_600_RGB_444_ch2 port map (
--i_test_source: test_source_800_600_RGB_444_ch4 port map (
i_test_source: test_source_800_600_RGB_444_colourbars_ch1 port map (
M_value => M_value,
N_value => N_value,
H_visible => H_visible,
H_total => H_total,
H_sync_width => H_sync_width,
H_start => H_start,
V_visible => V_visible,
V_total => V_total,
V_sync_width => V_sync_width,
V_start => V_start,
H_vsync_active_high => H_vsync_active_high,
V_vsync_active_high => V_vsync_active_high,
flag_sync_clock => flag_sync_clock,
flag_YCCnRGB => flag_YCCnRGB,
flag_422n444 => flag_422n444,
flag_range_reduced => flag_range_reduced,
flag_interlaced_even => flag_interlaced_even,
flag_YCC_colour_709 => flag_YCC_colour_709,
flags_3d_Indicators => flags_3d_Indicators,
bits_per_colour => bits_per_colour,
stream_channel_count => stream_channel_count,
clk => clk,
ready => ready,
data => raw_data
);
i_insert_main_stream_attrbutes_one_channel: insert_main_stream_attrbutes_one_channel port map (
--i_insert_main_stream_attrbutes_two_channels: insert_main_stream_attrbutes_two_channels port map (
--i_insert_main_stream_attrbutes_four_channels: insert_main_stream_attrbutes_four_channels port map (
clk => clk,
active => '1',
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value => M_value,
N_value => N_value,
H_visible => H_visible,
H_total => H_total,
H_sync_width => H_sync_width,
H_start => H_start,
V_visible => V_visible,
V_total => V_total,
V_sync_width => V_sync_width,
V_start => V_start,
H_vsync_active_high => H_vsync_active_high,
V_vsync_active_high => V_vsync_active_high,
flag_sync_clock => flag_sync_clock,
flag_YCCnRGB => flag_YCCnRGB,
flag_422n444 => flag_422n444,
flag_range_reduced => flag_range_reduced,
flag_interlaced_even => flag_interlaced_even,
flag_YCC_colour_709 => flag_YCC_colour_709,
flags_3d_Indicators => flags_3d_Indicators,
bits_per_colour => bits_per_colour,
-----------------------------------------------------
-- The stream of pixel data coming in
-----------------------------------------------------
in_data => raw_data,
-----------------------------------------------------
-- The stream of pixel data going out
-----------------------------------------------------
out_data => data
);
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Eth_TestSig_Cfg.all;
entity g_ethrx_input is
generic(
HEAD_AWIDTH : natural := 5; -- ½ÓÊÕ¶ÓÁеØÖ·¿í¶È 2^5 = 32 ×Ö½Ú
BUFF_AWIDTH : natural := 16 -- BUFF16λµØÖ·Ïß
);
port(
-- test_crc : out std_logic_vector(3 downto 0);
clk : in std_logic; -- FPGAʱÖÓ
reset : in std_logic;
rxclk : in std_logic; -- GMIIÊä³öʱÖÓ
rxd : in std_logic_vector(7 downto 0); -- ²¢¿ÚÊäÈëÊý¾Ý£¬8bitΪµ¥Î»£¨byte£©
rxdv : in std_logic; -- ÔÚRXDV='1'µÄÇé¿öϼì²âµ½"5..5D"£¬±íʾһ¸öÒÔÌ«°üµÄ¿ªÊ¼
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked: out std_logic;
head_wren : out std_logic;
head_waddr : out std_logic_vector(HEAD_AWIDTH - 1 downto 0); --ÿһ¸ö°ü´Ó0¿ªÊ¼µÝÔö¼ÆÊý
head_wdata : out std_logic_vector(7 downto 0);
head_wr_block : out std_logic; -- ָʾCRC½á¹û£¬'1'±íʾÕýÈ·£¬'0'±íʾ²»ÕýÈ·
buff_wren : out std_logic;
buff_waddr : out std_logic_vector(BUFF_AWIDTH - 1 downto 0);
buff_wdata : out std_logic_vector(31 downto 0) -- ÒÔÌ«°üÊý¾Ý°´×Ö½Úд³ö£¬Ð´µØÖ·´ÓÉÏ´ÎдµØÖ·µÄĩβµÝÔö£¬°üº¬ÒÔÌ«°üÍ·
);
end g_ethrx_input;
architecture arch_ethrx_input of g_ethrx_input is
component fifo_async_almost_full
generic(
DEPTH : NATURAL;
AWIDTH : NATURAL;
DWIDTH : NATURAL;
RAM_TYPE : STRING);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector((DWIDTH-1) downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector((DWIDTH-1) downto 0);
empty : out std_logic;
almost_full : out std_logic;
full : out std_logic;
dn : out std_logic_vector((AWIDTH-1) downto 0));
end component;
for all: fifo_async_almost_full use entity WORK.fifo_async_almost_full(fast_read);
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
-- component crcrom
-- port(
-- addr : in std_logic_vector(3 downto 0);
-- dout : out std_logic_vector(31 downto 0));
-- end component;
component crc8_blkrom
port(
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(31 downto 0));
end component;
component ASYNCWRITE
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end component;
constant INFO_LENGTH : natural := 4;
constant HEAD_LENGTH : natural := 2 ** HEAD_AWIDTH - INFO_LENGTH;
signal rxdv_buf : std_logic;
signal rxd_buf : std_logic_vector(7 downto 0);
-- signal d_ext : std_logic_vector(8 downto 0);
-- signal rxdv_int : std_logic;
-- signal rxd_int : std_logic_vector(7 downto 0);
-- signal d_int : std_logic_vector(8 downto 0);
signal ce : std_logic;
-- signal rd_ena : std_logic;
-- signal empty : std_logic;
signal RxFIFO_clr : std_logic;
signal RxFIFO_wea : std_logic;
signal RxFIFO_dia : std_logic_vector(31 downto 0);
signal RxFIFO_rdb : std_logic;
signal RxFIFO_dob : std_logic_vector(31 downto 0);
signal RxFIFO_empty : std_logic;
signal RxFIFO_not_empty : std_logic;
signal RxFIFO_clr_int : std_logic;
signal rx_state : std_logic_vector(1 downto 0);
signal rx_state_d1 : std_logic_vector(1 downto 0);
signal rx_state_int : std_logic_vector(1 downto 0);
signal rx_state_int_d1 : std_logic_vector(1 downto 0);
signal byte_cnt : std_logic_vector(11 downto 0);
signal byte_cnt_int : std_logic_vector(11 downto 0);
signal byte_cnt_int_d1 : std_logic_vector(11 downto 0);
signal rx_end_ext : std_logic;
signal rx_end_int : std_logic;
signal rxd_buf_d1 : std_logic_vector(7 downto 0);
signal rxd_buf_d2 : std_logic_vector(7 downto 0);
signal rxd_buf_d3 : std_logic_vector(7 downto 0);
signal rxd_buf_d4 : std_logic_vector(7 downto 0);
signal dword_data_ext : std_logic_vector(31 downto 0);
signal dword_data_int : std_logic_vector(31 downto 0);
signal dword_data_buf : std_logic_vector(23 downto 0);
signal byte_data_int : std_logic_vector(7 downto 0);
signal buff_wren_buf : std_logic;
signal buff_waddr_buf : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal crc_din : std_logic_vector(7 downto 0);
signal crc_reg : std_logic_vector(31 downto 0);
signal crc_reg_d1 : std_logic_vector(31 downto 0);
signal crcrom_addr : std_logic_vector(7 downto 0);
signal crcrom_dout : std_logic_vector(31 downto 0);
signal crc_flag : std_logic;
signal info_cnt : integer range 0 to INFO_LENGTH;
signal info_ena : std_logic;
signal start_addr : std_logic_vector(15 downto 0);
signal length : std_logic_vector(15 downto 0);
signal head_wren_buf : std_logic;
signal head_waddr_buf : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal head_wr_block_buf: std_logic;
signal rxclk_temp : std_logic;
signal localtime_locked_reg: std_logic;
begin
-- process(clk)
-- begin
-- if rising_edge(clk) then
-- if info_ena = '1' then
-- test_crc(0) <= crc_flag;
-- test_crc(1) <= crc_reg(2);
-- test_crc(2) <= crc_reg(4);
-- test_crc(3) <= crc_reg(8);
-- end if;
-- end if;
-- end process;
p_mii_din : process(rxclk, reset) -- MII->ETH-RX ÊäÈëÊý¾Ý»º´æ
begin
if reset = '1' then
rxdv_buf <= '0';
rxd_buf <= (others=>'0');
elsif rising_edge(rxclk) then
-- if falling_edge(rxclk) then
rxdv_buf <= rxdv;
rxd_buf <= rxd;
end if;
end process;
-- rxclk_temp <= not rxclk;
-- u_din_sync : fifo_async
-- generic map(
-- DEPTH => 4,
-- AWIDTH => 2,
-- DWIDTH => 9,
-- RAM_TYPE => "DIS_RAM")
-- port map(
-- reset => reset,
-- clr => '0',
-- clka => rxclk,
---- clka => rxclk_temp,
-- wea => '1',
-- dia => d_ext,
-- clkb => clk,
-- rdb => rd_ena,
-- dob => d_int,
-- empty => empty,
-- full => open,
-- dn => open
-- );
--
-- d_ext <= rxdv_buf & rxd_buf;
-- rxdv_int <= d_int(8);
-- rxd_int <= d_int(7 downto 0);
-- rd_ena <= not empty;
--
-- p_ce : process(clk)
-- begin
-- if rising_edge(clk) then
-- ce <= rd_ena;
-- end if;
-- end process;
------------------------------------------------------------------------------
-- p_state_machine : process(clk, reset)
-- begin
-- if reset = '1' then
-- rx_state <= (others => '0');
-- rx_state_d1 <= (others => '0');
-- elsif rising_edge(clk) then
-- if ce = '1' then
-- case rx_state is
-- when "00" =>
-- if rxdv_int = '1' and rxd_int = "01010101" then
-- rx_state <= "01";
-- else
-- rx_state <= "00";
-- end if;
-- when "01" =>
-- if rxdv_int = '1' then
-- if rxd_int = "11010101" then
-- rx_state <= "10";
-- elsif rxd_int = "01010101" then
-- rx_state <= "01";
-- else
-- rx_state <= "00";
-- end if;
-- else
-- rx_state <= "00";
-- end if;
-- when "10" =>
-- if rxdv_int = '1' then
-- rx_state <= "11";
-- end if;
-- when "11" =>
-- if rxdv_int = '0' then
-- rx_state <= "00";
-- end if;
-- when others =>
-- NULL;
-- end case;
-- end if;
-- rx_state_d1 <= rx_state;
-- end if;
-- end process;
p_state_machine : process(rxclk, reset)
begin
if reset = '1' then
rx_state <= (others => '0');
rx_state_d1 <= (others => '0');
elsif rising_edge(rxclk) then
-- if ce = '1' then
case rx_state is
when "00" =>
if rxdv_buf = '1' and rxd_buf = "01010101" then
rx_state <= "01";
else
rx_state <= "00";
end if;
when "01" =>
if rxdv_buf = '1' then
if rxd_buf = "11010101" then
rx_state <= "10";
elsif rxd_buf = "01010101" then
rx_state <= "01";
else
rx_state <= "00";
end if;
else
rx_state <= "00";
end if;
when "10" =>
if rxdv_buf = '1' then
rx_state <= "11";
end if;
when "11" =>
if rxdv_buf = '0' then
rx_state <= "00";
end if;
when others =>
NULL;
end case;
-- end if;
rx_state_d1 <= rx_state;
end if;
end process;
p_byte_cnt : process(rxclk, reset) -- byte count
begin
if reset = '1' then
byte_cnt <= (others => '0');
elsif rising_edge(rxclk) then
-- if ce = '1' then
if rx_state = "00" then
byte_cnt <= (others => '0');
elsif rx_state = "11" then
byte_cnt <= byte_cnt + 1;
end if;
-- end if;
end if;
end process;
p_length : process(rxclk, reset)
begin
if reset = '1' then
length <= (others => '0');
elsif rising_edge(rxclk) then
-- if ce = '1' then
if rx_state = "11" and rxdv_buf = '0' then
length <= "0000" & byte_cnt - 3; -- Êý¾Ý³¤¶È£¬³ýµô4Bytes CRCУÑé
end if;
-- end if;
end if;
end process;
------------------------------------------------------------------------------
-- u_crc_rom : CRCRom
-- port map(
-- addr => crcrom_addr,
-- dout => crcrom_dout
-- );
--
-- crcrom_addr <= crc_reg(31 downto 28);
--
-- p_calc_crc : process(clk, reset)
-- begin
-- if reset = '1' then
-- crc_din <= (others => '0');
-- crc_reg <= (others => '0');
-- elsif rising_edge(clk) then
-- if ce = '1' then
-- if nibble_cnt < 7 then
-- crc_din <= not (rxd_int(0) & rxd_int(1) & rxd_int(2) & rxd_int(3));
-- else
-- crc_din <= rxd_int(0) & rxd_int(1) & rxd_int(2) & rxd_int(3);
-- end if;
--
-- if rx_state = "10" then
-- crc_reg <= (others => '0');
-- elsif rx_state = "11" then
-- crc_reg <= (crc_reg(27 downto 0) & crc_din) xor crcrom_dout;
-- end if;
-- end if;
-- end if;
-- end process;
u_crc_rom : CRC8_BlkRom
port map(
clk => rxclk,
addr => crcrom_addr,
dout => crcrom_dout
);
crcrom_addr <= crc_reg(31 downto 24);
crc_reg <= (others=>'0') when rx_state_d1 = "10" else
crc_reg_d1 xor crcrom_dout when rx_state_d1 = "11" else
crc_reg_d1;
p_calc_crc : process(rxclk, reset)
begin
if reset = '1' then
crc_din <= (others => '0');
crc_reg_d1 <= (others => '0');
elsif rising_edge(rxclk) then
-- if ce = '1' then
if byte_cnt < 3 then
crc_din <= not (rxd_buf(0) & rxd_buf(1) & rxd_buf(2) & rxd_buf(3) & rxd_buf(4) & rxd_buf(5) & rxd_buf(6) & rxd_buf(7));
else
crc_din <= rxd_buf(0) & rxd_buf(1) & rxd_buf(2) & rxd_buf(3) & rxd_buf(4) & rxd_buf(5) & rxd_buf(6) & rxd_buf(7);
end if;
if rx_state = "10" then
crc_reg_d1 <= (others => '0');
elsif rx_state = "11" then
crc_reg_d1 <= (crc_reg(23 downto 0) & crc_din);
end if;
-- else
-- crc_reg_d1 <= crc_reg;
-- end if;
end if;
end process;
p_crc_flag : process(rxclk, reset)
begin
if reset = '1' then
crc_flag <= '0';
g_Test_EthRec_CRCFlag <= '0';
elsif rising_edge(rxclk) then
-- if ce = '1' then
if rx_state = "00" and crc_reg = X"FFFFFFFF" then
crc_flag <= '1';
elsif rx_state = "10" then
crc_flag <= '0';
end if;
-- end if;
g_Test_EthRec_CRCFlag <= crc_flag;
end if;
end process;
--------------------------------------------------------------------------------
p_s2p : process(rxclk, reset)
begin
if reset = '1' then
rxd_buf_d1 <= (others => '0');
rxd_buf_d2 <= (others => '0');
rxd_buf_d3 <= (others => '0');
rxd_buf_d4 <= (others => '0');
elsif rising_edge(rxclk) then
-- if ce = '1' then
rxd_buf_d1 <= rxd_buf;
rxd_buf_d2 <= rxd_buf_d1;
rxd_buf_d3 <= rxd_buf_d2;
rxd_buf_d4 <= rxd_buf_d3;
-- end if;
end if;
end process;
-- dword_data_ext <= rxd_buf_d4 & rxd_buf_d3 & rxd_buf_d2 & rxd_buf_d1;
dword_data_ext <= rxd_buf_d1 & rxd_buf_d2 & rxd_buf_d3 & rxd_buf_d4;
-----------------------------------------------------------------------------
RxFIFO_clr <= '1' when rx_state = "10" else '0';
RxFIFO_wea <= '1' when rx_state = "11" and byte_cnt(1 downto 0) = "11" else '0';
RxFIFO_dia <= dword_data_ext;
u_din_sync : fifo_async_almost_full
generic map(
DEPTH => 2**(HEAD_AWIDTH-1),
AWIDTH => HEAD_AWIDTH-1,
DWIDTH => 32,
RAM_TYPE => "DIS_RAM")
port map(
reset => reset,
clr => RxFIFO_clr,
clka => rxclk,
-- clka => rxclk_temp,
wea => RxFIFO_wea,
dia => RxFIFO_dia,
clkb => clk,
rdb => RxFIFO_rdb,
dob => RxFIFO_dob,
empty => RxFIFO_empty,
almost_full => open,
full => open,
dn => open
);
RxFIFO_not_empty <= not RxFIFO_empty;
RxFIFO_rdb <= not RxFIFO_empty when (rx_state_int = "01" and byte_cnt_int(1 downto 0) = "00") or rx_state_int = "10" else '0';
dword_data_int <= RxFIFO_dob;
p_ce : process(clk, reset)
begin
if reset = '1' then
ce <= '0';
elsif rising_edge(clk) then
ce <= RxFIFO_rdb;
end if;
end process;
ASYNCWRITE_RxFIFO_clr_int : ASYNCWRITE
port map(
reset => reset,
async_clk => rxclk,
sync_clk => clk,
async_wren => RxFIFO_clr,
trigger => RxFIFO_not_empty,
sync_wren => RxFIFO_clr_int,
over => open,
flag => open
);
p_rx_state_int : process( clk, reset )
begin
if reset = '1' then
rx_state_int <= "00";
rx_state_int_d1 <= "00";
elsif rising_edge( clk ) then
if RxFIFO_clr_int = '1' then
rx_state_int <= "01";
else
case rx_state_int is
when "01" => -- head_ena
if byte_cnt_int = HEAD_LENGTH-1 then
rx_state_int <= "10";
elsif rx_end_int = '1' then
rx_state_int <= "11";
else
rx_state_int <= "01";
end if;
when "10" => -- data_ena
if rx_end_int = '1' then
rx_state_int <= "11";
end if;
when "11" => -- info_ena
if info_cnt = INFO_LENGTH-1 then
rx_state_int <= "00";
end if;
when others =>
NULL;
end case;
end if;
rx_state_int_d1 <= rx_state_int;
end if;
end process;
rx_end_ext <= '1' when rx_state = "11" and rxdv_buf = '0' else '0';
ASYNCWRITE_rx_end_int : ASYNCWRITE
port map(
reset => reset,
async_clk => rxclk,
sync_clk => clk,
async_wren => rx_end_ext,
trigger => RxFIFO_empty,
sync_wren => rx_end_int,
over => open,
flag => open
);
p_dword_cnt : process(clk, reset, RxFIFO_clr) -- byte count
begin
if reset = '1' then
byte_cnt_int <= (others => '0');
byte_cnt_int_d1 <= (others => '0');
elsif rising_edge(clk) then
if rx_state_int = "00" then
byte_cnt_int <= (others=>'0');
elsif rx_state_int = "01" then
byte_cnt_int <= byte_cnt_int + 1;
elsif rx_state_int = "10" then
byte_cnt_int <= byte_cnt_int + 4;
end if;
byte_cnt_int_d1 <= byte_cnt_int;
end if;
end process;
------------------------------------------------------------------------------
-- p_recvtime : process(clk, reset)
-- begin
-- if reset = '1' then
-- recvtime(31 downto 0) <= (others => '0');
-- recvtime_valid <= '0';
-- elsif rising_edge(clk) then
-- if ce = '1' then
-- case dword_cnt is
-- when X"00e" => recvtime(31 downto 24) <= rxd_int;
-- when X"00f" => recvtime(23 downto 16) <= rxd_int;
-- when X"010" => recvtime(15 downto 8) <= rxd_int;
-- when X"011" => recvtime(7 downto 0) <= rxd_int;
-- when X"012" => recvtime_valid <= '1';
-- when others => recvtime_valid <= '0';
-- end case;
-- end if;
-- end if;
-- end process;
p_p2s : process( clk, reset )
begin
if reset = '1' then
dword_data_buf <= (others=>'0');
elsif rising_edge( clk ) then
if byte_cnt_int_d1(1 downto 0) = "00" then
-- dword_data_buf <= dword_data_int(23 downto 0);
dword_data_buf <= dword_data_int(31 downto 8);
else
-- dword_data_buf <= dword_data_buf(15 downto 0) & x"00";
dword_data_buf <= x"00" & dword_data_buf(23 downto 8);
end if;
end if;
end process;
-- byte_data_int <= dword_data_int(31 downto 24) when byte_cnt_int_d1(1 downto 0) = "00" else
-- dword_data_buf(23 downto 16);
byte_data_int <= dword_data_int(7 downto 0) when byte_cnt_int_d1(1 downto 0) = "00" else
dword_data_buf(7 downto 0);
p_recvtime : process(clk, reset)
begin
if reset = '1' then
recvtime(31 downto 0) <= (others => '0');
recvtime_valid <= '0';
elsif rising_edge(clk) then
-- if ce = '1' then
case byte_cnt_int_d1 is
when X"00e" => recvtime(31 downto 24) <= byte_data_int;
when X"00f" => recvtime(23 downto 16) <= byte_data_int;
when X"010" => recvtime(15 downto 8) <= byte_data_int;
when X"011" => recvtime(7 downto 0) <= byte_data_int;
when X"012" => recvtime_valid <= '1';
when others => recvtime_valid <= '0';
end case;
-- end if;
end if;
end process;
p_localtime_locked : process(clk, reset)
begin
if reset = '1' then
localtime_locked_reg <= '0';
elsif rising_edge(clk) then
-- if ce = '1' and rx_state = "10" and localtime_locked_reg = '0' then
if RxFIFO_clr_int = '1' and localtime_locked_reg = '0' then
localtime_locked_reg <= '1';
elsif localtime_locked_reg = '1' then
localtime_locked_reg <= '0';
end if;
end if;
end process;
localtime_locked <= localtime_locked_reg;
------------------------------------------------------------------------------
p_buff_wren : process(clk, reset)
begin
if reset = '1' then
buff_wren_buf <= '0';
elsif rising_edge(clk) then
-- if ce = '1' then
-- if byte_cnt(1 downto 0) = "11" and rx_state = "11" then -- 4byteдʹÄÜ£¿
-- buff_wren_buf <= '1';
-- else
-- buff_wren_buf <= '0';
-- end if;
-- end if;
-- if ce = '1' and (rx_state_int = "01" or rx_state_int = "10") then
-- buff_wren_buf <= '1';
-- else
-- buff_wren_buf <= '0';
-- end if;
buff_wren_buf <= ce;
end if;
end process;
p_buff_waddr : process(clk, reset)
begin
if reset = '1' then
buff_waddr_buf <= (others => '0');
elsif rising_edge(clk) then
-- if ce = '1' then
if buff_wren_buf = '1' then
buff_waddr_buf <= buff_waddr_buf + 1; -- buffer address ++
end if;
-- end if;
end if;
end process;
p_buff_wdata : process(clk, reset)
begin
if reset = '1' then
buff_wdata <= (others => '0');
elsif rising_edge(clk) then
if ce = '1' then
buff_wdata <= dword_data_int;
end if;
end if;
end process;
buff_wren <= buff_wren_buf;
buff_waddr <= buff_waddr_buf;
------------------------------------------------------------------------------
p_start_addr : process(clk, reset)
begin
if reset = '1' then
start_addr <= (others => '0');
elsif rising_edge(clk) then
-- if ce = '1' then
-- if rx_state = "10" then
if RxFIFO_clr_int = '1' then
start_addr <= EXT(buff_waddr_buf, 16); -- °üÀ¨CRCµØÖ·
-- end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
p_info_cnt : process(clk, reset)
begin
if reset = '1' then
-- info_ena <= '0';
info_cnt <= 0;
elsif rising_edge(clk) then
-- if ce = '1' then
-- if rx_state = "11" and rxdv_int = '0' then
-- if rx_end_int = '1' then
-- info_ena <= '1';
-- elsif info_cnt = INFO_LENGTH - 1 then
-- info_ena <= '0';
-- end if;
-- if info_ena = '0' then
-- info_cnt <= 0;
-- else
-- info_cnt <= info_cnt + 1;
-- end if;
-- end if;
if rx_state_int = "11" then
info_cnt <= info_cnt + 1;
else
info_cnt <= 0;
end if;
end if;
end process;
info_ena <= '1' when rx_state_int = "11" else '0';
p_head_wren : process(clk, reset)
begin
if reset = '1' then
head_wren_buf <= '0';
elsif rising_edge(clk) then
-- if ce = '1' then
-- if (rx_state = "11" and rxdv_int = '1' and byte_cnt < HEAD_LENGTH) or info_ena = '1' then -- Ç°32¸ö×Ö½Úдʱ£¬ÒÔ¼°×îºóдµØÖ·Ó볤¶È4×Ö½ÚʱΪ1
if rx_state_int_d1 = "01" or rx_state_int = "11" then
head_wren_buf <= '1';
else
head_wren_buf <= '0';
end if;
-- end if;
end if;
end process;
p_head_waddr : process(clk, reset)
begin
if reset = '1' then
head_waddr_buf <= (others => '0');
elsif rising_edge(clk) then
-- if ce = '1' then
--if rx_state = "10" then
if RxFIFO_clr_int = '1' then
head_waddr_buf <= conv_std_logic_vector(INFO_LENGTH, HEAD_AWIDTH);
--elsif rx_state = "11" and rxdv_int = '0' then
elsif rx_end_int = '1' then
head_waddr_buf <= conv_std_logic_vector(0, HEAD_AWIDTH);
elsif head_wren_buf = '1' then
head_waddr_buf <= head_waddr_buf + 1;
end if;
-- end if;
end if;
end process;
p_head_wdata : process(clk, reset)
begin
if reset = '1' then
head_wdata <= (others => '0');
elsif rising_edge(clk) then
-- if ce = '1' then
if info_ena = '1' then
case info_cnt is
when 0 => head_wdata <= length(7 downto 0);
when 1 => head_wdata <= length(15 downto 8);
when 2 => head_wdata <= start_addr(5 downto 0)&"00";
when 3 => head_wdata <= start_addr(13 downto 6);
when others => null;
end case;
else
head_wdata <= byte_data_int;
end if;
-- end if;
end if;
end process;
head_wren <= head_wren_buf;
head_waddr <= head_waddr_buf;
p_head_wr_block : process(clk, reset)
begin
if reset = '1' then
head_wr_block_buf <= '0';
elsif rising_edge(clk) then
-- if ce = '1' then
if info_cnt = INFO_LENGTH and crc_flag = '1' then -- crcУÑéÕýÈ·
head_wr_block_buf <= '1';
else
head_wr_block_buf <= '0';
end if;
-- end if;
end if;
end process;
head_wr_block <= head_wr_block_buf; -- crcУÑéÖ¸Õë
end arch_ethrx_input;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc82.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x03p01n01i00082ent IS
END c04s03b01x03p01n01i00082ent;
ARCHITECTURE c04s03b01x03p01n01i00082arch OF c04s03b01x03p01n01i00082ent IS
--
--
-- Declaration of composite types
-- - array types and subtypes
--
TYPE ut_chary IS ARRAY (CHARACTER RANGE <>) OF INTEGER; -- unconstrained array type
TYPE ct_word IS ARRAY (0 TO 15) OF BIT; -- constrained array type
SUBTYPE ust_subchary IS ut_chary; -- unconstrained array subtype
SUBTYPE cst_str10 IS STRING ( 1 TO 10 ); -- constrained array subtype
SUBTYPE cst_digit IS ut_chary ('0' TO '9'); -- constrained array subtype
--
-- Declaration of composite types
-- - records types and subtypes
--
TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
TYPE rt_date IS
RECORD
day : INTEGER RANGE 0 TO 31;
month : month_name;
year : INTEGER RANGE 0 TO 4000;
END RECORD;
--
SUBTYPE rst_date IS rt_date;
BEGIN
TESTING: PROCESS
--
-- VARIABLE declarations
--
VARIABLE STRING_con_0 : STRING (1 TO 7);
VARIABLE STRING_con_1 : STRING (1 TO 7) := "sailing";
VARIABLE STRING_con_2 : STRING (1 TO 7) := ( 's', 'a', 'i', 'l', 'i', 'n', 'g');
VARIABLE BIT_VECTOR_con_0 : BIT_VECTOR (0 TO 7);
VARIABLE BIT_VECTOR_con_1 : BIT_VECTOR (0 TO 7) := B"10101110";
VARIABLE BIT_VECTOR_con_2 : BIT_VECTOR (0 TO 7) := ( '1', '0', '1', '0', '1', '1', '1', '0');
VARIABLE ut_chary_con_0 : ut_chary (NUL TO ENQ);
VARIABLE ut_chary_con_1 : ut_chary (NUL TO ENQ) := ( 1, 2, 3, 9, 8, 7);
VARIABLE ct_word_con_0 : ct_word;
VARIABLE ct_word_con_1 : ct_word := ( '1', '1', '1', '1', '1', '1', '1', '1',
'1', '1', '1', '1', '1', '1', '1', '1');
VARIABLE cst_str10_con_0 : cst_str10;
VARIABLE cst_str10_con_1 : cst_str10 := "abcdefghij";
VARIABLE cst_str10_con_2 : cst_str10 := ( 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j');
VARIABLE cst_digit_con_0 : cst_digit;
VARIABLE cst_digit_con_1 : cst_digit := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
VARIABLE rt_date_con_0 : rt_date;
VARIABLE rt_date_con_1 : rt_date := (1, Jan, 1989);
VARIABLE rst_date_con_0 : rst_date;
VARIABLE rst_date_con_1 : rst_date := (1, Apr, 2000);
----------------------------------------------------------------------------------------------------------
BEGIN
ASSERT STRING_con_0(1) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(2) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(3) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(4) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(5) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(6) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(7) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(1) = 's' REPORT "STRING_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(2) = 'a' REPORT "STRING_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(3) = 'i' REPORT "STRING_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(4) = 'l' REPORT "STRING_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(5) = 'i' REPORT "STRING_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(6) = 'n' REPORT "STRING_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(7) = 'g' REPORT "STRING_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(1) = 's' REPORT "STRING_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(2) = 'a' REPORT "STRING_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(3) = 'i' REPORT "STRING_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(4) = 'l' REPORT "STRING_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(5) = 'i' REPORT "STRING_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(6) = 'n' REPORT "STRING_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(7) = 'g' REPORT "STRING_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(0) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(1) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(2) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(3) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(4) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(5) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(6) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(7) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(0) = '1' REPORT "BIT_VECTOR_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(1) = '0' REPORT "BIT_VECTOR_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(2) = '1' REPORT "BIT_VECTOR_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(3) = '0' REPORT "BIT_VECTOR_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(4) = '1' REPORT "BIT_VECTOR_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(5) = '1' REPORT "BIT_VECTOR_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(6) = '1' REPORT "BIT_VECTOR_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(7) = '0' REPORT "BIT_VECTOR_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(0) = '1' REPORT "BIT_VECTOR_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(1) = '0' REPORT "BIT_VECTOR_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(2) = '1' REPORT "BIT_VECTOR_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(3) = '0' REPORT "BIT_VECTOR_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(4) = '1' REPORT "BIT_VECTOR_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(5) = '1' REPORT "BIT_VECTOR_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(6) = '1' REPORT "BIT_VECTOR_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(7) = '0' REPORT "BIT_VECTOR_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(NUL) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(SOH) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(STX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(ETX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(EOT) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(ENQ) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(NUL) = 1 REPORT "ut_chary_con_1('a') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(SOH) = 2 REPORT "ut_chary_con_1('b') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(STX) = 3 REPORT "ut_chary_con_1('c') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(ETX) = 9 REPORT "ut_chary_con_1('d') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(EOT) = 8 REPORT "ut_chary_con_1('e') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(ENQ) = 7 REPORT "ut_chary_con_1('f') not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(0) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(1) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(2) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(3) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(4) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(5) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(6) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(7) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(8) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(9) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(10) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(11) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(12) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(13) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(14) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(15) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(0) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(1) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(2) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(3) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(4) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(5) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(6) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(7) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(8) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(9) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(10) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(11) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(12) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(13) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(14) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(15) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(1) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(2) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(3) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(4) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(5) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(6) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(7) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(8) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(9) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(10) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(1) = 'a' REPORT "cst_str10_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(2) = 'b' REPORT "cst_str10_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(3) = 'c' REPORT "cst_str10_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(4) = 'd' REPORT "cst_str10_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(5) = 'e' REPORT "cst_str10_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(6) = 'f' REPORT "cst_str10_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(7) = 'g' REPORT "cst_str10_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(8) = 'h' REPORT "cst_str10_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(9) = 'i' REPORT "cst_str10_con_1(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(10)= 'j' REPORT "cst_str10_con_1(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(1) = 'a' REPORT "cst_str10_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(2) = 'b' REPORT "cst_str10_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(3) = 'c' REPORT "cst_str10_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(4) = 'd' REPORT "cst_str10_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(5) = 'e' REPORT "cst_str10_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(6) = 'f' REPORT "cst_str10_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(7) = 'g' REPORT "cst_str10_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(8) = 'h' REPORT "cst_str10_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(9) = 'i' REPORT "cst_str10_con_2(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(10)= 'j' REPORT "cst_str10_con_2(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('0') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('1') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('2') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('3') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('4') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('5') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('6') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('7') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('8') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('9') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('0') = 0 REPORT "cst_digit_con_1('0') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('1') = 1 REPORT "cst_digit_con_1('1') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('2') = 2 REPORT "cst_digit_con_1('2') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('3') = 3 REPORT "cst_digit_con_1('3') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('4') = 4 REPORT "cst_digit_con_1('4') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('5') = 5 REPORT "cst_digit_con_1('5') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('6') = 6 REPORT "cst_digit_con_1('6') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('7') = 7 REPORT "cst_digit_con_1('7') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('8') = 8 REPORT "cst_digit_con_1('8') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('9') = 9 REPORT "cst_digit_con_1('9') not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.day = 0 REPORT " rt_date_con_0.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.month = Jan REPORT " rt_date_con_0.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.year = 0 REPORT " rt_date_con_0.year not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.day = 1 REPORT " rt_date_con_1.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.month = Jan REPORT " rt_date_con_1.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.year = 1989 REPORT " rt_date_con_1.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.day = 0 REPORT "rst_date_con_0.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.month = Jan REPORT "rst_date_con_0.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.year = 0 REPORT "rst_date_con_0.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.day = 1 REPORT "rst_date_con_1.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.month = Apr REPORT "rst_date_con_1.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.year = 2000 REPORT "rst_date_con_1.year not properly intialized" SEVERITY FAILURE;
--------------------------------------------------------------------------------------------------------------
assert NOT( STRING_con_0(1) = NUL and
STRING_con_0(2) = NUL and
STRING_con_0(3) = NUL and
STRING_con_0(4) = NUL and
STRING_con_0(5) = NUL and
STRING_con_0(6) = NUL and
STRING_con_0(7) = NUL and
STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_0(0) = '0' and
BIT_VECTOR_con_0(1) = '0' and
BIT_VECTOR_con_0(2) = '0' and
BIT_VECTOR_con_0(3) = '0' and
BIT_VECTOR_con_0(4) = '0' and
BIT_VECTOR_con_0(5) = '0' and
BIT_VECTOR_con_0(6) = '0' and
BIT_VECTOR_con_0(7) = '0' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con_0(NUL) = INTEGER'LEFT and
ut_chary_con_0(SOH) = INTEGER'LEFT and
ut_chary_con_0(STX) = INTEGER'LEFT and
ut_chary_con_0(ETX) = INTEGER'LEFT and
ut_chary_con_0(EOT) = INTEGER'LEFT and
ut_chary_con_0(ENQ) = INTEGER'LEFT and
ut_chary_con_1(NUL) = 1 and
ut_chary_con_1(SOH) = 2 and
ut_chary_con_1(STX) = 3 and
ut_chary_con_1(ETX) = 9 and
ut_chary_con_1(EOT) = 8 and
ut_chary_con_1(ENQ) = 7 and
ct_word_con_0(0) = '0' and
ct_word_con_0(1) = '0' and
ct_word_con_0(2) = '0' and
ct_word_con_0(3) = '0' and
ct_word_con_0(4) = '0' and
ct_word_con_0(5) = '0' and
ct_word_con_0(6) = '0' and
ct_word_con_0(7) = '0' and
ct_word_con_0(8) = '0' and
ct_word_con_0(9) = '0' and
ct_word_con_0(10) = '0' and
ct_word_con_0(11) = '0' and
ct_word_con_0(12) = '0' and
ct_word_con_0(13) = '0' and
ct_word_con_0(14) = '0' and
ct_word_con_0(15) = '0' and
ct_word_con_1(0) = '1' and
ct_word_con_1(1) = '1' and
ct_word_con_1(2) = '1' and
ct_word_con_1(3) = '1' and
ct_word_con_1(4) = '1' and
ct_word_con_1(5) = '1' and
ct_word_con_1(6) = '1' and
ct_word_con_1(7) = '1' and
ct_word_con_1(8) = '1' and
ct_word_con_1(9) = '1' and
ct_word_con_1(10) = '1' and
ct_word_con_1(11) = '1' and
ct_word_con_1(12) = '1' and
ct_word_con_1(13) = '1' and
ct_word_con_1(14) = '1' and
ct_word_con_1(15) = '1' and
cst_str10_con_0(1) = NUL and
cst_str10_con_0(2) = NUL and
cst_str10_con_0(3) = NUL and
cst_str10_con_0(4) = NUL and
cst_str10_con_0(5) = NUL and
cst_str10_con_0(6) = NUL and
cst_str10_con_0(7) = NUL and
cst_str10_con_0(8) = NUL and
cst_str10_con_0(9) = NUL and
cst_str10_con_0(10) = NUL and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con_0('0') = INTEGER'LEFT and
cst_digit_con_0('1') = INTEGER'LEFT and
cst_digit_con_0('2') = INTEGER'LEFT and
cst_digit_con_0('3') = INTEGER'LEFT and
cst_digit_con_0('4') = INTEGER'LEFT and
cst_digit_con_0('5') = INTEGER'LEFT and
cst_digit_con_0('6') = INTEGER'LEFT and
cst_digit_con_0('7') = INTEGER'LEFT and
cst_digit_con_0('8') = INTEGER'LEFT and
cst_digit_con_0('9') = INTEGER'LEFT and
cst_digit_con_1('0') = 0 and
cst_digit_con_1('1') = 1 and
cst_digit_con_1('2') = 2 and
cst_digit_con_1('3') = 3 and
cst_digit_con_1('4') = 4 and
cst_digit_con_1('5') = 5 and
cst_digit_con_1('6') = 6 and
cst_digit_con_1('7') = 7 and
cst_digit_con_1('8') = 8 and
cst_digit_con_1('9') = 9 and
rt_date_con_0.day = 0 and
rt_date_con_0.month = Jan and
rt_date_con_0.year = 0 and
rt_date_con_1.day = 1 and
rt_date_con_1.month = Jan and
rt_date_con_1.year = 1989 and
rst_date_con_0.day = 0 and
rst_date_con_0.month = Jan and
rst_date_con_0.year = 0 and
rst_date_con_1.day = 1 and
rst_date_con_1.month = Apr and
rst_date_con_1.year = 2000 )
report "***PASSED TEST: /src/ch04/sc03/sb01/ss03/p001/s010101.vhd"
severity NOTE;
assert ( STRING_con_0(1) = NUL and
STRING_con_0(2) = NUL and
STRING_con_0(3) = NUL and
STRING_con_0(4) = NUL and
STRING_con_0(5) = NUL and
STRING_con_0(6) = NUL and
STRING_con_0(7) = NUL and
STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_0(0) = '0' and
BIT_VECTOR_con_0(1) = '0' and
BIT_VECTOR_con_0(2) = '0' and
BIT_VECTOR_con_0(3) = '0' and
BIT_VECTOR_con_0(4) = '0' and
BIT_VECTOR_con_0(5) = '0' and
BIT_VECTOR_con_0(6) = '0' and
BIT_VECTOR_con_0(7) = '0' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con_0(NUL) = INTEGER'LEFT and
ut_chary_con_0(SOH) = INTEGER'LEFT and
ut_chary_con_0(STX) = INTEGER'LEFT and
ut_chary_con_0(ETX) = INTEGER'LEFT and
ut_chary_con_0(EOT) = INTEGER'LEFT and
ut_chary_con_0(ENQ) = INTEGER'LEFT and
ut_chary_con_1(NUL) = 1 and
ut_chary_con_1(SOH) = 2 and
ut_chary_con_1(STX) = 3 and
ut_chary_con_1(ETX) = 9 and
ut_chary_con_1(EOT) = 8 and
ut_chary_con_1(ENQ) = 7 and
ct_word_con_0(0) = '0' and
ct_word_con_0(1) = '0' and
ct_word_con_0(2) = '0' and
ct_word_con_0(3) = '0' and
ct_word_con_0(4) = '0' and
ct_word_con_0(5) = '0' and
ct_word_con_0(6) = '0' and
ct_word_con_0(7) = '0' and
ct_word_con_0(8) = '0' and
ct_word_con_0(9) = '0' and
ct_word_con_0(10) = '0' and
ct_word_con_0(11) = '0' and
ct_word_con_0(12) = '0' and
ct_word_con_0(13) = '0' and
ct_word_con_0(14) = '0' and
ct_word_con_0(15) = '0' and
ct_word_con_1(0) = '1' and
ct_word_con_1(1) = '1' and
ct_word_con_1(2) = '1' and
ct_word_con_1(3) = '1' and
ct_word_con_1(4) = '1' and
ct_word_con_1(5) = '1' and
ct_word_con_1(6) = '1' and
ct_word_con_1(7) = '1' and
ct_word_con_1(8) = '1' and
ct_word_con_1(9) = '1' and
ct_word_con_1(10) = '1' and
ct_word_con_1(11) = '1' and
ct_word_con_1(12) = '1' and
ct_word_con_1(13) = '1' and
ct_word_con_1(14) = '1' and
ct_word_con_1(15) = '1' and
cst_str10_con_0(1) = NUL and
cst_str10_con_0(2) = NUL and
cst_str10_con_0(3) = NUL and
cst_str10_con_0(4) = NUL and
cst_str10_con_0(5) = NUL and
cst_str10_con_0(6) = NUL and
cst_str10_con_0(7) = NUL and
cst_str10_con_0(8) = NUL and
cst_str10_con_0(9) = NUL and
cst_str10_con_0(10) = NUL and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con_0('0') = INTEGER'LEFT and
cst_digit_con_0('1') = INTEGER'LEFT and
cst_digit_con_0('2') = INTEGER'LEFT and
cst_digit_con_0('3') = INTEGER'LEFT and
cst_digit_con_0('4') = INTEGER'LEFT and
cst_digit_con_0('5') = INTEGER'LEFT and
cst_digit_con_0('6') = INTEGER'LEFT and
cst_digit_con_0('7') = INTEGER'LEFT and
cst_digit_con_0('8') = INTEGER'LEFT and
cst_digit_con_0('9') = INTEGER'LEFT and
cst_digit_con_1('0') = 0 and
cst_digit_con_1('1') = 1 and
cst_digit_con_1('2') = 2 and
cst_digit_con_1('3') = 3 and
cst_digit_con_1('4') = 4 and
cst_digit_con_1('5') = 5 and
cst_digit_con_1('6') = 6 and
cst_digit_con_1('7') = 7 and
cst_digit_con_1('8') = 8 and
cst_digit_con_1('9') = 9 and
rt_date_con_0.day = 0 and
rt_date_con_0.month = Jan and
rt_date_con_0.year = 0 and
rt_date_con_1.day = 1 and
rt_date_con_1.month = Jan and
rt_date_con_1.year = 1989 and
rst_date_con_0.day = 0 and
rst_date_con_0.month = Jan and
rst_date_con_0.year = 0 and
rst_date_con_1.day = 1 and
rst_date_con_1.month = Apr and
rst_date_con_1.year = 2000 )
report "***FAILED TEST: c04s03b01x03p01n01i00082 - A variable declaration declares a variable of the specified type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x03p01n01i00082arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc82.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x03p01n01i00082ent IS
END c04s03b01x03p01n01i00082ent;
ARCHITECTURE c04s03b01x03p01n01i00082arch OF c04s03b01x03p01n01i00082ent IS
--
--
-- Declaration of composite types
-- - array types and subtypes
--
TYPE ut_chary IS ARRAY (CHARACTER RANGE <>) OF INTEGER; -- unconstrained array type
TYPE ct_word IS ARRAY (0 TO 15) OF BIT; -- constrained array type
SUBTYPE ust_subchary IS ut_chary; -- unconstrained array subtype
SUBTYPE cst_str10 IS STRING ( 1 TO 10 ); -- constrained array subtype
SUBTYPE cst_digit IS ut_chary ('0' TO '9'); -- constrained array subtype
--
-- Declaration of composite types
-- - records types and subtypes
--
TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
TYPE rt_date IS
RECORD
day : INTEGER RANGE 0 TO 31;
month : month_name;
year : INTEGER RANGE 0 TO 4000;
END RECORD;
--
SUBTYPE rst_date IS rt_date;
BEGIN
TESTING: PROCESS
--
-- VARIABLE declarations
--
VARIABLE STRING_con_0 : STRING (1 TO 7);
VARIABLE STRING_con_1 : STRING (1 TO 7) := "sailing";
VARIABLE STRING_con_2 : STRING (1 TO 7) := ( 's', 'a', 'i', 'l', 'i', 'n', 'g');
VARIABLE BIT_VECTOR_con_0 : BIT_VECTOR (0 TO 7);
VARIABLE BIT_VECTOR_con_1 : BIT_VECTOR (0 TO 7) := B"10101110";
VARIABLE BIT_VECTOR_con_2 : BIT_VECTOR (0 TO 7) := ( '1', '0', '1', '0', '1', '1', '1', '0');
VARIABLE ut_chary_con_0 : ut_chary (NUL TO ENQ);
VARIABLE ut_chary_con_1 : ut_chary (NUL TO ENQ) := ( 1, 2, 3, 9, 8, 7);
VARIABLE ct_word_con_0 : ct_word;
VARIABLE ct_word_con_1 : ct_word := ( '1', '1', '1', '1', '1', '1', '1', '1',
'1', '1', '1', '1', '1', '1', '1', '1');
VARIABLE cst_str10_con_0 : cst_str10;
VARIABLE cst_str10_con_1 : cst_str10 := "abcdefghij";
VARIABLE cst_str10_con_2 : cst_str10 := ( 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j');
VARIABLE cst_digit_con_0 : cst_digit;
VARIABLE cst_digit_con_1 : cst_digit := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
VARIABLE rt_date_con_0 : rt_date;
VARIABLE rt_date_con_1 : rt_date := (1, Jan, 1989);
VARIABLE rst_date_con_0 : rst_date;
VARIABLE rst_date_con_1 : rst_date := (1, Apr, 2000);
----------------------------------------------------------------------------------------------------------
BEGIN
ASSERT STRING_con_0(1) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(2) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(3) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(4) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(5) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(6) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(7) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(1) = 's' REPORT "STRING_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(2) = 'a' REPORT "STRING_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(3) = 'i' REPORT "STRING_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(4) = 'l' REPORT "STRING_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(5) = 'i' REPORT "STRING_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(6) = 'n' REPORT "STRING_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(7) = 'g' REPORT "STRING_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(1) = 's' REPORT "STRING_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(2) = 'a' REPORT "STRING_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(3) = 'i' REPORT "STRING_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(4) = 'l' REPORT "STRING_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(5) = 'i' REPORT "STRING_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(6) = 'n' REPORT "STRING_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(7) = 'g' REPORT "STRING_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(0) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(1) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(2) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(3) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(4) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(5) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(6) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(7) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(0) = '1' REPORT "BIT_VECTOR_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(1) = '0' REPORT "BIT_VECTOR_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(2) = '1' REPORT "BIT_VECTOR_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(3) = '0' REPORT "BIT_VECTOR_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(4) = '1' REPORT "BIT_VECTOR_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(5) = '1' REPORT "BIT_VECTOR_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(6) = '1' REPORT "BIT_VECTOR_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(7) = '0' REPORT "BIT_VECTOR_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(0) = '1' REPORT "BIT_VECTOR_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(1) = '0' REPORT "BIT_VECTOR_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(2) = '1' REPORT "BIT_VECTOR_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(3) = '0' REPORT "BIT_VECTOR_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(4) = '1' REPORT "BIT_VECTOR_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(5) = '1' REPORT "BIT_VECTOR_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(6) = '1' REPORT "BIT_VECTOR_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(7) = '0' REPORT "BIT_VECTOR_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(NUL) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(SOH) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(STX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(ETX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(EOT) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(ENQ) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(NUL) = 1 REPORT "ut_chary_con_1('a') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(SOH) = 2 REPORT "ut_chary_con_1('b') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(STX) = 3 REPORT "ut_chary_con_1('c') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(ETX) = 9 REPORT "ut_chary_con_1('d') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(EOT) = 8 REPORT "ut_chary_con_1('e') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(ENQ) = 7 REPORT "ut_chary_con_1('f') not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(0) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(1) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(2) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(3) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(4) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(5) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(6) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(7) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(8) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(9) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(10) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(11) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(12) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(13) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(14) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(15) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(0) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(1) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(2) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(3) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(4) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(5) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(6) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(7) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(8) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(9) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(10) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(11) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(12) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(13) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(14) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(15) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(1) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(2) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(3) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(4) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(5) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(6) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(7) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(8) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(9) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(10) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(1) = 'a' REPORT "cst_str10_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(2) = 'b' REPORT "cst_str10_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(3) = 'c' REPORT "cst_str10_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(4) = 'd' REPORT "cst_str10_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(5) = 'e' REPORT "cst_str10_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(6) = 'f' REPORT "cst_str10_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(7) = 'g' REPORT "cst_str10_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(8) = 'h' REPORT "cst_str10_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(9) = 'i' REPORT "cst_str10_con_1(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(10)= 'j' REPORT "cst_str10_con_1(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(1) = 'a' REPORT "cst_str10_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(2) = 'b' REPORT "cst_str10_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(3) = 'c' REPORT "cst_str10_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(4) = 'd' REPORT "cst_str10_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(5) = 'e' REPORT "cst_str10_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(6) = 'f' REPORT "cst_str10_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(7) = 'g' REPORT "cst_str10_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(8) = 'h' REPORT "cst_str10_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(9) = 'i' REPORT "cst_str10_con_2(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(10)= 'j' REPORT "cst_str10_con_2(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('0') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('1') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('2') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('3') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('4') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('5') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('6') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('7') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('8') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('9') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('0') = 0 REPORT "cst_digit_con_1('0') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('1') = 1 REPORT "cst_digit_con_1('1') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('2') = 2 REPORT "cst_digit_con_1('2') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('3') = 3 REPORT "cst_digit_con_1('3') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('4') = 4 REPORT "cst_digit_con_1('4') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('5') = 5 REPORT "cst_digit_con_1('5') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('6') = 6 REPORT "cst_digit_con_1('6') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('7') = 7 REPORT "cst_digit_con_1('7') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('8') = 8 REPORT "cst_digit_con_1('8') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('9') = 9 REPORT "cst_digit_con_1('9') not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.day = 0 REPORT " rt_date_con_0.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.month = Jan REPORT " rt_date_con_0.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.year = 0 REPORT " rt_date_con_0.year not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.day = 1 REPORT " rt_date_con_1.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.month = Jan REPORT " rt_date_con_1.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.year = 1989 REPORT " rt_date_con_1.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.day = 0 REPORT "rst_date_con_0.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.month = Jan REPORT "rst_date_con_0.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.year = 0 REPORT "rst_date_con_0.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.day = 1 REPORT "rst_date_con_1.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.month = Apr REPORT "rst_date_con_1.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.year = 2000 REPORT "rst_date_con_1.year not properly intialized" SEVERITY FAILURE;
--------------------------------------------------------------------------------------------------------------
assert NOT( STRING_con_0(1) = NUL and
STRING_con_0(2) = NUL and
STRING_con_0(3) = NUL and
STRING_con_0(4) = NUL and
STRING_con_0(5) = NUL and
STRING_con_0(6) = NUL and
STRING_con_0(7) = NUL and
STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_0(0) = '0' and
BIT_VECTOR_con_0(1) = '0' and
BIT_VECTOR_con_0(2) = '0' and
BIT_VECTOR_con_0(3) = '0' and
BIT_VECTOR_con_0(4) = '0' and
BIT_VECTOR_con_0(5) = '0' and
BIT_VECTOR_con_0(6) = '0' and
BIT_VECTOR_con_0(7) = '0' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con_0(NUL) = INTEGER'LEFT and
ut_chary_con_0(SOH) = INTEGER'LEFT and
ut_chary_con_0(STX) = INTEGER'LEFT and
ut_chary_con_0(ETX) = INTEGER'LEFT and
ut_chary_con_0(EOT) = INTEGER'LEFT and
ut_chary_con_0(ENQ) = INTEGER'LEFT and
ut_chary_con_1(NUL) = 1 and
ut_chary_con_1(SOH) = 2 and
ut_chary_con_1(STX) = 3 and
ut_chary_con_1(ETX) = 9 and
ut_chary_con_1(EOT) = 8 and
ut_chary_con_1(ENQ) = 7 and
ct_word_con_0(0) = '0' and
ct_word_con_0(1) = '0' and
ct_word_con_0(2) = '0' and
ct_word_con_0(3) = '0' and
ct_word_con_0(4) = '0' and
ct_word_con_0(5) = '0' and
ct_word_con_0(6) = '0' and
ct_word_con_0(7) = '0' and
ct_word_con_0(8) = '0' and
ct_word_con_0(9) = '0' and
ct_word_con_0(10) = '0' and
ct_word_con_0(11) = '0' and
ct_word_con_0(12) = '0' and
ct_word_con_0(13) = '0' and
ct_word_con_0(14) = '0' and
ct_word_con_0(15) = '0' and
ct_word_con_1(0) = '1' and
ct_word_con_1(1) = '1' and
ct_word_con_1(2) = '1' and
ct_word_con_1(3) = '1' and
ct_word_con_1(4) = '1' and
ct_word_con_1(5) = '1' and
ct_word_con_1(6) = '1' and
ct_word_con_1(7) = '1' and
ct_word_con_1(8) = '1' and
ct_word_con_1(9) = '1' and
ct_word_con_1(10) = '1' and
ct_word_con_1(11) = '1' and
ct_word_con_1(12) = '1' and
ct_word_con_1(13) = '1' and
ct_word_con_1(14) = '1' and
ct_word_con_1(15) = '1' and
cst_str10_con_0(1) = NUL and
cst_str10_con_0(2) = NUL and
cst_str10_con_0(3) = NUL and
cst_str10_con_0(4) = NUL and
cst_str10_con_0(5) = NUL and
cst_str10_con_0(6) = NUL and
cst_str10_con_0(7) = NUL and
cst_str10_con_0(8) = NUL and
cst_str10_con_0(9) = NUL and
cst_str10_con_0(10) = NUL and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con_0('0') = INTEGER'LEFT and
cst_digit_con_0('1') = INTEGER'LEFT and
cst_digit_con_0('2') = INTEGER'LEFT and
cst_digit_con_0('3') = INTEGER'LEFT and
cst_digit_con_0('4') = INTEGER'LEFT and
cst_digit_con_0('5') = INTEGER'LEFT and
cst_digit_con_0('6') = INTEGER'LEFT and
cst_digit_con_0('7') = INTEGER'LEFT and
cst_digit_con_0('8') = INTEGER'LEFT and
cst_digit_con_0('9') = INTEGER'LEFT and
cst_digit_con_1('0') = 0 and
cst_digit_con_1('1') = 1 and
cst_digit_con_1('2') = 2 and
cst_digit_con_1('3') = 3 and
cst_digit_con_1('4') = 4 and
cst_digit_con_1('5') = 5 and
cst_digit_con_1('6') = 6 and
cst_digit_con_1('7') = 7 and
cst_digit_con_1('8') = 8 and
cst_digit_con_1('9') = 9 and
rt_date_con_0.day = 0 and
rt_date_con_0.month = Jan and
rt_date_con_0.year = 0 and
rt_date_con_1.day = 1 and
rt_date_con_1.month = Jan and
rt_date_con_1.year = 1989 and
rst_date_con_0.day = 0 and
rst_date_con_0.month = Jan and
rst_date_con_0.year = 0 and
rst_date_con_1.day = 1 and
rst_date_con_1.month = Apr and
rst_date_con_1.year = 2000 )
report "***PASSED TEST: /src/ch04/sc03/sb01/ss03/p001/s010101.vhd"
severity NOTE;
assert ( STRING_con_0(1) = NUL and
STRING_con_0(2) = NUL and
STRING_con_0(3) = NUL and
STRING_con_0(4) = NUL and
STRING_con_0(5) = NUL and
STRING_con_0(6) = NUL and
STRING_con_0(7) = NUL and
STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_0(0) = '0' and
BIT_VECTOR_con_0(1) = '0' and
BIT_VECTOR_con_0(2) = '0' and
BIT_VECTOR_con_0(3) = '0' and
BIT_VECTOR_con_0(4) = '0' and
BIT_VECTOR_con_0(5) = '0' and
BIT_VECTOR_con_0(6) = '0' and
BIT_VECTOR_con_0(7) = '0' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con_0(NUL) = INTEGER'LEFT and
ut_chary_con_0(SOH) = INTEGER'LEFT and
ut_chary_con_0(STX) = INTEGER'LEFT and
ut_chary_con_0(ETX) = INTEGER'LEFT and
ut_chary_con_0(EOT) = INTEGER'LEFT and
ut_chary_con_0(ENQ) = INTEGER'LEFT and
ut_chary_con_1(NUL) = 1 and
ut_chary_con_1(SOH) = 2 and
ut_chary_con_1(STX) = 3 and
ut_chary_con_1(ETX) = 9 and
ut_chary_con_1(EOT) = 8 and
ut_chary_con_1(ENQ) = 7 and
ct_word_con_0(0) = '0' and
ct_word_con_0(1) = '0' and
ct_word_con_0(2) = '0' and
ct_word_con_0(3) = '0' and
ct_word_con_0(4) = '0' and
ct_word_con_0(5) = '0' and
ct_word_con_0(6) = '0' and
ct_word_con_0(7) = '0' and
ct_word_con_0(8) = '0' and
ct_word_con_0(9) = '0' and
ct_word_con_0(10) = '0' and
ct_word_con_0(11) = '0' and
ct_word_con_0(12) = '0' and
ct_word_con_0(13) = '0' and
ct_word_con_0(14) = '0' and
ct_word_con_0(15) = '0' and
ct_word_con_1(0) = '1' and
ct_word_con_1(1) = '1' and
ct_word_con_1(2) = '1' and
ct_word_con_1(3) = '1' and
ct_word_con_1(4) = '1' and
ct_word_con_1(5) = '1' and
ct_word_con_1(6) = '1' and
ct_word_con_1(7) = '1' and
ct_word_con_1(8) = '1' and
ct_word_con_1(9) = '1' and
ct_word_con_1(10) = '1' and
ct_word_con_1(11) = '1' and
ct_word_con_1(12) = '1' and
ct_word_con_1(13) = '1' and
ct_word_con_1(14) = '1' and
ct_word_con_1(15) = '1' and
cst_str10_con_0(1) = NUL and
cst_str10_con_0(2) = NUL and
cst_str10_con_0(3) = NUL and
cst_str10_con_0(4) = NUL and
cst_str10_con_0(5) = NUL and
cst_str10_con_0(6) = NUL and
cst_str10_con_0(7) = NUL and
cst_str10_con_0(8) = NUL and
cst_str10_con_0(9) = NUL and
cst_str10_con_0(10) = NUL and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con_0('0') = INTEGER'LEFT and
cst_digit_con_0('1') = INTEGER'LEFT and
cst_digit_con_0('2') = INTEGER'LEFT and
cst_digit_con_0('3') = INTEGER'LEFT and
cst_digit_con_0('4') = INTEGER'LEFT and
cst_digit_con_0('5') = INTEGER'LEFT and
cst_digit_con_0('6') = INTEGER'LEFT and
cst_digit_con_0('7') = INTEGER'LEFT and
cst_digit_con_0('8') = INTEGER'LEFT and
cst_digit_con_0('9') = INTEGER'LEFT and
cst_digit_con_1('0') = 0 and
cst_digit_con_1('1') = 1 and
cst_digit_con_1('2') = 2 and
cst_digit_con_1('3') = 3 and
cst_digit_con_1('4') = 4 and
cst_digit_con_1('5') = 5 and
cst_digit_con_1('6') = 6 and
cst_digit_con_1('7') = 7 and
cst_digit_con_1('8') = 8 and
cst_digit_con_1('9') = 9 and
rt_date_con_0.day = 0 and
rt_date_con_0.month = Jan and
rt_date_con_0.year = 0 and
rt_date_con_1.day = 1 and
rt_date_con_1.month = Jan and
rt_date_con_1.year = 1989 and
rst_date_con_0.day = 0 and
rst_date_con_0.month = Jan and
rst_date_con_0.year = 0 and
rst_date_con_1.day = 1 and
rst_date_con_1.month = Apr and
rst_date_con_1.year = 2000 )
report "***FAILED TEST: c04s03b01x03p01n01i00082 - A variable declaration declares a variable of the specified type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x03p01n01i00082arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc82.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x03p01n01i00082ent IS
END c04s03b01x03p01n01i00082ent;
ARCHITECTURE c04s03b01x03p01n01i00082arch OF c04s03b01x03p01n01i00082ent IS
--
--
-- Declaration of composite types
-- - array types and subtypes
--
TYPE ut_chary IS ARRAY (CHARACTER RANGE <>) OF INTEGER; -- unconstrained array type
TYPE ct_word IS ARRAY (0 TO 15) OF BIT; -- constrained array type
SUBTYPE ust_subchary IS ut_chary; -- unconstrained array subtype
SUBTYPE cst_str10 IS STRING ( 1 TO 10 ); -- constrained array subtype
SUBTYPE cst_digit IS ut_chary ('0' TO '9'); -- constrained array subtype
--
-- Declaration of composite types
-- - records types and subtypes
--
TYPE month_name IS (Jan, Feb, Mar, Apr, May, Jun, Jul, Aug, Sep, Oct, Nov, Dec );
TYPE rt_date IS
RECORD
day : INTEGER RANGE 0 TO 31;
month : month_name;
year : INTEGER RANGE 0 TO 4000;
END RECORD;
--
SUBTYPE rst_date IS rt_date;
BEGIN
TESTING: PROCESS
--
-- VARIABLE declarations
--
VARIABLE STRING_con_0 : STRING (1 TO 7);
VARIABLE STRING_con_1 : STRING (1 TO 7) := "sailing";
VARIABLE STRING_con_2 : STRING (1 TO 7) := ( 's', 'a', 'i', 'l', 'i', 'n', 'g');
VARIABLE BIT_VECTOR_con_0 : BIT_VECTOR (0 TO 7);
VARIABLE BIT_VECTOR_con_1 : BIT_VECTOR (0 TO 7) := B"10101110";
VARIABLE BIT_VECTOR_con_2 : BIT_VECTOR (0 TO 7) := ( '1', '0', '1', '0', '1', '1', '1', '0');
VARIABLE ut_chary_con_0 : ut_chary (NUL TO ENQ);
VARIABLE ut_chary_con_1 : ut_chary (NUL TO ENQ) := ( 1, 2, 3, 9, 8, 7);
VARIABLE ct_word_con_0 : ct_word;
VARIABLE ct_word_con_1 : ct_word := ( '1', '1', '1', '1', '1', '1', '1', '1',
'1', '1', '1', '1', '1', '1', '1', '1');
VARIABLE cst_str10_con_0 : cst_str10;
VARIABLE cst_str10_con_1 : cst_str10 := "abcdefghij";
VARIABLE cst_str10_con_2 : cst_str10 := ( 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j');
VARIABLE cst_digit_con_0 : cst_digit;
VARIABLE cst_digit_con_1 : cst_digit := ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
VARIABLE rt_date_con_0 : rt_date;
VARIABLE rt_date_con_1 : rt_date := (1, Jan, 1989);
VARIABLE rst_date_con_0 : rst_date;
VARIABLE rst_date_con_1 : rst_date := (1, Apr, 2000);
----------------------------------------------------------------------------------------------------------
BEGIN
ASSERT STRING_con_0(1) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(2) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(3) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(4) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(5) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(6) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_0(7) = NUL REPORT "STRING_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(1) = 's' REPORT "STRING_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(2) = 'a' REPORT "STRING_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(3) = 'i' REPORT "STRING_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(4) = 'l' REPORT "STRING_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(5) = 'i' REPORT "STRING_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(6) = 'n' REPORT "STRING_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_1(7) = 'g' REPORT "STRING_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(1) = 's' REPORT "STRING_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(2) = 'a' REPORT "STRING_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(3) = 'i' REPORT "STRING_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(4) = 'l' REPORT "STRING_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(5) = 'i' REPORT "STRING_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(6) = 'n' REPORT "STRING_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT STRING_con_2(7) = 'g' REPORT "STRING_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(0) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(1) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(2) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(3) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(4) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(5) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(6) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_0(7) = '0' REPORT "BIT_VECTOR_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(0) = '1' REPORT "BIT_VECTOR_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(1) = '0' REPORT "BIT_VECTOR_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(2) = '1' REPORT "BIT_VECTOR_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(3) = '0' REPORT "BIT_VECTOR_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(4) = '1' REPORT "BIT_VECTOR_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(5) = '1' REPORT "BIT_VECTOR_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(6) = '1' REPORT "BIT_VECTOR_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_1(7) = '0' REPORT "BIT_VECTOR_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(0) = '1' REPORT "BIT_VECTOR_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(1) = '0' REPORT "BIT_VECTOR_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(2) = '1' REPORT "BIT_VECTOR_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(3) = '0' REPORT "BIT_VECTOR_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(4) = '1' REPORT "BIT_VECTOR_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(5) = '1' REPORT "BIT_VECTOR_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(6) = '1' REPORT "BIT_VECTOR_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT BIT_VECTOR_con_2(7) = '0' REPORT "BIT_VECTOR_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(NUL) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(SOH) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(STX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(ETX) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(EOT) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_0(ENQ) = INTEGER'LEFT REPORT "ut_chary_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(NUL) = 1 REPORT "ut_chary_con_1('a') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(SOH) = 2 REPORT "ut_chary_con_1('b') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(STX) = 3 REPORT "ut_chary_con_1('c') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(ETX) = 9 REPORT "ut_chary_con_1('d') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(EOT) = 8 REPORT "ut_chary_con_1('e') not properly intialized" SEVERITY FAILURE;
ASSERT ut_chary_con_1(ENQ) = 7 REPORT "ut_chary_con_1('f') not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(0) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(1) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(2) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(3) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(4) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(5) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(6) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(7) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(8) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(9) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(10) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(11) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(12) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(13) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(14) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_0(15) = '0' REPORT "ct_word_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(0) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(1) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(2) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(3) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(4) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(5) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(6) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(7) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(8) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(9) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(10) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(11) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(12) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(13) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(14) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT ct_word_con_1(15) = '1' REPORT "ct_word_con_1 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(1) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(2) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(3) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(4) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(5) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(6) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(7) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(8) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(9) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_0(10) = NUL REPORT "cst_str10_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(1) = 'a' REPORT "cst_str10_con_1(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(2) = 'b' REPORT "cst_str10_con_1(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(3) = 'c' REPORT "cst_str10_con_1(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(4) = 'd' REPORT "cst_str10_con_1(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(5) = 'e' REPORT "cst_str10_con_1(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(6) = 'f' REPORT "cst_str10_con_1(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(7) = 'g' REPORT "cst_str10_con_1(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(8) = 'h' REPORT "cst_str10_con_1(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(9) = 'i' REPORT "cst_str10_con_1(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_1(10)= 'j' REPORT "cst_str10_con_1(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(1) = 'a' REPORT "cst_str10_con_2(1) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(2) = 'b' REPORT "cst_str10_con_2(2) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(3) = 'c' REPORT "cst_str10_con_2(3) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(4) = 'd' REPORT "cst_str10_con_2(4) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(5) = 'e' REPORT "cst_str10_con_2(5) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(6) = 'f' REPORT "cst_str10_con_2(6) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(7) = 'g' REPORT "cst_str10_con_2(7) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(8) = 'h' REPORT "cst_str10_con_2(8) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(9) = 'i' REPORT "cst_str10_con_2(9) not properly intialized" SEVERITY FAILURE;
ASSERT cst_str10_con_2(10)= 'j' REPORT "cst_str10_con_2(10)not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('0') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('1') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('2') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('3') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('4') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('5') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('6') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('7') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('8') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_0('9') = INTEGER'LEFT REPORT "cst_digit_con_0 not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('0') = 0 REPORT "cst_digit_con_1('0') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('1') = 1 REPORT "cst_digit_con_1('1') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('2') = 2 REPORT "cst_digit_con_1('2') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('3') = 3 REPORT "cst_digit_con_1('3') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('4') = 4 REPORT "cst_digit_con_1('4') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('5') = 5 REPORT "cst_digit_con_1('5') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('6') = 6 REPORT "cst_digit_con_1('6') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('7') = 7 REPORT "cst_digit_con_1('7') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('8') = 8 REPORT "cst_digit_con_1('8') not properly intialized" SEVERITY FAILURE;
ASSERT cst_digit_con_1('9') = 9 REPORT "cst_digit_con_1('9') not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.day = 0 REPORT " rt_date_con_0.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.month = Jan REPORT " rt_date_con_0.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_0.year = 0 REPORT " rt_date_con_0.year not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.day = 1 REPORT " rt_date_con_1.day not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.month = Jan REPORT " rt_date_con_1.month not properly intialized" SEVERITY FAILURE;
ASSERT rt_date_con_1.year = 1989 REPORT " rt_date_con_1.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.day = 0 REPORT "rst_date_con_0.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.month = Jan REPORT "rst_date_con_0.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_0.year = 0 REPORT "rst_date_con_0.year not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.day = 1 REPORT "rst_date_con_1.day not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.month = Apr REPORT "rst_date_con_1.month not properly intialized" SEVERITY FAILURE;
ASSERT rst_date_con_1.year = 2000 REPORT "rst_date_con_1.year not properly intialized" SEVERITY FAILURE;
--------------------------------------------------------------------------------------------------------------
assert NOT( STRING_con_0(1) = NUL and
STRING_con_0(2) = NUL and
STRING_con_0(3) = NUL and
STRING_con_0(4) = NUL and
STRING_con_0(5) = NUL and
STRING_con_0(6) = NUL and
STRING_con_0(7) = NUL and
STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_0(0) = '0' and
BIT_VECTOR_con_0(1) = '0' and
BIT_VECTOR_con_0(2) = '0' and
BIT_VECTOR_con_0(3) = '0' and
BIT_VECTOR_con_0(4) = '0' and
BIT_VECTOR_con_0(5) = '0' and
BIT_VECTOR_con_0(6) = '0' and
BIT_VECTOR_con_0(7) = '0' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con_0(NUL) = INTEGER'LEFT and
ut_chary_con_0(SOH) = INTEGER'LEFT and
ut_chary_con_0(STX) = INTEGER'LEFT and
ut_chary_con_0(ETX) = INTEGER'LEFT and
ut_chary_con_0(EOT) = INTEGER'LEFT and
ut_chary_con_0(ENQ) = INTEGER'LEFT and
ut_chary_con_1(NUL) = 1 and
ut_chary_con_1(SOH) = 2 and
ut_chary_con_1(STX) = 3 and
ut_chary_con_1(ETX) = 9 and
ut_chary_con_1(EOT) = 8 and
ut_chary_con_1(ENQ) = 7 and
ct_word_con_0(0) = '0' and
ct_word_con_0(1) = '0' and
ct_word_con_0(2) = '0' and
ct_word_con_0(3) = '0' and
ct_word_con_0(4) = '0' and
ct_word_con_0(5) = '0' and
ct_word_con_0(6) = '0' and
ct_word_con_0(7) = '0' and
ct_word_con_0(8) = '0' and
ct_word_con_0(9) = '0' and
ct_word_con_0(10) = '0' and
ct_word_con_0(11) = '0' and
ct_word_con_0(12) = '0' and
ct_word_con_0(13) = '0' and
ct_word_con_0(14) = '0' and
ct_word_con_0(15) = '0' and
ct_word_con_1(0) = '1' and
ct_word_con_1(1) = '1' and
ct_word_con_1(2) = '1' and
ct_word_con_1(3) = '1' and
ct_word_con_1(4) = '1' and
ct_word_con_1(5) = '1' and
ct_word_con_1(6) = '1' and
ct_word_con_1(7) = '1' and
ct_word_con_1(8) = '1' and
ct_word_con_1(9) = '1' and
ct_word_con_1(10) = '1' and
ct_word_con_1(11) = '1' and
ct_word_con_1(12) = '1' and
ct_word_con_1(13) = '1' and
ct_word_con_1(14) = '1' and
ct_word_con_1(15) = '1' and
cst_str10_con_0(1) = NUL and
cst_str10_con_0(2) = NUL and
cst_str10_con_0(3) = NUL and
cst_str10_con_0(4) = NUL and
cst_str10_con_0(5) = NUL and
cst_str10_con_0(6) = NUL and
cst_str10_con_0(7) = NUL and
cst_str10_con_0(8) = NUL and
cst_str10_con_0(9) = NUL and
cst_str10_con_0(10) = NUL and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con_0('0') = INTEGER'LEFT and
cst_digit_con_0('1') = INTEGER'LEFT and
cst_digit_con_0('2') = INTEGER'LEFT and
cst_digit_con_0('3') = INTEGER'LEFT and
cst_digit_con_0('4') = INTEGER'LEFT and
cst_digit_con_0('5') = INTEGER'LEFT and
cst_digit_con_0('6') = INTEGER'LEFT and
cst_digit_con_0('7') = INTEGER'LEFT and
cst_digit_con_0('8') = INTEGER'LEFT and
cst_digit_con_0('9') = INTEGER'LEFT and
cst_digit_con_1('0') = 0 and
cst_digit_con_1('1') = 1 and
cst_digit_con_1('2') = 2 and
cst_digit_con_1('3') = 3 and
cst_digit_con_1('4') = 4 and
cst_digit_con_1('5') = 5 and
cst_digit_con_1('6') = 6 and
cst_digit_con_1('7') = 7 and
cst_digit_con_1('8') = 8 and
cst_digit_con_1('9') = 9 and
rt_date_con_0.day = 0 and
rt_date_con_0.month = Jan and
rt_date_con_0.year = 0 and
rt_date_con_1.day = 1 and
rt_date_con_1.month = Jan and
rt_date_con_1.year = 1989 and
rst_date_con_0.day = 0 and
rst_date_con_0.month = Jan and
rst_date_con_0.year = 0 and
rst_date_con_1.day = 1 and
rst_date_con_1.month = Apr and
rst_date_con_1.year = 2000 )
report "***PASSED TEST: /src/ch04/sc03/sb01/ss03/p001/s010101.vhd"
severity NOTE;
assert ( STRING_con_0(1) = NUL and
STRING_con_0(2) = NUL and
STRING_con_0(3) = NUL and
STRING_con_0(4) = NUL and
STRING_con_0(5) = NUL and
STRING_con_0(6) = NUL and
STRING_con_0(7) = NUL and
STRING_con_1(1) = 's' and
STRING_con_1(2) = 'a' and
STRING_con_1(3) = 'i' and
STRING_con_1(4) = 'l' and
STRING_con_1(5) = 'i' and
STRING_con_1(6) = 'n' and
STRING_con_1(7) = 'g' and
STRING_con_2(1) = 's' and
STRING_con_2(2) = 'a' and
STRING_con_2(3) = 'i' and
STRING_con_2(4) = 'l' and
STRING_con_2(5) = 'i' and
STRING_con_2(6) = 'n' and
STRING_con_2(7) = 'g' and
BIT_VECTOR_con_0(0) = '0' and
BIT_VECTOR_con_0(1) = '0' and
BIT_VECTOR_con_0(2) = '0' and
BIT_VECTOR_con_0(3) = '0' and
BIT_VECTOR_con_0(4) = '0' and
BIT_VECTOR_con_0(5) = '0' and
BIT_VECTOR_con_0(6) = '0' and
BIT_VECTOR_con_0(7) = '0' and
BIT_VECTOR_con_1(0) = '1' and
BIT_VECTOR_con_1(1) = '0' and
BIT_VECTOR_con_1(2) = '1' and
BIT_VECTOR_con_1(3) = '0' and
BIT_VECTOR_con_1(4) = '1' and
BIT_VECTOR_con_1(5) = '1' and
BIT_VECTOR_con_1(6) = '1' and
BIT_VECTOR_con_1(7) = '0' and
BIT_VECTOR_con_2(0) = '1' and
BIT_VECTOR_con_2(1) = '0' and
BIT_VECTOR_con_2(2) = '1' and
BIT_VECTOR_con_2(3) = '0' and
BIT_VECTOR_con_2(4) = '1' and
BIT_VECTOR_con_2(5) = '1' and
BIT_VECTOR_con_2(6) = '1' and
BIT_VECTOR_con_2(7) = '0' and
ut_chary_con_0(NUL) = INTEGER'LEFT and
ut_chary_con_0(SOH) = INTEGER'LEFT and
ut_chary_con_0(STX) = INTEGER'LEFT and
ut_chary_con_0(ETX) = INTEGER'LEFT and
ut_chary_con_0(EOT) = INTEGER'LEFT and
ut_chary_con_0(ENQ) = INTEGER'LEFT and
ut_chary_con_1(NUL) = 1 and
ut_chary_con_1(SOH) = 2 and
ut_chary_con_1(STX) = 3 and
ut_chary_con_1(ETX) = 9 and
ut_chary_con_1(EOT) = 8 and
ut_chary_con_1(ENQ) = 7 and
ct_word_con_0(0) = '0' and
ct_word_con_0(1) = '0' and
ct_word_con_0(2) = '0' and
ct_word_con_0(3) = '0' and
ct_word_con_0(4) = '0' and
ct_word_con_0(5) = '0' and
ct_word_con_0(6) = '0' and
ct_word_con_0(7) = '0' and
ct_word_con_0(8) = '0' and
ct_word_con_0(9) = '0' and
ct_word_con_0(10) = '0' and
ct_word_con_0(11) = '0' and
ct_word_con_0(12) = '0' and
ct_word_con_0(13) = '0' and
ct_word_con_0(14) = '0' and
ct_word_con_0(15) = '0' and
ct_word_con_1(0) = '1' and
ct_word_con_1(1) = '1' and
ct_word_con_1(2) = '1' and
ct_word_con_1(3) = '1' and
ct_word_con_1(4) = '1' and
ct_word_con_1(5) = '1' and
ct_word_con_1(6) = '1' and
ct_word_con_1(7) = '1' and
ct_word_con_1(8) = '1' and
ct_word_con_1(9) = '1' and
ct_word_con_1(10) = '1' and
ct_word_con_1(11) = '1' and
ct_word_con_1(12) = '1' and
ct_word_con_1(13) = '1' and
ct_word_con_1(14) = '1' and
ct_word_con_1(15) = '1' and
cst_str10_con_0(1) = NUL and
cst_str10_con_0(2) = NUL and
cst_str10_con_0(3) = NUL and
cst_str10_con_0(4) = NUL and
cst_str10_con_0(5) = NUL and
cst_str10_con_0(6) = NUL and
cst_str10_con_0(7) = NUL and
cst_str10_con_0(8) = NUL and
cst_str10_con_0(9) = NUL and
cst_str10_con_0(10) = NUL and
cst_str10_con_1(1) = 'a' and
cst_str10_con_1(2) = 'b' and
cst_str10_con_1(3) = 'c' and
cst_str10_con_1(4) = 'd' and
cst_str10_con_1(5) = 'e' and
cst_str10_con_1(6) = 'f' and
cst_str10_con_1(7) = 'g' and
cst_str10_con_1(8) = 'h' and
cst_str10_con_1(9) = 'i' and
cst_str10_con_1(10)= 'j' and
cst_str10_con_2(1) = 'a' and
cst_str10_con_2(2) = 'b' and
cst_str10_con_2(3) = 'c' and
cst_str10_con_2(4) = 'd' and
cst_str10_con_2(5) = 'e' and
cst_str10_con_2(6) = 'f' and
cst_str10_con_2(7) = 'g' and
cst_str10_con_2(8) = 'h' and
cst_str10_con_2(9) = 'i' and
cst_str10_con_2(10)= 'j' and
cst_digit_con_0('0') = INTEGER'LEFT and
cst_digit_con_0('1') = INTEGER'LEFT and
cst_digit_con_0('2') = INTEGER'LEFT and
cst_digit_con_0('3') = INTEGER'LEFT and
cst_digit_con_0('4') = INTEGER'LEFT and
cst_digit_con_0('5') = INTEGER'LEFT and
cst_digit_con_0('6') = INTEGER'LEFT and
cst_digit_con_0('7') = INTEGER'LEFT and
cst_digit_con_0('8') = INTEGER'LEFT and
cst_digit_con_0('9') = INTEGER'LEFT and
cst_digit_con_1('0') = 0 and
cst_digit_con_1('1') = 1 and
cst_digit_con_1('2') = 2 and
cst_digit_con_1('3') = 3 and
cst_digit_con_1('4') = 4 and
cst_digit_con_1('5') = 5 and
cst_digit_con_1('6') = 6 and
cst_digit_con_1('7') = 7 and
cst_digit_con_1('8') = 8 and
cst_digit_con_1('9') = 9 and
rt_date_con_0.day = 0 and
rt_date_con_0.month = Jan and
rt_date_con_0.year = 0 and
rt_date_con_1.day = 1 and
rt_date_con_1.month = Jan and
rt_date_con_1.year = 1989 and
rst_date_con_0.day = 0 and
rst_date_con_0.month = Jan and
rst_date_con_0.year = 0 and
rst_date_con_1.day = 1 and
rst_date_con_1.month = Apr and
rst_date_con_1.year = 2000 )
report "***FAILED TEST: c04s03b01x03p01n01i00082 - A variable declaration declares a variable of the specified type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x03p01n01i00082arch;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rom.vhd when simulating
-- the core, rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END rom;
ARCHITECTURE rom_a OF rom IS
-- synthesis translate_off
COMPONENT wrapped_rom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rom USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 14,
c_addrb_width => 14,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "rom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16384,
c_read_depth_b => 16384,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16384,
c_write_depth_b => 16384,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END rom_a;
|
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity dnk7_queens0 is
generic (
-- Design Parameters
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 240;
COUNT_CYCLES : boolean := false;
SENTINEL : std_logic_vector(7 downto 0) := x"FA"; -- Start Byte
-- Local Clock Parameters
CLK_FREQ : FREQ := 50 MHz;
CLK_DIV : positive := 1; -- CLK_FREQ / CLK_DIV * CLK_MUL:
CLK_MUL : positive := 22; -- as fast as possible but not above 1200 MHz
-- Output Clocks
CLK_DIV_COMP : positive := 5; -- fast computation clock
CLK_DIV_SLOW : positive := 15 -- slower communication clock
);
port (
---------------------------------------------------------------------------
-- 50-MHz Input Clock
CLK_MBCLK : in std_logic;
---------------------------------------------------------------------------
-- FPGA0: PCIe Interface
BUS_PCIE_CLK_IN_P : in std_logic;
BUS_PCIE_CLK_IN_N : in std_logic;
BUS_PCIE_CLK_OUT_P : out std_logic;
BUS_PCIE_CLK_OUT_N : out std_logic;
BUS_PCIE_TO_HOST : out std_logic_vector(38 downto 0);
BUS_PCIE_FROM_HOST : in std_logic_vector(77 downto 39);
---------------------------------------------------------------------------
-- Ring Bus
-- Output
BUS_OUT_CLKP : out std_logic;
BUS_OUT_CLKN : out std_logic;
BUS_OUT_PRE_DAT : out std_logic_vector(8 downto 0);
BUS_OUT_PRE_PUT : out std_logic;
BUS_OUT_PRE_STALL : in std_logic;
BUS_OUT_SOL_DAT : out std_logic_vector(8 downto 0);
BUS_OUT_SOL_PUT : out std_logic;
BUS_OUT_SOL_STALL : in std_logic;
-- Input
BUS_IN_CLKP : in std_logic;
BUS_IN_CLKN : in std_logic;
BUS_IN_PRE_DAT : in std_logic_vector(8 downto 0);
BUS_IN_PRE_PUT : in std_logic;
BUS_IN_PRE_STALL : out std_logic;
BUS_IN_SOL_DAT : in std_logic_vector(8 downto 0);
BUS_IN_SOL_PUT : in std_logic;
BUS_IN_SOL_STALL : out std_logic
);
end entity dnk7_queens0;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.utils.all;
use PoC.fifo.all;
library UNISIM;
use UNISIM.vcomponents.all;
architecture rtl of dnk7_queens0 is
----------------------------------------------------------------------------
-- Communication Addresses
-- Word Address: Read Write
-----------------------------------------------------------------------------
-- 0x0000 <byte capacity:32> <-:30><enable:2> input interrupt
-- 0x0004 <bytes available:32> <-:30><enable:2> output interrupt
-- 0x0008 <!vld:1><0:23><data_out:8> <-:24><data_in:8>
--
-- A data read (@ 0x8) implicitly clears an output interrupt.
-- A data write (@ 0x8) implicitly clears an input interrupt.
--
constant ADDR_STATUS : natural := 16#00#; -- status word, interrupt clearance
constant ADDR_STREAM : natural := 16#08#; -- data stream in- and output
constant ADDR_BITS : positive := 4; -- relevant address bits (at least 4)
-- Bit Length of Pre-Placement
constant PRE_BITS : positive := 4*L*log2ceil(N)-1;
constant PRE_BYTES : positive := (PRE_BITS+7)/8;
-- FIFO Dimensioning
constant FIFO_DEPTH : positive := 5*(SOLVERS+5);
constant STATE_BITS : natural := log2ceil(FIFO_DEPTH);
----------------------------------------------------------------------------
component reset_resync is
generic (
VALUE_DURING_RESET : natural := 1
);
port (
rst_in : in std_logic;
clk_in : in std_logic;
clk_out : in std_logic;
rst_out : out std_logic
);
end component;
component pcie_ddr_user_interface is
generic (
DCM_PHASE_SHIFT : natural := 30;
DCM_PERIOD : natural := 10;
DMA_ENGINE_ENABLES : natural := 7
);
port (
reset : in std_logic;
reset_out : out std_logic;
user_clk : in std_logic;
clk_out : out std_logic;
dcm_psdone : out std_logic;
dcm_psval : out std_logic_vector(16 downto 0);
dcm_psclk : in std_logic;
dcm_psen : in std_logic;
dcm_psincdec : in std_logic;
target_address : out std_logic_vector(63 downto 0);
target_write_data : out std_logic_vector(63 downto 0);
target_write_be : out std_logic_vector(7 downto 0);
target_address_valid : out std_logic;
target_write_enable : out std_logic;
target_write_accept : in std_logic;
target_read_enable : out std_logic;
target_request_tag : out std_logic_vector(3 downto 0);
target_read_data : in std_logic_vector(63 downto 0);
target_read_accept : in std_logic;
target_read_data_tag : in std_logic_vector(3 downto 0);
target_read_data_valid : in std_logic;
target_read_ctrl : out std_logic_vector(7 downto 0);
target_read_data_ctrl : in std_logic_vector(7 downto 0);
dma0_from_host_data : out std_logic_vector(63 downto 0);
dma0_from_host_ctrl : out std_logic_vector(7 downto 0);
dma0_from_host_valid : out std_logic;
dma0_from_host_advance : in std_logic;
dma1_from_host_data : out std_logic_vector(63 downto 0);
dma1_from_host_ctrl : out std_logic_vector(7 downto 0);
dma1_from_host_valid : out std_logic;
dma1_from_host_advance : in std_logic;
dma2_from_host_data : out std_logic_vector(63 downto 0);
dma2_from_host_ctrl : out std_logic_vector(7 downto 0);
dma2_from_host_valid : out std_logic;
dma2_from_host_advance : in std_logic;
dma0_to_host_data : in std_logic_vector(63 downto 0);
dma0_to_host_ctrl : in std_logic_vector(7 downto 0);
dma0_to_host_valid : in std_logic;
dma0_to_host_almost_full : out std_logic;
dma1_to_host_data : in std_logic_vector(63 downto 0);
dma1_to_host_ctrl : in std_logic_vector(7 downto 0);
dma1_to_host_valid : in std_logic;
dma1_to_host_almost_full : out std_logic;
dma2_to_host_data : in std_logic_vector(63 downto 0);
dma2_to_host_ctrl : in std_logic_vector(7 downto 0);
dma2_to_host_valid : in std_logic;
dma2_to_host_almost_full : out std_logic;
user_interrupts : in std_logic;
pcie_fromhost_counter : out std_logic_vector(31 downto 0);
PCIE_TO_HOST_DDR : out std_logic_vector(38 downto 0);
PCIE_TO_HOST_CLK_P : out std_logic;
PCIE_TO_HOST_CLK_N : out std_logic;
PCIE_FROM_HOST_DDR : in std_logic_vector(37 downto 0);
PCIE_FROM_HOST_CLK_P : in std_logic;
PCIE_FROM_HOST_CLK_N : in std_logic
);
end component;
----------------------------------------------------------------------------
-- Global Control
signal clk_comp : std_logic;
signal rst_comp : std_logic;
signal clk_slow : std_logic;
signal rst_slow : std_logic;
-----------------------------------------------------------------------------
-- Communication FIFOs
signal acap : std_logic_vector(STATE_BITS-1 downto 0);
signal avld : std_logic;
signal aful : std_logic;
signal adin : std_logic_vector(7 downto 0);
signal aput : std_logic;
signal bavl : std_logic_vector(STATE_BITS-1 downto 0);
signal bvld : std_logic;
signal bful : std_logic;
signal bdout : std_logic_vector(7 downto 0);
signal bgot : std_logic;
begin
----------------------------------------------------------------------------
-- Clock Generation
blkClock : block
signal clk50 : std_logic;
signal clkfb : std_logic;
signal clk_compu : std_logic;
signal clk_slowu : std_logic;
begin
clk_i : BUFG
port map (
I => CLK_MBCLK,
O => clk50
);
pll : PLLE2_BASE
generic map (
CLKIN1_PERIOD => to_real(to_time(CLK_FREQ), 1 ns),
DIVCLK_DIVIDE => CLK_DIV,
CLKFBOUT_MULT => CLK_MUL,
CLKOUT0_DIVIDE => CLK_DIV_COMP,
CLKOUT1_DIVIDE => CLK_DIV_SLOW,
STARTUP_WAIT => "true"
)
port map (
RST => '0',
CLKIN1 => clk50,
CLKFBOUT => clkfb,
CLKFBIN => clkfb,
CLKOUT0 => clk_compu,
CLKOUT1 => clk_slowu,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
PWRDWN => '0'
);
clk_compo : BUFG
port map (
I => clk_compu,
O => clk_comp
);
clk_slowo : BUFG
port map (
I => clk_slowu,
O => clk_slow
);
end block;
----------------------------------------------------------------------------
-- PCIe -> Target Interface
blkPcie: block
-- Local Clock
signal pcie_clk : std_logic;
signal pcie_rst : std_logic;
-- Target Interface
-- Address
signal target_address : std_logic_vector(63 downto 0);
signal target_address_valid : std_logic;
-- Writing
signal target_write_enable : std_logic;
signal target_write_accept : std_logic;
signal target_write_data : std_logic_vector(63 downto 0);
signal target_write_be : std_logic_vector( 7 downto 0);
-- Reading
signal target_read_enable : std_logic;
signal target_read_accept : std_logic;
signal target_request_tag : std_logic_vector(3 downto 0);
signal target_read_ctrl : std_logic_vector(7 downto 0);
signal target_read_data_valid : std_logic;
signal target_read_data : std_logic_vector(63 downto 0);
signal target_read_data_tag : std_logic_vector(3 downto 0);
signal target_read_data_ctrl : std_logic_vector(7 downto 0);
-- Interrupt
signal user_interrupt : std_logic;
begin
-- Reset Recovery
resync_comp: reset_resync
port map (
rst_in => pcie_rst,
clk_in => pcie_clk,
clk_out => clk_comp,
rst_out => rst_comp
);
resync_slow: reset_resync
port map (
rst_in => pcie_rst,
clk_in => pcie_clk,
clk_out => clk_slow,
rst_out => rst_slow
);
---------------------------------------------------------------------------
-- PCIE <-> Target Interface
pcie: pcie_ddr_user_interface
generic map (
DCM_PERIOD => 6,
DCM_PHASE_SHIFT => 198
)
port map (
reset => '0',
reset_out => pcie_rst,
clk_out => pcie_clk,
user_clk => clk_slow,
PCIE_TO_HOST_DDR => bus_pcie_to_host,
PCIE_TO_HOST_CLK_P => bus_pcie_clk_out_p,
PCIE_TO_HOST_CLK_N => bus_pcie_clk_out_n,
PCIE_FROM_HOST_DDR => bus_pcie_from_host(76 downto 39),
PCIE_FROM_HOST_CLK_P => bus_pcie_clk_in_p,
PCIE_FROM_HOST_CLK_N => bus_pcie_clk_in_n,
pcie_fromhost_counter => open,
user_interrupts => user_interrupt,
target_address => target_address,
target_address_valid => target_address_valid,
target_write_enable => target_write_enable,
target_write_accept => target_write_accept,
target_write_data => target_write_data,
target_write_be => target_write_be,
target_read_enable => target_read_enable,
target_read_accept => target_read_accept,
target_request_tag => target_request_tag,
target_read_ctrl => target_read_ctrl,
target_read_data_valid => target_read_data_valid,
target_read_data => target_read_data,
target_read_data_tag => target_read_data_tag,
target_read_data_ctrl => target_read_data_ctrl,
dma0_from_host_data => open,
dma0_from_host_ctrl => open,
dma0_from_host_valid => open,
dma0_from_host_advance => '1',
dma0_to_host_data => (others => '-'),
dma0_to_host_ctrl => (others => '0'),
dma0_to_host_valid => '0',
dma0_to_host_almost_full => open,
dma1_from_host_data => open,
dma1_from_host_ctrl => open,
dma1_from_host_valid => open,
dma1_from_host_advance => '1',
dma1_to_host_data => (others => '-'),
dma1_to_host_ctrl => (others => '0'),
dma1_to_host_valid => '0',
dma1_to_host_almost_full => open,
dma2_from_host_data => open,
dma2_from_host_ctrl => open,
dma2_from_host_valid => open,
dma2_from_host_advance => '1',
dma2_to_host_data => (others => '-'),
dma2_to_host_ctrl => (others => '0'),
dma2_to_host_valid => '0',
dma2_to_host_almost_full => open,
dcm_psdone => open,
dcm_psval => open,
dcm_psclk => clk_slow,
dcm_psen => '0',
dcm_psincdec => '0'
);
---------------------------------------------------------------------------
-- Writing
target_write_accept <= '1';
aput <= target_write_enable and target_write_be(0) when
to_integer(unsigned(target_address(ADDR_BITS-1 downto 0))) = ADDR_STREAM else '0';
adin <= target_write_data(7 downto 0);
---------------------------------------------------------------------------
-- Reading
bgot <= '0' when to_integer(unsigned(target_address(ADDR_BITS-1 downto 0))) /= ADDR_STREAM else
target_read_enable;
blkRead: block
signal rdVld : std_logic := '0';
signal rdTag : std_logic_vector( 3 downto 0) := (others => '-');
signal rdCtl : std_logic_vector( 7 downto 0) := (others => '-');
signal rdDat : std_logic_vector(63 downto 0) := (others => '-');
begin
process(clk_slow)
begin
if rising_edge(clk_slow) then
rdVld <= '0';
rdTag <= (others => '-');
rdCtl <= (others => '-');
rdDat <= (others => '-');
if rst_slow = '0' then
-- Only accept word-align addresses
if target_read_enable = '1' and target_address(1 downto 0) = "00" then
rdVld <= '1';
rdTag <= target_request_tag;
rdCtl <= target_read_ctrl;
rdDat <= (others => '0');
if to_integer(unsigned(target_address(ADDR_BITS-1 downto 3))) = ADDR_STATUS/8 then
-- Query FIFO States
rdDat(STATE_BITS+31 downto 32) <= bavl; -- @4
rdDat(STATE_BITS- 1 downto 0) <= acap; -- @0
elsif bgot = '1' then
-- Read Output
rdDat(31) <= not bvld; -- @8
rdDat(7 downto 0) <= bdout;
end if;
end if;
end if;
end if;
end process;
target_read_accept <= '1';
target_read_data_valid <= rdVld;
target_read_data <= rdDat;
target_read_data_tag <= rdTag;
target_read_data_ctrl <= rdCtl;
end block blkRead;
---------------------------------------------------------------------------
-- Interrupts
blkInterrupt: block
-- Delayed FIFO Status
signal Zavld : std_logic := '0';
signal Zaful : std_logic := '0';
signal Zbvld : std_logic := '0';
signal Zbful : std_logic := '0';
-- Interrupt State
signal EnaIn : std_logic := '0'; -- Enable
signal EnaOut : std_logic := '0';
signal IrqIn : std_logic := '0'; -- Pending
signal IrqOut : std_logic := '0';
begin
process(clk_slow)
begin
if rising_edge(clk_slow) then
if rst_slow = '1' then
Zavld <= '0';
Zaful <= '0';
Zbvld <= '0';
Zbful <= '0';
EnaIn <= '0';
EnaOut <= '0';
IrqIn <= '0';
IrqOut <= '0';
else
-- Delayed Status for Edge Detection
Zavld <= avld;
Zaful <= aful;
Zbvld <= bvld;
Zbful <= bful;
-- Input IRQ: space has become available | FIFO drained
if target_write_enable = '1' and target_write_be(0) = '1' and
to_integer(unsigned(target_address(ADDR_BITS-1 downto 0))) = ADDR_STATUS then
if target_write_data(1) = '1' then
EnaIn <= '1';
elsif target_write_data(0) = '0' then
EnaIn <= '0';
end if;
if target_write_data(1) = '0' then
IrqIn <= '0';
elsif target_write_data(0) = '1' then
IrqIn <= not aful;
end if;
elsif aput = '1' then
IrqIn <= '0';
elsif aful = '0' and Zaful = '1' then
IrqIn <= EnaIn;
elsif avld = '0' and Zavld = '1' then
IrqIn <= EnaIn;
end if;
-- Output IRQ: data has become available | FIFO full
if target_write_enable = '1' and target_write_be(4) = '1' and
to_integer(unsigned(target_address(ADDR_BITS-1 downto 0))) = ADDR_STATUS+4 then
if target_write_data(33) = '1' then
EnaOut <= '1';
elsif target_write_data(32) = '0' then
EnaOut <= '0';
end if;
if target_write_data(33) = '0' then
IrqOut <= '0';
elsif target_write_data(32) = '1' then
IrqOut <= bvld;
end if;
elsif bvld = '1' and bgot = '1' then
IrqOut <= '0';
elsif bvld = '1' and Zbvld = '0' then
IrqOut <= EnaOut;
elsif bful = '1' and Zbful = '0' then
IrqOut <= EnaOut;
end if;
end if;
end if;
end process;
user_interrupt <= IrqIn or IrqOut;
end block blkInterrupt;
end block blkPcie;
----------------------------------------------------------------------------
-- Input FIFO to Ring Bus
blkFeed: block
-- Byte FIFO -> Unframe
signal glue_vld : std_logic;
signal glue_dat : byte;
signal glue_got : std_logic;
-- Unframe -> Stream FIFO
signal oful : std_logic;
signal odat : byte;
signal oeof : std_logic;
signal oput : std_logic;
signal ocommit : std_logic;
signal orollback : std_logic;
-- Stream -> Ring Bus
signal pigot : std_logic;
signal pidat : byte;
signal pieof : std_logic;
begin
-- Raw Byte Interface: no real buffer
glue: fifo_glue
generic map (
D_BITS => 8
)
port map (
clk => clk_slow,
rst => rst_slow,
put => aput,
di => adin,
ful => aful,
vld => glue_vld,
do => glue_dat,
got => glue_got
);
-- Frame Extraction
unframe_i: entity work.unframe
generic map (
SENTINEL => SENTINEL,
PAY_LEN => PRE_BYTES
)
port map (
clk => clk_slow,
rst => rst_slow,
rx_dat => glue_dat,
rx_vld => glue_vld,
rx_got => glue_got,
odat => odat,
oeof => oeof,
oful => oful,
oput => oput,
ocommit => ocommit,
orollback => orollback
);
buf: fifo_cc_got_tempput
generic map (
D_BITS => 9,
MIN_DEPTH => FIFO_DEPTH,
ESTATE_WR_BITS => STATE_BITS
)
port map (
clk => clk_slow,
rst => rst_slow,
put => oput,
din(8) => oeof,
din(7 downto 0) => odat,
full => oful,
commit => ocommit,
rollback => orollback,
estate_wr => acap,
got => pigot,
dout(8) => pieof,
dout(7 downto 0) => pidat,
valid => avld
);
blkBus: block
-- Syncing the stall input
signal stall_s : std_logic_vector(1 downto 0) := (others => '1');
-- Outgoing Output Registers
signal OutDat : std_logic_vector(7 downto 0) := (others => '0');
signal OutEof : std_logic := '0';
signal OutPut : std_logic := '0';
-- Inverted Output Clock
signal clk_inv : std_logic;
begin
-------------------------------------------------------------------------
-- Output Inverted Clock
blkClock : block
signal clk_inv : std_logic;
begin
invert : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '1',
SRTYPE => "SYNC"
)
port map (
Q => clk_inv, -- 1-bit DDR output
C => clk_slow, -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D1 => '0', -- 1-bit data input (positive edge)
D2 => '1', -- 1-bit data input (negative edge)
R => rst_slow, -- 1-bit reset input
S => '0' -- 1-bit set input
);
OBUFDS_inst : OBUFDS
generic map (
IOSTANDARD => "DEFAULT",
SLEW => "FAST"
)
port map (
O => BUS_OUT_CLKP,
OB => BUS_OUT_CLKN,
I => clk_inv
);
end block blkClock;
-------------------------------------------------------------------------
-- Pre-placement Output
-- Syncing stall input
process(clk_slow)
begin
if rising_edge(clk_slow) then
if rst_slow = '1' then
stall_s <= (others => '1');
else
stall_s <= BUS_OUT_PRE_STALL & stall_s(stall_s'left downto 1);
end if;
end if;
end process;
pigot <= avld and not stall_s(0);
-- Output Registers
process(clk_slow)
begin
if rising_edge(clk_slow) then
if rst_slow = '1' then
OutDat <= (others => '0');
OutEof <= '0';
OutPut <= '0';
else
OutDat <= pidat;
OutEof <= pieof;
OutPut <= pigot;
end if;
end if;
end process;
BUS_OUT_PRE_DAT <= OutEof & OutDat;
BUS_OUT_PRE_PUT <= OutPut;
-------------------------------------------------------------------------
-- Start of Result Chain
BUS_OUT_SOL_DAT <= (others => '0');
BUS_OUT_SOL_PUT <= '0';
end block blkBus;
end block blkFeed;
blkDrain: block
-- Source synchronous clock domain
signal clk_in : std_logic;
signal rst_in : std_logic;
-- Incoming Bus Data Capture Registers
signal InPreDat : std_logic_vector(8 downto 0) := (others => '-');
signal InPrePut : std_logic := '0';
signal InPreCap : std_logic_vector(1 downto 0);
signal InSolDat : std_logic_vector(8 downto 0) := (others => '-');
signal InSolPut : std_logic := '0';
signal InSolCap : std_logic_vector(1 downto 0);
-- Solver Chain Connectivity
signal pivld : std_logic;
signal piful : std_logic;
signal pidat : byte;
signal pieof : std_logic;
signal piput : std_logic;
signal sivld : std_logic;
signal sidat : byte;
signal sieof : std_logic;
signal sigot : std_logic;
signal sovld : std_logic;
signal sodat : byte;
signal soeof : std_logic;
signal sogot : std_logic;
-- Solution Stream -> Frames
signal tx_dat : std_logic_vector(7 downto 0);
signal tx_ful : std_logic;
signal tx_put : std_logic;
begin
---------------------------------------------------------------------------
-- Reading the Bus
-- Clock Reconstruction
blkClock: block
signal clk_in0 : std_logic;
begin
IBUFGDS_inst : IBUFGDS
port map (
O => clk_in0,
I => BUS_IN_CLKP,
IB => BUS_IN_CLKN
);
BUFG_inst : BUFG
port map (
O => clk_in,
I => clk_in0
);
rst_in <= '0';
end block blkClock;
-- Bus Input Capture
process(clk_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
InPreDat <= (others => '-');
InPrePut <= '0';
InSolDat <= (others => '-');
InSolPut <= '0';
else
InPreDat <= BUS_IN_PRE_DAT;
InPrePut <= BUS_IN_PRE_PUT;
InSolDat <= BUS_IN_SOL_DAT;
InSolPut <= BUS_IN_SOL_PUT;
end if;
end if;
end process;
-- Input FIFO (ic): Pre-Placements
buf_pre : fifo_ic_got
generic map (
D_BITS => 9,
MIN_DEPTH => 64,
ESTATE_WR_BITS => InPreCap'length
)
port map (
clk_wr => clk_in,
rst_wr => rst_in,
put => InPrePut,
din => InPreDat,
full => open,
estate_wr => InPreCap,
clk_rd => clk_comp,
rst_rd => rst_comp,
got => piput,
dout(8) => pieof,
dout(7 downto 0) => pidat,
valid => pivld
);
piput <= pivld and not piful;
BUS_IN_PRE_STALL <= '1' when InPreCap = (InPreCap'range => '0') else '0';
-- Input FIFO (ic): Solutions
buf_sol : fifo_ic_got
generic map (
D_BITS => 9,
MIN_DEPTH => 64,
ESTATE_WR_BITS => InSolCap'length
)
port map (
clk_wr => clk_in,
rst_wr => rst_in,
put => InSolPut,
din => InSolDat,
full => open,
estate_wr => InSolCap,
clk_rd => clk_comp,
rst_rd => rst_comp,
got => sigot,
dout(8) => sieof,
dout(7 downto 0) => sidat,
valid => sivld
);
BUS_IN_SOL_STALL <= '1' when InSolCap = (InSolCap'range => '0') else '0';
---------------------------------------------------------------------------
-- Solver Chain
chain: entity work.queens_chain
generic map (
N => N,
L => L,
SOLVERS => SOLVERS,
COUNT_CYCLES => COUNT_CYCLES
)
port map (
clk => clk_comp,
rst => rst_comp,
piful => piful,
pidat => pidat,
pieof => pieof,
piput => piput,
sivld => sivld,
sidat => sidat,
sieof => sieof,
sigot => sigot,
poful => '1',
podat => open,
poeof => open,
poput => open,
sovld => sovld,
sodat => sodat,
soeof => soeof,
sogot => sogot
);
enframe_i: entity work.enframe
generic map (
SENTINEL => SENTINEL
)
port map (
clk => clk_comp,
rst => rst_comp,
ivld => sovld,
idat => sodat,
ieof => soeof,
igot => sogot,
tx_ful => tx_ful,
tx_put => tx_put,
tx_dat => tx_dat
);
-- Output FIFO (ic): Solutions
fifob : fifo_ic_got
generic map (
D_BITS => 8,
MIN_DEPTH => FIFO_DEPTH,
FSTATE_RD_BITS => STATE_BITS
)
port map (
clk_wr => clk_comp,
rst_wr => rst_comp,
put => tx_put,
din => tx_dat,
full => tx_ful,
clk_rd => clk_slow,
rst_rd => rst_slow,
got => bgot,
dout => bdout,
valid => bvld,
fstate_rd => bavl
);
end block blkDrain;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1993.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n01i01993ent IS
END c07s02b02x00p07n01i01993ent;
ARCHITECTURE c07s02b02x00p07n01i01993arch OF c07s02b02x00p07n01i01993ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : real := 5.5;
BEGIN
if (m /= 4.5) then
k := 5;
else
k := 3;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n01i01993"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n01i01993 - Inequality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i01993arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1993.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n01i01993ent IS
END c07s02b02x00p07n01i01993ent;
ARCHITECTURE c07s02b02x00p07n01i01993arch OF c07s02b02x00p07n01i01993ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : real := 5.5;
BEGIN
if (m /= 4.5) then
k := 5;
else
k := 3;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n01i01993"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n01i01993 - Inequality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i01993arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1993.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p07n01i01993ent IS
END c07s02b02x00p07n01i01993ent;
ARCHITECTURE c07s02b02x00p07n01i01993arch OF c07s02b02x00p07n01i01993ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
variable m : real := 5.5;
BEGIN
if (m /= 4.5) then
k := 5;
else
k := 3;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p07n01i01993"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p07n01i01993 - Inequality operators are not defined for file types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p07n01i01993arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY ram0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ram0;
ARCHITECTURE ram0_arch OF ram0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ram0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ram0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ram0_arch : ARCHITECTURE IS "ram0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ram0_arch: ARCHITECTURE IS "ram0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=ram0.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=bf,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 1.3396 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "ram0.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "bf",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 1.3396 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END ram0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cart_slot_pkg is
constant c_cart_c64_mode : unsigned(3 downto 0) := X"0";
constant c_cart_c64_stop : unsigned(3 downto 0) := X"1";
constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2";
constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3";
constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4";
constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5";
constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6";
constant c_cart_kernal_enable : unsigned(3 downto 0) := X"7";
constant c_cart_reu_enable : unsigned(3 downto 0) := X"8";
constant c_cart_reu_size : unsigned(3 downto 0) := X"9";
constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A";
constant c_cart_timing : unsigned(3 downto 0) := X"B";
constant c_cart_phi2_recover : unsigned(3 downto 0) := X"C";
constant c_cart_sampler_enable : unsigned(3 downto 0) := X"E";
constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F";
type t_cart_control is record
c64_reset : std_logic;
c64_nmi : std_logic;
c64_ultimax : std_logic;
c64_stop : std_logic;
c64_stop_mode : std_logic_vector(1 downto 0);
cartridge_type : std_logic_vector(3 downto 0);
cartridge_kill : std_logic;
kernal_enable : std_logic;
reu_enable : std_logic;
reu_size : std_logic_vector(2 downto 0);
eth_enable : std_logic;
sampler_enable : std_logic;
swap_buttons : std_logic;
timing_addr_valid : unsigned(2 downto 0);
phi2_edge_recover : std_logic;
end record;
type t_cart_status is record
c64_stopped : std_logic;
clock_detect : std_logic;
end record;
constant c_cart_control_init : t_cart_control := (
c64_nmi => '0',
c64_reset => '0',
c64_ultimax => '0',
c64_stop => '0',
c64_stop_mode => "00",
cartridge_type => X"0",
cartridge_kill => '0',
kernal_enable => '0',
reu_enable => '0',
reu_size => "111",
eth_enable => '0',
sampler_enable => '0',
timing_addr_valid => "100",
phi2_edge_recover => '1',
swap_buttons => '1' );
end cart_slot_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cart_slot_pkg is
constant c_cart_c64_mode : unsigned(3 downto 0) := X"0";
constant c_cart_c64_stop : unsigned(3 downto 0) := X"1";
constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2";
constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3";
constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4";
constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5";
constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6";
constant c_cart_kernal_enable : unsigned(3 downto 0) := X"7";
constant c_cart_reu_enable : unsigned(3 downto 0) := X"8";
constant c_cart_reu_size : unsigned(3 downto 0) := X"9";
constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A";
constant c_cart_timing : unsigned(3 downto 0) := X"B";
constant c_cart_phi2_recover : unsigned(3 downto 0) := X"C";
constant c_cart_sampler_enable : unsigned(3 downto 0) := X"E";
constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F";
type t_cart_control is record
c64_reset : std_logic;
c64_nmi : std_logic;
c64_ultimax : std_logic;
c64_stop : std_logic;
c64_stop_mode : std_logic_vector(1 downto 0);
cartridge_type : std_logic_vector(3 downto 0);
cartridge_kill : std_logic;
kernal_enable : std_logic;
reu_enable : std_logic;
reu_size : std_logic_vector(2 downto 0);
eth_enable : std_logic;
sampler_enable : std_logic;
swap_buttons : std_logic;
timing_addr_valid : unsigned(2 downto 0);
phi2_edge_recover : std_logic;
end record;
type t_cart_status is record
c64_stopped : std_logic;
clock_detect : std_logic;
end record;
constant c_cart_control_init : t_cart_control := (
c64_nmi => '0',
c64_reset => '0',
c64_ultimax => '0',
c64_stop => '0',
c64_stop_mode => "00",
cartridge_type => X"0",
cartridge_kill => '0',
kernal_enable => '0',
reu_enable => '0',
reu_size => "111",
eth_enable => '0',
sampler_enable => '0',
timing_addr_valid => "100",
phi2_edge_recover => '1',
swap_buttons => '1' );
end cart_slot_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cart_slot_pkg is
constant c_cart_c64_mode : unsigned(3 downto 0) := X"0";
constant c_cart_c64_stop : unsigned(3 downto 0) := X"1";
constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2";
constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3";
constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4";
constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5";
constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6";
constant c_cart_kernal_enable : unsigned(3 downto 0) := X"7";
constant c_cart_reu_enable : unsigned(3 downto 0) := X"8";
constant c_cart_reu_size : unsigned(3 downto 0) := X"9";
constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A";
constant c_cart_timing : unsigned(3 downto 0) := X"B";
constant c_cart_phi2_recover : unsigned(3 downto 0) := X"C";
constant c_cart_sampler_enable : unsigned(3 downto 0) := X"E";
constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F";
type t_cart_control is record
c64_reset : std_logic;
c64_nmi : std_logic;
c64_ultimax : std_logic;
c64_stop : std_logic;
c64_stop_mode : std_logic_vector(1 downto 0);
cartridge_type : std_logic_vector(3 downto 0);
cartridge_kill : std_logic;
kernal_enable : std_logic;
reu_enable : std_logic;
reu_size : std_logic_vector(2 downto 0);
eth_enable : std_logic;
sampler_enable : std_logic;
swap_buttons : std_logic;
timing_addr_valid : unsigned(2 downto 0);
phi2_edge_recover : std_logic;
end record;
type t_cart_status is record
c64_stopped : std_logic;
clock_detect : std_logic;
end record;
constant c_cart_control_init : t_cart_control := (
c64_nmi => '0',
c64_reset => '0',
c64_ultimax => '0',
c64_stop => '0',
c64_stop_mode => "00",
cartridge_type => X"0",
cartridge_kill => '0',
kernal_enable => '0',
reu_enable => '0',
reu_size => "111",
eth_enable => '0',
sampler_enable => '0',
timing_addr_valid => "100",
phi2_edge_recover => '1',
swap_buttons => '1' );
end cart_slot_pkg;
|
------------------------------------------------------------------------------
--
-- This vhdl module is a template for creating IP testbenches using the IBM
-- BFM toolkits. It provides a fixed interface to the subsystem testbench.
--
-- DO NOT CHANGE THE entity name, architecture name, generic parameter
-- declaration or port declaration of this file. You may add components,
-- instances, constants, signals, etc. as you wish.
--
-- See IBM Bus Functional Model Toolkit User's Manual for more information
-- on the BFMs.
--
------------------------------------------------------------------------------
-- plb_scheduler_tb.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_scheduler_tb.vhd
-- Version: 1.00.a
-- Description: IP testbench
-- Date: Mon Apr 6 14:20:49 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library plb_scheduler_v1_00_a;
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity plb_scheduler_tb is
------------------------------------------
-- DO NOT CHANGE THIS GENERIC DECLARATION
------------------------------------------
generic
(
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
);
------------------------------------------
-- DO NOT CHANGE THIS PORT DECLARATION
------------------------------------------
port
(
-- PLB (v4.6) bus interface, do not add or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- BFM synchronization bus interface
SYNCH_IN : in std_logic_vector(0 to 31) := (others => '0');
SYNCH_OUT : out std_logic_vector(0 to 31) := (others => '0')
);
end entity plb_scheduler_tb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture testbench of plb_scheduler_tb is
--USER testbench signal declarations added here as you wish
------------------------------------------
-- Signal to hook up master detected error and synch bus
------------------------------------------
signal sig_dev_mderr : std_logic;
------------------------------------------
-- Standard constants for bfl/vhdl communication
------------------------------------------
constant NOP : integer := 0;
constant START : integer := 1;
constant STOP : integer := 2;
constant WAIT_IN : integer := 3;
constant WAIT_OUT : integer := 4;
constant ASSERT_IN : integer := 5;
constant ASSERT_OUT : integer := 6;
constant ASSIGN_IN : integer := 7;
constant ASSIGN_OUT : integer := 8;
constant RESET_WDT : integer := 9;
constant MST_ERROR : integer := 30;
constant INTERRUPT : integer := 31;
signal my_reset : std_logic;
begin
------------------------------------------
-- Instance of IP under test.
-- Communication with the BFL is by using SYNCH_IN/SYNCH_OUT signals.
------------------------------------------
UUT : entity plb_scheduler_v1_00_a.plb_scheduler
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_SPLB_P2P => C_SPLB_P2P,
C_SPLB_SUPPORT_BURSTS => C_SPLB_SUPPORT_BURSTS,
C_SPLB_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER,
C_SPLB_CLK_PERIOD_PS => C_SPLB_CLK_PERIOD_PS,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY,
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_MPLB_P2P => C_MPLB_P2P,
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
C_MPLB_CLK_PERIOD_PS => C_MPLB_CLK_PERIOD_PS
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
Soft_Reset => my_reset,
Reset_Done => open,
Soft_Stop => '0',
SWTM_DOB => (others => '0'),
SWTM_ADDRB => open,
SWTM_DIB => open,
SWTM_ENB => open,
SWTM_WEB => open,
TM2SCH_current_cpu_tid => (others => '0'),
TM2SCH_opcode => (others => '0'),
TM2SCH_data => (others => '0'),
TM2SCH_request => '0',
SCH2TM_busy => open,
SCH2TM_data => open,
SCH2TM_next_cpu_tid => open,
SCH2TM_next_tid_valid => open,
Preemption_Interrupt => open,
-- MAP USER PORTS ABOVE THIS LINE ------------------
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => sig_dev_mderr,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm
);
------------------------------------------
-- Hook up UUT MD_error to synch_out bit for Master Detected Error status monitor
------------------------------------------
SYNCH_OUT(MST_ERROR) <= sig_dev_mderr;
------------------------------------------
-- Zero out the unused synch_out bits
------------------------------------------
SYNCH_OUT(10 to 31) <= (others => '0');
------------------------------------------
-- Test bench code itself
--
-- The test bench itself can be arbitrarily complex and may include
-- hierarchy as the designer sees fit
------------------------------------------
TEST_PROCESS : process
begin
SYNCH_OUT(NOP) <= '0';
SYNCH_OUT(START) <= '0';
SYNCH_OUT(STOP) <= '0';
SYNCH_OUT(WAIT_IN) <= '0';
SYNCH_OUT(WAIT_OUT) <= '0';
SYNCH_OUT(ASSERT_IN) <= '0';
SYNCH_OUT(ASSERT_OUT) <= '0';
SYNCH_OUT(ASSIGN_IN) <= '0';
SYNCH_OUT(ASSIGN_OUT) <= '0';
SYNCH_OUT(RESET_WDT) <= '0';
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
my_reset <= '1';
-- wait for end of reset
wait until (SPLB_Rst'EVENT and SPLB_Rst = '0');
my_reset <= '0';
assert FALSE report "*** Real simulation starts here ***" severity NOTE;
-- wait for reset to be completed
wait for 200 ns;
------------------------------------------
-- Test User Logic Slave Register
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic Slave Register Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic Slave Register Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User Logic IP Master
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic IP Master Read Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master read ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
assert FALSE report "*** User Logic is doing master read transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
assert FALSE report "*** Continue User Logic IP Master Write Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master write ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
assert FALSE report "*** User Logic is doing master write transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
assert FALSE report "*** Continue the rest of User Logic IP Master Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic IP Master Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User I/Os and other features
------------------------------------------
--USER code added here to stimulate any user I/Os
wait;
end process TEST_PROCESS;
end architecture testbench;
|
------------------------------------------------------------------------------
--
-- This vhdl module is a template for creating IP testbenches using the IBM
-- BFM toolkits. It provides a fixed interface to the subsystem testbench.
--
-- DO NOT CHANGE THE entity name, architecture name, generic parameter
-- declaration or port declaration of this file. You may add components,
-- instances, constants, signals, etc. as you wish.
--
-- See IBM Bus Functional Model Toolkit User's Manual for more information
-- on the BFMs.
--
------------------------------------------------------------------------------
-- plb_scheduler_tb.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: plb_scheduler_tb.vhd
-- Version: 1.00.a
-- Description: IP testbench
-- Date: Mon Apr 6 14:20:49 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library plb_scheduler_v1_00_a;
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity plb_scheduler_tb is
------------------------------------------
-- DO NOT CHANGE THIS GENERIC DECLARATION
------------------------------------------
generic
(
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 0;
C_FAMILY : string := "virtex5";
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 32;
C_MPLB_P2P : integer := 0;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_MPLB_CLK_PERIOD_PS : integer := 10000
);
------------------------------------------
-- DO NOT CHANGE THIS PORT DECLARATION
------------------------------------------
port
(
-- PLB (v4.6) bus interface, do not add or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to C_MPLB_DWIDTH/8-1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_MPLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- BFM synchronization bus interface
SYNCH_IN : in std_logic_vector(0 to 31) := (others => '0');
SYNCH_OUT : out std_logic_vector(0 to 31) := (others => '0')
);
end entity plb_scheduler_tb;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture testbench of plb_scheduler_tb is
--USER testbench signal declarations added here as you wish
------------------------------------------
-- Signal to hook up master detected error and synch bus
------------------------------------------
signal sig_dev_mderr : std_logic;
------------------------------------------
-- Standard constants for bfl/vhdl communication
------------------------------------------
constant NOP : integer := 0;
constant START : integer := 1;
constant STOP : integer := 2;
constant WAIT_IN : integer := 3;
constant WAIT_OUT : integer := 4;
constant ASSERT_IN : integer := 5;
constant ASSERT_OUT : integer := 6;
constant ASSIGN_IN : integer := 7;
constant ASSIGN_OUT : integer := 8;
constant RESET_WDT : integer := 9;
constant MST_ERROR : integer := 30;
constant INTERRUPT : integer := 31;
signal my_reset : std_logic;
begin
------------------------------------------
-- Instance of IP under test.
-- Communication with the BFL is by using SYNCH_IN/SYNCH_OUT signals.
------------------------------------------
UUT : entity plb_scheduler_v1_00_a.plb_scheduler
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_SPLB_P2P => C_SPLB_P2P,
C_SPLB_SUPPORT_BURSTS => C_SPLB_SUPPORT_BURSTS,
C_SPLB_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER,
C_SPLB_CLK_PERIOD_PS => C_SPLB_CLK_PERIOD_PS,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY,
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_MPLB_P2P => C_MPLB_P2P,
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
C_MPLB_CLK_PERIOD_PS => C_MPLB_CLK_PERIOD_PS
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
Soft_Reset => my_reset,
Reset_Done => open,
Soft_Stop => '0',
SWTM_DOB => (others => '0'),
SWTM_ADDRB => open,
SWTM_DIB => open,
SWTM_ENB => open,
SWTM_WEB => open,
TM2SCH_current_cpu_tid => (others => '0'),
TM2SCH_opcode => (others => '0'),
TM2SCH_data => (others => '0'),
TM2SCH_request => '0',
SCH2TM_busy => open,
SCH2TM_data => open,
SCH2TM_next_cpu_tid => open,
SCH2TM_next_tid_valid => open,
Preemption_Interrupt => open,
-- MAP USER PORTS ABOVE THIS LINE ------------------
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => sig_dev_mderr,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm
);
------------------------------------------
-- Hook up UUT MD_error to synch_out bit for Master Detected Error status monitor
------------------------------------------
SYNCH_OUT(MST_ERROR) <= sig_dev_mderr;
------------------------------------------
-- Zero out the unused synch_out bits
------------------------------------------
SYNCH_OUT(10 to 31) <= (others => '0');
------------------------------------------
-- Test bench code itself
--
-- The test bench itself can be arbitrarily complex and may include
-- hierarchy as the designer sees fit
------------------------------------------
TEST_PROCESS : process
begin
SYNCH_OUT(NOP) <= '0';
SYNCH_OUT(START) <= '0';
SYNCH_OUT(STOP) <= '0';
SYNCH_OUT(WAIT_IN) <= '0';
SYNCH_OUT(WAIT_OUT) <= '0';
SYNCH_OUT(ASSERT_IN) <= '0';
SYNCH_OUT(ASSERT_OUT) <= '0';
SYNCH_OUT(ASSIGN_IN) <= '0';
SYNCH_OUT(ASSIGN_OUT) <= '0';
SYNCH_OUT(RESET_WDT) <= '0';
-- initializations
-- wait for reset to stabalize after power-up
wait for 200 ns;
my_reset <= '1';
-- wait for end of reset
wait until (SPLB_Rst'EVENT and SPLB_Rst = '0');
my_reset <= '0';
assert FALSE report "*** Real simulation starts here ***" severity NOTE;
-- wait for reset to be completed
wait for 200 ns;
------------------------------------------
-- Test User Logic Slave Register
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic Slave Register Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic Slave Register Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User Logic IP Master
------------------------------------------
-- send out start signal to begin testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '1';
assert FALSE report "*** Start User Logic IP Master Read Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(START) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master read ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
assert FALSE report "*** User Logic is doing master read transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
assert FALSE report "*** Continue User Logic IP Master Write Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait for awhile for wait_out signal to let user logic master complete master write ...
wait until (SYNCH_IN(WAIT_OUT)'EVENT and SYNCH_IN(WAIT_OUT) = '1');
assert FALSE report "*** User Logic is doing master write transaction now ***" severity NOTE;
wait for 1 us;
-- send out wait_in signal to continue testing ...
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '1';
assert FALSE report "*** Continue the rest of User Logic IP Master Test ***" severity NOTE;
wait until (SPLB_Clk'EVENT and SPLB_Clk = '1');
SYNCH_OUT(WAIT_IN) <= '0';
-- wait stop signal for end of testing ...
wait until (SYNCH_IN(STOP)'EVENT and SYNCH_IN(STOP) = '1');
assert FALSE report "*** User Logic IP Master Test Complete ***" severity NOTE;
wait for 1 us;
------------------------------------------
-- Test User I/Os and other features
------------------------------------------
--USER code added here to stimulate any user I/Os
wait;
end process TEST_PROCESS;
end architecture testbench;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : asynchronous fifo with write_flush
-------------------------------------------------------------------------------
-- Description: Asynchronous fifo for transfer of data between 2 clock domains
-- This variant has a write_flush input. A '1' on the write flush
-- will transfer the current wr_ptr_wr to the read domain as the
-- new read pointer, effectively flushing the buffer. The read
-- domain reports the completion of the flushing, and after that
-- report the wr_inhibit flag is deasserted.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gray_code_pkg.all;
entity async_fifo is
generic(
g_data_width : integer := 36;
g_depth_bits : integer := 9; -- depth = 2^depth_bits (9 == 512 words)
g_count_bits : integer := 9;
g_threshold : integer := 3;
g_storage : string := "auto" -- can also be "blockram" or
-- "distributed"
);
port (
-- write port signals (synchronized to write clock)
wr_clock : in std_logic;
wr_reset : in std_logic;
wr_en : in std_logic;
wr_din : in std_logic_vector(g_data_width-1 downto 0);
wr_flush : in std_logic := '0';
wr_count : out std_logic_vector(g_count_bits-1 downto 0);
wr_full : out std_logic;
wr_almost_full : out std_logic;
wr_error : out std_logic;
wr_inhibit : out std_logic;
-- read port signals (synchronized to read clock)
rd_clock : in std_logic;
rd_reset : in std_logic;
rd_en : in std_logic;
rd_dout : out std_logic_vector(g_data_width-1 downto 0);
rd_count : out std_logic_vector(g_count_bits-1 downto 0);
rd_empty : out std_logic;
rd_almost_empty : out std_logic;
rd_error : out std_logic
);
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of async_fifo : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of async_fifo : entity is true;
end async_fifo;
architecture rtl of async_fifo is
---------------------------------------------------------------------------
-- constants
---------------------------------------------------------------------------
constant c_depth : integer := 2 ** g_depth_bits;
constant c_count_high : integer := g_depth_bits-1;
constant c_count_low : integer := g_depth_bits-g_count_bits;
---------------------------------------------------------------------------
-- storage memory for the data
---------------------------------------------------------------------------
type t_mem is array (0 to c_depth-1)
of std_logic_vector(g_data_width-1 downto 0);
signal mem : t_mem;
---------------------------------------------------------------------------
-- synthesis attributes to for ram style
---------------------------------------------------------------------------
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of mem : signal is g_storage;
---------------------------------------------------------------------------
-- All signals (internal and external) are prefixed with rd or wr.
-- This indicates the clock-domain in which they are generated (and used,
-- except from the notable exeptions, the transfer of the pointers).
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Read and write pointers, both in both domains.
---------------------------------------------------------------------------
signal rd_rd_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_wr_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_wr_ptr_d : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_rd_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal rd_wr_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is used as the wr_rd_ptr while flushing is in progress.
signal wr_wr_ptr_flush : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is the position of the writepointer upon a flush,
-- synchronised to the read clock domain.
signal rd_wr_ptr_flush : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is a temp value to cast the std_logic_vector to a gray value.
signal rd_wr_ptr_flush_std : std_logic_vector(g_depth_bits-1 downto 0);
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_balancing : string;
attribute register_balancing of rd_wr_ptr : signal is "no";
attribute register_balancing of wr_rd_ptr : signal is "no";
-- Altera attributes
attribute dont_retime : boolean;
attribute dont_retime of rd_wr_ptr : signal is true;
attribute dont_retime of wr_rd_ptr : signal is true;
---------------------------------------------------------------------------
-- internal flags
---------------------------------------------------------------------------
signal rd_empty_i : std_logic;
signal wr_full_i : std_logic;
signal rd_en_filt : std_logic;
signal wr_en_filt : std_logic;
signal rd_count_comb : unsigned(g_depth_bits-1 downto 0);
signal wr_count_comb : unsigned(g_depth_bits-1 downto 0);
signal rd_en_decr : unsigned(g_depth_bits-1 downto 0);
signal wr_en_incr : unsigned(g_depth_bits-1 downto 0);
---------------------------------------------------------------------------
-- extra flags for the flushing mechanism
---------------------------------------------------------------------------
signal wr_do_flush : std_logic; -- do flush command in write domain
signal rd_do_flush : std_logic; -- do flush command in read domain
signal rd_flush_done : std_logic;
begin
---------------------------------------------------------------------------
-- check parameters
---------------------------------------------------------------------------
assert (g_data_width /= 0)
report "error: g_data_width may not be 0!"
severity error;
assert (g_depth_bits /= 0)
report "error: g_depth_bits may not be 0!"
severity error;
assert (g_count_bits /= 0)
report "error: g_count_bits may not be 0!"
severity error;
assert (g_count_bits <= g_depth_bits)
report "error: g_count_bits may not be greater than g_depth_bits"
severity error;
assert (g_threshold <= 2**g_depth_bits)
report "error: g_threshold is too big for this g_depth_bits"
severity error;
assert (g_threshold > 0)
report "error: g_threshold may not be smaller or equal to 0"
severity error;
---------------------------------------------------------------------------
-- filtered read and write enable
---------------------------------------------------------------------------
rd_en_filt <= rd_en and not(rd_empty_i);
wr_en_filt <= wr_en and not(wr_full_i) and not wr_flush and not wr_do_flush;
rd_en_decr <= to_unsigned(1, g_depth_bits) when rd_en_filt = '1'else
to_unsigned(0, g_depth_bits);
wr_en_incr <= to_unsigned(1, g_depth_bits) when wr_en_filt = '1'else
to_unsigned(0, g_depth_bits);
---------------------------------------------------------------------------
-- read data process
---------------------------------------------------------------------------
read : process(rd_clock)
begin
if rd_clock'event and rd_clock = '1' then
if rd_en_filt = '1' then
rd_dout <= mem(to_integer(unsigned(rd_rd_ptr)));
---------------------------------------------------------------
-- beware: to_integer(unsigned()) does not do any computations.
-- So the address is a gray value, coded as a std_locic_vector
---------------------------------------------------------------
end if;
end if;
end process;
---------------------------------------------------------------------------
-- write data process
---------------------------------------------------------------------------
write : process(wr_clock)
begin
if wr_clock'event and wr_clock = '1' then
if wr_en_filt = '1' then
mem(to_integer(unsigned(wr_wr_ptr))) <= wr_din;
---------------------------------------------------------------
-- beware: to_integer(unsigned()) does not do any computations.
-- So the address is a gray value, coded as a std_locic_vector
---------------------------------------------------------------
end if;
end if;
end process;
---------------------------------------------------------------------------
-- read pointer count process, and rd_empty generation
---------------------------------------------------------------------------
rd_count_comb <= to_unsigned(rd_wr_ptr) -
to_unsigned(rd_rd_ptr) -
rd_en_decr;
proc_rd_rd_ptr : process (rd_clock)
begin
if rising_edge(rd_clock) then
if rd_en_filt = '1' then
rd_rd_ptr <= increment(rd_rd_ptr);
end if;
rd_wr_ptr <= wr_wr_ptr_d;
rd_count <= std_logic_vector(rd_count_comb(c_count_high downto c_count_low));
if (rd_count_comb = 0) then
rd_empty_i <= '1';
else
rd_empty_i <= '0';
end if;
if (rd_count_comb <= g_threshold) then
rd_almost_empty <= '1';
else
rd_almost_empty <= '0';
end if;
if rd_empty_i = '1' and rd_en = '1' then
rd_error <= '1';
report "read error!" severity error;
else
rd_error <= '0';
end if;
-------------------------------------------------------------------
-- flush logic
-------------------------------------------------------------------
if rd_do_flush = '1' then
rd_rd_ptr <= rd_wr_ptr_flush;
rd_empty_i <= '1'; -- to prevent reading to early
end if;
-------------------------------------------------------------------
-- synchronous reset
-------------------------------------------------------------------
if rd_reset = '1' then
rd_rd_ptr <= (others => '0');
rd_count <= (others => '0');
rd_empty_i <= '1';
rd_error <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- write pointer count process, and wr_full generation
---------------------------------------------------------------------------
wr_count_comb <= to_unsigned(wr_wr_ptr) -
to_unsigned(wr_rd_ptr) +
wr_en_incr;
proc_wr_wr_ptr : process (wr_clock)
begin
if rising_edge(wr_clock) then
wr_wr_ptr_d <= wr_wr_ptr;
if wr_en_filt = '1' then
wr_wr_ptr <= increment(wr_wr_ptr);
if wr_do_flush = '0' and wr_flush = '0' then
wr_wr_ptr_flush <= increment(wr_wr_ptr);
-- this should already contain the correct value.
-- Overruled (inhibited) if wr_do_flush = '1' or
-- wr_flush = '1'
end if;
end if;
wr_count <= std_logic_vector(wr_count_comb(c_count_high downto c_count_low));
if (wr_count_comb = c_depth-1) then
wr_full_i <= '1';
else
wr_full_i <= '0';
end if;
if (wr_count_comb >= c_depth-g_threshold-1) then
wr_almost_full <= '1';
else
wr_almost_full <= '0';
end if;
if wr_do_flush = '1' or wr_flush = '1' then
wr_rd_ptr <= wr_wr_ptr_flush;
else
wr_rd_ptr <= rd_rd_ptr;
end if;
if (wr_en = '1' and
(wr_full_i = '1' or wr_do_flush = '1' or wr_flush = '1'))
then
wr_error <= '1';
report "write error!" severity error;
else
wr_error <= '0';
end if;
-------------------------------------------------------------------
-- flush logic
-------------------------------------------------------------------
if wr_flush = '1' then
wr_do_flush <= '1';
end if;
if rd_flush_done = '1' then
wr_do_flush <= '0';
end if;
-------------------------------------------------------------------
-- synchronous reset
-------------------------------------------------------------------
if wr_reset = '1' then
wr_wr_ptr <= (others => '0');
wr_wr_ptr_flush <= (others => '0');
wr_full_i <= '0';
wr_almost_full <= '0';
wr_count <= (others => '0');
wr_error <= '0';
wr_do_flush <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- fifo status output signals
---------------------------------------------------------------------------
rd_empty <= rd_empty_i;
wr_full <= wr_full_i;
wr_inhibit <= wr_full_i or wr_do_flush or wr_flush;
synchroniser_1 : entity work.synchroniser
generic map (
g_data_width => (g_depth_bits))
port map (
tx_clock => wr_clock,
tx_reset => wr_reset,
tx_push => wr_flush,
tx_data => std_logic_vector(wr_wr_ptr),
tx_done => open,
rx_clock => rd_clock,
rx_reset => rd_reset,
rx_new_data => rd_do_flush,
rx_data => rd_wr_ptr_flush_std);
rd_wr_ptr_flush <= t_gray(rd_wr_ptr_flush_std);
-- this second synchroniser is needed to make sure that the rd_rd_ptr is
-- operating normal (e.g. not making a jump) around the time that the write
-- logic starts to read the rd_rd_ptr to wr_rd_ptr
synchroniser_2 : entity work.synchroniser
generic map (
g_data_width => (1))
port map (
tx_clock => rd_clock,
tx_reset => rd_reset,
tx_push => rd_do_flush,
tx_data => "0", -- not used.
tx_done => open,
rx_clock => wr_clock,
rx_reset => wr_reset,
rx_new_data => rd_flush_done,
rx_data => open);
end rtl;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : asynchronous fifo with write_flush
-------------------------------------------------------------------------------
-- Description: Asynchronous fifo for transfer of data between 2 clock domains
-- This variant has a write_flush input. A '1' on the write flush
-- will transfer the current wr_ptr_wr to the read domain as the
-- new read pointer, effectively flushing the buffer. The read
-- domain reports the completion of the flushing, and after that
-- report the wr_inhibit flag is deasserted.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gray_code_pkg.all;
entity async_fifo is
generic(
g_data_width : integer := 36;
g_depth_bits : integer := 9; -- depth = 2^depth_bits (9 == 512 words)
g_count_bits : integer := 9;
g_threshold : integer := 3;
g_storage : string := "auto" -- can also be "blockram" or
-- "distributed"
);
port (
-- write port signals (synchronized to write clock)
wr_clock : in std_logic;
wr_reset : in std_logic;
wr_en : in std_logic;
wr_din : in std_logic_vector(g_data_width-1 downto 0);
wr_flush : in std_logic := '0';
wr_count : out std_logic_vector(g_count_bits-1 downto 0);
wr_full : out std_logic;
wr_almost_full : out std_logic;
wr_error : out std_logic;
wr_inhibit : out std_logic;
-- read port signals (synchronized to read clock)
rd_clock : in std_logic;
rd_reset : in std_logic;
rd_en : in std_logic;
rd_dout : out std_logic_vector(g_data_width-1 downto 0);
rd_count : out std_logic_vector(g_count_bits-1 downto 0);
rd_empty : out std_logic;
rd_almost_empty : out std_logic;
rd_error : out std_logic
);
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of async_fifo : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of async_fifo : entity is true;
end async_fifo;
architecture rtl of async_fifo is
---------------------------------------------------------------------------
-- constants
---------------------------------------------------------------------------
constant c_depth : integer := 2 ** g_depth_bits;
constant c_count_high : integer := g_depth_bits-1;
constant c_count_low : integer := g_depth_bits-g_count_bits;
---------------------------------------------------------------------------
-- storage memory for the data
---------------------------------------------------------------------------
type t_mem is array (0 to c_depth-1)
of std_logic_vector(g_data_width-1 downto 0);
signal mem : t_mem;
---------------------------------------------------------------------------
-- synthesis attributes to for ram style
---------------------------------------------------------------------------
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of mem : signal is g_storage;
---------------------------------------------------------------------------
-- All signals (internal and external) are prefixed with rd or wr.
-- This indicates the clock-domain in which they are generated (and used,
-- except from the notable exeptions, the transfer of the pointers).
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Read and write pointers, both in both domains.
---------------------------------------------------------------------------
signal rd_rd_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_wr_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_wr_ptr_d : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_rd_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal rd_wr_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is used as the wr_rd_ptr while flushing is in progress.
signal wr_wr_ptr_flush : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is the position of the writepointer upon a flush,
-- synchronised to the read clock domain.
signal rd_wr_ptr_flush : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is a temp value to cast the std_logic_vector to a gray value.
signal rd_wr_ptr_flush_std : std_logic_vector(g_depth_bits-1 downto 0);
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_balancing : string;
attribute register_balancing of rd_wr_ptr : signal is "no";
attribute register_balancing of wr_rd_ptr : signal is "no";
-- Altera attributes
attribute dont_retime : boolean;
attribute dont_retime of rd_wr_ptr : signal is true;
attribute dont_retime of wr_rd_ptr : signal is true;
---------------------------------------------------------------------------
-- internal flags
---------------------------------------------------------------------------
signal rd_empty_i : std_logic;
signal wr_full_i : std_logic;
signal rd_en_filt : std_logic;
signal wr_en_filt : std_logic;
signal rd_count_comb : unsigned(g_depth_bits-1 downto 0);
signal wr_count_comb : unsigned(g_depth_bits-1 downto 0);
signal rd_en_decr : unsigned(g_depth_bits-1 downto 0);
signal wr_en_incr : unsigned(g_depth_bits-1 downto 0);
---------------------------------------------------------------------------
-- extra flags for the flushing mechanism
---------------------------------------------------------------------------
signal wr_do_flush : std_logic; -- do flush command in write domain
signal rd_do_flush : std_logic; -- do flush command in read domain
signal rd_flush_done : std_logic;
begin
---------------------------------------------------------------------------
-- check parameters
---------------------------------------------------------------------------
assert (g_data_width /= 0)
report "error: g_data_width may not be 0!"
severity error;
assert (g_depth_bits /= 0)
report "error: g_depth_bits may not be 0!"
severity error;
assert (g_count_bits /= 0)
report "error: g_count_bits may not be 0!"
severity error;
assert (g_count_bits <= g_depth_bits)
report "error: g_count_bits may not be greater than g_depth_bits"
severity error;
assert (g_threshold <= 2**g_depth_bits)
report "error: g_threshold is too big for this g_depth_bits"
severity error;
assert (g_threshold > 0)
report "error: g_threshold may not be smaller or equal to 0"
severity error;
---------------------------------------------------------------------------
-- filtered read and write enable
---------------------------------------------------------------------------
rd_en_filt <= rd_en and not(rd_empty_i);
wr_en_filt <= wr_en and not(wr_full_i) and not wr_flush and not wr_do_flush;
rd_en_decr <= to_unsigned(1, g_depth_bits) when rd_en_filt = '1'else
to_unsigned(0, g_depth_bits);
wr_en_incr <= to_unsigned(1, g_depth_bits) when wr_en_filt = '1'else
to_unsigned(0, g_depth_bits);
---------------------------------------------------------------------------
-- read data process
---------------------------------------------------------------------------
read : process(rd_clock)
begin
if rd_clock'event and rd_clock = '1' then
if rd_en_filt = '1' then
rd_dout <= mem(to_integer(unsigned(rd_rd_ptr)));
---------------------------------------------------------------
-- beware: to_integer(unsigned()) does not do any computations.
-- So the address is a gray value, coded as a std_locic_vector
---------------------------------------------------------------
end if;
end if;
end process;
---------------------------------------------------------------------------
-- write data process
---------------------------------------------------------------------------
write : process(wr_clock)
begin
if wr_clock'event and wr_clock = '1' then
if wr_en_filt = '1' then
mem(to_integer(unsigned(wr_wr_ptr))) <= wr_din;
---------------------------------------------------------------
-- beware: to_integer(unsigned()) does not do any computations.
-- So the address is a gray value, coded as a std_locic_vector
---------------------------------------------------------------
end if;
end if;
end process;
---------------------------------------------------------------------------
-- read pointer count process, and rd_empty generation
---------------------------------------------------------------------------
rd_count_comb <= to_unsigned(rd_wr_ptr) -
to_unsigned(rd_rd_ptr) -
rd_en_decr;
proc_rd_rd_ptr : process (rd_clock)
begin
if rising_edge(rd_clock) then
if rd_en_filt = '1' then
rd_rd_ptr <= increment(rd_rd_ptr);
end if;
rd_wr_ptr <= wr_wr_ptr_d;
rd_count <= std_logic_vector(rd_count_comb(c_count_high downto c_count_low));
if (rd_count_comb = 0) then
rd_empty_i <= '1';
else
rd_empty_i <= '0';
end if;
if (rd_count_comb <= g_threshold) then
rd_almost_empty <= '1';
else
rd_almost_empty <= '0';
end if;
if rd_empty_i = '1' and rd_en = '1' then
rd_error <= '1';
report "read error!" severity error;
else
rd_error <= '0';
end if;
-------------------------------------------------------------------
-- flush logic
-------------------------------------------------------------------
if rd_do_flush = '1' then
rd_rd_ptr <= rd_wr_ptr_flush;
rd_empty_i <= '1'; -- to prevent reading to early
end if;
-------------------------------------------------------------------
-- synchronous reset
-------------------------------------------------------------------
if rd_reset = '1' then
rd_rd_ptr <= (others => '0');
rd_count <= (others => '0');
rd_empty_i <= '1';
rd_error <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- write pointer count process, and wr_full generation
---------------------------------------------------------------------------
wr_count_comb <= to_unsigned(wr_wr_ptr) -
to_unsigned(wr_rd_ptr) +
wr_en_incr;
proc_wr_wr_ptr : process (wr_clock)
begin
if rising_edge(wr_clock) then
wr_wr_ptr_d <= wr_wr_ptr;
if wr_en_filt = '1' then
wr_wr_ptr <= increment(wr_wr_ptr);
if wr_do_flush = '0' and wr_flush = '0' then
wr_wr_ptr_flush <= increment(wr_wr_ptr);
-- this should already contain the correct value.
-- Overruled (inhibited) if wr_do_flush = '1' or
-- wr_flush = '1'
end if;
end if;
wr_count <= std_logic_vector(wr_count_comb(c_count_high downto c_count_low));
if (wr_count_comb = c_depth-1) then
wr_full_i <= '1';
else
wr_full_i <= '0';
end if;
if (wr_count_comb >= c_depth-g_threshold-1) then
wr_almost_full <= '1';
else
wr_almost_full <= '0';
end if;
if wr_do_flush = '1' or wr_flush = '1' then
wr_rd_ptr <= wr_wr_ptr_flush;
else
wr_rd_ptr <= rd_rd_ptr;
end if;
if (wr_en = '1' and
(wr_full_i = '1' or wr_do_flush = '1' or wr_flush = '1'))
then
wr_error <= '1';
report "write error!" severity error;
else
wr_error <= '0';
end if;
-------------------------------------------------------------------
-- flush logic
-------------------------------------------------------------------
if wr_flush = '1' then
wr_do_flush <= '1';
end if;
if rd_flush_done = '1' then
wr_do_flush <= '0';
end if;
-------------------------------------------------------------------
-- synchronous reset
-------------------------------------------------------------------
if wr_reset = '1' then
wr_wr_ptr <= (others => '0');
wr_wr_ptr_flush <= (others => '0');
wr_full_i <= '0';
wr_almost_full <= '0';
wr_count <= (others => '0');
wr_error <= '0';
wr_do_flush <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- fifo status output signals
---------------------------------------------------------------------------
rd_empty <= rd_empty_i;
wr_full <= wr_full_i;
wr_inhibit <= wr_full_i or wr_do_flush or wr_flush;
synchroniser_1 : entity work.synchroniser
generic map (
g_data_width => (g_depth_bits))
port map (
tx_clock => wr_clock,
tx_reset => wr_reset,
tx_push => wr_flush,
tx_data => std_logic_vector(wr_wr_ptr),
tx_done => open,
rx_clock => rd_clock,
rx_reset => rd_reset,
rx_new_data => rd_do_flush,
rx_data => rd_wr_ptr_flush_std);
rd_wr_ptr_flush <= t_gray(rd_wr_ptr_flush_std);
-- this second synchroniser is needed to make sure that the rd_rd_ptr is
-- operating normal (e.g. not making a jump) around the time that the write
-- logic starts to read the rd_rd_ptr to wr_rd_ptr
synchroniser_2 : entity work.synchroniser
generic map (
g_data_width => (1))
port map (
tx_clock => rd_clock,
tx_reset => rd_reset,
tx_push => rd_do_flush,
tx_data => "0", -- not used.
tx_done => open,
rx_clock => wr_clock,
rx_reset => wr_reset,
rx_new_data => rd_flush_done,
rx_data => open);
end rtl;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : asynchronous fifo with write_flush
-------------------------------------------------------------------------------
-- Description: Asynchronous fifo for transfer of data between 2 clock domains
-- This variant has a write_flush input. A '1' on the write flush
-- will transfer the current wr_ptr_wr to the read domain as the
-- new read pointer, effectively flushing the buffer. The read
-- domain reports the completion of the flushing, and after that
-- report the wr_inhibit flag is deasserted.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gray_code_pkg.all;
entity async_fifo is
generic(
g_data_width : integer := 36;
g_depth_bits : integer := 9; -- depth = 2^depth_bits (9 == 512 words)
g_count_bits : integer := 9;
g_threshold : integer := 3;
g_storage : string := "auto" -- can also be "blockram" or
-- "distributed"
);
port (
-- write port signals (synchronized to write clock)
wr_clock : in std_logic;
wr_reset : in std_logic;
wr_en : in std_logic;
wr_din : in std_logic_vector(g_data_width-1 downto 0);
wr_flush : in std_logic := '0';
wr_count : out std_logic_vector(g_count_bits-1 downto 0);
wr_full : out std_logic;
wr_almost_full : out std_logic;
wr_error : out std_logic;
wr_inhibit : out std_logic;
-- read port signals (synchronized to read clock)
rd_clock : in std_logic;
rd_reset : in std_logic;
rd_en : in std_logic;
rd_dout : out std_logic_vector(g_data_width-1 downto 0);
rd_count : out std_logic_vector(g_count_bits-1 downto 0);
rd_empty : out std_logic;
rd_almost_empty : out std_logic;
rd_error : out std_logic
);
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of async_fifo : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of async_fifo : entity is true;
end async_fifo;
architecture rtl of async_fifo is
---------------------------------------------------------------------------
-- constants
---------------------------------------------------------------------------
constant c_depth : integer := 2 ** g_depth_bits;
constant c_count_high : integer := g_depth_bits-1;
constant c_count_low : integer := g_depth_bits-g_count_bits;
---------------------------------------------------------------------------
-- storage memory for the data
---------------------------------------------------------------------------
type t_mem is array (0 to c_depth-1)
of std_logic_vector(g_data_width-1 downto 0);
signal mem : t_mem;
---------------------------------------------------------------------------
-- synthesis attributes to for ram style
---------------------------------------------------------------------------
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of mem : signal is g_storage;
---------------------------------------------------------------------------
-- All signals (internal and external) are prefixed with rd or wr.
-- This indicates the clock-domain in which they are generated (and used,
-- except from the notable exeptions, the transfer of the pointers).
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Read and write pointers, both in both domains.
---------------------------------------------------------------------------
signal rd_rd_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_wr_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_wr_ptr_d : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_rd_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal rd_wr_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is used as the wr_rd_ptr while flushing is in progress.
signal wr_wr_ptr_flush : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is the position of the writepointer upon a flush,
-- synchronised to the read clock domain.
signal rd_wr_ptr_flush : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is a temp value to cast the std_logic_vector to a gray value.
signal rd_wr_ptr_flush_std : std_logic_vector(g_depth_bits-1 downto 0);
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_balancing : string;
attribute register_balancing of rd_wr_ptr : signal is "no";
attribute register_balancing of wr_rd_ptr : signal is "no";
-- Altera attributes
attribute dont_retime : boolean;
attribute dont_retime of rd_wr_ptr : signal is true;
attribute dont_retime of wr_rd_ptr : signal is true;
---------------------------------------------------------------------------
-- internal flags
---------------------------------------------------------------------------
signal rd_empty_i : std_logic;
signal wr_full_i : std_logic;
signal rd_en_filt : std_logic;
signal wr_en_filt : std_logic;
signal rd_count_comb : unsigned(g_depth_bits-1 downto 0);
signal wr_count_comb : unsigned(g_depth_bits-1 downto 0);
signal rd_en_decr : unsigned(g_depth_bits-1 downto 0);
signal wr_en_incr : unsigned(g_depth_bits-1 downto 0);
---------------------------------------------------------------------------
-- extra flags for the flushing mechanism
---------------------------------------------------------------------------
signal wr_do_flush : std_logic; -- do flush command in write domain
signal rd_do_flush : std_logic; -- do flush command in read domain
signal rd_flush_done : std_logic;
begin
---------------------------------------------------------------------------
-- check parameters
---------------------------------------------------------------------------
assert (g_data_width /= 0)
report "error: g_data_width may not be 0!"
severity error;
assert (g_depth_bits /= 0)
report "error: g_depth_bits may not be 0!"
severity error;
assert (g_count_bits /= 0)
report "error: g_count_bits may not be 0!"
severity error;
assert (g_count_bits <= g_depth_bits)
report "error: g_count_bits may not be greater than g_depth_bits"
severity error;
assert (g_threshold <= 2**g_depth_bits)
report "error: g_threshold is too big for this g_depth_bits"
severity error;
assert (g_threshold > 0)
report "error: g_threshold may not be smaller or equal to 0"
severity error;
---------------------------------------------------------------------------
-- filtered read and write enable
---------------------------------------------------------------------------
rd_en_filt <= rd_en and not(rd_empty_i);
wr_en_filt <= wr_en and not(wr_full_i) and not wr_flush and not wr_do_flush;
rd_en_decr <= to_unsigned(1, g_depth_bits) when rd_en_filt = '1'else
to_unsigned(0, g_depth_bits);
wr_en_incr <= to_unsigned(1, g_depth_bits) when wr_en_filt = '1'else
to_unsigned(0, g_depth_bits);
---------------------------------------------------------------------------
-- read data process
---------------------------------------------------------------------------
read : process(rd_clock)
begin
if rd_clock'event and rd_clock = '1' then
if rd_en_filt = '1' then
rd_dout <= mem(to_integer(unsigned(rd_rd_ptr)));
---------------------------------------------------------------
-- beware: to_integer(unsigned()) does not do any computations.
-- So the address is a gray value, coded as a std_locic_vector
---------------------------------------------------------------
end if;
end if;
end process;
---------------------------------------------------------------------------
-- write data process
---------------------------------------------------------------------------
write : process(wr_clock)
begin
if wr_clock'event and wr_clock = '1' then
if wr_en_filt = '1' then
mem(to_integer(unsigned(wr_wr_ptr))) <= wr_din;
---------------------------------------------------------------
-- beware: to_integer(unsigned()) does not do any computations.
-- So the address is a gray value, coded as a std_locic_vector
---------------------------------------------------------------
end if;
end if;
end process;
---------------------------------------------------------------------------
-- read pointer count process, and rd_empty generation
---------------------------------------------------------------------------
rd_count_comb <= to_unsigned(rd_wr_ptr) -
to_unsigned(rd_rd_ptr) -
rd_en_decr;
proc_rd_rd_ptr : process (rd_clock)
begin
if rising_edge(rd_clock) then
if rd_en_filt = '1' then
rd_rd_ptr <= increment(rd_rd_ptr);
end if;
rd_wr_ptr <= wr_wr_ptr_d;
rd_count <= std_logic_vector(rd_count_comb(c_count_high downto c_count_low));
if (rd_count_comb = 0) then
rd_empty_i <= '1';
else
rd_empty_i <= '0';
end if;
if (rd_count_comb <= g_threshold) then
rd_almost_empty <= '1';
else
rd_almost_empty <= '0';
end if;
if rd_empty_i = '1' and rd_en = '1' then
rd_error <= '1';
report "read error!" severity error;
else
rd_error <= '0';
end if;
-------------------------------------------------------------------
-- flush logic
-------------------------------------------------------------------
if rd_do_flush = '1' then
rd_rd_ptr <= rd_wr_ptr_flush;
rd_empty_i <= '1'; -- to prevent reading to early
end if;
-------------------------------------------------------------------
-- synchronous reset
-------------------------------------------------------------------
if rd_reset = '1' then
rd_rd_ptr <= (others => '0');
rd_count <= (others => '0');
rd_empty_i <= '1';
rd_error <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- write pointer count process, and wr_full generation
---------------------------------------------------------------------------
wr_count_comb <= to_unsigned(wr_wr_ptr) -
to_unsigned(wr_rd_ptr) +
wr_en_incr;
proc_wr_wr_ptr : process (wr_clock)
begin
if rising_edge(wr_clock) then
wr_wr_ptr_d <= wr_wr_ptr;
if wr_en_filt = '1' then
wr_wr_ptr <= increment(wr_wr_ptr);
if wr_do_flush = '0' and wr_flush = '0' then
wr_wr_ptr_flush <= increment(wr_wr_ptr);
-- this should already contain the correct value.
-- Overruled (inhibited) if wr_do_flush = '1' or
-- wr_flush = '1'
end if;
end if;
wr_count <= std_logic_vector(wr_count_comb(c_count_high downto c_count_low));
if (wr_count_comb = c_depth-1) then
wr_full_i <= '1';
else
wr_full_i <= '0';
end if;
if (wr_count_comb >= c_depth-g_threshold-1) then
wr_almost_full <= '1';
else
wr_almost_full <= '0';
end if;
if wr_do_flush = '1' or wr_flush = '1' then
wr_rd_ptr <= wr_wr_ptr_flush;
else
wr_rd_ptr <= rd_rd_ptr;
end if;
if (wr_en = '1' and
(wr_full_i = '1' or wr_do_flush = '1' or wr_flush = '1'))
then
wr_error <= '1';
report "write error!" severity error;
else
wr_error <= '0';
end if;
-------------------------------------------------------------------
-- flush logic
-------------------------------------------------------------------
if wr_flush = '1' then
wr_do_flush <= '1';
end if;
if rd_flush_done = '1' then
wr_do_flush <= '0';
end if;
-------------------------------------------------------------------
-- synchronous reset
-------------------------------------------------------------------
if wr_reset = '1' then
wr_wr_ptr <= (others => '0');
wr_wr_ptr_flush <= (others => '0');
wr_full_i <= '0';
wr_almost_full <= '0';
wr_count <= (others => '0');
wr_error <= '0';
wr_do_flush <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- fifo status output signals
---------------------------------------------------------------------------
rd_empty <= rd_empty_i;
wr_full <= wr_full_i;
wr_inhibit <= wr_full_i or wr_do_flush or wr_flush;
synchroniser_1 : entity work.synchroniser
generic map (
g_data_width => (g_depth_bits))
port map (
tx_clock => wr_clock,
tx_reset => wr_reset,
tx_push => wr_flush,
tx_data => std_logic_vector(wr_wr_ptr),
tx_done => open,
rx_clock => rd_clock,
rx_reset => rd_reset,
rx_new_data => rd_do_flush,
rx_data => rd_wr_ptr_flush_std);
rd_wr_ptr_flush <= t_gray(rd_wr_ptr_flush_std);
-- this second synchroniser is needed to make sure that the rd_rd_ptr is
-- operating normal (e.g. not making a jump) around the time that the write
-- logic starts to read the rd_rd_ptr to wr_rd_ptr
synchroniser_2 : entity work.synchroniser
generic map (
g_data_width => (1))
port map (
tx_clock => rd_clock,
tx_reset => rd_reset,
tx_push => rd_do_flush,
tx_data => "0", -- not used.
tx_done => open,
rx_clock => wr_clock,
rx_reset => wr_reset,
rx_new_data => rd_flush_done,
rx_data => open);
end rtl;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : asynchronous fifo with write_flush
-------------------------------------------------------------------------------
-- Description: Asynchronous fifo for transfer of data between 2 clock domains
-- This variant has a write_flush input. A '1' on the write flush
-- will transfer the current wr_ptr_wr to the read domain as the
-- new read pointer, effectively flushing the buffer. The read
-- domain reports the completion of the flushing, and after that
-- report the wr_inhibit flag is deasserted.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gray_code_pkg.all;
entity async_fifo is
generic(
g_data_width : integer := 36;
g_depth_bits : integer := 9; -- depth = 2^depth_bits (9 == 512 words)
g_count_bits : integer := 9;
g_threshold : integer := 3;
g_storage : string := "auto" -- can also be "blockram" or
-- "distributed"
);
port (
-- write port signals (synchronized to write clock)
wr_clock : in std_logic;
wr_reset : in std_logic;
wr_en : in std_logic;
wr_din : in std_logic_vector(g_data_width-1 downto 0);
wr_flush : in std_logic := '0';
wr_count : out std_logic_vector(g_count_bits-1 downto 0);
wr_full : out std_logic;
wr_almost_full : out std_logic;
wr_error : out std_logic;
wr_inhibit : out std_logic;
-- read port signals (synchronized to read clock)
rd_clock : in std_logic;
rd_reset : in std_logic;
rd_en : in std_logic;
rd_dout : out std_logic_vector(g_data_width-1 downto 0);
rd_count : out std_logic_vector(g_count_bits-1 downto 0);
rd_empty : out std_logic;
rd_almost_empty : out std_logic;
rd_error : out std_logic
);
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of async_fifo : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of async_fifo : entity is true;
end async_fifo;
architecture rtl of async_fifo is
---------------------------------------------------------------------------
-- constants
---------------------------------------------------------------------------
constant c_depth : integer := 2 ** g_depth_bits;
constant c_count_high : integer := g_depth_bits-1;
constant c_count_low : integer := g_depth_bits-g_count_bits;
---------------------------------------------------------------------------
-- storage memory for the data
---------------------------------------------------------------------------
type t_mem is array (0 to c_depth-1)
of std_logic_vector(g_data_width-1 downto 0);
signal mem : t_mem;
---------------------------------------------------------------------------
-- synthesis attributes to for ram style
---------------------------------------------------------------------------
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of mem : signal is g_storage;
---------------------------------------------------------------------------
-- All signals (internal and external) are prefixed with rd or wr.
-- This indicates the clock-domain in which they are generated (and used,
-- except from the notable exeptions, the transfer of the pointers).
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Read and write pointers, both in both domains.
---------------------------------------------------------------------------
signal rd_rd_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_wr_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_wr_ptr_d : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_rd_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal rd_wr_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is used as the wr_rd_ptr while flushing is in progress.
signal wr_wr_ptr_flush : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is the position of the writepointer upon a flush,
-- synchronised to the read clock domain.
signal rd_wr_ptr_flush : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is a temp value to cast the std_logic_vector to a gray value.
signal rd_wr_ptr_flush_std : std_logic_vector(g_depth_bits-1 downto 0);
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_balancing : string;
attribute register_balancing of rd_wr_ptr : signal is "no";
attribute register_balancing of wr_rd_ptr : signal is "no";
-- Altera attributes
attribute dont_retime : boolean;
attribute dont_retime of rd_wr_ptr : signal is true;
attribute dont_retime of wr_rd_ptr : signal is true;
---------------------------------------------------------------------------
-- internal flags
---------------------------------------------------------------------------
signal rd_empty_i : std_logic;
signal wr_full_i : std_logic;
signal rd_en_filt : std_logic;
signal wr_en_filt : std_logic;
signal rd_count_comb : unsigned(g_depth_bits-1 downto 0);
signal wr_count_comb : unsigned(g_depth_bits-1 downto 0);
signal rd_en_decr : unsigned(g_depth_bits-1 downto 0);
signal wr_en_incr : unsigned(g_depth_bits-1 downto 0);
---------------------------------------------------------------------------
-- extra flags for the flushing mechanism
---------------------------------------------------------------------------
signal wr_do_flush : std_logic; -- do flush command in write domain
signal rd_do_flush : std_logic; -- do flush command in read domain
signal rd_flush_done : std_logic;
begin
---------------------------------------------------------------------------
-- check parameters
---------------------------------------------------------------------------
assert (g_data_width /= 0)
report "error: g_data_width may not be 0!"
severity error;
assert (g_depth_bits /= 0)
report "error: g_depth_bits may not be 0!"
severity error;
assert (g_count_bits /= 0)
report "error: g_count_bits may not be 0!"
severity error;
assert (g_count_bits <= g_depth_bits)
report "error: g_count_bits may not be greater than g_depth_bits"
severity error;
assert (g_threshold <= 2**g_depth_bits)
report "error: g_threshold is too big for this g_depth_bits"
severity error;
assert (g_threshold > 0)
report "error: g_threshold may not be smaller or equal to 0"
severity error;
---------------------------------------------------------------------------
-- filtered read and write enable
---------------------------------------------------------------------------
rd_en_filt <= rd_en and not(rd_empty_i);
wr_en_filt <= wr_en and not(wr_full_i) and not wr_flush and not wr_do_flush;
rd_en_decr <= to_unsigned(1, g_depth_bits) when rd_en_filt = '1'else
to_unsigned(0, g_depth_bits);
wr_en_incr <= to_unsigned(1, g_depth_bits) when wr_en_filt = '1'else
to_unsigned(0, g_depth_bits);
---------------------------------------------------------------------------
-- read data process
---------------------------------------------------------------------------
read : process(rd_clock)
begin
if rd_clock'event and rd_clock = '1' then
if rd_en_filt = '1' then
rd_dout <= mem(to_integer(unsigned(rd_rd_ptr)));
---------------------------------------------------------------
-- beware: to_integer(unsigned()) does not do any computations.
-- So the address is a gray value, coded as a std_locic_vector
---------------------------------------------------------------
end if;
end if;
end process;
---------------------------------------------------------------------------
-- write data process
---------------------------------------------------------------------------
write : process(wr_clock)
begin
if wr_clock'event and wr_clock = '1' then
if wr_en_filt = '1' then
mem(to_integer(unsigned(wr_wr_ptr))) <= wr_din;
---------------------------------------------------------------
-- beware: to_integer(unsigned()) does not do any computations.
-- So the address is a gray value, coded as a std_locic_vector
---------------------------------------------------------------
end if;
end if;
end process;
---------------------------------------------------------------------------
-- read pointer count process, and rd_empty generation
---------------------------------------------------------------------------
rd_count_comb <= to_unsigned(rd_wr_ptr) -
to_unsigned(rd_rd_ptr) -
rd_en_decr;
proc_rd_rd_ptr : process (rd_clock)
begin
if rising_edge(rd_clock) then
if rd_en_filt = '1' then
rd_rd_ptr <= increment(rd_rd_ptr);
end if;
rd_wr_ptr <= wr_wr_ptr_d;
rd_count <= std_logic_vector(rd_count_comb(c_count_high downto c_count_low));
if (rd_count_comb = 0) then
rd_empty_i <= '1';
else
rd_empty_i <= '0';
end if;
if (rd_count_comb <= g_threshold) then
rd_almost_empty <= '1';
else
rd_almost_empty <= '0';
end if;
if rd_empty_i = '1' and rd_en = '1' then
rd_error <= '1';
report "read error!" severity error;
else
rd_error <= '0';
end if;
-------------------------------------------------------------------
-- flush logic
-------------------------------------------------------------------
if rd_do_flush = '1' then
rd_rd_ptr <= rd_wr_ptr_flush;
rd_empty_i <= '1'; -- to prevent reading to early
end if;
-------------------------------------------------------------------
-- synchronous reset
-------------------------------------------------------------------
if rd_reset = '1' then
rd_rd_ptr <= (others => '0');
rd_count <= (others => '0');
rd_empty_i <= '1';
rd_error <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- write pointer count process, and wr_full generation
---------------------------------------------------------------------------
wr_count_comb <= to_unsigned(wr_wr_ptr) -
to_unsigned(wr_rd_ptr) +
wr_en_incr;
proc_wr_wr_ptr : process (wr_clock)
begin
if rising_edge(wr_clock) then
wr_wr_ptr_d <= wr_wr_ptr;
if wr_en_filt = '1' then
wr_wr_ptr <= increment(wr_wr_ptr);
if wr_do_flush = '0' and wr_flush = '0' then
wr_wr_ptr_flush <= increment(wr_wr_ptr);
-- this should already contain the correct value.
-- Overruled (inhibited) if wr_do_flush = '1' or
-- wr_flush = '1'
end if;
end if;
wr_count <= std_logic_vector(wr_count_comb(c_count_high downto c_count_low));
if (wr_count_comb = c_depth-1) then
wr_full_i <= '1';
else
wr_full_i <= '0';
end if;
if (wr_count_comb >= c_depth-g_threshold-1) then
wr_almost_full <= '1';
else
wr_almost_full <= '0';
end if;
if wr_do_flush = '1' or wr_flush = '1' then
wr_rd_ptr <= wr_wr_ptr_flush;
else
wr_rd_ptr <= rd_rd_ptr;
end if;
if (wr_en = '1' and
(wr_full_i = '1' or wr_do_flush = '1' or wr_flush = '1'))
then
wr_error <= '1';
report "write error!" severity error;
else
wr_error <= '0';
end if;
-------------------------------------------------------------------
-- flush logic
-------------------------------------------------------------------
if wr_flush = '1' then
wr_do_flush <= '1';
end if;
if rd_flush_done = '1' then
wr_do_flush <= '0';
end if;
-------------------------------------------------------------------
-- synchronous reset
-------------------------------------------------------------------
if wr_reset = '1' then
wr_wr_ptr <= (others => '0');
wr_wr_ptr_flush <= (others => '0');
wr_full_i <= '0';
wr_almost_full <= '0';
wr_count <= (others => '0');
wr_error <= '0';
wr_do_flush <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- fifo status output signals
---------------------------------------------------------------------------
rd_empty <= rd_empty_i;
wr_full <= wr_full_i;
wr_inhibit <= wr_full_i or wr_do_flush or wr_flush;
synchroniser_1 : entity work.synchroniser
generic map (
g_data_width => (g_depth_bits))
port map (
tx_clock => wr_clock,
tx_reset => wr_reset,
tx_push => wr_flush,
tx_data => std_logic_vector(wr_wr_ptr),
tx_done => open,
rx_clock => rd_clock,
rx_reset => rd_reset,
rx_new_data => rd_do_flush,
rx_data => rd_wr_ptr_flush_std);
rd_wr_ptr_flush <= t_gray(rd_wr_ptr_flush_std);
-- this second synchroniser is needed to make sure that the rd_rd_ptr is
-- operating normal (e.g. not making a jump) around the time that the write
-- logic starts to read the rd_rd_ptr to wr_rd_ptr
synchroniser_2 : entity work.synchroniser
generic map (
g_data_width => (1))
port map (
tx_clock => rd_clock,
tx_reset => rd_reset,
tx_push => rd_do_flush,
tx_data => "0", -- not used.
tx_done => open,
rx_clock => wr_clock,
rx_reset => wr_reset,
rx_new_data => rd_flush_done,
rx_data => open);
end rtl;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : asynchronous fifo with write_flush
-------------------------------------------------------------------------------
-- Description: Asynchronous fifo for transfer of data between 2 clock domains
-- This variant has a write_flush input. A '1' on the write flush
-- will transfer the current wr_ptr_wr to the read domain as the
-- new read pointer, effectively flushing the buffer. The read
-- domain reports the completion of the flushing, and after that
-- report the wr_inhibit flag is deasserted.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gray_code_pkg.all;
entity async_fifo is
generic(
g_data_width : integer := 36;
g_depth_bits : integer := 9; -- depth = 2^depth_bits (9 == 512 words)
g_count_bits : integer := 9;
g_threshold : integer := 3;
g_storage : string := "auto" -- can also be "blockram" or
-- "distributed"
);
port (
-- write port signals (synchronized to write clock)
wr_clock : in std_logic;
wr_reset : in std_logic;
wr_en : in std_logic;
wr_din : in std_logic_vector(g_data_width-1 downto 0);
wr_flush : in std_logic := '0';
wr_count : out std_logic_vector(g_count_bits-1 downto 0);
wr_full : out std_logic;
wr_almost_full : out std_logic;
wr_error : out std_logic;
wr_inhibit : out std_logic;
-- read port signals (synchronized to read clock)
rd_clock : in std_logic;
rd_reset : in std_logic;
rd_en : in std_logic;
rd_dout : out std_logic_vector(g_data_width-1 downto 0);
rd_count : out std_logic_vector(g_count_bits-1 downto 0);
rd_empty : out std_logic;
rd_almost_empty : out std_logic;
rd_error : out std_logic
);
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of async_fifo : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of async_fifo : entity is true;
end async_fifo;
architecture rtl of async_fifo is
---------------------------------------------------------------------------
-- constants
---------------------------------------------------------------------------
constant c_depth : integer := 2 ** g_depth_bits;
constant c_count_high : integer := g_depth_bits-1;
constant c_count_low : integer := g_depth_bits-g_count_bits;
---------------------------------------------------------------------------
-- storage memory for the data
---------------------------------------------------------------------------
type t_mem is array (0 to c_depth-1)
of std_logic_vector(g_data_width-1 downto 0);
signal mem : t_mem;
---------------------------------------------------------------------------
-- synthesis attributes to for ram style
---------------------------------------------------------------------------
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of mem : signal is g_storage;
---------------------------------------------------------------------------
-- All signals (internal and external) are prefixed with rd or wr.
-- This indicates the clock-domain in which they are generated (and used,
-- except from the notable exeptions, the transfer of the pointers).
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Read and write pointers, both in both domains.
---------------------------------------------------------------------------
signal rd_rd_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_wr_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_wr_ptr_d : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal wr_rd_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
signal rd_wr_ptr : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is used as the wr_rd_ptr while flushing is in progress.
signal wr_wr_ptr_flush : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is the position of the writepointer upon a flush,
-- synchronised to the read clock domain.
signal rd_wr_ptr_flush : t_gray(g_depth_bits-1 downto 0) := (others => '0');
-- this value is a temp value to cast the std_logic_vector to a gray value.
signal rd_wr_ptr_flush_std : std_logic_vector(g_depth_bits-1 downto 0);
---------------------------------------------------------------------------
-- synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_balancing : string;
attribute register_balancing of rd_wr_ptr : signal is "no";
attribute register_balancing of wr_rd_ptr : signal is "no";
-- Altera attributes
attribute dont_retime : boolean;
attribute dont_retime of rd_wr_ptr : signal is true;
attribute dont_retime of wr_rd_ptr : signal is true;
---------------------------------------------------------------------------
-- internal flags
---------------------------------------------------------------------------
signal rd_empty_i : std_logic;
signal wr_full_i : std_logic;
signal rd_en_filt : std_logic;
signal wr_en_filt : std_logic;
signal rd_count_comb : unsigned(g_depth_bits-1 downto 0);
signal wr_count_comb : unsigned(g_depth_bits-1 downto 0);
signal rd_en_decr : unsigned(g_depth_bits-1 downto 0);
signal wr_en_incr : unsigned(g_depth_bits-1 downto 0);
---------------------------------------------------------------------------
-- extra flags for the flushing mechanism
---------------------------------------------------------------------------
signal wr_do_flush : std_logic; -- do flush command in write domain
signal rd_do_flush : std_logic; -- do flush command in read domain
signal rd_flush_done : std_logic;
begin
---------------------------------------------------------------------------
-- check parameters
---------------------------------------------------------------------------
assert (g_data_width /= 0)
report "error: g_data_width may not be 0!"
severity error;
assert (g_depth_bits /= 0)
report "error: g_depth_bits may not be 0!"
severity error;
assert (g_count_bits /= 0)
report "error: g_count_bits may not be 0!"
severity error;
assert (g_count_bits <= g_depth_bits)
report "error: g_count_bits may not be greater than g_depth_bits"
severity error;
assert (g_threshold <= 2**g_depth_bits)
report "error: g_threshold is too big for this g_depth_bits"
severity error;
assert (g_threshold > 0)
report "error: g_threshold may not be smaller or equal to 0"
severity error;
---------------------------------------------------------------------------
-- filtered read and write enable
---------------------------------------------------------------------------
rd_en_filt <= rd_en and not(rd_empty_i);
wr_en_filt <= wr_en and not(wr_full_i) and not wr_flush and not wr_do_flush;
rd_en_decr <= to_unsigned(1, g_depth_bits) when rd_en_filt = '1'else
to_unsigned(0, g_depth_bits);
wr_en_incr <= to_unsigned(1, g_depth_bits) when wr_en_filt = '1'else
to_unsigned(0, g_depth_bits);
---------------------------------------------------------------------------
-- read data process
---------------------------------------------------------------------------
read : process(rd_clock)
begin
if rd_clock'event and rd_clock = '1' then
if rd_en_filt = '1' then
rd_dout <= mem(to_integer(unsigned(rd_rd_ptr)));
---------------------------------------------------------------
-- beware: to_integer(unsigned()) does not do any computations.
-- So the address is a gray value, coded as a std_locic_vector
---------------------------------------------------------------
end if;
end if;
end process;
---------------------------------------------------------------------------
-- write data process
---------------------------------------------------------------------------
write : process(wr_clock)
begin
if wr_clock'event and wr_clock = '1' then
if wr_en_filt = '1' then
mem(to_integer(unsigned(wr_wr_ptr))) <= wr_din;
---------------------------------------------------------------
-- beware: to_integer(unsigned()) does not do any computations.
-- So the address is a gray value, coded as a std_locic_vector
---------------------------------------------------------------
end if;
end if;
end process;
---------------------------------------------------------------------------
-- read pointer count process, and rd_empty generation
---------------------------------------------------------------------------
rd_count_comb <= to_unsigned(rd_wr_ptr) -
to_unsigned(rd_rd_ptr) -
rd_en_decr;
proc_rd_rd_ptr : process (rd_clock)
begin
if rising_edge(rd_clock) then
if rd_en_filt = '1' then
rd_rd_ptr <= increment(rd_rd_ptr);
end if;
rd_wr_ptr <= wr_wr_ptr_d;
rd_count <= std_logic_vector(rd_count_comb(c_count_high downto c_count_low));
if (rd_count_comb = 0) then
rd_empty_i <= '1';
else
rd_empty_i <= '0';
end if;
if (rd_count_comb <= g_threshold) then
rd_almost_empty <= '1';
else
rd_almost_empty <= '0';
end if;
if rd_empty_i = '1' and rd_en = '1' then
rd_error <= '1';
report "read error!" severity error;
else
rd_error <= '0';
end if;
-------------------------------------------------------------------
-- flush logic
-------------------------------------------------------------------
if rd_do_flush = '1' then
rd_rd_ptr <= rd_wr_ptr_flush;
rd_empty_i <= '1'; -- to prevent reading to early
end if;
-------------------------------------------------------------------
-- synchronous reset
-------------------------------------------------------------------
if rd_reset = '1' then
rd_rd_ptr <= (others => '0');
rd_count <= (others => '0');
rd_empty_i <= '1';
rd_error <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- write pointer count process, and wr_full generation
---------------------------------------------------------------------------
wr_count_comb <= to_unsigned(wr_wr_ptr) -
to_unsigned(wr_rd_ptr) +
wr_en_incr;
proc_wr_wr_ptr : process (wr_clock)
begin
if rising_edge(wr_clock) then
wr_wr_ptr_d <= wr_wr_ptr;
if wr_en_filt = '1' then
wr_wr_ptr <= increment(wr_wr_ptr);
if wr_do_flush = '0' and wr_flush = '0' then
wr_wr_ptr_flush <= increment(wr_wr_ptr);
-- this should already contain the correct value.
-- Overruled (inhibited) if wr_do_flush = '1' or
-- wr_flush = '1'
end if;
end if;
wr_count <= std_logic_vector(wr_count_comb(c_count_high downto c_count_low));
if (wr_count_comb = c_depth-1) then
wr_full_i <= '1';
else
wr_full_i <= '0';
end if;
if (wr_count_comb >= c_depth-g_threshold-1) then
wr_almost_full <= '1';
else
wr_almost_full <= '0';
end if;
if wr_do_flush = '1' or wr_flush = '1' then
wr_rd_ptr <= wr_wr_ptr_flush;
else
wr_rd_ptr <= rd_rd_ptr;
end if;
if (wr_en = '1' and
(wr_full_i = '1' or wr_do_flush = '1' or wr_flush = '1'))
then
wr_error <= '1';
report "write error!" severity error;
else
wr_error <= '0';
end if;
-------------------------------------------------------------------
-- flush logic
-------------------------------------------------------------------
if wr_flush = '1' then
wr_do_flush <= '1';
end if;
if rd_flush_done = '1' then
wr_do_flush <= '0';
end if;
-------------------------------------------------------------------
-- synchronous reset
-------------------------------------------------------------------
if wr_reset = '1' then
wr_wr_ptr <= (others => '0');
wr_wr_ptr_flush <= (others => '0');
wr_full_i <= '0';
wr_almost_full <= '0';
wr_count <= (others => '0');
wr_error <= '0';
wr_do_flush <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------
-- fifo status output signals
---------------------------------------------------------------------------
rd_empty <= rd_empty_i;
wr_full <= wr_full_i;
wr_inhibit <= wr_full_i or wr_do_flush or wr_flush;
synchroniser_1 : entity work.synchroniser
generic map (
g_data_width => (g_depth_bits))
port map (
tx_clock => wr_clock,
tx_reset => wr_reset,
tx_push => wr_flush,
tx_data => std_logic_vector(wr_wr_ptr),
tx_done => open,
rx_clock => rd_clock,
rx_reset => rd_reset,
rx_new_data => rd_do_flush,
rx_data => rd_wr_ptr_flush_std);
rd_wr_ptr_flush <= t_gray(rd_wr_ptr_flush_std);
-- this second synchroniser is needed to make sure that the rd_rd_ptr is
-- operating normal (e.g. not making a jump) around the time that the write
-- logic starts to read the rd_rd_ptr to wr_rd_ptr
synchroniser_2 : entity work.synchroniser
generic map (
g_data_width => (1))
port map (
tx_clock => rd_clock,
tx_reset => rd_reset,
tx_push => rd_do_flush,
tx_data => "0", -- not used.
tx_done => open,
rx_clock => wr_clock,
rx_reset => wr_reset,
rx_new_data => rd_flush_done,
rx_data => open);
end rtl;
|
library verilog;
use verilog.vl_types.all;
entity select8_8 is
port(
in1 : in vl_logic_vector(7 downto 0);
in2 : in vl_logic_vector(7 downto 0);
in3 : in vl_logic_vector(7 downto 0);
in4 : in vl_logic_vector(7 downto 0);
in5 : in vl_logic_vector(7 downto 0);
in6 : in vl_logic_vector(7 downto 0);
in7 : in vl_logic_vector(7 downto 0);
in8 : in vl_logic_vector(7 downto 0);
choose : in vl_logic_vector(2 downto 0);
\out\ : out vl_logic_vector(7 downto 0)
);
end select8_8;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis VIP AXISTREAM Library : axistream_bfm_pkg
--
-- Description : See library quick reference (under 'doc') and README-file(s).
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--========================================================================================================================
--========================================================================================================================
package axistream_bfm_pkg is
--========================================================================================================================
-- Types and constants for AXISTREAM_BFM
--========================================================================================================================
constant C_SCOPE : string := "AXISTREAM_BFM";
--========================================================================================================================
-- C_MAX_*_BITS : Maximum number of bits per data word supported by the BFM.
-- These constant can be increased as needed.
constant C_MAX_TUSER_BITS : positive := 8;
constant C_MAX_TSTRB_BITS : positive := 32; -- Must be large enough for number of data bytes per transfer, C_MAX_TSTRB_BITS >= tdata/8
constant C_MAX_TID_BITS : positive := 8; -- Recommended maximum in protocol specification (ARM IHI0051A)
constant C_MAX_TDEST_BITS : positive := 4; -- Recommended maximum in protocol specification (ARM IHI0051A)
constant C_RANDOM : integer := -1;
constant C_MULTIPLE_RANDOM : integer := -2;
type t_user_array is array(natural range <>) of std_logic_vector(C_MAX_TUSER_BITS-1 downto 0);
type t_strb_array is array(natural range <>) of std_logic_vector(C_MAX_TSTRB_BITS-1 downto 0);
type t_id_array is array(natural range <>) of std_logic_vector(C_MAX_TID_BITS-1 downto 0);
type t_dest_array is array(natural range <>) of std_logic_vector(C_MAX_TDEST_BITS-1 downto 0);
--========================================================================================================================
-- Interface record for BFM signals
type t_axistream_if is record
tdata : std_logic_vector; -- Data. Width is constrained when the procedure is called
tkeep : std_logic_vector; -- One valid-bit per data byte
tuser : std_logic_vector; -- User sideband data
tvalid : std_logic; -- Data valid
tlast : std_logic; -- Active high during last data word in packet.
tready : std_logic; -- Backpressure
tstrb : std_logic_vector; -- Treated as sideband data by BFM: tstrb does not affect tdata
tid : std_logic_vector; -- Treated as sideband data by BFM
tdest : std_logic_vector; -- Treated as sideband data by BFM
end record;
-- Configuration record to be assigned in the test harness.
type t_axistream_bfm_config is record
-- Common
max_wait_cycles : integer; -- Used for setting the maximum cycles to wait before an alert is issued when waiting for ready or valid signals from the DUT.
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
clock_period : time; -- Period of the clock signal.
clock_period_margin : time; -- Input clock period margin to specified clock_period
clock_margin_severity : t_alert_level; -- The above margin will have this severity
setup_time : time; -- Setup time for generated signals, set to clock_period/4
hold_time : time; -- Hold time for generated signals, set to clock_period/4
bfm_sync : t_bfm_sync; -- Synchronisation of the BFM procedures, i.e. using clock signals, using setup_time and hold_time.
match_strictness : t_match_strictness; -- Matching strictness for std_logic values in check procedures.
byte_endianness : t_byte_endianness; -- Byte ordering from left (big-endian) or right (little-endian)
-- config for axistream_transmit()
valid_low_at_word_num : integer; -- Word index where the Source BFM shall deassert valid
valid_low_multiple_random_prob : real range 0.0 to 1.0; -- Probability of how often valid shall be deasserted when using C_MULTIPLE_RANDOM
valid_low_duration : integer; -- Number of clock cycles to deassert valid
valid_low_max_random_duration : integer; -- Maximum number of clock cycles to deassert valid when using C_RANDOM
-- config for axistream_receive()
check_packet_length : boolean; -- When true, receive() will check that last is set at data_array'high
protocol_error_severity : t_alert_level; -- severity if protocol errors are detected by axistream_receive()
ready_low_at_word_num : integer; -- Word index where the Sink BFM shall deassert ready
ready_low_multiple_random_prob : real range 0.0 to 1.0; -- Probability of how often ready shall be deasserted when using C_MULTIPLE_RANDOM
ready_low_duration : integer; -- Number of clock cycles to deassert ready
ready_low_max_random_duration : integer; -- Maximum number of clock cycles to deassert ready when using C_RANDOM
ready_default_value : std_logic; -- Which value the BFM shall set ready to between accesses.
-- Common
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the BFM
end record;
-- Define the default value for the BFM config
constant C_AXISTREAM_BFM_CONFIG_DEFAULT : t_axistream_bfm_config := (
max_wait_cycles => 100,
max_wait_cycles_severity => ERROR,
clock_period => -1 ns,
clock_period_margin => 0 ns,
clock_margin_severity => TB_ERROR,
setup_time => -1 ns,
hold_time => -1 ns,
bfm_sync => SYNC_ON_CLOCK_ONLY,
match_strictness => MATCH_EXACT,
byte_endianness => LOWER_BYTE_LEFT,
valid_low_at_word_num => 0,
valid_low_multiple_random_prob => 0.5,
valid_low_duration => 0,
valid_low_max_random_duration => 5,
check_packet_length => false,
protocol_error_severity => ERROR,
ready_low_at_word_num => 0,
ready_low_multiple_random_prob => 0.5,
ready_low_duration => 0,
ready_low_max_random_duration => 5,
ready_default_value => '0',
id_for_bfm => ID_BFM
);
--========================================================================================================================
-- BFM procedures
--========================================================================================================================
-- - This function returns an AXI Stream interface with initialized signals.
-- - All input signals are initialized to 0
-- - All output signals are initialized to Z
function init_axistream_if_signals(
is_master : boolean; -- When true, this BFM drives data signals
data_width : natural;
user_width : natural;
id_width : natural;
dest_width : natural;
config : t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) return t_axistream_if;
--------------------------------------------------------
--
-- AXIStream Transmit
--
--------------------------------------------------------
--
-- Source: BFM
-- Sink: DUT
--¨
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overloaded version without records
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_transmit (
constant data_array : in t_slv_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default strb_array, id_array, dest_array
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default user_array, strb_array, id_array, dest_array
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_transmit (
constant data_array : in t_slv_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
--------------------------------------------------------
--
-- AXIStream Receive
--
--------------------------------------------------------
--
-- Source: DUT
-- Sink: BFM
--
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_receive_bytes (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
procedure axistream_receive (
variable data_array : inout t_slv_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
-- Overloaded version without records
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_receive_bytes (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
-- Overloaded version without records
procedure axistream_receive (
variable data_array : inout t_slv_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
);
--------------------------------------------------------
--
-- AXIStream Expect
--
--------------------------------------------------------
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overloaded version without records
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default strb_array, id_array, dest_array
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array;
constant exp_user_array : in t_user_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_expect (
constant exp_data_array : in t_slv_array;
constant exp_user_array : in t_user_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_expect (
constant exp_data_array : in std_logic_vector;
constant exp_user_array : in t_user_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- Overload for default user_array, strb_array, id_array, dest_array
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- t_slv_array overload
procedure axistream_expect (
constant exp_data_array : in t_slv_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
-- std_logic_vector overload
procedure axistream_expect (
constant exp_data_array : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
);
end package axistream_bfm_pkg;
--========================================================================================================================
--========================================================================================================================
package body axistream_bfm_pkg is
function init_axistream_if_signals(
is_master : boolean; -- When true, this BFM drives data signals
data_width : natural;
user_width : natural;
id_width : natural;
dest_width : natural;
config : t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) return t_axistream_if is
variable init_if : t_axistream_if(tdata(data_width-1 downto 0),
tkeep(data_width/8-1 downto 0),
tuser(user_width-1 downto 0),
tstrb(data_width/8-1 downto 0),
tid (id_width-1 downto 0),
tdest(dest_width-1 downto 0)
);
begin
if is_master then
-- from slave to master
init_if.tready := 'Z';
-- from master to slave
init_if.tvalid := '0';
init_if.tdata := (init_if.tdata'range => '0');
init_if.tkeep := (init_if.tkeep'range => '0');
init_if.tuser := (init_if.tuser'range => '0');
init_if.tstrb := (init_if.tstrb'range => '0');
init_if.tid := (init_if.tid'range => '0');
init_if.tdest := (init_if.tdest'range => '0');
init_if.tlast := '0';
else
-- from slave to master
init_if.tready := config.ready_default_value;
--init_if.tready := '0';
-- from master to slave
init_if.tvalid := 'Z';
init_if.tdata := (init_if.tdata'range => 'Z');
init_if.tkeep := (init_if.tkeep'range => 'Z');
init_if.tuser := (init_if.tuser'range => 'Z');
init_if.tstrb := (init_if.tstrb'range => 'Z');
init_if.tid := (init_if.tid'range => 'Z');
init_if.tdest := (init_if.tdest'range => 'Z');
init_if.tlast := 'Z';
end if;
return init_if;
end function;
--------------------------------------------------------
--
-- AXIStream Transmit
--
--------------------------------------------------------
-- Send a packet on the AXI interface.
-- Packet length and data is defined by data_array
-- tuser is set based on user_array,
-- tstrb is set based on strb_array, etc
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axistream_transmit";
constant proc_call : string := "axistream_transmit(" & to_string(data_array'length) & "B)";
constant c_num_bytes_per_word : natural := axistream_if.tdata'length/8;
constant c_num_user_bits_per_word : natural := axistream_if.tuser'length;
constant c_num_strb_bits_per_word : natural := axistream_if.tstrb'length;
constant c_num_id_bits_per_word : natural := axistream_if.tid'length;
constant c_num_dest_bits_per_word : natural := axistream_if.tdest'length;
-- Helper variables
variable v_byte_in_word : integer range 0 to c_num_bytes_per_word-1 := 0; -- current byte within the data word
variable v_clk_cycles_waited : natural := 0;
variable v_wait_for_next_transfer_cycle : boolean; -- When set, the BFM shall wait for at least one clock cycle, until tready='1' before continuing
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
variable v_valid_low_duration : natural := 0;
variable v_valid_low_cycle_count : natural := 0;
variable v_timeout : boolean := false;
variable v_tready : std_logic; -- Sampled tready for the current clock cycle
begin
-- DEPRECATE: data_array as t_byte_array will be removed in next major release
deprecate(proc_name, "data_array as t_byte_array has been deprecated. Use data_array as t_slv_array.");
check_value(axistream_if.tdata'length >= 8, TB_ERROR, "Sanity check: Check that tdata is at least one byte wide. Narrower tdata is not supported.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tdata'length mod 8 = 0, TB_ERROR, "Sanity check: Check that tdata is an integer number of bytes wide.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tuser'length <= C_MAX_TUSER_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TUSER_BITS is high enough for axistream_if.tuser.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tid'length <= C_MAX_TID_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TID_BITS is high enough for axistream_if.tid.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tdest'length <= C_MAX_TDEST_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TDEST_BITS is high enough for axistream_if.tdest.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tkeep'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tkeep equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(axistream_if.tstrb'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tstrb equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(data_array'ascending, TB_ERROR, "Sanity check: Check that data_array is ascending (defined with 'to'), for byte order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(user_array'ascending, TB_ERROR, "Sanity check: Check that user_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(strb_array'ascending, TB_ERROR, "Sanity check: Check that strb_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(id_array'ascending, TB_ERROR, "Sanity check: Check that id_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(dest_array'ascending, TB_ERROR, "Sanity check: Check that dest_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, proc_call);
if config.bfm_sync = SYNC_WITH_SETUP_AND_HOLD then
check_value(config.clock_period > -1 ns, TB_FAILURE, "Sanity check: Check that clock_period is set.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
end if;
axistream_if <= init_axistream_if_signals(is_master => true, -- this BFM drives data signals
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length);
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
log(ID_PACKET_INITIATE, proc_call & "=> " & add_msg_delimiter(msg), scope, msg_id_panel);
------------------------------------------------------------------------------------------------------------
-- Send byte by byte. There may be multiple bytes per clock cycle, depending on axistream_if'tdata width.
------------------------------------------------------------------------------------------------------------
for byte in 0 to data_array'high loop
log(ID_PACKET_DATA, proc_call & "=> Tx " & to_string(data_array(byte), HEX, AS_IS, INCL_RADIX) &
-- ", tuser=" & to_string(user_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tstrb=" & to_string(strb_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tid=" & to_string(id_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tdest=" & to_string(dest_array(byte/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
", byte# " & to_string(byte) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
-------------------------------------------------------------------
-- Set tvalid low (once per transmission or multiple random times)
-------------------------------------------------------------------
if v_byte_in_word = 0 and (config.valid_low_duration > 0 or config.valid_low_duration = C_RANDOM) then
v_valid_low_cycle_count := 0;
-- Check if pulse duration is defined or random
if config.valid_low_duration > 0 then
v_valid_low_duration := config.valid_low_duration;
elsif config.valid_low_duration = C_RANDOM then
v_valid_low_duration := random(1,config.valid_low_max_random_duration);
end if;
-- Deassert tvalid once per transmission on a specific word
if config.valid_low_at_word_num = byte/c_num_bytes_per_word then
while v_valid_low_cycle_count < v_valid_low_duration loop
v_valid_low_cycle_count := v_valid_low_cycle_count + 1;
wait until rising_edge(clk);
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end loop;
-- Deassert tvalid multiple random times per transmission
elsif config.valid_low_at_word_num = C_MULTIPLE_RANDOM and random(0.0,1.0) <= config.valid_low_multiple_random_prob then
while v_valid_low_cycle_count < v_valid_low_duration loop
v_valid_low_cycle_count := v_valid_low_cycle_count + 1;
wait until rising_edge(clk);
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end loop;
end if;
end if;
axistream_if.tvalid <= '1';
-- Byte locations within the data word is described in chapter 2.3 in "ARM IHI0051A"
axistream_if.tdata(7+8*v_byte_in_word downto 8*v_byte_in_word) <= data_array(byte);
-- Set sideband data for this transfer (i.e. this word)
if v_byte_in_word = 0 then
axistream_if.tuser(c_num_user_bits_per_word-1 downto 0) <= user_array(byte/c_num_bytes_per_word)(c_num_user_bits_per_word-1 downto 0);
axistream_if.tstrb(c_num_strb_bits_per_word-1 downto 0) <= strb_array(byte/c_num_bytes_per_word)(c_num_strb_bits_per_word-1 downto 0);
axistream_if.tid(c_num_id_bits_per_word-1 downto 0) <= id_array(byte/c_num_bytes_per_word)(c_num_id_bits_per_word-1 downto 0);
axistream_if.tdest(c_num_dest_bits_per_word-1 downto 0) <= dest_array(byte/c_num_bytes_per_word)(c_num_dest_bits_per_word-1 downto 0);
end if;
-- TKEEP[x] is associated with TDATA[(7+8*v_byte_in_word) : 8*v_byte_in_word].
axistream_if.tkeep(v_byte_in_word) <= '1';
-- Default: Go to next 'byte' iteration in zero time (when tdata is not completely filled with bytes).
v_wait_for_next_transfer_cycle := false;
if byte = data_array'high then
-- Packet done.
axistream_if.tlast <= '1';
v_wait_for_next_transfer_cycle := true; -- No more bytes to fill in tdata
else
axistream_if.tlast <= '0';
end if;
if v_byte_in_word = c_num_bytes_per_word-1 then
-- Next byte is in the next clk cycle
v_byte_in_word := 0;
v_wait_for_next_transfer_cycle := true; -- No more bytes to fill in tdata
else
-- Next byte is in the same clk cycle
v_byte_in_word := v_byte_in_word + 1;
end if;
--
-- If no more bytes to fill in tdata, wait until the transfer takes place (tvalid=1 and tready=1)
--
if v_wait_for_next_transfer_cycle then
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
v_tready := axistream_if.tready;
check_clock_period_margin(clk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
v_clk_cycles_waited := 1;
-- Check tready signal is asserted (sampled at rising_edge)
while v_tready = '0' loop
wait until rising_edge(clk);
v_tready := axistream_if.tready;
-- Wait according to config.bfm_sync setup
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
v_clk_cycles_waited := v_clk_cycles_waited + 1;
-- If timeout then exit procedure
if v_clk_cycles_waited >= config.max_wait_cycles then
v_timeout := true;
exit;
end if;
end loop;
if v_timeout then
exit;
end if;
-- Default values for the next clk cycle
axistream_if <= init_axistream_if_signals(is_master => true, -- this BFM drives data signals
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length
);
end if;
end loop;
-- Done. Check if there was a timeout or it was successful
if v_timeout then
alert(config.max_wait_cycles_severity, proc_call & "=> Failed. Timeout while waiting for tready. " &
add_msg_delimiter(msg), scope);
else
log(ID_PACKET_COMPLETE, proc_call & "=> Tx DONE. " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure axistream_transmit_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Helper variables
variable v_bytes_in_word : integer := (data_array(data_array'low)'length/8);
variable v_num_bytes : integer := (data_array'length) * v_bytes_in_word;
variable v_data_array : t_byte_array(0 to v_num_bytes-1);
variable v_data_array_idx : integer := 0;
variable v_check_ok : boolean := false;
variable v_byte_endianness : t_byte_endianness := config.byte_endianness;
begin
-- t_slv_array sanity check
v_check_ok := check_value(data_array(data_array'low)'length mod 8 = 0, TB_ERROR, "Sanity check: Check that data_array word is N*byte", scope, ID_NEVER, msg_id_panel);
if v_check_ok then
-- copy byte(s) from t_slv_array to t_byte_array
v_data_array := convert_slv_array_to_byte_array(data_array, v_byte_endianness);
-- call t_byte_array overloaded procedure
axistream_transmit_bytes(v_data_array, user_array, strb_array, id_array, dest_array, msg, clk, axistream_if, scope, msg_id_panel, config);
end if;
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Helper variables
variable v_check_ok : boolean := false;
variable v_data_array : t_slv_array(0 to 0)(data_array'length-1 downto 0);
begin
-- t_slv_array sanity check
v_check_ok := check_value(data_array'length mod 8 = 0, TB_ERROR, "Sanity check: Check that data_array word is N*byte", scope, ID_NEVER, msg_id_panel);
if v_check_ok then
v_data_array(0) := data_array;
-- call t_slv_array overloaded procedure
axistream_transmit(v_data_array, user_array, strb_array, id_array, dest_array, msg, clk, axistream_if, scope, msg_id_panel, config);
end if;
end procedure;
-- Overload that doesn't use records for the AXI interface:
-- (In turn calls the record version)
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- call overloading procedure
axistream_transmit_bytes(
data_array => data_array,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_transmit (
constant data_array : in t_slv_array;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- call overloading t_slv_array procedure
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant strb_array : in t_strb_array;
constant id_array : in t_id_array;
constant dest_array : in t_dest_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- call overloading slv procedure
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-- Overload with default value for strb_array, id_array, dest_array
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- One entry per word. Max words possible is the number of bytes in data_array
constant c_strb_array_default : t_strb_array(0 to data_array'high) := (others => (others => '0'));
constant c_id_array_default : t_id_array(0 to data_array'high) := (others => (others => '0'));
constant c_dest_array_default : t_dest_array(0 to data_array'high) := (others => (others => '0'));
begin
axistream_transmit_bytes(
data_array => data_array,
user_array => user_array,
strb_array => c_strb_array_default,
id_array => c_id_array_default,
dest_array => c_dest_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- One entry per word. Max words possible is the number of bytes in data_array
constant c_strb_array_default : t_strb_array(0 to data_array'high) := (others => (others => '0'));
constant c_id_array_default : t_id_array(0 to data_array'high) := (others => (others => '0'));
constant c_dest_array_default : t_dest_array(0 to data_array'high) := (others => (others => '0'));
begin
-- call overloading t_slv_array procedure
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => c_strb_array_default,
id_array => c_id_array_default,
dest_array => c_dest_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant user_array : in t_user_array;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- One entry per word. Max words possible is the number of bytes in data_array
constant c_strb_array_default : t_strb_array(0 to data_array'high) := (others => (others => '0'));
constant c_id_array_default : t_id_array(0 to data_array'high) := (others => (others => '0'));
constant c_dest_array_default : t_dest_array(0 to data_array'high) := (others => (others => '0'));
begin
-- call overloading slv procedure
axistream_transmit(
data_array => data_array,
user_array => user_array,
strb_array => c_strb_array_default,
id_array => c_id_array_default,
dest_array => c_dest_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-- Overload with default value for user_array, strb_array, id_array, dest_array
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_transmit_bytes (
constant data_array : in t_byte_array; -- Byte in index 0 is transmitted first
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant c_user_array_default : t_user_array(0 to data_array'high) := (others => (others => '0'));
begin
-- Calling another overload that fills in strb_array, id_array, dest_array
axistream_transmit_bytes(
data_array => data_array,
user_array => c_user_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_transmit (
constant data_array : in t_slv_array; -- Byte in index 0 is transmitted first
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant c_user_array_default : t_user_array(0 to data_array'high) := (others => (others => '0'));
begin
-- Calling another t_slv_array overload that fills in strb_array, id_array, dest_array
axistream_transmit(
data_array => data_array,
user_array => c_user_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_transmit (
constant data_array : in std_logic_vector;
constant msg : in string := "";
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant c_user_array_default : t_user_array(0 to data_array'high) := (others => (others => '0'));
begin
-- Calling another slv overload that fills in strb_array, id_array, dest_array
axistream_transmit(
data_array => data_array,
user_array => c_user_array_default,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure axistream_transmit;
--------------------------------------------------------
--
-- AXIStream Receive
--
--------------------------------------------------------
-- Receive a packet, store it in data_array
-- data_array'length can be longer than the actual packet, so that you can call receive() without knowing the length to be expected.
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_receive_bytes (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
constant c_num_bytes_per_word : natural := axistream_if.tdata'length/8;
constant c_num_user_bits_per_word : natural := axistream_if.tuser'length;
constant c_num_strb_bits_per_word : natural := axistream_if.tstrb'length;
constant c_num_id_bits_per_word : natural := axistream_if.tid'length;
constant c_num_dest_bits_per_word : natural := axistream_if.tdest'length;
constant local_proc_name : string := "axistream_receive"; -- Internal proc_name; used if called from sequncer or VVC
constant local_proc_call : string := local_proc_name & "()"; -- Internal proc_call; used if called from sequncer or VVC
-- Helper variables
variable v_proc_call : line; -- Current proc_call, external or local
variable v_byte_in_word : integer range 0 to c_num_bytes_per_word-1 := 0; -- current Byte within the data word
variable v_byte_cnt : integer := 0; -- # bytes received
variable v_timeout : boolean := false;
variable v_done : boolean := false;
variable v_invalid_count : integer := 0; -- # cycles without valid being asserted
variable v_byte_idx : integer;
variable v_word_idx : integer;
variable v_ready_low_duration : natural := 0;
variable v_ready_low_cycle_count : natural := 0;
variable v_time_of_rising_edge : time := -1 ns; -- time stamp for clk period checking
variable v_time_of_falling_edge : time := -1 ns; -- time stamp for clk period checking
variable v_sample_data_now : boolean := false;
begin
if ext_proc_call = "" then
-- Called directly from sequencer/VVC, log 'axistream_receive...'
write(v_proc_call, local_proc_call);
else
-- Called from another BFM procedure, log 'ext_proc_call while executing axistream_receive...'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
-- DEPRECATE: data_array as t_byte_array will be removed in next major release
deprecate(local_proc_call, "data_array as t_byte_array has been deprecated. Use data_array as t_slv_array.");
check_value(axistream_if.tuser'length <= C_MAX_TUSER_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TUSER_BITS is high enough for axistream_if.tuser.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tdata'length >= 8, TB_ERROR, "Sanity check: Check that tdata is at least one byte wide. Narrower tdata is not supported.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tdata'length mod 8 = 0, TB_ERROR, "Sanity check: Check that tdata is an integer number of bytes wide.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tid'length <= C_MAX_TID_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TID_BITS is high enough for axistream_if.tid.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tdest'length <= C_MAX_TDEST_BITS, TB_ERROR, "Sanity check: Check that C_MAX_TDEST_BITS is high enough for axistream_if.tdest.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tkeep'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tkeep equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(axistream_if.tstrb'length = (axistream_if.tdata'length/8), TB_ERROR, "Sanity check: Check that width of tstrb equals number of bytes in tdata.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(data_array'ascending, TB_ERROR, "Sanity check: Check that data_array is ascending (defined with 'to'), for knowing which byte is sent first", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(user_array'ascending, TB_ERROR, "Sanity check: Check that user_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(strb_array'ascending, TB_ERROR, "Sanity check: Check that strb_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(id_array'ascending, TB_ERROR, "Sanity check: Check that id_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(dest_array'ascending, TB_ERROR, "Sanity check: Check that dest_array is ascending (defined with 'to'), for word order clarity", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
if config.bfm_sync = SYNC_WITH_SETUP_AND_HOLD then
check_value(config.clock_period > -1 ns, TB_FAILURE, "Sanity check: Check that clock_period is set.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
end if;
-- Avoid driving inputs
axistream_if <= init_axistream_if_signals(
is_master => false,
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length,
config => config );
-- Wait according to config.bfm_sync setup
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
log(ID_PACKET_INITIATE, v_proc_call.all & "=> Receive packet. " & add_msg_delimiter(msg), scope, msg_id_panel);
------------------------------------------------------------------------------------------------------------
-- Sample byte by byte. There may be multiple bytes per clock cycle, depending on axistream_if'tdata width.
------------------------------------------------------------------------------------------------------------
while not v_done loop
--------------------------------------------------------------------------------------
-- Set tready low before given byte (once per transmission or multiple random times)
--------------------------------------------------------------------------------------
if v_byte_in_word = 0 and (config.ready_low_duration > 0 or config.ready_low_duration = C_RANDOM) then
v_ready_low_cycle_count := 0;
-- Check if pulse duration is defined or random
if config.ready_low_duration > 0 then
v_ready_low_duration := config.ready_low_duration;
elsif config.ready_low_duration = C_RANDOM then
v_ready_low_duration := random(1,config.ready_low_max_random_duration);
end if;
-- Deassert tready once per transmission on a specific word
if config.ready_low_at_word_num = v_byte_cnt/c_num_bytes_per_word then
axistream_if.tready <= '0';
-- Wait until tvalid goes high before counting the deassertion cycles
while axistream_if.tvalid = '0' and v_invalid_count < config.max_wait_cycles loop
v_invalid_count := v_invalid_count + 1;
wait until rising_edge(clk);
-- If tvalid was asserted right before the rising_edge then we have already waited
-- one cycle with tready deasserted
if axistream_if.tvalid = '1' then
v_ready_low_duration := v_ready_low_duration - 1;
end if;
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end loop;
-- TValid timed out
if v_invalid_count >= config.max_wait_cycles then
v_timeout := true;
v_done := true;
v_ready_low_duration := 0;
end if;
while v_ready_low_cycle_count < v_ready_low_duration loop
v_ready_low_cycle_count := v_ready_low_cycle_count + 1;
wait until rising_edge(clk);
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end loop;
-- Deassert tready multiple random times per transmission
elsif config.ready_low_at_word_num = C_MULTIPLE_RANDOM and random(0.0,1.0) <= config.ready_low_multiple_random_prob then
axistream_if.tready <= '0';
while v_ready_low_cycle_count < v_ready_low_duration loop
v_ready_low_cycle_count := v_ready_low_cycle_count + 1;
wait until rising_edge(clk);
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end loop;
end if;
end if;
------------------------------------------------------------
-- Assert the tready signal (after tvalid is high) and wait
-- for the rising_edge of the clock to sample the data
------------------------------------------------------------
if v_byte_in_word = 0 then
-- To receive the first byte wait until tvalid goes high before asserting tready
if v_byte_cnt = 0 and axistream_if.tvalid = '0' and not(v_timeout) then
while axistream_if.tvalid = '0' and v_invalid_count < config.max_wait_cycles loop
v_invalid_count := v_invalid_count + 1;
wait until rising_edge(clk);
-- If tvalid was asserted right before the rising_edge then we should sample
-- the data right away, otherwise we wait
if axistream_if.tvalid = '1' and axistream_if.tready = '1' then
v_sample_data_now := true;
else
v_sample_data_now := false;
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end if;
end loop;
if not(v_sample_data_now) then
-- TValid is now high, assert tready
if v_invalid_count < config.max_wait_cycles then
axistream_if.tready <= '1';
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
-- TValid timed out
else
v_timeout := true;
v_done := true;
end if;
end if;
-- TValid was already high, assert tready right away
else
axistream_if.tready <= '1';
wait until rising_edge(clk);
if v_time_of_rising_edge = -1 ns then
v_time_of_rising_edge := now;
end if;
end if;
end if;
if not(v_timeout) then
check_clock_period_margin(clk, config.bfm_sync, v_time_of_falling_edge, v_time_of_rising_edge,
config.clock_period, config.clock_period_margin, config.clock_margin_severity);
end if;
------------------------------------------------------------
-- Sample the data
------------------------------------------------------------
if axistream_if.tvalid = '1' and axistream_if.tready = '1' then
v_invalid_count := 0;
-- Sample data
data_array(v_byte_cnt) := axistream_if.tdata(7+8*v_byte_in_word downto 8*v_byte_in_word);
-- Sample sideband data for this transfer (this word): There is one array entry per word
if v_byte_in_word = 0 then
v_word_idx := v_byte_cnt/c_num_bytes_per_word;
if (v_word_idx <= user_array'high) then -- Include this 'if' to allow a shorter user_array if the caller doesn't care what tuser is
user_array(v_byte_cnt/c_num_bytes_per_word)(c_num_user_bits_per_word-1 downto 0) := axistream_if.tuser(c_num_user_bits_per_word-1 downto 0);
end if;
if (v_word_idx <= strb_array'high) then -- Include this 'if' to allow a shorter *_array if the caller doesn't care what tstrb is
strb_array(v_byte_cnt/c_num_bytes_per_word)(c_num_strb_bits_per_word-1 downto 0) := axistream_if.tstrb(c_num_strb_bits_per_word-1 downto 0);
end if;
if (v_word_idx <= id_array'high) then -- Include this 'if' to allow a shorter *_array if the caller doesn't care what tid is
id_array(v_byte_cnt/c_num_bytes_per_word)(c_num_id_bits_per_word-1 downto 0) := axistream_if.tid(c_num_id_bits_per_word-1 downto 0);
end if;
if (v_word_idx <= dest_array'high) then -- Include this 'if' to allow a shorter *_array if the caller doesn't care what tdest is
dest_array(v_byte_cnt/c_num_bytes_per_word)(c_num_dest_bits_per_word-1 downto 0) := axistream_if.tdest(c_num_dest_bits_per_word-1 downto 0);
end if;
end if;
log(ID_PACKET_DATA, v_proc_call.all & "=> Rx " & to_string(data_array(v_byte_cnt), HEX, AS_IS, INCL_RADIX) &
-- ", tuser=" & to_string(user_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tstrb=" & to_string(strb_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tid=" & to_string(id_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
-- ", tdest=" & to_string(dest_array(v_byte_cnt/c_num_bytes_per_word), HEX, AS_IS, INCL_RADIX) &
" (byte# " & to_string(v_byte_cnt) & "). " & add_msg_delimiter(msg), scope, msg_id_panel);
-- Stop sampling data when we have filled the data_array
if v_byte_cnt = data_array'high then
-- Check tlast='1' at expected last byte
if config.check_packet_length then
check_value(axistream_if.tlast, '1', config.protocol_error_severity, "Check tlast at expected last byte = " & to_string(v_byte_cnt) & ". " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
end if;
v_done := true;
end if;
-- Allow that tlast arrives sooner than indicated by data_array'high
-- if receive() is called without knowing the length to be expected.
if axistream_if.tlast = '1' then
if axistream_if.tkeep(v_byte_in_word) = '1' then
if v_byte_in_word = c_num_bytes_per_word-1 then
-- it's the last byte in word and tlast='1', thus the last in packet.
v_done := true;
else
if axistream_if.tkeep(v_byte_in_word+1) = '0' then
-- Next byte in word is invalid, so this is the last byte
v_done := true;
-- Check that tkeep for the remaining bytes in the last word are also '0'. (Only continous stream supported)
v_byte_idx := v_byte_in_word+1;
l_check_remaining_TKEEP: loop
check_value(axistream_if.tkeep(v_byte_idx), '0', ERROR, "Check that tkeep doesn't go from '1' to '0' to '1' again within this last word. (The BFM supports only continuous stream)", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
if v_byte_idx < (axistream_if.tkeep'length-1) then
v_byte_idx := v_byte_idx + 1;
else
exit l_check_remaining_TKEEP;
end if;
end loop;
else
-- Next byte in word is valid but the data_array has finished
if v_done then
alert(ERROR, v_proc_call.all & "=> Failed. data_array too small for received bytes. " & add_msg_delimiter(msg), scope);
end if;
end if;
end if;
end if;
else -- tlast = 0
-- Check that all tkeep bits are '1'. (Only continous stream supported)
check_value(axistream_if.tkeep(v_byte_in_word), '1', ERROR, "When tlast='0', check that all tkeep bits are '1'. (The BFM supports only continuous stream)" & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel, v_proc_call.all);
end if;
-- Next byte is in the next clk cycle
if v_byte_in_word = c_num_bytes_per_word-1 then
-- Don't wait on the last cycle
if not(v_done) then
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end if;
v_byte_in_word := 0;
-- Next byte is in the same clk cycle
else
v_byte_in_word := v_byte_in_word + 1;
end if;
-- Next byte
v_byte_cnt := v_byte_cnt + 1;
------------------------------------------------------------
-- Data couldn't be sampled, wait until next cycle
------------------------------------------------------------
elsif not(v_timeout) then
-- Check for timeout (also when max_wait_cycles_severity = NO_ALERT,
-- or else the VVC will wait forever, until the UVVM cmd times out)
if v_invalid_count >= config.max_wait_cycles then
v_timeout := true;
v_done := true;
else
v_invalid_count := v_invalid_count + 1;
end if;
wait_on_bfm_sync_start(clk, config.bfm_sync, config.setup_time, config.clock_period, v_time_of_falling_edge, v_time_of_rising_edge);
end if;
end loop; -- while not v_done
-- Wait according to bfm_sync config
if not(v_timeout) then
wait_on_bfm_exit(clk, config.bfm_sync, config.hold_time, v_time_of_falling_edge, v_time_of_rising_edge);
end if;
-- Set the number of bytes received
data_length := v_byte_cnt;
-- Log the received frame
if is_log_msg_enabled(ID_PACKET_PAYLOAD, msg_id_panel) then -- large frames may affect performance
log(ID_PACKET_PAYLOAD, v_proc_call.all & "=> Rx Frame (" & to_string(v_byte_cnt) & "B) " & to_string(data_array) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
-- Check if there was a timeout or it was successful
if v_timeout then
alert(config.max_wait_cycles_severity, v_proc_call.all & "=> Failed. Timeout while waiting for valid data. " & add_msg_delimiter(msg), scope);
else
if ext_proc_call = "" then
log(ID_PACKET_COMPLETE, v_proc_call.all & "=> Rx DONE (" & to_string(v_byte_cnt) & "B)" & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. axistream_expect)
end if;
end if;
-- Done, set axistream back to default
axistream_if <= init_axistream_if_signals(
is_master => false,
data_width => axistream_if.tdata'length,
user_width => axistream_if.tuser'length,
id_width => axistream_if.tid'length,
dest_width => axistream_if.tdest'length,
config => config );
DEALLOCATE(v_proc_call);
end procedure axistream_receive_bytes;
-- Overloaded t_slv_array procedure
procedure axistream_receive (
variable data_array : inout t_slv_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call: in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is -- helper variables
variable v_bytes_in_word : integer := (data_array(data_array'low)'length/8);
variable v_num_bytes : integer := (data_array'length) * v_bytes_in_word;
variable v_data_array_as_byte : t_byte_array(0 to v_num_bytes-1);
variable v_byte_endianness : t_byte_endianness := config.byte_endianness;
begin
-- call overloaded t_byte_array procedure
axistream_receive_bytes ( v_data_array_as_byte,
data_length, user_array, strb_array, id_array, dest_array, msg,
clk, axistream_if, scope, msg_id_panel, config, ext_proc_call );
data_array := convert_byte_array_to_slv_array(v_data_array_as_byte, v_bytes_in_word, v_byte_endianness);
end procedure axistream_receive;
-- Overloaded version without records
-- DEPRECATE: procedure with data_array as t_byte_array will be removed in next major release
procedure axistream_receive_bytes (
variable data_array : inout t_byte_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
begin
-- Simply call the record version
axistream_receive_bytes(
data_array => data_array,
data_length => data_length,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config,
ext_proc_call => ext_proc_call);
end procedure axistream_receive_bytes;
-- Overloading t_slv_array procedure
procedure axistream_receive (
variable data_array : inout t_slv_array;
variable data_length : inout natural; -- Number of bytes received
variable user_array : inout t_user_array;
variable strb_array : inout t_strb_array;
variable id_array : inout t_id_array;
variable dest_array : inout t_dest_array;
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call. Overwrite if called from another BFM procedure
) is
begin
-- Simply call the record version
axistream_receive(
data_array => data_array,
data_length => data_length,
user_array => user_array,
strb_array => strb_array,
id_array => id_array,
dest_array => dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
scope => scope,
msg_id_panel => msg_id_panel,
config => config,
ext_proc_call => ext_proc_call);
end procedure axistream_receive;
--------------------------------------------------------
--
-- AXIStream Expect
--
--------------------------------------------------------
-- Receive data, then compare the received data against exp_data_array
-- - If the received data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axistream_expect";
constant proc_call : string := "axistream_expect(" & to_string(exp_data_array'length) & "B)";
constant c_num_bytes_per_word : natural := axistream_if.tdata'length/8;
constant c_num_user_bits_per_word : natural := axistream_if.tuser'length;
constant c_num_strb_bits_per_word : natural := axistream_if.tstrb'length;
constant c_num_id_bits_per_word : natural := axistream_if.tid'length;
constant c_num_dest_bits_per_word : natural := axistream_if.tdest'length;
-- Helper variables
variable v_config : t_axistream_bfm_config := config;
variable v_rx_data_array : t_byte_array(exp_data_array'range); -- received data
variable v_rx_user_array : t_user_array(exp_user_array'range); -- received tuser
variable v_rx_strb_array : t_strb_array(exp_strb_array'range);
variable v_rx_id_array : t_id_array(exp_id_array'range);
variable v_rx_dest_array : t_dest_array(exp_dest_array'range);
variable v_rx_data_length : natural;
variable v_data_error_cnt : natural := 0;
variable v_user_error_cnt : natural := 0;
variable v_strb_error_cnt : natural := 0;
variable v_id_error_cnt : natural := 0;
variable v_dest_error_cnt : natural := 0;
variable v_first_errored_byte : natural;
variable v_alert_radix : t_radix;
begin
-- Receive and store data
axistream_receive_bytes(data_array => v_rx_data_array,
data_length => v_rx_data_length,
user_array => v_rx_user_array,
strb_array => v_rx_strb_array,
id_array => v_rx_id_array,
dest_array => v_rx_dest_array,
msg => msg,
clk => clk,
axistream_if => axistream_if,
scope => scope,
msg_id_panel => msg_id_panel,
config => v_config,
ext_proc_call => proc_call);
-- Check if each received bit matches the expected
-- Find and report the first errored byte
for byte in v_rx_data_array'high downto 0 loop
for i in v_rx_data_array(byte)'range loop
-- Allow don't care in expected value and use match strictness from config for comparison
if exp_data_array(byte)(i) = '-' or check_value(v_rx_data_array(byte)(i), exp_data_array(byte)(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
-- Check is OK
else
-- Received byte does not match the expected byte
--log(config.id_for_bfm, proc_call & "=> NOK, checked " & to_string(v_rx_data_array(byte), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_data_array(byte), HEX, AS_IS, INCL_RADIX) & msg, scope, msg_id_panel);
v_data_error_cnt := v_data_error_cnt + 1;
v_first_errored_byte := byte;
end if;
end loop;
end loop;
-- Check tuser matches exp_user_array
-- Check all bits the exp_user_array. If the caller (Test Sequencer or VVC) don't care, the length of exp_user_array input shall be only one
for word in exp_user_array'high downto 0 loop
for i in c_num_user_bits_per_word-1 downto 0 loop -- i = bit
-- Allow don't care in expected value and use match strictness from config for comparison
if exp_user_array(word)(i) = '-' or check_value(v_rx_user_array(word)(i), exp_user_array(word)(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
-- Check is OK
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_user_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_user_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tuser word does not match the expected word
v_user_error_cnt := v_user_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- Check that all bits in exp_strb_array matches received tstrb
for word in exp_strb_array'high downto 0 loop
for i in c_num_strb_bits_per_word-1 downto 0 loop -- i = bit
-- Allow don't care in expected value and use match strictness from config for comparison
if exp_strb_array(word)(i) = '-' or check_value(v_rx_strb_array(word)(i), exp_strb_array(word)(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
-- Check is OK
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_strb_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_strb_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tstrb word does not match the expected word
v_strb_error_cnt := v_strb_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- Check that all bits in exp_id_array matches received tid
for word in exp_id_array'high downto 0 loop
for i in c_num_id_bits_per_word-1 downto 0 loop -- i = bit
-- Allow don't care in expected value and use match strictness from config for comparison
if exp_id_array(word)(i) = '-' or check_value(v_rx_id_array(word)(i), exp_id_array(word)(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
-- Check is OK
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_id_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_id_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tid word does not match the expected word
v_id_error_cnt := v_id_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- Check that all bits in exp_dest_array matches received tdest
for word in exp_dest_array'high downto 0 loop
for i in c_num_dest_bits_per_word-1 downto 0 loop -- i = bit
-- Allow don't care in expected value and use match strictness from config for comparison
if exp_dest_array(word)(i) = '-' or check_value(v_rx_dest_array(word)(i), exp_dest_array(word)(i), config.match_strictness, NO_ALERT, msg, scope, ID_NEVER) then
-- Check is OK
else
log(ID_PACKET_DATA, proc_call & "=> NOK(word="&to_string(word)&"), checked " & to_string(v_rx_dest_array(word), HEX, AS_IS, INCL_RADIX) & "=" & to_string(exp_dest_array(word), HEX, AS_IS, INCL_RADIX) & add_msg_delimiter(msg), scope, msg_id_panel);
-- Received tdest word does not match the expected word
v_dest_error_cnt := v_dest_error_cnt + 1;
v_first_errored_byte := word;
end if;
end loop;
end loop;
-- No more than one alert per packet
if v_data_error_cnt /= 0 then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_data_array(v_first_errored_byte), exp_data_array(v_first_errored_byte), MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, proc_call & "=> Failed in " & to_string(v_data_error_cnt) & " data bits. First mismatch in byte# " & to_string(v_first_errored_byte) & ". Was " &
to_string(v_rx_data_array(v_first_errored_byte), v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " & to_string(exp_data_array(v_first_errored_byte), v_alert_radix, AS_IS, INCL_RADIX) &
"." & LF & add_msg_delimiter(msg), scope);
elsif v_user_error_cnt /= 0 then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_user_array(v_first_errored_byte), exp_user_array(v_first_errored_byte), MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, proc_call & "=> Failed in " & to_string(v_user_error_cnt) & " tuser bits. First mismatch in word# " & to_string(v_first_errored_byte) &
". Was " & to_string(v_rx_user_array(v_first_errored_byte)(c_num_user_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " &
to_string(exp_user_array(v_first_errored_byte)(c_num_user_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_strb_error_cnt /= 0 then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_strb_array(v_first_errored_byte), exp_strb_array(v_first_errored_byte), MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, proc_call & "=> Failed in " & to_string(v_strb_error_cnt) & " tstrb bits. First mismatch in word# " & to_string(v_first_errored_byte) &
". Was " & to_string(v_rx_strb_array(v_first_errored_byte)(c_num_strb_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " &
to_string(exp_strb_array(v_first_errored_byte)(c_num_strb_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_id_error_cnt /= 0 then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_id_array(v_first_errored_byte), exp_id_array(v_first_errored_byte), MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, proc_call & "=> Failed in " & to_string(v_id_error_cnt) & " tid bits. First mismatch in word# " & to_string(v_first_errored_byte) &
". Was " & to_string(v_rx_id_array(v_first_errored_byte)(c_num_id_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " &
to_string(exp_id_array(v_first_errored_byte)(c_num_id_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
elsif v_dest_error_cnt /= 0 then
-- Use binary representation when mismatch is due to weak signals
v_alert_radix := BIN when config.match_strictness = MATCH_EXACT and check_value(v_rx_dest_array(v_first_errored_byte), exp_dest_array(v_first_errored_byte), MATCH_STD, NO_ALERT, msg, scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER) else HEX;
alert(alert_level, proc_call & "=> Failed in " & to_string(v_dest_error_cnt) & " tdest bits. First mismatch in word# " & to_string(v_first_errored_byte) &
". Was " & to_string(v_rx_dest_array(v_first_errored_byte)(c_num_dest_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & ". Expected " &
to_string(exp_dest_array(v_first_errored_byte)(c_num_dest_bits_per_word-1 downto 0), v_alert_radix, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, proc_call & "=> OK, received " & to_string(v_rx_data_array'length) & "Bytes. " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure axistream_expect_bytes;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "axistream_expect"; -- Internal proc_name; used if called from sequncer or VVC
-- helper variables
variable v_bytes_in_word : integer := (exp_data_array(exp_data_array'low)'length/8);
variable v_num_bytes : integer := (exp_data_array'length) * v_bytes_in_word;
variable v_exp_data_array : t_byte_array(0 to v_num_bytes-1);
variable v_exp_data_array_idx : integer := 0;
variable v_check_ok : boolean := false;
variable v_dummy : t_slv_array(0 to 0)(31 downto 0);
variable v_byte_endianness : t_byte_endianness := config.byte_endianness;
begin
-- t_slv_array sanity check
v_check_ok := check_value(exp_data_array(exp_data_array'low)'length mod 8 = 0, TB_ERROR, "Sanity check: Check that exp_data_array is N*byte", scope, ID_NEVER, msg_id_panel);
if v_check_ok then
-- copy byte(s) from t_slv_array to t_byte_array
v_exp_data_array := convert_slv_array_to_byte_array(exp_data_array, v_byte_endianness);
-- call t_byte_array overloaded procedure
axistream_expect_bytes(v_exp_data_array,
exp_user_array,
exp_strb_array,
exp_id_array,
exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end if;
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
constant local_proc_name : string := "axistream_expect"; -- Internal proc_name; used if called from sequncer or VVC
-- helper variables
variable v_exp_data_array : t_slv_array(0 to 0)(exp_data_array'length-1 downto 0);
variable v_check_ok : boolean := false;
begin
-- t_slv_array sanity check
v_check_ok := check_value(exp_data_array'length mod 8 = 0, TB_ERROR, "Sanity check: Check that exp_data_array word is N*byte", scope, ID_NEVER, msg_id_panel);
if v_check_ok then
v_exp_data_array(0) := exp_data_array;
-- call t_slv_array overloaded procedure
axistream_expect(v_exp_data_array,
exp_user_array,
exp_strb_array,
exp_id_array,
exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end if;
end procedure;
-- Overloaded version without records
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- Simply call the record version
axistream_expect_bytes(
exp_data_array => exp_data_array,
exp_user_array => exp_user_array,
exp_strb_array => exp_strb_array,
exp_id_array => exp_id_array,
exp_dest_array => exp_dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
alert_level => alert_level,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- Simply call the t_slv_array record version
axistream_expect(
exp_data_array => exp_data_array,
exp_user_array => exp_user_array,
exp_strb_array => exp_strb_array,
exp_id_array => exp_id_array,
exp_dest_array => exp_dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
alert_level => alert_level,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant exp_strb_array : in t_strb_array; -- Expected tstrb
constant exp_id_array : in t_id_array; -- Expected tid
constant exp_dest_array : in t_dest_array; -- Expected tdest
constant msg : in string;
signal clk : in std_logic;
signal axistream_if_tdata : inout std_logic_vector;
signal axistream_if_tkeep : inout std_logic_vector;
signal axistream_if_tuser : inout std_logic_vector;
signal axistream_if_tstrb : inout std_logic_vector;
signal axistream_if_tid : inout std_logic_vector;
signal axistream_if_tdest : inout std_logic_vector;
signal axistream_if_tvalid : inout std_logic;
signal axistream_if_tlast : inout std_logic;
signal axistream_if_tready : inout std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
begin
-- Simply call the slv record version
axistream_expect(
exp_data_array => exp_data_array,
exp_user_array => exp_user_array,
exp_strb_array => exp_strb_array,
exp_id_array => exp_id_array,
exp_dest_array => exp_dest_array,
msg => msg,
clk => clk,
axistream_if.tdata => axistream_if_tdata,
axistream_if.tkeep => axistream_if_tkeep,
axistream_if.tuser => axistream_if_tuser,
axistream_if.tstrb => axistream_if_tstrb,
axistream_if.tid => axistream_if_tid,
axistream_if.tdest => axistream_if_tdest,
axistream_if.tvalid => axistream_if_tvalid,
axistream_if.tlast => axistream_if_tlast,
axistream_if.tready => axistream_if_tready,
alert_level => alert_level,
scope => scope,
msg_id_panel => msg_id_panel,
config => config);
end procedure;
-- Overload without exp_strb_array, exp_id_array, exp_dest_array arguments' argument
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
axistream_expect_bytes(exp_data_array,
exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
-- call overloaded t_slv_array procedure
axistream_expect(exp_data_array,
exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant exp_user_array : in t_user_array; -- Expected tuser
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
-- call overloaded slv procedure
axistream_expect(exp_data_array,
exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-- Overload without arguments exp_user_array, exp_strb_array, exp_id_array, exp_dest_array arguments
-- DEPRECATE: procedure with exp_data_array as t_byte_array will be removed in next major release
procedure axistream_expect_bytes (
constant exp_data_array : in t_byte_array; -- Expected data
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_user_array : t_user_array(0 to 0) := (others => (others => '-'));
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
axistream_expect_bytes(exp_data_array,
v_exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-----------------------
-- t_slv_array overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in t_slv_array; -- Expected data
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_user_array : t_user_array(0 to 0) := (others => (others => '-'));
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
-- call overloaded t_slv_array procedure
axistream_expect(exp_data_array,
v_exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
-----------------------
-- std_logic_vector overload
-----------------------
procedure axistream_expect (
constant exp_data_array : in std_logic_vector; -- Expected data
constant msg : in string;
signal clk : in std_logic;
signal axistream_if : inout t_axistream_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT
) is
-- Default value: don't care
variable v_exp_user_array : t_user_array(0 to 0) := (others => (others => '-'));
variable v_exp_strb_array : t_strb_array(0 to 0) := (others => (others => '-'));
variable v_exp_dest_array : t_dest_array(0 to 0) := (others => (others => '-'));
variable v_exp_id_array : t_id_array(0 to 0) := (others => (others => '-'));
begin
-- call overloaded slv procedure
axistream_expect(exp_data_array,
v_exp_user_array,
v_exp_strb_array,
v_exp_id_array,
v_exp_dest_array,
msg,
clk,
axistream_if,
alert_level,
scope,
msg_id_panel,
config);
end procedure;
end package body axistream_bfm_pkg;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT GC_fifo_top IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Thu Mar 27 15:00:40 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
library uart_cntrl_v1_00_a;
use uart_cntrl_v1_00_a.UARTController;
use uart_cntrl_v1_00_a.BaudRateGenerator;
use uart_cntrl_v1_00_a.UARTReciever;
use uart_cntrl_v1_00_a.UARTTransmitter;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 1;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
rx : in std_logic;
tx : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
-- component UARTController port (
-- clk : in STD_LOGIC;
-- rst : in STD_LOGIC;
-- rx : in STD_LOGIC;
-- w_data : in STD_LOGIC_VECTOR (7 downto 0);
-- w_start : in STD_LOGIC;
-- tx : out STD_LOGIC;
-- w_done : out STD_LOGIC;
-- r_data : out STD_LOGIC_VECTOR (7 downto 0);
-- r_done : out STD_LOGIC
-- );
-- end component;
--USER signal declarations added here, as needed for user logic
signal UART_clk : std_logic;
signal UART_rst : std_logic;
signal UART_wstart : std_logic;
signal UART_wdone : std_logic;
signal UART_rdone : std_logic;
signal indata : std_logic_vector (7 downto 0);
signal outdata : std_logic_vector (7 downto 0);
signal UART_rx : std_logic;
signal UART_tx : std_logic;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(0 to 0);
signal slv_reg_read_sel : std_logic_vector(0 to 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
UARTC: entity work.UARTController port map (UART_clk, UART_rst, UART_rx,
outdata, UART_wstart, UART_tx, UART_wdone, indata, UART_rdone);
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
-- slv_reg_write_sel <= Bus2IP_WrCE(0 downto 0);
-- slv_reg_read_sel <= Bus2IP_RdCE(0 downto 0);
-- slv_write_ack <= Bus2IP_WrCE(0);
-- slv_read_ack <= Bus2IP_RdCE(0);
UART_clk <= Bus2IP_Clk;
UART_rst <= Bus2IP_Resetn;
outdata <= Bus2IP_Data (7 downto 0);
UART_wstart <= Bus2IP_WrCE(0);
UART_rx <= rx;
-- implement slave model software accessible register(s)
-- SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
-- begin
--
--
-- if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
-- if Bus2IP_Resetn = '0' then
-- slv_reg0 <= (others => '0');
-- else
-- case slv_reg_write_sel is
-- when "1" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when others => null;
-- end case;
-- end if;
-- end if;
--
-- end process SLAVE_REG_WRITE_PROC;
--
-- -- implement slave model software accessible register(s) read mux
-- SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
-- begin
--
-- case slv_reg_read_sel is
-- when "1" => slv_ip2bus_data <= slv_reg0;
-- when others => slv_ip2bus_data <= (others => '0');
-- end case;
--
-- end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
--IP2Bus_Data(7 downto 0) <= indata;
IP2Bus_Data(7 downto 0) <= indata when UART_rdone = '1' else (others => '0');
IP2Bus_WrAck <= UART_wdone;
IP2Bus_RdAck <= UART_rdone;
tx <= UART_tx;
Bus2IP_RdCE(0) <= '0' when UART_rdone = '1' else '1';
-- IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
-- (others => '0');
--
-- IP2Bus_WrAck <= slv_write_ack;
-- IP2Bus_RdAck <= slv_read_ack;
-- IP2Bus_Error <= '0';
end IMP;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_testbench_clock is
generic (
PHASE_DELAY : string := "0 ns";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "20 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
clock_out : out std_logic;
aclr_out : out std_logic;
tb_aclr : out std_logic;
reg_aclr_out : out std_logic
);
end entity alt_dspbuilder_testbench_clock;
architecture rtl of alt_dspbuilder_testbench_clock is
component alt_dspbuilder_testbench_clock_GNXGQJH2DS is
generic (
PHASE_DELAY : string := "0 fs";
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
INITIAL_CLOCK : natural := 1;
PERIOD : string := "7.499999999999999 ns";
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic;
clock_out : out std_logic;
reg_aclr_out : out std_logic;
tb_aclr : out std_logic
);
end component alt_dspbuilder_testbench_clock_GNXGQJH2DS;
begin
alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: if ((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)) generate
inst_alt_dspbuilder_testbench_clock_GNXGQJH2DS_0: alt_dspbuilder_testbench_clock_GNXGQJH2DS
generic map(PHASE_DELAY => "0 fs", SIMULATION_START_CYCLE => 4, RESET_LATENCY => 0, INITIAL_CLOCK => 1, PERIOD => "7.499999999999999 ns", RESET_REGISTER_CASCADE_DEPTH => 0)
port map(aclr_out => aclr_out, clock_out => clock_out, reg_aclr_out => reg_aclr_out, tb_aclr => tb_aclr);
end generate;
assert not (((PHASE_DELAY = "0 fs") and (SIMULATION_START_CYCLE = 4) and (RESET_LATENCY = 0) and (INITIAL_CLOCK = 1) and (PERIOD = "7.499999999999999 ns") and (RESET_REGISTER_CASCADE_DEPTH = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_tx
-- File: greth_tx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet transmitter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of greth_tx is
function mirror2(din : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable do : std_logic_vector(3 downto 0);
begin
do(3) := din(0); do(2) := din(1);
do(1) := din(2); do(0) := din(3);
return do;
end function;
function init_ifg(
ifg_gap : in integer;
rmii : in integer)
return integer is
begin
if rmii = 0 then
return log2(ifg_gap);
else
return log2(ifg_gap*20);
end if;
end function;
constant maxattempts : std_logic_vector(4 downto 0) :=
conv_std_logic_vector(attempt_limit, 5);
--transmitter constants
constant ifg_bits : integer := init_ifg(ifg_gap, rmii);
constant ifg_p1 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap)/3, ifg_bits);
constant ifg_p2 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p1_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p2_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*4)/3, ifg_bits);
constant ifg_p1_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*20)/3, ifg_bits);
constant ifg_p2_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*40)/3, ifg_bits);
function ifg_sel(
rmii : in integer;
p1 : in integer;
speed : in std_ulogic)
return std_logic_vector is
begin
if p1 = 1 then
if rmii = 0 then
return ifg_p1;
else
if speed = '1' then
return ifg_p1_r100;
else
return ifg_p1_r10;
end if;
end if;
else
if rmii = 0 then
return ifg_p2;
else
if speed = '1' then
return ifg_p2_r100;
else
return ifg_p2_r10;
end if;
end if;
end if;
end function;
--transmitter types
type tx_state_type is (idle, preamble, sfd, data1, data2, pad1, pad2, fcs,
fcs2, finish, calc_backoff, wait_backoff, send_jam, send_jam2,
check_attempts);
type def_state_type is (monitor, def_on, ifg1, ifg2, frame_waitingst);
type tx_reg_type is record
--deference process
def_state : def_state_type;
ifg_cycls : std_logic_vector(ifg_bits-1 downto 0);
deferring : std_ulogic;
was_transmitting : std_ulogic;
--tx process
main_state : tx_state_type;
transmitting : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
cnt : std_logic_vector(3 downto 0);
icnt : std_logic_vector(1 downto 0);
crc : std_logic_vector(31 downto 0);
crc_en : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
slot_count : std_logic_vector(6 downto 0);
random : std_logic_vector(9 downto 0);
delay_val : std_logic_vector(9 downto 0);
retry_cnt : std_logic_vector(4 downto 0);
status : std_logic_vector(1 downto 0);
data : std_logic_vector(31 downto 0);
--synchronization
read : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
start : std_logic_vector(nsync downto 0);
read_ack : std_logic_vector(nsync-1 downto 0);
crs : std_logic_vector(1 downto 0);
col : std_logic_vector(1 downto 0);
fullduplex : std_logic_vector(1 downto 0);
--rmii
crs_act : std_ulogic;
crs_prev : std_ulogic;
speed : std_logic_vector(1 downto 0);
rcnt : std_logic_vector(3 downto 0);
switch : std_ulogic;
txd_msb : std_logic_vector(1 downto 0);
zero : std_ulogic;
rmii_crc_en : std_ulogic;
end record;
--transmitter signals
signal r, rin : tx_reg_type;
signal txrst : std_ulogic;
signal vcc : std_ulogic;
--attribute sync_set_reset : string;
attribute sync_set_reset of txrst : signal is "true";
begin
vcc <= '1';
tx_rst : eth_rstgen
port map(rst, clk, vcc, txrst, open);
tx : process(txrst, r, txi) is
variable collision : std_ulogic;
variable frame_waiting : std_ulogic;
variable index : integer range 0 to 7;
variable start : std_ulogic;
variable read_ack : std_ulogic;
variable v : tx_reg_type;
variable crs : std_ulogic;
variable col : std_ulogic;
variable tx_done : std_ulogic;
begin
v := r; frame_waiting := '0'; tx_done := '0'; v.rmii_crc_en := '0';
--synchronization
v.col(1) := r.col(0); v.col(0) := txi.rx_col;
v.crs(1) := r.crs(0); v.crs(0) := txi.rx_crs;
v.fullduplex(0) := txi.full_duplex;
v.fullduplex(1) := r.fullduplex(0);
v.start(0) := txi.start;
v.read_ack(0) := txi.readack;
if nsync = 2 then
v.start(1) := r.start(0);
v.read_ack(1) := r.read_ack(0);
end if;
start := r.start(nsync) xor r.start(nsync-1);
read_ack := not (r.read xor r.read_ack(nsync-1));
--crc generation
if (r.crc_en = '1') and ((rmii = 0) or (r.rmii_crc_en = '1')) then
v.crc := calccrc(r.txd, r.crc);
end if;
--rmii
if rmii = 0 then
col := r.col(1); crs := r.crs(1);
tx_done := '1';
else
v.crs_prev := r.crs(1);
if (r.crs(0) and not r.crs_act) = '1' then
v.crs_act := '1';
end if;
if (r.crs(1) or r.crs(0)) = '0' then
v.crs_act := '0';
end if;
crs := r.crs(1) and not ((not r.crs_prev) and r.crs_act);
col := crs and r.tx_en;
v.speed(1) := r.speed(0); v.speed(0) := txi.speed;
if r.tx_en = '1' then
v.rcnt := r.rcnt - 1;
if r.speed(1) = '1' then
v.switch := not r.switch;
if r.switch = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
else
v.zero := '0';
if r.rcnt = "0001" then
v.zero := '1';
end if;
if r.zero = '1' then
v.switch := not r.switch;
v.rcnt := "1001";
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
end if;
if (r.switch and r.zero) = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
end if;
end if;
end if;
collision := col and not r.fullduplex(1);
--main fsm
case r.main_state is
when idle =>
v.transmitting := '0';
if rmii = 1 then
v.rcnt := "1001"; v.switch := '0';
end if;
if (start and not r.deferring) = '1' then
v.main_state := preamble; v.transmitting := '1'; v.tx_en := '1';
v.byte_count := (others => '1'); v.status := (others => '0');
v.read := not r.read; v.start(nsync) := r.start(nsync-1);
elsif start = '1' then
frame_waiting := '1';
end if;
v.txd := "0101"; v.cnt := "1110";
when preamble =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.txd := "1101"; v.main_state := sfd;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when sfd =>
if tx_done = '1' then
v.main_state := data1; v.icnt := (others => '0'); v.crc_en := '1';
v.crc := (others => '1'); v.byte_count := (others => '0');
v.txd := txi.data(27 downto 24);
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data1 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
v.main_state := data2; v.icnt := r.icnt + 1;
case index is
when 0 => v.txd := r.data(31 downto 28);
when 1 => v.txd := r.data(23 downto 20);
when 2 => v.txd := r.data(15 downto 12);
when 3 => v.txd := r.data(7 downto 4);
when others => null;
end case;
if v.byte_count = txi.len then
v.tx_en := '1';
if conv_integer(v.byte_count) >= 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
elsif index = 3 then
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data2 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.main_state := data1;
case index is
when 0 => v.txd := r.data(27 downto 24);
when 1 => v.txd := r.data(19 downto 16);
when 2 => v.txd := r.data(11 downto 8);
when 3 => v.txd := r.data(3 downto 0);
when others => null;
end case;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad1 =>
if tx_done = '1' then
v.main_state := pad2;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad2 =>
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
if conv_integer(v.byte_count) = 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when fcs =>
if tx_done = '1' then
v.cnt := r.cnt + 1; v.crc_en := '0'; index := conv_integer(r.cnt);
case index is
when 0 => v.txd := mirror2(not v.crc(31 downto 28));
when 1 => v.txd := mirror2(not r.crc(27 downto 24));
when 2 => v.txd := mirror2(not r.crc(23 downto 20));
when 3 => v.txd := mirror2(not r.crc(19 downto 16));
when 4 => v.txd := mirror2(not r.crc(15 downto 12));
when 5 => v.txd := mirror2(not r.crc(11 downto 8));
when 6 => v.txd := mirror2(not r.crc(7 downto 4));
when 7 => v.txd := mirror2(not r.crc(3 downto 0));
v.main_state := fcs2;
when others => null;
end case;
end if;
when fcs2 =>
if tx_done = '1' then
v.main_state := finish; v.tx_en := '0';
end if;
when finish =>
v.tx_en := '0'; v.transmitting := '0'; v.main_state := idle;
v.retry_cnt := (others => '0'); v.done := not r.done;
when send_jam =>
if tx_done = '1' then
v.cnt := "0110"; v.main_state := send_jam2; v.crc_en := '0';
end if;
when send_jam2 =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.main_state := check_attempts; v.retry_cnt := r.retry_cnt + 1;
v.tx_en := '0';
end if;
end if;
when check_attempts =>
v.transmitting := '0';
if r.retry_cnt = maxattempts then
v.main_state := finish; v.status(1) := '1';
else
v.main_state := calc_backoff; v.restart := not r.restart;
end if;
v.tx_en := '0';
when calc_backoff =>
v.delay_val := (others => '0');
for i in 1 to backoff_limit-1 loop
if i < conv_integer(r.retry_cnt)+1 then
v.delay_val(i) := r.random(i);
end if;
end loop;
v.main_state := wait_backoff; v.slot_count := (others => '1');
when wait_backoff =>
if conv_integer(r.delay_val) = 0 then
v.main_state := idle;
end if;
v.slot_count := r.slot_count - 1;
if conv_integer(r.slot_count) = 0 then
v.slot_count := (others => '1'); v.delay_val := r.delay_val - 1;
end if;
when others =>
v.main_state := idle;
end case;
--random values;
v.random := r.random(8 downto 0) & (not (r.random(2) xor r.random(9)));
--deference
case r.def_state is
when monitor =>
v.was_transmitting := '0';
if ( (crs and not r.fullduplex(1)) or
(r.transmitting and r.fullduplex(1)) ) = '1' then
v.deferring := '1'; v.def_state := def_on;
v.was_transmitting := r.transmitting;
end if;
when def_on =>
v.was_transmitting := r.was_transmitting or r.transmitting;
if r.fullduplex(1) = '1' then
if r.transmitting = '0' then v.def_state := ifg1; end if;
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
else
if (r.transmitting or crs) = '0' then
v.def_state := ifg1; v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
end if;
when ifg1 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.def_state := ifg2;
v.ifg_cycls := ifg_sel(rmii, 0, r.speed(1));
elsif (crs and not r.fullduplex(1)) = '1' then
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
when ifg2 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.deferring := '0';
if (r.fullduplex(1) or not frame_waiting) = '1' then
v.def_state := monitor;
elsif frame_waiting = '1' then
v.def_state := frame_waitingst;
end if;
end if;
when frame_waitingst =>
if frame_waiting = '0' then v.def_state := monitor; end if;
when others => v.def_state := monitor;
end case;
if rmii = 1 then
v.txd_msb := v.txd(3 downto 2);
end if;
if txrst = '0' then
v.main_state := idle; v.random := (others => '0');
v.def_state := monitor; v.deferring := '0'; v.tx_en := '0';
v.done := '0'; v.restart := '0'; v.read := '0';
v.start := (others => '0'); v.read_ack := (others => '0');
v.icnt := (others => '0'); v.delay_val := (others => '0');
v.ifg_cycls := (others => '0');
v.crs_act := '0';
v.slot_count := (others => '1');
v.retry_cnt := (others => '0');
v.cnt := (others => '0');
end if;
rin <= v;
txo.tx_er <= '0';
txo.tx_en <= r.tx_en;
txo.txd <= r.txd;
txo.done <= r.done;
txo.read <= r.read;
txo.restart <= r.restart;
txo.status <= r.status;
end process;
gmiimode0 : if gmiimode = 0 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
if rst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
if txi.datavalid = '1' then r <= rin; end if;
if rst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
if txi.datavalid = '1' then
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end if;
end process;
end generate;
end architecture;
|
--------------------------------------------------------------------------------
-- ion_tcm_data.vhdl -- Tightly Coupled Memory for the data space.
--------------------------------------------------------------------------------
-- FIXME explain!
--
-- REFERENCES
-- [1] ion_design_notes.pdf -- ION project design notes.
--------------------------------------------------------------------------------
--
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_TCM_DATA is
generic(
-- Size of TCM block in 32-bit words. Set to zero to disable TCM.
SIZE : integer := 4096;
-- Initial contents of TCM. Default is zeros.
INIT_DATA : t_obj_code := zero_objcode(16)
);
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
EN_I : in std_logic;
MEM_MOSI_I : in t_cpumem_mosi;
MEM_MISO_O : out t_cpumem_miso
);
end;
architecture rtl of ION_TCM_DATA is
constant TCM_ADDR_SIZE : integer := log2(SIZE);
subtype t_tcm_address is std_logic_vector(TCM_ADDR_SIZE-1 downto 2);
signal tcm_addr : t_tcm_address;
signal tcm_rd_data : t_word;
signal tcm_rd_data0 : t_byte;
signal tcm_rd_data1 : t_byte;
signal tcm_rd_data2 : t_byte;
signal tcm_rd_data3 : t_byte;
signal wr_data0 : t_byte;
signal wr_data1 : t_byte;
signal wr_data2 : t_byte;
signal wr_data3 : t_byte;
signal tcm_ram0: t_byte_table(0 to ((SIZE/4)-1)) :=
objcode_to_btable(INIT_DATA, SIZE/4, 0);
signal tcm_ram1: t_byte_table(0 to ((SIZE/4)-1)) :=
objcode_to_btable(INIT_DATA, SIZE/4, 1);
signal tcm_ram2: t_byte_table(0 to ((SIZE/4)-1)) :=
objcode_to_btable(INIT_DATA, SIZE/4, 2);
signal tcm_ram3: t_byte_table(0 to ((SIZE/4)-1)) :=
objcode_to_btable(INIT_DATA, SIZE/4, 3);
begin
tcm_addr <= MEM_MOSI_I.addr(tcm_addr'high downto 2);
--------------------------------------------------------------------------------
---- Memory block inference.
-- We ned to implement the TCM as four independent blocks because it's not
-- possible to just infer a BRAM with byte enables. We just don't want to
-- instantiate vendor-specific BRAM entities.
tcm_memory_block0:
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
tcm_rd_data0 <= tcm_ram0(conv_integer(tcm_addr));
if MEM_MOSI_I.wr_be(0)='1' and EN_I='1' then
tcm_ram0(conv_integer(unsigned(tcm_addr))) <= wr_data0;
end if;
end if;
end process tcm_memory_block0;
tcm_memory_block1:
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
tcm_rd_data1 <= tcm_ram1(conv_integer(tcm_addr));
if MEM_MOSI_I.wr_be(1)='1' and EN_I='1' then
tcm_ram1(conv_integer(unsigned(tcm_addr))) <= wr_data1;
end if;
end if;
end process tcm_memory_block1;
tcm_memory_block2:
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
tcm_rd_data2 <= tcm_ram2(conv_integer(tcm_addr));
if MEM_MOSI_I.wr_be(2)='1' and EN_I='1' then
tcm_ram2(conv_integer(unsigned(tcm_addr))) <= wr_data2;
end if;
end if;
end process tcm_memory_block2;
tcm_memory_block3:
process(CLK_I)
begin
if (CLK_I'event and CLK_I='1') then
tcm_rd_data3 <= tcm_ram3(conv_integer(tcm_addr));
if MEM_MOSI_I.wr_be(3)='1' and EN_I='1' then
tcm_ram3(conv_integer(unsigned(tcm_addr))) <= wr_data3;
end if;
end if;
end process tcm_memory_block3;
wr_data0 <= MEM_MOSI_I.wr_data( 7 downto 0);
wr_data1 <= MEM_MOSI_I.wr_data(15 downto 8);
wr_data2 <= MEM_MOSI_I.wr_data(23 downto 16);
wr_data3 <= MEM_MOSI_I.wr_data(31 downto 24);
MEM_MISO_O.rd_data <= tcm_rd_data3 & tcm_rd_data2 & tcm_rd_data1 & tcm_rd_data0;
MEM_MISO_O.mwait <= '0';
end architecture rtl;
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_sram_arty (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-11-17 1071 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:02:47 05/20/2016
-- Design Name:
-- Module Name: mandelbrot - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.CONSTANTS.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mandelbrot is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
BTNU : in STD_LOGIC;
BTNC : in STD_LOGIC;
BTND : in STD_LOGIC;
BTNL : in STD_LOGIC;
BTNR : in STD_LOGIC;
inib : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0)); -- blue output);
end mandelbrot;
architecture Behavioral of mandelbrot is
component muxperso
Port ( ADDR1 : in STD_LOGIC_vector(ADDR_BIT_MUX-1 downto 0);
data_write1 : in STD_LOGIC;
data_in1 : in STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0);
ADDR2 : in STD_LOGIC_vector(ADDR_BIT_MUX-1 downto 0);
data_write2 : in STD_LOGIC;
data_in2 : in STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0);
-- ADDR3 : in STD_LOGIC_vector(ADDR_BIT_MUX-1 downto 0);
-- data_write3 : in STD_LOGIC;
-- data_in3 : in STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0);
-- ADDR4 : in STD_LOGIC_vector(ADDR_BIT_MUX-1 downto 0);
-- data_write4 : in STD_LOGIC;
-- data_in4 : in STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0);
ADDR : out STD_LOGIC_vector(ADDR_BIT-1 downto 0);
data_write : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0));
end component ;
component TOP_LEVEL is
generic( ystart : std_logic_vector(31 downto 0) := x"00000000");
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
inib : in std_logic;
bleft : in STD_LOGIC;
bright : in STD_LOGIC;
bup : in STD_LOGIC;
bdwn : in STD_LOGIC;
bctr : in STD_LOGIC;
ADDR : out std_logic_vector( ADDR_BIT_MUX-1 downto 0);
data_write : out STD_LOGIC;
data_out : out std_logic_vector(ITER_RANGE - 1 downto 0));
end component;
component VGA_bitmap_640x480
port(--clk : in std_logic;
clk_vga : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
iter : out std_logic_vector(7 downto 0); -- iter output
ADDR1 : in std_logic_vector(17 downto 0);
data_in1 : in std_logic_vector(7 downto 0);
data_write1 : in std_logic;
ADDR2 : in std_logic_vector(17 downto 0);
data_in2 : in std_logic_vector(7 downto 0);
data_write2 : in std_logic;
ADDR3 : in std_logic_vector(17 downto 0);
data_in3 : in std_logic_vector(7 downto 0);
data_write3 : in std_logic;
ADDR4 : in std_logic_vector(17 downto 0);
data_in4 : in std_logic_vector(7 downto 0);
data_write4 : in std_logic);
end component;
component Colorgen
Port ( iter : in STD_LOGIC_VECTOR (7 downto 0);
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0)); -- blue output
end component;
component pulse_filter
Generic ( DEBNC_CLOCKS : INTEGER range 2 to (INTEGER'high) := 2**16);
Port (
SIGNAL_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
SIGNAL_O : out STD_LOGIC
);
end component;
signal BTNUB, BTNCB, BTNDB, BTNRB, BTNLB, data_write1, data_write2,data_write3, data_write4,data_write5, data_write6,data_write7, data_write8, clk50, clk100_sig: std_logic;
signal data_writeVGA1,data_writeVGA2,data_writeVGA3,data_writeVGA4 : std_logic;
signal iterS, data_out1,data_out2, data_out3 ,data_out4, data_out5,data_out6, data_out7 ,data_out8 : std_logic_vector(7 downto 0);
signal ADDR1, ADDR2, ADDR3, ADDR4, ADDR5, ADDR6, ADDR7, ADDR8 : std_logic_vector(ADDR_BIT_MUX-1 downto 0);
signal ADDRVGA1, ADDRVGA2, ADDRVGA3, ADDRVGA4 : std_logic_vector(ADDR_BIT-1 downto 0);
signal data_outVGA1,data_outVGA2, data_outVGA3 ,data_outVGA4 : std_logic_vector(7 downto 0);
begin
m1:muxperso
port map(ADDR1,
data_write1,
data_out1,
ADDR2,
data_write2,
data_out2,
ADDRVGA1,
data_writeVGA1,
data_outVGA1);
m2:muxperso
port map(ADDR3,
data_write3,
data_out3,
ADDR4,
data_write4,
data_out4,
ADDRVGA2,
data_writeVGA2,
data_outVGA2);
m3:muxperso
port map(ADDR5,
data_write5,
data_out5,
ADDR6,
data_write6,
data_out6,
ADDRVGA3,
data_writeVGA3,
data_outVGA3);
m4:muxperso
port map(ADDR7,
data_write7,
data_out7,
ADDR8,
data_write8,
data_out8,
ADDRVGA4,
data_writeVGA4,
data_outVGA4);
I1: TOP_LEVEL
generic map(x"F0000000")
port map(
clk,
reset,
inib,
BTNLB,
BTNRB,
BTNUB,
BTNDB,
BTNCB,
ADDR1,
data_write1,
data_out1);
I2: TOP_LEVEL
generic map(x"F4000000")
port map(
clk,
reset,
inib,
BTNLB,
BTNRB,
BTNUB,
BTNDB,
BTNCB,
ADDR2,
data_write2,
data_out2);
I3: TOP_LEVEL
generic map(x"F8000000")
port map(
clk,
reset,
inib,
BTNLB,
BTNRB,
BTNUB,
BTNDB,
BTNCB,
ADDR3,
data_write3,
data_out3);
I4: TOP_LEVEL
generic map(x"FC000000")
port map(
clk,
reset,
inib,
BTNLB,
BTNRB,
BTNUB,
BTNDB,
BTNCB,
ADDR4,
data_write4,
data_out4);
I5: TOP_LEVEL
generic map(x"00000000")
port map(
clk,
reset,
inib,
BTNLB,
BTNRB,
BTNUB,
BTNDB,
BTNCB,
ADDR5,
data_write5,
data_out5);
I6: TOP_LEVEL
generic map(x"04000000")
port map(
clk,
reset,
inib,
BTNLB,
BTNRB,
BTNUB,
BTNDB,
BTNCB,
ADDR6,
data_write6,
data_out6);
I7: TOP_LEVEL
generic map(x"08000000")
port map(
clk,
reset,
inib,
BTNLB,
BTNRB,
BTNUB,
BTNDB,
BTNCB,
ADDR7,
data_write7,
data_out7);
I8: TOP_LEVEL
generic map(x"0C000000")
port map(
clk,
reset,
inib,
BTNLB,
BTNRB,
BTNUB,
BTNDB,
BTNCB,
ADDR8,
data_write8,
data_out8);
InstColorgen: Colorgen
port map(iterS,VGA_red,VGA_green,VGA_blue);
InstVGA: VGA_bitmap_640x480
port map(
clk,
reset,
VGA_hs,
VGA_vs,
iterS,
ADDRVGA1,
data_outVGA1,
data_writeVGA1,
ADDRVGA2,
data_outVGA2,
data_writeVGA2,
ADDRVGA3,
data_outVGA3,
data_writeVGA3,
ADDRVGA4,
data_outVGA4,
data_writeVGA4);
InstancepulsBTNU: pulse_filter
port map(BTNU,
clk,
BTNUB);
InstancepulsBTND: pulse_filter
port map(BTND,
clk,
BTNDB);
InstancepulsBTNL: pulse_filter
port map(BTNL,
clk,
BTNLB);
InstancepulsBTNR: pulse_filter
port map(BTNR,
clk,
BTNRB);
InstancepulsBTNC: pulse_filter
port map(BTNC,
clk,
BTNCB);
end Behavioral;
|
-------------------------------
---- Project: EurySPACE CCSDS RX/TX with wishbone interface
---- Design Name: ccsds_tx_framer
---- Version: 1.0.0
---- Description:
---- Implementation of standard CCSDS 132.0-B-2
-------------------------------
---- Author(s):
---- Guillaume REMBERT
-------------------------------
---- Licence:
---- MIT
-------------------------------
---- Changes list:
---- 2016/02/27: initial release
---- 2016/10/20: rework
---- 2016/10/24: multiple footers generation to ensure higher speed than input max data rate (CCSDS_TX_FRAMER_DATA_BUS_SIZE*CLK_FREQ bits/sec)
---- 2016/10/31: ressources optimization
---- 2016/11/03: add only idle data insertion
-------------------------------
--TODO: trailer as option
--HEADER (6 up to 70 bytes) / before data / f(idle)
--TRANSFER FRAME DATA FIELD => Variable
--TRAILER (2 up to 6 bytes) / after data / f(data, header)
-- libraries used
library ieee;
use ieee.std_logic_1164.all;
--=============================================================================
-- Entity declaration for ccsds_tx / unitary tx framer inputs and outputs
--=============================================================================
entity ccsds_tx_framer is
generic(
constant CCSDS_TX_FRAMER_DATA_BUS_SIZE: integer; -- in bits
constant CCSDS_TX_FRAMER_DATA_LENGTH: integer; -- in Bytes
constant CCSDS_TX_FRAMER_FOOTER_LENGTH: integer; -- in Bytes
constant CCSDS_TX_FRAMER_HEADER_LENGTH: integer; -- in Bytes
constant CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO: integer := 16 -- activated max framer parallelism speed ratio / 1 = full speed / 2 = wishbone bus non-pipelined write max speed / ... / CCSDS_TX_FRAMER_DATA_BUS_SIZE = external serial data
);
port(
-- inputs
clk_i: in std_logic;
dat_i: in std_logic_vector(CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto 0);
dat_val_i: in std_logic;
rst_i: in std_logic;
-- outputs
dat_o: out std_logic_vector((CCSDS_TX_FRAMER_HEADER_LENGTH+CCSDS_TX_FRAMER_FOOTER_LENGTH+CCSDS_TX_FRAMER_DATA_LENGTH)*8-1 downto 0);
dat_nxt_o: out std_logic;
dat_val_o: out std_logic;
idl_o: out std_logic
);
end ccsds_tx_framer;
--=============================================================================
-- architecture declaration / internal components and connections
--=============================================================================
architecture structure of ccsds_tx_framer is
component ccsds_tx_header is
generic(
constant CCSDS_TX_HEADER_LENGTH: integer
);
port(
clk_i: in std_logic;
idl_i: in std_logic;
nxt_i: in std_logic;
rst_i: in std_logic;
dat_o: out std_logic_vector(CCSDS_TX_HEADER_LENGTH*8-1 downto 0);
dat_val_o: out std_logic
);
end component;
component ccsds_tx_footer is
generic(
constant CCSDS_TX_FOOTER_DATA_LENGTH : integer;
constant CCSDS_TX_FOOTER_LENGTH: integer
);
port(
clk_i: in std_logic;
rst_i: in std_logic;
nxt_i: in std_logic;
bus_o: out std_logic;
dat_i: in std_logic_vector(CCSDS_TX_FOOTER_DATA_LENGTH*8-1 downto 0);
dat_o: out std_logic_vector((CCSDS_TX_FOOTER_LENGTH+CCSDS_TX_FOOTER_DATA_LENGTH)*8-1 downto 0);
dat_val_o: out std_logic
);
end component;
-- internal constants
constant CCSDS_TX_FRAMER_FOOTER_NUMBER : integer := CCSDS_TX_FRAMER_DATA_BUS_SIZE*((CCSDS_TX_FRAMER_HEADER_LENGTH+CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_FOOTER_LENGTH)*8+1)/(CCSDS_TX_FRAMER_DATA_LENGTH*8*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO)+1; -- 8*(HEAD+DATA+FOOT+1) clks / crc ; BUS bits / parallelism * clk ; DATA*8 bits / footer
constant CCSDS_TX_FRAMER_OID_PATTERN: std_logic_vector(CCSDS_TX_FRAMER_DATA_LENGTH*8-1 downto 0) := (others => '1'); -- Only Idle Data Pattern transmitted (jam payload for frame stuffing)
-- internal variable signals
type frame_array is array (CCSDS_TX_FRAMER_FOOTER_NUMBER-1 downto 0) of std_logic_vector((CCSDS_TX_FRAMER_FOOTER_LENGTH+CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_HEADER_LENGTH)*8-1 downto 0);
signal wire_header_data: std_logic_vector(CCSDS_TX_FRAMER_HEADER_LENGTH*8-1 downto 0);
signal wire_footer_data_o: frame_array;
signal wire_header_data_valid: std_logic;
signal wire_footer_data_valid: std_logic_vector(CCSDS_TX_FRAMER_FOOTER_NUMBER-1 downto 0);
signal wire_header_next: std_logic := '0';
signal wire_header_idle: std_logic := '0';
signal wire_footer_next: std_logic_vector(CCSDS_TX_FRAMER_FOOTER_NUMBER-1 downto 0) := (others => '0');
signal wire_footer_busy: std_logic_vector(CCSDS_TX_FRAMER_FOOTER_NUMBER-1 downto 0);
signal reg_next_frame: std_logic_vector(CCSDS_TX_FRAMER_DATA_LENGTH*8-CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto 0);
signal reg_current_frame: std_logic_vector((CCSDS_TX_FRAMER_DATA_LENGTH)*8-1 downto 0);
signal reg_processing_frame: std_logic_vector((CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_HEADER_LENGTH)*8-1 downto 0);
signal next_processing_frame_pointer : integer range 0 to CCSDS_TX_FRAMER_FOOTER_NUMBER-1 := 0;
-- components instanciation and mapping
begin
tx_header_0: ccsds_tx_header
generic map(
CCSDS_TX_HEADER_LENGTH => CCSDS_TX_FRAMER_HEADER_LENGTH
)
port map(
clk_i => clk_i,
idl_i => wire_header_idle,
nxt_i => wire_header_next,
rst_i => rst_i,
dat_o => wire_header_data,
dat_val_o => wire_header_data_valid
);
FOOTERGEN:
for i in 0 to CCSDS_TX_FRAMER_FOOTER_NUMBER-1 generate
tx_footer_x : ccsds_tx_footer
generic map(
CCSDS_TX_FOOTER_DATA_LENGTH => CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_HEADER_LENGTH,
CCSDS_TX_FOOTER_LENGTH => CCSDS_TX_FRAMER_FOOTER_LENGTH
)
port map(
clk_i => clk_i,
rst_i => rst_i,
nxt_i => wire_footer_next(i),
bus_o => wire_footer_busy(i),
dat_i => reg_processing_frame,
dat_o => wire_footer_data_o(i),
dat_val_o => wire_footer_data_valid(i)
);
end generate FOOTERGEN;
-- presynthesis checks
CHKFRAMERP0 : if ((CCSDS_TX_FRAMER_DATA_LENGTH*8) mod CCSDS_TX_FRAMER_DATA_BUS_SIZE /= 0) generate
process
begin
report "ERROR: FRAMER DATA LENGTH SHOULD BE A MULTIPLE OF FRAMER DATA BUS SIZE" severity failure;
wait;
end process;
end generate CHKFRAMERP0;
CHKFRAMERP1 : if ((CCSDS_TX_FRAMER_DATA_LENGTH) = 0) generate
process
begin
report "ERROR: FRAMER DATA LENGTH CANNOT BE 0" severity failure;
wait;
end process;
end generate CHKFRAMERP1;
CHKFRAMERP2 : if ((CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO) = 0) generate
process
begin
report "ERROR: PARALLELISM MAX RATIO CANNOT BE 0" severity failure;
wait;
end process;
end generate CHKFRAMERP2;
-- internal processing
--=============================================================================
-- Begin of frameroutputp
-- Generate valid frame output on footer data_valid signal
--=============================================================================
-- read: rst_i, wire_footer_data, wire_footer_data_valid
-- write: dat_o, dat_val_o
-- r/w: next_valid_frame_pointer
FRAMEROUTPUTP: process (clk_i)
variable next_valid_frame_pointer : integer range 0 to CCSDS_TX_FRAMER_FOOTER_NUMBER-1 := 0;
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
next_valid_frame_pointer := 0;
dat_o <= (others => '0');
dat_val_o <= '0';
-- generating valid frames output
else
dat_o <= wire_footer_data_o(next_valid_frame_pointer);
if (wire_footer_data_valid(next_valid_frame_pointer) = '1') then
dat_val_o <= '1';
if (next_valid_frame_pointer < (CCSDS_TX_FRAMER_FOOTER_NUMBER-1)) then
next_valid_frame_pointer := (next_valid_frame_pointer + 1);
else
next_valid_frame_pointer := 0;
end if;
else
dat_o <= (others => '0');
dat_val_o <= '0';
end if;
end if;
end if;
end process;
--=============================================================================
-- Begin of framerprocessp
-- Start footer computation on valid header signal
--=============================================================================
-- read: wire_header_data, wire_header_data_valid
-- write: next_processing_frame_pointer, reg_processing_frame, wire_footer_next
-- r/w:
FRAMERPROCESSP: process (clk_i)
variable reg_next_processing_frame: std_logic_vector((CCSDS_TX_FRAMER_DATA_LENGTH)*8-1 downto 0);
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
next_processing_frame_pointer <= 0;
wire_footer_next <= (others => '0');
else
if(wire_header_data_valid = '1') then
reg_processing_frame((CCSDS_TX_FRAMER_DATA_LENGTH+CCSDS_TX_FRAMER_HEADER_LENGTH)*8-1 downto CCSDS_TX_FRAMER_DATA_LENGTH*8) <= wire_header_data;
-- idle data to be used
if (wire_header_data(10 downto 0) = "11111111110") then
reg_processing_frame(CCSDS_TX_FRAMER_DATA_LENGTH*8-1 downto 0) <= CCSDS_TX_FRAMER_OID_PATTERN;
reg_next_processing_frame := reg_current_frame;
-- current data to be used
else
-- continuous data flow header is one clk in advance
if (CCSDS_TX_FRAMER_DATA_LENGTH*8 = CCSDS_TX_FRAMER_DATA_BUS_SIZE) and (CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO = 1) then
reg_processing_frame(CCSDS_TX_FRAMER_DATA_LENGTH*8-1 downto 0) <= reg_next_processing_frame;
reg_next_processing_frame := reg_current_frame;
-- header is synchronous with data
else
reg_processing_frame(CCSDS_TX_FRAMER_DATA_LENGTH*8-1 downto 0) <= reg_current_frame;
end if;
end if;
wire_footer_next(next_processing_frame_pointer) <= '1';
if (next_processing_frame_pointer = CCSDS_TX_FRAMER_FOOTER_NUMBER-1) then
next_processing_frame_pointer <= 0;
else
next_processing_frame_pointer <= (next_processing_frame_pointer + 1);
end if;
end if;
if (next_processing_frame_pointer = 0) then
wire_footer_next(CCSDS_TX_FRAMER_FOOTER_NUMBER-1) <= '0';
else
wire_footer_next(next_processing_frame_pointer-1) <= '0';
end if;
end if;
end if;
end process;
--=============================================================================
-- Begin of framergeneratep
-- Generate next_frame, start next header generation
--=============================================================================
-- read: dat_val_i, rst_i
-- write: wire_header_next, reg_current_frame, reg_next_frame, dat_nxt_o, idl_o
-- r/w:
FRAMERGENERATEP: process (clk_i)
variable next_frame_write_pos: integer range 0 to (CCSDS_TX_FRAMER_DATA_LENGTH*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1 := (CCSDS_TX_FRAMER_DATA_LENGTH*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
variable frame_output_counter: integer range 0 to (CCSDS_TX_FRAMER_DATA_LENGTH*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1 := 0;
variable current_frame_ready: std_logic := '0';
begin
-- on each clock rising edge
if rising_edge(clk_i) then
-- reset signal received
if (rst_i = '1') then
current_frame_ready := '0';
wire_header_next <= '0';
next_frame_write_pos := (CCSDS_TX_FRAMER_DATA_LENGTH*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
frame_output_counter := 0;
idl_o <= '0';
dat_nxt_o <= '0';
else
-- valid data is presented
if (dat_val_i = '1') then
-- next frame is full
if (next_frame_write_pos = 0) then
reg_current_frame(CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto 0) <= dat_i;
reg_current_frame(CCSDS_TX_FRAMER_DATA_LENGTH*8-1 downto CCSDS_TX_FRAMER_DATA_BUS_SIZE) <= reg_next_frame;
-- time to start frame computation
if (frame_output_counter = 0) then
-- CRC is ready to compute
if (wire_footer_busy(next_processing_frame_pointer) = '0') then
frame_output_counter := (CCSDS_TX_FRAMER_DATA_LENGTH*8*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
wire_header_next <= '1';
wire_header_idle <= '0';
idl_o <= '0';
-- source data rate overflow / stop buffer output
else
dat_nxt_o <= '0';
end if;
else
frame_output_counter := frame_output_counter - 1;
-- signal a frame ready for computation
if (current_frame_ready = '0') then
wire_header_next <= '0';
current_frame_ready := '1';
-- source data rate overflow
else
dat_nxt_o <= '0';
end if;
end if;
next_frame_write_pos := CCSDS_TX_FRAMER_DATA_LENGTH*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE-1;
else
-- filling next frame
reg_next_frame(next_frame_write_pos*CCSDS_TX_FRAMER_DATA_BUS_SIZE-1 downto (next_frame_write_pos-1)*CCSDS_TX_FRAMER_DATA_BUS_SIZE) <= dat_i;
next_frame_write_pos := next_frame_write_pos-1;
-- time to start frame computation
if (frame_output_counter = 0) then
-- CRC is ready to compute
if (wire_footer_busy(next_processing_frame_pointer) = '0') then
dat_nxt_o <= '1';
frame_output_counter := (CCSDS_TX_FRAMER_DATA_LENGTH*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
-- no frame is ready / inserting idle data
if (current_frame_ready = '0') then
wire_header_next <= '1';
wire_header_idle <= '1';
idl_o <= '1';
-- a frame is ready
else
wire_header_next <= '1';
wire_header_idle <= '0';
current_frame_ready := '0';
idl_o <= '0';
end if;
else
dat_nxt_o <= '0';
end if;
else
-- stop data before overflow
if (next_frame_write_pos = 1) and (current_frame_ready = '1') then
dat_nxt_o <= '0';
end if;
frame_output_counter := frame_output_counter - 1;
wire_header_next <= '0';
end if;
end if;
-- no valid data
else
-- time to start frame computation
if (frame_output_counter = 0) then
-- CRC is ready to compute
if (wire_footer_busy(next_processing_frame_pointer) = '0') then
dat_nxt_o <= '1';
frame_output_counter := (CCSDS_TX_FRAMER_DATA_LENGTH*CCSDS_TX_FRAMER_PARALLELISM_MAX_RATIO*8/CCSDS_TX_FRAMER_DATA_BUS_SIZE)-1;
if (current_frame_ready = '0') then
wire_header_next <= '1';
wire_header_idle <= '1';
idl_o <= '1';
else
wire_header_next <= '1';
wire_header_idle <= '0';
current_frame_ready := '0';
idl_o <= '0';
end if;
end if;
else
wire_header_next <= '0';
frame_output_counter := frame_output_counter - 1;
end if;
end if;
end if;
end if;
end process;
end structure;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Mon Sep 18 12:06:15 2017
-- Host : PC4719 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_sim_netlist.vhdl
-- Design : vio_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7k160tffg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder is
port (
s_drdy_i : out STD_LOGIC;
\wr_en_reg[4]_0\ : out STD_LOGIC;
\wr_en_reg[4]_1\ : out STD_LOGIC;
\wr_en_reg[4]_2\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_do_i : out STD_LOGIC_VECTOR ( 15 downto 0 );
s_rst_o : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 15 downto 0 );
\out\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 16 downto 0 );
s_dwe_o : in STD_LOGIC;
s_den_o : in STD_LOGIC;
\Bus_Data_out_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder is
signal Hold_probe_in : STD_LOGIC;
signal clear_int : STD_LOGIC;
signal committ_int : STD_LOGIC;
signal \data_info_probe_in__67\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal int_cnt_rst : STD_LOGIC;
signal probe_out_modified : STD_LOGIC_VECTOR ( 15 downto 0 );
signal rd_en_p1 : STD_LOGIC;
signal rd_en_p2 : STD_LOGIC;
signal wr_control_reg : STD_LOGIC;
signal \wr_en[2]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[2]_i_2_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_1_n_0\ : STD_LOGIC;
signal \wr_en[4]_i_6_n_0\ : STD_LOGIC;
signal \^wr_en_reg[4]_0\ : STD_LOGIC;
signal \^wr_en_reg[4]_1\ : STD_LOGIC;
signal \^wr_en_reg[4]_2\ : STD_LOGIC;
signal wr_probe_out_modified : STD_LOGIC;
signal xsdb_addr_2_0_p1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xsdb_addr_2_0_p2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xsdb_addr_8_p1 : STD_LOGIC;
signal xsdb_addr_8_p2 : STD_LOGIC;
signal xsdb_drdy_i_1_n_0 : STD_LOGIC;
signal xsdb_rd : STD_LOGIC;
signal xsdb_wr : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Bus_data_out[12]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \Bus_data_out[13]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Bus_data_out[14]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \Bus_data_out[15]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \wr_en[2]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \wr_en[4]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wr_en[4]_i_6\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of xsdb_drdy_i_1 : label is "soft_lutpair14";
begin
\wr_en_reg[4]_0\ <= \^wr_en_reg[4]_0\;
\wr_en_reg[4]_1\ <= \^wr_en_reg[4]_1\;
\wr_en_reg[4]_2\ <= \^wr_en_reg[4]_2\;
\Bus_data_out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AF00AF000FC000C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(0),
I1 => probe_out_modified(0),
I2 => xsdb_addr_2_0_p2(2),
I3 => xsdb_addr_2_0_p2(1),
I4 => committ_int,
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(0)
);
\Bus_data_out[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(10),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(10),
O => \data_info_probe_in__67\(10)
);
\Bus_data_out[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(11),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(11),
O => \data_info_probe_in__67\(11)
);
\Bus_data_out[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(12),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(12)
);
\Bus_data_out[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(13),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(13)
);
\Bus_data_out[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(14),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(14)
);
\Bus_data_out[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(1),
I2 => probe_out_modified(15),
I3 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(15)
);
\Bus_data_out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0000FC0A00000C0"
)
port map (
I0 => \Bus_Data_out_reg[11]\(1),
I1 => probe_out_modified(1),
I2 => xsdb_addr_2_0_p2(2),
I3 => xsdb_addr_2_0_p2(1),
I4 => xsdb_addr_2_0_p2(0),
I5 => clear_int,
O => \data_info_probe_in__67\(1)
);
\Bus_data_out[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A000000F00CFCF"
)
port map (
I0 => \Bus_Data_out_reg[11]\(2),
I1 => probe_out_modified(2),
I2 => xsdb_addr_2_0_p2(2),
I3 => int_cnt_rst,
I4 => xsdb_addr_2_0_p2(1),
I5 => xsdb_addr_2_0_p2(0),
O => \data_info_probe_in__67\(2)
);
\Bus_data_out[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(3),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(3),
O => \data_info_probe_in__67\(3)
);
\Bus_data_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(4),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(4),
O => \data_info_probe_in__67\(4)
);
\Bus_data_out[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(5),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(5),
O => \data_info_probe_in__67\(5)
);
\Bus_data_out[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(6),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(6),
O => \data_info_probe_in__67\(6)
);
\Bus_data_out[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(7),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(7),
O => \data_info_probe_in__67\(7)
);
\Bus_data_out[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(8),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(8),
O => \data_info_probe_in__67\(8)
);
\Bus_data_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"88200020"
)
port map (
I0 => xsdb_addr_2_0_p2(2),
I1 => xsdb_addr_2_0_p2(0),
I2 => probe_out_modified(9),
I3 => xsdb_addr_2_0_p2(1),
I4 => \Bus_Data_out_reg[11]\(9),
O => \data_info_probe_in__67\(9)
);
\Bus_data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(0),
Q => s_do_i(0),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(10),
Q => s_do_i(10),
R => xsdb_addr_8_p2
);
\bus_data_out_reg[11]_RnM\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(11),
Q => s_do_i(11),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(12),
Q => s_do_i(12),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(13),
Q => s_do_i(13),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(14),
Q => s_do_i(14),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(15),
Q => s_do_i(15),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(1),
Q => s_do_i(1),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(2),
Q => s_do_i(2),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(3),
Q => s_do_i(3),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(4),
Q => s_do_i(4),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(5),
Q => s_do_i(5),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(6),
Q => s_do_i(6),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(7),
Q => s_do_i(7),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(8),
Q => s_do_i(8),
R => xsdb_addr_8_p2
);
\Bus_data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \data_info_probe_in__67\(9),
Q => s_do_i(9),
R => xsdb_addr_8_p2
);
Hold_probe_in_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(3),
Q => Hold_probe_in,
R => s_rst_o
);
clear_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(1),
Q => clear_int,
R => s_rst_o
);
committ_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(0),
Q => committ_int,
R => s_rst_o
);
int_cnt_rst_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_control_reg,
D => Q(2),
Q => int_cnt_rst,
R => s_rst_o
);
\probe_in_reg[3]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => Hold_probe_in,
O => E(0)
);
\probe_out_modified_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(0),
Q => probe_out_modified(0),
R => clear_int
);
\probe_out_modified_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(10),
Q => probe_out_modified(10),
R => clear_int
);
\probe_out_modified_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(11),
Q => probe_out_modified(11),
R => clear_int
);
\probe_out_modified_reg[12]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(12),
Q => probe_out_modified(12),
R => clear_int
);
\probe_out_modified_reg[13]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(13),
Q => probe_out_modified(13),
R => clear_int
);
\probe_out_modified_reg[14]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(14),
Q => probe_out_modified(14),
R => clear_int
);
\probe_out_modified_reg[15]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(15),
Q => probe_out_modified(15),
R => clear_int
);
\probe_out_modified_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(1),
Q => probe_out_modified(1),
R => clear_int
);
\probe_out_modified_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(2),
Q => probe_out_modified(2),
R => clear_int
);
\probe_out_modified_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(3),
Q => probe_out_modified(3),
R => clear_int
);
\probe_out_modified_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(4),
Q => probe_out_modified(4),
R => clear_int
);
\probe_out_modified_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(5),
Q => probe_out_modified(5),
R => clear_int
);
\probe_out_modified_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(6),
Q => probe_out_modified(6),
R => clear_int
);
\probe_out_modified_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(7),
Q => probe_out_modified(7),
R => clear_int
);
\probe_out_modified_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(8),
Q => probe_out_modified(8),
R => clear_int
);
\probe_out_modified_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => wr_probe_out_modified,
D => Q(9),
Q => probe_out_modified(9),
R => clear_int
);
rd_en_p1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => xsdb_rd
);
rd_en_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_rd,
Q => rd_en_p1,
R => s_rst_o
);
rd_en_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => rd_en_p1,
Q => rd_en_p2,
R => s_rst_o
);
\wr_en[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => xsdb_wr,
I1 => s_daddr_o(2),
I2 => \^wr_en_reg[4]_0\,
I3 => \^wr_en_reg[4]_2\,
I4 => \^wr_en_reg[4]_1\,
I5 => \wr_en[2]_i_2_n_0\,
O => \wr_en[2]_i_1_n_0\
);
\wr_en[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
O => \wr_en[2]_i_2_n_0\
);
\wr_en[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000020000"
)
port map (
I0 => xsdb_wr,
I1 => \^wr_en_reg[4]_0\,
I2 => \^wr_en_reg[4]_2\,
I3 => \^wr_en_reg[4]_1\,
I4 => s_daddr_o(2),
I5 => \wr_en[4]_i_6_n_0\,
O => \wr_en[4]_i_1_n_0\
);
\wr_en[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_den_o,
I1 => s_dwe_o,
O => xsdb_wr
);
\wr_en[4]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => s_daddr_o(15),
I1 => s_daddr_o(16),
I2 => s_daddr_o(13),
I3 => s_daddr_o(14),
I4 => s_daddr_o(4),
I5 => s_daddr_o(3),
O => \^wr_en_reg[4]_0\
);
\wr_en[4]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(6),
I1 => s_daddr_o(5),
I2 => s_daddr_o(8),
I3 => s_daddr_o(7),
O => \^wr_en_reg[4]_2\
);
\wr_en[4]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_daddr_o(10),
I1 => s_daddr_o(9),
I2 => s_daddr_o(12),
I3 => s_daddr_o(11),
O => \^wr_en_reg[4]_1\
);
\wr_en[4]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
O => \wr_en[4]_i_6_n_0\
);
\wr_en_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[2]_i_1_n_0\,
Q => wr_control_reg,
R => '0'
);
\wr_en_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \wr_en[4]_i_1_n_0\,
Q => wr_probe_out_modified,
R => '0'
);
\xsdb_addr_2_0_p1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(0),
Q => xsdb_addr_2_0_p1(0),
R => '0'
);
\xsdb_addr_2_0_p1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(1),
Q => xsdb_addr_2_0_p1(1),
R => '0'
);
\xsdb_addr_2_0_p1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(2),
Q => xsdb_addr_2_0_p1(2),
R => '0'
);
\xsdb_addr_2_0_p2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(0),
Q => xsdb_addr_2_0_p2(0),
R => '0'
);
\xsdb_addr_2_0_p2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(1),
Q => xsdb_addr_2_0_p2(1),
R => '0'
);
\xsdb_addr_2_0_p2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_2_0_p1(2),
Q => xsdb_addr_2_0_p2(2),
R => '0'
);
xsdb_addr_8_p1_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => s_daddr_o(8),
Q => xsdb_addr_8_p1,
R => '0'
);
xsdb_addr_8_p2_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_addr_8_p1,
Q => xsdb_addr_8_p2,
R => '0'
);
xsdb_drdy_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => s_dwe_o,
I1 => s_den_o,
I2 => rd_en_p2,
O => xsdb_drdy_i_1_n_0
);
xsdb_drdy_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => xsdb_drdy_i_1_n_0,
Q => s_drdy_i,
R => s_rst_o
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one is
port (
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\out\ : in STD_LOGIC;
\wr_en[4]_i_3\ : in STD_LOGIC;
\wr_en[4]_i_4\ : in STD_LOGIC;
\wr_en[4]_i_5\ : in STD_LOGIC;
s_daddr_o : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_dwe_o : in STD_LOGIC;
s_den_o : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
clk : in STD_LOGIC;
s_rst_o : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one is
signal \DECODER_INST/rd_en_int_7\ : STD_LOGIC;
signal Read_int : STD_LOGIC;
signal Read_int_i_2_n_0 : STD_LOGIC;
signal data_int_sync1 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of data_int_sync1 : signal is "true";
signal data_int_sync2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg of data_int_sync2 : signal is "true";
signal \dn_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \dn_activity_reg_n_0_[3]\ : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal probe_in_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of probe_in_reg : signal is std.standard.true;
signal read_done : STD_LOGIC;
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of read_done : signal is "200";
attribute RTL_MAX_FANOUT : string;
attribute RTL_MAX_FANOUT of read_done : signal is "found";
signal read_done_i_1_n_0 : STD_LOGIC;
signal \up_activity[0]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[1]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[2]_i_1_n_0\ : STD_LOGIC;
signal \up_activity[3]_i_1_n_0\ : STD_LOGIC;
signal \up_activity_reg_n_0_[0]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[1]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[2]\ : STD_LOGIC;
signal \up_activity_reg_n_0_[3]\ : STD_LOGIC;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \data_int_sync1_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \data_int_sync1_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync1_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync1_reg[3]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[0]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[1]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[1]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[2]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[2]\ : label is "yes";
attribute ASYNC_REG_boolean of \data_int_sync2_reg[3]\ : label is std.standard.true;
attribute KEEP of \data_int_sync2_reg[3]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[0]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[1]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[2]\ : label is "yes";
attribute DONT_TOUCH of \probe_in_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \probe_in_reg_reg[3]\ : label is "yes";
attribute RTL_MAX_FANOUT of read_done_reg : label is "found";
begin
\Bus_Data_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(0),
Q => Q(0),
R => '0'
);
\Bus_Data_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_9_in,
Q => Q(10),
R => '0'
);
\Bus_Data_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[3]\,
Q => Q(11),
R => '0'
);
\Bus_Data_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(1),
Q => Q(1),
R => '0'
);
\Bus_Data_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(2),
Q => Q(2),
R => '0'
);
\Bus_Data_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => data_int_sync2(3),
Q => Q(3),
R => '0'
);
\Bus_Data_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[0]\,
Q => Q(4),
R => '0'
);
\Bus_Data_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[1]\,
Q => Q(5),
R => '0'
);
\Bus_Data_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[2]\,
Q => Q(6),
R => '0'
);
\Bus_Data_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \up_activity_reg_n_0_[3]\,
Q => Q(7),
R => '0'
);
\Bus_Data_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \dn_activity_reg_n_0_[0]\,
Q => Q(8),
R => '0'
);
\Bus_Data_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => p_6_in,
Q => Q(9),
R => '0'
);
Read_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => Read_int_i_2_n_0,
I1 => \wr_en[4]_i_3\,
I2 => \wr_en[4]_i_4\,
I3 => \wr_en[4]_i_5\,
O => \DECODER_INST/rd_en_int_7\
);
Read_int_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => s_daddr_o(0),
I1 => s_daddr_o(1),
I2 => s_daddr_o(2),
I3 => s_dwe_o,
I4 => s_den_o,
O => Read_int_i_2_n_0
);
Read_int_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => \DECODER_INST/rd_en_int_7\,
Q => Read_int,
R => '0'
);
\data_int_sync1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(0),
Q => data_int_sync1(0),
R => '0'
);
\data_int_sync1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(1),
Q => data_int_sync1(1),
R => '0'
);
\data_int_sync1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(2),
Q => data_int_sync1(2),
R => '0'
);
\data_int_sync1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => probe_in_reg(3),
Q => data_int_sync1(3),
R => '0'
);
\data_int_sync2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(0),
Q => data_int_sync2(0),
R => '0'
);
\data_int_sync2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(1),
Q => data_int_sync2(1),
R => '0'
);
\data_int_sync2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(2),
Q => data_int_sync2(2),
R => '0'
);
\data_int_sync2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => data_int_sync1(3),
Q => data_int_sync2(3),
R => '0'
);
\dn_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[0]\,
I1 => data_int_sync1(0),
I2 => data_int_sync2(0),
O => \dn_activity[0]_i_1_n_0\
);
\dn_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_6_in,
I1 => data_int_sync1(1),
I2 => data_int_sync2(1),
O => \dn_activity[1]_i_1_n_0\
);
\dn_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => p_9_in,
I1 => data_int_sync1(2),
I2 => data_int_sync2(2),
O => \dn_activity[2]_i_1_n_0\
);
\dn_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \dn_activity_reg_n_0_[3]\,
I1 => data_int_sync1(3),
I2 => data_int_sync2(3),
O => \dn_activity[3]_i_1_n_0\
);
\dn_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[0]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[0]\,
R => read_done
);
\dn_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[1]_i_1_n_0\,
Q => p_6_in,
R => read_done
);
\dn_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[2]_i_1_n_0\,
Q => p_9_in,
R => read_done
);
\dn_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \dn_activity[3]_i_1_n_0\,
Q => \dn_activity_reg_n_0_[3]\,
R => read_done
);
\probe_in_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(0),
Q => probe_in_reg(0),
R => '0'
);
\probe_in_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(1),
Q => probe_in_reg(1),
R => '0'
);
\probe_in_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(2),
Q => probe_in_reg(2),
R => '0'
);
\probe_in_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => D(3),
Q => probe_in_reg(3),
R => '0'
);
read_done_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => Read_int,
I1 => read_done,
I2 => s_rst_o,
O => read_done_i_1_n_0
);
read_done_reg: unisim.vcomponents.FDRE
port map (
C => \out\,
CE => '1',
D => read_done_i_1_n_0,
Q => read_done,
R => '0'
);
\up_activity[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[0]\,
I1 => data_int_sync2(0),
I2 => data_int_sync1(0),
O => \up_activity[0]_i_1_n_0\
);
\up_activity[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[1]\,
I1 => data_int_sync2(1),
I2 => data_int_sync1(1),
O => \up_activity[1]_i_1_n_0\
);
\up_activity[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[2]\,
I1 => data_int_sync2(2),
I2 => data_int_sync1(2),
O => \up_activity[2]_i_1_n_0\
);
\up_activity[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \up_activity_reg_n_0_[3]\,
I1 => data_int_sync2(3),
I2 => data_int_sync1(3),
O => \up_activity[3]_i_1_n_0\
);
\up_activity_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[0]_i_1_n_0\,
Q => \up_activity_reg_n_0_[0]\,
R => read_done
);
\up_activity_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[1]_i_1_n_0\,
Q => \up_activity_reg_n_0_[1]\,
R => read_done
);
\up_activity_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[2]_i_1_n_0\,
Q => \up_activity_reg_n_0_[2]\,
R => read_done
);
\up_activity_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \out\,
CE => '1',
D => \up_activity[3]_i_1_n_0\,
Q => \up_activity_reg_n_0_[3]\,
R => read_done
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is
port (
s_rst_o : out STD_LOGIC;
s_dclk_o : out STD_LOGIC;
s_den_o : out STD_LOGIC;
s_dwe_o : out STD_LOGIC;
s_daddr_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_di_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
sl_oport_o : out STD_LOGIC_VECTOR ( 16 downto 0 );
s_do_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
sl_iport_i : in STD_LOGIC_VECTOR ( 36 downto 0 );
s_drdy_i : in STD_LOGIC
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 2013;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 0;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "kintex7";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is 33;
attribute dont_touch : string;
attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs : entity is "true";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs is
signal reg_do : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \reg_do[10]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[10]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[15]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[1]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[2]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[3]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[4]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[5]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[6]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[7]_i_1_n_0\ : STD_LOGIC;
signal \reg_do[8]_i_2_n_0\ : STD_LOGIC;
signal \reg_do[9]_i_1_n_0\ : STD_LOGIC;
signal \reg_do_reg_n_0_[0]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[10]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[11]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[12]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[13]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[14]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[15]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[1]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[2]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[3]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[4]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[5]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[6]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[7]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[8]\ : STD_LOGIC;
signal \reg_do_reg_n_0_[9]\ : STD_LOGIC;
signal reg_drdy : STD_LOGIC;
signal reg_drdy_i_1_n_0 : STD_LOGIC;
signal reg_test : STD_LOGIC_VECTOR ( 15 downto 0 );
signal reg_test0 : STD_LOGIC;
signal s_den_o_INST_0_i_1_n_0 : STD_LOGIC;
signal \^sl_iport_i\ : STD_LOGIC_VECTOR ( 36 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \reg_do[10]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[1]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \reg_do[3]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[4]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \reg_do[5]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \reg_do[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \reg_do[7]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \sl_oport_o[0]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[10]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[11]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \sl_oport_o[12]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[13]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \sl_oport_o[14]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[15]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \sl_oport_o[1]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[2]_INST_0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \sl_oport_o[3]_INST_0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \sl_oport_o[4]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[5]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[6]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \sl_oport_o[7]_INST_0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \sl_oport_o[8]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \sl_oport_o[9]_INST_0\ : label is "soft_lutpair8";
begin
\^sl_iport_i\(36 downto 0) <= sl_iport_i(36 downto 0);
s_daddr_o(16 downto 0) <= \^sl_iport_i\(20 downto 4);
s_dclk_o <= \^sl_iport_i\(1);
s_di_o(15 downto 0) <= \^sl_iport_i\(36 downto 21);
s_dwe_o <= \^sl_iport_i\(3);
s_rst_o <= \^sl_iport_i\(0);
\reg_do[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BAAAFFFFAAAAAAAA"
)
port map (
I0 => \reg_do[5]_i_2_n_0\,
I1 => \^sl_iport_i\(4),
I2 => reg_test(0),
I3 => \^sl_iport_i\(6),
I4 => \^sl_iport_i\(5),
I5 => \^sl_iport_i\(8),
O => reg_do(0)
);
\reg_do[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \reg_do[8]_i_2_n_0\,
I2 => \^sl_iport_i\(4),
O => \reg_do[10]_i_1_n_0\
);
\reg_do[10]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(10),
O => \reg_do[10]_i_2_n_0\
);
\reg_do[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"F7"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
O => \reg_do[15]_i_1_n_0\
);
\reg_do[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20220000"
)
port map (
I0 => \^sl_iport_i\(5),
I1 => \^sl_iport_i\(4),
I2 => reg_test(1),
I3 => \^sl_iport_i\(6),
I4 => \reg_do[1]_i_2_n_0\,
O => reg_do(1)
);
\reg_do[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => \^sl_iport_i\(8),
I1 => \^sl_iport_i\(10),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(7),
I4 => \^sl_iport_i\(9),
O => \reg_do[1]_i_2_n_0\
);
\reg_do[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(2),
O => \reg_do[2]_i_1_n_0\
);
\reg_do[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(3),
O => \reg_do[3]_i_1_n_0\
);
\reg_do[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(4),
O => \reg_do[4]_i_1_n_0\
);
\reg_do[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00800044"
)
port map (
I0 => \^sl_iport_i\(6),
I1 => \^sl_iport_i\(8),
I2 => reg_test(5),
I3 => \^sl_iport_i\(4),
I4 => \^sl_iport_i\(5),
I5 => \reg_do[5]_i_2_n_0\,
O => reg_do(5)
);
\reg_do[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFFFFC"
)
port map (
I0 => \^sl_iport_i\(7),
I1 => \^sl_iport_i\(8),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(9),
O => \reg_do[5]_i_2_n_0\
);
\reg_do[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(6),
O => \reg_do[6]_i_1_n_0\
);
\reg_do[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \reg_do[8]_i_2_n_0\,
I1 => \^sl_iport_i\(5),
I2 => \^sl_iport_i\(4),
I3 => reg_test(7),
O => \reg_do[7]_i_1_n_0\
);
\reg_do[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2F00"
)
port map (
I0 => reg_test(8),
I1 => \^sl_iport_i\(4),
I2 => \^sl_iport_i\(5),
I3 => \reg_do[8]_i_2_n_0\,
O => reg_do(8)
);
\reg_do[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2000000000000000"
)
port map (
I0 => \^sl_iport_i\(9),
I1 => \^sl_iport_i\(7),
I2 => \^sl_iport_i\(11),
I3 => \^sl_iport_i\(10),
I4 => \^sl_iport_i\(8),
I5 => \^sl_iport_i\(6),
O => \reg_do[8]_i_2_n_0\
);
\reg_do[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0C008000"
)
port map (
I0 => reg_test(9),
I1 => \reg_do[1]_i_2_n_0\,
I2 => \^sl_iport_i\(6),
I3 => \^sl_iport_i\(5),
I4 => \^sl_iport_i\(4),
O => \reg_do[9]_i_1_n_0\
);
\reg_do_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(0),
Q => \reg_do_reg_n_0_[0]\,
R => '0'
);
\reg_do_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[10]_i_2_n_0\,
Q => \reg_do_reg_n_0_[10]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(11),
Q => \reg_do_reg_n_0_[11]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(12),
Q => \reg_do_reg_n_0_[12]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(13),
Q => \reg_do_reg_n_0_[13]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(14),
Q => \reg_do_reg_n_0_[14]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_test(15),
Q => \reg_do_reg_n_0_[15]\,
R => \reg_do[15]_i_1_n_0\
);
\reg_do_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(1),
Q => \reg_do_reg_n_0_[1]\,
R => '0'
);
\reg_do_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[2]_i_1_n_0\,
Q => \reg_do_reg_n_0_[2]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[3]_i_1_n_0\,
Q => \reg_do_reg_n_0_[3]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[4]_i_1_n_0\,
Q => \reg_do_reg_n_0_[4]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(5),
Q => \reg_do_reg_n_0_[5]\,
R => '0'
);
\reg_do_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[6]_i_1_n_0\,
Q => \reg_do_reg_n_0_[6]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[7]_i_1_n_0\,
Q => \reg_do_reg_n_0_[7]\,
S => \reg_do[10]_i_1_n_0\
);
\reg_do_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_do(8),
Q => \reg_do_reg_n_0_[8]\,
R => '0'
);
\reg_do_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => \reg_do[9]_i_1_n_0\,
Q => \reg_do_reg_n_0_[9]\,
S => \reg_do[10]_i_1_n_0\
);
reg_drdy_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080000000"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => s_den_o_INST_0_i_1_n_0,
I2 => \^sl_iport_i\(12),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(14),
I5 => \^sl_iport_i\(0),
O => reg_drdy_i_1_n_0
);
reg_drdy_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => '1',
D => reg_drdy_i_1_n_0,
Q => reg_drdy,
R => '0'
);
\reg_test[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(3),
I1 => \^sl_iport_i\(2),
I2 => \^sl_iport_i\(14),
I3 => \^sl_iport_i\(13),
I4 => \^sl_iport_i\(12),
I5 => s_den_o_INST_0_i_1_n_0,
O => reg_test0
);
\reg_test_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(21),
Q => reg_test(0),
R => '0'
);
\reg_test_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(31),
Q => reg_test(10),
R => '0'
);
\reg_test_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(32),
Q => reg_test(11),
R => '0'
);
\reg_test_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(33),
Q => reg_test(12),
R => '0'
);
\reg_test_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(34),
Q => reg_test(13),
R => '0'
);
\reg_test_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(35),
Q => reg_test(14),
R => '0'
);
\reg_test_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(36),
Q => reg_test(15),
R => '0'
);
\reg_test_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(22),
Q => reg_test(1),
R => '0'
);
\reg_test_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(23),
Q => reg_test(2),
R => '0'
);
\reg_test_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(24),
Q => reg_test(3),
R => '0'
);
\reg_test_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(25),
Q => reg_test(4),
R => '0'
);
\reg_test_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(26),
Q => reg_test(5),
R => '0'
);
\reg_test_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(27),
Q => reg_test(6),
R => '0'
);
\reg_test_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(28),
Q => reg_test(7),
R => '0'
);
\reg_test_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(29),
Q => reg_test(8),
R => '0'
);
\reg_test_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => \^sl_iport_i\(1),
CE => reg_test0,
D => \^sl_iport_i\(30),
Q => reg_test(9),
R => '0'
);
s_den_o_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"2AAAAAAA"
)
port map (
I0 => \^sl_iport_i\(2),
I1 => \^sl_iport_i\(14),
I2 => \^sl_iport_i\(13),
I3 => \^sl_iport_i\(12),
I4 => s_den_o_INST_0_i_1_n_0,
O => s_den_o
);
s_den_o_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^sl_iport_i\(15),
I1 => \^sl_iport_i\(16),
I2 => \^sl_iport_i\(17),
I3 => \^sl_iport_i\(18),
I4 => \^sl_iport_i\(20),
I5 => \^sl_iport_i\(19),
O => s_den_o_INST_0_i_1_n_0
);
\sl_oport_o[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => s_drdy_i,
I1 => reg_drdy,
O => sl_oport_o(0)
);
\sl_oport_o[10]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[9]\,
I1 => s_do_i(9),
I2 => reg_drdy,
O => sl_oport_o(10)
);
\sl_oport_o[11]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[10]\,
I1 => s_do_i(10),
I2 => reg_drdy,
O => sl_oport_o(11)
);
\sl_oport_o[12]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[11]\,
I1 => s_do_i(11),
I2 => reg_drdy,
O => sl_oport_o(12)
);
\sl_oport_o[13]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[12]\,
I1 => s_do_i(12),
I2 => reg_drdy,
O => sl_oport_o(13)
);
\sl_oport_o[14]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[13]\,
I1 => s_do_i(13),
I2 => reg_drdy,
O => sl_oport_o(14)
);
\sl_oport_o[15]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[14]\,
I1 => s_do_i(14),
I2 => reg_drdy,
O => sl_oport_o(15)
);
\sl_oport_o[16]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[15]\,
I1 => s_do_i(15),
I2 => reg_drdy,
O => sl_oport_o(16)
);
\sl_oport_o[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[0]\,
I1 => s_do_i(0),
I2 => reg_drdy,
O => sl_oport_o(1)
);
\sl_oport_o[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[1]\,
I1 => s_do_i(1),
I2 => reg_drdy,
O => sl_oport_o(2)
);
\sl_oport_o[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[2]\,
I1 => s_do_i(2),
I2 => reg_drdy,
O => sl_oport_o(3)
);
\sl_oport_o[4]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[3]\,
I1 => s_do_i(3),
I2 => reg_drdy,
O => sl_oport_o(4)
);
\sl_oport_o[5]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[4]\,
I1 => s_do_i(4),
I2 => reg_drdy,
O => sl_oport_o(5)
);
\sl_oport_o[6]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[5]\,
I1 => s_do_i(5),
I2 => reg_drdy,
O => sl_oport_o(6)
);
\sl_oport_o[7]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[6]\,
I1 => s_do_i(6),
I2 => reg_drdy,
O => sl_oport_o(7)
);
\sl_oport_o[8]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[7]\,
I1 => s_do_i(7),
I2 => reg_drdy,
O => sl_oport_o(8)
);
\sl_oport_o[9]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => \reg_do_reg_n_0_[8]\,
I1 => s_do_i(8),
I2 => reg_drdy,
O => sl_oport_o(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in7 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in12 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in19 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in20 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in21 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in22 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in25 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in26 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in27 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in28 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in29 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in30 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in31 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in32 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in33 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in34 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in35 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in36 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in37 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in38 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in39 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in40 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in41 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in42 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in43 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in44 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in45 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in46 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in47 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in48 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in49 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in50 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in51 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in52 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in53 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in54 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in55 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in56 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in57 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in58 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in59 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in60 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in61 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in62 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in63 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in64 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in65 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in66 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in67 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in68 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in69 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in70 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in71 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in72 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in73 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in74 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in75 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in76 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in77 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in78 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in79 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in80 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in81 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in82 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in83 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in84 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in85 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in86 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in87 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in88 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in89 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in90 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in91 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in92 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in93 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in94 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in95 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in96 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in97 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in98 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in99 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in100 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in101 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in102 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in103 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in104 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in105 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in106 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in107 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in108 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in109 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in110 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in111 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in112 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in113 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in114 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in115 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in116 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in117 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in118 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in119 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in120 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in121 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in122 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in123 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in124 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in125 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in126 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in127 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in128 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in129 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in130 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in131 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in132 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in133 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in134 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in135 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in136 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in137 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in138 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in139 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in140 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in141 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in142 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in143 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in144 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in145 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in146 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in147 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in148 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in149 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in150 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in151 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in152 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in153 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in154 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in155 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in156 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in157 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in158 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in159 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in160 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in161 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in162 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in163 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in164 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in165 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in166 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in167 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in168 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in169 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in170 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in171 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in172 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in173 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in174 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in175 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in176 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in177 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in178 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in179 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in180 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in181 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in182 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in183 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in184 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in185 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in186 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in187 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in188 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in189 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in190 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in191 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in192 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in193 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in194 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in195 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in196 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in197 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in198 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in199 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in200 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in201 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in202 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in203 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in204 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in205 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in206 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in207 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in208 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in209 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in210 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in211 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in212 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in213 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in214 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in215 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in216 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in217 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in218 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in219 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in220 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in221 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in222 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in223 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in224 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in225 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in226 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in227 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in228 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in229 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in230 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in231 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in232 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in233 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in234 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in235 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in236 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in237 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in238 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in239 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in240 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in241 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in242 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in243 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in244 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in245 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in246 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in247 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in248 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in249 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in250 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in251 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in252 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in253 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in254 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in255 : in STD_LOGIC_VECTOR ( 0 to 0 );
sl_iport0 : in STD_LOGIC_VECTOR ( 36 downto 0 );
sl_oport0 : out STD_LOGIC_VECTOR ( 16 downto 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out17 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out18 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out19 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out20 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out21 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out22 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out23 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out24 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out25 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out26 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out27 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out28 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out29 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out30 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out31 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out32 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out33 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out34 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out35 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out36 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out37 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out38 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out39 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out40 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out41 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out42 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out43 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out44 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out45 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out46 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out47 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out48 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out49 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out50 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out51 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out52 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out53 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out54 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out55 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out56 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out57 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out58 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out59 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out60 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out61 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out62 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out63 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out64 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out65 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out66 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out67 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out68 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out69 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out70 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out71 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out72 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out73 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out74 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out75 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out76 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out77 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out78 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out79 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out80 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out81 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out82 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out83 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out84 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out85 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out86 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out87 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out88 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out89 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out90 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out91 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out92 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out93 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out94 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out95 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out96 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out97 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out98 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out99 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out100 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out101 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out102 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out103 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out104 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out105 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out106 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out107 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out108 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out109 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out110 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out111 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out112 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out113 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out114 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out115 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out116 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out117 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out118 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out119 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out120 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out121 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out122 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out123 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out124 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out125 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out126 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out127 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out128 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out129 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out130 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out131 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out132 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out133 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out134 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out135 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out136 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out137 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out138 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out139 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out140 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out141 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out142 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out143 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out144 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out145 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out146 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out147 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out148 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out149 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out150 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out151 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out152 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out153 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out154 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out155 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out156 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out157 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out158 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out159 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out160 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out161 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out162 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out163 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out164 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out165 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out166 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out167 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out168 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out169 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out170 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out171 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out172 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out173 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out174 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out175 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out176 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out177 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out178 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out179 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out180 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out181 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out182 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out183 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out184 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out185 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out186 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out187 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out188 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out189 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out190 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out191 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out192 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out193 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out194 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out195 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out196 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out197 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out198 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out199 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out200 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out201 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out202 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out203 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out204 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out205 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out206 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out207 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out208 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out209 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out210 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out211 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out212 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out213 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out214 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out215 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out216 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out217 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out218 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out219 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out220 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out221 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out222 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out223 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out224 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out225 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out226 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out227 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out228 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out229 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out230 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out231 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out232 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out233 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out234 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out235 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out236 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out237 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out238 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out239 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out240 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out241 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out242 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out243 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out244 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out245 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out246 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out247 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out248 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out249 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out250 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out251 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out252 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out253 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out254 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out255 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 33;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is 0;
attribute dont_touch : string;
attribute dont_touch of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio : entity is "true";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio is
signal \<const0>\ : STD_LOGIC;
signal Bus_Data_out : STD_LOGIC_VECTOR ( 11 downto 0 );
signal DECODER_INST_n_1 : STD_LOGIC;
signal DECODER_INST_n_2 : STD_LOGIC;
signal DECODER_INST_n_3 : STD_LOGIC;
signal DECODER_INST_n_4 : STD_LOGIC;
signal bus_addr : STD_LOGIC_VECTOR ( 16 downto 0 );
signal bus_clk : STD_LOGIC;
attribute DONT_TOUCH_boolean : boolean;
attribute DONT_TOUCH_boolean of bus_clk : signal is std.standard.true;
signal \bus_data_int_reg_n_0_[0]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[10]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[11]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[12]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[13]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[14]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[15]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[2]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[3]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[4]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[5]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[6]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[7]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[8]\ : STD_LOGIC;
signal \bus_data_int_reg_n_0_[9]\ : STD_LOGIC;
signal bus_den : STD_LOGIC;
signal bus_di : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_do : STD_LOGIC_VECTOR ( 15 downto 0 );
signal bus_drdy : STD_LOGIC;
signal bus_dwe : STD_LOGIC;
signal bus_rst : STD_LOGIC;
signal p_0_in : STD_LOGIC;
attribute C_BUILD_REVISION of U_XSDB_SLAVE : label is 0;
attribute C_CORE_INFO1 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 of U_XSDB_SLAVE : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER of U_XSDB_SLAVE : label is 2;
attribute C_CORE_MINOR_VER of U_XSDB_SLAVE : label is 0;
attribute C_CORE_TYPE of U_XSDB_SLAVE : label is 2;
attribute C_CSE_DRV_VER of U_XSDB_SLAVE : label is 1;
attribute C_MAJOR_VERSION of U_XSDB_SLAVE : label is 2013;
attribute C_MINOR_VERSION of U_XSDB_SLAVE : label is 1;
attribute C_NEXT_SLAVE of U_XSDB_SLAVE : label is 0;
attribute C_PIPE_IFACE of U_XSDB_SLAVE : label is 0;
attribute C_USE_TEST_REG of U_XSDB_SLAVE : label is 1;
attribute C_XDEVICEFAMILY of U_XSDB_SLAVE : label is "kintex7";
attribute C_XSDB_SLAVE_TYPE of U_XSDB_SLAVE : label is 33;
attribute DONT_TOUCH_boolean of U_XSDB_SLAVE : label is std.standard.true;
begin
probe_out0(0) <= \<const0>\;
probe_out1(0) <= \<const0>\;
probe_out10(0) <= \<const0>\;
probe_out100(0) <= \<const0>\;
probe_out101(0) <= \<const0>\;
probe_out102(0) <= \<const0>\;
probe_out103(0) <= \<const0>\;
probe_out104(0) <= \<const0>\;
probe_out105(0) <= \<const0>\;
probe_out106(0) <= \<const0>\;
probe_out107(0) <= \<const0>\;
probe_out108(0) <= \<const0>\;
probe_out109(0) <= \<const0>\;
probe_out11(0) <= \<const0>\;
probe_out110(0) <= \<const0>\;
probe_out111(0) <= \<const0>\;
probe_out112(0) <= \<const0>\;
probe_out113(0) <= \<const0>\;
probe_out114(0) <= \<const0>\;
probe_out115(0) <= \<const0>\;
probe_out116(0) <= \<const0>\;
probe_out117(0) <= \<const0>\;
probe_out118(0) <= \<const0>\;
probe_out119(0) <= \<const0>\;
probe_out12(0) <= \<const0>\;
probe_out120(0) <= \<const0>\;
probe_out121(0) <= \<const0>\;
probe_out122(0) <= \<const0>\;
probe_out123(0) <= \<const0>\;
probe_out124(0) <= \<const0>\;
probe_out125(0) <= \<const0>\;
probe_out126(0) <= \<const0>\;
probe_out127(0) <= \<const0>\;
probe_out128(0) <= \<const0>\;
probe_out129(0) <= \<const0>\;
probe_out13(0) <= \<const0>\;
probe_out130(0) <= \<const0>\;
probe_out131(0) <= \<const0>\;
probe_out132(0) <= \<const0>\;
probe_out133(0) <= \<const0>\;
probe_out134(0) <= \<const0>\;
probe_out135(0) <= \<const0>\;
probe_out136(0) <= \<const0>\;
probe_out137(0) <= \<const0>\;
probe_out138(0) <= \<const0>\;
probe_out139(0) <= \<const0>\;
probe_out14(0) <= \<const0>\;
probe_out140(0) <= \<const0>\;
probe_out141(0) <= \<const0>\;
probe_out142(0) <= \<const0>\;
probe_out143(0) <= \<const0>\;
probe_out144(0) <= \<const0>\;
probe_out145(0) <= \<const0>\;
probe_out146(0) <= \<const0>\;
probe_out147(0) <= \<const0>\;
probe_out148(0) <= \<const0>\;
probe_out149(0) <= \<const0>\;
probe_out15(0) <= \<const0>\;
probe_out150(0) <= \<const0>\;
probe_out151(0) <= \<const0>\;
probe_out152(0) <= \<const0>\;
probe_out153(0) <= \<const0>\;
probe_out154(0) <= \<const0>\;
probe_out155(0) <= \<const0>\;
probe_out156(0) <= \<const0>\;
probe_out157(0) <= \<const0>\;
probe_out158(0) <= \<const0>\;
probe_out159(0) <= \<const0>\;
probe_out16(0) <= \<const0>\;
probe_out160(0) <= \<const0>\;
probe_out161(0) <= \<const0>\;
probe_out162(0) <= \<const0>\;
probe_out163(0) <= \<const0>\;
probe_out164(0) <= \<const0>\;
probe_out165(0) <= \<const0>\;
probe_out166(0) <= \<const0>\;
probe_out167(0) <= \<const0>\;
probe_out168(0) <= \<const0>\;
probe_out169(0) <= \<const0>\;
probe_out17(0) <= \<const0>\;
probe_out170(0) <= \<const0>\;
probe_out171(0) <= \<const0>\;
probe_out172(0) <= \<const0>\;
probe_out173(0) <= \<const0>\;
probe_out174(0) <= \<const0>\;
probe_out175(0) <= \<const0>\;
probe_out176(0) <= \<const0>\;
probe_out177(0) <= \<const0>\;
probe_out178(0) <= \<const0>\;
probe_out179(0) <= \<const0>\;
probe_out18(0) <= \<const0>\;
probe_out180(0) <= \<const0>\;
probe_out181(0) <= \<const0>\;
probe_out182(0) <= \<const0>\;
probe_out183(0) <= \<const0>\;
probe_out184(0) <= \<const0>\;
probe_out185(0) <= \<const0>\;
probe_out186(0) <= \<const0>\;
probe_out187(0) <= \<const0>\;
probe_out188(0) <= \<const0>\;
probe_out189(0) <= \<const0>\;
probe_out19(0) <= \<const0>\;
probe_out190(0) <= \<const0>\;
probe_out191(0) <= \<const0>\;
probe_out192(0) <= \<const0>\;
probe_out193(0) <= \<const0>\;
probe_out194(0) <= \<const0>\;
probe_out195(0) <= \<const0>\;
probe_out196(0) <= \<const0>\;
probe_out197(0) <= \<const0>\;
probe_out198(0) <= \<const0>\;
probe_out199(0) <= \<const0>\;
probe_out2(0) <= \<const0>\;
probe_out20(0) <= \<const0>\;
probe_out200(0) <= \<const0>\;
probe_out201(0) <= \<const0>\;
probe_out202(0) <= \<const0>\;
probe_out203(0) <= \<const0>\;
probe_out204(0) <= \<const0>\;
probe_out205(0) <= \<const0>\;
probe_out206(0) <= \<const0>\;
probe_out207(0) <= \<const0>\;
probe_out208(0) <= \<const0>\;
probe_out209(0) <= \<const0>\;
probe_out21(0) <= \<const0>\;
probe_out210(0) <= \<const0>\;
probe_out211(0) <= \<const0>\;
probe_out212(0) <= \<const0>\;
probe_out213(0) <= \<const0>\;
probe_out214(0) <= \<const0>\;
probe_out215(0) <= \<const0>\;
probe_out216(0) <= \<const0>\;
probe_out217(0) <= \<const0>\;
probe_out218(0) <= \<const0>\;
probe_out219(0) <= \<const0>\;
probe_out22(0) <= \<const0>\;
probe_out220(0) <= \<const0>\;
probe_out221(0) <= \<const0>\;
probe_out222(0) <= \<const0>\;
probe_out223(0) <= \<const0>\;
probe_out224(0) <= \<const0>\;
probe_out225(0) <= \<const0>\;
probe_out226(0) <= \<const0>\;
probe_out227(0) <= \<const0>\;
probe_out228(0) <= \<const0>\;
probe_out229(0) <= \<const0>\;
probe_out23(0) <= \<const0>\;
probe_out230(0) <= \<const0>\;
probe_out231(0) <= \<const0>\;
probe_out232(0) <= \<const0>\;
probe_out233(0) <= \<const0>\;
probe_out234(0) <= \<const0>\;
probe_out235(0) <= \<const0>\;
probe_out236(0) <= \<const0>\;
probe_out237(0) <= \<const0>\;
probe_out238(0) <= \<const0>\;
probe_out239(0) <= \<const0>\;
probe_out24(0) <= \<const0>\;
probe_out240(0) <= \<const0>\;
probe_out241(0) <= \<const0>\;
probe_out242(0) <= \<const0>\;
probe_out243(0) <= \<const0>\;
probe_out244(0) <= \<const0>\;
probe_out245(0) <= \<const0>\;
probe_out246(0) <= \<const0>\;
probe_out247(0) <= \<const0>\;
probe_out248(0) <= \<const0>\;
probe_out249(0) <= \<const0>\;
probe_out25(0) <= \<const0>\;
probe_out250(0) <= \<const0>\;
probe_out251(0) <= \<const0>\;
probe_out252(0) <= \<const0>\;
probe_out253(0) <= \<const0>\;
probe_out254(0) <= \<const0>\;
probe_out255(0) <= \<const0>\;
probe_out26(0) <= \<const0>\;
probe_out27(0) <= \<const0>\;
probe_out28(0) <= \<const0>\;
probe_out29(0) <= \<const0>\;
probe_out3(0) <= \<const0>\;
probe_out30(0) <= \<const0>\;
probe_out31(0) <= \<const0>\;
probe_out32(0) <= \<const0>\;
probe_out33(0) <= \<const0>\;
probe_out34(0) <= \<const0>\;
probe_out35(0) <= \<const0>\;
probe_out36(0) <= \<const0>\;
probe_out37(0) <= \<const0>\;
probe_out38(0) <= \<const0>\;
probe_out39(0) <= \<const0>\;
probe_out4(0) <= \<const0>\;
probe_out40(0) <= \<const0>\;
probe_out41(0) <= \<const0>\;
probe_out42(0) <= \<const0>\;
probe_out43(0) <= \<const0>\;
probe_out44(0) <= \<const0>\;
probe_out45(0) <= \<const0>\;
probe_out46(0) <= \<const0>\;
probe_out47(0) <= \<const0>\;
probe_out48(0) <= \<const0>\;
probe_out49(0) <= \<const0>\;
probe_out5(0) <= \<const0>\;
probe_out50(0) <= \<const0>\;
probe_out51(0) <= \<const0>\;
probe_out52(0) <= \<const0>\;
probe_out53(0) <= \<const0>\;
probe_out54(0) <= \<const0>\;
probe_out55(0) <= \<const0>\;
probe_out56(0) <= \<const0>\;
probe_out57(0) <= \<const0>\;
probe_out58(0) <= \<const0>\;
probe_out59(0) <= \<const0>\;
probe_out6(0) <= \<const0>\;
probe_out60(0) <= \<const0>\;
probe_out61(0) <= \<const0>\;
probe_out62(0) <= \<const0>\;
probe_out63(0) <= \<const0>\;
probe_out64(0) <= \<const0>\;
probe_out65(0) <= \<const0>\;
probe_out66(0) <= \<const0>\;
probe_out67(0) <= \<const0>\;
probe_out68(0) <= \<const0>\;
probe_out69(0) <= \<const0>\;
probe_out7(0) <= \<const0>\;
probe_out70(0) <= \<const0>\;
probe_out71(0) <= \<const0>\;
probe_out72(0) <= \<const0>\;
probe_out73(0) <= \<const0>\;
probe_out74(0) <= \<const0>\;
probe_out75(0) <= \<const0>\;
probe_out76(0) <= \<const0>\;
probe_out77(0) <= \<const0>\;
probe_out78(0) <= \<const0>\;
probe_out79(0) <= \<const0>\;
probe_out8(0) <= \<const0>\;
probe_out80(0) <= \<const0>\;
probe_out81(0) <= \<const0>\;
probe_out82(0) <= \<const0>\;
probe_out83(0) <= \<const0>\;
probe_out84(0) <= \<const0>\;
probe_out85(0) <= \<const0>\;
probe_out86(0) <= \<const0>\;
probe_out87(0) <= \<const0>\;
probe_out88(0) <= \<const0>\;
probe_out89(0) <= \<const0>\;
probe_out9(0) <= \<const0>\;
probe_out90(0) <= \<const0>\;
probe_out91(0) <= \<const0>\;
probe_out92(0) <= \<const0>\;
probe_out93(0) <= \<const0>\;
probe_out94(0) <= \<const0>\;
probe_out95(0) <= \<const0>\;
probe_out96(0) <= \<const0>\;
probe_out97(0) <= \<const0>\;
probe_out98(0) <= \<const0>\;
probe_out99(0) <= \<const0>\;
DECODER_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder
port map (
\Bus_Data_out_reg[11]\(11 downto 0) => Bus_Data_out(11 downto 0),
E(0) => DECODER_INST_n_4,
Q(15) => \bus_data_int_reg_n_0_[15]\,
Q(14) => \bus_data_int_reg_n_0_[14]\,
Q(13) => \bus_data_int_reg_n_0_[13]\,
Q(12) => \bus_data_int_reg_n_0_[12]\,
Q(11) => \bus_data_int_reg_n_0_[11]\,
Q(10) => \bus_data_int_reg_n_0_[10]\,
Q(9) => \bus_data_int_reg_n_0_[9]\,
Q(8) => \bus_data_int_reg_n_0_[8]\,
Q(7) => \bus_data_int_reg_n_0_[7]\,
Q(6) => \bus_data_int_reg_n_0_[6]\,
Q(5) => \bus_data_int_reg_n_0_[5]\,
Q(4) => \bus_data_int_reg_n_0_[4]\,
Q(3) => \bus_data_int_reg_n_0_[3]\,
Q(2) => \bus_data_int_reg_n_0_[2]\,
Q(1) => p_0_in,
Q(0) => \bus_data_int_reg_n_0_[0]\,
\out\ => bus_clk,
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_den_o => bus_den,
s_do_i(15 downto 0) => bus_do(15 downto 0),
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\wr_en_reg[4]_0\ => DECODER_INST_n_1,
\wr_en_reg[4]_1\ => DECODER_INST_n_2,
\wr_en_reg[4]_2\ => DECODER_INST_n_3
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
PROBE_IN_INST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one
port map (
D(3) => probe_in3(0),
D(2) => probe_in2(0),
D(1) => probe_in1(0),
D(0) => probe_in0(0),
E(0) => DECODER_INST_n_4,
Q(11 downto 0) => Bus_Data_out(11 downto 0),
clk => clk,
\out\ => bus_clk,
s_daddr_o(2 downto 0) => bus_addr(2 downto 0),
s_den_o => bus_den,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
\wr_en[4]_i_3\ => DECODER_INST_n_1,
\wr_en[4]_i_4\ => DECODER_INST_n_3,
\wr_en[4]_i_5\ => DECODER_INST_n_2
);
U_XSDB_SLAVE: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs
port map (
s_daddr_o(16 downto 0) => bus_addr(16 downto 0),
s_dclk_o => bus_clk,
s_den_o => bus_den,
s_di_o(15 downto 0) => bus_di(15 downto 0),
s_do_i(15 downto 0) => bus_do(15 downto 0),
s_drdy_i => bus_drdy,
s_dwe_o => bus_dwe,
s_rst_o => bus_rst,
sl_iport_i(36 downto 0) => sl_iport0(36 downto 0),
sl_oport_o(16 downto 0) => sl_oport0(16 downto 0)
);
\bus_data_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(0),
Q => \bus_data_int_reg_n_0_[0]\,
R => '0'
);
\bus_data_int_reg[10]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(10),
Q => \bus_data_int_reg_n_0_[10]\,
R => '0'
);
\bus_data_int_reg[11]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(11),
Q => \bus_data_int_reg_n_0_[11]\,
R => '0'
);
\bus_data_int_reg[12]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(12),
Q => \bus_data_int_reg_n_0_[12]\,
R => '0'
);
\bus_data_int_reg[13]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(13),
Q => \bus_data_int_reg_n_0_[13]\,
R => '0'
);
\bus_data_int_reg[14]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(14),
Q => \bus_data_int_reg_n_0_[14]\,
R => '0'
);
\bus_data_int_reg[15]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(15),
Q => \bus_data_int_reg_n_0_[15]\,
R => '0'
);
\bus_data_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(1),
Q => p_0_in,
R => '0'
);
\bus_data_int_reg[2]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(2),
Q => \bus_data_int_reg_n_0_[2]\,
R => '0'
);
\bus_data_int_reg[3]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(3),
Q => \bus_data_int_reg_n_0_[3]\,
R => '0'
);
\bus_data_int_reg[4]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(4),
Q => \bus_data_int_reg_n_0_[4]\,
R => '0'
);
\bus_data_int_reg[5]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(5),
Q => \bus_data_int_reg_n_0_[5]\,
R => '0'
);
\bus_data_int_reg[6]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(6),
Q => \bus_data_int_reg_n_0_[6]\,
R => '0'
);
\bus_data_int_reg[7]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(7),
Q => \bus_data_int_reg_n_0_[7]\,
R => '0'
);
\bus_data_int_reg[8]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(8),
Q => \bus_data_int_reg_n_0_[8]\,
R => '0'
);
\bus_data_int_reg[9]\: unisim.vcomponents.FDRE
port map (
C => bus_clk,
CE => '1',
D => bus_di(9),
Q => \bus_data_int_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio_0,vio,{}";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "vio,Vivado 2016.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_probe_out0_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out1_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out10_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out100_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out101_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out102_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out103_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out104_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out105_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out106_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out107_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out108_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out109_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out11_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out110_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out111_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out112_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out113_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out114_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out115_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out116_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out117_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out118_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out119_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out12_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out120_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out121_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out122_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out123_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out124_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out125_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out126_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out127_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out128_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out129_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out13_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out130_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out131_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out132_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out133_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out134_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out135_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out136_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out137_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out138_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out139_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out14_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out140_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out141_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out142_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out143_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out144_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out145_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out146_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out147_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out148_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out149_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out15_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out150_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out151_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out152_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out153_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out154_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out155_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out156_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out157_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out158_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out159_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out16_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out160_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out161_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out162_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out163_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out164_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out165_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out166_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out167_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out168_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out169_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out17_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out170_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out171_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out172_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out173_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out174_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out175_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out176_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out177_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out178_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out179_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out18_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out180_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out181_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out182_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out183_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out184_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out185_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out186_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out187_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out188_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out189_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out19_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out190_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out191_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out192_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out193_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out194_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out195_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out196_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out197_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out198_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out199_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out2_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out20_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out200_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out201_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out202_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out203_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out204_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out205_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out206_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out207_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out208_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out209_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out21_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out210_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out211_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out212_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out213_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out214_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out215_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out216_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out217_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out218_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out219_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out22_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out220_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out221_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out222_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out223_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out224_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out225_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out226_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out227_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out228_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out229_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out23_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out230_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out231_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out232_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out233_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out234_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out235_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out236_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out237_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out238_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out239_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out24_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out240_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out241_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out242_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out243_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out244_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out245_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out246_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out247_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out248_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out249_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out25_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out250_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out251_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out252_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out253_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out254_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out255_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out26_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out27_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out28_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out29_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out3_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out30_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out31_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out32_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out33_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out34_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out35_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out36_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out37_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out38_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out39_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out4_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out40_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out41_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out42_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out43_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out44_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out45_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out46_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out47_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out48_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out49_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out5_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out50_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out51_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out52_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out53_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out54_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out55_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out56_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out57_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out58_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out59_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out6_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out60_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out61_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out62_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out63_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out64_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out65_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out66_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out67_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out68_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out69_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out7_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out70_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out71_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out72_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out73_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out74_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out75_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out76_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out77_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out78_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out79_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out8_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out80_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out81_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out82_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out83_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out84_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out85_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out86_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out87_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out88_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out89_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out9_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out90_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out91_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out92_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out93_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out94_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out95_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out96_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out97_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out98_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_probe_out99_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_sl_oport0_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
attribute C_BUILD_REVISION : integer;
attribute C_BUILD_REVISION of inst : label is 0;
attribute C_BUS_ADDR_WIDTH : integer;
attribute C_BUS_ADDR_WIDTH of inst : label is 17;
attribute C_BUS_DATA_WIDTH : integer;
attribute C_BUS_DATA_WIDTH of inst : label is 16;
attribute C_CORE_INFO1 : string;
attribute C_CORE_INFO1 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_INFO2 : string;
attribute C_CORE_INFO2 of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_CORE_MAJOR_VER : integer;
attribute C_CORE_MAJOR_VER of inst : label is 2;
attribute C_CORE_MINOR_ALPHA_VER : integer;
attribute C_CORE_MINOR_ALPHA_VER of inst : label is 97;
attribute C_CORE_MINOR_VER : integer;
attribute C_CORE_MINOR_VER of inst : label is 0;
attribute C_CORE_TYPE : integer;
attribute C_CORE_TYPE of inst : label is 2;
attribute C_CSE_DRV_VER : integer;
attribute C_CSE_DRV_VER of inst : label is 1;
attribute C_EN_PROBE_IN_ACTIVITY : integer;
attribute C_EN_PROBE_IN_ACTIVITY of inst : label is 1;
attribute C_EN_SYNCHRONIZATION : integer;
attribute C_EN_SYNCHRONIZATION of inst : label is 1;
attribute C_MAJOR_VERSION : integer;
attribute C_MAJOR_VERSION of inst : label is 2013;
attribute C_MAX_NUM_PROBE : integer;
attribute C_MAX_NUM_PROBE of inst : label is 256;
attribute C_MAX_WIDTH_PER_PROBE : integer;
attribute C_MAX_WIDTH_PER_PROBE of inst : label is 256;
attribute C_MINOR_VERSION : integer;
attribute C_MINOR_VERSION of inst : label is 1;
attribute C_NEXT_SLAVE : integer;
attribute C_NEXT_SLAVE of inst : label is 0;
attribute C_NUM_PROBE_IN : integer;
attribute C_NUM_PROBE_IN of inst : label is 4;
attribute C_NUM_PROBE_OUT : integer;
attribute C_NUM_PROBE_OUT of inst : label is 0;
attribute C_PIPE_IFACE : integer;
attribute C_PIPE_IFACE of inst : label is 0;
attribute C_PROBE_IN0_WIDTH : integer;
attribute C_PROBE_IN0_WIDTH of inst : label is 1;
attribute C_PROBE_IN100_WIDTH : integer;
attribute C_PROBE_IN100_WIDTH of inst : label is 1;
attribute C_PROBE_IN101_WIDTH : integer;
attribute C_PROBE_IN101_WIDTH of inst : label is 1;
attribute C_PROBE_IN102_WIDTH : integer;
attribute C_PROBE_IN102_WIDTH of inst : label is 1;
attribute C_PROBE_IN103_WIDTH : integer;
attribute C_PROBE_IN103_WIDTH of inst : label is 1;
attribute C_PROBE_IN104_WIDTH : integer;
attribute C_PROBE_IN104_WIDTH of inst : label is 1;
attribute C_PROBE_IN105_WIDTH : integer;
attribute C_PROBE_IN105_WIDTH of inst : label is 1;
attribute C_PROBE_IN106_WIDTH : integer;
attribute C_PROBE_IN106_WIDTH of inst : label is 1;
attribute C_PROBE_IN107_WIDTH : integer;
attribute C_PROBE_IN107_WIDTH of inst : label is 1;
attribute C_PROBE_IN108_WIDTH : integer;
attribute C_PROBE_IN108_WIDTH of inst : label is 1;
attribute C_PROBE_IN109_WIDTH : integer;
attribute C_PROBE_IN109_WIDTH of inst : label is 1;
attribute C_PROBE_IN10_WIDTH : integer;
attribute C_PROBE_IN10_WIDTH of inst : label is 1;
attribute C_PROBE_IN110_WIDTH : integer;
attribute C_PROBE_IN110_WIDTH of inst : label is 1;
attribute C_PROBE_IN111_WIDTH : integer;
attribute C_PROBE_IN111_WIDTH of inst : label is 1;
attribute C_PROBE_IN112_WIDTH : integer;
attribute C_PROBE_IN112_WIDTH of inst : label is 1;
attribute C_PROBE_IN113_WIDTH : integer;
attribute C_PROBE_IN113_WIDTH of inst : label is 1;
attribute C_PROBE_IN114_WIDTH : integer;
attribute C_PROBE_IN114_WIDTH of inst : label is 1;
attribute C_PROBE_IN115_WIDTH : integer;
attribute C_PROBE_IN115_WIDTH of inst : label is 1;
attribute C_PROBE_IN116_WIDTH : integer;
attribute C_PROBE_IN116_WIDTH of inst : label is 1;
attribute C_PROBE_IN117_WIDTH : integer;
attribute C_PROBE_IN117_WIDTH of inst : label is 1;
attribute C_PROBE_IN118_WIDTH : integer;
attribute C_PROBE_IN118_WIDTH of inst : label is 1;
attribute C_PROBE_IN119_WIDTH : integer;
attribute C_PROBE_IN119_WIDTH of inst : label is 1;
attribute C_PROBE_IN11_WIDTH : integer;
attribute C_PROBE_IN11_WIDTH of inst : label is 1;
attribute C_PROBE_IN120_WIDTH : integer;
attribute C_PROBE_IN120_WIDTH of inst : label is 1;
attribute C_PROBE_IN121_WIDTH : integer;
attribute C_PROBE_IN121_WIDTH of inst : label is 1;
attribute C_PROBE_IN122_WIDTH : integer;
attribute C_PROBE_IN122_WIDTH of inst : label is 1;
attribute C_PROBE_IN123_WIDTH : integer;
attribute C_PROBE_IN123_WIDTH of inst : label is 1;
attribute C_PROBE_IN124_WIDTH : integer;
attribute C_PROBE_IN124_WIDTH of inst : label is 1;
attribute C_PROBE_IN125_WIDTH : integer;
attribute C_PROBE_IN125_WIDTH of inst : label is 1;
attribute C_PROBE_IN126_WIDTH : integer;
attribute C_PROBE_IN126_WIDTH of inst : label is 1;
attribute C_PROBE_IN127_WIDTH : integer;
attribute C_PROBE_IN127_WIDTH of inst : label is 1;
attribute C_PROBE_IN128_WIDTH : integer;
attribute C_PROBE_IN128_WIDTH of inst : label is 1;
attribute C_PROBE_IN129_WIDTH : integer;
attribute C_PROBE_IN129_WIDTH of inst : label is 1;
attribute C_PROBE_IN12_WIDTH : integer;
attribute C_PROBE_IN12_WIDTH of inst : label is 1;
attribute C_PROBE_IN130_WIDTH : integer;
attribute C_PROBE_IN130_WIDTH of inst : label is 1;
attribute C_PROBE_IN131_WIDTH : integer;
attribute C_PROBE_IN131_WIDTH of inst : label is 1;
attribute C_PROBE_IN132_WIDTH : integer;
attribute C_PROBE_IN132_WIDTH of inst : label is 1;
attribute C_PROBE_IN133_WIDTH : integer;
attribute C_PROBE_IN133_WIDTH of inst : label is 1;
attribute C_PROBE_IN134_WIDTH : integer;
attribute C_PROBE_IN134_WIDTH of inst : label is 1;
attribute C_PROBE_IN135_WIDTH : integer;
attribute C_PROBE_IN135_WIDTH of inst : label is 1;
attribute C_PROBE_IN136_WIDTH : integer;
attribute C_PROBE_IN136_WIDTH of inst : label is 1;
attribute C_PROBE_IN137_WIDTH : integer;
attribute C_PROBE_IN137_WIDTH of inst : label is 1;
attribute C_PROBE_IN138_WIDTH : integer;
attribute C_PROBE_IN138_WIDTH of inst : label is 1;
attribute C_PROBE_IN139_WIDTH : integer;
attribute C_PROBE_IN139_WIDTH of inst : label is 1;
attribute C_PROBE_IN13_WIDTH : integer;
attribute C_PROBE_IN13_WIDTH of inst : label is 1;
attribute C_PROBE_IN140_WIDTH : integer;
attribute C_PROBE_IN140_WIDTH of inst : label is 1;
attribute C_PROBE_IN141_WIDTH : integer;
attribute C_PROBE_IN141_WIDTH of inst : label is 1;
attribute C_PROBE_IN142_WIDTH : integer;
attribute C_PROBE_IN142_WIDTH of inst : label is 1;
attribute C_PROBE_IN143_WIDTH : integer;
attribute C_PROBE_IN143_WIDTH of inst : label is 1;
attribute C_PROBE_IN144_WIDTH : integer;
attribute C_PROBE_IN144_WIDTH of inst : label is 1;
attribute C_PROBE_IN145_WIDTH : integer;
attribute C_PROBE_IN145_WIDTH of inst : label is 1;
attribute C_PROBE_IN146_WIDTH : integer;
attribute C_PROBE_IN146_WIDTH of inst : label is 1;
attribute C_PROBE_IN147_WIDTH : integer;
attribute C_PROBE_IN147_WIDTH of inst : label is 1;
attribute C_PROBE_IN148_WIDTH : integer;
attribute C_PROBE_IN148_WIDTH of inst : label is 1;
attribute C_PROBE_IN149_WIDTH : integer;
attribute C_PROBE_IN149_WIDTH of inst : label is 1;
attribute C_PROBE_IN14_WIDTH : integer;
attribute C_PROBE_IN14_WIDTH of inst : label is 1;
attribute C_PROBE_IN150_WIDTH : integer;
attribute C_PROBE_IN150_WIDTH of inst : label is 1;
attribute C_PROBE_IN151_WIDTH : integer;
attribute C_PROBE_IN151_WIDTH of inst : label is 1;
attribute C_PROBE_IN152_WIDTH : integer;
attribute C_PROBE_IN152_WIDTH of inst : label is 1;
attribute C_PROBE_IN153_WIDTH : integer;
attribute C_PROBE_IN153_WIDTH of inst : label is 1;
attribute C_PROBE_IN154_WIDTH : integer;
attribute C_PROBE_IN154_WIDTH of inst : label is 1;
attribute C_PROBE_IN155_WIDTH : integer;
attribute C_PROBE_IN155_WIDTH of inst : label is 1;
attribute C_PROBE_IN156_WIDTH : integer;
attribute C_PROBE_IN156_WIDTH of inst : label is 1;
attribute C_PROBE_IN157_WIDTH : integer;
attribute C_PROBE_IN157_WIDTH of inst : label is 1;
attribute C_PROBE_IN158_WIDTH : integer;
attribute C_PROBE_IN158_WIDTH of inst : label is 1;
attribute C_PROBE_IN159_WIDTH : integer;
attribute C_PROBE_IN159_WIDTH of inst : label is 1;
attribute C_PROBE_IN15_WIDTH : integer;
attribute C_PROBE_IN15_WIDTH of inst : label is 1;
attribute C_PROBE_IN160_WIDTH : integer;
attribute C_PROBE_IN160_WIDTH of inst : label is 1;
attribute C_PROBE_IN161_WIDTH : integer;
attribute C_PROBE_IN161_WIDTH of inst : label is 1;
attribute C_PROBE_IN162_WIDTH : integer;
attribute C_PROBE_IN162_WIDTH of inst : label is 1;
attribute C_PROBE_IN163_WIDTH : integer;
attribute C_PROBE_IN163_WIDTH of inst : label is 1;
attribute C_PROBE_IN164_WIDTH : integer;
attribute C_PROBE_IN164_WIDTH of inst : label is 1;
attribute C_PROBE_IN165_WIDTH : integer;
attribute C_PROBE_IN165_WIDTH of inst : label is 1;
attribute C_PROBE_IN166_WIDTH : integer;
attribute C_PROBE_IN166_WIDTH of inst : label is 1;
attribute C_PROBE_IN167_WIDTH : integer;
attribute C_PROBE_IN167_WIDTH of inst : label is 1;
attribute C_PROBE_IN168_WIDTH : integer;
attribute C_PROBE_IN168_WIDTH of inst : label is 1;
attribute C_PROBE_IN169_WIDTH : integer;
attribute C_PROBE_IN169_WIDTH of inst : label is 1;
attribute C_PROBE_IN16_WIDTH : integer;
attribute C_PROBE_IN16_WIDTH of inst : label is 1;
attribute C_PROBE_IN170_WIDTH : integer;
attribute C_PROBE_IN170_WIDTH of inst : label is 1;
attribute C_PROBE_IN171_WIDTH : integer;
attribute C_PROBE_IN171_WIDTH of inst : label is 1;
attribute C_PROBE_IN172_WIDTH : integer;
attribute C_PROBE_IN172_WIDTH of inst : label is 1;
attribute C_PROBE_IN173_WIDTH : integer;
attribute C_PROBE_IN173_WIDTH of inst : label is 1;
attribute C_PROBE_IN174_WIDTH : integer;
attribute C_PROBE_IN174_WIDTH of inst : label is 1;
attribute C_PROBE_IN175_WIDTH : integer;
attribute C_PROBE_IN175_WIDTH of inst : label is 1;
attribute C_PROBE_IN176_WIDTH : integer;
attribute C_PROBE_IN176_WIDTH of inst : label is 1;
attribute C_PROBE_IN177_WIDTH : integer;
attribute C_PROBE_IN177_WIDTH of inst : label is 1;
attribute C_PROBE_IN178_WIDTH : integer;
attribute C_PROBE_IN178_WIDTH of inst : label is 1;
attribute C_PROBE_IN179_WIDTH : integer;
attribute C_PROBE_IN179_WIDTH of inst : label is 1;
attribute C_PROBE_IN17_WIDTH : integer;
attribute C_PROBE_IN17_WIDTH of inst : label is 1;
attribute C_PROBE_IN180_WIDTH : integer;
attribute C_PROBE_IN180_WIDTH of inst : label is 1;
attribute C_PROBE_IN181_WIDTH : integer;
attribute C_PROBE_IN181_WIDTH of inst : label is 1;
attribute C_PROBE_IN182_WIDTH : integer;
attribute C_PROBE_IN182_WIDTH of inst : label is 1;
attribute C_PROBE_IN183_WIDTH : integer;
attribute C_PROBE_IN183_WIDTH of inst : label is 1;
attribute C_PROBE_IN184_WIDTH : integer;
attribute C_PROBE_IN184_WIDTH of inst : label is 1;
attribute C_PROBE_IN185_WIDTH : integer;
attribute C_PROBE_IN185_WIDTH of inst : label is 1;
attribute C_PROBE_IN186_WIDTH : integer;
attribute C_PROBE_IN186_WIDTH of inst : label is 1;
attribute C_PROBE_IN187_WIDTH : integer;
attribute C_PROBE_IN187_WIDTH of inst : label is 1;
attribute C_PROBE_IN188_WIDTH : integer;
attribute C_PROBE_IN188_WIDTH of inst : label is 1;
attribute C_PROBE_IN189_WIDTH : integer;
attribute C_PROBE_IN189_WIDTH of inst : label is 1;
attribute C_PROBE_IN18_WIDTH : integer;
attribute C_PROBE_IN18_WIDTH of inst : label is 1;
attribute C_PROBE_IN190_WIDTH : integer;
attribute C_PROBE_IN190_WIDTH of inst : label is 1;
attribute C_PROBE_IN191_WIDTH : integer;
attribute C_PROBE_IN191_WIDTH of inst : label is 1;
attribute C_PROBE_IN192_WIDTH : integer;
attribute C_PROBE_IN192_WIDTH of inst : label is 1;
attribute C_PROBE_IN193_WIDTH : integer;
attribute C_PROBE_IN193_WIDTH of inst : label is 1;
attribute C_PROBE_IN194_WIDTH : integer;
attribute C_PROBE_IN194_WIDTH of inst : label is 1;
attribute C_PROBE_IN195_WIDTH : integer;
attribute C_PROBE_IN195_WIDTH of inst : label is 1;
attribute C_PROBE_IN196_WIDTH : integer;
attribute C_PROBE_IN196_WIDTH of inst : label is 1;
attribute C_PROBE_IN197_WIDTH : integer;
attribute C_PROBE_IN197_WIDTH of inst : label is 1;
attribute C_PROBE_IN198_WIDTH : integer;
attribute C_PROBE_IN198_WIDTH of inst : label is 1;
attribute C_PROBE_IN199_WIDTH : integer;
attribute C_PROBE_IN199_WIDTH of inst : label is 1;
attribute C_PROBE_IN19_WIDTH : integer;
attribute C_PROBE_IN19_WIDTH of inst : label is 1;
attribute C_PROBE_IN1_WIDTH : integer;
attribute C_PROBE_IN1_WIDTH of inst : label is 1;
attribute C_PROBE_IN200_WIDTH : integer;
attribute C_PROBE_IN200_WIDTH of inst : label is 1;
attribute C_PROBE_IN201_WIDTH : integer;
attribute C_PROBE_IN201_WIDTH of inst : label is 1;
attribute C_PROBE_IN202_WIDTH : integer;
attribute C_PROBE_IN202_WIDTH of inst : label is 1;
attribute C_PROBE_IN203_WIDTH : integer;
attribute C_PROBE_IN203_WIDTH of inst : label is 1;
attribute C_PROBE_IN204_WIDTH : integer;
attribute C_PROBE_IN204_WIDTH of inst : label is 1;
attribute C_PROBE_IN205_WIDTH : integer;
attribute C_PROBE_IN205_WIDTH of inst : label is 1;
attribute C_PROBE_IN206_WIDTH : integer;
attribute C_PROBE_IN206_WIDTH of inst : label is 1;
attribute C_PROBE_IN207_WIDTH : integer;
attribute C_PROBE_IN207_WIDTH of inst : label is 1;
attribute C_PROBE_IN208_WIDTH : integer;
attribute C_PROBE_IN208_WIDTH of inst : label is 1;
attribute C_PROBE_IN209_WIDTH : integer;
attribute C_PROBE_IN209_WIDTH of inst : label is 1;
attribute C_PROBE_IN20_WIDTH : integer;
attribute C_PROBE_IN20_WIDTH of inst : label is 1;
attribute C_PROBE_IN210_WIDTH : integer;
attribute C_PROBE_IN210_WIDTH of inst : label is 1;
attribute C_PROBE_IN211_WIDTH : integer;
attribute C_PROBE_IN211_WIDTH of inst : label is 1;
attribute C_PROBE_IN212_WIDTH : integer;
attribute C_PROBE_IN212_WIDTH of inst : label is 1;
attribute C_PROBE_IN213_WIDTH : integer;
attribute C_PROBE_IN213_WIDTH of inst : label is 1;
attribute C_PROBE_IN214_WIDTH : integer;
attribute C_PROBE_IN214_WIDTH of inst : label is 1;
attribute C_PROBE_IN215_WIDTH : integer;
attribute C_PROBE_IN215_WIDTH of inst : label is 1;
attribute C_PROBE_IN216_WIDTH : integer;
attribute C_PROBE_IN216_WIDTH of inst : label is 1;
attribute C_PROBE_IN217_WIDTH : integer;
attribute C_PROBE_IN217_WIDTH of inst : label is 1;
attribute C_PROBE_IN218_WIDTH : integer;
attribute C_PROBE_IN218_WIDTH of inst : label is 1;
attribute C_PROBE_IN219_WIDTH : integer;
attribute C_PROBE_IN219_WIDTH of inst : label is 1;
attribute C_PROBE_IN21_WIDTH : integer;
attribute C_PROBE_IN21_WIDTH of inst : label is 1;
attribute C_PROBE_IN220_WIDTH : integer;
attribute C_PROBE_IN220_WIDTH of inst : label is 1;
attribute C_PROBE_IN221_WIDTH : integer;
attribute C_PROBE_IN221_WIDTH of inst : label is 1;
attribute C_PROBE_IN222_WIDTH : integer;
attribute C_PROBE_IN222_WIDTH of inst : label is 1;
attribute C_PROBE_IN223_WIDTH : integer;
attribute C_PROBE_IN223_WIDTH of inst : label is 1;
attribute C_PROBE_IN224_WIDTH : integer;
attribute C_PROBE_IN224_WIDTH of inst : label is 1;
attribute C_PROBE_IN225_WIDTH : integer;
attribute C_PROBE_IN225_WIDTH of inst : label is 1;
attribute C_PROBE_IN226_WIDTH : integer;
attribute C_PROBE_IN226_WIDTH of inst : label is 1;
attribute C_PROBE_IN227_WIDTH : integer;
attribute C_PROBE_IN227_WIDTH of inst : label is 1;
attribute C_PROBE_IN228_WIDTH : integer;
attribute C_PROBE_IN228_WIDTH of inst : label is 1;
attribute C_PROBE_IN229_WIDTH : integer;
attribute C_PROBE_IN229_WIDTH of inst : label is 1;
attribute C_PROBE_IN22_WIDTH : integer;
attribute C_PROBE_IN22_WIDTH of inst : label is 1;
attribute C_PROBE_IN230_WIDTH : integer;
attribute C_PROBE_IN230_WIDTH of inst : label is 1;
attribute C_PROBE_IN231_WIDTH : integer;
attribute C_PROBE_IN231_WIDTH of inst : label is 1;
attribute C_PROBE_IN232_WIDTH : integer;
attribute C_PROBE_IN232_WIDTH of inst : label is 1;
attribute C_PROBE_IN233_WIDTH : integer;
attribute C_PROBE_IN233_WIDTH of inst : label is 1;
attribute C_PROBE_IN234_WIDTH : integer;
attribute C_PROBE_IN234_WIDTH of inst : label is 1;
attribute C_PROBE_IN235_WIDTH : integer;
attribute C_PROBE_IN235_WIDTH of inst : label is 1;
attribute C_PROBE_IN236_WIDTH : integer;
attribute C_PROBE_IN236_WIDTH of inst : label is 1;
attribute C_PROBE_IN237_WIDTH : integer;
attribute C_PROBE_IN237_WIDTH of inst : label is 1;
attribute C_PROBE_IN238_WIDTH : integer;
attribute C_PROBE_IN238_WIDTH of inst : label is 1;
attribute C_PROBE_IN239_WIDTH : integer;
attribute C_PROBE_IN239_WIDTH of inst : label is 1;
attribute C_PROBE_IN23_WIDTH : integer;
attribute C_PROBE_IN23_WIDTH of inst : label is 1;
attribute C_PROBE_IN240_WIDTH : integer;
attribute C_PROBE_IN240_WIDTH of inst : label is 1;
attribute C_PROBE_IN241_WIDTH : integer;
attribute C_PROBE_IN241_WIDTH of inst : label is 1;
attribute C_PROBE_IN242_WIDTH : integer;
attribute C_PROBE_IN242_WIDTH of inst : label is 1;
attribute C_PROBE_IN243_WIDTH : integer;
attribute C_PROBE_IN243_WIDTH of inst : label is 1;
attribute C_PROBE_IN244_WIDTH : integer;
attribute C_PROBE_IN244_WIDTH of inst : label is 1;
attribute C_PROBE_IN245_WIDTH : integer;
attribute C_PROBE_IN245_WIDTH of inst : label is 1;
attribute C_PROBE_IN246_WIDTH : integer;
attribute C_PROBE_IN246_WIDTH of inst : label is 1;
attribute C_PROBE_IN247_WIDTH : integer;
attribute C_PROBE_IN247_WIDTH of inst : label is 1;
attribute C_PROBE_IN248_WIDTH : integer;
attribute C_PROBE_IN248_WIDTH of inst : label is 1;
attribute C_PROBE_IN249_WIDTH : integer;
attribute C_PROBE_IN249_WIDTH of inst : label is 1;
attribute C_PROBE_IN24_WIDTH : integer;
attribute C_PROBE_IN24_WIDTH of inst : label is 1;
attribute C_PROBE_IN250_WIDTH : integer;
attribute C_PROBE_IN250_WIDTH of inst : label is 1;
attribute C_PROBE_IN251_WIDTH : integer;
attribute C_PROBE_IN251_WIDTH of inst : label is 1;
attribute C_PROBE_IN252_WIDTH : integer;
attribute C_PROBE_IN252_WIDTH of inst : label is 1;
attribute C_PROBE_IN253_WIDTH : integer;
attribute C_PROBE_IN253_WIDTH of inst : label is 1;
attribute C_PROBE_IN254_WIDTH : integer;
attribute C_PROBE_IN254_WIDTH of inst : label is 1;
attribute C_PROBE_IN255_WIDTH : integer;
attribute C_PROBE_IN255_WIDTH of inst : label is 1;
attribute C_PROBE_IN25_WIDTH : integer;
attribute C_PROBE_IN25_WIDTH of inst : label is 1;
attribute C_PROBE_IN26_WIDTH : integer;
attribute C_PROBE_IN26_WIDTH of inst : label is 1;
attribute C_PROBE_IN27_WIDTH : integer;
attribute C_PROBE_IN27_WIDTH of inst : label is 1;
attribute C_PROBE_IN28_WIDTH : integer;
attribute C_PROBE_IN28_WIDTH of inst : label is 1;
attribute C_PROBE_IN29_WIDTH : integer;
attribute C_PROBE_IN29_WIDTH of inst : label is 1;
attribute C_PROBE_IN2_WIDTH : integer;
attribute C_PROBE_IN2_WIDTH of inst : label is 1;
attribute C_PROBE_IN30_WIDTH : integer;
attribute C_PROBE_IN30_WIDTH of inst : label is 1;
attribute C_PROBE_IN31_WIDTH : integer;
attribute C_PROBE_IN31_WIDTH of inst : label is 1;
attribute C_PROBE_IN32_WIDTH : integer;
attribute C_PROBE_IN32_WIDTH of inst : label is 1;
attribute C_PROBE_IN33_WIDTH : integer;
attribute C_PROBE_IN33_WIDTH of inst : label is 1;
attribute C_PROBE_IN34_WIDTH : integer;
attribute C_PROBE_IN34_WIDTH of inst : label is 1;
attribute C_PROBE_IN35_WIDTH : integer;
attribute C_PROBE_IN35_WIDTH of inst : label is 1;
attribute C_PROBE_IN36_WIDTH : integer;
attribute C_PROBE_IN36_WIDTH of inst : label is 1;
attribute C_PROBE_IN37_WIDTH : integer;
attribute C_PROBE_IN37_WIDTH of inst : label is 1;
attribute C_PROBE_IN38_WIDTH : integer;
attribute C_PROBE_IN38_WIDTH of inst : label is 1;
attribute C_PROBE_IN39_WIDTH : integer;
attribute C_PROBE_IN39_WIDTH of inst : label is 1;
attribute C_PROBE_IN3_WIDTH : integer;
attribute C_PROBE_IN3_WIDTH of inst : label is 1;
attribute C_PROBE_IN40_WIDTH : integer;
attribute C_PROBE_IN40_WIDTH of inst : label is 1;
attribute C_PROBE_IN41_WIDTH : integer;
attribute C_PROBE_IN41_WIDTH of inst : label is 1;
attribute C_PROBE_IN42_WIDTH : integer;
attribute C_PROBE_IN42_WIDTH of inst : label is 1;
attribute C_PROBE_IN43_WIDTH : integer;
attribute C_PROBE_IN43_WIDTH of inst : label is 1;
attribute C_PROBE_IN44_WIDTH : integer;
attribute C_PROBE_IN44_WIDTH of inst : label is 1;
attribute C_PROBE_IN45_WIDTH : integer;
attribute C_PROBE_IN45_WIDTH of inst : label is 1;
attribute C_PROBE_IN46_WIDTH : integer;
attribute C_PROBE_IN46_WIDTH of inst : label is 1;
attribute C_PROBE_IN47_WIDTH : integer;
attribute C_PROBE_IN47_WIDTH of inst : label is 1;
attribute C_PROBE_IN48_WIDTH : integer;
attribute C_PROBE_IN48_WIDTH of inst : label is 1;
attribute C_PROBE_IN49_WIDTH : integer;
attribute C_PROBE_IN49_WIDTH of inst : label is 1;
attribute C_PROBE_IN4_WIDTH : integer;
attribute C_PROBE_IN4_WIDTH of inst : label is 1;
attribute C_PROBE_IN50_WIDTH : integer;
attribute C_PROBE_IN50_WIDTH of inst : label is 1;
attribute C_PROBE_IN51_WIDTH : integer;
attribute C_PROBE_IN51_WIDTH of inst : label is 1;
attribute C_PROBE_IN52_WIDTH : integer;
attribute C_PROBE_IN52_WIDTH of inst : label is 1;
attribute C_PROBE_IN53_WIDTH : integer;
attribute C_PROBE_IN53_WIDTH of inst : label is 1;
attribute C_PROBE_IN54_WIDTH : integer;
attribute C_PROBE_IN54_WIDTH of inst : label is 1;
attribute C_PROBE_IN55_WIDTH : integer;
attribute C_PROBE_IN55_WIDTH of inst : label is 1;
attribute C_PROBE_IN56_WIDTH : integer;
attribute C_PROBE_IN56_WIDTH of inst : label is 1;
attribute C_PROBE_IN57_WIDTH : integer;
attribute C_PROBE_IN57_WIDTH of inst : label is 1;
attribute C_PROBE_IN58_WIDTH : integer;
attribute C_PROBE_IN58_WIDTH of inst : label is 1;
attribute C_PROBE_IN59_WIDTH : integer;
attribute C_PROBE_IN59_WIDTH of inst : label is 1;
attribute C_PROBE_IN5_WIDTH : integer;
attribute C_PROBE_IN5_WIDTH of inst : label is 1;
attribute C_PROBE_IN60_WIDTH : integer;
attribute C_PROBE_IN60_WIDTH of inst : label is 1;
attribute C_PROBE_IN61_WIDTH : integer;
attribute C_PROBE_IN61_WIDTH of inst : label is 1;
attribute C_PROBE_IN62_WIDTH : integer;
attribute C_PROBE_IN62_WIDTH of inst : label is 1;
attribute C_PROBE_IN63_WIDTH : integer;
attribute C_PROBE_IN63_WIDTH of inst : label is 1;
attribute C_PROBE_IN64_WIDTH : integer;
attribute C_PROBE_IN64_WIDTH of inst : label is 1;
attribute C_PROBE_IN65_WIDTH : integer;
attribute C_PROBE_IN65_WIDTH of inst : label is 1;
attribute C_PROBE_IN66_WIDTH : integer;
attribute C_PROBE_IN66_WIDTH of inst : label is 1;
attribute C_PROBE_IN67_WIDTH : integer;
attribute C_PROBE_IN67_WIDTH of inst : label is 1;
attribute C_PROBE_IN68_WIDTH : integer;
attribute C_PROBE_IN68_WIDTH of inst : label is 1;
attribute C_PROBE_IN69_WIDTH : integer;
attribute C_PROBE_IN69_WIDTH of inst : label is 1;
attribute C_PROBE_IN6_WIDTH : integer;
attribute C_PROBE_IN6_WIDTH of inst : label is 1;
attribute C_PROBE_IN70_WIDTH : integer;
attribute C_PROBE_IN70_WIDTH of inst : label is 1;
attribute C_PROBE_IN71_WIDTH : integer;
attribute C_PROBE_IN71_WIDTH of inst : label is 1;
attribute C_PROBE_IN72_WIDTH : integer;
attribute C_PROBE_IN72_WIDTH of inst : label is 1;
attribute C_PROBE_IN73_WIDTH : integer;
attribute C_PROBE_IN73_WIDTH of inst : label is 1;
attribute C_PROBE_IN74_WIDTH : integer;
attribute C_PROBE_IN74_WIDTH of inst : label is 1;
attribute C_PROBE_IN75_WIDTH : integer;
attribute C_PROBE_IN75_WIDTH of inst : label is 1;
attribute C_PROBE_IN76_WIDTH : integer;
attribute C_PROBE_IN76_WIDTH of inst : label is 1;
attribute C_PROBE_IN77_WIDTH : integer;
attribute C_PROBE_IN77_WIDTH of inst : label is 1;
attribute C_PROBE_IN78_WIDTH : integer;
attribute C_PROBE_IN78_WIDTH of inst : label is 1;
attribute C_PROBE_IN79_WIDTH : integer;
attribute C_PROBE_IN79_WIDTH of inst : label is 1;
attribute C_PROBE_IN7_WIDTH : integer;
attribute C_PROBE_IN7_WIDTH of inst : label is 1;
attribute C_PROBE_IN80_WIDTH : integer;
attribute C_PROBE_IN80_WIDTH of inst : label is 1;
attribute C_PROBE_IN81_WIDTH : integer;
attribute C_PROBE_IN81_WIDTH of inst : label is 1;
attribute C_PROBE_IN82_WIDTH : integer;
attribute C_PROBE_IN82_WIDTH of inst : label is 1;
attribute C_PROBE_IN83_WIDTH : integer;
attribute C_PROBE_IN83_WIDTH of inst : label is 1;
attribute C_PROBE_IN84_WIDTH : integer;
attribute C_PROBE_IN84_WIDTH of inst : label is 1;
attribute C_PROBE_IN85_WIDTH : integer;
attribute C_PROBE_IN85_WIDTH of inst : label is 1;
attribute C_PROBE_IN86_WIDTH : integer;
attribute C_PROBE_IN86_WIDTH of inst : label is 1;
attribute C_PROBE_IN87_WIDTH : integer;
attribute C_PROBE_IN87_WIDTH of inst : label is 1;
attribute C_PROBE_IN88_WIDTH : integer;
attribute C_PROBE_IN88_WIDTH of inst : label is 1;
attribute C_PROBE_IN89_WIDTH : integer;
attribute C_PROBE_IN89_WIDTH of inst : label is 1;
attribute C_PROBE_IN8_WIDTH : integer;
attribute C_PROBE_IN8_WIDTH of inst : label is 1;
attribute C_PROBE_IN90_WIDTH : integer;
attribute C_PROBE_IN90_WIDTH of inst : label is 1;
attribute C_PROBE_IN91_WIDTH : integer;
attribute C_PROBE_IN91_WIDTH of inst : label is 1;
attribute C_PROBE_IN92_WIDTH : integer;
attribute C_PROBE_IN92_WIDTH of inst : label is 1;
attribute C_PROBE_IN93_WIDTH : integer;
attribute C_PROBE_IN93_WIDTH of inst : label is 1;
attribute C_PROBE_IN94_WIDTH : integer;
attribute C_PROBE_IN94_WIDTH of inst : label is 1;
attribute C_PROBE_IN95_WIDTH : integer;
attribute C_PROBE_IN95_WIDTH of inst : label is 1;
attribute C_PROBE_IN96_WIDTH : integer;
attribute C_PROBE_IN96_WIDTH of inst : label is 1;
attribute C_PROBE_IN97_WIDTH : integer;
attribute C_PROBE_IN97_WIDTH of inst : label is 1;
attribute C_PROBE_IN98_WIDTH : integer;
attribute C_PROBE_IN98_WIDTH of inst : label is 1;
attribute C_PROBE_IN99_WIDTH : integer;
attribute C_PROBE_IN99_WIDTH of inst : label is 1;
attribute C_PROBE_IN9_WIDTH : integer;
attribute C_PROBE_IN9_WIDTH of inst : label is 1;
attribute C_PROBE_OUT0_INIT_VAL : string;
attribute C_PROBE_OUT0_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT0_WIDTH : integer;
attribute C_PROBE_OUT0_WIDTH of inst : label is 1;
attribute C_PROBE_OUT100_INIT_VAL : string;
attribute C_PROBE_OUT100_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT100_WIDTH : integer;
attribute C_PROBE_OUT100_WIDTH of inst : label is 1;
attribute C_PROBE_OUT101_INIT_VAL : string;
attribute C_PROBE_OUT101_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT101_WIDTH : integer;
attribute C_PROBE_OUT101_WIDTH of inst : label is 1;
attribute C_PROBE_OUT102_INIT_VAL : string;
attribute C_PROBE_OUT102_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT102_WIDTH : integer;
attribute C_PROBE_OUT102_WIDTH of inst : label is 1;
attribute C_PROBE_OUT103_INIT_VAL : string;
attribute C_PROBE_OUT103_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT103_WIDTH : integer;
attribute C_PROBE_OUT103_WIDTH of inst : label is 1;
attribute C_PROBE_OUT104_INIT_VAL : string;
attribute C_PROBE_OUT104_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT104_WIDTH : integer;
attribute C_PROBE_OUT104_WIDTH of inst : label is 1;
attribute C_PROBE_OUT105_INIT_VAL : string;
attribute C_PROBE_OUT105_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT105_WIDTH : integer;
attribute C_PROBE_OUT105_WIDTH of inst : label is 1;
attribute C_PROBE_OUT106_INIT_VAL : string;
attribute C_PROBE_OUT106_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT106_WIDTH : integer;
attribute C_PROBE_OUT106_WIDTH of inst : label is 1;
attribute C_PROBE_OUT107_INIT_VAL : string;
attribute C_PROBE_OUT107_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT107_WIDTH : integer;
attribute C_PROBE_OUT107_WIDTH of inst : label is 1;
attribute C_PROBE_OUT108_INIT_VAL : string;
attribute C_PROBE_OUT108_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT108_WIDTH : integer;
attribute C_PROBE_OUT108_WIDTH of inst : label is 1;
attribute C_PROBE_OUT109_INIT_VAL : string;
attribute C_PROBE_OUT109_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT109_WIDTH : integer;
attribute C_PROBE_OUT109_WIDTH of inst : label is 1;
attribute C_PROBE_OUT10_INIT_VAL : string;
attribute C_PROBE_OUT10_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT10_WIDTH : integer;
attribute C_PROBE_OUT10_WIDTH of inst : label is 1;
attribute C_PROBE_OUT110_INIT_VAL : string;
attribute C_PROBE_OUT110_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT110_WIDTH : integer;
attribute C_PROBE_OUT110_WIDTH of inst : label is 1;
attribute C_PROBE_OUT111_INIT_VAL : string;
attribute C_PROBE_OUT111_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT111_WIDTH : integer;
attribute C_PROBE_OUT111_WIDTH of inst : label is 1;
attribute C_PROBE_OUT112_INIT_VAL : string;
attribute C_PROBE_OUT112_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT112_WIDTH : integer;
attribute C_PROBE_OUT112_WIDTH of inst : label is 1;
attribute C_PROBE_OUT113_INIT_VAL : string;
attribute C_PROBE_OUT113_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT113_WIDTH : integer;
attribute C_PROBE_OUT113_WIDTH of inst : label is 1;
attribute C_PROBE_OUT114_INIT_VAL : string;
attribute C_PROBE_OUT114_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT114_WIDTH : integer;
attribute C_PROBE_OUT114_WIDTH of inst : label is 1;
attribute C_PROBE_OUT115_INIT_VAL : string;
attribute C_PROBE_OUT115_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT115_WIDTH : integer;
attribute C_PROBE_OUT115_WIDTH of inst : label is 1;
attribute C_PROBE_OUT116_INIT_VAL : string;
attribute C_PROBE_OUT116_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT116_WIDTH : integer;
attribute C_PROBE_OUT116_WIDTH of inst : label is 1;
attribute C_PROBE_OUT117_INIT_VAL : string;
attribute C_PROBE_OUT117_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT117_WIDTH : integer;
attribute C_PROBE_OUT117_WIDTH of inst : label is 1;
attribute C_PROBE_OUT118_INIT_VAL : string;
attribute C_PROBE_OUT118_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT118_WIDTH : integer;
attribute C_PROBE_OUT118_WIDTH of inst : label is 1;
attribute C_PROBE_OUT119_INIT_VAL : string;
attribute C_PROBE_OUT119_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT119_WIDTH : integer;
attribute C_PROBE_OUT119_WIDTH of inst : label is 1;
attribute C_PROBE_OUT11_INIT_VAL : string;
attribute C_PROBE_OUT11_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT11_WIDTH : integer;
attribute C_PROBE_OUT11_WIDTH of inst : label is 1;
attribute C_PROBE_OUT120_INIT_VAL : string;
attribute C_PROBE_OUT120_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT120_WIDTH : integer;
attribute C_PROBE_OUT120_WIDTH of inst : label is 1;
attribute C_PROBE_OUT121_INIT_VAL : string;
attribute C_PROBE_OUT121_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT121_WIDTH : integer;
attribute C_PROBE_OUT121_WIDTH of inst : label is 1;
attribute C_PROBE_OUT122_INIT_VAL : string;
attribute C_PROBE_OUT122_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT122_WIDTH : integer;
attribute C_PROBE_OUT122_WIDTH of inst : label is 1;
attribute C_PROBE_OUT123_INIT_VAL : string;
attribute C_PROBE_OUT123_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT123_WIDTH : integer;
attribute C_PROBE_OUT123_WIDTH of inst : label is 1;
attribute C_PROBE_OUT124_INIT_VAL : string;
attribute C_PROBE_OUT124_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT124_WIDTH : integer;
attribute C_PROBE_OUT124_WIDTH of inst : label is 1;
attribute C_PROBE_OUT125_INIT_VAL : string;
attribute C_PROBE_OUT125_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT125_WIDTH : integer;
attribute C_PROBE_OUT125_WIDTH of inst : label is 1;
attribute C_PROBE_OUT126_INIT_VAL : string;
attribute C_PROBE_OUT126_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT126_WIDTH : integer;
attribute C_PROBE_OUT126_WIDTH of inst : label is 1;
attribute C_PROBE_OUT127_INIT_VAL : string;
attribute C_PROBE_OUT127_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT127_WIDTH : integer;
attribute C_PROBE_OUT127_WIDTH of inst : label is 1;
attribute C_PROBE_OUT128_INIT_VAL : string;
attribute C_PROBE_OUT128_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT128_WIDTH : integer;
attribute C_PROBE_OUT128_WIDTH of inst : label is 1;
attribute C_PROBE_OUT129_INIT_VAL : string;
attribute C_PROBE_OUT129_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT129_WIDTH : integer;
attribute C_PROBE_OUT129_WIDTH of inst : label is 1;
attribute C_PROBE_OUT12_INIT_VAL : string;
attribute C_PROBE_OUT12_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT12_WIDTH : integer;
attribute C_PROBE_OUT12_WIDTH of inst : label is 1;
attribute C_PROBE_OUT130_INIT_VAL : string;
attribute C_PROBE_OUT130_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT130_WIDTH : integer;
attribute C_PROBE_OUT130_WIDTH of inst : label is 1;
attribute C_PROBE_OUT131_INIT_VAL : string;
attribute C_PROBE_OUT131_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT131_WIDTH : integer;
attribute C_PROBE_OUT131_WIDTH of inst : label is 1;
attribute C_PROBE_OUT132_INIT_VAL : string;
attribute C_PROBE_OUT132_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT132_WIDTH : integer;
attribute C_PROBE_OUT132_WIDTH of inst : label is 1;
attribute C_PROBE_OUT133_INIT_VAL : string;
attribute C_PROBE_OUT133_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT133_WIDTH : integer;
attribute C_PROBE_OUT133_WIDTH of inst : label is 1;
attribute C_PROBE_OUT134_INIT_VAL : string;
attribute C_PROBE_OUT134_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT134_WIDTH : integer;
attribute C_PROBE_OUT134_WIDTH of inst : label is 1;
attribute C_PROBE_OUT135_INIT_VAL : string;
attribute C_PROBE_OUT135_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT135_WIDTH : integer;
attribute C_PROBE_OUT135_WIDTH of inst : label is 1;
attribute C_PROBE_OUT136_INIT_VAL : string;
attribute C_PROBE_OUT136_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT136_WIDTH : integer;
attribute C_PROBE_OUT136_WIDTH of inst : label is 1;
attribute C_PROBE_OUT137_INIT_VAL : string;
attribute C_PROBE_OUT137_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT137_WIDTH : integer;
attribute C_PROBE_OUT137_WIDTH of inst : label is 1;
attribute C_PROBE_OUT138_INIT_VAL : string;
attribute C_PROBE_OUT138_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT138_WIDTH : integer;
attribute C_PROBE_OUT138_WIDTH of inst : label is 1;
attribute C_PROBE_OUT139_INIT_VAL : string;
attribute C_PROBE_OUT139_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT139_WIDTH : integer;
attribute C_PROBE_OUT139_WIDTH of inst : label is 1;
attribute C_PROBE_OUT13_INIT_VAL : string;
attribute C_PROBE_OUT13_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT13_WIDTH : integer;
attribute C_PROBE_OUT13_WIDTH of inst : label is 1;
attribute C_PROBE_OUT140_INIT_VAL : string;
attribute C_PROBE_OUT140_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT140_WIDTH : integer;
attribute C_PROBE_OUT140_WIDTH of inst : label is 1;
attribute C_PROBE_OUT141_INIT_VAL : string;
attribute C_PROBE_OUT141_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT141_WIDTH : integer;
attribute C_PROBE_OUT141_WIDTH of inst : label is 1;
attribute C_PROBE_OUT142_INIT_VAL : string;
attribute C_PROBE_OUT142_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT142_WIDTH : integer;
attribute C_PROBE_OUT142_WIDTH of inst : label is 1;
attribute C_PROBE_OUT143_INIT_VAL : string;
attribute C_PROBE_OUT143_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT143_WIDTH : integer;
attribute C_PROBE_OUT143_WIDTH of inst : label is 1;
attribute C_PROBE_OUT144_INIT_VAL : string;
attribute C_PROBE_OUT144_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT144_WIDTH : integer;
attribute C_PROBE_OUT144_WIDTH of inst : label is 1;
attribute C_PROBE_OUT145_INIT_VAL : string;
attribute C_PROBE_OUT145_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT145_WIDTH : integer;
attribute C_PROBE_OUT145_WIDTH of inst : label is 1;
attribute C_PROBE_OUT146_INIT_VAL : string;
attribute C_PROBE_OUT146_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT146_WIDTH : integer;
attribute C_PROBE_OUT146_WIDTH of inst : label is 1;
attribute C_PROBE_OUT147_INIT_VAL : string;
attribute C_PROBE_OUT147_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT147_WIDTH : integer;
attribute C_PROBE_OUT147_WIDTH of inst : label is 1;
attribute C_PROBE_OUT148_INIT_VAL : string;
attribute C_PROBE_OUT148_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT148_WIDTH : integer;
attribute C_PROBE_OUT148_WIDTH of inst : label is 1;
attribute C_PROBE_OUT149_INIT_VAL : string;
attribute C_PROBE_OUT149_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT149_WIDTH : integer;
attribute C_PROBE_OUT149_WIDTH of inst : label is 1;
attribute C_PROBE_OUT14_INIT_VAL : string;
attribute C_PROBE_OUT14_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT14_WIDTH : integer;
attribute C_PROBE_OUT14_WIDTH of inst : label is 1;
attribute C_PROBE_OUT150_INIT_VAL : string;
attribute C_PROBE_OUT150_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT150_WIDTH : integer;
attribute C_PROBE_OUT150_WIDTH of inst : label is 1;
attribute C_PROBE_OUT151_INIT_VAL : string;
attribute C_PROBE_OUT151_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT151_WIDTH : integer;
attribute C_PROBE_OUT151_WIDTH of inst : label is 1;
attribute C_PROBE_OUT152_INIT_VAL : string;
attribute C_PROBE_OUT152_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT152_WIDTH : integer;
attribute C_PROBE_OUT152_WIDTH of inst : label is 1;
attribute C_PROBE_OUT153_INIT_VAL : string;
attribute C_PROBE_OUT153_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT153_WIDTH : integer;
attribute C_PROBE_OUT153_WIDTH of inst : label is 1;
attribute C_PROBE_OUT154_INIT_VAL : string;
attribute C_PROBE_OUT154_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT154_WIDTH : integer;
attribute C_PROBE_OUT154_WIDTH of inst : label is 1;
attribute C_PROBE_OUT155_INIT_VAL : string;
attribute C_PROBE_OUT155_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT155_WIDTH : integer;
attribute C_PROBE_OUT155_WIDTH of inst : label is 1;
attribute C_PROBE_OUT156_INIT_VAL : string;
attribute C_PROBE_OUT156_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT156_WIDTH : integer;
attribute C_PROBE_OUT156_WIDTH of inst : label is 1;
attribute C_PROBE_OUT157_INIT_VAL : string;
attribute C_PROBE_OUT157_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT157_WIDTH : integer;
attribute C_PROBE_OUT157_WIDTH of inst : label is 1;
attribute C_PROBE_OUT158_INIT_VAL : string;
attribute C_PROBE_OUT158_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT158_WIDTH : integer;
attribute C_PROBE_OUT158_WIDTH of inst : label is 1;
attribute C_PROBE_OUT159_INIT_VAL : string;
attribute C_PROBE_OUT159_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT159_WIDTH : integer;
attribute C_PROBE_OUT159_WIDTH of inst : label is 1;
attribute C_PROBE_OUT15_INIT_VAL : string;
attribute C_PROBE_OUT15_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT15_WIDTH : integer;
attribute C_PROBE_OUT15_WIDTH of inst : label is 1;
attribute C_PROBE_OUT160_INIT_VAL : string;
attribute C_PROBE_OUT160_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT160_WIDTH : integer;
attribute C_PROBE_OUT160_WIDTH of inst : label is 1;
attribute C_PROBE_OUT161_INIT_VAL : string;
attribute C_PROBE_OUT161_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT161_WIDTH : integer;
attribute C_PROBE_OUT161_WIDTH of inst : label is 1;
attribute C_PROBE_OUT162_INIT_VAL : string;
attribute C_PROBE_OUT162_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT162_WIDTH : integer;
attribute C_PROBE_OUT162_WIDTH of inst : label is 1;
attribute C_PROBE_OUT163_INIT_VAL : string;
attribute C_PROBE_OUT163_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT163_WIDTH : integer;
attribute C_PROBE_OUT163_WIDTH of inst : label is 1;
attribute C_PROBE_OUT164_INIT_VAL : string;
attribute C_PROBE_OUT164_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT164_WIDTH : integer;
attribute C_PROBE_OUT164_WIDTH of inst : label is 1;
attribute C_PROBE_OUT165_INIT_VAL : string;
attribute C_PROBE_OUT165_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT165_WIDTH : integer;
attribute C_PROBE_OUT165_WIDTH of inst : label is 1;
attribute C_PROBE_OUT166_INIT_VAL : string;
attribute C_PROBE_OUT166_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT166_WIDTH : integer;
attribute C_PROBE_OUT166_WIDTH of inst : label is 1;
attribute C_PROBE_OUT167_INIT_VAL : string;
attribute C_PROBE_OUT167_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT167_WIDTH : integer;
attribute C_PROBE_OUT167_WIDTH of inst : label is 1;
attribute C_PROBE_OUT168_INIT_VAL : string;
attribute C_PROBE_OUT168_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT168_WIDTH : integer;
attribute C_PROBE_OUT168_WIDTH of inst : label is 1;
attribute C_PROBE_OUT169_INIT_VAL : string;
attribute C_PROBE_OUT169_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT169_WIDTH : integer;
attribute C_PROBE_OUT169_WIDTH of inst : label is 1;
attribute C_PROBE_OUT16_INIT_VAL : string;
attribute C_PROBE_OUT16_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT16_WIDTH : integer;
attribute C_PROBE_OUT16_WIDTH of inst : label is 1;
attribute C_PROBE_OUT170_INIT_VAL : string;
attribute C_PROBE_OUT170_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT170_WIDTH : integer;
attribute C_PROBE_OUT170_WIDTH of inst : label is 1;
attribute C_PROBE_OUT171_INIT_VAL : string;
attribute C_PROBE_OUT171_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT171_WIDTH : integer;
attribute C_PROBE_OUT171_WIDTH of inst : label is 1;
attribute C_PROBE_OUT172_INIT_VAL : string;
attribute C_PROBE_OUT172_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT172_WIDTH : integer;
attribute C_PROBE_OUT172_WIDTH of inst : label is 1;
attribute C_PROBE_OUT173_INIT_VAL : string;
attribute C_PROBE_OUT173_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT173_WIDTH : integer;
attribute C_PROBE_OUT173_WIDTH of inst : label is 1;
attribute C_PROBE_OUT174_INIT_VAL : string;
attribute C_PROBE_OUT174_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT174_WIDTH : integer;
attribute C_PROBE_OUT174_WIDTH of inst : label is 1;
attribute C_PROBE_OUT175_INIT_VAL : string;
attribute C_PROBE_OUT175_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT175_WIDTH : integer;
attribute C_PROBE_OUT175_WIDTH of inst : label is 1;
attribute C_PROBE_OUT176_INIT_VAL : string;
attribute C_PROBE_OUT176_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT176_WIDTH : integer;
attribute C_PROBE_OUT176_WIDTH of inst : label is 1;
attribute C_PROBE_OUT177_INIT_VAL : string;
attribute C_PROBE_OUT177_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT177_WIDTH : integer;
attribute C_PROBE_OUT177_WIDTH of inst : label is 1;
attribute C_PROBE_OUT178_INIT_VAL : string;
attribute C_PROBE_OUT178_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT178_WIDTH : integer;
attribute C_PROBE_OUT178_WIDTH of inst : label is 1;
attribute C_PROBE_OUT179_INIT_VAL : string;
attribute C_PROBE_OUT179_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT179_WIDTH : integer;
attribute C_PROBE_OUT179_WIDTH of inst : label is 1;
attribute C_PROBE_OUT17_INIT_VAL : string;
attribute C_PROBE_OUT17_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT17_WIDTH : integer;
attribute C_PROBE_OUT17_WIDTH of inst : label is 1;
attribute C_PROBE_OUT180_INIT_VAL : string;
attribute C_PROBE_OUT180_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT180_WIDTH : integer;
attribute C_PROBE_OUT180_WIDTH of inst : label is 1;
attribute C_PROBE_OUT181_INIT_VAL : string;
attribute C_PROBE_OUT181_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT181_WIDTH : integer;
attribute C_PROBE_OUT181_WIDTH of inst : label is 1;
attribute C_PROBE_OUT182_INIT_VAL : string;
attribute C_PROBE_OUT182_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT182_WIDTH : integer;
attribute C_PROBE_OUT182_WIDTH of inst : label is 1;
attribute C_PROBE_OUT183_INIT_VAL : string;
attribute C_PROBE_OUT183_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT183_WIDTH : integer;
attribute C_PROBE_OUT183_WIDTH of inst : label is 1;
attribute C_PROBE_OUT184_INIT_VAL : string;
attribute C_PROBE_OUT184_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT184_WIDTH : integer;
attribute C_PROBE_OUT184_WIDTH of inst : label is 1;
attribute C_PROBE_OUT185_INIT_VAL : string;
attribute C_PROBE_OUT185_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT185_WIDTH : integer;
attribute C_PROBE_OUT185_WIDTH of inst : label is 1;
attribute C_PROBE_OUT186_INIT_VAL : string;
attribute C_PROBE_OUT186_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT186_WIDTH : integer;
attribute C_PROBE_OUT186_WIDTH of inst : label is 1;
attribute C_PROBE_OUT187_INIT_VAL : string;
attribute C_PROBE_OUT187_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT187_WIDTH : integer;
attribute C_PROBE_OUT187_WIDTH of inst : label is 1;
attribute C_PROBE_OUT188_INIT_VAL : string;
attribute C_PROBE_OUT188_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT188_WIDTH : integer;
attribute C_PROBE_OUT188_WIDTH of inst : label is 1;
attribute C_PROBE_OUT189_INIT_VAL : string;
attribute C_PROBE_OUT189_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT189_WIDTH : integer;
attribute C_PROBE_OUT189_WIDTH of inst : label is 1;
attribute C_PROBE_OUT18_INIT_VAL : string;
attribute C_PROBE_OUT18_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT18_WIDTH : integer;
attribute C_PROBE_OUT18_WIDTH of inst : label is 1;
attribute C_PROBE_OUT190_INIT_VAL : string;
attribute C_PROBE_OUT190_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT190_WIDTH : integer;
attribute C_PROBE_OUT190_WIDTH of inst : label is 1;
attribute C_PROBE_OUT191_INIT_VAL : string;
attribute C_PROBE_OUT191_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT191_WIDTH : integer;
attribute C_PROBE_OUT191_WIDTH of inst : label is 1;
attribute C_PROBE_OUT192_INIT_VAL : string;
attribute C_PROBE_OUT192_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT192_WIDTH : integer;
attribute C_PROBE_OUT192_WIDTH of inst : label is 1;
attribute C_PROBE_OUT193_INIT_VAL : string;
attribute C_PROBE_OUT193_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT193_WIDTH : integer;
attribute C_PROBE_OUT193_WIDTH of inst : label is 1;
attribute C_PROBE_OUT194_INIT_VAL : string;
attribute C_PROBE_OUT194_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT194_WIDTH : integer;
attribute C_PROBE_OUT194_WIDTH of inst : label is 1;
attribute C_PROBE_OUT195_INIT_VAL : string;
attribute C_PROBE_OUT195_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT195_WIDTH : integer;
attribute C_PROBE_OUT195_WIDTH of inst : label is 1;
attribute C_PROBE_OUT196_INIT_VAL : string;
attribute C_PROBE_OUT196_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT196_WIDTH : integer;
attribute C_PROBE_OUT196_WIDTH of inst : label is 1;
attribute C_PROBE_OUT197_INIT_VAL : string;
attribute C_PROBE_OUT197_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT197_WIDTH : integer;
attribute C_PROBE_OUT197_WIDTH of inst : label is 1;
attribute C_PROBE_OUT198_INIT_VAL : string;
attribute C_PROBE_OUT198_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT198_WIDTH : integer;
attribute C_PROBE_OUT198_WIDTH of inst : label is 1;
attribute C_PROBE_OUT199_INIT_VAL : string;
attribute C_PROBE_OUT199_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT199_WIDTH : integer;
attribute C_PROBE_OUT199_WIDTH of inst : label is 1;
attribute C_PROBE_OUT19_INIT_VAL : string;
attribute C_PROBE_OUT19_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT19_WIDTH : integer;
attribute C_PROBE_OUT19_WIDTH of inst : label is 1;
attribute C_PROBE_OUT1_INIT_VAL : string;
attribute C_PROBE_OUT1_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT1_WIDTH : integer;
attribute C_PROBE_OUT1_WIDTH of inst : label is 1;
attribute C_PROBE_OUT200_INIT_VAL : string;
attribute C_PROBE_OUT200_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT200_WIDTH : integer;
attribute C_PROBE_OUT200_WIDTH of inst : label is 1;
attribute C_PROBE_OUT201_INIT_VAL : string;
attribute C_PROBE_OUT201_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT201_WIDTH : integer;
attribute C_PROBE_OUT201_WIDTH of inst : label is 1;
attribute C_PROBE_OUT202_INIT_VAL : string;
attribute C_PROBE_OUT202_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT202_WIDTH : integer;
attribute C_PROBE_OUT202_WIDTH of inst : label is 1;
attribute C_PROBE_OUT203_INIT_VAL : string;
attribute C_PROBE_OUT203_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT203_WIDTH : integer;
attribute C_PROBE_OUT203_WIDTH of inst : label is 1;
attribute C_PROBE_OUT204_INIT_VAL : string;
attribute C_PROBE_OUT204_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT204_WIDTH : integer;
attribute C_PROBE_OUT204_WIDTH of inst : label is 1;
attribute C_PROBE_OUT205_INIT_VAL : string;
attribute C_PROBE_OUT205_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT205_WIDTH : integer;
attribute C_PROBE_OUT205_WIDTH of inst : label is 1;
attribute C_PROBE_OUT206_INIT_VAL : string;
attribute C_PROBE_OUT206_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT206_WIDTH : integer;
attribute C_PROBE_OUT206_WIDTH of inst : label is 1;
attribute C_PROBE_OUT207_INIT_VAL : string;
attribute C_PROBE_OUT207_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT207_WIDTH : integer;
attribute C_PROBE_OUT207_WIDTH of inst : label is 1;
attribute C_PROBE_OUT208_INIT_VAL : string;
attribute C_PROBE_OUT208_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT208_WIDTH : integer;
attribute C_PROBE_OUT208_WIDTH of inst : label is 1;
attribute C_PROBE_OUT209_INIT_VAL : string;
attribute C_PROBE_OUT209_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT209_WIDTH : integer;
attribute C_PROBE_OUT209_WIDTH of inst : label is 1;
attribute C_PROBE_OUT20_INIT_VAL : string;
attribute C_PROBE_OUT20_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT20_WIDTH : integer;
attribute C_PROBE_OUT20_WIDTH of inst : label is 1;
attribute C_PROBE_OUT210_INIT_VAL : string;
attribute C_PROBE_OUT210_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT210_WIDTH : integer;
attribute C_PROBE_OUT210_WIDTH of inst : label is 1;
attribute C_PROBE_OUT211_INIT_VAL : string;
attribute C_PROBE_OUT211_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT211_WIDTH : integer;
attribute C_PROBE_OUT211_WIDTH of inst : label is 1;
attribute C_PROBE_OUT212_INIT_VAL : string;
attribute C_PROBE_OUT212_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT212_WIDTH : integer;
attribute C_PROBE_OUT212_WIDTH of inst : label is 1;
attribute C_PROBE_OUT213_INIT_VAL : string;
attribute C_PROBE_OUT213_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT213_WIDTH : integer;
attribute C_PROBE_OUT213_WIDTH of inst : label is 1;
attribute C_PROBE_OUT214_INIT_VAL : string;
attribute C_PROBE_OUT214_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT214_WIDTH : integer;
attribute C_PROBE_OUT214_WIDTH of inst : label is 1;
attribute C_PROBE_OUT215_INIT_VAL : string;
attribute C_PROBE_OUT215_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT215_WIDTH : integer;
attribute C_PROBE_OUT215_WIDTH of inst : label is 1;
attribute C_PROBE_OUT216_INIT_VAL : string;
attribute C_PROBE_OUT216_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT216_WIDTH : integer;
attribute C_PROBE_OUT216_WIDTH of inst : label is 1;
attribute C_PROBE_OUT217_INIT_VAL : string;
attribute C_PROBE_OUT217_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT217_WIDTH : integer;
attribute C_PROBE_OUT217_WIDTH of inst : label is 1;
attribute C_PROBE_OUT218_INIT_VAL : string;
attribute C_PROBE_OUT218_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT218_WIDTH : integer;
attribute C_PROBE_OUT218_WIDTH of inst : label is 1;
attribute C_PROBE_OUT219_INIT_VAL : string;
attribute C_PROBE_OUT219_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT219_WIDTH : integer;
attribute C_PROBE_OUT219_WIDTH of inst : label is 1;
attribute C_PROBE_OUT21_INIT_VAL : string;
attribute C_PROBE_OUT21_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT21_WIDTH : integer;
attribute C_PROBE_OUT21_WIDTH of inst : label is 1;
attribute C_PROBE_OUT220_INIT_VAL : string;
attribute C_PROBE_OUT220_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT220_WIDTH : integer;
attribute C_PROBE_OUT220_WIDTH of inst : label is 1;
attribute C_PROBE_OUT221_INIT_VAL : string;
attribute C_PROBE_OUT221_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT221_WIDTH : integer;
attribute C_PROBE_OUT221_WIDTH of inst : label is 1;
attribute C_PROBE_OUT222_INIT_VAL : string;
attribute C_PROBE_OUT222_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT222_WIDTH : integer;
attribute C_PROBE_OUT222_WIDTH of inst : label is 1;
attribute C_PROBE_OUT223_INIT_VAL : string;
attribute C_PROBE_OUT223_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT223_WIDTH : integer;
attribute C_PROBE_OUT223_WIDTH of inst : label is 1;
attribute C_PROBE_OUT224_INIT_VAL : string;
attribute C_PROBE_OUT224_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT224_WIDTH : integer;
attribute C_PROBE_OUT224_WIDTH of inst : label is 1;
attribute C_PROBE_OUT225_INIT_VAL : string;
attribute C_PROBE_OUT225_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT225_WIDTH : integer;
attribute C_PROBE_OUT225_WIDTH of inst : label is 1;
attribute C_PROBE_OUT226_INIT_VAL : string;
attribute C_PROBE_OUT226_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT226_WIDTH : integer;
attribute C_PROBE_OUT226_WIDTH of inst : label is 1;
attribute C_PROBE_OUT227_INIT_VAL : string;
attribute C_PROBE_OUT227_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT227_WIDTH : integer;
attribute C_PROBE_OUT227_WIDTH of inst : label is 1;
attribute C_PROBE_OUT228_INIT_VAL : string;
attribute C_PROBE_OUT228_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT228_WIDTH : integer;
attribute C_PROBE_OUT228_WIDTH of inst : label is 1;
attribute C_PROBE_OUT229_INIT_VAL : string;
attribute C_PROBE_OUT229_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT229_WIDTH : integer;
attribute C_PROBE_OUT229_WIDTH of inst : label is 1;
attribute C_PROBE_OUT22_INIT_VAL : string;
attribute C_PROBE_OUT22_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT22_WIDTH : integer;
attribute C_PROBE_OUT22_WIDTH of inst : label is 1;
attribute C_PROBE_OUT230_INIT_VAL : string;
attribute C_PROBE_OUT230_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT230_WIDTH : integer;
attribute C_PROBE_OUT230_WIDTH of inst : label is 1;
attribute C_PROBE_OUT231_INIT_VAL : string;
attribute C_PROBE_OUT231_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT231_WIDTH : integer;
attribute C_PROBE_OUT231_WIDTH of inst : label is 1;
attribute C_PROBE_OUT232_INIT_VAL : string;
attribute C_PROBE_OUT232_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT232_WIDTH : integer;
attribute C_PROBE_OUT232_WIDTH of inst : label is 1;
attribute C_PROBE_OUT233_INIT_VAL : string;
attribute C_PROBE_OUT233_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT233_WIDTH : integer;
attribute C_PROBE_OUT233_WIDTH of inst : label is 1;
attribute C_PROBE_OUT234_INIT_VAL : string;
attribute C_PROBE_OUT234_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT234_WIDTH : integer;
attribute C_PROBE_OUT234_WIDTH of inst : label is 1;
attribute C_PROBE_OUT235_INIT_VAL : string;
attribute C_PROBE_OUT235_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT235_WIDTH : integer;
attribute C_PROBE_OUT235_WIDTH of inst : label is 1;
attribute C_PROBE_OUT236_INIT_VAL : string;
attribute C_PROBE_OUT236_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT236_WIDTH : integer;
attribute C_PROBE_OUT236_WIDTH of inst : label is 1;
attribute C_PROBE_OUT237_INIT_VAL : string;
attribute C_PROBE_OUT237_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT237_WIDTH : integer;
attribute C_PROBE_OUT237_WIDTH of inst : label is 1;
attribute C_PROBE_OUT238_INIT_VAL : string;
attribute C_PROBE_OUT238_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT238_WIDTH : integer;
attribute C_PROBE_OUT238_WIDTH of inst : label is 1;
attribute C_PROBE_OUT239_INIT_VAL : string;
attribute C_PROBE_OUT239_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT239_WIDTH : integer;
attribute C_PROBE_OUT239_WIDTH of inst : label is 1;
attribute C_PROBE_OUT23_INIT_VAL : string;
attribute C_PROBE_OUT23_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT23_WIDTH : integer;
attribute C_PROBE_OUT23_WIDTH of inst : label is 1;
attribute C_PROBE_OUT240_INIT_VAL : string;
attribute C_PROBE_OUT240_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT240_WIDTH : integer;
attribute C_PROBE_OUT240_WIDTH of inst : label is 1;
attribute C_PROBE_OUT241_INIT_VAL : string;
attribute C_PROBE_OUT241_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT241_WIDTH : integer;
attribute C_PROBE_OUT241_WIDTH of inst : label is 1;
attribute C_PROBE_OUT242_INIT_VAL : string;
attribute C_PROBE_OUT242_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT242_WIDTH : integer;
attribute C_PROBE_OUT242_WIDTH of inst : label is 1;
attribute C_PROBE_OUT243_INIT_VAL : string;
attribute C_PROBE_OUT243_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT243_WIDTH : integer;
attribute C_PROBE_OUT243_WIDTH of inst : label is 1;
attribute C_PROBE_OUT244_INIT_VAL : string;
attribute C_PROBE_OUT244_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT244_WIDTH : integer;
attribute C_PROBE_OUT244_WIDTH of inst : label is 1;
attribute C_PROBE_OUT245_INIT_VAL : string;
attribute C_PROBE_OUT245_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT245_WIDTH : integer;
attribute C_PROBE_OUT245_WIDTH of inst : label is 1;
attribute C_PROBE_OUT246_INIT_VAL : string;
attribute C_PROBE_OUT246_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT246_WIDTH : integer;
attribute C_PROBE_OUT246_WIDTH of inst : label is 1;
attribute C_PROBE_OUT247_INIT_VAL : string;
attribute C_PROBE_OUT247_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT247_WIDTH : integer;
attribute C_PROBE_OUT247_WIDTH of inst : label is 1;
attribute C_PROBE_OUT248_INIT_VAL : string;
attribute C_PROBE_OUT248_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT248_WIDTH : integer;
attribute C_PROBE_OUT248_WIDTH of inst : label is 1;
attribute C_PROBE_OUT249_INIT_VAL : string;
attribute C_PROBE_OUT249_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT249_WIDTH : integer;
attribute C_PROBE_OUT249_WIDTH of inst : label is 1;
attribute C_PROBE_OUT24_INIT_VAL : string;
attribute C_PROBE_OUT24_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT24_WIDTH : integer;
attribute C_PROBE_OUT24_WIDTH of inst : label is 1;
attribute C_PROBE_OUT250_INIT_VAL : string;
attribute C_PROBE_OUT250_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT250_WIDTH : integer;
attribute C_PROBE_OUT250_WIDTH of inst : label is 1;
attribute C_PROBE_OUT251_INIT_VAL : string;
attribute C_PROBE_OUT251_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT251_WIDTH : integer;
attribute C_PROBE_OUT251_WIDTH of inst : label is 1;
attribute C_PROBE_OUT252_INIT_VAL : string;
attribute C_PROBE_OUT252_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT252_WIDTH : integer;
attribute C_PROBE_OUT252_WIDTH of inst : label is 1;
attribute C_PROBE_OUT253_INIT_VAL : string;
attribute C_PROBE_OUT253_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT253_WIDTH : integer;
attribute C_PROBE_OUT253_WIDTH of inst : label is 1;
attribute C_PROBE_OUT254_INIT_VAL : string;
attribute C_PROBE_OUT254_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT254_WIDTH : integer;
attribute C_PROBE_OUT254_WIDTH of inst : label is 1;
attribute C_PROBE_OUT255_INIT_VAL : string;
attribute C_PROBE_OUT255_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT255_WIDTH : integer;
attribute C_PROBE_OUT255_WIDTH of inst : label is 1;
attribute C_PROBE_OUT25_INIT_VAL : string;
attribute C_PROBE_OUT25_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT25_WIDTH : integer;
attribute C_PROBE_OUT25_WIDTH of inst : label is 1;
attribute C_PROBE_OUT26_INIT_VAL : string;
attribute C_PROBE_OUT26_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT26_WIDTH : integer;
attribute C_PROBE_OUT26_WIDTH of inst : label is 1;
attribute C_PROBE_OUT27_INIT_VAL : string;
attribute C_PROBE_OUT27_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT27_WIDTH : integer;
attribute C_PROBE_OUT27_WIDTH of inst : label is 1;
attribute C_PROBE_OUT28_INIT_VAL : string;
attribute C_PROBE_OUT28_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT28_WIDTH : integer;
attribute C_PROBE_OUT28_WIDTH of inst : label is 1;
attribute C_PROBE_OUT29_INIT_VAL : string;
attribute C_PROBE_OUT29_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT29_WIDTH : integer;
attribute C_PROBE_OUT29_WIDTH of inst : label is 1;
attribute C_PROBE_OUT2_INIT_VAL : string;
attribute C_PROBE_OUT2_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT2_WIDTH : integer;
attribute C_PROBE_OUT2_WIDTH of inst : label is 1;
attribute C_PROBE_OUT30_INIT_VAL : string;
attribute C_PROBE_OUT30_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT30_WIDTH : integer;
attribute C_PROBE_OUT30_WIDTH of inst : label is 1;
attribute C_PROBE_OUT31_INIT_VAL : string;
attribute C_PROBE_OUT31_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT31_WIDTH : integer;
attribute C_PROBE_OUT31_WIDTH of inst : label is 1;
attribute C_PROBE_OUT32_INIT_VAL : string;
attribute C_PROBE_OUT32_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT32_WIDTH : integer;
attribute C_PROBE_OUT32_WIDTH of inst : label is 1;
attribute C_PROBE_OUT33_INIT_VAL : string;
attribute C_PROBE_OUT33_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT33_WIDTH : integer;
attribute C_PROBE_OUT33_WIDTH of inst : label is 1;
attribute C_PROBE_OUT34_INIT_VAL : string;
attribute C_PROBE_OUT34_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT34_WIDTH : integer;
attribute C_PROBE_OUT34_WIDTH of inst : label is 1;
attribute C_PROBE_OUT35_INIT_VAL : string;
attribute C_PROBE_OUT35_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT35_WIDTH : integer;
attribute C_PROBE_OUT35_WIDTH of inst : label is 1;
attribute C_PROBE_OUT36_INIT_VAL : string;
attribute C_PROBE_OUT36_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT36_WIDTH : integer;
attribute C_PROBE_OUT36_WIDTH of inst : label is 1;
attribute C_PROBE_OUT37_INIT_VAL : string;
attribute C_PROBE_OUT37_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT37_WIDTH : integer;
attribute C_PROBE_OUT37_WIDTH of inst : label is 1;
attribute C_PROBE_OUT38_INIT_VAL : string;
attribute C_PROBE_OUT38_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT38_WIDTH : integer;
attribute C_PROBE_OUT38_WIDTH of inst : label is 1;
attribute C_PROBE_OUT39_INIT_VAL : string;
attribute C_PROBE_OUT39_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT39_WIDTH : integer;
attribute C_PROBE_OUT39_WIDTH of inst : label is 1;
attribute C_PROBE_OUT3_INIT_VAL : string;
attribute C_PROBE_OUT3_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT3_WIDTH : integer;
attribute C_PROBE_OUT3_WIDTH of inst : label is 1;
attribute C_PROBE_OUT40_INIT_VAL : string;
attribute C_PROBE_OUT40_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT40_WIDTH : integer;
attribute C_PROBE_OUT40_WIDTH of inst : label is 1;
attribute C_PROBE_OUT41_INIT_VAL : string;
attribute C_PROBE_OUT41_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT41_WIDTH : integer;
attribute C_PROBE_OUT41_WIDTH of inst : label is 1;
attribute C_PROBE_OUT42_INIT_VAL : string;
attribute C_PROBE_OUT42_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT42_WIDTH : integer;
attribute C_PROBE_OUT42_WIDTH of inst : label is 1;
attribute C_PROBE_OUT43_INIT_VAL : string;
attribute C_PROBE_OUT43_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT43_WIDTH : integer;
attribute C_PROBE_OUT43_WIDTH of inst : label is 1;
attribute C_PROBE_OUT44_INIT_VAL : string;
attribute C_PROBE_OUT44_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT44_WIDTH : integer;
attribute C_PROBE_OUT44_WIDTH of inst : label is 1;
attribute C_PROBE_OUT45_INIT_VAL : string;
attribute C_PROBE_OUT45_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT45_WIDTH : integer;
attribute C_PROBE_OUT45_WIDTH of inst : label is 1;
attribute C_PROBE_OUT46_INIT_VAL : string;
attribute C_PROBE_OUT46_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT46_WIDTH : integer;
attribute C_PROBE_OUT46_WIDTH of inst : label is 1;
attribute C_PROBE_OUT47_INIT_VAL : string;
attribute C_PROBE_OUT47_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT47_WIDTH : integer;
attribute C_PROBE_OUT47_WIDTH of inst : label is 1;
attribute C_PROBE_OUT48_INIT_VAL : string;
attribute C_PROBE_OUT48_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT48_WIDTH : integer;
attribute C_PROBE_OUT48_WIDTH of inst : label is 1;
attribute C_PROBE_OUT49_INIT_VAL : string;
attribute C_PROBE_OUT49_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT49_WIDTH : integer;
attribute C_PROBE_OUT49_WIDTH of inst : label is 1;
attribute C_PROBE_OUT4_INIT_VAL : string;
attribute C_PROBE_OUT4_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT4_WIDTH : integer;
attribute C_PROBE_OUT4_WIDTH of inst : label is 1;
attribute C_PROBE_OUT50_INIT_VAL : string;
attribute C_PROBE_OUT50_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT50_WIDTH : integer;
attribute C_PROBE_OUT50_WIDTH of inst : label is 1;
attribute C_PROBE_OUT51_INIT_VAL : string;
attribute C_PROBE_OUT51_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT51_WIDTH : integer;
attribute C_PROBE_OUT51_WIDTH of inst : label is 1;
attribute C_PROBE_OUT52_INIT_VAL : string;
attribute C_PROBE_OUT52_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT52_WIDTH : integer;
attribute C_PROBE_OUT52_WIDTH of inst : label is 1;
attribute C_PROBE_OUT53_INIT_VAL : string;
attribute C_PROBE_OUT53_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT53_WIDTH : integer;
attribute C_PROBE_OUT53_WIDTH of inst : label is 1;
attribute C_PROBE_OUT54_INIT_VAL : string;
attribute C_PROBE_OUT54_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT54_WIDTH : integer;
attribute C_PROBE_OUT54_WIDTH of inst : label is 1;
attribute C_PROBE_OUT55_INIT_VAL : string;
attribute C_PROBE_OUT55_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT55_WIDTH : integer;
attribute C_PROBE_OUT55_WIDTH of inst : label is 1;
attribute C_PROBE_OUT56_INIT_VAL : string;
attribute C_PROBE_OUT56_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT56_WIDTH : integer;
attribute C_PROBE_OUT56_WIDTH of inst : label is 1;
attribute C_PROBE_OUT57_INIT_VAL : string;
attribute C_PROBE_OUT57_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT57_WIDTH : integer;
attribute C_PROBE_OUT57_WIDTH of inst : label is 1;
attribute C_PROBE_OUT58_INIT_VAL : string;
attribute C_PROBE_OUT58_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT58_WIDTH : integer;
attribute C_PROBE_OUT58_WIDTH of inst : label is 1;
attribute C_PROBE_OUT59_INIT_VAL : string;
attribute C_PROBE_OUT59_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT59_WIDTH : integer;
attribute C_PROBE_OUT59_WIDTH of inst : label is 1;
attribute C_PROBE_OUT5_INIT_VAL : string;
attribute C_PROBE_OUT5_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT5_WIDTH : integer;
attribute C_PROBE_OUT5_WIDTH of inst : label is 1;
attribute C_PROBE_OUT60_INIT_VAL : string;
attribute C_PROBE_OUT60_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT60_WIDTH : integer;
attribute C_PROBE_OUT60_WIDTH of inst : label is 1;
attribute C_PROBE_OUT61_INIT_VAL : string;
attribute C_PROBE_OUT61_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT61_WIDTH : integer;
attribute C_PROBE_OUT61_WIDTH of inst : label is 1;
attribute C_PROBE_OUT62_INIT_VAL : string;
attribute C_PROBE_OUT62_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT62_WIDTH : integer;
attribute C_PROBE_OUT62_WIDTH of inst : label is 1;
attribute C_PROBE_OUT63_INIT_VAL : string;
attribute C_PROBE_OUT63_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT63_WIDTH : integer;
attribute C_PROBE_OUT63_WIDTH of inst : label is 1;
attribute C_PROBE_OUT64_INIT_VAL : string;
attribute C_PROBE_OUT64_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT64_WIDTH : integer;
attribute C_PROBE_OUT64_WIDTH of inst : label is 1;
attribute C_PROBE_OUT65_INIT_VAL : string;
attribute C_PROBE_OUT65_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT65_WIDTH : integer;
attribute C_PROBE_OUT65_WIDTH of inst : label is 1;
attribute C_PROBE_OUT66_INIT_VAL : string;
attribute C_PROBE_OUT66_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT66_WIDTH : integer;
attribute C_PROBE_OUT66_WIDTH of inst : label is 1;
attribute C_PROBE_OUT67_INIT_VAL : string;
attribute C_PROBE_OUT67_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT67_WIDTH : integer;
attribute C_PROBE_OUT67_WIDTH of inst : label is 1;
attribute C_PROBE_OUT68_INIT_VAL : string;
attribute C_PROBE_OUT68_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT68_WIDTH : integer;
attribute C_PROBE_OUT68_WIDTH of inst : label is 1;
attribute C_PROBE_OUT69_INIT_VAL : string;
attribute C_PROBE_OUT69_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT69_WIDTH : integer;
attribute C_PROBE_OUT69_WIDTH of inst : label is 1;
attribute C_PROBE_OUT6_INIT_VAL : string;
attribute C_PROBE_OUT6_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT6_WIDTH : integer;
attribute C_PROBE_OUT6_WIDTH of inst : label is 1;
attribute C_PROBE_OUT70_INIT_VAL : string;
attribute C_PROBE_OUT70_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT70_WIDTH : integer;
attribute C_PROBE_OUT70_WIDTH of inst : label is 1;
attribute C_PROBE_OUT71_INIT_VAL : string;
attribute C_PROBE_OUT71_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT71_WIDTH : integer;
attribute C_PROBE_OUT71_WIDTH of inst : label is 1;
attribute C_PROBE_OUT72_INIT_VAL : string;
attribute C_PROBE_OUT72_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT72_WIDTH : integer;
attribute C_PROBE_OUT72_WIDTH of inst : label is 1;
attribute C_PROBE_OUT73_INIT_VAL : string;
attribute C_PROBE_OUT73_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT73_WIDTH : integer;
attribute C_PROBE_OUT73_WIDTH of inst : label is 1;
attribute C_PROBE_OUT74_INIT_VAL : string;
attribute C_PROBE_OUT74_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT74_WIDTH : integer;
attribute C_PROBE_OUT74_WIDTH of inst : label is 1;
attribute C_PROBE_OUT75_INIT_VAL : string;
attribute C_PROBE_OUT75_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT75_WIDTH : integer;
attribute C_PROBE_OUT75_WIDTH of inst : label is 1;
attribute C_PROBE_OUT76_INIT_VAL : string;
attribute C_PROBE_OUT76_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT76_WIDTH : integer;
attribute C_PROBE_OUT76_WIDTH of inst : label is 1;
attribute C_PROBE_OUT77_INIT_VAL : string;
attribute C_PROBE_OUT77_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT77_WIDTH : integer;
attribute C_PROBE_OUT77_WIDTH of inst : label is 1;
attribute C_PROBE_OUT78_INIT_VAL : string;
attribute C_PROBE_OUT78_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT78_WIDTH : integer;
attribute C_PROBE_OUT78_WIDTH of inst : label is 1;
attribute C_PROBE_OUT79_INIT_VAL : string;
attribute C_PROBE_OUT79_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT79_WIDTH : integer;
attribute C_PROBE_OUT79_WIDTH of inst : label is 1;
attribute C_PROBE_OUT7_INIT_VAL : string;
attribute C_PROBE_OUT7_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT7_WIDTH : integer;
attribute C_PROBE_OUT7_WIDTH of inst : label is 1;
attribute C_PROBE_OUT80_INIT_VAL : string;
attribute C_PROBE_OUT80_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT80_WIDTH : integer;
attribute C_PROBE_OUT80_WIDTH of inst : label is 1;
attribute C_PROBE_OUT81_INIT_VAL : string;
attribute C_PROBE_OUT81_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT81_WIDTH : integer;
attribute C_PROBE_OUT81_WIDTH of inst : label is 1;
attribute C_PROBE_OUT82_INIT_VAL : string;
attribute C_PROBE_OUT82_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT82_WIDTH : integer;
attribute C_PROBE_OUT82_WIDTH of inst : label is 1;
attribute C_PROBE_OUT83_INIT_VAL : string;
attribute C_PROBE_OUT83_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT83_WIDTH : integer;
attribute C_PROBE_OUT83_WIDTH of inst : label is 1;
attribute C_PROBE_OUT84_INIT_VAL : string;
attribute C_PROBE_OUT84_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT84_WIDTH : integer;
attribute C_PROBE_OUT84_WIDTH of inst : label is 1;
attribute C_PROBE_OUT85_INIT_VAL : string;
attribute C_PROBE_OUT85_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT85_WIDTH : integer;
attribute C_PROBE_OUT85_WIDTH of inst : label is 1;
attribute C_PROBE_OUT86_INIT_VAL : string;
attribute C_PROBE_OUT86_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT86_WIDTH : integer;
attribute C_PROBE_OUT86_WIDTH of inst : label is 1;
attribute C_PROBE_OUT87_INIT_VAL : string;
attribute C_PROBE_OUT87_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT87_WIDTH : integer;
attribute C_PROBE_OUT87_WIDTH of inst : label is 1;
attribute C_PROBE_OUT88_INIT_VAL : string;
attribute C_PROBE_OUT88_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT88_WIDTH : integer;
attribute C_PROBE_OUT88_WIDTH of inst : label is 1;
attribute C_PROBE_OUT89_INIT_VAL : string;
attribute C_PROBE_OUT89_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT89_WIDTH : integer;
attribute C_PROBE_OUT89_WIDTH of inst : label is 1;
attribute C_PROBE_OUT8_INIT_VAL : string;
attribute C_PROBE_OUT8_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT8_WIDTH : integer;
attribute C_PROBE_OUT8_WIDTH of inst : label is 1;
attribute C_PROBE_OUT90_INIT_VAL : string;
attribute C_PROBE_OUT90_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT90_WIDTH : integer;
attribute C_PROBE_OUT90_WIDTH of inst : label is 1;
attribute C_PROBE_OUT91_INIT_VAL : string;
attribute C_PROBE_OUT91_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT91_WIDTH : integer;
attribute C_PROBE_OUT91_WIDTH of inst : label is 1;
attribute C_PROBE_OUT92_INIT_VAL : string;
attribute C_PROBE_OUT92_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT92_WIDTH : integer;
attribute C_PROBE_OUT92_WIDTH of inst : label is 1;
attribute C_PROBE_OUT93_INIT_VAL : string;
attribute C_PROBE_OUT93_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT93_WIDTH : integer;
attribute C_PROBE_OUT93_WIDTH of inst : label is 1;
attribute C_PROBE_OUT94_INIT_VAL : string;
attribute C_PROBE_OUT94_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT94_WIDTH : integer;
attribute C_PROBE_OUT94_WIDTH of inst : label is 1;
attribute C_PROBE_OUT95_INIT_VAL : string;
attribute C_PROBE_OUT95_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT95_WIDTH : integer;
attribute C_PROBE_OUT95_WIDTH of inst : label is 1;
attribute C_PROBE_OUT96_INIT_VAL : string;
attribute C_PROBE_OUT96_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT96_WIDTH : integer;
attribute C_PROBE_OUT96_WIDTH of inst : label is 1;
attribute C_PROBE_OUT97_INIT_VAL : string;
attribute C_PROBE_OUT97_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT97_WIDTH : integer;
attribute C_PROBE_OUT97_WIDTH of inst : label is 1;
attribute C_PROBE_OUT98_INIT_VAL : string;
attribute C_PROBE_OUT98_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT98_WIDTH : integer;
attribute C_PROBE_OUT98_WIDTH of inst : label is 1;
attribute C_PROBE_OUT99_INIT_VAL : string;
attribute C_PROBE_OUT99_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT99_WIDTH : integer;
attribute C_PROBE_OUT99_WIDTH of inst : label is 1;
attribute C_PROBE_OUT9_INIT_VAL : string;
attribute C_PROBE_OUT9_INIT_VAL of inst : label is "1'b0";
attribute C_PROBE_OUT9_WIDTH : integer;
attribute C_PROBE_OUT9_WIDTH of inst : label is 1;
attribute C_USE_TEST_REG : integer;
attribute C_USE_TEST_REG of inst : label is 1;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of inst : label is "kintex7";
attribute C_XLNX_HW_PROBE_INFO : string;
attribute C_XLNX_HW_PROBE_INFO of inst : label is "DEFAULT";
attribute C_XSDB_SLAVE_TYPE : integer;
attribute C_XSDB_SLAVE_TYPE of inst : label is 33;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of inst : label is std.standard.true;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute LC_HIGH_BIT_POS_PROBE_OUT0 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT1 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT10 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT100 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT101 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT102 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT103 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT104 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT105 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT106 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT107 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT108 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT109 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT11 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT110 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT111 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT112 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT113 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT114 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT115 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT116 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT117 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT118 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT119 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT12 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT120 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT121 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT122 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT123 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT124 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT125 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT126 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT127 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT128 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT129 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT13 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT130 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT131 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT132 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT133 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT134 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT135 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT136 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT137 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT138 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT139 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT14 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT140 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT141 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT142 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT143 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT144 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT145 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT146 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT147 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT148 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT149 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT15 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT150 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT151 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT152 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT153 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT154 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT155 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT156 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT157 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT158 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT159 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT16 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT160 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT161 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT162 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT163 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT164 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT165 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT166 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT167 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT168 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT169 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT17 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT170 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT171 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT172 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT173 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT174 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT175 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT176 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT177 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT178 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT179 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT18 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT180 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT181 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT182 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT183 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT184 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT185 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT186 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT187 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT188 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT189 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT19 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT190 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT191 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT192 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT193 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT194 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT195 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT196 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT197 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT198 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT199 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT2 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT20 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT200 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT201 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT202 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT203 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT204 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT205 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT206 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT207 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT208 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT209 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT21 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT210 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT211 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT212 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT213 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT214 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT215 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT216 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT217 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT218 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT219 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT22 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT220 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT221 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT222 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT223 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT224 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT225 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT226 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT227 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT228 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT229 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT23 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT230 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT231 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT232 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT233 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT234 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT235 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT236 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT237 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT238 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT239 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT24 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT240 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT241 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT242 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT243 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT244 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT245 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT246 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT247 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT248 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT249 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT25 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT250 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT251 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT252 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT253 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT254 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT255 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT26 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT27 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT28 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT29 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT3 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT30 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT31 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT32 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT33 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT34 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT35 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_HIGH_BIT_POS_PROBE_OUT36 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_HIGH_BIT_POS_PROBE_OUT37 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_HIGH_BIT_POS_PROBE_OUT38 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_HIGH_BIT_POS_PROBE_OUT39 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_HIGH_BIT_POS_PROBE_OUT4 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT40 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_HIGH_BIT_POS_PROBE_OUT41 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_HIGH_BIT_POS_PROBE_OUT42 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_HIGH_BIT_POS_PROBE_OUT43 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_HIGH_BIT_POS_PROBE_OUT44 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_HIGH_BIT_POS_PROBE_OUT45 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_HIGH_BIT_POS_PROBE_OUT46 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_HIGH_BIT_POS_PROBE_OUT47 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_HIGH_BIT_POS_PROBE_OUT48 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_HIGH_BIT_POS_PROBE_OUT49 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_HIGH_BIT_POS_PROBE_OUT5 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT50 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_HIGH_BIT_POS_PROBE_OUT51 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_HIGH_BIT_POS_PROBE_OUT52 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_HIGH_BIT_POS_PROBE_OUT53 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_HIGH_BIT_POS_PROBE_OUT54 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_HIGH_BIT_POS_PROBE_OUT55 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_HIGH_BIT_POS_PROBE_OUT56 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_HIGH_BIT_POS_PROBE_OUT57 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_HIGH_BIT_POS_PROBE_OUT58 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_HIGH_BIT_POS_PROBE_OUT59 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_HIGH_BIT_POS_PROBE_OUT6 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT60 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_HIGH_BIT_POS_PROBE_OUT61 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_HIGH_BIT_POS_PROBE_OUT62 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_HIGH_BIT_POS_PROBE_OUT63 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_HIGH_BIT_POS_PROBE_OUT64 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_HIGH_BIT_POS_PROBE_OUT65 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_HIGH_BIT_POS_PROBE_OUT66 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_HIGH_BIT_POS_PROBE_OUT67 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_HIGH_BIT_POS_PROBE_OUT68 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_HIGH_BIT_POS_PROBE_OUT69 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_HIGH_BIT_POS_PROBE_OUT7 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT70 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_HIGH_BIT_POS_PROBE_OUT71 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_HIGH_BIT_POS_PROBE_OUT72 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT73 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT74 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_HIGH_BIT_POS_PROBE_OUT75 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_HIGH_BIT_POS_PROBE_OUT76 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_HIGH_BIT_POS_PROBE_OUT77 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_HIGH_BIT_POS_PROBE_OUT78 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_HIGH_BIT_POS_PROBE_OUT79 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_HIGH_BIT_POS_PROBE_OUT8 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_HIGH_BIT_POS_PROBE_OUT80 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_HIGH_BIT_POS_PROBE_OUT81 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_HIGH_BIT_POS_PROBE_OUT82 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_HIGH_BIT_POS_PROBE_OUT83 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_HIGH_BIT_POS_PROBE_OUT84 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_HIGH_BIT_POS_PROBE_OUT85 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_HIGH_BIT_POS_PROBE_OUT86 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_HIGH_BIT_POS_PROBE_OUT87 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_HIGH_BIT_POS_PROBE_OUT88 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_HIGH_BIT_POS_PROBE_OUT89 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_HIGH_BIT_POS_PROBE_OUT9 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_HIGH_BIT_POS_PROBE_OUT90 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_HIGH_BIT_POS_PROBE_OUT91 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_HIGH_BIT_POS_PROBE_OUT92 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_HIGH_BIT_POS_PROBE_OUT93 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_HIGH_BIT_POS_PROBE_OUT94 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_HIGH_BIT_POS_PROBE_OUT95 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_HIGH_BIT_POS_PROBE_OUT96 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_HIGH_BIT_POS_PROBE_OUT97 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_HIGH_BIT_POS_PROBE_OUT98 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_HIGH_BIT_POS_PROBE_OUT99 : string;
attribute LC_HIGH_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_LOW_BIT_POS_PROBE_OUT0 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT0 of inst : label is "16'b0000000000000000";
attribute LC_LOW_BIT_POS_PROBE_OUT1 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT1 of inst : label is "16'b0000000000000001";
attribute LC_LOW_BIT_POS_PROBE_OUT10 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT10 of inst : label is "16'b0000000000001010";
attribute LC_LOW_BIT_POS_PROBE_OUT100 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT100 of inst : label is "16'b0000000001100100";
attribute LC_LOW_BIT_POS_PROBE_OUT101 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT101 of inst : label is "16'b0000000001100101";
attribute LC_LOW_BIT_POS_PROBE_OUT102 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT102 of inst : label is "16'b0000000001100110";
attribute LC_LOW_BIT_POS_PROBE_OUT103 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT103 of inst : label is "16'b0000000001100111";
attribute LC_LOW_BIT_POS_PROBE_OUT104 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT104 of inst : label is "16'b0000000001101000";
attribute LC_LOW_BIT_POS_PROBE_OUT105 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT105 of inst : label is "16'b0000000001101001";
attribute LC_LOW_BIT_POS_PROBE_OUT106 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT106 of inst : label is "16'b0000000001101010";
attribute LC_LOW_BIT_POS_PROBE_OUT107 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT107 of inst : label is "16'b0000000001101011";
attribute LC_LOW_BIT_POS_PROBE_OUT108 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT108 of inst : label is "16'b0000000001101100";
attribute LC_LOW_BIT_POS_PROBE_OUT109 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT109 of inst : label is "16'b0000000001101101";
attribute LC_LOW_BIT_POS_PROBE_OUT11 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT11 of inst : label is "16'b0000000000001011";
attribute LC_LOW_BIT_POS_PROBE_OUT110 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT110 of inst : label is "16'b0000000001101110";
attribute LC_LOW_BIT_POS_PROBE_OUT111 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT111 of inst : label is "16'b0000000001101111";
attribute LC_LOW_BIT_POS_PROBE_OUT112 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT112 of inst : label is "16'b0000000001110000";
attribute LC_LOW_BIT_POS_PROBE_OUT113 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT113 of inst : label is "16'b0000000001110001";
attribute LC_LOW_BIT_POS_PROBE_OUT114 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT114 of inst : label is "16'b0000000001110010";
attribute LC_LOW_BIT_POS_PROBE_OUT115 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT115 of inst : label is "16'b0000000001110011";
attribute LC_LOW_BIT_POS_PROBE_OUT116 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT116 of inst : label is "16'b0000000001110100";
attribute LC_LOW_BIT_POS_PROBE_OUT117 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT117 of inst : label is "16'b0000000001110101";
attribute LC_LOW_BIT_POS_PROBE_OUT118 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT118 of inst : label is "16'b0000000001110110";
attribute LC_LOW_BIT_POS_PROBE_OUT119 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT119 of inst : label is "16'b0000000001110111";
attribute LC_LOW_BIT_POS_PROBE_OUT12 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT12 of inst : label is "16'b0000000000001100";
attribute LC_LOW_BIT_POS_PROBE_OUT120 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT120 of inst : label is "16'b0000000001111000";
attribute LC_LOW_BIT_POS_PROBE_OUT121 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT121 of inst : label is "16'b0000000001111001";
attribute LC_LOW_BIT_POS_PROBE_OUT122 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT122 of inst : label is "16'b0000000001111010";
attribute LC_LOW_BIT_POS_PROBE_OUT123 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT123 of inst : label is "16'b0000000001111011";
attribute LC_LOW_BIT_POS_PROBE_OUT124 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT124 of inst : label is "16'b0000000001111100";
attribute LC_LOW_BIT_POS_PROBE_OUT125 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT125 of inst : label is "16'b0000000001111101";
attribute LC_LOW_BIT_POS_PROBE_OUT126 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT126 of inst : label is "16'b0000000001111110";
attribute LC_LOW_BIT_POS_PROBE_OUT127 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT127 of inst : label is "16'b0000000001111111";
attribute LC_LOW_BIT_POS_PROBE_OUT128 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT128 of inst : label is "16'b0000000010000000";
attribute LC_LOW_BIT_POS_PROBE_OUT129 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT129 of inst : label is "16'b0000000010000001";
attribute LC_LOW_BIT_POS_PROBE_OUT13 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT13 of inst : label is "16'b0000000000001101";
attribute LC_LOW_BIT_POS_PROBE_OUT130 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT130 of inst : label is "16'b0000000010000010";
attribute LC_LOW_BIT_POS_PROBE_OUT131 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT131 of inst : label is "16'b0000000010000011";
attribute LC_LOW_BIT_POS_PROBE_OUT132 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT132 of inst : label is "16'b0000000010000100";
attribute LC_LOW_BIT_POS_PROBE_OUT133 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT133 of inst : label is "16'b0000000010000101";
attribute LC_LOW_BIT_POS_PROBE_OUT134 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT134 of inst : label is "16'b0000000010000110";
attribute LC_LOW_BIT_POS_PROBE_OUT135 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT135 of inst : label is "16'b0000000010000111";
attribute LC_LOW_BIT_POS_PROBE_OUT136 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT136 of inst : label is "16'b0000000010001000";
attribute LC_LOW_BIT_POS_PROBE_OUT137 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT137 of inst : label is "16'b0000000010001001";
attribute LC_LOW_BIT_POS_PROBE_OUT138 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT138 of inst : label is "16'b0000000010001010";
attribute LC_LOW_BIT_POS_PROBE_OUT139 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT139 of inst : label is "16'b0000000010001011";
attribute LC_LOW_BIT_POS_PROBE_OUT14 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT14 of inst : label is "16'b0000000000001110";
attribute LC_LOW_BIT_POS_PROBE_OUT140 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT140 of inst : label is "16'b0000000010001100";
attribute LC_LOW_BIT_POS_PROBE_OUT141 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT141 of inst : label is "16'b0000000010001101";
attribute LC_LOW_BIT_POS_PROBE_OUT142 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT142 of inst : label is "16'b0000000010001110";
attribute LC_LOW_BIT_POS_PROBE_OUT143 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT143 of inst : label is "16'b0000000010001111";
attribute LC_LOW_BIT_POS_PROBE_OUT144 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT144 of inst : label is "16'b0000000010010000";
attribute LC_LOW_BIT_POS_PROBE_OUT145 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT145 of inst : label is "16'b0000000010010001";
attribute LC_LOW_BIT_POS_PROBE_OUT146 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT146 of inst : label is "16'b0000000010010010";
attribute LC_LOW_BIT_POS_PROBE_OUT147 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT147 of inst : label is "16'b0000000010010011";
attribute LC_LOW_BIT_POS_PROBE_OUT148 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT148 of inst : label is "16'b0000000010010100";
attribute LC_LOW_BIT_POS_PROBE_OUT149 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT149 of inst : label is "16'b0000000010010101";
attribute LC_LOW_BIT_POS_PROBE_OUT15 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT15 of inst : label is "16'b0000000000001111";
attribute LC_LOW_BIT_POS_PROBE_OUT150 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT150 of inst : label is "16'b0000000010010110";
attribute LC_LOW_BIT_POS_PROBE_OUT151 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT151 of inst : label is "16'b0000000010010111";
attribute LC_LOW_BIT_POS_PROBE_OUT152 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT152 of inst : label is "16'b0000000010011000";
attribute LC_LOW_BIT_POS_PROBE_OUT153 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT153 of inst : label is "16'b0000000010011001";
attribute LC_LOW_BIT_POS_PROBE_OUT154 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT154 of inst : label is "16'b0000000010011010";
attribute LC_LOW_BIT_POS_PROBE_OUT155 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT155 of inst : label is "16'b0000000010011011";
attribute LC_LOW_BIT_POS_PROBE_OUT156 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT156 of inst : label is "16'b0000000010011100";
attribute LC_LOW_BIT_POS_PROBE_OUT157 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT157 of inst : label is "16'b0000000010011101";
attribute LC_LOW_BIT_POS_PROBE_OUT158 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT158 of inst : label is "16'b0000000010011110";
attribute LC_LOW_BIT_POS_PROBE_OUT159 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT159 of inst : label is "16'b0000000010011111";
attribute LC_LOW_BIT_POS_PROBE_OUT16 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT16 of inst : label is "16'b0000000000010000";
attribute LC_LOW_BIT_POS_PROBE_OUT160 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT160 of inst : label is "16'b0000000010100000";
attribute LC_LOW_BIT_POS_PROBE_OUT161 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT161 of inst : label is "16'b0000000010100001";
attribute LC_LOW_BIT_POS_PROBE_OUT162 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT162 of inst : label is "16'b0000000010100010";
attribute LC_LOW_BIT_POS_PROBE_OUT163 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT163 of inst : label is "16'b0000000010100011";
attribute LC_LOW_BIT_POS_PROBE_OUT164 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT164 of inst : label is "16'b0000000010100100";
attribute LC_LOW_BIT_POS_PROBE_OUT165 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT165 of inst : label is "16'b0000000010100101";
attribute LC_LOW_BIT_POS_PROBE_OUT166 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT166 of inst : label is "16'b0000000010100110";
attribute LC_LOW_BIT_POS_PROBE_OUT167 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT167 of inst : label is "16'b0000000010100111";
attribute LC_LOW_BIT_POS_PROBE_OUT168 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT168 of inst : label is "16'b0000000010101000";
attribute LC_LOW_BIT_POS_PROBE_OUT169 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT169 of inst : label is "16'b0000000010101001";
attribute LC_LOW_BIT_POS_PROBE_OUT17 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT17 of inst : label is "16'b0000000000010001";
attribute LC_LOW_BIT_POS_PROBE_OUT170 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT170 of inst : label is "16'b0000000010101010";
attribute LC_LOW_BIT_POS_PROBE_OUT171 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT171 of inst : label is "16'b0000000010101011";
attribute LC_LOW_BIT_POS_PROBE_OUT172 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT172 of inst : label is "16'b0000000010101100";
attribute LC_LOW_BIT_POS_PROBE_OUT173 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT173 of inst : label is "16'b0000000010101101";
attribute LC_LOW_BIT_POS_PROBE_OUT174 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT174 of inst : label is "16'b0000000010101110";
attribute LC_LOW_BIT_POS_PROBE_OUT175 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT175 of inst : label is "16'b0000000010101111";
attribute LC_LOW_BIT_POS_PROBE_OUT176 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT176 of inst : label is "16'b0000000010110000";
attribute LC_LOW_BIT_POS_PROBE_OUT177 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT177 of inst : label is "16'b0000000010110001";
attribute LC_LOW_BIT_POS_PROBE_OUT178 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT178 of inst : label is "16'b0000000010110010";
attribute LC_LOW_BIT_POS_PROBE_OUT179 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT179 of inst : label is "16'b0000000010110011";
attribute LC_LOW_BIT_POS_PROBE_OUT18 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT18 of inst : label is "16'b0000000000010010";
attribute LC_LOW_BIT_POS_PROBE_OUT180 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT180 of inst : label is "16'b0000000010110100";
attribute LC_LOW_BIT_POS_PROBE_OUT181 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT181 of inst : label is "16'b0000000010110101";
attribute LC_LOW_BIT_POS_PROBE_OUT182 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT182 of inst : label is "16'b0000000010110110";
attribute LC_LOW_BIT_POS_PROBE_OUT183 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT183 of inst : label is "16'b0000000010110111";
attribute LC_LOW_BIT_POS_PROBE_OUT184 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT184 of inst : label is "16'b0000000010111000";
attribute LC_LOW_BIT_POS_PROBE_OUT185 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT185 of inst : label is "16'b0000000010111001";
attribute LC_LOW_BIT_POS_PROBE_OUT186 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT186 of inst : label is "16'b0000000010111010";
attribute LC_LOW_BIT_POS_PROBE_OUT187 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT187 of inst : label is "16'b0000000010111011";
attribute LC_LOW_BIT_POS_PROBE_OUT188 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT188 of inst : label is "16'b0000000010111100";
attribute LC_LOW_BIT_POS_PROBE_OUT189 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT189 of inst : label is "16'b0000000010111101";
attribute LC_LOW_BIT_POS_PROBE_OUT19 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT19 of inst : label is "16'b0000000000010011";
attribute LC_LOW_BIT_POS_PROBE_OUT190 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT190 of inst : label is "16'b0000000010111110";
attribute LC_LOW_BIT_POS_PROBE_OUT191 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT191 of inst : label is "16'b0000000010111111";
attribute LC_LOW_BIT_POS_PROBE_OUT192 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT192 of inst : label is "16'b0000000011000000";
attribute LC_LOW_BIT_POS_PROBE_OUT193 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT193 of inst : label is "16'b0000000011000001";
attribute LC_LOW_BIT_POS_PROBE_OUT194 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT194 of inst : label is "16'b0000000011000010";
attribute LC_LOW_BIT_POS_PROBE_OUT195 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT195 of inst : label is "16'b0000000011000011";
attribute LC_LOW_BIT_POS_PROBE_OUT196 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT196 of inst : label is "16'b0000000011000100";
attribute LC_LOW_BIT_POS_PROBE_OUT197 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT197 of inst : label is "16'b0000000011000101";
attribute LC_LOW_BIT_POS_PROBE_OUT198 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT198 of inst : label is "16'b0000000011000110";
attribute LC_LOW_BIT_POS_PROBE_OUT199 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT199 of inst : label is "16'b0000000011000111";
attribute LC_LOW_BIT_POS_PROBE_OUT2 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT2 of inst : label is "16'b0000000000000010";
attribute LC_LOW_BIT_POS_PROBE_OUT20 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT20 of inst : label is "16'b0000000000010100";
attribute LC_LOW_BIT_POS_PROBE_OUT200 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT200 of inst : label is "16'b0000000011001000";
attribute LC_LOW_BIT_POS_PROBE_OUT201 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT201 of inst : label is "16'b0000000011001001";
attribute LC_LOW_BIT_POS_PROBE_OUT202 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT202 of inst : label is "16'b0000000011001010";
attribute LC_LOW_BIT_POS_PROBE_OUT203 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT203 of inst : label is "16'b0000000011001011";
attribute LC_LOW_BIT_POS_PROBE_OUT204 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT204 of inst : label is "16'b0000000011001100";
attribute LC_LOW_BIT_POS_PROBE_OUT205 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT205 of inst : label is "16'b0000000011001101";
attribute LC_LOW_BIT_POS_PROBE_OUT206 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT206 of inst : label is "16'b0000000011001110";
attribute LC_LOW_BIT_POS_PROBE_OUT207 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT207 of inst : label is "16'b0000000011001111";
attribute LC_LOW_BIT_POS_PROBE_OUT208 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT208 of inst : label is "16'b0000000011010000";
attribute LC_LOW_BIT_POS_PROBE_OUT209 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT209 of inst : label is "16'b0000000011010001";
attribute LC_LOW_BIT_POS_PROBE_OUT21 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT21 of inst : label is "16'b0000000000010101";
attribute LC_LOW_BIT_POS_PROBE_OUT210 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT210 of inst : label is "16'b0000000011010010";
attribute LC_LOW_BIT_POS_PROBE_OUT211 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT211 of inst : label is "16'b0000000011010011";
attribute LC_LOW_BIT_POS_PROBE_OUT212 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT212 of inst : label is "16'b0000000011010100";
attribute LC_LOW_BIT_POS_PROBE_OUT213 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT213 of inst : label is "16'b0000000011010101";
attribute LC_LOW_BIT_POS_PROBE_OUT214 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT214 of inst : label is "16'b0000000011010110";
attribute LC_LOW_BIT_POS_PROBE_OUT215 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT215 of inst : label is "16'b0000000011010111";
attribute LC_LOW_BIT_POS_PROBE_OUT216 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT216 of inst : label is "16'b0000000011011000";
attribute LC_LOW_BIT_POS_PROBE_OUT217 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT217 of inst : label is "16'b0000000011011001";
attribute LC_LOW_BIT_POS_PROBE_OUT218 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT218 of inst : label is "16'b0000000011011010";
attribute LC_LOW_BIT_POS_PROBE_OUT219 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT219 of inst : label is "16'b0000000011011011";
attribute LC_LOW_BIT_POS_PROBE_OUT22 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT22 of inst : label is "16'b0000000000010110";
attribute LC_LOW_BIT_POS_PROBE_OUT220 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT220 of inst : label is "16'b0000000011011100";
attribute LC_LOW_BIT_POS_PROBE_OUT221 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT221 of inst : label is "16'b0000000011011101";
attribute LC_LOW_BIT_POS_PROBE_OUT222 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT222 of inst : label is "16'b0000000011011110";
attribute LC_LOW_BIT_POS_PROBE_OUT223 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT223 of inst : label is "16'b0000000011011111";
attribute LC_LOW_BIT_POS_PROBE_OUT224 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT224 of inst : label is "16'b0000000011100000";
attribute LC_LOW_BIT_POS_PROBE_OUT225 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT225 of inst : label is "16'b0000000011100001";
attribute LC_LOW_BIT_POS_PROBE_OUT226 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT226 of inst : label is "16'b0000000011100010";
attribute LC_LOW_BIT_POS_PROBE_OUT227 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT227 of inst : label is "16'b0000000011100011";
attribute LC_LOW_BIT_POS_PROBE_OUT228 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT228 of inst : label is "16'b0000000011100100";
attribute LC_LOW_BIT_POS_PROBE_OUT229 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT229 of inst : label is "16'b0000000011100101";
attribute LC_LOW_BIT_POS_PROBE_OUT23 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT23 of inst : label is "16'b0000000000010111";
attribute LC_LOW_BIT_POS_PROBE_OUT230 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT230 of inst : label is "16'b0000000011100110";
attribute LC_LOW_BIT_POS_PROBE_OUT231 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT231 of inst : label is "16'b0000000011100111";
attribute LC_LOW_BIT_POS_PROBE_OUT232 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT232 of inst : label is "16'b0000000011101000";
attribute LC_LOW_BIT_POS_PROBE_OUT233 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT233 of inst : label is "16'b0000000011101001";
attribute LC_LOW_BIT_POS_PROBE_OUT234 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT234 of inst : label is "16'b0000000011101010";
attribute LC_LOW_BIT_POS_PROBE_OUT235 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT235 of inst : label is "16'b0000000011101011";
attribute LC_LOW_BIT_POS_PROBE_OUT236 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT236 of inst : label is "16'b0000000011101100";
attribute LC_LOW_BIT_POS_PROBE_OUT237 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT237 of inst : label is "16'b0000000011101101";
attribute LC_LOW_BIT_POS_PROBE_OUT238 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT238 of inst : label is "16'b0000000011101110";
attribute LC_LOW_BIT_POS_PROBE_OUT239 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT239 of inst : label is "16'b0000000011101111";
attribute LC_LOW_BIT_POS_PROBE_OUT24 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT24 of inst : label is "16'b0000000000011000";
attribute LC_LOW_BIT_POS_PROBE_OUT240 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT240 of inst : label is "16'b0000000011110000";
attribute LC_LOW_BIT_POS_PROBE_OUT241 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT241 of inst : label is "16'b0000000011110001";
attribute LC_LOW_BIT_POS_PROBE_OUT242 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT242 of inst : label is "16'b0000000011110010";
attribute LC_LOW_BIT_POS_PROBE_OUT243 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT243 of inst : label is "16'b0000000011110011";
attribute LC_LOW_BIT_POS_PROBE_OUT244 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT244 of inst : label is "16'b0000000011110100";
attribute LC_LOW_BIT_POS_PROBE_OUT245 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT245 of inst : label is "16'b0000000011110101";
attribute LC_LOW_BIT_POS_PROBE_OUT246 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT246 of inst : label is "16'b0000000011110110";
attribute LC_LOW_BIT_POS_PROBE_OUT247 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT247 of inst : label is "16'b0000000011110111";
attribute LC_LOW_BIT_POS_PROBE_OUT248 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT248 of inst : label is "16'b0000000011111000";
attribute LC_LOW_BIT_POS_PROBE_OUT249 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT249 of inst : label is "16'b0000000011111001";
attribute LC_LOW_BIT_POS_PROBE_OUT25 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT25 of inst : label is "16'b0000000000011001";
attribute LC_LOW_BIT_POS_PROBE_OUT250 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT250 of inst : label is "16'b0000000011111010";
attribute LC_LOW_BIT_POS_PROBE_OUT251 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT251 of inst : label is "16'b0000000011111011";
attribute LC_LOW_BIT_POS_PROBE_OUT252 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT252 of inst : label is "16'b0000000011111100";
attribute LC_LOW_BIT_POS_PROBE_OUT253 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT253 of inst : label is "16'b0000000011111101";
attribute LC_LOW_BIT_POS_PROBE_OUT254 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT254 of inst : label is "16'b0000000011111110";
attribute LC_LOW_BIT_POS_PROBE_OUT255 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT255 of inst : label is "16'b0000000011111111";
attribute LC_LOW_BIT_POS_PROBE_OUT26 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT26 of inst : label is "16'b0000000000011010";
attribute LC_LOW_BIT_POS_PROBE_OUT27 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT27 of inst : label is "16'b0000000000011011";
attribute LC_LOW_BIT_POS_PROBE_OUT28 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT28 of inst : label is "16'b0000000000011100";
attribute LC_LOW_BIT_POS_PROBE_OUT29 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT29 of inst : label is "16'b0000000000011101";
attribute LC_LOW_BIT_POS_PROBE_OUT3 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT3 of inst : label is "16'b0000000000000011";
attribute LC_LOW_BIT_POS_PROBE_OUT30 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT30 of inst : label is "16'b0000000000011110";
attribute LC_LOW_BIT_POS_PROBE_OUT31 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT31 of inst : label is "16'b0000000000011111";
attribute LC_LOW_BIT_POS_PROBE_OUT32 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT32 of inst : label is "16'b0000000000100000";
attribute LC_LOW_BIT_POS_PROBE_OUT33 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT33 of inst : label is "16'b0000000000100001";
attribute LC_LOW_BIT_POS_PROBE_OUT34 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT34 of inst : label is "16'b0000000000100010";
attribute LC_LOW_BIT_POS_PROBE_OUT35 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT35 of inst : label is "16'b0000000000100011";
attribute LC_LOW_BIT_POS_PROBE_OUT36 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT36 of inst : label is "16'b0000000000100100";
attribute LC_LOW_BIT_POS_PROBE_OUT37 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT37 of inst : label is "16'b0000000000100101";
attribute LC_LOW_BIT_POS_PROBE_OUT38 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT38 of inst : label is "16'b0000000000100110";
attribute LC_LOW_BIT_POS_PROBE_OUT39 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT39 of inst : label is "16'b0000000000100111";
attribute LC_LOW_BIT_POS_PROBE_OUT4 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT4 of inst : label is "16'b0000000000000100";
attribute LC_LOW_BIT_POS_PROBE_OUT40 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT40 of inst : label is "16'b0000000000101000";
attribute LC_LOW_BIT_POS_PROBE_OUT41 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT41 of inst : label is "16'b0000000000101001";
attribute LC_LOW_BIT_POS_PROBE_OUT42 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT42 of inst : label is "16'b0000000000101010";
attribute LC_LOW_BIT_POS_PROBE_OUT43 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT43 of inst : label is "16'b0000000000101011";
attribute LC_LOW_BIT_POS_PROBE_OUT44 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT44 of inst : label is "16'b0000000000101100";
attribute LC_LOW_BIT_POS_PROBE_OUT45 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT45 of inst : label is "16'b0000000000101101";
attribute LC_LOW_BIT_POS_PROBE_OUT46 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT46 of inst : label is "16'b0000000000101110";
attribute LC_LOW_BIT_POS_PROBE_OUT47 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT47 of inst : label is "16'b0000000000101111";
attribute LC_LOW_BIT_POS_PROBE_OUT48 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT48 of inst : label is "16'b0000000000110000";
attribute LC_LOW_BIT_POS_PROBE_OUT49 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT49 of inst : label is "16'b0000000000110001";
attribute LC_LOW_BIT_POS_PROBE_OUT5 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT5 of inst : label is "16'b0000000000000101";
attribute LC_LOW_BIT_POS_PROBE_OUT50 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT50 of inst : label is "16'b0000000000110010";
attribute LC_LOW_BIT_POS_PROBE_OUT51 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT51 of inst : label is "16'b0000000000110011";
attribute LC_LOW_BIT_POS_PROBE_OUT52 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT52 of inst : label is "16'b0000000000110100";
attribute LC_LOW_BIT_POS_PROBE_OUT53 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT53 of inst : label is "16'b0000000000110101";
attribute LC_LOW_BIT_POS_PROBE_OUT54 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT54 of inst : label is "16'b0000000000110110";
attribute LC_LOW_BIT_POS_PROBE_OUT55 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT55 of inst : label is "16'b0000000000110111";
attribute LC_LOW_BIT_POS_PROBE_OUT56 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT56 of inst : label is "16'b0000000000111000";
attribute LC_LOW_BIT_POS_PROBE_OUT57 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT57 of inst : label is "16'b0000000000111001";
attribute LC_LOW_BIT_POS_PROBE_OUT58 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT58 of inst : label is "16'b0000000000111010";
attribute LC_LOW_BIT_POS_PROBE_OUT59 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT59 of inst : label is "16'b0000000000111011";
attribute LC_LOW_BIT_POS_PROBE_OUT6 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT6 of inst : label is "16'b0000000000000110";
attribute LC_LOW_BIT_POS_PROBE_OUT60 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT60 of inst : label is "16'b0000000000111100";
attribute LC_LOW_BIT_POS_PROBE_OUT61 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT61 of inst : label is "16'b0000000000111101";
attribute LC_LOW_BIT_POS_PROBE_OUT62 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT62 of inst : label is "16'b0000000000111110";
attribute LC_LOW_BIT_POS_PROBE_OUT63 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT63 of inst : label is "16'b0000000000111111";
attribute LC_LOW_BIT_POS_PROBE_OUT64 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT64 of inst : label is "16'b0000000001000000";
attribute LC_LOW_BIT_POS_PROBE_OUT65 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT65 of inst : label is "16'b0000000001000001";
attribute LC_LOW_BIT_POS_PROBE_OUT66 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT66 of inst : label is "16'b0000000001000010";
attribute LC_LOW_BIT_POS_PROBE_OUT67 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT67 of inst : label is "16'b0000000001000011";
attribute LC_LOW_BIT_POS_PROBE_OUT68 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT68 of inst : label is "16'b0000000001000100";
attribute LC_LOW_BIT_POS_PROBE_OUT69 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT69 of inst : label is "16'b0000000001000101";
attribute LC_LOW_BIT_POS_PROBE_OUT7 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT7 of inst : label is "16'b0000000000000111";
attribute LC_LOW_BIT_POS_PROBE_OUT70 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT70 of inst : label is "16'b0000000001000110";
attribute LC_LOW_BIT_POS_PROBE_OUT71 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT71 of inst : label is "16'b0000000001000111";
attribute LC_LOW_BIT_POS_PROBE_OUT72 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT72 of inst : label is "16'b0000000001001000";
attribute LC_LOW_BIT_POS_PROBE_OUT73 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT73 of inst : label is "16'b0000000001001001";
attribute LC_LOW_BIT_POS_PROBE_OUT74 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT74 of inst : label is "16'b0000000001001010";
attribute LC_LOW_BIT_POS_PROBE_OUT75 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT75 of inst : label is "16'b0000000001001011";
attribute LC_LOW_BIT_POS_PROBE_OUT76 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT76 of inst : label is "16'b0000000001001100";
attribute LC_LOW_BIT_POS_PROBE_OUT77 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT77 of inst : label is "16'b0000000001001101";
attribute LC_LOW_BIT_POS_PROBE_OUT78 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT78 of inst : label is "16'b0000000001001110";
attribute LC_LOW_BIT_POS_PROBE_OUT79 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT79 of inst : label is "16'b0000000001001111";
attribute LC_LOW_BIT_POS_PROBE_OUT8 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT8 of inst : label is "16'b0000000000001000";
attribute LC_LOW_BIT_POS_PROBE_OUT80 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT80 of inst : label is "16'b0000000001010000";
attribute LC_LOW_BIT_POS_PROBE_OUT81 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT81 of inst : label is "16'b0000000001010001";
attribute LC_LOW_BIT_POS_PROBE_OUT82 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT82 of inst : label is "16'b0000000001010010";
attribute LC_LOW_BIT_POS_PROBE_OUT83 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT83 of inst : label is "16'b0000000001010011";
attribute LC_LOW_BIT_POS_PROBE_OUT84 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT84 of inst : label is "16'b0000000001010100";
attribute LC_LOW_BIT_POS_PROBE_OUT85 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT85 of inst : label is "16'b0000000001010101";
attribute LC_LOW_BIT_POS_PROBE_OUT86 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT86 of inst : label is "16'b0000000001010110";
attribute LC_LOW_BIT_POS_PROBE_OUT87 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT87 of inst : label is "16'b0000000001010111";
attribute LC_LOW_BIT_POS_PROBE_OUT88 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT88 of inst : label is "16'b0000000001011000";
attribute LC_LOW_BIT_POS_PROBE_OUT89 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT89 of inst : label is "16'b0000000001011001";
attribute LC_LOW_BIT_POS_PROBE_OUT9 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT9 of inst : label is "16'b0000000000001001";
attribute LC_LOW_BIT_POS_PROBE_OUT90 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT90 of inst : label is "16'b0000000001011010";
attribute LC_LOW_BIT_POS_PROBE_OUT91 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT91 of inst : label is "16'b0000000001011011";
attribute LC_LOW_BIT_POS_PROBE_OUT92 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT92 of inst : label is "16'b0000000001011100";
attribute LC_LOW_BIT_POS_PROBE_OUT93 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT93 of inst : label is "16'b0000000001011101";
attribute LC_LOW_BIT_POS_PROBE_OUT94 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT94 of inst : label is "16'b0000000001011110";
attribute LC_LOW_BIT_POS_PROBE_OUT95 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT95 of inst : label is "16'b0000000001011111";
attribute LC_LOW_BIT_POS_PROBE_OUT96 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT96 of inst : label is "16'b0000000001100000";
attribute LC_LOW_BIT_POS_PROBE_OUT97 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT97 of inst : label is "16'b0000000001100001";
attribute LC_LOW_BIT_POS_PROBE_OUT98 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT98 of inst : label is "16'b0000000001100010";
attribute LC_LOW_BIT_POS_PROBE_OUT99 : string;
attribute LC_LOW_BIT_POS_PROBE_OUT99 of inst : label is "16'b0000000001100011";
attribute LC_PROBE_IN_WIDTH_STRING : string;
attribute LC_PROBE_IN_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_HIGH_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_INIT_VAL_STRING : string;
attribute LC_PROBE_OUT_INIT_VAL_STRING of inst : label is "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING : string;
attribute LC_PROBE_OUT_LOW_BIT_POS_STRING of inst : label is "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000";
attribute LC_PROBE_OUT_WIDTH_STRING : string;
attribute LC_PROBE_OUT_WIDTH_STRING of inst : label is "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute LC_TOTAL_PROBE_IN_WIDTH : integer;
attribute LC_TOTAL_PROBE_IN_WIDTH of inst : label is 4;
attribute LC_TOTAL_PROBE_OUT_WIDTH : integer;
attribute LC_TOTAL_PROBE_OUT_WIDTH of inst : label is 0;
attribute syn_noprune : string;
attribute syn_noprune of inst : label is "1";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio
port map (
clk => clk,
probe_in0(0) => probe_in0(0),
probe_in1(0) => probe_in1(0),
probe_in10(0) => '0',
probe_in100(0) => '0',
probe_in101(0) => '0',
probe_in102(0) => '0',
probe_in103(0) => '0',
probe_in104(0) => '0',
probe_in105(0) => '0',
probe_in106(0) => '0',
probe_in107(0) => '0',
probe_in108(0) => '0',
probe_in109(0) => '0',
probe_in11(0) => '0',
probe_in110(0) => '0',
probe_in111(0) => '0',
probe_in112(0) => '0',
probe_in113(0) => '0',
probe_in114(0) => '0',
probe_in115(0) => '0',
probe_in116(0) => '0',
probe_in117(0) => '0',
probe_in118(0) => '0',
probe_in119(0) => '0',
probe_in12(0) => '0',
probe_in120(0) => '0',
probe_in121(0) => '0',
probe_in122(0) => '0',
probe_in123(0) => '0',
probe_in124(0) => '0',
probe_in125(0) => '0',
probe_in126(0) => '0',
probe_in127(0) => '0',
probe_in128(0) => '0',
probe_in129(0) => '0',
probe_in13(0) => '0',
probe_in130(0) => '0',
probe_in131(0) => '0',
probe_in132(0) => '0',
probe_in133(0) => '0',
probe_in134(0) => '0',
probe_in135(0) => '0',
probe_in136(0) => '0',
probe_in137(0) => '0',
probe_in138(0) => '0',
probe_in139(0) => '0',
probe_in14(0) => '0',
probe_in140(0) => '0',
probe_in141(0) => '0',
probe_in142(0) => '0',
probe_in143(0) => '0',
probe_in144(0) => '0',
probe_in145(0) => '0',
probe_in146(0) => '0',
probe_in147(0) => '0',
probe_in148(0) => '0',
probe_in149(0) => '0',
probe_in15(0) => '0',
probe_in150(0) => '0',
probe_in151(0) => '0',
probe_in152(0) => '0',
probe_in153(0) => '0',
probe_in154(0) => '0',
probe_in155(0) => '0',
probe_in156(0) => '0',
probe_in157(0) => '0',
probe_in158(0) => '0',
probe_in159(0) => '0',
probe_in16(0) => '0',
probe_in160(0) => '0',
probe_in161(0) => '0',
probe_in162(0) => '0',
probe_in163(0) => '0',
probe_in164(0) => '0',
probe_in165(0) => '0',
probe_in166(0) => '0',
probe_in167(0) => '0',
probe_in168(0) => '0',
probe_in169(0) => '0',
probe_in17(0) => '0',
probe_in170(0) => '0',
probe_in171(0) => '0',
probe_in172(0) => '0',
probe_in173(0) => '0',
probe_in174(0) => '0',
probe_in175(0) => '0',
probe_in176(0) => '0',
probe_in177(0) => '0',
probe_in178(0) => '0',
probe_in179(0) => '0',
probe_in18(0) => '0',
probe_in180(0) => '0',
probe_in181(0) => '0',
probe_in182(0) => '0',
probe_in183(0) => '0',
probe_in184(0) => '0',
probe_in185(0) => '0',
probe_in186(0) => '0',
probe_in187(0) => '0',
probe_in188(0) => '0',
probe_in189(0) => '0',
probe_in19(0) => '0',
probe_in190(0) => '0',
probe_in191(0) => '0',
probe_in192(0) => '0',
probe_in193(0) => '0',
probe_in194(0) => '0',
probe_in195(0) => '0',
probe_in196(0) => '0',
probe_in197(0) => '0',
probe_in198(0) => '0',
probe_in199(0) => '0',
probe_in2(0) => probe_in2(0),
probe_in20(0) => '0',
probe_in200(0) => '0',
probe_in201(0) => '0',
probe_in202(0) => '0',
probe_in203(0) => '0',
probe_in204(0) => '0',
probe_in205(0) => '0',
probe_in206(0) => '0',
probe_in207(0) => '0',
probe_in208(0) => '0',
probe_in209(0) => '0',
probe_in21(0) => '0',
probe_in210(0) => '0',
probe_in211(0) => '0',
probe_in212(0) => '0',
probe_in213(0) => '0',
probe_in214(0) => '0',
probe_in215(0) => '0',
probe_in216(0) => '0',
probe_in217(0) => '0',
probe_in218(0) => '0',
probe_in219(0) => '0',
probe_in22(0) => '0',
probe_in220(0) => '0',
probe_in221(0) => '0',
probe_in222(0) => '0',
probe_in223(0) => '0',
probe_in224(0) => '0',
probe_in225(0) => '0',
probe_in226(0) => '0',
probe_in227(0) => '0',
probe_in228(0) => '0',
probe_in229(0) => '0',
probe_in23(0) => '0',
probe_in230(0) => '0',
probe_in231(0) => '0',
probe_in232(0) => '0',
probe_in233(0) => '0',
probe_in234(0) => '0',
probe_in235(0) => '0',
probe_in236(0) => '0',
probe_in237(0) => '0',
probe_in238(0) => '0',
probe_in239(0) => '0',
probe_in24(0) => '0',
probe_in240(0) => '0',
probe_in241(0) => '0',
probe_in242(0) => '0',
probe_in243(0) => '0',
probe_in244(0) => '0',
probe_in245(0) => '0',
probe_in246(0) => '0',
probe_in247(0) => '0',
probe_in248(0) => '0',
probe_in249(0) => '0',
probe_in25(0) => '0',
probe_in250(0) => '0',
probe_in251(0) => '0',
probe_in252(0) => '0',
probe_in253(0) => '0',
probe_in254(0) => '0',
probe_in255(0) => '0',
probe_in26(0) => '0',
probe_in27(0) => '0',
probe_in28(0) => '0',
probe_in29(0) => '0',
probe_in3(0) => probe_in3(0),
probe_in30(0) => '0',
probe_in31(0) => '0',
probe_in32(0) => '0',
probe_in33(0) => '0',
probe_in34(0) => '0',
probe_in35(0) => '0',
probe_in36(0) => '0',
probe_in37(0) => '0',
probe_in38(0) => '0',
probe_in39(0) => '0',
probe_in4(0) => '0',
probe_in40(0) => '0',
probe_in41(0) => '0',
probe_in42(0) => '0',
probe_in43(0) => '0',
probe_in44(0) => '0',
probe_in45(0) => '0',
probe_in46(0) => '0',
probe_in47(0) => '0',
probe_in48(0) => '0',
probe_in49(0) => '0',
probe_in5(0) => '0',
probe_in50(0) => '0',
probe_in51(0) => '0',
probe_in52(0) => '0',
probe_in53(0) => '0',
probe_in54(0) => '0',
probe_in55(0) => '0',
probe_in56(0) => '0',
probe_in57(0) => '0',
probe_in58(0) => '0',
probe_in59(0) => '0',
probe_in6(0) => '0',
probe_in60(0) => '0',
probe_in61(0) => '0',
probe_in62(0) => '0',
probe_in63(0) => '0',
probe_in64(0) => '0',
probe_in65(0) => '0',
probe_in66(0) => '0',
probe_in67(0) => '0',
probe_in68(0) => '0',
probe_in69(0) => '0',
probe_in7(0) => '0',
probe_in70(0) => '0',
probe_in71(0) => '0',
probe_in72(0) => '0',
probe_in73(0) => '0',
probe_in74(0) => '0',
probe_in75(0) => '0',
probe_in76(0) => '0',
probe_in77(0) => '0',
probe_in78(0) => '0',
probe_in79(0) => '0',
probe_in8(0) => '0',
probe_in80(0) => '0',
probe_in81(0) => '0',
probe_in82(0) => '0',
probe_in83(0) => '0',
probe_in84(0) => '0',
probe_in85(0) => '0',
probe_in86(0) => '0',
probe_in87(0) => '0',
probe_in88(0) => '0',
probe_in89(0) => '0',
probe_in9(0) => '0',
probe_in90(0) => '0',
probe_in91(0) => '0',
probe_in92(0) => '0',
probe_in93(0) => '0',
probe_in94(0) => '0',
probe_in95(0) => '0',
probe_in96(0) => '0',
probe_in97(0) => '0',
probe_in98(0) => '0',
probe_in99(0) => '0',
probe_out0(0) => NLW_inst_probe_out0_UNCONNECTED(0),
probe_out1(0) => NLW_inst_probe_out1_UNCONNECTED(0),
probe_out10(0) => NLW_inst_probe_out10_UNCONNECTED(0),
probe_out100(0) => NLW_inst_probe_out100_UNCONNECTED(0),
probe_out101(0) => NLW_inst_probe_out101_UNCONNECTED(0),
probe_out102(0) => NLW_inst_probe_out102_UNCONNECTED(0),
probe_out103(0) => NLW_inst_probe_out103_UNCONNECTED(0),
probe_out104(0) => NLW_inst_probe_out104_UNCONNECTED(0),
probe_out105(0) => NLW_inst_probe_out105_UNCONNECTED(0),
probe_out106(0) => NLW_inst_probe_out106_UNCONNECTED(0),
probe_out107(0) => NLW_inst_probe_out107_UNCONNECTED(0),
probe_out108(0) => NLW_inst_probe_out108_UNCONNECTED(0),
probe_out109(0) => NLW_inst_probe_out109_UNCONNECTED(0),
probe_out11(0) => NLW_inst_probe_out11_UNCONNECTED(0),
probe_out110(0) => NLW_inst_probe_out110_UNCONNECTED(0),
probe_out111(0) => NLW_inst_probe_out111_UNCONNECTED(0),
probe_out112(0) => NLW_inst_probe_out112_UNCONNECTED(0),
probe_out113(0) => NLW_inst_probe_out113_UNCONNECTED(0),
probe_out114(0) => NLW_inst_probe_out114_UNCONNECTED(0),
probe_out115(0) => NLW_inst_probe_out115_UNCONNECTED(0),
probe_out116(0) => NLW_inst_probe_out116_UNCONNECTED(0),
probe_out117(0) => NLW_inst_probe_out117_UNCONNECTED(0),
probe_out118(0) => NLW_inst_probe_out118_UNCONNECTED(0),
probe_out119(0) => NLW_inst_probe_out119_UNCONNECTED(0),
probe_out12(0) => NLW_inst_probe_out12_UNCONNECTED(0),
probe_out120(0) => NLW_inst_probe_out120_UNCONNECTED(0),
probe_out121(0) => NLW_inst_probe_out121_UNCONNECTED(0),
probe_out122(0) => NLW_inst_probe_out122_UNCONNECTED(0),
probe_out123(0) => NLW_inst_probe_out123_UNCONNECTED(0),
probe_out124(0) => NLW_inst_probe_out124_UNCONNECTED(0),
probe_out125(0) => NLW_inst_probe_out125_UNCONNECTED(0),
probe_out126(0) => NLW_inst_probe_out126_UNCONNECTED(0),
probe_out127(0) => NLW_inst_probe_out127_UNCONNECTED(0),
probe_out128(0) => NLW_inst_probe_out128_UNCONNECTED(0),
probe_out129(0) => NLW_inst_probe_out129_UNCONNECTED(0),
probe_out13(0) => NLW_inst_probe_out13_UNCONNECTED(0),
probe_out130(0) => NLW_inst_probe_out130_UNCONNECTED(0),
probe_out131(0) => NLW_inst_probe_out131_UNCONNECTED(0),
probe_out132(0) => NLW_inst_probe_out132_UNCONNECTED(0),
probe_out133(0) => NLW_inst_probe_out133_UNCONNECTED(0),
probe_out134(0) => NLW_inst_probe_out134_UNCONNECTED(0),
probe_out135(0) => NLW_inst_probe_out135_UNCONNECTED(0),
probe_out136(0) => NLW_inst_probe_out136_UNCONNECTED(0),
probe_out137(0) => NLW_inst_probe_out137_UNCONNECTED(0),
probe_out138(0) => NLW_inst_probe_out138_UNCONNECTED(0),
probe_out139(0) => NLW_inst_probe_out139_UNCONNECTED(0),
probe_out14(0) => NLW_inst_probe_out14_UNCONNECTED(0),
probe_out140(0) => NLW_inst_probe_out140_UNCONNECTED(0),
probe_out141(0) => NLW_inst_probe_out141_UNCONNECTED(0),
probe_out142(0) => NLW_inst_probe_out142_UNCONNECTED(0),
probe_out143(0) => NLW_inst_probe_out143_UNCONNECTED(0),
probe_out144(0) => NLW_inst_probe_out144_UNCONNECTED(0),
probe_out145(0) => NLW_inst_probe_out145_UNCONNECTED(0),
probe_out146(0) => NLW_inst_probe_out146_UNCONNECTED(0),
probe_out147(0) => NLW_inst_probe_out147_UNCONNECTED(0),
probe_out148(0) => NLW_inst_probe_out148_UNCONNECTED(0),
probe_out149(0) => NLW_inst_probe_out149_UNCONNECTED(0),
probe_out15(0) => NLW_inst_probe_out15_UNCONNECTED(0),
probe_out150(0) => NLW_inst_probe_out150_UNCONNECTED(0),
probe_out151(0) => NLW_inst_probe_out151_UNCONNECTED(0),
probe_out152(0) => NLW_inst_probe_out152_UNCONNECTED(0),
probe_out153(0) => NLW_inst_probe_out153_UNCONNECTED(0),
probe_out154(0) => NLW_inst_probe_out154_UNCONNECTED(0),
probe_out155(0) => NLW_inst_probe_out155_UNCONNECTED(0),
probe_out156(0) => NLW_inst_probe_out156_UNCONNECTED(0),
probe_out157(0) => NLW_inst_probe_out157_UNCONNECTED(0),
probe_out158(0) => NLW_inst_probe_out158_UNCONNECTED(0),
probe_out159(0) => NLW_inst_probe_out159_UNCONNECTED(0),
probe_out16(0) => NLW_inst_probe_out16_UNCONNECTED(0),
probe_out160(0) => NLW_inst_probe_out160_UNCONNECTED(0),
probe_out161(0) => NLW_inst_probe_out161_UNCONNECTED(0),
probe_out162(0) => NLW_inst_probe_out162_UNCONNECTED(0),
probe_out163(0) => NLW_inst_probe_out163_UNCONNECTED(0),
probe_out164(0) => NLW_inst_probe_out164_UNCONNECTED(0),
probe_out165(0) => NLW_inst_probe_out165_UNCONNECTED(0),
probe_out166(0) => NLW_inst_probe_out166_UNCONNECTED(0),
probe_out167(0) => NLW_inst_probe_out167_UNCONNECTED(0),
probe_out168(0) => NLW_inst_probe_out168_UNCONNECTED(0),
probe_out169(0) => NLW_inst_probe_out169_UNCONNECTED(0),
probe_out17(0) => NLW_inst_probe_out17_UNCONNECTED(0),
probe_out170(0) => NLW_inst_probe_out170_UNCONNECTED(0),
probe_out171(0) => NLW_inst_probe_out171_UNCONNECTED(0),
probe_out172(0) => NLW_inst_probe_out172_UNCONNECTED(0),
probe_out173(0) => NLW_inst_probe_out173_UNCONNECTED(0),
probe_out174(0) => NLW_inst_probe_out174_UNCONNECTED(0),
probe_out175(0) => NLW_inst_probe_out175_UNCONNECTED(0),
probe_out176(0) => NLW_inst_probe_out176_UNCONNECTED(0),
probe_out177(0) => NLW_inst_probe_out177_UNCONNECTED(0),
probe_out178(0) => NLW_inst_probe_out178_UNCONNECTED(0),
probe_out179(0) => NLW_inst_probe_out179_UNCONNECTED(0),
probe_out18(0) => NLW_inst_probe_out18_UNCONNECTED(0),
probe_out180(0) => NLW_inst_probe_out180_UNCONNECTED(0),
probe_out181(0) => NLW_inst_probe_out181_UNCONNECTED(0),
probe_out182(0) => NLW_inst_probe_out182_UNCONNECTED(0),
probe_out183(0) => NLW_inst_probe_out183_UNCONNECTED(0),
probe_out184(0) => NLW_inst_probe_out184_UNCONNECTED(0),
probe_out185(0) => NLW_inst_probe_out185_UNCONNECTED(0),
probe_out186(0) => NLW_inst_probe_out186_UNCONNECTED(0),
probe_out187(0) => NLW_inst_probe_out187_UNCONNECTED(0),
probe_out188(0) => NLW_inst_probe_out188_UNCONNECTED(0),
probe_out189(0) => NLW_inst_probe_out189_UNCONNECTED(0),
probe_out19(0) => NLW_inst_probe_out19_UNCONNECTED(0),
probe_out190(0) => NLW_inst_probe_out190_UNCONNECTED(0),
probe_out191(0) => NLW_inst_probe_out191_UNCONNECTED(0),
probe_out192(0) => NLW_inst_probe_out192_UNCONNECTED(0),
probe_out193(0) => NLW_inst_probe_out193_UNCONNECTED(0),
probe_out194(0) => NLW_inst_probe_out194_UNCONNECTED(0),
probe_out195(0) => NLW_inst_probe_out195_UNCONNECTED(0),
probe_out196(0) => NLW_inst_probe_out196_UNCONNECTED(0),
probe_out197(0) => NLW_inst_probe_out197_UNCONNECTED(0),
probe_out198(0) => NLW_inst_probe_out198_UNCONNECTED(0),
probe_out199(0) => NLW_inst_probe_out199_UNCONNECTED(0),
probe_out2(0) => NLW_inst_probe_out2_UNCONNECTED(0),
probe_out20(0) => NLW_inst_probe_out20_UNCONNECTED(0),
probe_out200(0) => NLW_inst_probe_out200_UNCONNECTED(0),
probe_out201(0) => NLW_inst_probe_out201_UNCONNECTED(0),
probe_out202(0) => NLW_inst_probe_out202_UNCONNECTED(0),
probe_out203(0) => NLW_inst_probe_out203_UNCONNECTED(0),
probe_out204(0) => NLW_inst_probe_out204_UNCONNECTED(0),
probe_out205(0) => NLW_inst_probe_out205_UNCONNECTED(0),
probe_out206(0) => NLW_inst_probe_out206_UNCONNECTED(0),
probe_out207(0) => NLW_inst_probe_out207_UNCONNECTED(0),
probe_out208(0) => NLW_inst_probe_out208_UNCONNECTED(0),
probe_out209(0) => NLW_inst_probe_out209_UNCONNECTED(0),
probe_out21(0) => NLW_inst_probe_out21_UNCONNECTED(0),
probe_out210(0) => NLW_inst_probe_out210_UNCONNECTED(0),
probe_out211(0) => NLW_inst_probe_out211_UNCONNECTED(0),
probe_out212(0) => NLW_inst_probe_out212_UNCONNECTED(0),
probe_out213(0) => NLW_inst_probe_out213_UNCONNECTED(0),
probe_out214(0) => NLW_inst_probe_out214_UNCONNECTED(0),
probe_out215(0) => NLW_inst_probe_out215_UNCONNECTED(0),
probe_out216(0) => NLW_inst_probe_out216_UNCONNECTED(0),
probe_out217(0) => NLW_inst_probe_out217_UNCONNECTED(0),
probe_out218(0) => NLW_inst_probe_out218_UNCONNECTED(0),
probe_out219(0) => NLW_inst_probe_out219_UNCONNECTED(0),
probe_out22(0) => NLW_inst_probe_out22_UNCONNECTED(0),
probe_out220(0) => NLW_inst_probe_out220_UNCONNECTED(0),
probe_out221(0) => NLW_inst_probe_out221_UNCONNECTED(0),
probe_out222(0) => NLW_inst_probe_out222_UNCONNECTED(0),
probe_out223(0) => NLW_inst_probe_out223_UNCONNECTED(0),
probe_out224(0) => NLW_inst_probe_out224_UNCONNECTED(0),
probe_out225(0) => NLW_inst_probe_out225_UNCONNECTED(0),
probe_out226(0) => NLW_inst_probe_out226_UNCONNECTED(0),
probe_out227(0) => NLW_inst_probe_out227_UNCONNECTED(0),
probe_out228(0) => NLW_inst_probe_out228_UNCONNECTED(0),
probe_out229(0) => NLW_inst_probe_out229_UNCONNECTED(0),
probe_out23(0) => NLW_inst_probe_out23_UNCONNECTED(0),
probe_out230(0) => NLW_inst_probe_out230_UNCONNECTED(0),
probe_out231(0) => NLW_inst_probe_out231_UNCONNECTED(0),
probe_out232(0) => NLW_inst_probe_out232_UNCONNECTED(0),
probe_out233(0) => NLW_inst_probe_out233_UNCONNECTED(0),
probe_out234(0) => NLW_inst_probe_out234_UNCONNECTED(0),
probe_out235(0) => NLW_inst_probe_out235_UNCONNECTED(0),
probe_out236(0) => NLW_inst_probe_out236_UNCONNECTED(0),
probe_out237(0) => NLW_inst_probe_out237_UNCONNECTED(0),
probe_out238(0) => NLW_inst_probe_out238_UNCONNECTED(0),
probe_out239(0) => NLW_inst_probe_out239_UNCONNECTED(0),
probe_out24(0) => NLW_inst_probe_out24_UNCONNECTED(0),
probe_out240(0) => NLW_inst_probe_out240_UNCONNECTED(0),
probe_out241(0) => NLW_inst_probe_out241_UNCONNECTED(0),
probe_out242(0) => NLW_inst_probe_out242_UNCONNECTED(0),
probe_out243(0) => NLW_inst_probe_out243_UNCONNECTED(0),
probe_out244(0) => NLW_inst_probe_out244_UNCONNECTED(0),
probe_out245(0) => NLW_inst_probe_out245_UNCONNECTED(0),
probe_out246(0) => NLW_inst_probe_out246_UNCONNECTED(0),
probe_out247(0) => NLW_inst_probe_out247_UNCONNECTED(0),
probe_out248(0) => NLW_inst_probe_out248_UNCONNECTED(0),
probe_out249(0) => NLW_inst_probe_out249_UNCONNECTED(0),
probe_out25(0) => NLW_inst_probe_out25_UNCONNECTED(0),
probe_out250(0) => NLW_inst_probe_out250_UNCONNECTED(0),
probe_out251(0) => NLW_inst_probe_out251_UNCONNECTED(0),
probe_out252(0) => NLW_inst_probe_out252_UNCONNECTED(0),
probe_out253(0) => NLW_inst_probe_out253_UNCONNECTED(0),
probe_out254(0) => NLW_inst_probe_out254_UNCONNECTED(0),
probe_out255(0) => NLW_inst_probe_out255_UNCONNECTED(0),
probe_out26(0) => NLW_inst_probe_out26_UNCONNECTED(0),
probe_out27(0) => NLW_inst_probe_out27_UNCONNECTED(0),
probe_out28(0) => NLW_inst_probe_out28_UNCONNECTED(0),
probe_out29(0) => NLW_inst_probe_out29_UNCONNECTED(0),
probe_out3(0) => NLW_inst_probe_out3_UNCONNECTED(0),
probe_out30(0) => NLW_inst_probe_out30_UNCONNECTED(0),
probe_out31(0) => NLW_inst_probe_out31_UNCONNECTED(0),
probe_out32(0) => NLW_inst_probe_out32_UNCONNECTED(0),
probe_out33(0) => NLW_inst_probe_out33_UNCONNECTED(0),
probe_out34(0) => NLW_inst_probe_out34_UNCONNECTED(0),
probe_out35(0) => NLW_inst_probe_out35_UNCONNECTED(0),
probe_out36(0) => NLW_inst_probe_out36_UNCONNECTED(0),
probe_out37(0) => NLW_inst_probe_out37_UNCONNECTED(0),
probe_out38(0) => NLW_inst_probe_out38_UNCONNECTED(0),
probe_out39(0) => NLW_inst_probe_out39_UNCONNECTED(0),
probe_out4(0) => NLW_inst_probe_out4_UNCONNECTED(0),
probe_out40(0) => NLW_inst_probe_out40_UNCONNECTED(0),
probe_out41(0) => NLW_inst_probe_out41_UNCONNECTED(0),
probe_out42(0) => NLW_inst_probe_out42_UNCONNECTED(0),
probe_out43(0) => NLW_inst_probe_out43_UNCONNECTED(0),
probe_out44(0) => NLW_inst_probe_out44_UNCONNECTED(0),
probe_out45(0) => NLW_inst_probe_out45_UNCONNECTED(0),
probe_out46(0) => NLW_inst_probe_out46_UNCONNECTED(0),
probe_out47(0) => NLW_inst_probe_out47_UNCONNECTED(0),
probe_out48(0) => NLW_inst_probe_out48_UNCONNECTED(0),
probe_out49(0) => NLW_inst_probe_out49_UNCONNECTED(0),
probe_out5(0) => NLW_inst_probe_out5_UNCONNECTED(0),
probe_out50(0) => NLW_inst_probe_out50_UNCONNECTED(0),
probe_out51(0) => NLW_inst_probe_out51_UNCONNECTED(0),
probe_out52(0) => NLW_inst_probe_out52_UNCONNECTED(0),
probe_out53(0) => NLW_inst_probe_out53_UNCONNECTED(0),
probe_out54(0) => NLW_inst_probe_out54_UNCONNECTED(0),
probe_out55(0) => NLW_inst_probe_out55_UNCONNECTED(0),
probe_out56(0) => NLW_inst_probe_out56_UNCONNECTED(0),
probe_out57(0) => NLW_inst_probe_out57_UNCONNECTED(0),
probe_out58(0) => NLW_inst_probe_out58_UNCONNECTED(0),
probe_out59(0) => NLW_inst_probe_out59_UNCONNECTED(0),
probe_out6(0) => NLW_inst_probe_out6_UNCONNECTED(0),
probe_out60(0) => NLW_inst_probe_out60_UNCONNECTED(0),
probe_out61(0) => NLW_inst_probe_out61_UNCONNECTED(0),
probe_out62(0) => NLW_inst_probe_out62_UNCONNECTED(0),
probe_out63(0) => NLW_inst_probe_out63_UNCONNECTED(0),
probe_out64(0) => NLW_inst_probe_out64_UNCONNECTED(0),
probe_out65(0) => NLW_inst_probe_out65_UNCONNECTED(0),
probe_out66(0) => NLW_inst_probe_out66_UNCONNECTED(0),
probe_out67(0) => NLW_inst_probe_out67_UNCONNECTED(0),
probe_out68(0) => NLW_inst_probe_out68_UNCONNECTED(0),
probe_out69(0) => NLW_inst_probe_out69_UNCONNECTED(0),
probe_out7(0) => NLW_inst_probe_out7_UNCONNECTED(0),
probe_out70(0) => NLW_inst_probe_out70_UNCONNECTED(0),
probe_out71(0) => NLW_inst_probe_out71_UNCONNECTED(0),
probe_out72(0) => NLW_inst_probe_out72_UNCONNECTED(0),
probe_out73(0) => NLW_inst_probe_out73_UNCONNECTED(0),
probe_out74(0) => NLW_inst_probe_out74_UNCONNECTED(0),
probe_out75(0) => NLW_inst_probe_out75_UNCONNECTED(0),
probe_out76(0) => NLW_inst_probe_out76_UNCONNECTED(0),
probe_out77(0) => NLW_inst_probe_out77_UNCONNECTED(0),
probe_out78(0) => NLW_inst_probe_out78_UNCONNECTED(0),
probe_out79(0) => NLW_inst_probe_out79_UNCONNECTED(0),
probe_out8(0) => NLW_inst_probe_out8_UNCONNECTED(0),
probe_out80(0) => NLW_inst_probe_out80_UNCONNECTED(0),
probe_out81(0) => NLW_inst_probe_out81_UNCONNECTED(0),
probe_out82(0) => NLW_inst_probe_out82_UNCONNECTED(0),
probe_out83(0) => NLW_inst_probe_out83_UNCONNECTED(0),
probe_out84(0) => NLW_inst_probe_out84_UNCONNECTED(0),
probe_out85(0) => NLW_inst_probe_out85_UNCONNECTED(0),
probe_out86(0) => NLW_inst_probe_out86_UNCONNECTED(0),
probe_out87(0) => NLW_inst_probe_out87_UNCONNECTED(0),
probe_out88(0) => NLW_inst_probe_out88_UNCONNECTED(0),
probe_out89(0) => NLW_inst_probe_out89_UNCONNECTED(0),
probe_out9(0) => NLW_inst_probe_out9_UNCONNECTED(0),
probe_out90(0) => NLW_inst_probe_out90_UNCONNECTED(0),
probe_out91(0) => NLW_inst_probe_out91_UNCONNECTED(0),
probe_out92(0) => NLW_inst_probe_out92_UNCONNECTED(0),
probe_out93(0) => NLW_inst_probe_out93_UNCONNECTED(0),
probe_out94(0) => NLW_inst_probe_out94_UNCONNECTED(0),
probe_out95(0) => NLW_inst_probe_out95_UNCONNECTED(0),
probe_out96(0) => NLW_inst_probe_out96_UNCONNECTED(0),
probe_out97(0) => NLW_inst_probe_out97_UNCONNECTED(0),
probe_out98(0) => NLW_inst_probe_out98_UNCONNECTED(0),
probe_out99(0) => NLW_inst_probe_out99_UNCONNECTED(0),
sl_iport0(36 downto 0) => B"0000000000000000000000000000000000000",
sl_oport0(16 downto 0) => NLW_inst_sl_oport0_UNCONNECTED(16 downto 0)
);
end STRUCTURE;
|
-------------------------------------------------------------------------------
-- $Id: pselect.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- pselect.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:02 $
--
-- History:
-- BLT 2001-04-10 First Version
-- BLT 2001-04-23 Moved function to this file
-- BLT 2001-05-21 Changed library to MicroBlaze
-- BLT 2001-08-13 Changed pragma to synthesis
-- ALS 2001-10-15 C_BAR is now padded to nearest multiple of 4
-- to handle lut equations
-- FLO 2002-03-26 Corrected implementation for case where C_AB
-- is not a multiple of 4 and the C_BAR values
-- at the pad bits are not '0'.
-- Removed implementation restriction that
-- required C_AW = C_BAR'length.
-- Added assertion to flag invalid generic
-- combinations.
-- ALS, FLO 2002-04-09 -Implemented XST workaround for the case
-- that C_AB = 0.
-- -Removed remnants of earlier
-- "instantiated-lut" implementation.
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MUXCY
port map (
O => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- pselect.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect.vhd
--
-- Description: Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain. For version with AValid at top of
-- carry chain, see pselect_top.vhd.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:02 $
--
-- History:
-- BLT 2001-04-10 First Version
-- BLT 2001-04-23 Moved function to this file
-- BLT 2001-05-21 Changed library to MicroBlaze
-- BLT 2001-08-13 Changed pragma to synthesis
-- ALS 2001-10-15 C_BAR is now padded to nearest multiple of 4
-- to handle lut equations
-- FLO 2002-03-26 Corrected implementation for case where C_AB
-- is not a multiple of 4 and the C_BAR values
-- at the pad bits are not '0'.
-- Removed implementation restriction that
-- required C_AW = C_BAR'length.
-- Added assertion to flag invalid generic
-- combinations.
-- ALS, FLO 2002-04-09 -Implemented XST workaround for the case
-- that C_AB = 0.
-- -Removed remnants of earlier
-- "instantiated-lut" implementation.
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect is
attribute INIT : string;
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_LUTS : integer := (C_AB+3)/4;
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
--signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Check that the passed generics allow for correct implementation.
--------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
--------------------------------------------------------------------------------
-- Build the decoder using the fast carry chain.
--------------------------------------------------------------------------------
carry_chain(0) <= AValid;
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST; remove this
-- enclosing generate when fixed
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
signal lut_in : std_logic_vector(3 downto 0);
signal invert : std_logic_vector(3 downto 0);
begin
GEN_LUT_INPUTS: for j in 0 to 3 generate
-- Generate to assign address bits to LUT4 inputs
GEN_INPUT: if i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4) generate
lut_in(j) <= A(i*4+j);
invert(j) <= not BAR(i*4+j);
end generate;
-- Generate to assign one to remaining LUT4, pad, inputs
GEN_ZEROS: if not(i < NUM_LUTS-1 or j <= ((C_AB-1) mod 4)) generate
lut_in(j) <= '1';
invert(j) <= '0';
end generate;
end generate;
---------------------------------------------------------------------------
-- RTL LUT instantiation
---------------------------------------------------------------------------
lut_out(i) <= (lut_in(0) xor invert(0)) and
(lut_in(1) xor invert(1)) and
(lut_in(2) xor invert(2)) and
(lut_in(3) xor invert(3));
MUXCY_I: MUXCY
port map (
O => carry_chain(i+1), --[out]
CI => carry_chain(i), --[in]
DI => '0', --[in]
S => lut_out(i) --[in]
);
end generate GEN_DECODE;
end generate XST_WA;
CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output;
-- if NUM_LUTS=0, then
-- CS <= carry_chain(0) <= AValid
end imp;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libfpu
-- File: libfpu.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 FPU interface types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
package libfpu is
type fp_rf_in_type is record
rd1addr : std_logic_vector(3 downto 0); -- read address 1
rd2addr : std_logic_vector(3 downto 0); -- read address 2
wraddr : std_logic_vector(3 downto 0); -- write address
wrdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
end record;
type fp_rf_out_type is record
data1 : std_logic_vector(31 downto 0); -- read data 1
data2 : std_logic_vector(31 downto 0); -- read data 2
end record;
type fpc_pipeline_control_type is record
pc : std_logic_vector(31 downto 0);
inst : std_logic_vector(31 downto 0);
cnt : std_logic_vector(1 downto 0);
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
end record;
type fpc_debug_in_type is record
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic; -- FSR access
addr : std_logic_vector(4 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type fpc_debug_out_type is record
data : std_logic_vector(31 downto 0);
end record;
constant fpc_debug_none : fpc_debug_out_type := (data => X"00000000"
);
type fpc_in_type is record
flush : std_ulogic; -- pipeline flush
exack : std_ulogic; -- FP exception acknowledge
a_rs1 : std_logic_vector(4 downto 0);
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector(31 downto 0); -- load data
dbg : fpc_debug_in_type; -- debug signals
end record;
type fpc_out_type is record
data : std_logic_vector(31 downto 0); -- store data
exc : std_logic; -- FP exception
cc : std_logic_vector(1 downto 0); -- FP condition codes
ccv : std_ulogic; -- FP condition codes valid
ldlock : std_logic; -- FP pipeline hold
holdn : std_ulogic;
dbg : fpc_debug_out_type; -- FP debug signals
end record;
constant fpc_out_none : fpc_out_type := (X"00000000", '0', "00", '1', '0', '1',
fpc_debug_none);
component grfpwxsh
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--------------------------------------------------------
-- Sin celda y sin maquina de estados
--------------------------------------------------------
-- x^113 + x ^9 + 1
entity serial_multiplier_113 is
generic (
NUM_BITS : positive := 113 -- The order of the finite field
);
port(
ax : in std_logic_vector(NUM_BITS-1 downto 0);
bx : in std_logic_vector(NUM_BITS-1 downto 0);
cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx
reset : in std_logic;
clk : in std_logic;
done : out std_logic
);
end serial_multiplier_113;
-----------------------------------------------------------
architecture behave of serial_multiplier_113 is
-----------------------------------------------------------
signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth
signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers
signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m
signal done_int : std_logic;
--señales para las xor de la reduccion:
signal xor_1 : std_logic;
-----------------------------------------------------------
-- States for the finite state machine
-----------------------------------------------------------
--type CurrentState_type is (NOTHING, END_STATE, MUL_STATE);
--signal CurrentState: CurrentState_type;
-----------------------------------------------------------
begin
-----------------------------------------------------------
-- Result of the multiplication
xor_1 <= Cx_int(8) xor Cx_int(NUM_BITS-1);
--Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position
bx_int <= Bx_shift; -- Shift Bx to left one position
------------------------------------------------------------
-- The finite state machine, it takes m cycles to compute
-- the multiplication, a counter is used to keep this count
------------------------------------------------------------
done <= done_int;
cx <= cx_int;
FSM_MUL: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
counter <= "00000000"; -- m-1 value, in this case, it is 112, be sure to set the correct value
cx_int <= (others => '0');
Done_int <= '0';
else
if done_int = '0' then
counter <= counter + 1;
Cx_int(0) <= ( Ax(0) and Bx_int(NUM_BITS-1) ) xor Cx_int(NUM_BITS-1);
Cx_int(1) <= ( Ax(1) and Bx_int(NUM_BITS-1) ) xor Cx_int(0);
Cx_int(2) <= ( Ax(2) and Bx_int(NUM_BITS-1) ) xor Cx_int(1);
Cx_int(3) <= ( Ax(3) and Bx_int(NUM_BITS-1) ) xor Cx_int(2);
Cx_int(4) <= ( Ax(4) and Bx_int(NUM_BITS-1) ) xor Cx_int(3);
Cx_int(5) <= ( Ax(5) and Bx_int(NUM_BITS-1) ) xor Cx_int(4);
Cx_int(6) <= ( Ax(6) and Bx_int(NUM_BITS-1) ) xor Cx_int(5);
Cx_int(7) <= ( Ax(7) and Bx_int(NUM_BITS-1) ) xor Cx_int(6);
Cx_int(8) <= ( Ax(8) and Bx_int(NUM_BITS-1) ) xor Cx_int(7);
Cx_int(9) <= ( Ax(9) and Bx_int(NUM_BITS-1) ) xor xor_1;
Cx_int(10) <= ( Ax(10) and Bx_int(NUM_BITS-1) ) xor Cx_int(9);
Cx_int(11) <= ( Ax(11) and Bx_int(NUM_BITS-1) ) xor Cx_int(10);
Cx_int(12) <= ( Ax(12) and Bx_int(NUM_BITS-1) ) xor Cx_int(11);
Cx_int(13) <= ( Ax(13) and Bx_int(NUM_BITS-1) ) xor Cx_int(12);
Cx_int(14) <= ( Ax(14) and Bx_int(NUM_BITS-1) ) xor Cx_int(13);
Cx_int(15) <= ( Ax(15) and Bx_int(NUM_BITS-1) ) xor Cx_int(14);
Cx_int(16) <= ( Ax(16) and Bx_int(NUM_BITS-1) ) xor Cx_int(15);
Cx_int(17) <= ( Ax(17) and Bx_int(NUM_BITS-1) ) xor Cx_int(16);
Cx_int(18) <= ( Ax(18) and Bx_int(NUM_BITS-1) ) xor Cx_int(17);
Cx_int(19) <= ( Ax(19) and Bx_int(NUM_BITS-1) ) xor Cx_int(18);
Cx_int(20) <= ( Ax(20) and Bx_int(NUM_BITS-1) ) xor Cx_int(19);
Cx_int(21) <= ( Ax(21) and Bx_int(NUM_BITS-1) ) xor Cx_int(20);
Cx_int(22) <= ( Ax(22) and Bx_int(NUM_BITS-1) ) xor Cx_int(21);
Cx_int(23) <= ( Ax(23) and Bx_int(NUM_BITS-1) ) xor Cx_int(22);
Cx_int(24) <= ( Ax(24) and Bx_int(NUM_BITS-1) ) xor Cx_int(23);
Cx_int(25) <= ( Ax(25) and Bx_int(NUM_BITS-1) ) xor Cx_int(24);
Cx_int(26) <= ( Ax(26) and Bx_int(NUM_BITS-1) ) xor Cx_int(25);
Cx_int(27) <= ( Ax(27) and Bx_int(NUM_BITS-1) ) xor Cx_int(26);
Cx_int(28) <= ( Ax(28) and Bx_int(NUM_BITS-1) ) xor Cx_int(27);
Cx_int(29) <= ( Ax(29) and Bx_int(NUM_BITS-1) ) xor Cx_int(28);
Cx_int(30) <= ( Ax(30) and Bx_int(NUM_BITS-1) ) xor Cx_int(29);
Cx_int(31) <= ( Ax(31) and Bx_int(NUM_BITS-1) ) xor Cx_int(30);
Cx_int(32) <= ( Ax(32) and Bx_int(NUM_BITS-1) ) xor Cx_int(31);
Cx_int(33) <= ( Ax(33) and Bx_int(NUM_BITS-1) ) xor Cx_int(32);
Cx_int(34) <= ( Ax(34) and Bx_int(NUM_BITS-1) ) xor Cx_int(33);
Cx_int(35) <= ( Ax(35) and Bx_int(NUM_BITS-1) ) xor Cx_int(34);
Cx_int(36) <= ( Ax(36) and Bx_int(NUM_BITS-1) ) xor Cx_int(35);
Cx_int(37) <= ( Ax(37) and Bx_int(NUM_BITS-1) ) xor Cx_int(36);
Cx_int(38) <= ( Ax(38) and Bx_int(NUM_BITS-1) ) xor Cx_int(37);
Cx_int(39) <= ( Ax(39) and Bx_int(NUM_BITS-1) ) xor Cx_int(38);
Cx_int(40) <= ( Ax(40) and Bx_int(NUM_BITS-1) ) xor Cx_int(39);
Cx_int(41) <= ( Ax(41) and Bx_int(NUM_BITS-1) ) xor Cx_int(40);
Cx_int(42) <= ( Ax(42) and Bx_int(NUM_BITS-1) ) xor Cx_int(41);
Cx_int(43) <= ( Ax(43) and Bx_int(NUM_BITS-1) ) xor Cx_int(42);
Cx_int(44) <= ( Ax(44) and Bx_int(NUM_BITS-1) ) xor Cx_int(43);
Cx_int(45) <= ( Ax(45) and Bx_int(NUM_BITS-1) ) xor Cx_int(44);
Cx_int(46) <= ( Ax(46) and Bx_int(NUM_BITS-1) ) xor Cx_int(45);
Cx_int(47) <= ( Ax(47) and Bx_int(NUM_BITS-1) ) xor Cx_int(46);
Cx_int(48) <= ( Ax(48) and Bx_int(NUM_BITS-1) ) xor Cx_int(47);
Cx_int(49) <= ( Ax(49) and Bx_int(NUM_BITS-1) ) xor Cx_int(48);
Cx_int(50) <= ( Ax(50) and Bx_int(NUM_BITS-1) ) xor Cx_int(49);
Cx_int(51) <= ( Ax(51) and Bx_int(NUM_BITS-1) ) xor Cx_int(50);
Cx_int(52) <= ( Ax(52) and Bx_int(NUM_BITS-1) ) xor Cx_int(51);
Cx_int(53) <= ( Ax(53) and Bx_int(NUM_BITS-1) ) xor Cx_int(52);
Cx_int(54) <= ( Ax(54) and Bx_int(NUM_BITS-1) ) xor Cx_int(53);
Cx_int(55) <= ( Ax(55) and Bx_int(NUM_BITS-1) ) xor Cx_int(54);
Cx_int(56) <= ( Ax(56) and Bx_int(NUM_BITS-1) ) xor Cx_int(55);
Cx_int(57) <= ( Ax(57) and Bx_int(NUM_BITS-1) ) xor Cx_int(56);
Cx_int(58) <= ( Ax(58) and Bx_int(NUM_BITS-1) ) xor Cx_int(57);
Cx_int(59) <= ( Ax(59) and Bx_int(NUM_BITS-1) ) xor Cx_int(58);
Cx_int(60) <= ( Ax(60) and Bx_int(NUM_BITS-1) ) xor Cx_int(59);
Cx_int(61) <= ( Ax(61) and Bx_int(NUM_BITS-1) ) xor Cx_int(60);
Cx_int(62) <= ( Ax(62) and Bx_int(NUM_BITS-1) ) xor Cx_int(61);
Cx_int(63) <= ( Ax(63) and Bx_int(NUM_BITS-1) ) xor Cx_int(62);
Cx_int(64) <= ( Ax(64) and Bx_int(NUM_BITS-1) ) xor Cx_int(63);
Cx_int(65) <= ( Ax(65) and Bx_int(NUM_BITS-1) ) xor Cx_int(64);
Cx_int(66) <= ( Ax(66) and Bx_int(NUM_BITS-1) ) xor Cx_int(65);
Cx_int(67) <= ( Ax(67) and Bx_int(NUM_BITS-1) ) xor Cx_int(66);
Cx_int(68) <= ( Ax(68) and Bx_int(NUM_BITS-1) ) xor Cx_int(67);
Cx_int(69) <= ( Ax(69) and Bx_int(NUM_BITS-1) ) xor Cx_int(68);
Cx_int(70) <= ( Ax(70) and Bx_int(NUM_BITS-1) ) xor Cx_int(69);
Cx_int(71) <= ( Ax(71) and Bx_int(NUM_BITS-1) ) xor Cx_int(70);
Cx_int(72) <= ( Ax(72) and Bx_int(NUM_BITS-1) ) xor Cx_int(71);
Cx_int(73) <= ( Ax(73) and Bx_int(NUM_BITS-1) ) xor Cx_int(72);
Cx_int(74) <= ( Ax(74) and Bx_int(NUM_BITS-1) ) xor Cx_int(73);
Cx_int(75) <= ( Ax(75) and Bx_int(NUM_BITS-1) ) xor Cx_int(74);
Cx_int(76) <= ( Ax(76) and Bx_int(NUM_BITS-1) ) xor Cx_int(75);
Cx_int(77) <= ( Ax(77) and Bx_int(NUM_BITS-1) ) xor Cx_int(76);
Cx_int(78) <= ( Ax(78) and Bx_int(NUM_BITS-1) ) xor Cx_int(77);
Cx_int(79) <= ( Ax(79) and Bx_int(NUM_BITS-1) ) xor Cx_int(78);
Cx_int(80) <= ( Ax(80) and Bx_int(NUM_BITS-1) ) xor Cx_int(79);
Cx_int(81) <= ( Ax(81) and Bx_int(NUM_BITS-1) ) xor Cx_int(80);
Cx_int(82) <= ( Ax(82) and Bx_int(NUM_BITS-1) ) xor Cx_int(81);
Cx_int(83) <= ( Ax(83) and Bx_int(NUM_BITS-1) ) xor Cx_int(82);
Cx_int(84) <= ( Ax(84) and Bx_int(NUM_BITS-1) ) xor Cx_int(83);
Cx_int(85) <= ( Ax(85) and Bx_int(NUM_BITS-1) ) xor Cx_int(84);
Cx_int(86) <= ( Ax(86) and Bx_int(NUM_BITS-1) ) xor Cx_int(85);
Cx_int(87) <= ( Ax(87) and Bx_int(NUM_BITS-1) ) xor Cx_int(86);
Cx_int(88) <= ( Ax(88) and Bx_int(NUM_BITS-1) ) xor Cx_int(87);
Cx_int(89) <= ( Ax(89) and Bx_int(NUM_BITS-1) ) xor Cx_int(88);
Cx_int(90) <= ( Ax(90) and Bx_int(NUM_BITS-1) ) xor Cx_int(89);
Cx_int(91) <= ( Ax(91) and Bx_int(NUM_BITS-1) ) xor Cx_int(90);
Cx_int(92) <= ( Ax(92) and Bx_int(NUM_BITS-1) ) xor Cx_int(91);
Cx_int(93) <= ( Ax(93) and Bx_int(NUM_BITS-1) ) xor Cx_int(92);
Cx_int(94) <= ( Ax(94) and Bx_int(NUM_BITS-1) ) xor Cx_int(93);
Cx_int(95) <= ( Ax(95) and Bx_int(NUM_BITS-1) ) xor Cx_int(94);
Cx_int(96) <= ( Ax(96) and Bx_int(NUM_BITS-1) ) xor Cx_int(95);
Cx_int(97) <= ( Ax(97) and Bx_int(NUM_BITS-1) ) xor Cx_int(96);
Cx_int(98) <= ( Ax(98) and Bx_int(NUM_BITS-1) ) xor Cx_int(97);
Cx_int(99) <= ( Ax(99) and Bx_int(NUM_BITS-1) ) xor Cx_int(98);
Cx_int(100) <= ( Ax(100) and Bx_int(NUM_BITS-1) ) xor Cx_int(99);
Cx_int(101) <= ( Ax(101) and Bx_int(NUM_BITS-1) ) xor Cx_int(100);
Cx_int(102) <= ( Ax(102) and Bx_int(NUM_BITS-1) ) xor Cx_int(101);
Cx_int(103) <= ( Ax(103) and Bx_int(NUM_BITS-1) ) xor Cx_int(102);
Cx_int(104) <= ( Ax(104) and Bx_int(NUM_BITS-1) ) xor Cx_int(103);
Cx_int(105) <= ( Ax(105) and Bx_int(NUM_BITS-1) ) xor Cx_int(104);
Cx_int(106) <= ( Ax(106) and Bx_int(NUM_BITS-1) ) xor Cx_int(105);
Cx_int(107) <= ( Ax(107) and Bx_int(NUM_BITS-1) ) xor Cx_int(106);
Cx_int(108) <= ( Ax(108) and Bx_int(NUM_BITS-1) ) xor Cx_int(107);
Cx_int(109) <= ( Ax(109) and Bx_int(NUM_BITS-1) ) xor Cx_int(108);
Cx_int(110) <= ( Ax(110) and Bx_int(NUM_BITS-1) ) xor Cx_int(109);
Cx_int(111) <= ( Ax(111) and Bx_int(NUM_BITS-1) ) xor Cx_int(110);
Cx_int(112) <= ( Ax(112) and Bx_int(NUM_BITS-1) ) xor Cx_int(111);
end if;
if counter = "01110000" then
done_int <= '1';
end if;
end if;
end if;
end process;
SHIFT_REGISTER: process (CLK)
Begin
if CLK'event and CLK = '1' then
if Reset = '1' then
Bx_shift <= Bx;
else
Bx_shift <= Bx_shift(NUM_BITS-2 downto 0) & '0'; -- carga paralela
end if;
end if;
end process;
end behave;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcilib
-- File: pcilib.vhd
-- Author: Alf Vaerneus - Gaisler Research
-- Description: Package with type declarations for PCI registers & constants
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
package pcilib is
constant zero : std_logic_vector(31 downto 0) := (others => '0');
constant addzero : std_logic_vector(31 downto 0) := (others => '0');
subtype word4 is std_logic_vector(3 downto 0);
subtype word32 is std_logic_vector(31 downto 0);
-- Constants for PCI commands
constant pci_memory_read : word4 := "0110";
constant pci_memory_write : word4 := "0111";
constant pci_config_read : word4 := "1010";
constant pci_config_write : word4 := "1011";
constant INT_ACK : word4 := "0000";
constant SPEC_CYCLE : word4 := "0001";
constant IO_READ : word4 := "0010";
constant IO_WRITE : word4 := "0011";
constant MEM_READ : word4 := "0110";
constant MEM_WRITE : word4 := "0111";
constant CONF_READ : word4 := "1010";
constant CONF_WRITE : word4 := "1011";
constant MEM_R_MULT : word4 := "1100";
constant DAC : word4 := "1101";
constant MEM_R_LINE : word4 := "1110";
constant MEM_W_INV : word4 := "1111";
-- Constants for word size
constant W_SIZE_8_n : word4 := "1110"; -- word size active low
constant W_SIZE_16_n : word4 := "1100";
constant W_SIZE_32_n : word4 := "0000";
type pci_config_command_type is record
-- ioen : std_logic; -- I/O access enable
men : std_logic; -- Memory access enable
msen : std_logic; -- Master enable
-- spcen : std_logic; -- Special cycle enable
mwie : std_logic; -- Memory write and invalidate enable
-- vgaps : std_logic; -- VGA palette snooping enable
per : std_logic; -- Parity error response enable
-- wcc : std_logic; -- Address stepping enable
-- serre : std_logic; -- Enable SERR# driver
-- fbtbe : std_logic; -- Fast back-to-back enable
end record;
type pci_config_status_type is record
-- c66mhz : std_logic; -- 66MHz capability
-- udf : std_logic; -- UDF supported
-- fbtbc : std_logic; -- Fast back-to-back capability
dped : std_logic; -- Data parity error detected
-- dst : std_logic_vector(1 downto 0); -- DEVSEL timing
sta : std_logic; -- Signaled target abort
rta : std_logic; -- Received target abort
rma : std_logic; -- Received master abort
-- sse : std_logic; -- Signaled system error
dpe : std_logic; -- Detected parity error
end record;
--type pci_config_type is record
-- conf_en : std_logic;
-- bus : std_logic_vector(7 downto 0);
-- dev : std_logic_vector(4 downto 0);
-- func : std_logic_vector(2 downto 0);
-- reg : std_logic_vector(5 downto 0);
-- data : std_logic_vector(31 downto 0);
--end record;
type pci_sigs_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic; -- Master frame
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
req : std_logic; -- Master bus request
perr : std_logic; -- Parity Error
oe_par : std_logic;
oe_ad : std_logic;
oe_ctrl : std_logic;
oe_cbe : std_logic;
oe_frame : std_logic;
oe_irdy : std_logic;
oe_req : std_logic;
oe_perr : std_logic;
end record;
end ;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pcilib
-- File: pcilib.vhd
-- Author: Alf Vaerneus - Gaisler Research
-- Description: Package with type declarations for PCI registers & constants
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
package pcilib is
constant zero : std_logic_vector(31 downto 0) := (others => '0');
constant addzero : std_logic_vector(31 downto 0) := (others => '0');
subtype word4 is std_logic_vector(3 downto 0);
subtype word32 is std_logic_vector(31 downto 0);
-- Constants for PCI commands
constant pci_memory_read : word4 := "0110";
constant pci_memory_write : word4 := "0111";
constant pci_config_read : word4 := "1010";
constant pci_config_write : word4 := "1011";
constant INT_ACK : word4 := "0000";
constant SPEC_CYCLE : word4 := "0001";
constant IO_READ : word4 := "0010";
constant IO_WRITE : word4 := "0011";
constant MEM_READ : word4 := "0110";
constant MEM_WRITE : word4 := "0111";
constant CONF_READ : word4 := "1010";
constant CONF_WRITE : word4 := "1011";
constant MEM_R_MULT : word4 := "1100";
constant DAC : word4 := "1101";
constant MEM_R_LINE : word4 := "1110";
constant MEM_W_INV : word4 := "1111";
-- Constants for word size
constant W_SIZE_8_n : word4 := "1110"; -- word size active low
constant W_SIZE_16_n : word4 := "1100";
constant W_SIZE_32_n : word4 := "0000";
type pci_config_command_type is record
-- ioen : std_logic; -- I/O access enable
men : std_logic; -- Memory access enable
msen : std_logic; -- Master enable
-- spcen : std_logic; -- Special cycle enable
mwie : std_logic; -- Memory write and invalidate enable
-- vgaps : std_logic; -- VGA palette snooping enable
per : std_logic; -- Parity error response enable
-- wcc : std_logic; -- Address stepping enable
-- serre : std_logic; -- Enable SERR# driver
-- fbtbe : std_logic; -- Fast back-to-back enable
end record;
type pci_config_status_type is record
-- c66mhz : std_logic; -- 66MHz capability
-- udf : std_logic; -- UDF supported
-- fbtbc : std_logic; -- Fast back-to-back capability
dped : std_logic; -- Data parity error detected
-- dst : std_logic_vector(1 downto 0); -- DEVSEL timing
sta : std_logic; -- Signaled target abort
rta : std_logic; -- Received target abort
rma : std_logic; -- Received master abort
-- sse : std_logic; -- Signaled system error
dpe : std_logic; -- Detected parity error
end record;
--type pci_config_type is record
-- conf_en : std_logic;
-- bus : std_logic_vector(7 downto 0);
-- dev : std_logic_vector(4 downto 0);
-- func : std_logic_vector(2 downto 0);
-- reg : std_logic_vector(5 downto 0);
-- data : std_logic_vector(31 downto 0);
--end record;
type pci_sigs_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic; -- Master frame
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
req : std_logic; -- Master bus request
perr : std_logic; -- Parity Error
oe_par : std_logic;
oe_ad : std_logic;
oe_ctrl : std_logic;
oe_cbe : std_logic;
oe_frame : std_logic;
oe_irdy : std_logic;
oe_req : std_logic;
oe_perr : std_logic;
end record;
end ;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
entity shift_register_serial_in is
generic (
REG_WIDTH: integer := 8
);
port (
clk, reset : in std_logic;
shift: in std_logic;
data_in_serial: in std_logic;
data_out_parallel: out std_logic_vector(REG_WIDTH-1 downto 0);
data_out_serial: out std_logic
);
end;
architecture behavior of shift_register_serial_in is
signal shift_register_mem_out : std_logic_vector(REG_WIDTH-1 downto 0);
begin
process (clk, reset)
begin
if reset = '0' then
shift_register_mem_out <= (others => '0');
elsif clk'event and clk = '1' then
if shift = '1' then
shift_register_mem_out <= shift_register_mem_out (REG_WIDTH-2 downto 0) & data_in_serial;
end if;
end if;
end process;
data_out_parallel <= shift_register_mem_out;
data_out_serial <= shift_register_mem_out (REG_WIDTH-2);
end; |
-- $Id: rb_sres_or_2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2010 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rb_sres_or_2 - syn
-- Description: rbus result or, 2 input
--
-- Dependencies: rb_sres_or_mon [sim only]
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.1-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-12-04 343 1.1.1 use now rb_sres_or_mon
-- 2010-06-26 309 1.1 add rritb_sres_or_mon
-- 2008-08-22 161 1.0.1 renamed rri_rbres_ -> rb_sres_
-- 2008-01-20 113 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.rblib.all;
-- ----------------------------------------------------------------------------
entity rb_sres_or_2 is -- rbus result or, 2 input
port (
RB_SRES_1 : in rb_sres_type; -- rb_sres input 1
RB_SRES_2 : in rb_sres_type := rb_sres_init; -- rb_sres input 2
RB_SRES_OR : out rb_sres_type -- rb_sres or'ed output
);
end rb_sres_or_2;
architecture syn of rb_sres_or_2 is
begin
proc_comb : process (RB_SRES_1, RB_SRES_2)
begin
RB_SRES_OR.ack <= RB_SRES_1.ack or
RB_SRES_2.ack;
RB_SRES_OR.busy <= RB_SRES_1.busy or
RB_SRES_2.busy;
RB_SRES_OR.err <= RB_SRES_1.err or
RB_SRES_2.err;
RB_SRES_OR.dout <= RB_SRES_1.dout or
RB_SRES_2.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : rb_sres_or_mon
port map (
RB_SRES_1 => RB_SRES_1,
RB_SRES_2 => RB_SRES_2,
RB_SRES_3 => rb_sres_init,
RB_SRES_4 => rb_sres_init
);
-- synthesis translate_on
end syn;
|
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`protect version = 1
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|
`protect begin_protected
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|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_comps_info_h_samp_factor is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end p_jinfo_comps_info_h_samp_factor;
architecture augh of p_jinfo_comps_info_h_samp_factor is
-- Embedded RAM
type ram_type is array (0 to 2) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-');
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_comps_info_h_samp_factor is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
wa0_en : in std_logic
);
end p_jinfo_comps_info_h_samp_factor;
architecture augh of p_jinfo_comps_info_h_samp_factor is
-- Embedded RAM
type ram_type is array (0 to 2) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else (others => '-');
end architecture;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 26-02-2017
-- Module Name: mux.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mux is
port (sel : in std_logic_vector(1 downto 0);
i : in std_logic_vector(3 downto 0);
o : out std_logic);
end entity mux;
architecture beh_arch_mux of mux is
begin
with sel select
o <= i(0) when "00",
i(1) when "01",
i(2) when "10",
i(3) when "11",
'X' when others;
end architecture beh_arch_mux;
architecture seq_arch_mux of mux is
begin
process (sel)
begin
if sel = "00" then
o <= i(0);
elsif sel = "01" then
o <= i(1);
elsif sel = "10" then
o <= i(2);
elsif sel = "11" then
o <= i(3);
end if;
end process
end architecture seq_arch_mux;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reu_pkg is
constant c_status : unsigned(4 downto 0) := '0' & X"0";
constant c_command : unsigned(4 downto 0) := '0' & X"1";
constant c_c64base_l : unsigned(4 downto 0) := '0' & X"2";
constant c_c64base_h : unsigned(4 downto 0) := '0' & X"3";
constant c_reubase_l : unsigned(4 downto 0) := '0' & X"4";
constant c_reubase_m : unsigned(4 downto 0) := '0' & X"5";
constant c_reubase_h : unsigned(4 downto 0) := '0' & X"6";
constant c_translen_l : unsigned(4 downto 0) := '0' & X"7";
constant c_translen_h : unsigned(4 downto 0) := '0' & X"8";
constant c_irqmask : unsigned(4 downto 0) := '0' & X"9";
constant c_control : unsigned(4 downto 0) := '0' & X"A";
-- extended registers
constant c_size_read : unsigned(4 downto 0) := '0' & X"C";
constant c_start_delay: unsigned(4 downto 0) := '0' & X"D";
constant c_rate_div : unsigned(4 downto 0) := '0' & X"E";
constant c_translen_x : unsigned(4 downto 0) := '0' & X"F";
constant c_mode_toreu : std_logic_vector(1 downto 0) := "00";
constant c_mode_toc64 : std_logic_vector(1 downto 0) := "01";
constant c_mode_swap : std_logic_vector(1 downto 0) := "10";
constant c_mode_verify : std_logic_vector(1 downto 0) := "11";
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reu_pkg is
constant c_status : unsigned(4 downto 0) := '0' & X"0";
constant c_command : unsigned(4 downto 0) := '0' & X"1";
constant c_c64base_l : unsigned(4 downto 0) := '0' & X"2";
constant c_c64base_h : unsigned(4 downto 0) := '0' & X"3";
constant c_reubase_l : unsigned(4 downto 0) := '0' & X"4";
constant c_reubase_m : unsigned(4 downto 0) := '0' & X"5";
constant c_reubase_h : unsigned(4 downto 0) := '0' & X"6";
constant c_translen_l : unsigned(4 downto 0) := '0' & X"7";
constant c_translen_h : unsigned(4 downto 0) := '0' & X"8";
constant c_irqmask : unsigned(4 downto 0) := '0' & X"9";
constant c_control : unsigned(4 downto 0) := '0' & X"A";
-- extended registers
constant c_size_read : unsigned(4 downto 0) := '0' & X"C";
constant c_start_delay: unsigned(4 downto 0) := '0' & X"D";
constant c_rate_div : unsigned(4 downto 0) := '0' & X"E";
constant c_translen_x : unsigned(4 downto 0) := '0' & X"F";
constant c_mode_toreu : std_logic_vector(1 downto 0) := "00";
constant c_mode_toc64 : std_logic_vector(1 downto 0) := "01";
constant c_mode_swap : std_logic_vector(1 downto 0) := "10";
constant c_mode_verify : std_logic_vector(1 downto 0) := "11";
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reu_pkg is
constant c_status : unsigned(4 downto 0) := '0' & X"0";
constant c_command : unsigned(4 downto 0) := '0' & X"1";
constant c_c64base_l : unsigned(4 downto 0) := '0' & X"2";
constant c_c64base_h : unsigned(4 downto 0) := '0' & X"3";
constant c_reubase_l : unsigned(4 downto 0) := '0' & X"4";
constant c_reubase_m : unsigned(4 downto 0) := '0' & X"5";
constant c_reubase_h : unsigned(4 downto 0) := '0' & X"6";
constant c_translen_l : unsigned(4 downto 0) := '0' & X"7";
constant c_translen_h : unsigned(4 downto 0) := '0' & X"8";
constant c_irqmask : unsigned(4 downto 0) := '0' & X"9";
constant c_control : unsigned(4 downto 0) := '0' & X"A";
-- extended registers
constant c_size_read : unsigned(4 downto 0) := '0' & X"C";
constant c_start_delay: unsigned(4 downto 0) := '0' & X"D";
constant c_rate_div : unsigned(4 downto 0) := '0' & X"E";
constant c_translen_x : unsigned(4 downto 0) := '0' & X"F";
constant c_mode_toreu : std_logic_vector(1 downto 0) := "00";
constant c_mode_toc64 : std_logic_vector(1 downto 0) := "01";
constant c_mode_swap : std_logic_vector(1 downto 0) := "10";
constant c_mode_verify : std_logic_vector(1 downto 0) := "11";
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reu_pkg is
constant c_status : unsigned(4 downto 0) := '0' & X"0";
constant c_command : unsigned(4 downto 0) := '0' & X"1";
constant c_c64base_l : unsigned(4 downto 0) := '0' & X"2";
constant c_c64base_h : unsigned(4 downto 0) := '0' & X"3";
constant c_reubase_l : unsigned(4 downto 0) := '0' & X"4";
constant c_reubase_m : unsigned(4 downto 0) := '0' & X"5";
constant c_reubase_h : unsigned(4 downto 0) := '0' & X"6";
constant c_translen_l : unsigned(4 downto 0) := '0' & X"7";
constant c_translen_h : unsigned(4 downto 0) := '0' & X"8";
constant c_irqmask : unsigned(4 downto 0) := '0' & X"9";
constant c_control : unsigned(4 downto 0) := '0' & X"A";
-- extended registers
constant c_size_read : unsigned(4 downto 0) := '0' & X"C";
constant c_start_delay: unsigned(4 downto 0) := '0' & X"D";
constant c_rate_div : unsigned(4 downto 0) := '0' & X"E";
constant c_translen_x : unsigned(4 downto 0) := '0' & X"F";
constant c_mode_toreu : std_logic_vector(1 downto 0) := "00";
constant c_mode_toc64 : std_logic_vector(1 downto 0) := "01";
constant c_mode_swap : std_logic_vector(1 downto 0) := "10";
constant c_mode_verify : std_logic_vector(1 downto 0) := "11";
end;
|
architecture RTL of FIFO is
procedure proc1 is begin end PROCEDURE proc1;
PROCEDURE PROC1 IS BEGIN END PROCEDURE PROC1;
begin
end architecture RTL;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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3Dy9MpLHjhnDs7WyNjE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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i2+F51e0QoKxbiQA47/h0urJkMupwRu3Fxnoiw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10080)
`protect data_block
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:20:51 08/06/2012
-- Design Name:
-- Module Name: iis_ser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity iis_ser is
Port ( CLK_100MHZ : in STD_LOGIC; --gbuf clock
SCLK : in STD_LOGIC; --logic (not used as clk)
LRCLK : in STD_LOGIC; --logic (not used as clk)
SDATA : out STD_LOGIC;
EN : in STD_LOGIC;
LDATA : in STD_LOGIC_VECTOR (23 downto 0);
RDATA : in STD_LOGIC_VECTOR (23 downto 0));
end iis_ser;
architecture Behavioral of iis_ser is
--bit cntr counts to 25 (not 24) so that it can set sdata to zero after
--the 24th bit has been sent to the receiver
constant bit_cntr_max : std_logic_vector(4 downto 0) := "11001";--25
type IIS_STATE_TYPE is (RESET, WAIT_LEFT, WRITE_LEFT, WAIT_RIGHT, WRITE_RIGHT);
signal start_left : std_logic;
signal start_right : std_logic;
signal write_bit : std_logic;
signal sclk_d1 : std_logic := '0';
signal lrclk_d1 : std_logic := '0';
signal bit_cntr : std_logic_vector(4 downto 0) := (others => '0');
signal ldata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal rdata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal sdata_reg : std_logic := '0';
signal iis_state : IIS_STATE_TYPE := RESET;
begin
process(CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
sclk_d1 <= SCLK;
lrclk_d1 <= LRCLK;
end if;
end process;
--Detect falling edge on LRCLK
start_left <= (lrclk_d1 and not(LRCLK));
--Detect rising edge on LRCLK
start_right <= (not(lrclk_d1) and LRCLK);
--Detect falling edge on SCLK
write_bit <= (sclk_d1 and not(SCLK));
--Next state logic
next_iis_state_process : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
case iis_state is
when RESET =>
if (EN = '1') then
iis_state <= WAIT_LEFT;
end if;
when WAIT_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_left = '1') then
iis_state <= WRITE_LEFT;
end if;
when WRITE_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_RIGHT;
end if;
when WAIT_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_right = '1') then
iis_state <= WRITE_RIGHT;
end if;
when WRITE_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_LEFT;
end if;
when others=> --should never be reached
iis_state <= RESET;
end case;
end if;
end process;
process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = WRITE_RIGHT or iis_state = WRITE_LEFT) then
if (write_bit = '1') then
bit_cntr <= bit_cntr + 1;
end if;
else
bit_cntr <= (others => '0');
end if;
end if;
end process;
data_shift_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
ldata_reg <= (others => '0');
rdata_reg <= (others => '0');
elsif ((iis_state = WAIT_LEFT) and (start_left = '1')) then
ldata_reg <= LDATA;
rdata_reg <= RDATA;
else
if (iis_state = WRITE_LEFT and write_bit = '1') then
ldata_reg(23 downto 1) <= ldata_reg(22 downto 0);
ldata_reg(0) <= '0';
end if;
if (iis_state = WRITE_RIGHT and write_bit = '1') then
rdata_reg(23 downto 1) <= rdata_reg(22 downto 0);
rdata_reg(0) <= '0';
end if;
end if;
end if;
end process data_shift_proc;
sdata_update_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
sdata_reg <= '0';
elsif (iis_state = WRITE_LEFT and write_bit = '1') then
sdata_reg <= ldata_reg(23);
elsif (iis_state = WRITE_RIGHT and write_bit = '1') then
sdata_reg <= rdata_reg(23);
end if;
end if;
end process sdata_update_proc;
SDATA <= sdata_reg;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:20:51 08/06/2012
-- Design Name:
-- Module Name: iis_ser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity iis_ser is
Port ( CLK_100MHZ : in STD_LOGIC; --gbuf clock
SCLK : in STD_LOGIC; --logic (not used as clk)
LRCLK : in STD_LOGIC; --logic (not used as clk)
SDATA : out STD_LOGIC;
EN : in STD_LOGIC;
LDATA : in STD_LOGIC_VECTOR (23 downto 0);
RDATA : in STD_LOGIC_VECTOR (23 downto 0));
end iis_ser;
architecture Behavioral of iis_ser is
--bit cntr counts to 25 (not 24) so that it can set sdata to zero after
--the 24th bit has been sent to the receiver
constant bit_cntr_max : std_logic_vector(4 downto 0) := "11001";--25
type IIS_STATE_TYPE is (RESET, WAIT_LEFT, WRITE_LEFT, WAIT_RIGHT, WRITE_RIGHT);
signal start_left : std_logic;
signal start_right : std_logic;
signal write_bit : std_logic;
signal sclk_d1 : std_logic := '0';
signal lrclk_d1 : std_logic := '0';
signal bit_cntr : std_logic_vector(4 downto 0) := (others => '0');
signal ldata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal rdata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal sdata_reg : std_logic := '0';
signal iis_state : IIS_STATE_TYPE := RESET;
begin
process(CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
sclk_d1 <= SCLK;
lrclk_d1 <= LRCLK;
end if;
end process;
--Detect falling edge on LRCLK
start_left <= (lrclk_d1 and not(LRCLK));
--Detect rising edge on LRCLK
start_right <= (not(lrclk_d1) and LRCLK);
--Detect falling edge on SCLK
write_bit <= (sclk_d1 and not(SCLK));
--Next state logic
next_iis_state_process : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
case iis_state is
when RESET =>
if (EN = '1') then
iis_state <= WAIT_LEFT;
end if;
when WAIT_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_left = '1') then
iis_state <= WRITE_LEFT;
end if;
when WRITE_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_RIGHT;
end if;
when WAIT_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_right = '1') then
iis_state <= WRITE_RIGHT;
end if;
when WRITE_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_LEFT;
end if;
when others=> --should never be reached
iis_state <= RESET;
end case;
end if;
end process;
process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = WRITE_RIGHT or iis_state = WRITE_LEFT) then
if (write_bit = '1') then
bit_cntr <= bit_cntr + 1;
end if;
else
bit_cntr <= (others => '0');
end if;
end if;
end process;
data_shift_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
ldata_reg <= (others => '0');
rdata_reg <= (others => '0');
elsif ((iis_state = WAIT_LEFT) and (start_left = '1')) then
ldata_reg <= LDATA;
rdata_reg <= RDATA;
else
if (iis_state = WRITE_LEFT and write_bit = '1') then
ldata_reg(23 downto 1) <= ldata_reg(22 downto 0);
ldata_reg(0) <= '0';
end if;
if (iis_state = WRITE_RIGHT and write_bit = '1') then
rdata_reg(23 downto 1) <= rdata_reg(22 downto 0);
rdata_reg(0) <= '0';
end if;
end if;
end if;
end process data_shift_proc;
sdata_update_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
sdata_reg <= '0';
elsif (iis_state = WRITE_LEFT and write_bit = '1') then
sdata_reg <= ldata_reg(23);
elsif (iis_state = WRITE_RIGHT and write_bit = '1') then
sdata_reg <= rdata_reg(23);
end if;
end if;
end process sdata_update_proc;
SDATA <= sdata_reg;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:20:51 08/06/2012
-- Design Name:
-- Module Name: iis_ser - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity iis_ser is
Port ( CLK_100MHZ : in STD_LOGIC; --gbuf clock
SCLK : in STD_LOGIC; --logic (not used as clk)
LRCLK : in STD_LOGIC; --logic (not used as clk)
SDATA : out STD_LOGIC;
EN : in STD_LOGIC;
LDATA : in STD_LOGIC_VECTOR (23 downto 0);
RDATA : in STD_LOGIC_VECTOR (23 downto 0));
end iis_ser;
architecture Behavioral of iis_ser is
--bit cntr counts to 25 (not 24) so that it can set sdata to zero after
--the 24th bit has been sent to the receiver
constant bit_cntr_max : std_logic_vector(4 downto 0) := "11001";--25
type IIS_STATE_TYPE is (RESET, WAIT_LEFT, WRITE_LEFT, WAIT_RIGHT, WRITE_RIGHT);
signal start_left : std_logic;
signal start_right : std_logic;
signal write_bit : std_logic;
signal sclk_d1 : std_logic := '0';
signal lrclk_d1 : std_logic := '0';
signal bit_cntr : std_logic_vector(4 downto 0) := (others => '0');
signal ldata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal rdata_reg : std_logic_vector(23 downto 0) := (others => '0');
signal sdata_reg : std_logic := '0';
signal iis_state : IIS_STATE_TYPE := RESET;
begin
process(CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
sclk_d1 <= SCLK;
lrclk_d1 <= LRCLK;
end if;
end process;
--Detect falling edge on LRCLK
start_left <= (lrclk_d1 and not(LRCLK));
--Detect rising edge on LRCLK
start_right <= (not(lrclk_d1) and LRCLK);
--Detect falling edge on SCLK
write_bit <= (sclk_d1 and not(SCLK));
--Next state logic
next_iis_state_process : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
case iis_state is
when RESET =>
if (EN = '1') then
iis_state <= WAIT_LEFT;
end if;
when WAIT_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_left = '1') then
iis_state <= WRITE_LEFT;
end if;
when WRITE_LEFT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_RIGHT;
end if;
when WAIT_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (start_right = '1') then
iis_state <= WRITE_RIGHT;
end if;
when WRITE_RIGHT =>
if (EN = '0') then
iis_state <= RESET;
elsif (bit_cntr = bit_cntr_max) then
iis_state <= WAIT_LEFT;
end if;
when others=> --should never be reached
iis_state <= RESET;
end case;
end if;
end process;
process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = WRITE_RIGHT or iis_state = WRITE_LEFT) then
if (write_bit = '1') then
bit_cntr <= bit_cntr + 1;
end if;
else
bit_cntr <= (others => '0');
end if;
end if;
end process;
data_shift_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
ldata_reg <= (others => '0');
rdata_reg <= (others => '0');
elsif ((iis_state = WAIT_LEFT) and (start_left = '1')) then
ldata_reg <= LDATA;
rdata_reg <= RDATA;
else
if (iis_state = WRITE_LEFT and write_bit = '1') then
ldata_reg(23 downto 1) <= ldata_reg(22 downto 0);
ldata_reg(0) <= '0';
end if;
if (iis_state = WRITE_RIGHT and write_bit = '1') then
rdata_reg(23 downto 1) <= rdata_reg(22 downto 0);
rdata_reg(0) <= '0';
end if;
end if;
end if;
end process data_shift_proc;
sdata_update_proc : process (CLK_100MHZ)
begin
if (rising_edge(CLK_100MHZ)) then
if (iis_state = RESET) then
sdata_reg <= '0';
elsif (iis_state = WRITE_LEFT and write_bit = '1') then
sdata_reg <= ldata_reg(23);
elsif (iis_state = WRITE_RIGHT and write_bit = '1') then
sdata_reg <= rdata_reg(23);
end if;
end if;
end process sdata_update_proc;
SDATA <= sdata_reg;
end Behavioral;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 157776)
`protect data_block
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`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 157776)
`protect data_block
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|
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 157776)
`protect data_block
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|
`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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|
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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|
------------------------------------------------------------------------------
---- ----
---- ZPU Small ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the small size version. ----
---- It doesn't support external memories, needs a dual ported memory. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUSmallCore(Behave) (Entity and architecture) ----
---- File name: zpu_small.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.zpupkg.all;
entity ZPUSmallCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (text, data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(WORD_SIZE-1 downto 0);
data_o : out unsigned(WORD_SIZE-1 downto 0);
addr_o : out unsigned(ADDR_W-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity ZPUSmallCore;
architecture Behave of ZPUSmallCore is
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=
SP_START_1(MAX_ADDR_BIT downto BYTE_BITS);
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(MAX_ADDR_BIT downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
-- We also use the B port to fetch instructions.
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_io, st_write_io, st_fetch_next,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(MEM_W-1 downto BYTE_BITS);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(MEM_W-1 downto BYTE_BITS);
b_o <= b_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use Port B memory to fetch the opcodes.
decode_control:
process(b_i, pc_r)
variable topcode : unsigned(c_opcode_width-1 downto 0);
begin
-- Select the addressed byte inside the fetched word
case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is
when 0 =>
topcode:=b_i(31 downto 24);
when 1 =>
topcode:=b_i(23 downto 16);
when 2 =>
topcode:=b_i(15 downto 8);
when others => -- 3
topcode:=b_i(7 downto 0);
end case;
opcode <= topcode;
if (topcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (topcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (topcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (topcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (topcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
dbg_o.b_inst <= '0';
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
a_r <= (others => D_CARE_VAL);
b_r <= (others => D_CARE_VAL);
sp_offset:=(others => D_CARE_VAL);
a_addr_r <= (others => D_CARE_VAL);
b_addr_r <= (others => D_CARE_VAL);
addr_r <= a_i(ADDR_W-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(MAX_ADDR_BIT downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32,MAX_ADDR_BIT+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),WORD_SIZE));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(WORD_SIZE-1 downto 7) <= a_i(WORD_SIZE-8 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(31) <= '1'; -- for easy comparison with my own version of ZPU
a_r(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(MAX_ADDR_BIT downto 0);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
if a_i(IO_BIT)='1' then
addr_r <= a_i(ADDR_W-1 downto 0);
read_en_o <= '1';
state <= st_read_io;
else
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_i(WORD_SIZE-1-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
b_addr_r <= sp_r+1;
sp_r <= sp_r+1;
if a_i(IO_BIT)='1' then
state <= st_write_io;
else
state <= st_store;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_read_io =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
a_r <= data_i;
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(ADDR_W-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During the *next* cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute the cycle after
-- next
b_addr_r <= pc_r(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_fetch_next;
when st_fetch_next =>
-- At this point a_i contains the value that is either
-- from the top of stack or should be copied to the top of the stack
a_we_r <= '1';
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
a_r <= b_i;
state <= st_resync;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: ZPUSmallCore
|
------------------------------------------------------------------------------
---- ----
---- ZPU Small ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the small size version. ----
---- It doesn't support external memories, needs a dual ported memory. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUSmallCore(Behave) (Entity and architecture) ----
---- File name: zpu_small.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.zpupkg.all;
entity ZPUSmallCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (text, data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(WORD_SIZE-1 downto 0);
data_o : out unsigned(WORD_SIZE-1 downto 0);
addr_o : out unsigned(ADDR_W-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity ZPUSmallCore;
architecture Behave of ZPUSmallCore is
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=
SP_START_1(MAX_ADDR_BIT downto BYTE_BITS);
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(MAX_ADDR_BIT downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
-- We also use the B port to fetch instructions.
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_io, st_write_io, st_fetch_next,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(MEM_W-1 downto BYTE_BITS);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(MEM_W-1 downto BYTE_BITS);
b_o <= b_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use Port B memory to fetch the opcodes.
decode_control:
process(b_i, pc_r)
variable topcode : unsigned(c_opcode_width-1 downto 0);
begin
-- Select the addressed byte inside the fetched word
case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is
when 0 =>
topcode:=b_i(31 downto 24);
when 1 =>
topcode:=b_i(23 downto 16);
when 2 =>
topcode:=b_i(15 downto 8);
when others => -- 3
topcode:=b_i(7 downto 0);
end case;
opcode <= topcode;
if (topcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (topcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (topcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (topcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (topcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
dbg_o.b_inst <= '0';
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
a_r <= (others => D_CARE_VAL);
b_r <= (others => D_CARE_VAL);
sp_offset:=(others => D_CARE_VAL);
a_addr_r <= (others => D_CARE_VAL);
b_addr_r <= (others => D_CARE_VAL);
addr_r <= a_i(ADDR_W-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(MAX_ADDR_BIT downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32,MAX_ADDR_BIT+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),WORD_SIZE));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(WORD_SIZE-1 downto 7) <= a_i(WORD_SIZE-8 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(31) <= '1'; -- for easy comparison with my own version of ZPU
a_r(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(MAX_ADDR_BIT downto 0);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
if a_i(IO_BIT)='1' then
addr_r <= a_i(ADDR_W-1 downto 0);
read_en_o <= '1';
state <= st_read_io;
else
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_i(WORD_SIZE-1-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
b_addr_r <= sp_r+1;
sp_r <= sp_r+1;
if a_i(IO_BIT)='1' then
state <= st_write_io;
else
state <= st_store;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_read_io =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
a_r <= data_i;
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(ADDR_W-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During the *next* cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute the cycle after
-- next
b_addr_r <= pc_r(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_fetch_next;
when st_fetch_next =>
-- At this point a_i contains the value that is either
-- from the top of stack or should be copied to the top of the stack
a_we_r <= '1';
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
a_r <= b_i;
state <= st_resync;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: ZPUSmallCore
|
------------------------------------------------------------------------------
---- ----
---- ZPU Small ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the small size version. ----
---- It doesn't support external memories, needs a dual ported memory. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUSmallCore(Behave) (Entity and architecture) ----
---- File name: zpu_small.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.zpupkg.all;
entity ZPUSmallCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (text, data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(WORD_SIZE-1 downto 0);
data_o : out unsigned(WORD_SIZE-1 downto 0);
addr_o : out unsigned(ADDR_W-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity ZPUSmallCore;
architecture Behave of ZPUSmallCore is
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=
SP_START_1(MAX_ADDR_BIT downto BYTE_BITS);
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(MAX_ADDR_BIT downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
-- We also use the B port to fetch instructions.
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_io, st_write_io, st_fetch_next,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(MEM_W-1 downto BYTE_BITS);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(MEM_W-1 downto BYTE_BITS);
b_o <= b_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use Port B memory to fetch the opcodes.
decode_control:
process(b_i, pc_r)
variable topcode : unsigned(c_opcode_width-1 downto 0);
begin
-- Select the addressed byte inside the fetched word
case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is
when 0 =>
topcode:=b_i(31 downto 24);
when 1 =>
topcode:=b_i(23 downto 16);
when 2 =>
topcode:=b_i(15 downto 8);
when others => -- 3
topcode:=b_i(7 downto 0);
end case;
opcode <= topcode;
if (topcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (topcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (topcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (topcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (topcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
dbg_o.b_inst <= '0';
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
a_r <= (others => D_CARE_VAL);
b_r <= (others => D_CARE_VAL);
sp_offset:=(others => D_CARE_VAL);
a_addr_r <= (others => D_CARE_VAL);
b_addr_r <= (others => D_CARE_VAL);
addr_r <= a_i(ADDR_W-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(MAX_ADDR_BIT downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32,MAX_ADDR_BIT+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),WORD_SIZE));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(WORD_SIZE-1 downto 7) <= a_i(WORD_SIZE-8 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(31) <= '1'; -- for easy comparison with my own version of ZPU
a_r(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(MAX_ADDR_BIT downto 0);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
if a_i(IO_BIT)='1' then
addr_r <= a_i(ADDR_W-1 downto 0);
read_en_o <= '1';
state <= st_read_io;
else
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_i(WORD_SIZE-1-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
b_addr_r <= sp_r+1;
sp_r <= sp_r+1;
if a_i(IO_BIT)='1' then
state <= st_write_io;
else
state <= st_store;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_read_io =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
a_r <= data_i;
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(ADDR_W-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During the *next* cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute the cycle after
-- next
b_addr_r <= pc_r(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_fetch_next;
when st_fetch_next =>
-- At this point a_i contains the value that is either
-- from the top of stack or should be copied to the top of the stack
a_we_r <= '1';
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
a_r <= b_i;
state <= st_resync;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: ZPUSmallCore
|
------------------------------------------------------------------------------
---- ----
---- ZPU Small ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the small size version. ----
---- It doesn't support external memories, needs a dual ported memory. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUSmallCore(Behave) (Entity and architecture) ----
---- File name: zpu_small.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.zpupkg.all;
entity ZPUSmallCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (text, data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(WORD_SIZE-1 downto 0);
data_o : out unsigned(WORD_SIZE-1 downto 0);
addr_o : out unsigned(ADDR_W-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity ZPUSmallCore;
architecture Behave of ZPUSmallCore is
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=
SP_START_1(MAX_ADDR_BIT downto BYTE_BITS);
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(MAX_ADDR_BIT downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
-- We also use the B port to fetch instructions.
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_io, st_write_io, st_fetch_next,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(MEM_W-1 downto BYTE_BITS);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(MEM_W-1 downto BYTE_BITS);
b_o <= b_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use Port B memory to fetch the opcodes.
decode_control:
process(b_i, pc_r)
variable topcode : unsigned(c_opcode_width-1 downto 0);
begin
-- Select the addressed byte inside the fetched word
case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is
when 0 =>
topcode:=b_i(31 downto 24);
when 1 =>
topcode:=b_i(23 downto 16);
when 2 =>
topcode:=b_i(15 downto 8);
when others => -- 3
topcode:=b_i(7 downto 0);
end case;
opcode <= topcode;
if (topcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (topcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (topcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (topcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (topcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
dbg_o.b_inst <= '0';
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
a_r <= (others => D_CARE_VAL);
b_r <= (others => D_CARE_VAL);
sp_offset:=(others => D_CARE_VAL);
a_addr_r <= (others => D_CARE_VAL);
b_addr_r <= (others => D_CARE_VAL);
addr_r <= a_i(ADDR_W-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(MAX_ADDR_BIT downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32,MAX_ADDR_BIT+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),WORD_SIZE));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(WORD_SIZE-1 downto 7) <= a_i(WORD_SIZE-8 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(31) <= '1'; -- for easy comparison with my own version of ZPU
a_r(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(MAX_ADDR_BIT downto 0);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
if a_i(IO_BIT)='1' then
addr_r <= a_i(ADDR_W-1 downto 0);
read_en_o <= '1';
state <= st_read_io;
else
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_i(WORD_SIZE-1-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
b_addr_r <= sp_r+1;
sp_r <= sp_r+1;
if a_i(IO_BIT)='1' then
state <= st_write_io;
else
state <= st_store;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_read_io =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
a_r <= data_i;
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(ADDR_W-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During the *next* cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute the cycle after
-- next
b_addr_r <= pc_r(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_fetch_next;
when st_fetch_next =>
-- At this point a_i contains the value that is either
-- from the top of stack or should be copied to the top of the stack
a_we_r <= '1';
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
a_r <= b_i;
state <= st_resync;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: ZPUSmallCore
|
------------------------------------------------------------------------------
---- ----
---- ZPU Small ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the small size version. ----
---- It doesn't support external memories, needs a dual ported memory. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUSmallCore(Behave) (Entity and architecture) ----
---- File name: zpu_small.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.zpupkg.all;
entity ZPUSmallCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (text, data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(WORD_SIZE-1 downto 0);
data_o : out unsigned(WORD_SIZE-1 downto 0);
addr_o : out unsigned(ADDR_W-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity ZPUSmallCore;
architecture Behave of ZPUSmallCore is
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=
SP_START_1(MAX_ADDR_BIT downto BYTE_BITS);
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(MAX_ADDR_BIT downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
-- We also use the B port to fetch instructions.
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_io, st_write_io, st_fetch_next,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(MEM_W-1 downto BYTE_BITS);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(MEM_W-1 downto BYTE_BITS);
b_o <= b_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use Port B memory to fetch the opcodes.
decode_control:
process(b_i, pc_r)
variable topcode : unsigned(c_opcode_width-1 downto 0);
begin
-- Select the addressed byte inside the fetched word
case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is
when 0 =>
topcode:=b_i(31 downto 24);
when 1 =>
topcode:=b_i(23 downto 16);
when 2 =>
topcode:=b_i(15 downto 8);
when others => -- 3
topcode:=b_i(7 downto 0);
end case;
opcode <= topcode;
if (topcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (topcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (topcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (topcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (topcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
dbg_o.b_inst <= '0';
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
a_r <= (others => D_CARE_VAL);
b_r <= (others => D_CARE_VAL);
sp_offset:=(others => D_CARE_VAL);
a_addr_r <= (others => D_CARE_VAL);
b_addr_r <= (others => D_CARE_VAL);
addr_r <= a_i(ADDR_W-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(MAX_ADDR_BIT downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32,MAX_ADDR_BIT+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),WORD_SIZE));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(WORD_SIZE-1 downto 7) <= a_i(WORD_SIZE-8 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(31) <= '1'; -- for easy comparison with my own version of ZPU
a_r(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(MAX_ADDR_BIT downto 0);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
if a_i(IO_BIT)='1' then
addr_r <= a_i(ADDR_W-1 downto 0);
read_en_o <= '1';
state <= st_read_io;
else
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_i(WORD_SIZE-1-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
b_addr_r <= sp_r+1;
sp_r <= sp_r+1;
if a_i(IO_BIT)='1' then
state <= st_write_io;
else
state <= st_store;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_read_io =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
a_r <= data_i;
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(ADDR_W-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During the *next* cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute the cycle after
-- next
b_addr_r <= pc_r(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_fetch_next;
when st_fetch_next =>
-- At this point a_i contains the value that is either
-- from the top of stack or should be copied to the top of the stack
a_we_r <= '1';
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
a_r <= b_i;
state <= st_resync;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: ZPUSmallCore
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.3 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
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-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
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--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : virtex6
-- C_XDEVICEFAMILY : virtex6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 256
-- C_READ_WIDTH_A : 256
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 32768
-- C_READ_DEPTH_B : 32768
-- C_ADDRB_WIDTH : 15
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 1
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT RAM_WRITE_top IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : RAM_WRITE_top
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
-- This one is a slave interface, it provides Zynq PS with access to system registers
-- and filesystem buffers. Since PS have its own memory interface, no need to provide
-- access for DDR here.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ABus2AXI4Lite_Slave_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_SLAVE_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_SLAVE_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
-- registers
PCNTR : out std_logic_vector(15 downto 0);
STATUS : out std_logic_vector(15 downto 0);
MODE : in std_logic_vector(15 downto 0);
HWVER : in std_logic_vector(15 downto 0);
SWVER : out std_logic_vector(15 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
SLAVE_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
SLAVE_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
SLAVE_AXI_AWADDR : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
SLAVE_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
SLAVE_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
SLAVE_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
SLAVE_AXI_WDATA : in std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
SLAVE_AXI_WSTRB : in std_logic_vector((C_SLAVE_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
SLAVE_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
SLAVE_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
SLAVE_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
SLAVE_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
SLAVE_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
SLAVE_AXI_ARADDR : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
SLAVE_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
SLAVE_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
SLAVE_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
SLAVE_AXI_RDATA : out std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
SLAVE_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
SLAVE_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
SLAVE_AXI_RREADY : in std_logic
);
end ABus2AXI4Lite_Slave_AXI;
architecture arch_imp of ABus2AXI4Lite_Slave_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_SLAVE_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_SLAVE_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal slv_reg0 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
SLAVE_AXI_AWREADY <= axi_awready;
SLAVE_AXI_WREADY <= axi_wready;
SLAVE_AXI_BRESP <= axi_bresp;
SLAVE_AXI_BVALID <= axi_bvalid;
SLAVE_AXI_ARREADY <= axi_arready;
SLAVE_AXI_RDATA <= axi_rdata;
SLAVE_AXI_RRESP <= axi_rresp;
SLAVE_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and SLAVE_AXI_AWVALID = '1' and SLAVE_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and SLAVE_AXI_AWVALID = '1' and SLAVE_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= SLAVE_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and SLAVE_AXI_WVALID = '1' and SLAVE_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and SLAVE_AXI_WVALID and axi_awready and SLAVE_AXI_AWVALID ;
process (SLAVE_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and SLAVE_AXI_AWVALID = '1' and axi_wready = '1' and SLAVE_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (SLAVE_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and SLAVE_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= SLAVE_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and SLAVE_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and SLAVE_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and SLAVE_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, axi_araddr, SLAVE_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000" =>
reg_data_out <= slv_reg0;
when b"001" =>
reg_data_out <= HWVER & MODE;--slv_reg1;
when b"010" =>
reg_data_out <= slv_reg2;
-- when b"011" =>
-- reg_data_out <= slv_reg3;
-- when b"100" =>
-- reg_data_out <= slv_reg4;
-- when b"101" =>
-- reg_data_out <= slv_reg5;
-- when b"110" =>
-- reg_data_out <= slv_reg6;
-- when b"111" =>
-- reg_data_out <= slv_reg7;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( SLAVE_AXI_ACLK ) is
begin
if (rising_edge (SLAVE_AXI_ACLK)) then
if ( SLAVE_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
PCNTR <= slv_reg0(15 downto 0);
STATUS <= slv_reg0(31 downto 16);
--MODE : in std_logic_vector(15 downto 0);
--HWVER : in std_logic_vector(15 downto 0);
SWVER <= slv_reg2(15 downto 0);
-- User logic ends
end arch_imp;
|
-- This one is a slave interface, it provides Zynq PS with access to system registers
-- and filesystem buffers. Since PS have its own memory interface, no need to provide
-- access for DDR here.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ABus2AXI4Lite_Slave_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_SLAVE_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_SLAVE_AXI_ADDR_WIDTH : integer := 5
);
port (
-- Users to add ports here
-- registers
PCNTR : out std_logic_vector(15 downto 0);
STATUS : out std_logic_vector(15 downto 0);
MODE : in std_logic_vector(15 downto 0);
HWVER : in std_logic_vector(15 downto 0);
SWVER : out std_logic_vector(15 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
SLAVE_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
SLAVE_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
SLAVE_AXI_AWADDR : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
SLAVE_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
SLAVE_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
SLAVE_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
SLAVE_AXI_WDATA : in std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
SLAVE_AXI_WSTRB : in std_logic_vector((C_SLAVE_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
SLAVE_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
SLAVE_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
SLAVE_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
SLAVE_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
SLAVE_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
SLAVE_AXI_ARADDR : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
SLAVE_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
SLAVE_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
SLAVE_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
SLAVE_AXI_RDATA : out std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
SLAVE_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
SLAVE_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
SLAVE_AXI_RREADY : in std_logic
);
end ABus2AXI4Lite_Slave_AXI;
architecture arch_imp of ABus2AXI4Lite_Slave_AXI is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_SLAVE_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_SLAVE_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 2;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 8
signal slv_reg0 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg4 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg5 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg6 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg7 :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
SLAVE_AXI_AWREADY <= axi_awready;
SLAVE_AXI_WREADY <= axi_wready;
SLAVE_AXI_BRESP <= axi_bresp;
SLAVE_AXI_BVALID <= axi_bvalid;
SLAVE_AXI_ARREADY <= axi_arready;
SLAVE_AXI_RDATA <= axi_rdata;
SLAVE_AXI_RRESP <= axi_rresp;
SLAVE_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and SLAVE_AXI_AWVALID = '1' and SLAVE_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and SLAVE_AXI_AWVALID = '1' and SLAVE_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= SLAVE_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and SLAVE_AXI_WVALID = '1' and SLAVE_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and SLAVE_AXI_WVALID and axi_awready and SLAVE_AXI_AWVALID ;
process (SLAVE_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"000" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"001" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 1
slv_reg1(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"010" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"011" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 3
slv_reg3(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"100" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 4
slv_reg4(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"101" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 5
slv_reg5(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"110" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 6
slv_reg6(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"111" =>
for byte_index in 0 to (C_SLAVE_AXI_DATA_WIDTH/8-1) loop
if ( SLAVE_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 7
slv_reg7(byte_index*8+7 downto byte_index*8) <= SLAVE_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5;
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and SLAVE_AXI_AWVALID = '1' and axi_wready = '1' and SLAVE_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (SLAVE_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and SLAVE_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= SLAVE_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (SLAVE_AXI_ACLK)
begin
if rising_edge(SLAVE_AXI_ACLK) then
if SLAVE_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and SLAVE_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and SLAVE_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and SLAVE_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, axi_araddr, SLAVE_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"000" =>
reg_data_out <= slv_reg0;
when b"001" =>
reg_data_out <= HWVER & MODE;--slv_reg1;
when b"010" =>
reg_data_out <= slv_reg2;
-- when b"011" =>
-- reg_data_out <= slv_reg3;
-- when b"100" =>
-- reg_data_out <= slv_reg4;
-- when b"101" =>
-- reg_data_out <= slv_reg5;
-- when b"110" =>
-- reg_data_out <= slv_reg6;
-- when b"111" =>
-- reg_data_out <= slv_reg7;
when others =>
reg_data_out <= (others => '0');
end case;
end process;
-- Output register or memory read data
process( SLAVE_AXI_ACLK ) is
begin
if (rising_edge (SLAVE_AXI_ACLK)) then
if ( SLAVE_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
PCNTR <= slv_reg0(15 downto 0);
STATUS <= slv_reg0(31 downto 16);
--MODE : in std_logic_vector(15 downto 0);
--HWVER : in std_logic_vector(15 downto 0);
SWVER <= slv_reg2(15 downto 0);
-- User logic ends
end arch_imp;
|
-- -----------------------------------------------------------------------
--
-- Turbo Chameleon
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2014 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- SDRAM controller
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon_sdram is
generic (
-- SDRAM cols/rows 8/12 = 8 Mbyte, 9/12 = 16 Mbyte, 9/13 = 32 Mbyte
colAddrBits : integer := 9;
rowAddrBits : integer := 12;
-- Port settings
enable_cpu6510_port : boolean := false;
enable_cache1_port : boolean := false;
enable_cache2_port : boolean := false;
enable_vid0_port : boolean := false;
enable_vid1_port : boolean := false;
-- Controller settings
initTimeout : integer := 10000;
readAutoPrecharge : boolean := true;
-- SDRAM timing
casLatency : integer := 3;
ras_cycles : integer := 2;
precharge_cycles : integer := 2;
t_refresh_ms : real := 64.0;
t_refresh_ns : real := 60.0;
t_clk_ns : real := 10.0 -- Clock cycle time
);
port (
-- System
clk : in std_logic;
reserve : in std_logic := '0';
delay_refresh : in std_logic := '0';
-- SDRAM interface
sd_data : inout unsigned(15 downto 0);
sd_addr : out unsigned((rowAddrBits-1) downto 0);
sd_we_n : out std_logic;
sd_ras_n : out std_logic;
sd_cas_n : out std_logic;
sd_ba_0 : out std_logic;
sd_ba_1 : out std_logic;
sd_ldqm : out std_logic;
sd_udqm : out std_logic;
-- first cache port
cache_req : in std_logic := '0';
cache_ack : out std_logic;
cache_we : in std_logic := '0';
cache_burst : in std_logic := '0';
cache_a : in unsigned((colAddrBits+rowAddrBits+2) downto 0) := (others => '0');
cache_d : in unsigned(63 downto 0) := (others => '0');
cache_q : out unsigned(63 downto 0);
-- second cache port
cache2_req : in std_logic := '0';
cache2_ack : out std_logic;
cache2_we : in std_logic := '0';
cache2_burst : in std_logic := '0';
cache2_a : in unsigned((colAddrBits+rowAddrBits+2) downto 0) := (others => '0');
cache2_d : in unsigned(63 downto 0) := (others => '0');
cache2_q : out unsigned(63 downto 0);
-- VGA Video read ports
vid0_req : in std_logic := '0'; -- Toggle for request
vid0_ack : out std_logic; -- Ack follows req when done
vid0_addr : unsigned((colAddrBits+rowAddrBits+2) downto 3) := (others => '0');
vid0_do : out unsigned(63 downto 0);
vid1_req : in std_logic := '0'; -- Toggle for request
vid1_ack : out std_logic; -- Ack follows req when done
vid1_addr : unsigned((colAddrBits+rowAddrBits+2) downto 3) := (others => '0');
vid1_do : out unsigned(63 downto 0);
-- 6510 port (8 bit port)
cpu6510_req : in std_logic := '0'; -- toggle to start memory request
cpu6510_ack : out std_logic; -- will follow 'request' after transfer
cpu6510_we : in std_logic := '0'; -- 1 write action, 0 read action
cpu6510_a : in unsigned((colAddrBits+rowAddrBits+2) downto 0) := (others => '0');
cpu6510_d : in unsigned(7 downto 0) := (others => '0');
cpu6510_q : out unsigned(7 downto 0);
-- Debug ports
debugIdle : out std_logic; -- '1' memory is idle
debugRefresh : out std_logic -- '1' memory is being refreshed
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of chameleon_sdram is
constant refresh_clocks : integer := integer((t_refresh_ns / t_clk_ns) + 0.5);
constant refresh_interval : integer := integer((t_refresh_ms*1000000.0) / (t_clk_ns * 2.0**rowAddrBits));
constant refresh_timer_range : integer := refresh_interval*3;
-- ram state machine
type ramStates is (
RAM_INIT,
RAM_INIT_PRECHARGE,
RAM_SETMODE,
RAM_IDLE,
RAM_ACTIVE,
RAM_READ_1,
RAM_READ_2,
RAM_READ_3,
RAM_READ_4,
RAM_READ_5,
RAM_WRITE_1,
RAM_WRITE_2,
RAM_WRITE_3,
RAM_WRITE_4,
RAM_WRITE_ABORT,
RAM_WRITE_DLY,
RAM_PRECHARGE,
RAM_PRECHARGE_ALL,
RAM_AUTOREFRESH
);
type ramPorts is (
PORT_NONE,
PORT_CACHE_1,
PORT_CACHE_2,
PORT_VID0,
PORT_VID1,
PORT_CPU6510
);
type timer_t is record
cnt : integer range 0 to 32767;
run : std_logic;
end record;
subtype row_t is unsigned((rowAddrBits-1) downto 0);
subtype col_t is unsigned((colAddrBits-1) downto 0);
signal ramState : ramStates := RAM_INIT;
signal timer : timer_t := (cnt => 0, run => '0');
signal ram_data_reg : unsigned(sd_data'range);
-- Registered sdram signals
signal sd_data_reg : unsigned(15 downto 0);
signal sd_data_ena : std_logic := '0';
signal sd_addr_reg : unsigned((rowAddrBits-1) downto 0);
signal sd_we_n_reg : std_logic;
signal sd_ras_n_reg : std_logic;
signal sd_cas_n_reg : std_logic;
signal sd_ba_0_reg : std_logic;
signal sd_ba_1_reg : std_logic;
signal sd_ldqm_reg : std_logic;
signal sd_udqm_reg : std_logic;
-- ram acknowledge signals
signal cache1_ack_reg : std_logic := '0';
signal cache2_ack_reg : std_logic := '0';
signal vid0_ack_reg : std_logic := '0';
signal vid1_ack_reg : std_logic := '0';
signal cpu6510_ack_reg : std_logic := '0';
-- Active rows in SDRAM
type bankRowDef is array(0 to 3) of row_t;
signal bankActive : std_logic_vector(0 to 3) := (others => '0');
signal bankRow : bankRowDef;
-- Memory auto refresh
signal refreshTimer : integer range 0 to refresh_timer_range := 0;
signal refresh_active_reg : std_logic := '0';
signal refresh_subtract_reg : std_logic := '0';
signal refresh_required_reg : std_logic := '0';
signal currentPort : ramPorts;
signal currentBank : unsigned(1 downto 0);
signal currentRow : row_t;
signal currentCol : col_t;
signal currentWrData : unsigned(63 downto 0);
signal currentLdqm : std_logic;
signal currentUdqm : std_logic;
signal currentWe : std_logic;
signal nextRamBank : unsigned(1 downto 0);
signal nextRamRow : row_t;
signal nextRamCol : col_t;
signal nextRamPort : ramPorts;
signal nextWrData : unsigned(63 downto 0);
signal nextLdqm : std_logic;
signal nextUdqm : std_logic;
signal nextWe : std_logic;
procedure set_timer(signal timer : inout timer_t; constant timeout : in integer) is
begin
if timeout > 0 then
timer.run <= '1';
timer.cnt <= timeout-1;
else
timer.run <= '0';
end if;
end procedure;
begin
ram_data_reg <= sd_data;
sd_data <= sd_data_reg when sd_data_ena = '1' else (others => 'Z');
sd_addr <= sd_addr_reg;
sd_ras_n <= sd_ras_n_reg;
sd_cas_n <= sd_cas_n_reg;
sd_we_n <= sd_we_n_reg;
sd_ba_0 <= sd_ba_0_reg;
sd_ba_1 <= sd_ba_1_reg;
sd_ldqm <= sd_ldqm_reg;
sd_udqm <= sd_udqm_reg;
cache_ack <= cache1_ack_reg;
cache2_ack <= cache2_ack_reg;
vid0_ack <= vid0_ack_reg;
vid1_ack <= vid1_ack_reg;
cpu6510_ack <= cpu6510_ack_reg;
-- -----------------------------------------------------------------------
-- Refresh timer
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if refreshTimer < refresh_timer_range-1 then
refreshTimer <= refreshTimer + 1;
end if;
if refresh_subtract_reg = '1' then
refreshTimer <= refreshTimer - refresh_interval;
end if;
refresh_required_reg <= '0';
if refreshTimer >= refresh_interval then
-- Suppress refreshes when "reserve" pin is high.
refresh_required_reg <= not reserve;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- State machine
-- -----------------------------------------------------------------------
process(currentPort, cpu6510_req, cpu6510_ack_reg, cache_req, cache1_ack_reg,
reserve, cache_a, cache_d, cache_burst, cache_we, vid0_req,
vid0_ack_reg, vid0_addr)
begin
nextRamPort <= PORT_NONE;
nextRamBank <= "00";
nextRamRow <= ( others => '0');
nextRamCol <= ( others => '0');
nextLdqm <= '0';
nextUdqm <= '0';
nextWe <= '0';
nextWrData <= (others => '-');
if enable_cpu6510_port and (cpu6510_req /= cpu6510_ack_reg) and (currentPort /= PORT_CPU6510) then
if cpu6510_we = '1' then
nextWe <= '1';
nextLdqm <= cpu6510_a(0);
nextUdqm <= not cpu6510_a(0);
end if;
nextRamPort <= PORT_CPU6510;
nextRamBank <= cpu6510_a((colAddrBits+rowAddrBits+2) downto (colAddrBits+rowAddrBits+1));
nextRamRow <= cpu6510_a((colAddrBits+rowAddrBits) downto (colAddrBits+1));
nextRamCol <= cpu6510_a(colAddrBits downto 1);
nextWrData(15 downto 0) <= cpu6510_d & cpu6510_d;
elsif enable_cache1_port and (cache_req /= cache1_ack_reg) and (currentPort /= PORT_CACHE_1) then
nextRamPort <= PORT_CACHE_1;
nextRamBank <= cache_a((colAddrBits+rowAddrBits+2) downto (colAddrBits+rowAddrBits+1));
nextRamRow <= cache_a((colAddrBits+rowAddrBits) downto (colAddrBits+1));
nextRamCol <= cache_a(colAddrBits downto 1);
nextWrData <= cache_d;
if cache_burst = '1' then
nextRamCol(1 downto 0) <= "00";
end if;
if cache_we = '1' then
nextWe <= '1';
if cache_burst = '0' then
nextLdqm <= cache_a(0);
nextUdqm <= not cache_a(0);
end if;
end if;
elsif enable_cache2_port and (cache2_req /= cache2_ack_reg) and (currentPort /= PORT_CACHE_2) then
nextRamPort <= PORT_CACHE_2;
nextRamBank <= cache2_a((colAddrBits+rowAddrBits+2) downto (colAddrBits+rowAddrBits+1));
nextRamRow <= cache2_a((colAddrBits+rowAddrBits) downto (colAddrBits+1));
nextRamCol <= cache2_a(colAddrBits downto 1);
nextWrData <= cache2_d;
if cache2_burst = '1' then
nextRamCol(1 downto 0) <= "00";
end if;
if cache2_we = '1' then
nextWe <= '1';
if cache2_burst = '0' then
nextLdqm <= cache2_a(0);
nextUdqm <= not cache2_a(0);
end if;
end if;
elsif reserve = '0' then
if enable_vid0_port and (vid0_req /= vid0_ack_reg) and (currentPort /= PORT_VID0) then
nextRamPort <= PORT_VID0;
nextRamBank <= vid0_addr((colAddrBits+rowAddrBits+2) downto (colAddrBits+rowAddrBits+1));
nextRamRow <= vid0_addr((colAddrBits+rowAddrBits) downto (colAddrBits+1));
nextRamCol <= vid0_addr(colAddrBits downto 3) & "00";
elsif enable_vid1_port and (vid1_req /= vid1_ack_reg) and (currentPort /= PORT_VID1) then
nextRamPort <= PORT_VID1;
nextRamBank <= vid1_addr((colAddrBits+rowAddrBits+2) downto (colAddrBits+rowAddrBits+1));
nextRamRow <= vid1_addr((colAddrBits+rowAddrBits) downto (colAddrBits+1));
nextRamCol <= vid1_addr(colAddrBits downto 3) & "00";
end if;
end if;
end process;
process(clk)
variable done_cache1 : std_logic;
variable done_cache2 : std_logic;
variable done_vid0 : std_logic;
variable done_vid1 : std_logic;
variable done_cpu6510 : std_logic;
begin
done_cache1 := '0';
done_cache2 := '0';
done_vid0 := '0';
done_vid1 := '0';
done_cpu6510 := '0';
if rising_edge(clk) then
refresh_subtract_reg <= '0';
sd_data_ena <= '0';
sd_addr_reg <= (others => '0');
sd_ras_n_reg <= '1';
sd_cas_n_reg <= '1';
sd_we_n_reg <= '1';
sd_ldqm_reg <= '0';
sd_udqm_reg <= '0';
sd_ba_0_reg <= currentBank(0);
sd_ba_1_reg <= currentBank(1);
if timer.run = '1' then
if timer.cnt = 0 then
timer.run <= '0';
else
timer.cnt <= timer.cnt - 1;
end if;
else
case ramState is
when RAM_INIT =>
-- Wait for clock to stabilise and PLL locks
-- Then follow init steps in datasheet:
-- precharge all banks
-- perform a few autorefresh cycles (we do 2 of them)
-- setmode (burst and CAS latency)
-- after a few clocks ram is ready for use (we wait 10 just to be sure).
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
currentLdqm <= '-';
currentUdqm <= '-';
currentWe <= '-';
set_timer(timer, 20000);
ramState <= RAM_INIT_PRECHARGE;
when RAM_INIT_PRECHARGE =>
-- Precharge all banks, part of initialisation sequence.
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
currentLdqm <= '-';
currentUdqm <= '-';
currentWe <= '-';
set_timer(timer, 100);
ramState <= RAM_SETMODE;
sd_ras_n_reg <= '0';
sd_we_n_reg <= '0';
sd_addr_reg(10) <= '1'; -- precharge all banks
when RAM_SETMODE =>
-- Set mode bits of RAM, part of initialisation sequence.
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
currentLdqm <= '-';
currentUdqm <= '-';
currentWe <= '-';
set_timer(timer, 10);
ramState <= RAM_IDLE; -- ram is ready for commands after set-mode
sd_addr_reg <= resize("000000100010", sd_addr'length); -- CAS2, Burstlength 4 (8 bytes, 64 bits)
if casLatency = 3 then
sd_addr_reg(6 downto 4) <= "011";
end if;
sd_we_n_reg <= '0';
sd_ras_n_reg <= '0';
sd_cas_n_reg <= '0';
when RAM_IDLE =>
currentPort <= nextRamPort;
currentBank <= nextRamBank;
currentRow <= nextRamRow;
currentCol <= nextRamCol;
currentLdqm <= nextLdqm;
currentUdqm <= nextUdqm;
currentWe <= nextWe;
currentWrData <= nextWrData;
refresh_active_reg <= '0';
if nextRamPort /= PORT_NONE then
ramState <= RAM_READ_1;
if nextWe = '1' then
ramState <= RAM_WRITE_1;
end if;
if bankActive(to_integer(nextRamBank)) = '0' then
-- Current bank not active. Activate a row first
ramState <= RAM_ACTIVE;
elsif bankRow(to_integer(nextRamBank)) /= nextRamRow then
-- Wrong row active in bank, do precharge then activate a row.
ramState <= RAM_PRECHARGE;
end if;
elsif (delay_refresh = '0') and (refresh_required_reg = '1') then
-- Refresh timeout, perform auto-refresh cycle
refresh_active_reg <= '1';
refresh_subtract_reg <= '1';
if bankActive /= "0000" then
-- There are still rows active, so we precharge them first
ramState <= RAM_PRECHARGE_ALL;
else
ramState <= RAM_AUTOREFRESH;
end if;
end if;
when RAM_ACTIVE =>
set_timer(timer, ras_cycles);
ramState <= RAM_READ_1;
if currentWe = '1' then
ramState <= RAM_WRITE_1;
end if;
sd_addr_reg <= currentRow;
sd_ras_n_reg <= '0';
bankRow(to_integer(currentBank)) <= currentRow;
bankActive(to_integer(currentBank)) <= '1';
when RAM_READ_1 =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
set_timer(timer, casLatency);
ramState <= RAM_READ_2;
sd_addr_reg <= resize(currentCol, sd_addr'length);
sd_cas_n_reg <= '0';
if readAutoPrecharge then
sd_addr_reg(10) <= '1';
bankActive(to_integer(currentBank)) <= '0';
end if;
when RAM_READ_2 =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_READ_3;
case currentPort is
when PORT_CACHE_1 =>
cache_q(15 downto 0) <= ram_data_reg;
when PORT_CACHE_2 =>
cache2_q(15 downto 0) <= ram_data_reg;
when PORT_VID0 =>
vid0_do(15 downto 0) <= ram_data_reg;
when PORT_VID1 =>
vid1_do(15 downto 0) <= ram_data_reg;
when PORT_CPU6510 =>
if enable_cpu6510_port then
cpu6510_q <= ram_data_reg(7 downto 0);
if cpu6510_a(0) = '1' then
cpu6510_q <= ram_data_reg(15 downto 8);
end if;
done_cpu6510 := '1';
end if;
when others =>
null;
end case;
when RAM_READ_3 =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_READ_4;
case currentPort is
when PORT_CACHE_1 =>
cache_q(31 downto 16) <= ram_data_reg;
when PORT_CACHE_2 =>
cache2_q(31 downto 16) <= ram_data_reg;
when PORT_VID0 =>
vid0_do(31 downto 16) <= ram_data_reg;
when PORT_VID1 =>
vid1_do(31 downto 16) <= ram_data_reg;
when others =>
null;
end case;
when RAM_READ_4 =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_READ_5;
case currentPort is
when PORT_CACHE_1 =>
cache_q(47 downto 32) <= ram_data_reg;
when PORT_CACHE_2 =>
cache2_q(47 downto 32) <= ram_data_reg;
when PORT_VID0 =>
vid0_do(47 downto 32) <= ram_data_reg;
when PORT_VID1 =>
vid1_do(47 downto 32) <= ram_data_reg;
when others =>
null;
end case;
when RAM_READ_5 =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_IDLE;
case currentPort is
when PORT_CACHE_1 =>
cache_q(63 downto 48) <= ram_data_reg;
done_cache1 := '1';
when PORT_CACHE_2 =>
cache2_q(63 downto 48) <= ram_data_reg;
done_cache2 := '1';
when PORT_VID0 =>
vid0_do(63 downto 48) <= ram_data_reg;
done_vid0 := '1';
when PORT_VID1 =>
vid1_do(63 downto 48) <= ram_data_reg;
done_vid1 := '1';
when PORT_CPU6510 =>
null;
when others =>
null;
end case;
when RAM_WRITE_1 =>
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_WRITE_2;
sd_data_ena <= '1';
sd_we_n_reg <= '0';
sd_cas_n_reg <= '0';
sd_addr_reg <= resize(currentCol, sd_addr'length);
sd_data_reg <= currentWrData(15 downto 0);
sd_ldqm_reg <= currentLdqm;
sd_udqm_reg <= currentUdqm;
if currentLdqm = '1'
or currentUdqm = '1' then
-- This is a partial write, abort burst.
ramState <= RAM_WRITE_ABORT;
-- ramDone := '1';
end if;
currentWrData(47 downto 0) <= currentWrData(63 downto 16);
when RAM_WRITE_2 =>
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_WRITE_3;
sd_data_ena <= '1';
sd_data_reg <= currentWrData(15 downto 0);
currentWrData(47 downto 0) <= currentWrData(63 downto 16);
when RAM_WRITE_3 =>
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_WRITE_4;
sd_data_ena <= '1';
sd_data_reg <= currentWrData(15 downto 0);
currentWrData(47 downto 0) <= currentWrData(63 downto 16);
when RAM_WRITE_4 =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
ramState <= RAM_WRITE_DLY;
sd_data_ena <= '1';
sd_data_reg <= currentWrData(15 downto 0);
-- currentWrData(47 downto 0) <= currentWrData(63 downto 16);
case currentPort is
when PORT_CACHE_1 =>
done_cache1 := '1';
when PORT_CACHE_2 =>
done_cache2 := '1';
when PORT_VID0 =>
done_vid0 := '1';
when PORT_VID1 =>
done_vid1 := '1';
when PORT_CPU6510 =>
done_cpu6510 := '1';
when others =>
null;
end case;
when RAM_WRITE_ABORT =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
--currentPort <= PORT_NONE;
ramState <= RAM_WRITE_DLY;
sd_we_n_reg <= '0';
case currentPort is
when PORT_CACHE_1 =>
done_cache1 := '1';
when PORT_CACHE_2 =>
done_cache2 := '1';
when PORT_VID0 =>
done_vid0 := '1';
when PORT_VID1 =>
done_vid1 := '1';
when PORT_CPU6510 =>
done_cpu6510 := '1';
when others =>
null;
end case;
when RAM_WRITE_DLY =>
currentWrData <= (others => '-');
currentBank <= (others => '-');
currentRow <= (others => '-');
currentCol <= (others => '-');
currentPort <= PORT_NONE;
ramState <= RAM_IDLE;
when RAM_PRECHARGE =>
set_timer(timer, precharge_cycles);
ramState <= RAM_ACTIVE;
sd_we_n_reg <= '0';
sd_ras_n_reg <= '0';
bankActive(to_integer(currentBank)) <= '0';
when RAM_PRECHARGE_ALL =>
set_timer(timer, precharge_cycles);
ramState <= RAM_IDLE;
if refresh_active_reg = '1' then
set_timer(timer, 1);
ramState <= RAM_AUTOREFRESH;
end if;
sd_addr_reg(10) <= '1'; -- All banks
sd_we_n_reg <= '0';
sd_ras_n_reg <= '0';
bankActive <= "0000";
when RAM_AUTOREFRESH =>
set_timer(timer, refresh_clocks);
ramState <= RAM_IDLE;
sd_we_n_reg <= '1';
sd_ras_n_reg <= '0';
sd_cas_n_reg <= '0';
end case;
end if;
if enable_cache1_port and (done_cache1 = '1') then
cache1_ack_reg <= cache_req;
end if;
if enable_cache2_port and (done_cache2 = '1') then
cache2_ack_reg <= cache2_req;
end if;
if enable_vid0_port and (done_vid0 = '1') then
vid0_ack_reg <= vid0_req;
end if;
if enable_vid1_port and (done_vid1 = '1') then
vid1_ack_reg <= vid1_req;
end if;
if enable_cpu6510_port and (done_cpu6510 = '1') then
cpu6510_ack_reg <= cpu6510_req;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Debug and measurement signals
-- -----------------------------------------------------------------------
debugIdle <= '1' when ((refresh_active_reg = '0') and (ramState = RAM_IDLE)) else '0';
debugRefresh <= refresh_active_reg;
end architecture;
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