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function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
function Pow2( N, Exp : integer ) return mylib.myinteger is
Variable Result : integer := 1;
begin
for i in 1 to Exp loop
Result := Result * N;
end loop;
return( Result );
end Pow;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2009 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539A803";
when 16#00069# => romdata <= X"8410A261";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"0539A81B";
when 16#00077# => romdata <= X"8410A260";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000008";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D1003FF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple memory tester that can be
-- traced with chipscope. This is the 32 bit version.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_32 is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
inhibit : out std_logic := '0';
req : out t_mem_burst_32_req;
resp : in t_mem_burst_32_resp;
okay : out std_logic );
end entity;
architecture gideon of ext_mem_test_32 is
type t_access is record
address : unsigned(27 downto 0);
read_writen : std_logic;
end record;
type t_accesses is array (natural range <>) of t_access;
constant c_test_vector : t_accesses := (
( X"0000000", '0' ), -- write to 0
( X"0000100", '0' ), -- write to 100
( X"0000000", '1' ), -- read from 0
( X"0010000", '0' ), -- write to 64K
( X"0000100", '1' ), -- read from 100
( X"0010000", '1' ) ); -- read from 64K
subtype t_data is std_logic_vector(31 downto 0);
type t_datas is array (natural range <>) of t_data;
constant c_test_data : t_datas(0 to 7) := (
X"12345678", X"9ABCDEF0", -- 0
X"DEADBEEF", X"C0EDBABE", -- 100
X"00FF00FF", X"00FF00FF", -- 64K
X"55AA55AA", X"3366CC99" ); -- 0, etc
signal data_count : integer range 0 to c_test_data'high;
signal check_count : integer range 0 to c_test_data'high;
signal cmd_count : integer range 0 to c_test_vector'high;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
req <= c_mem_burst_32_req_init;
data_count <= 0;
cmd_count <= 0;
check_count <= 0;
okay <= '1';
else
-- push write data
if resp.wdata_full='0' then
req.data <= c_test_data(data_count);
req.byte_en <= (others => '1');
req.data_push <= '1';
if data_count = c_test_data'high then
data_count <= 0;
else
data_count <= data_count + 1;
end if;
else
req.data_push <= '0';
end if;
-- push commands
req.request <= '1';
if resp.ready='1' then
req.request_tag <= std_logic_vector(to_unsigned(cmd_count, 8));
req.address <= c_test_vector(cmd_count).address(25 downto 0);
req.read_writen <= c_test_vector(cmd_count).read_writen;
if cmd_count = c_test_vector'high then
cmd_count <= 0;
else
cmd_count <= cmd_count + 1;
end if;
end if;
-- check read data
if resp.rdata_av='1' then
if resp.data = c_test_data(check_count) then
okay <= '1';
else
okay <= '0';
end if;
if check_count = c_test_data'high then
check_count <= 0;
else
check_count <= check_count + 1;
end if;
end if;
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple memory tester that can be
-- traced with chipscope. This is the 32 bit version.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_32 is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
inhibit : out std_logic := '0';
req : out t_mem_burst_32_req;
resp : in t_mem_burst_32_resp;
okay : out std_logic );
end entity;
architecture gideon of ext_mem_test_32 is
type t_access is record
address : unsigned(27 downto 0);
read_writen : std_logic;
end record;
type t_accesses is array (natural range <>) of t_access;
constant c_test_vector : t_accesses := (
( X"0000000", '0' ), -- write to 0
( X"0000100", '0' ), -- write to 100
( X"0000000", '1' ), -- read from 0
( X"0010000", '0' ), -- write to 64K
( X"0000100", '1' ), -- read from 100
( X"0010000", '1' ) ); -- read from 64K
subtype t_data is std_logic_vector(31 downto 0);
type t_datas is array (natural range <>) of t_data;
constant c_test_data : t_datas(0 to 7) := (
X"12345678", X"9ABCDEF0", -- 0
X"DEADBEEF", X"C0EDBABE", -- 100
X"00FF00FF", X"00FF00FF", -- 64K
X"55AA55AA", X"3366CC99" ); -- 0, etc
signal data_count : integer range 0 to c_test_data'high;
signal check_count : integer range 0 to c_test_data'high;
signal cmd_count : integer range 0 to c_test_vector'high;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
req <= c_mem_burst_32_req_init;
data_count <= 0;
cmd_count <= 0;
check_count <= 0;
okay <= '1';
else
-- push write data
if resp.wdata_full='0' then
req.data <= c_test_data(data_count);
req.byte_en <= (others => '1');
req.data_push <= '1';
if data_count = c_test_data'high then
data_count <= 0;
else
data_count <= data_count + 1;
end if;
else
req.data_push <= '0';
end if;
-- push commands
req.request <= '1';
if resp.ready='1' then
req.request_tag <= std_logic_vector(to_unsigned(cmd_count, 8));
req.address <= c_test_vector(cmd_count).address(25 downto 0);
req.read_writen <= c_test_vector(cmd_count).read_writen;
if cmd_count = c_test_vector'high then
cmd_count <= 0;
else
cmd_count <= cmd_count + 1;
end if;
end if;
-- check read data
if resp.rdata_av='1' then
if resp.data = c_test_data(check_count) then
okay <= '1';
else
okay <= '0';
end if;
if check_count = c_test_data'high then
check_count <= 0;
else
check_count <= check_count + 1;
end if;
end if;
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple memory tester that can be
-- traced with chipscope. This is the 32 bit version.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_32 is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
inhibit : out std_logic := '0';
req : out t_mem_burst_32_req;
resp : in t_mem_burst_32_resp;
okay : out std_logic );
end entity;
architecture gideon of ext_mem_test_32 is
type t_access is record
address : unsigned(27 downto 0);
read_writen : std_logic;
end record;
type t_accesses is array (natural range <>) of t_access;
constant c_test_vector : t_accesses := (
( X"0000000", '0' ), -- write to 0
( X"0000100", '0' ), -- write to 100
( X"0000000", '1' ), -- read from 0
( X"0010000", '0' ), -- write to 64K
( X"0000100", '1' ), -- read from 100
( X"0010000", '1' ) ); -- read from 64K
subtype t_data is std_logic_vector(31 downto 0);
type t_datas is array (natural range <>) of t_data;
constant c_test_data : t_datas(0 to 7) := (
X"12345678", X"9ABCDEF0", -- 0
X"DEADBEEF", X"C0EDBABE", -- 100
X"00FF00FF", X"00FF00FF", -- 64K
X"55AA55AA", X"3366CC99" ); -- 0, etc
signal data_count : integer range 0 to c_test_data'high;
signal check_count : integer range 0 to c_test_data'high;
signal cmd_count : integer range 0 to c_test_vector'high;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
req <= c_mem_burst_32_req_init;
data_count <= 0;
cmd_count <= 0;
check_count <= 0;
okay <= '1';
else
-- push write data
if resp.wdata_full='0' then
req.data <= c_test_data(data_count);
req.byte_en <= (others => '1');
req.data_push <= '1';
if data_count = c_test_data'high then
data_count <= 0;
else
data_count <= data_count + 1;
end if;
else
req.data_push <= '0';
end if;
-- push commands
req.request <= '1';
if resp.ready='1' then
req.request_tag <= std_logic_vector(to_unsigned(cmd_count, 8));
req.address <= c_test_vector(cmd_count).address(25 downto 0);
req.read_writen <= c_test_vector(cmd_count).read_writen;
if cmd_count = c_test_vector'high then
cmd_count <= 0;
else
cmd_count <= cmd_count + 1;
end if;
end if;
-- check read data
if resp.rdata_av='1' then
if resp.data = c_test_data(check_count) then
okay <= '1';
else
okay <= '0';
end if;
if check_count = c_test_data'high then
check_count <= 0;
else
check_count <= check_count + 1;
end if;
end if;
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple memory tester that can be
-- traced with chipscope. This is the 32 bit version.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_32 is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
inhibit : out std_logic := '0';
req : out t_mem_burst_32_req;
resp : in t_mem_burst_32_resp;
okay : out std_logic );
end entity;
architecture gideon of ext_mem_test_32 is
type t_access is record
address : unsigned(27 downto 0);
read_writen : std_logic;
end record;
type t_accesses is array (natural range <>) of t_access;
constant c_test_vector : t_accesses := (
( X"0000000", '0' ), -- write to 0
( X"0000100", '0' ), -- write to 100
( X"0000000", '1' ), -- read from 0
( X"0010000", '0' ), -- write to 64K
( X"0000100", '1' ), -- read from 100
( X"0010000", '1' ) ); -- read from 64K
subtype t_data is std_logic_vector(31 downto 0);
type t_datas is array (natural range <>) of t_data;
constant c_test_data : t_datas(0 to 7) := (
X"12345678", X"9ABCDEF0", -- 0
X"DEADBEEF", X"C0EDBABE", -- 100
X"00FF00FF", X"00FF00FF", -- 64K
X"55AA55AA", X"3366CC99" ); -- 0, etc
signal data_count : integer range 0 to c_test_data'high;
signal check_count : integer range 0 to c_test_data'high;
signal cmd_count : integer range 0 to c_test_vector'high;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
req <= c_mem_burst_32_req_init;
data_count <= 0;
cmd_count <= 0;
check_count <= 0;
okay <= '1';
else
-- push write data
if resp.wdata_full='0' then
req.data <= c_test_data(data_count);
req.byte_en <= (others => '1');
req.data_push <= '1';
if data_count = c_test_data'high then
data_count <= 0;
else
data_count <= data_count + 1;
end if;
else
req.data_push <= '0';
end if;
-- push commands
req.request <= '1';
if resp.ready='1' then
req.request_tag <= std_logic_vector(to_unsigned(cmd_count, 8));
req.address <= c_test_vector(cmd_count).address(25 downto 0);
req.read_writen <= c_test_vector(cmd_count).read_writen;
if cmd_count = c_test_vector'high then
cmd_count <= 0;
else
cmd_count <= cmd_count + 1;
end if;
end if;
-- check read data
if resp.rdata_av='1' then
if resp.data = c_test_data(check_count) then
okay <= '1';
else
okay <= '0';
end if;
if check_count = c_test_data'high then
check_count <= 0;
else
check_count <= check_count + 1;
end if;
end if;
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple memory tester that can be
-- traced with chipscope. This is the 32 bit version.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_32 is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
inhibit : out std_logic := '0';
req : out t_mem_burst_32_req;
resp : in t_mem_burst_32_resp;
okay : out std_logic );
end entity;
architecture gideon of ext_mem_test_32 is
type t_access is record
address : unsigned(27 downto 0);
read_writen : std_logic;
end record;
type t_accesses is array (natural range <>) of t_access;
constant c_test_vector : t_accesses := (
( X"0000000", '0' ), -- write to 0
( X"0000100", '0' ), -- write to 100
( X"0000000", '1' ), -- read from 0
( X"0010000", '0' ), -- write to 64K
( X"0000100", '1' ), -- read from 100
( X"0010000", '1' ) ); -- read from 64K
subtype t_data is std_logic_vector(31 downto 0);
type t_datas is array (natural range <>) of t_data;
constant c_test_data : t_datas(0 to 7) := (
X"12345678", X"9ABCDEF0", -- 0
X"DEADBEEF", X"C0EDBABE", -- 100
X"00FF00FF", X"00FF00FF", -- 64K
X"55AA55AA", X"3366CC99" ); -- 0, etc
signal data_count : integer range 0 to c_test_data'high;
signal check_count : integer range 0 to c_test_data'high;
signal cmd_count : integer range 0 to c_test_vector'high;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
req <= c_mem_burst_32_req_init;
data_count <= 0;
cmd_count <= 0;
check_count <= 0;
okay <= '1';
else
-- push write data
if resp.wdata_full='0' then
req.data <= c_test_data(data_count);
req.byte_en <= (others => '1');
req.data_push <= '1';
if data_count = c_test_data'high then
data_count <= 0;
else
data_count <= data_count + 1;
end if;
else
req.data_push <= '0';
end if;
-- push commands
req.request <= '1';
if resp.ready='1' then
req.request_tag <= std_logic_vector(to_unsigned(cmd_count, 8));
req.address <= c_test_vector(cmd_count).address(25 downto 0);
req.read_writen <= c_test_vector(cmd_count).read_writen;
if cmd_count = c_test_vector'high then
cmd_count <= 0;
else
cmd_count <= cmd_count + 1;
end if;
end if;
-- check read data
if resp.rdata_av='1' then
if resp.data = c_test_data(check_count) then
okay <= '1';
else
okay <= '0';
end if;
if check_count = c_test_data'high then
check_count <= 0;
else
check_count <= check_count + 1;
end if;
end if;
end if;
end if;
end process;
end architecture;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter is
port (
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
OUTPUT_STREAM_TVALID : OUT STD_LOGIC;
OUTPUT_STREAM_TREADY : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC );
end;
architecture behav of image_filter is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"image_filter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=6.666670,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=5.758000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=586,HLS_SYN_LUT=990}";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_true : BOOLEAN := true;
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
signal ap_rst_n_inv : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_start : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_done : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_continue : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_idle : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_ready : STD_LOGIC;
signal image_filter_Block_proc_U0_rows : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Block_proc_U0_cols : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Block_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_2 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_3 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V : STD_LOGIC;
signal img_1_rows_V_full_n : STD_LOGIC;
signal ap_reg_ready_img_1_rows_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_1_rows_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel : STD_LOGIC;
signal img_0_rows_V_channel_full_n : STD_LOGIC;
signal ap_reg_ready_img_0_rows_V_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_0_rows_V_channel_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V : STD_LOGIC;
signal img_1_cols_V_full_n : STD_LOGIC;
signal ap_reg_ready_img_1_cols_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_1_cols_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel : STD_LOGIC;
signal img_0_cols_V_channel_full_n : STD_LOGIC;
signal ap_reg_ready_img_0_cols_V_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_0_cols_V_channel_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_start : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_done : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_continue : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_idle : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_ready : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_start : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_done : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_continue : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_idle : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_ready : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_rows : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Loop_1_proc_U0_cols : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_0_address0 : STD_LOGIC_VECTOR (1 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_0_ce0 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_0_we0 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_0_d0 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_0_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_0_address1 : STD_LOGIC_VECTOR (1 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_0_ce1 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_0_we1 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_0_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_0_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_1_address0 : STD_LOGIC_VECTOR (1 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_1_ce0 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_1_we0 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_1_d0 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_1_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_1_address1 : STD_LOGIC_VECTOR (1 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_1_ce1 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_1_we1 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_1_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_1_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_2_address0 : STD_LOGIC_VECTOR (1 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_2_ce0 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_2_we0 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_2_d0 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_2_address1 : STD_LOGIC_VECTOR (1 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_2_ce1 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_2_we1 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_2_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_2_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_ap_start : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_done : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_continue : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_idle : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_ready : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_hs_continue : STD_LOGIC;
signal img_0_rows_V_channel_U_ap_dummy_ce : STD_LOGIC;
signal img_0_rows_V_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_rows_V_channel_write : STD_LOGIC;
signal img_0_rows_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_rows_V_channel_empty_n : STD_LOGIC;
signal img_0_rows_V_channel_read : STD_LOGIC;
signal img_0_cols_V_channel_U_ap_dummy_ce : STD_LOGIC;
signal img_0_cols_V_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_cols_V_channel_write : STD_LOGIC;
signal img_0_cols_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_cols_V_channel_empty_n : STD_LOGIC;
signal img_0_cols_V_channel_read : STD_LOGIC;
signal img_1_rows_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_rows_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_rows_V_write : STD_LOGIC;
signal img_1_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_rows_V_empty_n : STD_LOGIC;
signal img_1_rows_V_read : STD_LOGIC;
signal img_1_cols_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_cols_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_cols_V_write : STD_LOGIC;
signal img_1_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_cols_V_empty_n : STD_LOGIC;
signal img_1_cols_V_read : STD_LOGIC;
signal img_0_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal img_0_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_0_V_full_n : STD_LOGIC;
signal img_0_data_stream_0_V_write : STD_LOGIC;
signal img_0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_0_V_empty_n : STD_LOGIC;
signal img_0_data_stream_0_V_read : STD_LOGIC;
signal img_0_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC;
signal img_0_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_1_V_full_n : STD_LOGIC;
signal img_0_data_stream_1_V_write : STD_LOGIC;
signal img_0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_1_V_empty_n : STD_LOGIC;
signal img_0_data_stream_1_V_read : STD_LOGIC;
signal img_0_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC;
signal img_0_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_2_V_full_n : STD_LOGIC;
signal img_0_data_stream_2_V_write : STD_LOGIC;
signal img_0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_2_V_empty_n : STD_LOGIC;
signal img_0_data_stream_2_V_read : STD_LOGIC;
signal img_1_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_0_V_full_n : STD_LOGIC;
signal img_1_data_stream_0_V_write : STD_LOGIC;
signal img_1_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_0_V_empty_n : STD_LOGIC;
signal img_1_data_stream_0_V_read : STD_LOGIC;
signal img_1_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_1_V_full_n : STD_LOGIC;
signal img_1_data_stream_1_V_write : STD_LOGIC;
signal img_1_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_1_V_empty_n : STD_LOGIC;
signal img_1_data_stream_1_V_read : STD_LOGIC;
signal img_1_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_2_V_full_n : STD_LOGIC;
signal img_1_data_stream_2_V_write : STD_LOGIC;
signal img_1_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_2_V_empty_n : STD_LOGIC;
signal img_1_data_stream_2_V_read : STD_LOGIC;
signal ap_reg_procdone_image_filter_Block_proc_U0 : STD_LOGIC := '0';
signal ap_sig_hs_done : STD_LOGIC;
signal ap_reg_procdone_image_filter_AXIvideo2Mat_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_Loop_1_proc_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_Mat2AXIvideo_U0 : STD_LOGIC := '0';
signal ap_CS : STD_LOGIC;
signal ap_sig_top_allready : STD_LOGIC;
component image_filter_Block_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end component;
component image_filter_AXIvideo2Mat IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC );
end component;
component image_filter_Loop_1_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
img_1_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_0_V_full_n : IN STD_LOGIC;
img_1_data_stream_0_V_write : OUT STD_LOGIC;
img_1_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_1_V_full_n : IN STD_LOGIC;
img_1_data_stream_1_V_write : OUT STD_LOGIC;
img_1_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_2_V_full_n : IN STD_LOGIC;
img_1_data_stream_2_V_write : OUT STD_LOGIC;
img_0_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_0_V_empty_n : IN STD_LOGIC;
img_0_data_stream_0_V_read : OUT STD_LOGIC;
img_0_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_1_V_empty_n : IN STD_LOGIC;
img_0_data_stream_1_V_read : OUT STD_LOGIC;
img_0_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_2_V_empty_n : IN STD_LOGIC;
img_0_data_stream_2_V_read : OUT STD_LOGIC;
buffer_val_0_address0 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_0_ce0 : OUT STD_LOGIC;
buffer_val_0_we0 : OUT STD_LOGIC;
buffer_val_0_d0 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_0_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_0_address1 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_0_ce1 : OUT STD_LOGIC;
buffer_val_0_we1 : OUT STD_LOGIC;
buffer_val_0_d1 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_0_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_1_address0 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_1_ce0 : OUT STD_LOGIC;
buffer_val_1_we0 : OUT STD_LOGIC;
buffer_val_1_d0 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_1_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_1_address1 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_1_ce1 : OUT STD_LOGIC;
buffer_val_1_we1 : OUT STD_LOGIC;
buffer_val_1_d1 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_1_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_2_address0 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_2_ce0 : OUT STD_LOGIC;
buffer_val_2_we0 : OUT STD_LOGIC;
buffer_val_2_d0 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_2_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_2_address1 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_2_ce1 : OUT STD_LOGIC;
buffer_val_2_we1 : OUT STD_LOGIC;
buffer_val_2_d1 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_2_q1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
component image_filter_Mat2AXIvideo IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
OUTPUT_STREAM_TVALID : OUT STD_LOGIC;
OUTPUT_STREAM_TREADY : IN STD_LOGIC;
OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component FIFO_image_filter_img_0_rows_V_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_cols_V_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_rows_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_cols_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_data_stream_1_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_data_stream_2_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_data_stream_1_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_data_stream_2_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
begin
image_filter_Block_proc_U0 : component image_filter_Block_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Block_proc_U0_ap_start,
ap_done => image_filter_Block_proc_U0_ap_done,
ap_continue => image_filter_Block_proc_U0_ap_continue,
ap_idle => image_filter_Block_proc_U0_ap_idle,
ap_ready => image_filter_Block_proc_U0_ap_ready,
rows => image_filter_Block_proc_U0_rows,
cols => image_filter_Block_proc_U0_cols,
ap_return_0 => image_filter_Block_proc_U0_ap_return_0,
ap_return_1 => image_filter_Block_proc_U0_ap_return_1,
ap_return_2 => image_filter_Block_proc_U0_ap_return_2,
ap_return_3 => image_filter_Block_proc_U0_ap_return_3);
image_filter_AXIvideo2Mat_U0 : component image_filter_AXIvideo2Mat
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_AXIvideo2Mat_U0_ap_start,
ap_done => image_filter_AXIvideo2Mat_U0_ap_done,
ap_continue => image_filter_AXIvideo2Mat_U0_ap_continue,
ap_idle => image_filter_AXIvideo2Mat_U0_ap_idle,
ap_ready => image_filter_AXIvideo2Mat_U0_ap_ready,
INPUT_STREAM_TDATA => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA,
INPUT_STREAM_TVALID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY,
INPUT_STREAM_TKEEP => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST,
INPUT_STREAM_TID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID,
INPUT_STREAM_TDEST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST,
img_rows_V_read => image_filter_AXIvideo2Mat_U0_img_rows_V_read,
img_cols_V_read => image_filter_AXIvideo2Mat_U0_img_cols_V_read,
img_data_stream_0_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din,
img_data_stream_0_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n,
img_data_stream_0_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write,
img_data_stream_1_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din,
img_data_stream_1_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n,
img_data_stream_1_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write,
img_data_stream_2_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din,
img_data_stream_2_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n,
img_data_stream_2_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write);
image_filter_Loop_1_proc_U0 : component image_filter_Loop_1_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Loop_1_proc_U0_ap_start,
ap_done => image_filter_Loop_1_proc_U0_ap_done,
ap_continue => image_filter_Loop_1_proc_U0_ap_continue,
ap_idle => image_filter_Loop_1_proc_U0_ap_idle,
ap_ready => image_filter_Loop_1_proc_U0_ap_ready,
rows => image_filter_Loop_1_proc_U0_rows,
cols => image_filter_Loop_1_proc_U0_cols,
img_1_data_stream_0_V_din => image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din,
img_1_data_stream_0_V_full_n => image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n,
img_1_data_stream_0_V_write => image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write,
img_1_data_stream_1_V_din => image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din,
img_1_data_stream_1_V_full_n => image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n,
img_1_data_stream_1_V_write => image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write,
img_1_data_stream_2_V_din => image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din,
img_1_data_stream_2_V_full_n => image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n,
img_1_data_stream_2_V_write => image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write,
img_0_data_stream_0_V_dout => image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout,
img_0_data_stream_0_V_empty_n => image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n,
img_0_data_stream_0_V_read => image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read,
img_0_data_stream_1_V_dout => image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout,
img_0_data_stream_1_V_empty_n => image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n,
img_0_data_stream_1_V_read => image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read,
img_0_data_stream_2_V_dout => image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout,
img_0_data_stream_2_V_empty_n => image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n,
img_0_data_stream_2_V_read => image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read,
buffer_val_0_address0 => image_filter_Loop_1_proc_U0_buffer_val_0_address0,
buffer_val_0_ce0 => image_filter_Loop_1_proc_U0_buffer_val_0_ce0,
buffer_val_0_we0 => image_filter_Loop_1_proc_U0_buffer_val_0_we0,
buffer_val_0_d0 => image_filter_Loop_1_proc_U0_buffer_val_0_d0,
buffer_val_0_q0 => image_filter_Loop_1_proc_U0_buffer_val_0_q0,
buffer_val_0_address1 => image_filter_Loop_1_proc_U0_buffer_val_0_address1,
buffer_val_0_ce1 => image_filter_Loop_1_proc_U0_buffer_val_0_ce1,
buffer_val_0_we1 => image_filter_Loop_1_proc_U0_buffer_val_0_we1,
buffer_val_0_d1 => image_filter_Loop_1_proc_U0_buffer_val_0_d1,
buffer_val_0_q1 => image_filter_Loop_1_proc_U0_buffer_val_0_q1,
buffer_val_1_address0 => image_filter_Loop_1_proc_U0_buffer_val_1_address0,
buffer_val_1_ce0 => image_filter_Loop_1_proc_U0_buffer_val_1_ce0,
buffer_val_1_we0 => image_filter_Loop_1_proc_U0_buffer_val_1_we0,
buffer_val_1_d0 => image_filter_Loop_1_proc_U0_buffer_val_1_d0,
buffer_val_1_q0 => image_filter_Loop_1_proc_U0_buffer_val_1_q0,
buffer_val_1_address1 => image_filter_Loop_1_proc_U0_buffer_val_1_address1,
buffer_val_1_ce1 => image_filter_Loop_1_proc_U0_buffer_val_1_ce1,
buffer_val_1_we1 => image_filter_Loop_1_proc_U0_buffer_val_1_we1,
buffer_val_1_d1 => image_filter_Loop_1_proc_U0_buffer_val_1_d1,
buffer_val_1_q1 => image_filter_Loop_1_proc_U0_buffer_val_1_q1,
buffer_val_2_address0 => image_filter_Loop_1_proc_U0_buffer_val_2_address0,
buffer_val_2_ce0 => image_filter_Loop_1_proc_U0_buffer_val_2_ce0,
buffer_val_2_we0 => image_filter_Loop_1_proc_U0_buffer_val_2_we0,
buffer_val_2_d0 => image_filter_Loop_1_proc_U0_buffer_val_2_d0,
buffer_val_2_q0 => image_filter_Loop_1_proc_U0_buffer_val_2_q0,
buffer_val_2_address1 => image_filter_Loop_1_proc_U0_buffer_val_2_address1,
buffer_val_2_ce1 => image_filter_Loop_1_proc_U0_buffer_val_2_ce1,
buffer_val_2_we1 => image_filter_Loop_1_proc_U0_buffer_val_2_we1,
buffer_val_2_d1 => image_filter_Loop_1_proc_U0_buffer_val_2_d1,
buffer_val_2_q1 => image_filter_Loop_1_proc_U0_buffer_val_2_q1);
image_filter_Mat2AXIvideo_U0 : component image_filter_Mat2AXIvideo
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Mat2AXIvideo_U0_ap_start,
ap_done => image_filter_Mat2AXIvideo_U0_ap_done,
ap_continue => image_filter_Mat2AXIvideo_U0_ap_continue,
ap_idle => image_filter_Mat2AXIvideo_U0_ap_idle,
ap_ready => image_filter_Mat2AXIvideo_U0_ap_ready,
img_rows_V_read => image_filter_Mat2AXIvideo_U0_img_rows_V_read,
img_cols_V_read => image_filter_Mat2AXIvideo_U0_img_cols_V_read,
img_data_stream_0_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout,
img_data_stream_0_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n,
img_data_stream_0_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read,
img_data_stream_1_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout,
img_data_stream_1_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n,
img_data_stream_1_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read,
img_data_stream_2_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout,
img_data_stream_2_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n,
img_data_stream_2_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read,
OUTPUT_STREAM_TDATA => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TVALID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY,
OUTPUT_STREAM_TKEEP => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST);
img_0_rows_V_channel_U : component FIFO_image_filter_img_0_rows_V_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_rows_V_channel_U_ap_dummy_ce,
if_write_ce => img_0_rows_V_channel_U_ap_dummy_ce,
if_din => img_0_rows_V_channel_din,
if_full_n => img_0_rows_V_channel_full_n,
if_write => img_0_rows_V_channel_write,
if_dout => img_0_rows_V_channel_dout,
if_empty_n => img_0_rows_V_channel_empty_n,
if_read => img_0_rows_V_channel_read);
img_0_cols_V_channel_U : component FIFO_image_filter_img_0_cols_V_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_cols_V_channel_U_ap_dummy_ce,
if_write_ce => img_0_cols_V_channel_U_ap_dummy_ce,
if_din => img_0_cols_V_channel_din,
if_full_n => img_0_cols_V_channel_full_n,
if_write => img_0_cols_V_channel_write,
if_dout => img_0_cols_V_channel_dout,
if_empty_n => img_0_cols_V_channel_empty_n,
if_read => img_0_cols_V_channel_read);
img_1_rows_V_U : component FIFO_image_filter_img_1_rows_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_rows_V_U_ap_dummy_ce,
if_write_ce => img_1_rows_V_U_ap_dummy_ce,
if_din => img_1_rows_V_din,
if_full_n => img_1_rows_V_full_n,
if_write => img_1_rows_V_write,
if_dout => img_1_rows_V_dout,
if_empty_n => img_1_rows_V_empty_n,
if_read => img_1_rows_V_read);
img_1_cols_V_U : component FIFO_image_filter_img_1_cols_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_cols_V_U_ap_dummy_ce,
if_write_ce => img_1_cols_V_U_ap_dummy_ce,
if_din => img_1_cols_V_din,
if_full_n => img_1_cols_V_full_n,
if_write => img_1_cols_V_write,
if_dout => img_1_cols_V_dout,
if_empty_n => img_1_cols_V_empty_n,
if_read => img_1_cols_V_read);
img_0_data_stream_0_V_U : component FIFO_image_filter_img_0_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => img_0_data_stream_0_V_U_ap_dummy_ce,
if_din => img_0_data_stream_0_V_din,
if_full_n => img_0_data_stream_0_V_full_n,
if_write => img_0_data_stream_0_V_write,
if_dout => img_0_data_stream_0_V_dout,
if_empty_n => img_0_data_stream_0_V_empty_n,
if_read => img_0_data_stream_0_V_read);
img_0_data_stream_1_V_U : component FIFO_image_filter_img_0_data_stream_1_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_data_stream_1_V_U_ap_dummy_ce,
if_write_ce => img_0_data_stream_1_V_U_ap_dummy_ce,
if_din => img_0_data_stream_1_V_din,
if_full_n => img_0_data_stream_1_V_full_n,
if_write => img_0_data_stream_1_V_write,
if_dout => img_0_data_stream_1_V_dout,
if_empty_n => img_0_data_stream_1_V_empty_n,
if_read => img_0_data_stream_1_V_read);
img_0_data_stream_2_V_U : component FIFO_image_filter_img_0_data_stream_2_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_data_stream_2_V_U_ap_dummy_ce,
if_write_ce => img_0_data_stream_2_V_U_ap_dummy_ce,
if_din => img_0_data_stream_2_V_din,
if_full_n => img_0_data_stream_2_V_full_n,
if_write => img_0_data_stream_2_V_write,
if_dout => img_0_data_stream_2_V_dout,
if_empty_n => img_0_data_stream_2_V_empty_n,
if_read => img_0_data_stream_2_V_read);
img_1_data_stream_0_V_U : component FIFO_image_filter_img_1_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => img_1_data_stream_0_V_U_ap_dummy_ce,
if_din => img_1_data_stream_0_V_din,
if_full_n => img_1_data_stream_0_V_full_n,
if_write => img_1_data_stream_0_V_write,
if_dout => img_1_data_stream_0_V_dout,
if_empty_n => img_1_data_stream_0_V_empty_n,
if_read => img_1_data_stream_0_V_read);
img_1_data_stream_1_V_U : component FIFO_image_filter_img_1_data_stream_1_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_data_stream_1_V_U_ap_dummy_ce,
if_write_ce => img_1_data_stream_1_V_U_ap_dummy_ce,
if_din => img_1_data_stream_1_V_din,
if_full_n => img_1_data_stream_1_V_full_n,
if_write => img_1_data_stream_1_V_write,
if_dout => img_1_data_stream_1_V_dout,
if_empty_n => img_1_data_stream_1_V_empty_n,
if_read => img_1_data_stream_1_V_read);
img_1_data_stream_2_V_U : component FIFO_image_filter_img_1_data_stream_2_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_data_stream_2_V_U_ap_dummy_ce,
if_write_ce => img_1_data_stream_2_V_U_ap_dummy_ce,
if_din => img_1_data_stream_2_V_din,
if_full_n => img_1_data_stream_2_V_full_n,
if_write => img_1_data_stream_2_V_write,
if_dout => img_1_data_stream_2_V_dout,
if_empty_n => img_1_data_stream_2_V_empty_n,
if_read => img_1_data_stream_2_V_read);
-- ap_reg_procdone_image_filter_AXIvideo2Mat_U0 assign process. --
ap_reg_procdone_image_filter_AXIvideo2Mat_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_done)) then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Block_proc_U0 assign process. --
ap_reg_procdone_image_filter_Block_proc_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
elsif ((image_filter_Block_proc_U0_ap_done = ap_const_logic_1)) then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Loop_1_proc_U0 assign process. --
ap_reg_procdone_image_filter_Loop_1_proc_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_Loop_1_proc_U0_ap_done)) then
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Mat2AXIvideo_U0 assign process. --
ap_reg_procdone_image_filter_Mat2AXIvideo_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_0_cols_V_channel_full_n assign process. --
ap_reg_ready_img_0_cols_V_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = img_0_cols_V_channel_full_n))) then
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_0_rows_V_channel_full_n assign process. --
ap_reg_ready_img_0_rows_V_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = img_0_rows_V_channel_full_n))) then
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_1_cols_V_full_n assign process. --
ap_reg_ready_img_1_cols_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = img_1_cols_V_full_n))) then
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_1_rows_V_full_n assign process. --
ap_reg_ready_img_1_rows_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (img_1_rows_V_full_n = ap_const_logic_1))) then
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_CS assign process. --
ap_CS_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
ap_CS <= ap_const_logic_0;
end if;
end process;
INPUT_STREAM_TREADY <= image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY;
OUTPUT_STREAM_TDATA <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA;
OUTPUT_STREAM_TDEST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST;
OUTPUT_STREAM_TID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID;
OUTPUT_STREAM_TKEEP <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP;
OUTPUT_STREAM_TLAST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST;
OUTPUT_STREAM_TSTRB <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB;
OUTPUT_STREAM_TUSER <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER;
OUTPUT_STREAM_TVALID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID;
-- ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_0_cols_V_channel_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_img_0_cols_V_channel_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_0_rows_V_channel_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_img_0_rows_V_channel_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_1_cols_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_img_1_cols_V_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_1_rows_V_full_n)
begin
if ((ap_reg_ready_img_1_rows_V_full_n = ap_const_logic_1)) then
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
ap_done <= ap_sig_hs_done;
-- ap_idle assign process. --
ap_idle_assign_proc : process(image_filter_Block_proc_U0_ap_idle, image_filter_AXIvideo2Mat_U0_ap_idle, image_filter_Loop_1_proc_U0_ap_idle, image_filter_Mat2AXIvideo_U0_ap_idle, img_0_rows_V_channel_empty_n, img_0_cols_V_channel_empty_n, img_1_rows_V_empty_n, img_1_cols_V_empty_n)
begin
if (((image_filter_Block_proc_U0_ap_idle = ap_const_logic_1) and (ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_idle) and (ap_const_logic_1 = image_filter_Loop_1_proc_U0_ap_idle) and (ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_idle) and (ap_const_logic_0 = img_0_rows_V_channel_empty_n) and (ap_const_logic_0 = img_0_cols_V_channel_empty_n) and (ap_const_logic_0 = img_1_rows_V_empty_n) and (ap_const_logic_0 = img_1_cols_V_empty_n))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= ap_sig_top_allready;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_hs_continue <= ap_const_logic_1;
-- ap_sig_hs_done assign process. --
ap_sig_hs_done_assign_proc : process(image_filter_Mat2AXIvideo_U0_ap_done)
begin
if ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then
ap_sig_hs_done <= ap_const_logic_1;
else
ap_sig_hs_done <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ready_img_0_cols_V_channel_full_n assign process. --
ap_sig_ready_img_0_cols_V_channel_full_n_assign_proc : process(img_0_cols_V_channel_full_n, ap_reg_ready_img_0_cols_V_channel_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_img_0_cols_V_channel_full_n)) then
ap_sig_ready_img_0_cols_V_channel_full_n <= img_0_cols_V_channel_full_n;
else
ap_sig_ready_img_0_cols_V_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_img_0_rows_V_channel_full_n assign process. --
ap_sig_ready_img_0_rows_V_channel_full_n_assign_proc : process(img_0_rows_V_channel_full_n, ap_reg_ready_img_0_rows_V_channel_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_img_0_rows_V_channel_full_n)) then
ap_sig_ready_img_0_rows_V_channel_full_n <= img_0_rows_V_channel_full_n;
else
ap_sig_ready_img_0_rows_V_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_img_1_cols_V_full_n assign process. --
ap_sig_ready_img_1_cols_V_full_n_assign_proc : process(img_1_cols_V_full_n, ap_reg_ready_img_1_cols_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_img_1_cols_V_full_n)) then
ap_sig_ready_img_1_cols_V_full_n <= img_1_cols_V_full_n;
else
ap_sig_ready_img_1_cols_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_img_1_rows_V_full_n assign process. --
ap_sig_ready_img_1_rows_V_full_n_assign_proc : process(img_1_rows_V_full_n, ap_reg_ready_img_1_rows_V_full_n)
begin
if ((ap_reg_ready_img_1_rows_V_full_n = ap_const_logic_0)) then
ap_sig_ready_img_1_rows_V_full_n <= img_1_rows_V_full_n;
else
ap_sig_ready_img_1_rows_V_full_n <= ap_const_logic_1;
end if;
end process;
ap_sig_top_allready <= image_filter_AXIvideo2Mat_U0_ap_ready;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA <= INPUT_STREAM_TDATA;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST <= INPUT_STREAM_TDEST;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID <= INPUT_STREAM_TID;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP <= INPUT_STREAM_TKEEP;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST <= INPUT_STREAM_TLAST;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB <= INPUT_STREAM_TSTRB;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER <= INPUT_STREAM_TUSER;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID <= INPUT_STREAM_TVALID;
image_filter_AXIvideo2Mat_U0_ap_continue <= ap_const_logic_1;
image_filter_AXIvideo2Mat_U0_ap_start <= (ap_start and img_0_rows_V_channel_empty_n and img_0_cols_V_channel_empty_n);
image_filter_AXIvideo2Mat_U0_img_cols_V_read <= img_0_cols_V_channel_dout;
image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n <= img_0_data_stream_0_V_full_n;
image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n <= img_0_data_stream_1_V_full_n;
image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n <= img_0_data_stream_2_V_full_n;
image_filter_AXIvideo2Mat_U0_img_rows_V_read <= img_0_rows_V_channel_dout;
-- image_filter_Block_proc_U0_ap_continue assign process. --
image_filter_Block_proc_U0_ap_continue_assign_proc : process(ap_sig_ready_img_1_rows_V_full_n, ap_sig_ready_img_0_rows_V_channel_full_n, ap_sig_ready_img_1_cols_V_full_n, ap_sig_ready_img_0_cols_V_channel_full_n)
begin
if (((ap_sig_ready_img_1_rows_V_full_n = ap_const_logic_1) and (ap_const_logic_1 = ap_sig_ready_img_0_rows_V_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_img_1_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_img_0_cols_V_channel_full_n))) then
image_filter_Block_proc_U0_ap_continue <= ap_const_logic_1;
else
image_filter_Block_proc_U0_ap_continue <= ap_const_logic_0;
end if;
end process;
image_filter_Block_proc_U0_ap_start <= ap_start;
image_filter_Block_proc_U0_cols <= cols;
image_filter_Block_proc_U0_rows <= rows;
image_filter_Loop_1_proc_U0_ap_continue <= ap_const_logic_1;
image_filter_Loop_1_proc_U0_ap_start <= ap_start;
image_filter_Loop_1_proc_U0_buffer_val_0_q0 <= ap_const_lv8_0;
image_filter_Loop_1_proc_U0_buffer_val_0_q1 <= ap_const_lv8_0;
image_filter_Loop_1_proc_U0_buffer_val_1_q0 <= ap_const_lv8_0;
image_filter_Loop_1_proc_U0_buffer_val_1_q1 <= ap_const_lv8_0;
image_filter_Loop_1_proc_U0_buffer_val_2_q0 <= ap_const_lv8_0;
image_filter_Loop_1_proc_U0_buffer_val_2_q1 <= ap_const_lv8_0;
image_filter_Loop_1_proc_U0_cols <= cols;
image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout <= img_0_data_stream_0_V_dout;
image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n <= img_0_data_stream_0_V_empty_n;
image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout <= img_0_data_stream_1_V_dout;
image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n <= img_0_data_stream_1_V_empty_n;
image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout <= img_0_data_stream_2_V_dout;
image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n <= img_0_data_stream_2_V_empty_n;
image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n <= img_1_data_stream_0_V_full_n;
image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n <= img_1_data_stream_1_V_full_n;
image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n <= img_1_data_stream_2_V_full_n;
image_filter_Loop_1_proc_U0_rows <= rows;
image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY <= OUTPUT_STREAM_TREADY;
image_filter_Mat2AXIvideo_U0_ap_continue <= ap_sig_hs_continue;
image_filter_Mat2AXIvideo_U0_ap_start <= (img_1_rows_V_empty_n and img_1_cols_V_empty_n);
image_filter_Mat2AXIvideo_U0_img_cols_V_read <= img_1_cols_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout <= img_1_data_stream_0_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n <= img_1_data_stream_0_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout <= img_1_data_stream_1_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n <= img_1_data_stream_1_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout <= img_1_data_stream_2_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n <= img_1_data_stream_2_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_rows_V_read <= img_1_rows_V_dout;
img_0_cols_V_channel_U_ap_dummy_ce <= ap_const_logic_1;
img_0_cols_V_channel_din <= image_filter_Block_proc_U0_ap_return_1;
img_0_cols_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready;
img_0_cols_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel;
img_0_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
img_0_data_stream_0_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din;
img_0_data_stream_0_V_read <= image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read;
img_0_data_stream_0_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write;
img_0_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1;
img_0_data_stream_1_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din;
img_0_data_stream_1_V_read <= image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read;
img_0_data_stream_1_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write;
img_0_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1;
img_0_data_stream_2_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din;
img_0_data_stream_2_V_read <= image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read;
img_0_data_stream_2_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write;
img_0_rows_V_channel_U_ap_dummy_ce <= ap_const_logic_1;
img_0_rows_V_channel_din <= image_filter_Block_proc_U0_ap_return_0;
img_0_rows_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready;
img_0_rows_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel;
img_1_cols_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_cols_V_din <= image_filter_Block_proc_U0_ap_return_3;
img_1_cols_V_read <= image_filter_Mat2AXIvideo_U0_ap_ready;
img_1_cols_V_write <= ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V;
img_1_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_data_stream_0_V_din <= image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din;
img_1_data_stream_0_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read;
img_1_data_stream_0_V_write <= image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write;
img_1_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_data_stream_1_V_din <= image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din;
img_1_data_stream_1_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read;
img_1_data_stream_1_V_write <= image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write;
img_1_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_data_stream_2_V_din <= image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din;
img_1_data_stream_2_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read;
img_1_data_stream_2_V_write <= image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write;
img_1_rows_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_rows_V_din <= image_filter_Block_proc_U0_ap_return_2;
img_1_rows_V_read <= image_filter_Mat2AXIvideo_U0_ap_ready;
img_1_rows_V_write <= ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter is
port (
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0);
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
OUTPUT_STREAM_TVALID : OUT STD_LOGIC;
OUTPUT_STREAM_TREADY : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC );
end;
architecture behav of image_filter is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"image_filter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=6.666670,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=5.758000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=586,HLS_SYN_LUT=990}";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_true : BOOLEAN := true;
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
signal ap_rst_n_inv : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_start : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_done : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_continue : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_idle : STD_LOGIC;
signal image_filter_Block_proc_U0_ap_ready : STD_LOGIC;
signal image_filter_Block_proc_U0_rows : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Block_proc_U0_cols : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Block_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_2 : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Block_proc_U0_ap_return_3 : STD_LOGIC_VECTOR (11 downto 0);
signal ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V : STD_LOGIC;
signal img_1_rows_V_full_n : STD_LOGIC;
signal ap_reg_ready_img_1_rows_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_1_rows_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel : STD_LOGIC;
signal img_0_rows_V_channel_full_n : STD_LOGIC;
signal ap_reg_ready_img_0_rows_V_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_0_rows_V_channel_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V : STD_LOGIC;
signal img_1_cols_V_full_n : STD_LOGIC;
signal ap_reg_ready_img_1_cols_V_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_1_cols_V_full_n : STD_LOGIC;
signal ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel : STD_LOGIC;
signal img_0_cols_V_channel_full_n : STD_LOGIC;
signal ap_reg_ready_img_0_cols_V_channel_full_n : STD_LOGIC := '0';
signal ap_sig_ready_img_0_cols_V_channel_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_start : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_done : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_continue : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_idle : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_ap_ready : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n : STD_LOGIC;
signal image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_start : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_done : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_continue : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_idle : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_ap_ready : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_rows : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Loop_1_proc_U0_cols : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_0_address0 : STD_LOGIC_VECTOR (1 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_0_ce0 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_0_we0 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_0_d0 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_0_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_0_address1 : STD_LOGIC_VECTOR (1 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_0_ce1 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_0_we1 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_0_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_0_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_1_address0 : STD_LOGIC_VECTOR (1 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_1_ce0 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_1_we0 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_1_d0 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_1_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_1_address1 : STD_LOGIC_VECTOR (1 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_1_ce1 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_1_we1 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_1_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_1_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_2_address0 : STD_LOGIC_VECTOR (1 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_2_ce0 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_2_we0 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_2_d0 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_2_q0 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_2_address1 : STD_LOGIC_VECTOR (1 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_2_ce1 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_2_we1 : STD_LOGIC;
signal image_filter_Loop_1_proc_U0_buffer_val_2_d1 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Loop_1_proc_U0_buffer_val_2_q1 : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_ap_start : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_done : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_continue : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_idle : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_ap_ready : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_rows_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_cols_V_read : STD_LOGIC_VECTOR (11 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA : STD_LOGIC_VECTOR (31 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY : STD_LOGIC;
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID : STD_LOGIC_VECTOR (0 downto 0);
signal image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_hs_continue : STD_LOGIC;
signal img_0_rows_V_channel_U_ap_dummy_ce : STD_LOGIC;
signal img_0_rows_V_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_rows_V_channel_write : STD_LOGIC;
signal img_0_rows_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_rows_V_channel_empty_n : STD_LOGIC;
signal img_0_rows_V_channel_read : STD_LOGIC;
signal img_0_cols_V_channel_U_ap_dummy_ce : STD_LOGIC;
signal img_0_cols_V_channel_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_cols_V_channel_write : STD_LOGIC;
signal img_0_cols_V_channel_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_0_cols_V_channel_empty_n : STD_LOGIC;
signal img_0_cols_V_channel_read : STD_LOGIC;
signal img_1_rows_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_rows_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_rows_V_write : STD_LOGIC;
signal img_1_rows_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_rows_V_empty_n : STD_LOGIC;
signal img_1_rows_V_read : STD_LOGIC;
signal img_1_cols_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_cols_V_din : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_cols_V_write : STD_LOGIC;
signal img_1_cols_V_dout : STD_LOGIC_VECTOR (11 downto 0);
signal img_1_cols_V_empty_n : STD_LOGIC;
signal img_1_cols_V_read : STD_LOGIC;
signal img_0_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal img_0_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_0_V_full_n : STD_LOGIC;
signal img_0_data_stream_0_V_write : STD_LOGIC;
signal img_0_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_0_V_empty_n : STD_LOGIC;
signal img_0_data_stream_0_V_read : STD_LOGIC;
signal img_0_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC;
signal img_0_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_1_V_full_n : STD_LOGIC;
signal img_0_data_stream_1_V_write : STD_LOGIC;
signal img_0_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_1_V_empty_n : STD_LOGIC;
signal img_0_data_stream_1_V_read : STD_LOGIC;
signal img_0_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC;
signal img_0_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_2_V_full_n : STD_LOGIC;
signal img_0_data_stream_2_V_write : STD_LOGIC;
signal img_0_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_0_data_stream_2_V_empty_n : STD_LOGIC;
signal img_0_data_stream_2_V_read : STD_LOGIC;
signal img_1_data_stream_0_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_data_stream_0_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_0_V_full_n : STD_LOGIC;
signal img_1_data_stream_0_V_write : STD_LOGIC;
signal img_1_data_stream_0_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_0_V_empty_n : STD_LOGIC;
signal img_1_data_stream_0_V_read : STD_LOGIC;
signal img_1_data_stream_1_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_data_stream_1_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_1_V_full_n : STD_LOGIC;
signal img_1_data_stream_1_V_write : STD_LOGIC;
signal img_1_data_stream_1_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_1_V_empty_n : STD_LOGIC;
signal img_1_data_stream_1_V_read : STD_LOGIC;
signal img_1_data_stream_2_V_U_ap_dummy_ce : STD_LOGIC;
signal img_1_data_stream_2_V_din : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_2_V_full_n : STD_LOGIC;
signal img_1_data_stream_2_V_write : STD_LOGIC;
signal img_1_data_stream_2_V_dout : STD_LOGIC_VECTOR (7 downto 0);
signal img_1_data_stream_2_V_empty_n : STD_LOGIC;
signal img_1_data_stream_2_V_read : STD_LOGIC;
signal ap_reg_procdone_image_filter_Block_proc_U0 : STD_LOGIC := '0';
signal ap_sig_hs_done : STD_LOGIC;
signal ap_reg_procdone_image_filter_AXIvideo2Mat_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_Loop_1_proc_U0 : STD_LOGIC := '0';
signal ap_reg_procdone_image_filter_Mat2AXIvideo_U0 : STD_LOGIC := '0';
signal ap_CS : STD_LOGIC;
signal ap_sig_top_allready : STD_LOGIC;
component image_filter_Block_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_2 : OUT STD_LOGIC_VECTOR (11 downto 0);
ap_return_3 : OUT STD_LOGIC_VECTOR (11 downto 0) );
end component;
component image_filter_AXIvideo2Mat IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC );
end component;
component image_filter_Loop_1_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
rows : IN STD_LOGIC_VECTOR (31 downto 0);
cols : IN STD_LOGIC_VECTOR (31 downto 0);
img_1_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_0_V_full_n : IN STD_LOGIC;
img_1_data_stream_0_V_write : OUT STD_LOGIC;
img_1_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_1_V_full_n : IN STD_LOGIC;
img_1_data_stream_1_V_write : OUT STD_LOGIC;
img_1_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_1_data_stream_2_V_full_n : IN STD_LOGIC;
img_1_data_stream_2_V_write : OUT STD_LOGIC;
img_0_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_0_V_empty_n : IN STD_LOGIC;
img_0_data_stream_0_V_read : OUT STD_LOGIC;
img_0_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_1_V_empty_n : IN STD_LOGIC;
img_0_data_stream_1_V_read : OUT STD_LOGIC;
img_0_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_0_data_stream_2_V_empty_n : IN STD_LOGIC;
img_0_data_stream_2_V_read : OUT STD_LOGIC;
buffer_val_0_address0 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_0_ce0 : OUT STD_LOGIC;
buffer_val_0_we0 : OUT STD_LOGIC;
buffer_val_0_d0 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_0_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_0_address1 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_0_ce1 : OUT STD_LOGIC;
buffer_val_0_we1 : OUT STD_LOGIC;
buffer_val_0_d1 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_0_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_1_address0 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_1_ce0 : OUT STD_LOGIC;
buffer_val_1_we0 : OUT STD_LOGIC;
buffer_val_1_d0 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_1_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_1_address1 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_1_ce1 : OUT STD_LOGIC;
buffer_val_1_we1 : OUT STD_LOGIC;
buffer_val_1_d1 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_1_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_2_address0 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_2_ce0 : OUT STD_LOGIC;
buffer_val_2_we0 : OUT STD_LOGIC;
buffer_val_2_d0 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_2_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
buffer_val_2_address1 : OUT STD_LOGIC_VECTOR (1 downto 0);
buffer_val_2_ce1 : OUT STD_LOGIC;
buffer_val_2_we1 : OUT STD_LOGIC;
buffer_val_2_d1 : OUT STD_LOGIC_VECTOR (7 downto 0);
buffer_val_2_q1 : IN STD_LOGIC_VECTOR (7 downto 0) );
end component;
component image_filter_Mat2AXIvideo IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_empty_n : IN STD_LOGIC;
img_data_stream_0_V_read : OUT STD_LOGIC;
img_data_stream_1_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_empty_n : IN STD_LOGIC;
img_data_stream_1_V_read : OUT STD_LOGIC;
img_data_stream_2_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_empty_n : IN STD_LOGIC;
img_data_stream_2_V_read : OUT STD_LOGIC;
OUTPUT_STREAM_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
OUTPUT_STREAM_TVALID : OUT STD_LOGIC;
OUTPUT_STREAM_TREADY : IN STD_LOGIC;
OUTPUT_STREAM_TKEEP : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
OUTPUT_STREAM_TUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TLAST : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TID : OUT STD_LOGIC_VECTOR (0 downto 0);
OUTPUT_STREAM_TDEST : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component FIFO_image_filter_img_0_rows_V_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_cols_V_channel IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_rows_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_cols_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (11 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (11 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_data_stream_1_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_0_data_stream_2_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_data_stream_0_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_data_stream_1_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
component FIFO_image_filter_img_1_data_stream_2_V IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (7 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (7 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
begin
image_filter_Block_proc_U0 : component image_filter_Block_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Block_proc_U0_ap_start,
ap_done => image_filter_Block_proc_U0_ap_done,
ap_continue => image_filter_Block_proc_U0_ap_continue,
ap_idle => image_filter_Block_proc_U0_ap_idle,
ap_ready => image_filter_Block_proc_U0_ap_ready,
rows => image_filter_Block_proc_U0_rows,
cols => image_filter_Block_proc_U0_cols,
ap_return_0 => image_filter_Block_proc_U0_ap_return_0,
ap_return_1 => image_filter_Block_proc_U0_ap_return_1,
ap_return_2 => image_filter_Block_proc_U0_ap_return_2,
ap_return_3 => image_filter_Block_proc_U0_ap_return_3);
image_filter_AXIvideo2Mat_U0 : component image_filter_AXIvideo2Mat
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_AXIvideo2Mat_U0_ap_start,
ap_done => image_filter_AXIvideo2Mat_U0_ap_done,
ap_continue => image_filter_AXIvideo2Mat_U0_ap_continue,
ap_idle => image_filter_AXIvideo2Mat_U0_ap_idle,
ap_ready => image_filter_AXIvideo2Mat_U0_ap_ready,
INPUT_STREAM_TDATA => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA,
INPUT_STREAM_TVALID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY,
INPUT_STREAM_TKEEP => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST,
INPUT_STREAM_TID => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID,
INPUT_STREAM_TDEST => image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST,
img_rows_V_read => image_filter_AXIvideo2Mat_U0_img_rows_V_read,
img_cols_V_read => image_filter_AXIvideo2Mat_U0_img_cols_V_read,
img_data_stream_0_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din,
img_data_stream_0_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n,
img_data_stream_0_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write,
img_data_stream_1_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din,
img_data_stream_1_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n,
img_data_stream_1_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write,
img_data_stream_2_V_din => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din,
img_data_stream_2_V_full_n => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n,
img_data_stream_2_V_write => image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write);
image_filter_Loop_1_proc_U0 : component image_filter_Loop_1_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Loop_1_proc_U0_ap_start,
ap_done => image_filter_Loop_1_proc_U0_ap_done,
ap_continue => image_filter_Loop_1_proc_U0_ap_continue,
ap_idle => image_filter_Loop_1_proc_U0_ap_idle,
ap_ready => image_filter_Loop_1_proc_U0_ap_ready,
rows => image_filter_Loop_1_proc_U0_rows,
cols => image_filter_Loop_1_proc_U0_cols,
img_1_data_stream_0_V_din => image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din,
img_1_data_stream_0_V_full_n => image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n,
img_1_data_stream_0_V_write => image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write,
img_1_data_stream_1_V_din => image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din,
img_1_data_stream_1_V_full_n => image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n,
img_1_data_stream_1_V_write => image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write,
img_1_data_stream_2_V_din => image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din,
img_1_data_stream_2_V_full_n => image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n,
img_1_data_stream_2_V_write => image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write,
img_0_data_stream_0_V_dout => image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout,
img_0_data_stream_0_V_empty_n => image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n,
img_0_data_stream_0_V_read => image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read,
img_0_data_stream_1_V_dout => image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout,
img_0_data_stream_1_V_empty_n => image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n,
img_0_data_stream_1_V_read => image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read,
img_0_data_stream_2_V_dout => image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout,
img_0_data_stream_2_V_empty_n => image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n,
img_0_data_stream_2_V_read => image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read,
buffer_val_0_address0 => image_filter_Loop_1_proc_U0_buffer_val_0_address0,
buffer_val_0_ce0 => image_filter_Loop_1_proc_U0_buffer_val_0_ce0,
buffer_val_0_we0 => image_filter_Loop_1_proc_U0_buffer_val_0_we0,
buffer_val_0_d0 => image_filter_Loop_1_proc_U0_buffer_val_0_d0,
buffer_val_0_q0 => image_filter_Loop_1_proc_U0_buffer_val_0_q0,
buffer_val_0_address1 => image_filter_Loop_1_proc_U0_buffer_val_0_address1,
buffer_val_0_ce1 => image_filter_Loop_1_proc_U0_buffer_val_0_ce1,
buffer_val_0_we1 => image_filter_Loop_1_proc_U0_buffer_val_0_we1,
buffer_val_0_d1 => image_filter_Loop_1_proc_U0_buffer_val_0_d1,
buffer_val_0_q1 => image_filter_Loop_1_proc_U0_buffer_val_0_q1,
buffer_val_1_address0 => image_filter_Loop_1_proc_U0_buffer_val_1_address0,
buffer_val_1_ce0 => image_filter_Loop_1_proc_U0_buffer_val_1_ce0,
buffer_val_1_we0 => image_filter_Loop_1_proc_U0_buffer_val_1_we0,
buffer_val_1_d0 => image_filter_Loop_1_proc_U0_buffer_val_1_d0,
buffer_val_1_q0 => image_filter_Loop_1_proc_U0_buffer_val_1_q0,
buffer_val_1_address1 => image_filter_Loop_1_proc_U0_buffer_val_1_address1,
buffer_val_1_ce1 => image_filter_Loop_1_proc_U0_buffer_val_1_ce1,
buffer_val_1_we1 => image_filter_Loop_1_proc_U0_buffer_val_1_we1,
buffer_val_1_d1 => image_filter_Loop_1_proc_U0_buffer_val_1_d1,
buffer_val_1_q1 => image_filter_Loop_1_proc_U0_buffer_val_1_q1,
buffer_val_2_address0 => image_filter_Loop_1_proc_U0_buffer_val_2_address0,
buffer_val_2_ce0 => image_filter_Loop_1_proc_U0_buffer_val_2_ce0,
buffer_val_2_we0 => image_filter_Loop_1_proc_U0_buffer_val_2_we0,
buffer_val_2_d0 => image_filter_Loop_1_proc_U0_buffer_val_2_d0,
buffer_val_2_q0 => image_filter_Loop_1_proc_U0_buffer_val_2_q0,
buffer_val_2_address1 => image_filter_Loop_1_proc_U0_buffer_val_2_address1,
buffer_val_2_ce1 => image_filter_Loop_1_proc_U0_buffer_val_2_ce1,
buffer_val_2_we1 => image_filter_Loop_1_proc_U0_buffer_val_2_we1,
buffer_val_2_d1 => image_filter_Loop_1_proc_U0_buffer_val_2_d1,
buffer_val_2_q1 => image_filter_Loop_1_proc_U0_buffer_val_2_q1);
image_filter_Mat2AXIvideo_U0 : component image_filter_Mat2AXIvideo
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => image_filter_Mat2AXIvideo_U0_ap_start,
ap_done => image_filter_Mat2AXIvideo_U0_ap_done,
ap_continue => image_filter_Mat2AXIvideo_U0_ap_continue,
ap_idle => image_filter_Mat2AXIvideo_U0_ap_idle,
ap_ready => image_filter_Mat2AXIvideo_U0_ap_ready,
img_rows_V_read => image_filter_Mat2AXIvideo_U0_img_rows_V_read,
img_cols_V_read => image_filter_Mat2AXIvideo_U0_img_cols_V_read,
img_data_stream_0_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout,
img_data_stream_0_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n,
img_data_stream_0_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read,
img_data_stream_1_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout,
img_data_stream_1_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n,
img_data_stream_1_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read,
img_data_stream_2_V_dout => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout,
img_data_stream_2_V_empty_n => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n,
img_data_stream_2_V_read => image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read,
OUTPUT_STREAM_TDATA => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TVALID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY,
OUTPUT_STREAM_TKEEP => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST => image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST);
img_0_rows_V_channel_U : component FIFO_image_filter_img_0_rows_V_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_rows_V_channel_U_ap_dummy_ce,
if_write_ce => img_0_rows_V_channel_U_ap_dummy_ce,
if_din => img_0_rows_V_channel_din,
if_full_n => img_0_rows_V_channel_full_n,
if_write => img_0_rows_V_channel_write,
if_dout => img_0_rows_V_channel_dout,
if_empty_n => img_0_rows_V_channel_empty_n,
if_read => img_0_rows_V_channel_read);
img_0_cols_V_channel_U : component FIFO_image_filter_img_0_cols_V_channel
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_cols_V_channel_U_ap_dummy_ce,
if_write_ce => img_0_cols_V_channel_U_ap_dummy_ce,
if_din => img_0_cols_V_channel_din,
if_full_n => img_0_cols_V_channel_full_n,
if_write => img_0_cols_V_channel_write,
if_dout => img_0_cols_V_channel_dout,
if_empty_n => img_0_cols_V_channel_empty_n,
if_read => img_0_cols_V_channel_read);
img_1_rows_V_U : component FIFO_image_filter_img_1_rows_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_rows_V_U_ap_dummy_ce,
if_write_ce => img_1_rows_V_U_ap_dummy_ce,
if_din => img_1_rows_V_din,
if_full_n => img_1_rows_V_full_n,
if_write => img_1_rows_V_write,
if_dout => img_1_rows_V_dout,
if_empty_n => img_1_rows_V_empty_n,
if_read => img_1_rows_V_read);
img_1_cols_V_U : component FIFO_image_filter_img_1_cols_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_cols_V_U_ap_dummy_ce,
if_write_ce => img_1_cols_V_U_ap_dummy_ce,
if_din => img_1_cols_V_din,
if_full_n => img_1_cols_V_full_n,
if_write => img_1_cols_V_write,
if_dout => img_1_cols_V_dout,
if_empty_n => img_1_cols_V_empty_n,
if_read => img_1_cols_V_read);
img_0_data_stream_0_V_U : component FIFO_image_filter_img_0_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => img_0_data_stream_0_V_U_ap_dummy_ce,
if_din => img_0_data_stream_0_V_din,
if_full_n => img_0_data_stream_0_V_full_n,
if_write => img_0_data_stream_0_V_write,
if_dout => img_0_data_stream_0_V_dout,
if_empty_n => img_0_data_stream_0_V_empty_n,
if_read => img_0_data_stream_0_V_read);
img_0_data_stream_1_V_U : component FIFO_image_filter_img_0_data_stream_1_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_data_stream_1_V_U_ap_dummy_ce,
if_write_ce => img_0_data_stream_1_V_U_ap_dummy_ce,
if_din => img_0_data_stream_1_V_din,
if_full_n => img_0_data_stream_1_V_full_n,
if_write => img_0_data_stream_1_V_write,
if_dout => img_0_data_stream_1_V_dout,
if_empty_n => img_0_data_stream_1_V_empty_n,
if_read => img_0_data_stream_1_V_read);
img_0_data_stream_2_V_U : component FIFO_image_filter_img_0_data_stream_2_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_0_data_stream_2_V_U_ap_dummy_ce,
if_write_ce => img_0_data_stream_2_V_U_ap_dummy_ce,
if_din => img_0_data_stream_2_V_din,
if_full_n => img_0_data_stream_2_V_full_n,
if_write => img_0_data_stream_2_V_write,
if_dout => img_0_data_stream_2_V_dout,
if_empty_n => img_0_data_stream_2_V_empty_n,
if_read => img_0_data_stream_2_V_read);
img_1_data_stream_0_V_U : component FIFO_image_filter_img_1_data_stream_0_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_data_stream_0_V_U_ap_dummy_ce,
if_write_ce => img_1_data_stream_0_V_U_ap_dummy_ce,
if_din => img_1_data_stream_0_V_din,
if_full_n => img_1_data_stream_0_V_full_n,
if_write => img_1_data_stream_0_V_write,
if_dout => img_1_data_stream_0_V_dout,
if_empty_n => img_1_data_stream_0_V_empty_n,
if_read => img_1_data_stream_0_V_read);
img_1_data_stream_1_V_U : component FIFO_image_filter_img_1_data_stream_1_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_data_stream_1_V_U_ap_dummy_ce,
if_write_ce => img_1_data_stream_1_V_U_ap_dummy_ce,
if_din => img_1_data_stream_1_V_din,
if_full_n => img_1_data_stream_1_V_full_n,
if_write => img_1_data_stream_1_V_write,
if_dout => img_1_data_stream_1_V_dout,
if_empty_n => img_1_data_stream_1_V_empty_n,
if_read => img_1_data_stream_1_V_read);
img_1_data_stream_2_V_U : component FIFO_image_filter_img_1_data_stream_2_V
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
if_read_ce => img_1_data_stream_2_V_U_ap_dummy_ce,
if_write_ce => img_1_data_stream_2_V_U_ap_dummy_ce,
if_din => img_1_data_stream_2_V_din,
if_full_n => img_1_data_stream_2_V_full_n,
if_write => img_1_data_stream_2_V_write,
if_dout => img_1_data_stream_2_V_dout,
if_empty_n => img_1_data_stream_2_V_empty_n,
if_read => img_1_data_stream_2_V_read);
-- ap_reg_procdone_image_filter_AXIvideo2Mat_U0 assign process. --
ap_reg_procdone_image_filter_AXIvideo2Mat_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_done)) then
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Block_proc_U0 assign process. --
ap_reg_procdone_image_filter_Block_proc_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
elsif ((image_filter_Block_proc_U0_ap_done = ap_const_logic_1)) then
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Loop_1_proc_U0 assign process. --
ap_reg_procdone_image_filter_Loop_1_proc_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_Loop_1_proc_U0_ap_done)) then
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_procdone_image_filter_Mat2AXIvideo_U0 assign process. --
ap_reg_procdone_image_filter_Mat2AXIvideo_U0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_hs_done)) then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
elsif ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_0_cols_V_channel_full_n assign process. --
ap_reg_ready_img_0_cols_V_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = img_0_cols_V_channel_full_n))) then
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_0_rows_V_channel_full_n assign process. --
ap_reg_ready_img_0_rows_V_channel_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = img_0_rows_V_channel_full_n))) then
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_1_cols_V_full_n assign process. --
ap_reg_ready_img_1_cols_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (ap_const_logic_1 = img_1_cols_V_full_n))) then
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ready_img_1_rows_V_full_n assign process. --
ap_reg_ready_img_1_rows_V_full_n_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_0;
else
if (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (image_filter_Block_proc_U0_ap_continue = ap_const_logic_1))) then
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_0;
elsif (((image_filter_Block_proc_U0_ap_done = ap_const_logic_1) and (img_1_rows_V_full_n = ap_const_logic_1))) then
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_CS assign process. --
ap_CS_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
ap_CS <= ap_const_logic_0;
end if;
end process;
INPUT_STREAM_TREADY <= image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY;
OUTPUT_STREAM_TDATA <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA;
OUTPUT_STREAM_TDEST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST;
OUTPUT_STREAM_TID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID;
OUTPUT_STREAM_TKEEP <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP;
OUTPUT_STREAM_TLAST <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST;
OUTPUT_STREAM_TSTRB <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB;
OUTPUT_STREAM_TUSER <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER;
OUTPUT_STREAM_TVALID <= image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID;
-- ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_0_cols_V_channel_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_img_0_cols_V_channel_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_0_rows_V_channel_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_img_0_rows_V_channel_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_1_cols_V_full_n)
begin
if ((ap_const_logic_1 = ap_reg_ready_img_1_cols_V_full_n)) then
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
-- ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V assign process. --
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V_assign_proc : process(image_filter_Block_proc_U0_ap_done, ap_reg_ready_img_1_rows_V_full_n)
begin
if ((ap_reg_ready_img_1_rows_V_full_n = ap_const_logic_1)) then
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V <= ap_const_logic_0;
else
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V <= image_filter_Block_proc_U0_ap_done;
end if;
end process;
ap_done <= ap_sig_hs_done;
-- ap_idle assign process. --
ap_idle_assign_proc : process(image_filter_Block_proc_U0_ap_idle, image_filter_AXIvideo2Mat_U0_ap_idle, image_filter_Loop_1_proc_U0_ap_idle, image_filter_Mat2AXIvideo_U0_ap_idle, img_0_rows_V_channel_empty_n, img_0_cols_V_channel_empty_n, img_1_rows_V_empty_n, img_1_cols_V_empty_n)
begin
if (((image_filter_Block_proc_U0_ap_idle = ap_const_logic_1) and (ap_const_logic_1 = image_filter_AXIvideo2Mat_U0_ap_idle) and (ap_const_logic_1 = image_filter_Loop_1_proc_U0_ap_idle) and (ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_idle) and (ap_const_logic_0 = img_0_rows_V_channel_empty_n) and (ap_const_logic_0 = img_0_cols_V_channel_empty_n) and (ap_const_logic_0 = img_1_rows_V_empty_n) and (ap_const_logic_0 = img_1_cols_V_empty_n))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready <= ap_sig_top_allready;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
ap_sig_hs_continue <= ap_const_logic_1;
-- ap_sig_hs_done assign process. --
ap_sig_hs_done_assign_proc : process(image_filter_Mat2AXIvideo_U0_ap_done)
begin
if ((ap_const_logic_1 = image_filter_Mat2AXIvideo_U0_ap_done)) then
ap_sig_hs_done <= ap_const_logic_1;
else
ap_sig_hs_done <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ready_img_0_cols_V_channel_full_n assign process. --
ap_sig_ready_img_0_cols_V_channel_full_n_assign_proc : process(img_0_cols_V_channel_full_n, ap_reg_ready_img_0_cols_V_channel_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_img_0_cols_V_channel_full_n)) then
ap_sig_ready_img_0_cols_V_channel_full_n <= img_0_cols_V_channel_full_n;
else
ap_sig_ready_img_0_cols_V_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_img_0_rows_V_channel_full_n assign process. --
ap_sig_ready_img_0_rows_V_channel_full_n_assign_proc : process(img_0_rows_V_channel_full_n, ap_reg_ready_img_0_rows_V_channel_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_img_0_rows_V_channel_full_n)) then
ap_sig_ready_img_0_rows_V_channel_full_n <= img_0_rows_V_channel_full_n;
else
ap_sig_ready_img_0_rows_V_channel_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_img_1_cols_V_full_n assign process. --
ap_sig_ready_img_1_cols_V_full_n_assign_proc : process(img_1_cols_V_full_n, ap_reg_ready_img_1_cols_V_full_n)
begin
if ((ap_const_logic_0 = ap_reg_ready_img_1_cols_V_full_n)) then
ap_sig_ready_img_1_cols_V_full_n <= img_1_cols_V_full_n;
else
ap_sig_ready_img_1_cols_V_full_n <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ready_img_1_rows_V_full_n assign process. --
ap_sig_ready_img_1_rows_V_full_n_assign_proc : process(img_1_rows_V_full_n, ap_reg_ready_img_1_rows_V_full_n)
begin
if ((ap_reg_ready_img_1_rows_V_full_n = ap_const_logic_0)) then
ap_sig_ready_img_1_rows_V_full_n <= img_1_rows_V_full_n;
else
ap_sig_ready_img_1_rows_V_full_n <= ap_const_logic_1;
end if;
end process;
ap_sig_top_allready <= image_filter_AXIvideo2Mat_U0_ap_ready;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA <= INPUT_STREAM_TDATA;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST <= INPUT_STREAM_TDEST;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID <= INPUT_STREAM_TID;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP <= INPUT_STREAM_TKEEP;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST <= INPUT_STREAM_TLAST;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB <= INPUT_STREAM_TSTRB;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER <= INPUT_STREAM_TUSER;
image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID <= INPUT_STREAM_TVALID;
image_filter_AXIvideo2Mat_U0_ap_continue <= ap_const_logic_1;
image_filter_AXIvideo2Mat_U0_ap_start <= (ap_start and img_0_rows_V_channel_empty_n and img_0_cols_V_channel_empty_n);
image_filter_AXIvideo2Mat_U0_img_cols_V_read <= img_0_cols_V_channel_dout;
image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n <= img_0_data_stream_0_V_full_n;
image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n <= img_0_data_stream_1_V_full_n;
image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n <= img_0_data_stream_2_V_full_n;
image_filter_AXIvideo2Mat_U0_img_rows_V_read <= img_0_rows_V_channel_dout;
-- image_filter_Block_proc_U0_ap_continue assign process. --
image_filter_Block_proc_U0_ap_continue_assign_proc : process(ap_sig_ready_img_1_rows_V_full_n, ap_sig_ready_img_0_rows_V_channel_full_n, ap_sig_ready_img_1_cols_V_full_n, ap_sig_ready_img_0_cols_V_channel_full_n)
begin
if (((ap_sig_ready_img_1_rows_V_full_n = ap_const_logic_1) and (ap_const_logic_1 = ap_sig_ready_img_0_rows_V_channel_full_n) and (ap_const_logic_1 = ap_sig_ready_img_1_cols_V_full_n) and (ap_const_logic_1 = ap_sig_ready_img_0_cols_V_channel_full_n))) then
image_filter_Block_proc_U0_ap_continue <= ap_const_logic_1;
else
image_filter_Block_proc_U0_ap_continue <= ap_const_logic_0;
end if;
end process;
image_filter_Block_proc_U0_ap_start <= ap_start;
image_filter_Block_proc_U0_cols <= cols;
image_filter_Block_proc_U0_rows <= rows;
image_filter_Loop_1_proc_U0_ap_continue <= ap_const_logic_1;
image_filter_Loop_1_proc_U0_ap_start <= ap_start;
image_filter_Loop_1_proc_U0_buffer_val_0_q0 <= ap_const_lv8_0;
image_filter_Loop_1_proc_U0_buffer_val_0_q1 <= ap_const_lv8_0;
image_filter_Loop_1_proc_U0_buffer_val_1_q0 <= ap_const_lv8_0;
image_filter_Loop_1_proc_U0_buffer_val_1_q1 <= ap_const_lv8_0;
image_filter_Loop_1_proc_U0_buffer_val_2_q0 <= ap_const_lv8_0;
image_filter_Loop_1_proc_U0_buffer_val_2_q1 <= ap_const_lv8_0;
image_filter_Loop_1_proc_U0_cols <= cols;
image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout <= img_0_data_stream_0_V_dout;
image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n <= img_0_data_stream_0_V_empty_n;
image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout <= img_0_data_stream_1_V_dout;
image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n <= img_0_data_stream_1_V_empty_n;
image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout <= img_0_data_stream_2_V_dout;
image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n <= img_0_data_stream_2_V_empty_n;
image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n <= img_1_data_stream_0_V_full_n;
image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n <= img_1_data_stream_1_V_full_n;
image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n <= img_1_data_stream_2_V_full_n;
image_filter_Loop_1_proc_U0_rows <= rows;
image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY <= OUTPUT_STREAM_TREADY;
image_filter_Mat2AXIvideo_U0_ap_continue <= ap_sig_hs_continue;
image_filter_Mat2AXIvideo_U0_ap_start <= (img_1_rows_V_empty_n and img_1_cols_V_empty_n);
image_filter_Mat2AXIvideo_U0_img_cols_V_read <= img_1_cols_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout <= img_1_data_stream_0_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n <= img_1_data_stream_0_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout <= img_1_data_stream_1_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n <= img_1_data_stream_1_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout <= img_1_data_stream_2_V_dout;
image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n <= img_1_data_stream_2_V_empty_n;
image_filter_Mat2AXIvideo_U0_img_rows_V_read <= img_1_rows_V_dout;
img_0_cols_V_channel_U_ap_dummy_ce <= ap_const_logic_1;
img_0_cols_V_channel_din <= image_filter_Block_proc_U0_ap_return_1;
img_0_cols_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready;
img_0_cols_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel;
img_0_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
img_0_data_stream_0_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din;
img_0_data_stream_0_V_read <= image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read;
img_0_data_stream_0_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write;
img_0_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1;
img_0_data_stream_1_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din;
img_0_data_stream_1_V_read <= image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read;
img_0_data_stream_1_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write;
img_0_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1;
img_0_data_stream_2_V_din <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din;
img_0_data_stream_2_V_read <= image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read;
img_0_data_stream_2_V_write <= image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write;
img_0_rows_V_channel_U_ap_dummy_ce <= ap_const_logic_1;
img_0_rows_V_channel_din <= image_filter_Block_proc_U0_ap_return_0;
img_0_rows_V_channel_read <= image_filter_AXIvideo2Mat_U0_ap_ready;
img_0_rows_V_channel_write <= ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel;
img_1_cols_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_cols_V_din <= image_filter_Block_proc_U0_ap_return_3;
img_1_cols_V_read <= image_filter_Mat2AXIvideo_U0_ap_ready;
img_1_cols_V_write <= ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V;
img_1_data_stream_0_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_data_stream_0_V_din <= image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din;
img_1_data_stream_0_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read;
img_1_data_stream_0_V_write <= image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write;
img_1_data_stream_1_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_data_stream_1_V_din <= image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din;
img_1_data_stream_1_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read;
img_1_data_stream_1_V_write <= image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write;
img_1_data_stream_2_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_data_stream_2_V_din <= image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din;
img_1_data_stream_2_V_read <= image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read;
img_1_data_stream_2_V_write <= image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write;
img_1_rows_V_U_ap_dummy_ce <= ap_const_logic_1;
img_1_rows_V_din <= image_filter_Block_proc_U0_ap_return_2;
img_1_rows_V_read <= image_filter_Mat2AXIvideo_U0_ap_ready;
img_1_rows_V_write <= ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V;
end behav;
|
-- adsb receiver test bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity early_late_tb is
end early_late_tb;
architecture behav of early_late_tb is
component early_late
generic (
width : positive;
sam_per_bit : positive
);
port (
clk : in std_logic;
rst : in std_logic;
inclk : in std_logic;
outclk : out std_logic;
d : in std_logic_vector(width-1 downto 0)
);
end component;
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal inclk : std_logic := '0';
signal outclk : std_logic;
signal d : std_logic_vector(7 downto 0) := (others => '0');
begin
dut : early_late
generic map (width => 8, sam_per_bit => 8)
port map (clk, rst, clk, outclk, d);
clk <= not clk after 50 ns;
rst <= '0' after 200 ns;
in_file : process
variable input : integer;
variable l : line;
file vector_file : text is in "early_late_test.txt";
begin
wait until rst <= '0';
while not endfile(vector_file) loop
readline(vector_file, l);
read(l, input);
wait until rising_edge(clk);
inclk <= '1';
d <= std_logic_vector(to_signed(input, 8));
wait until rising_edge(clk);
inclk <= '0';
end loop;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
-- uncomment the following library declaration if using
-- arithmetic functions with signed or unsigned values
--use ieee.numeric_std.all;
entity counter_tb is
end counter_tb;
architecture behavior of counter_tb is
-- component declaration for the unit under test (uut)
component counter
generic ( n: integer;
max: integer );
port(
clk : in std_logic;
reset : in std_logic;
clear : in std_logic;
enable: in STD_LOGIC;
count_out : out std_logic_vector(n-1 downto 0);
cout : out std_logic
);
end component;
--inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal clear : std_logic := '0';
signal enable: std_logic := '1';
--outputs
signal count_out_3 : std_logic_vector(2 downto 0);
signal cout: std_logic;
-- clock period definitions
constant clk_period : time := 40 ns;
begin
-- instantiate the unit under test (uut)
uut: counter
generic map (3,5) -- 4-bit counter
port map (
clk => clk,
reset => reset,
clear => clear,
enable => enable,
count_out => count_out_3,
cout => cout
);
-- clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- stimulus process
stim_proc: process
begin
reset <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
clear <= '1';
wait for clk_period;
clear <= '0';
wait for clk_period*10;
enable <= '0';
wait for clk_period*2;
enable <= '1';
wait for clk_period*10;
wait;
end process;
end;
|
--
-- File Name: TbUtilPkg.vhd
-- Design Unit Name: TbUtilPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Package Defines
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2021 2021.02 Added AckType, RdyType, RequestTransaction, WaitForTransaction for AckType/RdyType
-- 12/2020 2020.12 Added IfElse functions for string and integer.
-- Added Increment function for integer
-- 01/2020 2020.01 Updated Licenses to Apache
-- 08/2018 2018.08 Updated WaitForTransaction to allow 0 time transactions
-- 04/2018 2018.04 Added RequestTransaction, WaitForTransaction, Toggle, WaitForToggle for bit.
-- Added Increment and WaitForToggle for integer.
-- 11/2016 2016.11 First Public Release Version
-- Updated naming for consistency.
-- 10/2013 2013.10 Split out Text Utilities
-- 11/1999: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 1999 - 2021 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.std_logic_1164.all ;
library osvvm ;
use osvvm.AlertLogPkg.all ;
use osvvm.TranscriptPkg.all ;
use osvvm.ResolutionPkg.all ;
package TbUtilPkg is
constant CLK_ACTIVE : std_logic := '1' ;
constant t_sim_resolution : time := std.env.resolution_limit ; -- VHDL-2008
-- constant t_sim_resolution : time := 1 ns ; -- for non VHDL-2008 simulators
------------------------------------------------------------
-- ZeroOneHot, OneHot
-- OneHot: return true if exactly one value is 1
-- ZeroOneHot: return false when more than one value is a 1
------------------------------------------------------------
function OneHot ( constant A : in std_logic_vector ) return boolean ;
function ZeroOneHot ( constant A : in std_logic_vector ) return boolean ;
------------------------------------------------------------
-- IfElse
-- Crutch until VHDL-2019 conditional initialization
-- If condition is true return first parameter otherwise return second
------------------------------------------------------------
function IfElse(Expr : boolean ; A, B : std_logic_vector) return std_logic_vector ;
function IfElse(Expr : boolean ; A, B : integer) return integer ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- RequestTransaction - Transaction initiation in transaction procedure
-- WaitForTransaction - Transaction execution control in VC
------------------------------------------------------------
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- std_logic
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out std_logic ;
signal Ack : In std_logic
) ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- bit
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out bit ;
signal Ack : In bit
) ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In bit ;
signal Ack : Out bit
) ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- integer
------------------------------------------------------------
subtype RdyType is resolved_max integer range 0 to integer'high ;
subtype AckType is resolved_max integer range -1 to integer'high ;
procedure RequestTransaction (
signal Rdy : InOut RdyType ;
signal Ack : In AckType
) ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In RdyType ;
signal Ack : InOut AckType
) ;
------------------------------------------------------------
-- WaitForTransaction
-- Specializations for interrupt handling
-- Currently only std_logic based
------------------------------------------------------------
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic ;
signal TimeOut : In std_logic ;
constant Polarity : In std_logic := '1'
) ;
-- Variation for model that stops waiting when IntReq is asserted
-- Intended for models that need to switch between instruction streams
-- such as a CPU when interrupt is pending
procedure WaitForTransactionOrIrq (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal IntReq : In std_logic
) ;
-- Set Ack to Model starting value
procedure StartTransaction ( signal Ack : Out std_logic ) ;
-- Set Ack to Model finishing value
procedure FinishTransaction ( signal Ack : Out std_logic ) ;
-- If a transaction is pending, return true
function TransactionPending ( signal Rdy : In std_logic ) return boolean ;
-- Variation for clockless models
procedure WaitForTransaction (
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) ;
------------------------------------------------------------
-- Toggle, WaitForToggle
-- Used for communicating between processes
------------------------------------------------------------
procedure Toggle (
signal Sig : InOut std_logic ;
constant DelayVal : time
) ;
procedure Toggle ( signal Sig : InOut std_logic ) ;
procedure ToggleHS ( signal Sig : InOut std_logic ) ;
function IsToggle ( signal Sig : In std_logic ) return boolean ;
procedure WaitForToggle ( signal Sig : In std_logic ) ;
-- Bit type versions
procedure Toggle ( signal Sig : InOut bit ; constant DelayVal : time ) ;
procedure Toggle ( signal Sig : InOut bit ) ;
procedure ToggleHS ( signal Sig : InOut bit ) ;
function IsToggle ( signal Sig : In bit ) return boolean ;
procedure WaitForToggle ( signal Sig : In bit ) ;
-- Integer type versions
procedure Increment ( signal Sig : InOut integer ; constant RollOverValue : in integer := 0) ;
function Increment (constant Sig : in integer ; constant Amount : in integer := 1) return integer ;
procedure WaitForToggle ( signal Sig : In integer ) ;
------------------------------------------------------------
-- WaitForBarrier
-- Barrier Synchronization
-- Multiple processes call it, it finishes when all have called it
------------------------------------------------------------
procedure WaitForBarrier ( signal Sig : InOut std_logic ) ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; constant TimeOut : time ) ;
-- resolved_barrier : summing resolution used in conjunction with integer based barriers
function resolved_barrier ( s : integer_vector ) return integer ;
subtype integer_barrier is resolved_barrier integer ;
-- Usage of integer barriers requires resolved_barrier. Initialization to 1 recommended, but not required
-- signal barrier1 : resolved_barrier integer := 1 ; -- using the resolution function
-- signal barrier2 : integer_barrier := 1 ; -- using the subtype that already applies the resolution function
procedure WaitForBarrier ( signal Sig : InOut integer ) ;
procedure WaitForBarrier ( signal Sig : InOut integer ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') ;
procedure WaitForBarrier ( signal Sig : InOut integer ; constant TimeOut : time ) ;
-- Using separate signals
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncIn : in std_logic ) ;
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncInV : in std_logic_vector ) ;
------------------------------------------------------------
-- WaitForClock
-- Sync to Clock - after a delay, after a number of clocks
------------------------------------------------------------
procedure WaitForClock ( signal Clk : in std_logic ; constant Delay : in time ) ;
procedure WaitForClock ( signal Clk : in std_logic ; constant NumberOfClocks : in integer := 1) ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in boolean ) ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in std_logic ; constant Polarity : std_logic := '1' ) ;
------------------------------------------------------------
-- WaitForLevel
-- Find a signal at a level
------------------------------------------------------------
procedure WaitForLevel ( signal A : in boolean ) ;
procedure WaitForLevel ( signal A : in std_logic ; Polarity : std_logic := '1' ) ;
------------------------------------------------------------
-- CreateClock, CreateReset
-- Note these do not exit
------------------------------------------------------------
procedure CreateClock (
signal Clk : inout std_logic ;
constant Period : time ;
constant DutyCycle : real := 0.5
) ;
procedure CheckClockPeriod (
constant AlertLogID : AlertLogIDType ;
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) ;
procedure CheckClockPeriod (
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) ;
procedure CreateReset (
signal Reset : out std_logic ;
constant ResetActive : in std_logic ;
signal Clk : in std_logic ;
constant Period : time ;
constant tpd : time
) ;
procedure LogReset (
constant AlertLogID : AlertLogIDType ;
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) ;
procedure LogReset (
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) ;
------------------------------------------------------------
-- Deprecated subprogram names
-- Maintaining backward compatibility using aliases
------------------------------------------------------------
-- History of RequestTransaction / WaitForTransaction
alias RequestAction is RequestTransaction [std_logic, std_logic] ;
alias WaitForRequest is WaitForTransaction [std_logic, std_logic, std_logic] ;
-- History of WaitForToggle
alias WaitOnToggle is WaitForToggle [std_logic] ;
-- History of WaitForBarrier
alias WayPointBlock is WaitForBarrier [std_logic] ;
alias SyncTo is WaitForBarrier2[std_logic, std_logic] ;
alias SyncTo is WaitForBarrier2[std_logic, std_logic_vector] ;
-- Backward compatible name
alias SyncToClk is WaitForClock [std_logic, time] ;
------------------------------------------------------------
-- Deprecated
-- WaitForAck, StrobeAck
-- Replaced by WaitForToggle and Toggle
------------------------------------------------------------
procedure WaitForAck ( signal Ack : In std_logic ) ;
procedure StrobeAck ( signal Ack : Out std_logic ) ;
end TbUtilPkg ;
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
package body TbUtilPkg is
------------------------------------------------------------
-- ZeroOneHot, OneHot
-- OneHot: return true if exactly one value is 1
-- ZeroOneHot: return false when more than one value is a 1
------------------------------------------------------------
function OneHot ( constant A : in std_logic_vector ) return boolean is
variable found_one : boolean := FALSE ;
begin
for i in A'range loop
if A(i) = '1' or A(i) = 'H' then
if found_one then
return FALSE ;
end if ;
found_one := TRUE ;
end if ;
end loop ;
return found_one ; -- found a one
end function OneHot ;
function ZeroOneHot ( constant A : in std_logic_vector ) return boolean is
variable found_one : boolean := FALSE ;
begin
for i in A'range loop
if A(i) = '1' or A(i) = 'H' then
if found_one then
return FALSE ;
end if ;
found_one := TRUE ;
end if ;
end loop ;
return TRUE ; -- all zero or found a one
end function ZeroOneHot ;
------------------------------------------------------------
-- IfElse
-- Crutch until VHDL-2019 conditional initialization
-- If condition is true return first parameter otherwise return second
------------------------------------------------------------
function IfElse(Expr : boolean ; A, B : std_logic_vector) return std_logic_vector is
begin
if Expr then
return A ;
else
return B ;
end if ;
end function IfElse ;
function IfElse(Expr : boolean ; A, B : integer) return integer is
begin
if Expr then
return A ;
else
return B ;
end if ;
end function IfElse ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- RequestTransaction - Transaction initiation in transaction procedure
-- WaitForTransaction - Transaction execution control in VC
------------------------------------------------------------
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- std_logic
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out std_logic ;
signal Ack : In std_logic
) is
begin
-- Record contains new transaction
Rdy <= '1' ;
-- Find Ack low = '0'
wait until Ack = '0' ;
-- Prepare for Next Transaction
Rdy <= '0' ;
-- Transaction Done
wait until Ack = '1' ;
end procedure RequestTransaction ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Start of Transaction
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
end if ;
-- align to clock if needed (not back-to-back transactions)
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- Allow transactions without time passing
end procedure WaitForTransaction ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- bit
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out bit ;
signal Ack : In bit
) is
begin
-- Record contains new transaction
Rdy <= '1' ;
-- Find Ack low = '0'
wait until Ack = '0' ;
-- Prepare for Next Transaction
Rdy <= '0' ;
-- Transaction Done
wait until Ack = '1' ;
end procedure RequestTransaction ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In bit ;
signal Ack : Out bit
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Start of Transaction
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
else
wait for 0 ns ; -- allow Ack to update
end if ;
-- align to clock if needed (not back-to-back transactions)
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- Allow transactions without time passing
end procedure WaitForTransaction ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- integer
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : InOut RdyType ;
signal Ack : In AckType
) is
begin
-- Initiate Transaction Request
Rdy <= Increment(Rdy) ;
wait for 0 ns ;
-- Wait for Transaction Completion
wait until Rdy = Ack ;
end procedure RequestTransaction ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In RdyType ;
signal Ack : InOut AckType
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= Increment(Ack) ;
AckTime := NOW ;
-- Find Start of Transaction
wait until Ack /= Rdy ;
-- Align to clock if needed (not back-to-back transactions)
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
end procedure WaitForTransaction ;
------------------------------------------------------------
-- WaitForTransaction
-- Specializations for interrupt handling
-- Currently only std_logic based
------------------------------------------------------------
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic ;
signal TimeOut : In std_logic ;
constant Polarity : In std_logic := '1'
) is
variable AckTime : time ;
variable FoundRdy : boolean ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Ready or Time out
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if (Rdy /= '1' and TimeOut /= Polarity) then
wait until Rdy = '1' or TimeOut = Polarity ;
end if ;
FoundRdy := Rdy = '1' ;
-- align to clock if Rdy or TimeOut does not happen within delta cycles from Ack
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
if FoundRdy then
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- Allow transactions without time passing
end if ;
end procedure WaitForTransaction ;
-- Variation for model that stops waiting when IntReq is asserted
-- Intended for models that need to switch between instruction streams
-- such as a CPU when interrupt is pending
procedure WaitForTransactionOrIrq (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal IntReq : In std_logic
) is
variable AckTime : time ;
constant POLARITY : std_logic := '1' ;
begin
AckTime := NOW ;
-- Find Ready or Time out
wait for 0 ns ; -- allow Rdy from previous cycle to clear
if (Rdy /= '1' and IntReq /= POLARITY) then
wait until Rdy = '1' or IntReq = POLARITY ;
else
wait for 0 ns ; -- allow Ack to update
end if ;
-- align to clock if Rdy or IntReq does not happen within delta cycles from Ack
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
end procedure ;
-- Set Ack to Model starting value
-- Pairs with WaitForTransactionOrIrq above
procedure StartTransaction ( signal Ack : Out std_logic ) is
begin
Ack <= '0' ;
wait for 0 ns ; -- Allow transactions without time passing
end procedure StartTransaction ;
-- Set Ack to Model finishing value
-- Pairs with WaitForTransactionOrIrq above
procedure FinishTransaction ( signal Ack : Out std_logic ) is
begin
-- End of Cycle
Ack <= '1' ;
wait for 0 ns ; -- Allow Ack to update
end procedure FinishTransaction ;
-- If a transaction is pending, return true
-- Used to detect presence of transaction stream,
-- such as an interrupt handler
function TransactionPending (
signal Rdy : In std_logic
) return boolean is
begin
return Rdy = '1' ;
end function TransactionPending ;
-- Variation for clockless models
procedure WaitForTransaction (
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
-- Find Start of Transaction
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- allow 0 time transactions
end procedure WaitForTransaction ;
------------------------------------------------------------
-- Toggle, WaitForToggle
-- Used for communicating between processes
------------------------------------------------------------
type stdulogic_indexby_stdulogic is array (std_ulogic) of std_ulogic;
constant toggle_sl_table : stdulogic_indexby_stdulogic := (
'0' => '1',
'L' => '1',
others => '0'
);
procedure Toggle (
signal Sig : InOut std_logic ;
constant DelayVal : time
) is
variable iDelayVal : time ;
begin
if DelayVal > t_sim_resolution then
iDelayVal := DelayVal - t_sim_resolution ;
else
iDelayVal := 0 sec ;
AlertIf(OSVVM_ALERTLOG_ID, DelayVal < 0 sec, "osvvm.TbUtilPkg.Toggle: Delay value < 0 ns") ;
end if ;
Sig <= toggle_sl_table(Sig) after iDelayVal ;
end procedure Toggle ;
procedure Toggle ( signal Sig : InOut std_logic ) is
begin
Sig <= toggle_sl_table(Sig) ;
end procedure Toggle ;
procedure ToggleHS ( signal Sig : InOut std_logic ) is
begin
Sig <= toggle_sl_table(Sig) ;
wait for 0 ns ; -- Sig toggles
wait for 0 ns ; -- new values updated into record
end procedure ToggleHS ;
function IsToggle ( signal Sig : In std_logic ) return boolean is
begin
return Sig'event ;
end function IsToggle ;
procedure WaitForToggle ( signal Sig : In std_logic ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
-- Bit type versions
procedure Toggle ( signal Sig : InOut bit ; constant DelayVal : time ) is
variable iDelayVal : time ;
begin
if DelayVal > t_sim_resolution then
iDelayVal := DelayVal - t_sim_resolution ;
else
iDelayVal := 0 sec ;
AlertIf(OSVVM_ALERTLOG_ID, DelayVal < 0 sec,
"osvvm.TbUtilPkg.Toggle: Delay value < 0 ns", WARNING) ;
end if ;
Sig <= not Sig after iDelayVal ;
end procedure Toggle ;
procedure Toggle ( signal Sig : InOut bit ) is
begin
Sig <= not Sig ;
end procedure Toggle ;
procedure ToggleHS ( signal Sig : InOut bit ) is
begin
Sig <= not Sig ;
wait for 0 ns ; -- Sig toggles
wait for 0 ns ; -- new values updated into record
end procedure ToggleHS ;
function IsToggle ( signal Sig : In bit ) return boolean is
begin
return Sig'event ;
end function IsToggle ;
procedure WaitForToggle ( signal Sig : In bit ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
-- Integer type versions
procedure Increment (signal Sig : InOut integer ; constant RollOverValue : in integer := 0) is
begin
--!! if Sig = integer'high then
if Sig = 2**30-1 then -- for consistency with function increment
Sig <= RollOverValue ;
else
Sig <= Sig + 1 ;
end if ;
end procedure Increment ;
function Increment (constant Sig : in integer ; constant Amount : in integer := 1) return integer is
begin
return (Sig + Amount) mod 2**30 ;
end function Increment ;
procedure WaitForToggle ( signal Sig : In integer ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
------------------------------------------------------------
-- WaitForBarrier
-- Barrier Synchronization
-- Multiple processes call it, it finishes when all have called it
------------------------------------------------------------
procedure WaitForBarrier ( signal Sig : InOut std_logic ) is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' or TimeOut = Polarity ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; constant TimeOut : time ) is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' for TimeOut ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
------------------------------------------------------------
-- resolved_barrier
-- summing resolution used in conjunction with integer based barriers
function resolved_barrier ( s : integer_vector ) return integer is
variable result : integer := 0 ;
begin
for i in s'RANGE loop
-- if s(i) /= integer'left then
-- result := result + s(i);
-- else
if s(i) /= 0 then
result := result + 1; -- removes the initialization requirement
end if ;
end loop ;
return result ;
end function resolved_barrier ;
-- Usage of integer barriers requires resolved_barrier. Initialization to 1 recommended, but not required
-- signal barrier1 : resolved_barrier integer := 1 ; -- using the resolution function
-- signal barrier2 : integer_barrier := 1 ; -- using the subtype that already applies the resolution function
procedure WaitForBarrier ( signal Sig : InOut integer ) is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut integer ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 or TimeOut = Polarity ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut integer ; constant TimeOut : time ) is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 for TimeOut ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
-- Using separate signals
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncIn : in std_logic ) is
begin
-- Activate Rdy
SyncOut <= '1' ;
-- Make sure our Rdy is seen
wait for 0 ns ;
-- Wait until other process' Rdy is at level 1
if SyncIn /= '1' then
wait until SyncIn = '1' ;
end if ;
-- Deactivate Rdy
SyncOut <= '0' ;
end procedure WaitForBarrier2 ;
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncInV : in std_logic_vector ) is
constant ALL_ONE : std_logic_vector(SyncInV'Range) := (others => '1');
begin
-- Activate Rdy
SyncOut <= '1' ;
-- Make sure our Rdy is seen
wait for 0 ns ;
-- Wait until all other process' Rdy is at level 1
if SyncInV /= ALL_ONE then
wait until SyncInV = ALL_ONE ;
end if ;
-- Deactivate Rdy
SyncOut <= '0' ;
end procedure WaitForBarrier2 ;
------------------------------------------------------------
-- WaitForClock
-- Sync to Clock - after a delay, after a number of clocks
------------------------------------------------------------
procedure WaitForClock ( signal Clk : in std_logic ; constant Delay : in time ) is
begin
if delay > t_sim_resolution then
wait for delay - t_sim_resolution ;
end if ;
wait until Clk = CLK_ACTIVE ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; constant NumberOfClocks : in integer := 1) is
begin
for i in 1 to NumberOfClocks loop
wait until Clk = CLK_ACTIVE ;
end loop ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in boolean ) is
begin
wait on Clk until Clk = CLK_ACTIVE and Enable ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in std_logic ; constant Polarity : std_logic := '1' ) is
begin
wait on Clk until Clk = CLK_ACTIVE and Enable = Polarity ;
end procedure WaitForClock ;
------------------------------------------------------------
-- WaitForLevel
-- Find a signal at a level
------------------------------------------------------------
procedure WaitForLevel ( signal A : in boolean ) is
begin
if not A then
wait until A ;
end if ;
end procedure WaitForLevel ;
procedure WaitForLevel ( signal A : in std_logic ; Polarity : std_logic := '1' ) is
begin
if A /= Polarity then
-- wait on A until A = Polarity ;
if Polarity = '1' then
wait until A = '1' ;
else
wait until A = '0' ;
end if ;
end if ;
end procedure WaitForLevel ;
------------------------------------------------------------
-- CreateClock, CreateReset
-- Note these do not exit
------------------------------------------------------------
procedure CreateClock (
signal Clk : inout std_logic ;
constant Period : time ;
constant DutyCycle : real := 0.5
) is
constant HIGH_TIME : time := Period * DutyCycle ;
constant LOW_TIME : time := Period - HIGH_TIME ;
begin
if HIGH_TIME = LOW_TIME then
loop
Clk <= toggle_sl_table(Clk) after HIGH_TIME ;
wait on Clk ;
end loop ;
else
-- Schedule s.t. all assignments after the first occur on delta cycle 0
Clk <= '0', '1' after LOW_TIME ;
wait for period - 1 ns ; -- allows after on future Clk <= '0'
loop
Clk <= '0' after 1 ns, '1' after LOW_TIME + 1 ns ;
wait for period ;
end loop ;
end if ;
end procedure CreateClock ;
procedure CheckClockPeriod (
constant AlertLogID : AlertLogIDType ;
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) is
variable LastLogTime, ObservedPeriod : time ;
begin
wait until Clk = CLK_ACTIVE ;
LastLogTime := now ;
-- Check First HowMany clocks
for i in 1 to HowMany loop
wait until Clk = CLK_ACTIVE ;
ObservedPeriod := now - LastLogTime ;
AffirmIf(AlertLogID, ObservedPeriod = Period,
"CheckClockPeriod: " & ClkName & " Period: " & to_string(ObservedPeriod) &
" = Expected " & to_string(Period)) ;
LastLogTime := now ;
end loop ;
wait ;
end procedure CheckClockPeriod ;
procedure CheckClockPeriod (
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) is
begin
CheckClockPeriod (
AlertLogID => ALERTLOG_DEFAULT_ID,
Clk => Clk,
Period => Period,
ClkName => ClkName,
HowMany => HowMany
) ;
end procedure CheckClockPeriod ;
procedure CreateReset (
signal Reset : out std_logic ;
constant ResetActive : in std_logic ;
signal Clk : in std_logic ;
constant Period : time ;
constant tpd : time
) is
begin
wait until Clk = CLK_ACTIVE ;
Reset <= ResetActive after tpd ;
wait for Period - t_sim_resolution ;
wait until Clk = CLK_ACTIVE ;
Reset <= not ResetActive after tpd ;
wait ;
end procedure CreateReset ;
procedure LogReset (
constant AlertLogID : AlertLogIDType ;
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) is
begin
-- Does not log the value of Reset at time 0.
for_ever : loop
wait on Reset ;
if Reset = ResetActive then
LOG(AlertLogID, ResetName & " now active", INFO) ;
print("") ;
elsif Reset = not ResetActive then
LOG(AlertLogID, ResetName & " now inactive", INFO) ;
print("") ;
else
LOG(AlertLogID, ResetName & " = " & to_string(Reset), INFO) ;
print("") ;
end if ;
end loop for_ever ;
end procedure LogReset ;
procedure LogReset (
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) is
begin
LogReset (
AlertLogID => ALERTLOG_DEFAULT_ID,
Reset => Reset,
ResetActive => ResetActive,
ResetName => ResetName,
LogLevel => LogLevel
) ;
end procedure LogReset ;
------------------------------------------------------------
-- Deprecated
-- WaitForAck, StrobeAck
-- Replaced by WaitForToggle and Toggle
------------------------------------------------------------
procedure WaitForAck ( signal Ack : In std_logic ) is
begin
-- Wait for Model to be done
wait until Ack = '1' ;
wait for 0 ns ;
end procedure ;
procedure StrobeAck ( signal Ack : Out std_logic ) is
begin
-- Model done, drive rising edge on Ack
Ack <= '0' ;
wait for 0 ns ;
Ack <= '1' ;
wait for 0 ns ;
end procedure ;
end TbUtilPkg ;
|
----------------------------------------------------------------------------------
-- Project: YASG (Yet another signal generator)
-- Project Page: https://github.com/id101010/vhdl-yasg/
-- Authors: Aaron Schmocker & Timo Lang
-- License: GPL v3
-- Create Date: 15:38:41 05/17/2016
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY spi_driver_tb IS
END spi_driver_tb;
ARCHITECTURE behavior OF spi_driver_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT spi_driver
PORT(
clk : IN std_logic;
rst : IN std_logic;
val : IN unsigned(11 downto 0);
sck : OUT std_logic;
cs : OUT std_logic;
mosi : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal val : unsigned(11 downto 0) := (others => '0');
--Outputs
signal sck : std_logic;
signal cs : std_logic;
signal mosi : std_logic;
-- Clock period definitions
constant clk_period : time := 20 ns; --50mhz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: spi_driver PORT MAP (
clk => clk,
rst => rst,
val => val,
sck => sck,
cs => cs,
mosi => mosi
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for clk_period*10;
val <= to_unsigned(0,12);
wait for clk_period*64;
val <= to_unsigned(7,12);
wait for clk_period*64;
val <= to_unsigned(31,12);
wait for clk_period*64;
val <= to_unsigned(128,12);
wait for clk_period*64;
val <= to_unsigned(512,12);
wait for clk_period*64;
-- insert stimulus here
wait;
end process;
END;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Rhody_CPU_pipelinev7 is
port ( clk : in std_logic;
rst : in std_logic;
MEM_ADR : out std_logic_vector(31 downto 0);
MEM_IN : in std_logic_vector(31 downto 0);
MEM_OUT : out std_logic_vector(31 downto 0);
mem_wr : out std_logic;
mem_rd : out std_logic;
key : in std_logic;
LEDR : out std_logic_vector(3 downto 0)
);
end;
architecture Structural of Rhody_CPU_pipelinev7 is
-- state machine: CPU_state
type State_type is (S1, S2);
signal update, stage1, stage2, stage3, stage4: State_type;
-- Register File: 8x32
type reg_file_type is array (0 to 7) of std_logic_vector(31 downto 0);
signal register_file : reg_file_type;
-- Internal registers
signal MDR_in, MDR_out, MAR, PSW: std_logic_vector(31 downto 0);
signal PC, SP: unsigned(31 downto 0); --unsigned for arithemtic operations
-- Internal control signals
signal operand0, operand1, ALU_out : std_logic_vector(31 downto 0);
signal carry, overflow, zero : std_logic;
-- Pipeline Istruction registers
signal stall: Boolean;
signal IR2, IR3, IR4: std_logic_vector(31 downto 0);
--Rhody Instruction Format
alias Opcode2: std_logic_vector(5 downto 0) is IR2(31 downto 26);
alias Opcode3: std_logic_vector(5 downto 0) is IR3(31 downto 26);
alias Opcode4: std_logic_vector(5 downto 0) is IR4(31 downto 26);
alias RX2 : std_logic_vector(2 downto 0) is IR2(25 downto 23);
alias RX3 : std_logic_vector(2 downto 0) is IR3(25 downto 23);
alias RY2 : std_logic_vector(2 downto 0) is IR2(22 downto 20);
alias RZ2 : std_logic_vector(2 downto 0) is IR2(19 downto 17);
alias RA2 : std_logic_vector(2 downto 0) is IR2(16 downto 14);
alias RB2 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RB3 : std_logic_vector(2 downto 0) is IR2(13 downto 11);
alias RC2 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RC3 : std_logic_vector(2 downto 0) is IR2(10 downto 8);
alias RD2 : std_logic_vector(2 downto 0) is IR2(7 downto 5);
alias RE2 : std_logic_vector(2 downto 0) is IR2(4 downto 2);
alias I2 : std_logic_vector(15 downto 0) is IR2(15 downto 0);
alias M2 : std_logic_vector(19 downto 0) is IR2(19 downto 0);
alias M3 : std_logic_vector(19 downto 0) is IR3(19 downto 0);
-- Temporary control signals
signal tmpx, tmpy, tmpz, tmpa: std_logic_vector(31 downto 0);
--Condition Codes
alias Z: std_logic is PSW(0);
alias C: std_logic is PSW(1);
alias S: std_logic is PSW(2);
alias V: std_logic is PSW(3);
--Instruction Opcodes
constant NOP : std_logic_vector(5 downto 0) := "000000";
constant ADD64: std_logic_vector(5 downto 0) := "000001";
constant T2 : std_logic_vector(5 downto 0) := "000010";
constant LDM : std_logic_vector(5 downto 0) := "000100";
constant LDR : std_logic_vector(5 downto 0) := "000101";
constant LDIX : std_logic_vector(5 downto 0) := "000110";
constant STIX : std_logic_vector(5 downto 0) := "000111";
constant LDH : std_logic_vector(5 downto 0) := "001000";
constant LDL : std_logic_vector(5 downto 0) := "001001";
constant LDI : std_logic_vector(5 downto 0) := "001010";
constant MOV : std_logic_vector(5 downto 0) := "001011";
constant STM : std_logic_vector(5 downto 0) := "001100";
constant STR : std_logic_vector(5 downto 0) := "001101";
constant ADD : std_logic_vector(5 downto 0) := "010000";
constant ADI : std_logic_vector(5 downto 0) := "010001";
constant SUB : std_logic_vector(5 downto 0) := "010010";
constant MUL : std_logic_vector(5 downto 0) := "010011";
constant IAND : std_logic_vector(5 downto 0) := "010100"; --avoid keyword
constant IOR : std_logic_vector(5 downto 0) := "010101"; --avoid keyword
constant IXOR : std_logic_vector(5 downto 0) := "010110"; --avoid keyword
constant IROR : std_logic_vector(5 downto 0) := "010111"; --avoid keyword
constant JNZ : std_logic_vector(5 downto 0) := "100000";
constant JNS : std_logic_vector(5 downto 0) := "100001";
constant JNV : std_logic_vector(5 downto 0) := "100010";
constant JNC : std_logic_vector(5 downto 0) := "100011";
constant JZ : std_logic_vector(5 downto 0) := "100100";
constant JS : std_logic_vector(5 downto 0) := "100101";
constant JV : std_logic_vector(5 downto 0) := "100110";
constant JC : std_logic_vector(5 downto 0) := "100111";
constant JMP : std_logic_vector(5 downto 0) := "101000";
constant CMP : std_logic_vector(5 downto 0) := "101010";
constant T11 : std_logic_vector(5 downto 0) := "101110";
constant T12 : std_logic_vector(5 downto 0) := "101111";
constant CALL : std_logic_vector(5 downto 0) := "110000";
constant CMPI : std_logic_vector(5 downto 0) := "110010";
constant RET : std_logic_vector(5 downto 0) := "110100";
constant RETI : std_logic_vector(5 downto 0) := "110101";
constant PUSH : std_logic_vector(5 downto 0) := "111000";
constant POP : std_logic_vector(5 downto 0) := "111001";
constant SYS : std_logic_vector(5 downto 0) := "111100";
constant SIG0 : std_logic_vector(5 downto 0) := "111110";
constant SIG1 : std_logic_vector(5 downto 0) := "111111";
constant MLOAD0 : std_logic_vector(5 downto 0) := "011001";
constant MLOAD1 : std_logic_vector(5 downto 0) := "011010";
constant MLOAD2 : std_logic_vector(5 downto 0) := "011011";
constant MLOAD3 : std_logic_vector(5 downto 0) := "011100";
constant WLOAD : std_logic_vector(5 downto 0) := "011101";
constant ROUND1 : std_logic_vector(5 downto 0) := "101100";
constant FIN : std_logic_vector(5 downto 0) := "101101";
constant MSTM0 : std_logic_vector(5 downto 0) := "101001";
constant MSTM1 : std_logic_vector(5 downto 0) := "101011";
constant WPAD2 : std_logic_vector(5 downto 0) := "111010";
constant WPAD : std_logic_vector(5 downto 0) := "111011";
constant WORD_BITS : integer := 64;
subtype WORD_TYPE is std_logic_vector(63 downto 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
constant WORD_NULL : WORD_TYPE := (others => '0');
--shared variable w_80 : WORD_VECTOR(0 to 79);
----------------------------------------------------------------
constant K_TABLE : WORD_VECTOR(0 to 79) := (
0 => To_StdLogicVector(bit_vector'(X"428a2f98d728ae22")),
1 => To_StdLogicVector(bit_vector'(X"7137449123ef65cd")),
2 => To_StdLogicVector(bit_vector'(X"b5c0fbcfec4d3b2f")),
3 => To_StdLogicVector(bit_vector'(X"e9b5dba58189dbbc")),
4 => To_StdLogicVector(bit_vector'(X"3956c25bf348b538")),
5 => To_StdLogicVector(bit_vector'(X"59f111f1b605d019")),
6 => To_StdLogicVector(bit_vector'(X"923f82a4af194f9b")),
7 => To_StdLogicVector(bit_vector'(X"ab1c5ed5da6d8118")),
8 => To_StdLogicVector(bit_vector'(X"d807aa98a3030242")),
9 => To_StdLogicVector(bit_vector'(X"12835b0145706fbe")),
10 => To_StdLogicVector(bit_vector'(X"243185be4ee4b28c")),
11 => To_StdLogicVector(bit_vector'(X"550c7dc3d5ffb4e2")),
12 => To_StdLogicVector(bit_vector'(X"72be5d74f27b896f")),
13 => To_StdLogicVector(bit_vector'(X"80deb1fe3b1696b1")),
14 => To_StdLogicVector(bit_vector'(X"9bdc06a725c71235")),
15 => To_StdLogicVector(bit_vector'(X"c19bf174cf692694")),
16 => To_StdLogicVector(bit_vector'(X"e49b69c19ef14ad2")),
17 => To_StdLogicVector(bit_vector'(X"efbe4786384f25e3")),
18 => To_StdLogicVector(bit_vector'(X"0fc19dc68b8cd5b5")),
19 => To_StdLogicVector(bit_vector'(X"240ca1cc77ac9c65")),
20 => To_StdLogicVector(bit_vector'(X"2de92c6f592b0275")),
21 => To_StdLogicVector(bit_vector'(X"4a7484aa6ea6e483")),
22 => To_StdLogicVector(bit_vector'(X"5cb0a9dcbd41fbd4")),
23 => To_StdLogicVector(bit_vector'(X"76f988da831153b5")),
24 => To_StdLogicVector(bit_vector'(X"983e5152ee66dfab")),
25 => To_StdLogicVector(bit_vector'(X"a831c66d2db43210")),
26 => To_StdLogicVector(bit_vector'(X"b00327c898fb213f")),
27 => To_StdLogicVector(bit_vector'(X"bf597fc7beef0ee4")),
28 => To_StdLogicVector(bit_vector'(X"c6e00bf33da88fc2")),
29 => To_StdLogicVector(bit_vector'(X"d5a79147930aa725")),
30 => To_StdLogicVector(bit_vector'(X"06ca6351e003826f")),
31 => To_StdLogicVector(bit_vector'(X"142929670a0e6e70")),
32 => To_StdLogicVector(bit_vector'(X"27b70a8546d22ffc")),
33 => To_StdLogicVector(bit_vector'(X"2e1b21385c26c926")),
34 => To_StdLogicVector(bit_vector'(X"4d2c6dfc5ac42aed")),
35 => To_StdLogicVector(bit_vector'(X"53380d139d95b3df")),
36 => To_StdLogicVector(bit_vector'(X"650a73548baf63de")),
37 => To_StdLogicVector(bit_vector'(X"766a0abb3c77b2a8")),
38 => To_StdLogicVector(bit_vector'(X"81c2c92e47edaee6")),
39 => To_StdLogicVector(bit_vector'(X"92722c851482353b")),
40 => To_StdLogicVector(bit_vector'(X"a2bfe8a14cf10364")),
41 => To_StdLogicVector(bit_vector'(X"a81a664bbc423001")),
42 => To_StdLogicVector(bit_vector'(X"c24b8b70d0f89791")),
43 => To_StdLogicVector(bit_vector'(X"c76c51a30654be30")),
44 => To_StdLogicVector(bit_vector'(X"d192e819d6ef5218")),
45 => To_StdLogicVector(bit_vector'(X"d69906245565a910")),
46 => To_StdLogicVector(bit_vector'(X"f40e35855771202a")),
47 => To_StdLogicVector(bit_vector'(X"106aa07032bbd1b8")),
48 => To_StdLogicVector(bit_vector'(X"19a4c116b8d2d0c8")),
49 => To_StdLogicVector(bit_vector'(X"1e376c085141ab53")),
50 => To_StdLogicVector(bit_vector'(X"2748774cdf8eeb99")),
51 => To_StdLogicVector(bit_vector'(X"34b0bcb5e19b48a8")),
52 => To_StdLogicVector(bit_vector'(X"391c0cb3c5c95a63")),
53 => To_StdLogicVector(bit_vector'(X"4ed8aa4ae3418acb")),
54 => To_StdLogicVector(bit_vector'(X"5b9cca4f7763e373")),
55 => To_StdLogicVector(bit_vector'(X"682e6ff3d6b2b8a3")),
56 => To_StdLogicVector(bit_vector'(X"748f82ee5defb2fc")),
57 => To_StdLogicVector(bit_vector'(X"78a5636f43172f60")),
58 => To_StdLogicVector(bit_vector'(X"84c87814a1f0ab72")),
59 => To_StdLogicVector(bit_vector'(X"8cc702081a6439ec")),
60 => To_StdLogicVector(bit_vector'(X"90befffa23631e28")),
61 => To_StdLogicVector(bit_vector'(X"a4506cebde82bde9")),
62 => To_StdLogicVector(bit_vector'(X"bef9a3f7b2c67915")),
63 => To_StdLogicVector(bit_vector'(X"c67178f2e372532b")),
64 => To_StdLogicVector(bit_vector'(X"ca273eceea26619c")),
65 => To_StdLogicVector(bit_vector'(X"d186b8c721c0c207")),
66 => To_StdLogicVector(bit_vector'(X"eada7dd6cde0eb1e")),
67 => To_StdLogicVector(bit_vector'(X"f57d4f7fee6ed178")),
68 => To_StdLogicVector(bit_vector'(X"06f067aa72176fba")),
69 => To_StdLogicVector(bit_vector'(X"0a637dc5a2c898a6")),
70 => To_StdLogicVector(bit_vector'(X"113f9804bef90dae")),
71 => To_StdLogicVector(bit_vector'(X"1b710b35131c471b")),
72 => To_StdLogicVector(bit_vector'(X"28db77f523047d84")),
73 => To_StdLogicVector(bit_vector'(X"32caab7b40c72493")),
74 => To_StdLogicVector(bit_vector'(X"3c9ebe0a15c9bebc")),
75 => To_StdLogicVector(bit_vector'(X"431d67c49c100d4c")),
76 => To_StdLogicVector(bit_vector'(X"4cc5d4becb3e42b6")),
77 => To_StdLogicVector(bit_vector'(X"597f299cfc657e2a")),
78 => To_StdLogicVector(bit_vector'(X"5fcb6fab3ad6faec")),
79 => To_StdLogicVector(bit_vector'(X"6c44198c4a475817"))
);
constant H0_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"6a09e667f3bcc908"));
constant H1_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"bb67ae8584caa73b"));
constant H2_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"3c6ef372fe94f82b"));
constant H3_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"a54ff53a5f1d36f1"));
constant H4_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"510e527fade682d1"));
constant H5_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"9b05688c2b3e6c1f"));
constant H6_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"1f83d9abfb41bd6b"));
constant H7_INIT : WORD_TYPE := To_StdLogicVector(bit_vector'(X"5be0cd19137e2179"));
-------------------------------------------------------------------------
signal dm0 : std_logic_vector(63 downto 0);
signal dm1 : std_logic_vector(63 downto 0);
signal dm2 : std_logic_vector(63 downto 0);
signal dm3 : std_logic_vector(63 downto 0);
signal dm4 : std_logic_vector(63 downto 0);
signal dm5 : std_logic_vector(63 downto 0);
signal dm6 : std_logic_vector(63 downto 0);
signal dm7 : std_logic_vector(63 downto 0);
signal dm8 : std_logic_vector(63 downto 0);
signal dm9 : std_logic_vector(63 downto 0);
signal dm10 : std_logic_vector(63 downto 0);
signal dm11 : std_logic_vector(63 downto 0);
signal dm12 : std_logic_vector(63 downto 0);
signal dm13 : std_logic_vector(63 downto 0);
signal dm14 : std_logic_vector(63 downto 0);
signal dm15 : std_logic_vector(63 downto 0);
-- a,b,c,d,e,f,g,h
signal wva : WORD_TYPE;
signal wvb : WORD_TYPE;
signal wvc : WORD_TYPE;
signal wvd : WORD_TYPE;
signal wve : WORD_TYPE;
signal wvf : WORD_TYPE;
signal wvg : WORD_TYPE;
signal wvh : WORD_TYPE;
signal t1_val : WORD_TYPE;
signal t2_val : WORD_TYPE;
signal rcount: integer := 0;
-- H0,H1,H2,H3,H4,H5,H6,H7
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
signal h5 : WORD_TYPE;
signal h6 : WORD_TYPE;
signal h7 : WORD_TYPE;
signal tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7: std_logic_vector(63 downto 0);
signal mvect : WORD_VECTOR(0 to 15);
signal wout: std_logic_vector(63 downto 0);
begin
--Display condition code on LEDR for debugging purpose
LEDR(3) <= Z when key='0' else '0';
LEDR(2) <= C when key='0' else '0';
LEDR(1) <= S when key='0' else '0';
LEDR(0) <= V when key='0' else '0';
--CPU bus interface
MEM_OUT <= MDR_out; --Outgoing data bus
MEM_ADR <= MAR; --Address bus
--One clock cycle delay in obtaining CPU_state, e.g. S1->S2
mem_rd <= '1' when ((Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX) and stage2=S2) else
'1' when (stage1=S2 and not stall) else
'1' when ((Opcode2=POP or Opcode2=RET) and stage2=S2) else
'1' when (Opcode2=RETI and stage2=S2) else
'1' when (Opcode3=RETI and stage3=S2) else
'0'; --Memory read control signal
mem_wr <= '1' when ((Opcode3=STM or Opcode3=STR or Opcode3=STIX) and stage3=S1) else
'1' when ((Opcode3=PUSH or Opcode3=CALL) and stage3=S2) else
'1' when (Opcode3=SYS and stage3=S2) else
'1' when (Opcode4=SYS and stage4=S2) else
'0'; --Memory write control signal
stall <= true when(Opcode2=LDM or Opcode2=LDR or Opcode2 = LDIX or Opcode2=STM or Opcode2=STR or Opcode2=STIX or Opcode2=WPAD or Opcode2=WPAD2) else
true when(Opcode2=CALL or Opcode2=PUSH or Opcode2=POP or Opcode2=RET
or Opcode2=SYS or Opcode2=RETI) else
true when(Opcode3=CALL or Opcode3=RET or Opcode3=PUSH
or Opcode3=SYS or Opcode3=RETI) else
true when(Opcode4=SYS or Opcode4=RETI) else
false;
--The state machine that is CPU
CPU_State_Machine: process (clk, rst)
begin
if rst='1' then
update <= S1;
stage1 <= S1;
stage2 <= S1;
stage3 <= S1;
stage4 <= S1;
PC <= x"00000000"; --initialize PC
SP <= x"000FF7FF"; --initialize SP
IR2 <= x"00000000";
IR3 <= x"00000000";
IR4 <= x"00000000";
elsif clk'event and clk = '1' then
case update is
when S1 =>
update <= S2;
when S2 =>
if (stall or
(Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z='0') or
(Opcode2=JNS and S='1') or (Opcode2=JS and S='0') or
(Opcode2=JNV and V='1') or (Opcode2=JV and V='0') or
(Opcode2=JNC and C='1') or (Opcode2=JC and C='0') ) then
IR2 <= x"00000000"; --insert NOP
else
IR2 <= MEM_in;
end if;
IR3 <= IR2;
IR4 <= IR3;
update <= S1;
when others =>
null;
end case;
case stage1 is
when S1 =>
if (not stall) then
if(Opcode2=JMP or Opcode2=JNZ or Opcode2=JZ or Opcode2=JNS or
Opcode2=JS or Opcode2=JNV or Opcode2=JV or
Opcode2=JNC or Opcode2=JC) then
MAR <= x"000" & M2;
else
MAR <= std_logic_vector(PC);
end if;
end if;
stage1 <= S2;
when S2 =>
if (not stall) then
if (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= (x"000" & unsigned(M2))+1;
elsif ((Opcode2=JNZ and Z='1') or (Opcode2=JZ and Z = '0') or
(Opcode2=JNS and S = '1')or (Opcode2=JS and S = '0') or
(Opcode2=JNV and V = '1') or (Opcode2=JV and V = '0') or
(Opcode2=JNC and C = '1') or (Opcode2=JC and C = '0')) then
null;
else
PC <= PC + 1;
end if;
end if;
stage1 <= S1;
when others =>
null;
end case;
case stage2 is
when S1 =>
if (Opcode2=LDI) then
register_file(to_integer(unsigned(RX2)))<=(31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDH) then
register_file(to_integer(unsigned(RX2)))
<= I2 & register_file(to_integer(unsigned(RX2)))(15 downto 0);
--(31 downto 16)<= I2;
elsif (Opcode2=LDL) then
register_file(to_integer(unsigned(RX2)))
<= register_file(to_integer(unsigned(RX2)))(31 downto 16) & I2;
--(15 downto 0)<= I2;
elsif (Opcode2=MOV) then
register_file(to_integer(unsigned(RX2)))<=register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=ADD or Opcode2=SUB or Opcode2=MUL or Opcode2=CMP or
Opcode2=IAND or Opcode2=IOR or Opcode2=IXOR) then
operand1 <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=IROR) then
null;
elsif (Opcode2=ADI or Opcode2=CMPI) then
operand1 <= (31 downto 16=>I2(15)) & I2;
elsif (Opcode2=LDM) then
MAR <= x"000" & M2;
elsif (Opcode2=LDR) then
MAR <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=LDIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RY2))))
+ unsigned(M2));
elsif (Opcode2=STM) then
MAR <= x"000" & M2; MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2=STR) then
MAR <= register_file(to_integer(unsigned(RX2)));
MDR_out <= register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=STIX) then
MAR <= std_logic_vector(unsigned(
register_file(to_integer(unsigned(RX2))))
+ unsigned(M2));
MDR_out <=
register_file(to_integer(unsigned(RY2)));
elsif (Opcode2=JMP or
(Opcode2=JNZ and Z='0') or (Opcode2=JZ and Z='1') or
(Opcode2=JNS and S='0') or (Opcode2=JS and S='1') or
(Opcode2=JNV and V='0') or (Opcode2=JV and V='1') or
(Opcode2=JNC and C='0') or (Opcode2=JC and C='1') ) then
PC <= x"000" & unsigned(M2);
elsif (Opcode2=CALL or Opcode2=PUSH or Opcode2=SYS) then
SP <= SP + 1;
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MAR <= std_logic_vector(SP);
elsif (Opcode2=SIG0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),1)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),8)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),7)))(31 downto 0);
elsif (Opcode2=SIG1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),19)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),61)) xor
std_logic_vector(shift_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),6)))(31 downto 0);
elsif (Opcode2 = ADD64) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) + (unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))))(31 downto 0);
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector(unsigned(((register_file(to_integer(unsigned(RB2)))& register_file(to_integer(unsigned(RC2)))) xor ((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and ((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) xor (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))))) +
unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),14)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),18)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),41)))
+ (unsigned(register_file(to_integer(unsigned(RD2)))) & unsigned(register_file(to_integer(unsigned(RE2)))) + 0))(31 downto 0);
tmpx <= std_logic_vector(register_file(to_integer(unsigned(RX2))));
tmpy <= std_logic_vector(register_file(to_integer(unsigned(RY2))));
elsif (Opcode2 = T12) then
register_file(to_integer(unsigned(RX2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <=
std_logic_vector((unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2))))) +
(unsigned(register_file(to_integer(unsigned(RZ2)))) & unsigned(register_file(to_integer(unsigned(RA2))))) +
(unsigned(register_file(to_integer(unsigned(RB2)))) & unsigned(register_file(to_integer(unsigned(RC2))))))(31 downto 0);
elsif (Opcode2 = T2) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector((unsigned(std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),28)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),34)) xor
std_logic_vector(rotate_right(unsigned(register_file(to_integer(unsigned(RX2)))) & unsigned(register_file(to_integer(unsigned(RY2)))),39))) +
unsigned(((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))))xor
((register_file(to_integer(unsigned(RX2))) & register_file(to_integer(unsigned(RY2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2)))))xor
((register_file(to_integer(unsigned(RZ2))) & register_file(to_integer(unsigned(RA2)))) and (register_file(to_integer(unsigned(RB2))) & register_file(to_integer(unsigned(RC2))))))))(31 downto 0);
elsif (Opcode2 = WLOAD) then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
h5 <= H5_INIT;
h6 <= H6_INIT;
h7 <= H7_INIT;
wva <= H0_INIT;
wvb <= H1_INIT;
wvc <= H2_INIT;
wvd <= H3_INIT;
wve <= H4_INIT;
wvf <= H5_INIT;
wvg <= H6_INIT;
wvh <= H7_INIT;
elsif (Opcode2 = WPAD) then
if (rcount < 80) then
wout <= std_logic_vector(mvect(to_integer(unsigned(register_file(to_integer(unsigned(RX2)))))));
end if;
elsif (Opcode2 = WPAD2) then
if (rcount < 80) then
wout <= std_Logic_vector(
unsigned(unsigned(rotate_right(unsigned(mvect(14)),19)) xor unsigned(rotate_right(unsigned(mvect(14)),61)) xor unsigned(shift_right(unsigned(mvect(14)),6))) +
unsigned(mvect(9)) +
unsigned(unsigned(rotate_right(unsigned(mvect(1)),1)) xor unsigned(rotate_right(unsigned(mvect(1)),8)) xor unsigned(shift_right(unsigned(mvect(1)),7))) +
unsigned(mvect(0)));
end if;
elsif (Opcode2= MLOAD0) then
mvect(0) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(1) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(2) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(3) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD1) then
mvect(4) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(5) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(6) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(7) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD2) then
mvect(8) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(9) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(10) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(11) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2= MLOAD3) then
mvect(12) <= (std_logic_vector(register_file(to_integer(unsigned(RX2)))) & std_logic_vector(register_file(to_integer(unsigned(RY2)))));
mvect(13) <= (std_logic_vector(register_file(to_integer(unsigned(RZ2)))) & std_logic_vector(register_file(to_integer(unsigned(RA2)))));
mvect(14) <= (std_logic_vector(register_file(to_integer(unsigned(RB2)))) & std_logic_vector(register_file(to_integer(unsigned(RC2)))));
mvect(15) <= (std_logic_vector(register_file(to_integer(unsigned(RD2)))) & std_logic_vector(register_file(to_integer(unsigned(RE2)))));
elsif (Opcode2 = MSTM0) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm0))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm0))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm1))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm1))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm2))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm2))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm3))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm3))(31 downto 0);
elsif (Opcode2 = MSTM1) then
register_file(to_integer(unsigned(RX2))) <= std_logic_vector(unsigned(dm4))(63 downto 32);
register_file(to_integer(unsigned(RY2))) <= std_logic_vector(unsigned(dm4))(31 downto 0);
register_file(to_integer(unsigned(RZ2))) <= std_logic_vector(unsigned(dm5))(63 downto 32);
register_file(to_integer(unsigned(RA2))) <= std_logic_vector(unsigned(dm5))(31 downto 0);
register_file(to_integer(unsigned(RB2))) <= std_logic_vector(unsigned(dm6))(63 downto 32);
register_file(to_integer(unsigned(RC2))) <= std_logic_vector(unsigned(dm6))(31 downto 0);
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(unsigned(dm7))(63 downto 32);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(unsigned(dm7))(31 downto 0);
elsif (Opcode2 = FIN) then
dm0 <= std_logic_vector(unsigned(wva) + unsigned(h0));
dm1 <= std_logic_vector(unsigned(wvb) + unsigned(h1));
dm2 <= std_logic_vector(unsigned(wvc) + unsigned(h2));
dm3 <= std_logic_vector(unsigned(wvd) + unsigned(h3));
dm4 <= std_logic_vector(unsigned(wve) + unsigned(h4));
dm5 <= std_logic_vector(unsigned(wvf) + unsigned(h5));
dm6 <= std_logic_vector(unsigned(wvg) + unsigned(h6));
dm7 <= std_logic_vector(unsigned(wvh) + unsigned(h7));
end if;
stage2 <= S2;
when S2 =>
if (Opcode2=ADD or Opcode2=SUB or Opcode2=IROR or Opcode2=IAND or
Opcode2=MUL or Opcode2=IOR or Opcode2=IXOR or Opcode2=ADI) then
register_file(to_integer(unsigned(RX2))) <= ALU_out;
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC
elsif (Opcode2=CMP or Opcode2=CMPI) then
Z <= zero; S <= ALU_out(31); V <= overflow; C <= carry; --update CC only
elsif (Opcode2=LDM or Opcode2=LDR or Opcode2=LDIX) then
MDR_in <= MEM_in;
elsif (Opcode2=STM or Opcode2=STR or Opcode2=STIX) then
null;
elsif (Opcode2=CALL or Opcode2=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= std_logic_vector(PC);
elsif (Opcode2=RET or Opcode2=RETI or Opcode2=POP) then
MDR_in <= MEM_IN; SP <= SP - 1;
elsif (Opcode2=PUSH) then
MAR <= std_logic_vector(SP);
MDR_out <= register_file(to_integer(unsigned(RX2)));
elsif (Opcode2 = T11) then
register_file(to_integer(unsigned(RD2))) <= std_logic_vector(tmpx);
register_file(to_integer(unsigned(RE2))) <= std_logic_vector(tmpy);
elsif (Opcode2 = WPAD) then
if (rcount < 80) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
elsif (Opcode2 = WPAD2) then
if (rcount < 80) then
t1_val <= std_logic_vector(
(unsigned(wvh) +
(unsigned(rotate_right(unsigned(wve), 14)) xor unsigned(rotate_right(unsigned(wve), 18)) xor unsigned(rotate_right(unsigned(wve), 41))) +
((unsigned(wve) and unsigned(wvf)) xor (not(unsigned(wve)) and unsigned(wvg))) +
(unsigned(K_TABLE(to_integer(unsigned(register_file(to_integer(unsigned(RX2))))))) + unsigned(wout))
));
t2_val <= std_logic_vector(
(unsigned(rotate_right(unsigned(wva), 28)) xor unsigned(rotate_right(unsigned(wva), 34)) xor unsigned(rotate_right(unsigned(wva), 39))) +
(((unsigned(wva)) and (unsigned(wvb))) xor ((unsigned(wva)) and (unsigned(wvc))) xor ((unsigned(wvb)) and (unsigned(wvc))))
);
end if;
end if;
stage2 <= S1;
when others =>
null;
end case;
case stage3 is
when S1 =>
if (Opcode3=LDM or Opcode3=LDR or Opcode3=LDIX) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=STM or Opcode3=STR or Opcode3=STIX) then
null;
elsif (Opcode3=CALL) then
PC <= x"000" & unsigned(M3);
elsif (Opcode3=POP) then
register_file(to_integer(unsigned(RX3))) <= MDR_in;
elsif (Opcode3=RET) then
PC <= unsigned(MDR_in);
elsif (Opcode3=RETI) then
PSW <= MDR_in; MAR <= std_logic_vector(SP);
elsif (Opcode3=PUSH) then
null;
elsif (Opcode3=SYS) then
SP <= SP + 1;
elsif(Opcode3 = WPAD) then
if (rcount < 80) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
rcount <= rcount + 1;
end if;
elsif(Opcode3 = WPAD2) then
if (rcount < 80) then
wvh <= wvg;
wvg <= wvf;
wvf <= wve;
wve <= std_logic_vector(unsigned(wvd) + unsigned(t1_val));
wvd <= wvc;
wvc <= wvb;
wvb <= wva;
wva <= std_logic_vector(unsigned(t1_val) + unsigned(t2_val));
mvect(0) <= mvect(1);
mvect(1) <= mvect(2);
mvect(2) <= mvect(3);
mvect(3) <= mvect(4);
mvect(4) <= mvect(5);
mvect(5) <= mvect(6);
mvect(6) <= mvect(7);
mvect(7) <= (mvect(8));
mvect(8) <= (mvect(9));
mvect(9) <= (mvect(10));
mvect(10) <= (mvect(11));
mvect(11) <= (mvect(12));
mvect(12) <= (mvect(13));
mvect(13) <= (mvect(14));
mvect(14) <= (mvect(15));
mvect(15) <= wout;
rcount <= rcount + 1;
end if;
end if;
stage3 <= S2;
when S2 =>
if (Opcode3=RETI) then
MDR_in <= MEM_IN; sp <= sp - 1;
elsif (Opcode3=SYS) then
MAR <= std_logic_vector(SP);
MDR_out <= PSW;
elsif (Opcode3 = WPAD2) then
end if;
stage3 <= S1;
when others =>
null;
end case;
case stage4 is
when S1 =>
if (Opcode4=RETI) then
PC <= unsigned(MDR_in);
elsif (Opcode4=SYS) then
PC <= X"000FFC0"&unsigned(IR4(3 downto 0));
else stage4 <= S2;
end if;
stage4 <= S2;
when S2 =>
stage4 <= S1;
when others =>
null;
end case;
end if;
end process;
--------------------ALU----------------------------
Rhody_ALU: entity work.alu port map(
alu_op => IR2(28 downto 26),
operand0 => operand0,
operand1 => operand1,
n => IR2(4 downto 0),
alu_out => ALU_out,
carry => carry,
overflow => overflow);
zero <= '1' when alu_out = X"00000000" else '0';
operand0 <= register_file(to_integer(unsigned(RX2)));
-----------------------------------------------------
end Structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc110.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00110ent IS
port (S1 : out BIT_VECTOR(0 to 3) := "1011");
END c04s03b02x00p29n06i00110ent;
ARCHITECTURE c04s03b02x00p29n06i00110arch OF c04s03b02x00p29n06i00110ent IS
signal S2,S3 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
if (S1'LOW = 0) then
S2 <= '1' after 10 ns;
end if;
if (S1'HIGH = 3) then
S3 <= '1' after 10 ns;
end if;
wait for 20 ns;
assert NOT(S2='1' and S3='1')
report "***PASSED TEST: c04s03b02x00p29n06i00110"
severity NOTE;
assert (S2='1' and S3='1')
report "***FAILED TEST: c04s03b02x00p29n06i00110 - Reading of the attributes LOW and HIGH of the interface element of mode out is allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00110arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc110.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00110ent IS
port (S1 : out BIT_VECTOR(0 to 3) := "1011");
END c04s03b02x00p29n06i00110ent;
ARCHITECTURE c04s03b02x00p29n06i00110arch OF c04s03b02x00p29n06i00110ent IS
signal S2,S3 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
if (S1'LOW = 0) then
S2 <= '1' after 10 ns;
end if;
if (S1'HIGH = 3) then
S3 <= '1' after 10 ns;
end if;
wait for 20 ns;
assert NOT(S2='1' and S3='1')
report "***PASSED TEST: c04s03b02x00p29n06i00110"
severity NOTE;
assert (S2='1' and S3='1')
report "***FAILED TEST: c04s03b02x00p29n06i00110 - Reading of the attributes LOW and HIGH of the interface element of mode out is allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00110arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc110.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n06i00110ent IS
port (S1 : out BIT_VECTOR(0 to 3) := "1011");
END c04s03b02x00p29n06i00110ent;
ARCHITECTURE c04s03b02x00p29n06i00110arch OF c04s03b02x00p29n06i00110ent IS
signal S2,S3 : BIT;
BEGIN
TESTING: PROCESS
BEGIN
if (S1'LOW = 0) then
S2 <= '1' after 10 ns;
end if;
if (S1'HIGH = 3) then
S3 <= '1' after 10 ns;
end if;
wait for 20 ns;
assert NOT(S2='1' and S3='1')
report "***PASSED TEST: c04s03b02x00p29n06i00110"
severity NOTE;
assert (S2='1' and S3='1')
report "***FAILED TEST: c04s03b02x00p29n06i00110 - Reading of the attributes LOW and HIGH of the interface element of mode out is allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n06i00110arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book (in text)
entity random_source is
generic ( min, max : natural;
seed : natural;
interval : delay_length );
port ( number : out natural );
end entity random_source;
-- end code from book
architecture fudged of random_source is
begin
process is
variable next_number : natural := seed;
begin
if next_number > max then
next_number := min;
end if;
number <= next_number;
next_number := next_number + 1;
wait for interval;
end process;
end architecture fudged;
entity test_bench is
end entity test_bench;
-- code from book
architecture random_test of test_bench is
subtype bv11 is bit_vector(10 downto 0);
function natural_to_bv11 ( n : natural ) return bv11 is
variable result : bv11 := (others => '0');
variable remaining_digits : natural := n;
begin
for index in result'reverse_range loop
result(index) := bit'val(remaining_digits mod 2);
remaining_digits := remaining_digits / 2;
exit when remaining_digits = 0;
end loop;
return result;
end function natural_to_bv11;
signal stimulus_vector : bv11;
-- . . .
begin
stimulus_generator : entity work.random_source
generic map ( min => 0, max => 2**10 - 1, seed => 0,
interval => 100 ns )
port map ( natural_to_bv11(number) => stimulus_vector );
-- . . .
end architecture random_test;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book (in text)
entity random_source is
generic ( min, max : natural;
seed : natural;
interval : delay_length );
port ( number : out natural );
end entity random_source;
-- end code from book
architecture fudged of random_source is
begin
process is
variable next_number : natural := seed;
begin
if next_number > max then
next_number := min;
end if;
number <= next_number;
next_number := next_number + 1;
wait for interval;
end process;
end architecture fudged;
entity test_bench is
end entity test_bench;
-- code from book
architecture random_test of test_bench is
subtype bv11 is bit_vector(10 downto 0);
function natural_to_bv11 ( n : natural ) return bv11 is
variable result : bv11 := (others => '0');
variable remaining_digits : natural := n;
begin
for index in result'reverse_range loop
result(index) := bit'val(remaining_digits mod 2);
remaining_digits := remaining_digits / 2;
exit when remaining_digits = 0;
end loop;
return result;
end function natural_to_bv11;
signal stimulus_vector : bv11;
-- . . .
begin
stimulus_generator : entity work.random_source
generic map ( min => 0, max => 2**10 - 1, seed => 0,
interval => 100 ns )
port map ( natural_to_bv11(number) => stimulus_vector );
-- . . .
end architecture random_test;
-- end code from book
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- code from book (in text)
entity random_source is
generic ( min, max : natural;
seed : natural;
interval : delay_length );
port ( number : out natural );
end entity random_source;
-- end code from book
architecture fudged of random_source is
begin
process is
variable next_number : natural := seed;
begin
if next_number > max then
next_number := min;
end if;
number <= next_number;
next_number := next_number + 1;
wait for interval;
end process;
end architecture fudged;
entity test_bench is
end entity test_bench;
-- code from book
architecture random_test of test_bench is
subtype bv11 is bit_vector(10 downto 0);
function natural_to_bv11 ( n : natural ) return bv11 is
variable result : bv11 := (others => '0');
variable remaining_digits : natural := n;
begin
for index in result'reverse_range loop
result(index) := bit'val(remaining_digits mod 2);
remaining_digits := remaining_digits / 2;
exit when remaining_digits = 0;
end loop;
return result;
end function natural_to_bv11;
signal stimulus_vector : bv11;
-- . . .
begin
stimulus_generator : entity work.random_source
generic map ( min => 0, max => 2**10 - 1, seed => 0,
interval => 100 ns )
port map ( natural_to_bv11(number) => stimulus_vector );
-- . . .
end architecture random_test;
-- end code from book
|
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: top_nto1_pll_diff_tx
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: June 1 2009
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: Example differential output transmitter for clock and data using PLL
-- Serdes factor and number of data lines are set by constants in the code
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
--
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity top_nto1_pll_diff_tx is port (
refclkin_p, refclkin_n : in std_logic ; -- reference clock input
reset : in std_logic ; -- reset (active high)
clkout_p, clkout_n : out std_logic ; -- lvds clock output
dataout_p, dataout_n : out std_logic_vector(5 downto 0)) ; -- lvds data outputs
end top_nto1_pll_diff_tx ;
architecture arch_top_nto1_pll_diff_tx of top_nto1_pll_diff_tx is
component serdes_n_to_1_s8_diff is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
txioclk : in std_logic ; -- IO Clock network
txserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset
gclk : in std_logic ; -- Global clock
datain : in std_logic_vector((D*S)-1 downto 0) ; -- Data for output
dataout_p : out std_logic_vector(D-1 downto 0) ; -- output
dataout_n : out std_logic_vector(D-1 downto 0)) ; -- output
end component ;
component clock_generator_pll_s8_diff is generic (
PLLD : integer := 1 ; -- Parameter to set the division factor in the PLL
PLLX : integer := 8 ; -- Parameter to set the multiplication factor in the PLL
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
CLKIN_PERIOD : real := 6.000) ; -- clock period (ns) of input clock on clkin_p
port (
reset : in std_logic ; -- reset (active high)
clkin_p, clkin_n : in std_logic ; -- differential clock input
ioclk : out std_logic ; -- ioclock from BUFPLL
serdesstrobe : out std_logic ; -- serdes strobe from BUFPLL
gclk : out std_logic ; -- global clock output from BUFG x1
bufpll_lckd : out std_logic) ; -- Locked output from BUFPLL
end component ;
-- Parameters for serdes factor and number of IO pins
constant S : integer := 7 ; -- Set the serdes factor to be 7
constant D : integer := 6 ; -- Set the number of inputs and outputs to be 6
constant DS : integer := (D*S)-1 ; -- Used for bus widths = serdes factor * number of inputs - 1
signal tx_bufpll_lckd : std_logic ;
signal txd : std_logic_vector(DS downto 0) ;
signal tx_bufg_x1 : std_logic ;
signal rst : std_logic ;
signal tx_bufpll_clk_xn : std_logic ;
signal temp1p : std_logic_vector(0 downto 0) ;
signal temp1n : std_logic_vector(0 downto 0) ;
signal tx_serdesstrobe : std_logic ;
-- Parameters for pin swapping and clock generation
constant TX_CLK_GEN : std_logic_vector(S-1 downto 0) := "1100001" ; -- Transmit a constant to make a clock
begin
rst <= reset ; -- active high reset pin
-- Frequency Generator Clock Input
clkgen : clock_generator_pll_s8_diff generic map(
S => S,
PLLX => 7,
PLLD => 1,
CLKIN_PERIOD => 7.000)
port map (
reset => rst,
clkin_p => refclkin_p,
clkin_n => refclkin_n,
ioclk => tx_bufpll_clk_xn,
serdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
bufpll_lckd => tx_bufpll_lckd) ;
process (tx_bufg_x1, rst) -- Generate some data to transmit
begin
if rst = '1' then
txd <= (0 => '1', others => '0') ;
elsif tx_bufg_x1'event and tx_bufg_x1 = '1' then
txd <= txd(40 downto 0) & txd(41) ;
end if ;
end process ;
-- Transmitter Logic - Instantiate serialiser to generate forwarded clock
clkout : serdes_n_to_1_s8_diff generic map (
S => S,
D => 1)
port map (
dataout_p => temp1p,
dataout_n => temp1n,
txioclk => tx_bufpll_clk_xn,
txserdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
reset => rst,
datain => TX_CLK_GEN); -- Transmit a constant to make the clock
clkout_p <= temp1p(0) ;
clkout_n <= temp1n(0) ;
-- Instantiate Outputs and output serialisers for output data lines
dataout : serdes_n_to_1_s8_diff generic map(
S => S,
D => D)
port map (
dataout_p => dataout_p,
dataout_n => dataout_n,
txioclk => tx_bufpll_clk_xn,
txserdesstrobe => tx_serdesstrobe,
gclk => tx_bufg_x1,
reset => rst,
datain => txd);
end arch_top_nto1_pll_diff_tx ; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#0d0007#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 1;
constant CFG_SPICTRL_NUM : integer := (1);
constant CFG_SPICTRL_SLVS : integer := (1);
constant CFG_SPICTRL_FIFO : integer := (2);
constant CFG_SPICTRL_SLVREG : integer := 1;
constant CFG_SPICTRL_ODMODE : integer := 1;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 1;
constant CFG_SPICTRL_MAXWLEN : integer := (0);
constant CFG_SPICTRL_SYNCRAM : integer := 1;
constant CFG_SPICTRL_FT : integer := 0;
-- SPI to AHB bridge
constant CFG_SPI2AHB : integer := 0;
constant CFG_SPI2AHB_APB : integer := 0;
constant CFG_SPI2AHB_ADDRH : integer := 16#0#;
constant CFG_SPI2AHB_ADDRL : integer := 16#0#;
constant CFG_SPI2AHB_MASKH : integer := 16#0#;
constant CFG_SPI2AHB_MASKL : integer := 16#0#;
constant CFG_SPI2AHB_RESEN : integer := 0;
constant CFG_SPI2AHB_FILTER : integer := 2;
constant CFG_SPI2AHB_CPOL : integer := 0;
constant CFG_SPI2AHB_CPHA : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#fe#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: clkgen_xilinx.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Virtex-2 and Virtex-4
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDDR;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex4 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex4_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex4_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute keep of rclk90b : signal is true;
attribute syn_keep : boolean;
attribute syn_keep of rclk90b : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of rclk90b : signal is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation
ddrref_pad : clkpad generic map (tech => virtex4)
port map (ddr_clk_fb, ddrclkfbl);
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dllfb <= clk_0r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR port map ( Q => ddr_clk_fb_outr, C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR port map ( Q => ddr_clkbl(i), C => clk90r, CE => vcc,
D1 => gnd, D2 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk0r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk0r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk0r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk0r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk0r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clk0r, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk0r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk0r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), -- 1-bit output for negative edge of clock
C => rclk90b, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clk0r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.FDDRRSE;
use unisim.IFDDRRSE;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrv2;
------------------------------------------------------------------
-- Virtex2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex2_ddr_phy is
generic(
MHz : integer := 100;
rstdelay: integer := 200;
dbits : integer := 16;
clk_mul : integer := 2;
clk_div : integer := 2;
rskew : integer := 0
);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex2_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FDDRRSE
-- generic ( INIT : bit := '0');
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IFDDRRSE
port (
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component oddrv2
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : FDDRRSE port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : FDDRRSE port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : FDDRRSE port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2 port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IFDDRRSE
port map(
Q0 => dqinl(i), -- 1-bit output for positive edge of clock
Q1 => dqin(i), -- 1-bit output for negative edge of clock
C0 => rclk90b, -- clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
C1 => rclk270b, -- clk90r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dq(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map(
Q => dqin(i+dbits),
C => rclk270b,
D => dqinl(i)
);
dout : oddrv2
port map(
Q => ddr_dqout(i),
C1 => clk0r,
C2 => clk180r,
CE => vcc,
D1 => dqout(i+dbits),
D2 => dqout(i),
R => gnd,
S => gnd
);
doen : FD
port map(
Q => ddr_dqoen(i),
C => clk0r,
D => oen
);
dq_pad : iopad
generic map(
tech => virtex4,
level => sstl2_ii
)
port map(
pad => ddr_dq(i),
i => ddr_dqout(i),
en => ddr_dqoen(i),
o => open
); -- o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR2;
use unisim.IDDR2;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrc3e;
------------------------------------------------------------------
-- Spartan3E DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity spartan3e_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of spartan3e_ddr_phy is
component oddrc3e
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r;
-- clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR2 port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR2 port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR2 port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
clkread <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR2
port map ( Q0 => dqinl(i), Q1 => dqin(i), C0 => rclk90b, C1 => rclk270b,
CE => vcc, D => ddr_dqin(i), R => gnd, S => gnd );
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrc3e
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDELAY;
use unisim.ISERDES;
use unisim.BUFIO;
use unisim.IDELAYCTRL;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex5 DDR2 PHY ----------------------------------------------
------------------------------------------------------------------
entity virtex5_ddr2_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; tech : integer := virtex5);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex5_ddr2_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
-- component BUFIO
-- port ( O : out std_ulogic;
-- I : in std_ulogic);
-- end component;
component IDELAY
generic ( IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0);
port ( O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic);
end component;
-- component ISERDES
-- generic
-- (
-- BITSLIP_ENABLE : boolean := false;
-- DATA_RATE : string := "DDR";
-- DATA_WIDTH : integer := 4;
-- INIT_Q1 : bit := '0';
-- INIT_Q2 : bit := '0';
-- INIT_Q3 : bit := '0';
-- INIT_Q4 : bit := '0';
-- INTERFACE_TYPE : string := "MEMORY";
-- IOBDELAY : string := "NONE";
-- IOBDELAY_TYPE : string := "DEFAULT";
-- IOBDELAY_VALUE : integer := 0;
-- NUM_CE : integer := 2;
-- SERDES_MODE : string := "MASTER";
-- SRVAL_Q1 : bit := '0';
-- SRVAL_Q2 : bit := '0';
-- SRVAL_Q3 : bit := '0';
-- SRVAL_Q4 : bit := '0'
-- );
-- port
-- (
-- O : out std_ulogic;
-- Q1 : out std_ulogic;
-- Q2 : out std_ulogic;
-- Q3 : out std_ulogic;
-- Q4 : out std_ulogic;
-- Q5 : out std_ulogic;
-- Q6 : out std_ulogic;
-- SHIFTOUT1 : out std_ulogic;
-- SHIFTOUT2 : out std_ulogic;
-- BITSLIP : in std_ulogic;
-- CE1 : in std_ulogic;
-- CE2 : in std_ulogic;
-- CLK : in std_ulogic;
-- CLKDIV : in std_ulogic;
-- D : in std_ulogic;
-- DLYCE : in std_ulogic;
-- DLYINC : in std_ulogic;
-- DLYRST : in std_ulogic;
-- OCLK : in std_ulogic;
-- REV : in std_ulogic;
-- SHIFTIN1 : in std_ulogic;
-- SHIFTIN2 : in std_ulogic;
-- SR : in std_ulogic
-- );
-- end component;
component IDELAYCTRL
port ( RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic);
end component;
--signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin, ddr_dqin_nodel : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk, dqsclkn : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
signal clk200, clk200_0, clk200fb, clk200fx, lock200 : std_logic;
signal odtl : std_logic_vector(1 downto 0);
signal refclk_rdy : std_logic_vector(numidelctrl-1 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
type ddelay_type is array (7 downto 0) of integer;
constant ddelay : ddelay_type := (ddelayb0, ddelayb1, ddelayb2,
ddelayb3, ddelayb4, ddelayb5,
ddelayb6, ddelayb7);
attribute syn_noprune : boolean;
attribute syn_noprune of IDELAYCTRL : component is true;
attribute syn_keep : boolean;
attribute syn_keep of dqsclk : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of dqsclk : signal is true;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute keep : boolean;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
begin
-- Generate 200 MHz ref clock if not supplied
refclkx : if norefclk = 0 generate
buf_clk200 : BUFG port map( I => clkref200, O => clk200);
lock200 <= '1';
end generate;
norefclkx : if norefclk /= 0 generate
bufg0 : BUFG port map (I => clk200fx, O => clk200);
bufg1 : BUFG port map (I => clk200_0, O => clk200fb);
HMODE_dll200 : if (tech = virtex4 and ((200 >= 210) or (MHz >= 210)))
or (tech = virtex5 and ((200 >= 140) or (MHz >= 140))) generate
dll200 : DCM
generic map (CLKFX_MULTIPLY => 2000/MHz, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
port map ( CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => clk200_0,
LOCKED => lock200, CLKFX => clk200fx);
end generate;
LMODE_dll200 : if not ((tech = virtex4 and ((200 >= 210) or (MHz >= 210)))
or (tech = virtex5 and ((200 >= 140) or (MHz >= 140)))) generate
dll200 : DCM
generic map (CLKFX_MULTIPLY => 2000/MHz, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => clk200_0,
LOCKED => lock200, CLKFX => clk200fx);
end generate;
end generate;
-- Delay control
idelctrl : for i in 0 to numidelctrl-1 generate
u : IDELAYCTRL port map (rst => dllrst(0), refclk => clk200, rdy => refclk_rdy(i));
end generate;
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
--mclk <= clk;
dll0rst <= dllrst;
mlock <= '1';
mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
HMODE_dllm : if (tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div >= 140) or (MHz >= 140))) generate
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
LMODE_dllm : if not ((tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div >= 140) or (MHz >= 140)))) generate
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
end generate;
-- DDR clock generation
-- bufg1 : BUFG port map (I => clk_0ro, O => clk0r);
clk0r <= mclk;
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
-- bufg3 : BUFG port map (I => clk_180ro, O => clk180r);
clk180r <= not mclk;
-- bufg4 : BUFG port map (I => clk_270ro, O => clk270r);
clkout <= clk0r;
-- dllfb <= clk0r;
dllfb <= clk90r;
HMODE_dll : if (tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120)) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
LMODE_dll : if not ((tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120))) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
-- dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2, CLKIN_PERIOD => 6.25,
-- DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "HIGH") --"HIGH")
-- port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
-- PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
-- CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
-- LOCKED => lockl);
rstdel : process (mclk, rst, mlock, lock200)
begin
if rst = '0' or mlock = '0' or lock200 = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
--rcnt : process (clk_0r)
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
--if rising_edge(clk_0r) then
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked and orv(refclk_rdy);
-- Generate external DDR clock
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_clk(i), ddr_clkl(i));
-- Diff ddr_clk
-- ddrclk_pad : outpad_ds generic map(tech => virtex5, level => sstl18_ii)
-- port map (ddr_clk(i), ddr_clkb(i), ddr_clkl(i), gnd);
dclk0rb : ODDR port map ( Q => ddr_clkbl(i), C => clk90r, CE => vcc,
D1 => gnd, D2 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
-- ODT pads
odtgen : for i in 0 to 1 generate
odtl(i) <= locked and orv(refclk_rdy) and odt(i);
ddr_odt_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_odt(i), odtl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk0r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
csn0_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk0r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
cke_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk0r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
rasn_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_rasb, ddr_rasnr);
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk0r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
casn_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_casb, ddr_casnr);
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk0r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
wen_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clk0r, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk0r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
ddr_ba_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk0r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
ddr_ad_pad : outpad generic map (tech => virtex5, level => sstl18_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
--dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
dsqreg : FD port map ( Q => dqsn(i), C => clk180r, D => oe);
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
--D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
D1 => dqsn(i), D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad_ds generic map (tech => virtex5, level => sstl18_ii)
port map (padp => ddr_dqs(i), padn => ddr_dqsn(i),i => ddr_dqsin(i),
en => ddr_dqsoen(i), o => ddr_dqsoutl(i));
-- del_dqs0 : IDELAY generic map(IOBDELAY_TYPE => "FIXED", IOBDELAY_VALUE => 10)
-- port map(O => dqsclk(i), I => ddr_dqsoutl(i), C => gnd, CE => gnd,
-- INC => gnd, RST => dllrst(0));
-- --buf_dqs0 : BUFIO port map(O => dqsclk(i), I => dqsdel(i));
-- dqsclkn(i) <= not dqsclk(i);
end generate;
-- Data bus
ddgen : for i in 0 to dbits-1 generate
del_dq0 : IDELAY generic map(IOBDELAY_TYPE => "VARIABLE", IOBDELAY_VALUE => ddelay(i/8))
--port map(O => ddr_dqin(i), I => ddr_dqin_nodel(i), C => clk_270r, CE => cal_en(i/8),
port map(O => ddr_dqin(i), I => ddr_dqin_nodel(i), C => clk0r, CE => cal_en(i/8),
INC => cal_inc(i/8), RST => cal_rst);
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), --dqin(i), -- 1-bit output for negative edge of clock
--C => clk_90r, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
C => clk180r, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
--dinq1 : FD port map ( Q => dqin(i+dbits), C => clk_270r, D => dqinl(i));
dinq1 : FD port map ( Q => dqin(i+dbits), C => clk0r, D => dqinl(i));
--dqi : ISERDES generic map(IOBDELAY => "IFD", IOBDELAY_TYPE => "FIXED", IOBDELAY_VALUE => 0)
-- port map(O => open, Q1 => dqin(i), Q2 => dqin(i+dbits), Q3 => open, Q4 => open, Q5 => open,
-- Q6 => open, SHIFTOUT1 => open, SHIFTOUT2 => open, BITSLIP => gnd,
-- CE1 => vcc, CE2 => vcc, CLK => dqsclk(i/8), CLKDIV => clk0r, D => ddr_dqin(i),
-- DLYCE => gnd, DLYINC => gnd, DLYRST => gnd, OCLK => clk0r, REV => gnd,
-- SHIFTIN1 => gnd, SHIFTIN2 => gnd, SR => gnd);
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clk0r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex5, level => sstl18_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin_nodel(i)); --o => ddr_dqin(i));
end generate;
end;
|
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 21:50:03 03/21/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: top - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use IEEE.std_logic_arith.all;
entity top is
generic(
reg_num : integer := 32; -- number of registers in register field
reg_width : integer := 16; -- register width in register field
baud_rate : integer := 19200;
data_bits : integer := 8; -- fifo is 8 bit, but a new one can be generated
stop_bits : real := 1.0
);
port(
clk : in std_logic;
reset : in std_logic;
rx : in std_logic;
tx : out std_logic ;
rot_a : in std_logic;
rot_b : in std_logic;
sw0 : in std_logic;
sw1 : in std_logic;
sw2 : in std_logic;
sw3 : in std_logic;
lcd_dout : out std_logic_vector(3 downto 0);
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_e : out std_logic;
renew_reg : in std_logic;
led : out std_logic_vector(7 downto 0)
);
end top;
architecture Behavioral of top is
component rate_generator is
generic(
dvsr : integer := 2604
);
port(
clk : in std_logic;
reset : in std_logic;
b_edge : out std_logic
);
end component;
component uart_rx is
generic(
dbits : integer := 8;
sb_ticks : integer := 16 -- 16 for 1 stop bit, 24 for 1.5, 32 for 2
);
port(
clk : in std_logic;
reset : in std_logic;
b_edge : in std_logic;
rx: in std_logic;
rx_data : out std_logic_vector((dbits-1) downto 0);
rx_done : out std_logic
);
end component;
component uart_tx is
generic(
dbits : integer := 8;
sb_ticks : integer := 16 -- 16 for 1 stop bit, 24 for 1.5, 32 for 2
);
port(
clk : in std_logic;
reset : in std_logic;
b_edge : in std_logic;
tx_start : in std_logic;
tx_data : in std_logic_vector((dbits-1) downto 0);
tx_done : out std_logic;
tx : out std_logic
);
end component;
COMPONENT fifo_rx
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_tx
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_uart IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT fifo_uart_long IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_uart_long3 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fifo_uart_long_w_outp IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT;
component disp_controller
port(
clk : in std_logic;
reset : in std_logic;
din : in std_logic_vector(7 downto 0);
data_count : in std_logic_vector(5 downto 0);
show_data : in std_logic;
get_data_o : out std_logic;
dout : out std_logic_vector(3 downto 0);
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_e : out std_logic
);
end component;
component reg_file_controller is
generic(
reg_num : integer := 32;
reg_width : integer := 32;
rf_addr_w : integer := 5;
data_bits : integer := 8
);
port(
clk : in std_logic;
reset : in std_logic;
rx_din : in std_logic_vector(data_bits - 1 downto 0);
renew : in std_logic;
rx_req : out std_logic;
tx_req : out std_logic;
rf_req : out std_logic;
tx_dout : out std_logic_vector(data_bits - 1 downto 0);
rf_dout : out std_logic_vector(reg_width - 1 downto 0);
rf_addr : out std_logic_vector(rf_addr_w - 1 downto 0)
);
end component;
component register_file is
generic(
addr_width : integer := 5; -- log2(number of regs)
reg_width : integer := 32 -- width of a reg
);
port(
clk : in std_logic;
reset : in std_logic;
wr_en : in std_logic;
wr_addr : in std_logic_vector(addr_width - 1 downto 0);
wr_data : in std_logic_vector(reg_width - 1 downto 0);
rd_addr : in std_logic_vector(addr_width - 1 downto 0);
rd_data : out std_logic_vector(reg_width - 1 downto 0);
rd_addr_2 : in std_logic_vector(addr_width - 1 downto 0);
rd_data_2 : out std_logic_vector(reg_width - 1 downto 0);
rd_addr_3 : in std_logic_vector(addr_width - 1 downto 0);
rd_data_3 : out std_logic_vector(reg_width - 1 downto 0)
);
end component;
component show_controller is
generic(
addr_width : integer := 5; -- log2(number of regs)
reg_width : integer := 32 -- width of a reg
);
port(
clk : in std_logic;
reset : in std_logic;
up : in std_logic;
down : in std_logic;
rf_data : in std_logic_vector(reg_width - 1 downto 0);
fifo_wr : out std_logic;
rf_addr : out std_logic_vector(addr_width - 1 downto 0);
show_dout : out std_logic_vector(7 downto 0);
data_count : out std_logic_vector(5 downto 0);
show_data : out std_logic
);
end component;
component show_fifo_wide IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
component rotary is
port(
clk : in std_logic;
rot_a : in std_logic;
rot_b : in std_logic;
up : out std_logic;
down : out std_logic
);
end component;
component switch_controller is
generic(
rf_addr_w : integer := 5;
reg_width : integer := 32
);
port(
clk : in std_logic;
reset : in std_logic;
sw0 : in std_logic;
sw1 : in std_logic;
sw2 : in std_logic;
sw3 : in std_logic;
rf_data : in std_logic_vector(reg_width - 1 downto 0);
rf_addr : out std_logic_vector(rf_addr_w - 1 downto 0);
led : out std_logic_vector(3 downto 0)
);
end component;
component led_controller is
generic(
rf_addr_w : integer := 5;
reg_width : integer := 32
);
port(
clk : in std_logic;
reset : in std_logic;
rf_data : in std_logic_vector(reg_width - 1 downto 0);
rf_addr : out std_logic_vector(rf_addr_w - 1 downto 0);
led : out std_logic_vector(3 downto 0)
);
end component;
attribute box_type : string;
attribute box_type of fifo_uart_long : component is "black_box";
attribute box_type of fifo_uart_long3 : component is "black_box";
attribute box_type of show_fifo_wide : component is "black_box";
constant dvsr : integer := integer(round(real(50000000/(baud_rate*16))));
constant stop_bit_ticks : integer := integer(stop_bits*16.0);
constant rf_addr_w : integer := integer(ceil(log2(real(reg_num))));
signal b_edge : std_logic;
signal rx_data : std_logic_vector((data_bits-1) downto 0);
signal tx_data : std_logic_vector((data_bits-1) downto 0);
signal rx_done : std_logic;
signal tx_done : std_logic;
signal got_data : std_logic_vector(7 downto 0);
signal to_send_data : std_logic_vector(7 downto 0);
signal get_data : std_logic;
signal send_data : std_logic;
signal rx_full : std_logic;
signal tx_full : std_logic;
signal rx_empty : std_logic;
signal inv_in : std_logic;
signal inv_out : std_logic;
signal inv2_in : std_logic;
signal inv2_out : std_logic;
signal wr_rf : std_logic;
signal rf_wr_data : std_logic_vector(reg_width - 1 downto 0);
signal rf_wr_addr : std_logic_vector(rf_addr_w - 1 downto 0);
signal rf_rd_data : std_logic_vector(reg_width - 1 downto 0);
signal rf_rd_addr : std_logic_vector(rf_addr_w - 1 downto 0);
signal rf_rd_data2 : std_logic_vector(reg_width - 1 downto 0);
signal rf_rd_addr2 : std_logic_vector(rf_addr_w - 1 downto 0);
signal rf_rd_data3 : std_logic_vector(reg_width - 1 downto 0);
signal rf_rd_addr3 : std_logic_vector(rf_addr_w - 1 downto 0);
signal up : std_logic;
signal down : std_logic;
signal sh_ctrl_data : std_logic_vector(7 downto 0);
signal show_data : std_logic;
signal sh_get_data : std_logic;
signal data_count : std_logic_vector(5 downto 0);
signal show_wr_en : std_logic;
signal sh_ctrl_dout : std_logic_vector(7 downto 0);
signal show_full : std_logic;
signal show_empty : std_logic;
begin
inv_out <= not inv_in;
rate_gen_unit : rate_generator
generic map(dvsr => dvsr)
port map(clk => clk, reset => reset, b_edge => b_edge);
uart_rx_unit : uart_rx
generic map(dbits => data_bits, sb_ticks => stop_bit_ticks)
port map(clk => clk, reset => reset, b_edge => b_edge, rx => rx, rx_data => rx_data, rx_done => rx_done);
uart_tx_unit : uart_tx
generic map(dbits => data_bits, sb_ticks => stop_bit_ticks)
port map(clk => clk, reset => reset, b_edge => b_edge, tx_start => inv_out, tx_data => tx_data, tx_done => tx_done, tx => tx);
uart_rx_fifo : fifo_uart_long
port map(clk => clk, rst => reset, din => rx_data, wr_en => rx_done, rd_en => get_data, dout => got_data,
full => rx_full, empty => rx_empty);
uart_tx_fifo : fifo_uart_long3
port map(clk => clk, rst => reset, din => to_send_data, wr_en => send_data, rd_en => tx_done, dout => tx_data,
full => tx_full, empty => inv_in);
disp_ctrl : disp_controller
port map(clk => clk, reset => reset, din => sh_ctrl_dout, data_count => data_count, show_data => show_data,
get_data_o => sh_get_data, dout => lcd_dout, lcd_rs => lcd_rs, lcd_rw => lcd_rw, lcd_e => lcd_e);
rf_ctrl : reg_file_controller
generic map(reg_num => reg_num, reg_width => reg_width, rf_addr_w => rf_addr_w, data_bits => data_bits)
port map(clk => clk, reset => reset, rx_din => got_data, rx_req => get_data, renew => renew_reg,
tx_req => send_data, rf_req => wr_rf, tx_dout => to_send_data, rf_dout => rf_wr_data, rf_addr => rf_wr_addr
);
regfile : register_file
generic map(reg_width => reg_width, addr_width => rf_addr_w)
port map(clk => clk, reset => reset, wr_en => wr_rf, wr_addr => rf_wr_addr, rd_addr => rf_rd_addr,
wr_data => rf_wr_data, rd_data => rf_rd_data, rd_addr_2 => rf_rd_addr2, rd_data_2 => rf_rd_data2,
rd_addr_3 => rf_rd_addr3, rd_data_3 => rf_rd_data3);
show_ctrl : show_controller
generic map(reg_width => reg_width, addr_width => rf_addr_w)
port map(clk => clk, reset => reset, up => up, down => down, rf_data => rf_rd_data,
rf_addr => rf_rd_addr, show_dout => sh_ctrl_data, data_count => data_count, show_data => show_data, fifo_wr => show_wr_en);
show_ctrl_fifo : show_fifo_wide
port map(clk => clk, rst => reset, din => sh_ctrl_data, wr_en => show_wr_en, rd_en => sh_get_data, dout => sh_ctrl_dout,
full => show_full, empty => show_empty);
rot_ctrl : rotary
port map(clk => clk, rot_a => rot_a, rot_b => rot_b, up => up, down => down);
sw_ctrl : switch_controller
generic map(reg_width => reg_width, rf_addr_w => rf_addr_w)
port map(clk => clk, reset => reset, sw0 => sw0, sw1 => sw1, sw2 => sw2, sw3 => sw3,
rf_data => rf_rd_data2, rf_addr => rf_rd_addr2, led => led(3 downto 0));
l_ctrl : led_controller
generic map(reg_width => reg_width, rf_addr_w => rf_addr_w)
port map(clk => clk, reset => reset, rf_data => rf_rd_data3, rf_addr => rf_rd_addr3, led => led(7 downto 4));
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy_datapath
-- File: ddrphy_datapath.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR/DDR2 PHY data path (digital part of phy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ddrphy_datapath is
generic (
regtech: integer := 0;
dbits: integer;
abits: integer;
bankbits: integer range 2 to 3 := 2;
ncs: integer;
nclk: integer;
-- Enable extra resync stage clocked by clkresync
resync: integer range 0 to 2 := 0
);
port (
clk0: in std_ulogic;
clk90: in std_ulogic;
clk180: in std_ulogic;
clk270: in std_ulogic;
clkresync: in std_ulogic;
ddr_clk: out std_logic_vector(nclk-1 downto 0);
ddr_clkb: out std_logic_vector(nclk-1 downto 0);
ddr_dq_in: in std_logic_vector(dbits-1 downto 0);
ddr_dq_out: out std_logic_vector(dbits-1 downto 0);
ddr_dq_oen: out std_logic_vector(dbits-1 downto 0);
ddr_dqs_in90: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_in90n: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_out: out std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_oen: out std_logic_vector(dbits/8-1 downto 0);
ddr_cke: out std_logic_vector(ncs-1 downto 0);
ddr_csb: out std_logic_vector(ncs-1 downto 0);
ddr_web: out std_ulogic;
ddr_rasb: out std_ulogic;
ddr_casb: out std_ulogic;
ddr_ad: out std_logic_vector(abits-1 downto 0);
ddr_ba: out std_logic_vector(bankbits-1 downto 0);
ddr_dm: out std_logic_vector(dbits/8-1 downto 0);
ddr_odt: out std_logic_vector(ncs-1 downto 0);
-- Control signals synchronous to clk0
dqin: out std_logic_vector(dbits*2-1 downto 0);
dqout: in std_logic_vector(dbits*2-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (bankbits-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0); -- Clk enable control signal to memory
odt : in std_logic_vector(ncs-1 downto 0);
dqs_en : in std_ulogic; -- Run dqs strobe (active low)
dqs_oen : in std_ulogic; -- DQS output enable (active low)
ddrclk_en : in std_logic_vector(nclk-1 downto 0) -- Enable/stop ddr_clk
);
end;
architecture rtl of ddrphy_datapath is
signal vcc,gnd: std_ulogic;
signal dqs_en_inv,dqs_en_inv180: std_ulogic;
signal dqcaptr,dqcaptf: std_logic_vector(dbits-1 downto 0);
signal dqsyncr,dqsyncf: std_logic_vector(dbits-1 downto 0);
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- DDR interface clock signal
-----------------------------------------------------------------------------
-- 90 degree shifted relative to master clock, gated by ddrclk_en
genclk: for x in 0 to nclk-1 generate
clkreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => ddrclk_en(x), d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clk(x));
clkbreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => gnd, d2 => ddrclk_en(x), ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clkb(x));
end generate;
-----------------------------------------------------------------------------
-- Control signals RAS,CAS,WE,BA,ADDR,CS,ODT,CKE
-----------------------------------------------------------------------------
rasreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => rasn, q => ddr_rasb);
casreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => casn, q => ddr_casb);
wereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => wen, q => ddr_web);
genba: for x in 0 to bankbits-1 generate
bareg: grdff generic map (tech => regtech)
port map (clk => clk0, d => ba(x), q => ddr_ba(x));
end generate;
gencs: for x in 0 to ncs-1 generate
csreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => csn(x), q => ddr_csb(x));
ckereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => cke(x), q => ddr_cke(x));
odtreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => odt(x), q => ddr_odt(x));
end generate;
genaddr: for x in 0 to abits-1 generate
addrreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => addr(x), q => ddr_ad(x));
end generate;
-----------------------------------------------------------------------------
-- Outgoing data, output enable, DQS, DQSOEN, DM
-----------------------------------------------------------------------------
gendqout: for x in 0 to dbits-1 generate
dqoutreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqout(x+dbits), d2 => dqout(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dq_out(x));
dqoenreg: grdff
generic map (tech => regtech)
port map (clk => clk0, d => oen, q => ddr_dq_oen(x));
end generate;
-- dqs_en -> invert -> delay -> +90-deg DDR-regs -> dqs_out
-- In total oen is delayed 5/4 cycles. We use 1/2 cycle delay
-- instead of 1 cycle delay to get better timing margin to DDR regs.
-- DQSOEN is delayed one cycle just like ctrl sigs
dqs_en_inv <= not dqs_en;
dqseninv180reg: grdff
generic map (tech => regtech)
port map (clk => clk180, d => dqs_en_inv, q => dqs_en_inv180);
gendqsout: for x in 0 to dbits/8-1 generate
dqsreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqs_en_inv180, d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_dqs_out(x));
dqsoenreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqs_oen, q => ddr_dqs_oen(x));
end generate;
gendm: for x in 0 to dbits/8-1 generate
dmreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dm(x+dbits/8), d2 => dm(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dm(x));
end generate;
-----------------------------------------------------------------------------
-- Incoming data
-----------------------------------------------------------------------------
gendqin: for x in 0 to dbits-1 generate
-- capture using dqs+90
-- Note: The ddr_ireg delivers both edges on c1 rising edge, therefore c1
-- is connected to inverted clock (c1 rising edge == dqs falling edge)
dqcaptreg: ddr_ireg generic map (tech => regtech)
port map (d => ddr_dq_in(x),
c1 => ddr_dqs_in90n(x/8), c2 => ddr_dqs_in90(x/8), ce => vcc, r => gnd, s => gnd,
q1 => dqcaptf(x), q2 => dqcaptr(x));
-- optional extra resync stage
ifresync: if resync=1 generate
genresync: for x in 0 to dbits-1 generate
dqsyncrreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptr(x), q => dqsyncr(x));
dqsyncfreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptf(x), q => dqsyncf(x));
end generate;
end generate;
noresync: if resync/=1 generate
dqsyncr <= dqcaptr;
dqsyncf <= dqcaptf;
end generate;
-- sample in clk0 domain
gensamp: if resync/=2 generate
dqinregr: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncr(x), q => dqin(x+dbits));
dqinregf: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncf(x), q => dqin(x));
end generate;
nosamp: if resync=2 generate
dqin(x+dbits) <= dqsyncr(x);
dqin(x) <= dqsyncf(x);
end generate;
end generate;
end;
|
entity paren6 is
end paren6;
architecture behav of paren6
is
begin
process
type string_acc is access string;
variable a : string_acc := new string'("hello");
constant b : natural := 3;
begin
assert a(b) = 'l';
wait;
end process;
end behav;
|
entity paren6 is
end paren6;
architecture behav of paren6
is
begin
process
type string_acc is access string;
variable a : string_acc := new string'("hello");
constant b : natural := 3;
begin
assert a(b) = 'l';
wait;
end process;
end behav;
|
entity paren6 is
end paren6;
architecture behav of paren6
is
begin
process
type string_acc is access string;
variable a : string_acc := new string'("hello");
constant b : natural := 3;
begin
assert a(b) = 'l';
wait;
end process;
end behav;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ad
--
-- Generated
-- by: wig
-- on: Fri Jul 15 12:55:13 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ad.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: ent_ad.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_ad
--
entity ent_ad is
-- Generics:
-- No Generated Generics for Entity ent_ad
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_ad
port_ad_2 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end ent_ad;
--
-- End of Generated Entity ent_ad
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ad
--
-- Generated
-- by: wig
-- on: Fri Jul 15 12:55:13 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ad.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: ent_ad.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ad
--
architecture rtl of ent_ad is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_ad
--
-- Generated
-- by: wig
-- on: Fri Jul 15 12:55:13 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ad.vhd,v 1.2 2005/07/15 16:20:06 wig Exp $
-- $Date: 2005/07/15 16:20:06 $
-- $Log: ent_ad.vhd,v $
-- Revision 1.2 2005/07/15 16:20:06 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_ad_rtl_config / ent_ad
--
configuration ent_ad_rtl_config of ent_ad is
for rtl
-- Generated Configuration
end for;
end ent_ad_rtl_config;
--
-- End of Generated Configuration ent_ad_rtl_config
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Juan Carlos Angeles Ceron
--
-- Create Date: 19:26:58 19/15/2115
-- Design Name:
-- Module Name: First_term_exam - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 1.11 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity First_term_exam is
Port ( BCDin : in STD_LOGIC_VECTOR (3 downto 0);
DECout : out STD_LOGIC_VECTOR (9 downto 0));
end First_term_exam;
architecture Behavioral of First_term_exam is
begin
with BCDin select
DECout <= "1111111110" when "0000",
"1111111101" when "0001",
"1111111011" when "0010",
"1111110111" when "0011",
"1111101111" when "0100",
"1111011111" when "0101",
"1110111111" when "0110",
"1101111111" when "0111",
"1011111111" when "1000",
"0111111111" when "1001",
"1111111111" when others; -- Invalid BCD
end Behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_08 is
end entity inline_08;
----------------------------------------------------------------
library ieee; use ieee.numeric_bit.all;
architecture test of inline_08 is
begin
process_5_b : process is
-- code from book:
function "+" ( left, right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bit_vector( "+"(signed(left), signed(right)) );
-- end not in book
end function "+";
variable addr_reg : bit_vector(31 downto 0);
-- . . .
-- end of code from book
-- code from book:
function "abs" ( right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
if right(right'left) = '0' then
return right;
else
return bit_vector( "-"(signed(right)) );
end if;
-- end not in book
end function "abs";
variable accumulator : bit_vector(31 downto 0);
-- . . .
-- end of code from book
begin
-- code from book:
addr_reg := addr_reg + X"0000_0004";
-- end of code from book
accumulator := X"000000FF";
-- code from book:
accumulator := abs accumulator;
-- end of code from book
accumulator := X"FFFFFFFE";
accumulator := abs accumulator;
wait;
end process process_5_b;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_08 is
end entity inline_08;
----------------------------------------------------------------
library ieee; use ieee.numeric_bit.all;
architecture test of inline_08 is
begin
process_5_b : process is
-- code from book:
function "+" ( left, right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bit_vector( "+"(signed(left), signed(right)) );
-- end not in book
end function "+";
variable addr_reg : bit_vector(31 downto 0);
-- . . .
-- end of code from book
-- code from book:
function "abs" ( right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
if right(right'left) = '0' then
return right;
else
return bit_vector( "-"(signed(right)) );
end if;
-- end not in book
end function "abs";
variable accumulator : bit_vector(31 downto 0);
-- . . .
-- end of code from book
begin
-- code from book:
addr_reg := addr_reg + X"0000_0004";
-- end of code from book
accumulator := X"000000FF";
-- code from book:
accumulator := abs accumulator;
-- end of code from book
accumulator := X"FFFFFFFE";
accumulator := abs accumulator;
wait;
end process process_5_b;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_08 is
end entity inline_08;
----------------------------------------------------------------
library ieee; use ieee.numeric_bit.all;
architecture test of inline_08 is
begin
process_5_b : process is
-- code from book:
function "+" ( left, right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bit_vector( "+"(signed(left), signed(right)) );
-- end not in book
end function "+";
variable addr_reg : bit_vector(31 downto 0);
-- . . .
-- end of code from book
-- code from book:
function "abs" ( right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
if right(right'left) = '0' then
return right;
else
return bit_vector( "-"(signed(right)) );
end if;
-- end not in book
end function "abs";
variable accumulator : bit_vector(31 downto 0);
-- . . .
-- end of code from book
begin
-- code from book:
addr_reg := addr_reg + X"0000_0004";
-- end of code from book
accumulator := X"000000FF";
-- code from book:
accumulator := abs accumulator;
-- end of code from book
accumulator := X"FFFFFFFE";
accumulator := abs accumulator;
wait;
end process process_5_b;
end architecture test;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY system_microblaze_0_xlconcat_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END system_microblaze_0_xlconcat_0;
ARCHITECTURE system_microblaze_0_xlconcat_0_arch OF system_microblaze_0_xlconcat_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_microblaze_0_xlconcat_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT xlconcat;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_microblaze_0_xlconcat_0_arch: ARCHITECTURE IS "xlconcat,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_microblaze_0_xlconcat_0_arch : ARCHITECTURE IS "system_microblaze_0_xlconcat_0,xlconcat,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_microblaze_0_xlconcat_0_arch: ARCHITECTURE IS "system_microblaze_0_xlconcat_0,xlconcat,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,I" &
"N24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=7,NUM_PORTS=7}";
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 1,
IN1_WIDTH => 1,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 7,
NUM_PORTS => 7
)
PORT MAP (
In0 => In0,
In1 => In1,
In2 => In2,
In3 => In3,
In4 => In4,
In5 => In5,
In6 => In6,
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END system_microblaze_0_xlconcat_0_arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.ffaccel_globals.all;
use work.ffaccel_gcu_opcodes.all;
use work.tce_util.all;
entity ffaccel_decoder is
port (
instructionword : in std_logic_vector(INSTRUCTIONWIDTH-1 downto 0);
pc_load : out std_logic;
ra_load : out std_logic;
pc_opcode : out std_logic_vector(0 downto 0);
lock : in std_logic;
lock_r : out std_logic;
clk : in std_logic;
rstx : in std_logic;
locked : out std_logic;
simm_B1 : out std_logic_vector(31 downto 0);
simm_B1_1 : out std_logic_vector(31 downto 0);
socket_lsu_i1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_lsu_i2_bus_cntrl : out std_logic_vector(0 downto 0);
socket_alu_comp_i1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_alu_comp_i2_bus_cntrl : out std_logic_vector(0 downto 0);
socket_RF_i1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_bool_i1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_gcu_i1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_gcu_i2_bus_cntrl : out std_logic_vector(0 downto 0);
socket_lsu_i1_1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_lsu_i2_1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_lsu_i2_1_1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_lsu_i1_1_1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_lsu_i2_1_1_2_1_bus_cntrl : out std_logic_vector(0 downto 0);
B1_src_sel : out std_logic_vector(3 downto 0);
B1_1_src_sel : out std_logic_vector(3 downto 0);
fu_DATA_LSU_in1t_load : out std_logic;
fu_DATA_LSU_in2_load : out std_logic;
fu_DATA_LSU_opc : out std_logic_vector(2 downto 0);
fu_alu_comp_in1t_load : out std_logic;
fu_alu_comp_in2_load : out std_logic;
fu_alu_comp_opc : out std_logic_vector(3 downto 0);
fu_PARAM_LSU_in1t_load : out std_logic;
fu_PARAM_LSU_in2_load : out std_logic;
fu_PARAM_LSU_opc : out std_logic_vector(2 downto 0);
fu_SP_LSU_in1t_load : out std_logic;
fu_SP_LSU_in2_load : out std_logic;
fu_SP_LSU_opc : out std_logic_vector(2 downto 0);
fu_AQL_FU_t1_in_load : out std_logic;
fu_AQL_FU_opc : out std_logic_vector(0 downto 0);
rf_RF_wr_load : out std_logic;
rf_RF_wr_opc : out std_logic_vector(4 downto 0);
rf_RF_rd_load : out std_logic;
rf_RF_rd_opc : out std_logic_vector(4 downto 0);
rf_bool_wr_load : out std_logic;
rf_bool_wr_opc : out std_logic_vector(0 downto 0);
rf_bool_rd_load : out std_logic;
rf_bool_rd_opc : out std_logic_vector(0 downto 0);
iu_IMM_P1_read_load : out std_logic;
iu_IMM_P1_read_opc : out std_logic_vector(0 downto 0);
iu_IMM_write : out std_logic_vector(31 downto 0);
iu_IMM_write_load : out std_logic;
iu_IMM_write_opc : out std_logic_vector(0 downto 0);
rf_guard_bool_0 : in std_logic;
rf_guard_bool_1 : in std_logic;
lock_req : in std_logic_vector(4 downto 0);
glock : out std_logic_vector(8 downto 0);
db_tta_nreset : in std_logic);
end ffaccel_decoder;
architecture rtl_andor of ffaccel_decoder is
-- signals for source, destination and guard fields
signal move_B1 : std_logic_vector(23 downto 0);
signal src_B1 : std_logic_vector(13 downto 0);
signal dst_B1 : std_logic_vector(6 downto 0);
signal grd_B1 : std_logic_vector(2 downto 0);
signal move_B1_1 : std_logic_vector(17 downto 0);
signal src_B1_1 : std_logic_vector(7 downto 0);
signal dst_B1_1 : std_logic_vector(6 downto 0);
signal grd_B1_1 : std_logic_vector(2 downto 0);
-- signals for dedicated immediate slots
-- signal for long immediate tag
signal limm_tag : std_logic_vector(0 downto 0);
-- squash signals
signal squash_B1 : std_logic;
signal squash_B1_1 : std_logic;
-- socket control signals
signal socket_lsu_i1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_lsu_o1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_lsu_i2_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_alu_comp_i1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_alu_comp_i2_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_alu_comp_o1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_RF_i1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_RF_o1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_bool_i1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_bool_o1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_gcu_i1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_gcu_i2_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_gcu_o1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_lsu_i1_1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_lsu_o1_1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_lsu_i2_1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_RF_o1_1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_lsu_i2_1_1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_lsu_i1_1_1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_lsu_o1_1_1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_alu_comp_o1_1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_lsu_o1_1_1_1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_lsu_i2_1_1_2_1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_lsu_o1_1_1_1_1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal simm_B1_reg : std_logic_vector(31 downto 0);
signal B1_src_sel_reg : std_logic_vector(3 downto 0);
signal simm_B1_1_reg : std_logic_vector(31 downto 0);
signal B1_1_src_sel_reg : std_logic_vector(3 downto 0);
-- FU control signals
signal fu_DATA_LSU_in1t_load_reg : std_logic;
signal fu_DATA_LSU_in2_load_reg : std_logic;
signal fu_DATA_LSU_opc_reg : std_logic_vector(2 downto 0);
signal fu_alu_comp_in1t_load_reg : std_logic;
signal fu_alu_comp_in2_load_reg : std_logic;
signal fu_alu_comp_opc_reg : std_logic_vector(3 downto 0);
signal fu_PARAM_LSU_in1t_load_reg : std_logic;
signal fu_PARAM_LSU_in2_load_reg : std_logic;
signal fu_PARAM_LSU_opc_reg : std_logic_vector(2 downto 0);
signal fu_SP_LSU_in1t_load_reg : std_logic;
signal fu_SP_LSU_in2_load_reg : std_logic;
signal fu_SP_LSU_opc_reg : std_logic_vector(2 downto 0);
signal fu_AQL_FU_t1_in_load_reg : std_logic;
signal fu_AQL_FU_opc_reg : std_logic_vector(0 downto 0);
signal fu_gcu_pc_load_reg : std_logic;
signal fu_gcu_ra_load_reg : std_logic;
signal fu_gcu_opc_reg : std_logic_vector(0 downto 0);
-- RF control signals
signal rf_RF_wr_load_reg : std_logic;
signal rf_RF_wr_opc_reg : std_logic_vector(4 downto 0);
signal rf_RF_rd_load_reg : std_logic;
signal rf_RF_rd_opc_reg : std_logic_vector(4 downto 0);
signal rf_bool_wr_load_reg : std_logic;
signal rf_bool_wr_opc_reg : std_logic_vector(0 downto 0);
signal rf_bool_rd_load_reg : std_logic;
signal rf_bool_rd_opc_reg : std_logic_vector(0 downto 0);
signal merged_glock_req : std_logic;
signal pre_decode_merged_glock : std_logic;
signal post_decode_merged_glock : std_logic;
signal post_decode_merged_glock_r : std_logic;
signal decode_fill_lock_reg : std_logic;
begin
-- dismembering of instruction
process (instructionword)
begin --process
move_B1 <= instructionword(24-1 downto 0);
src_B1 <= instructionword(20 downto 7);
dst_B1 <= instructionword(6 downto 0);
grd_B1 <= instructionword(23 downto 21);
move_B1_1 <= instructionword(42-1 downto 24);
src_B1_1 <= instructionword(38 downto 31);
dst_B1_1 <= instructionword(30 downto 24);
grd_B1_1 <= instructionword(41 downto 39);
limm_tag <= instructionword(42 downto 42);
end process;
-- map control registers to outputs
fu_DATA_LSU_in1t_load <= fu_DATA_LSU_in1t_load_reg;
fu_DATA_LSU_in2_load <= fu_DATA_LSU_in2_load_reg;
fu_DATA_LSU_opc <= fu_DATA_LSU_opc_reg;
fu_alu_comp_in1t_load <= fu_alu_comp_in1t_load_reg;
fu_alu_comp_in2_load <= fu_alu_comp_in2_load_reg;
fu_alu_comp_opc <= fu_alu_comp_opc_reg;
fu_PARAM_LSU_in1t_load <= fu_PARAM_LSU_in1t_load_reg;
fu_PARAM_LSU_in2_load <= fu_PARAM_LSU_in2_load_reg;
fu_PARAM_LSU_opc <= fu_PARAM_LSU_opc_reg;
fu_SP_LSU_in1t_load <= fu_SP_LSU_in1t_load_reg;
fu_SP_LSU_in2_load <= fu_SP_LSU_in2_load_reg;
fu_SP_LSU_opc <= fu_SP_LSU_opc_reg;
fu_AQL_FU_t1_in_load <= fu_AQL_FU_t1_in_load_reg;
fu_AQL_FU_opc <= fu_AQL_FU_opc_reg;
ra_load <= fu_gcu_ra_load_reg;
pc_load <= fu_gcu_pc_load_reg;
pc_opcode <= fu_gcu_opc_reg;
rf_RF_wr_load <= rf_RF_wr_load_reg;
rf_RF_wr_opc <= rf_RF_wr_opc_reg;
rf_RF_rd_load <= rf_RF_rd_load_reg;
rf_RF_rd_opc <= rf_RF_rd_opc_reg;
rf_bool_wr_load <= rf_bool_wr_load_reg;
rf_bool_wr_opc <= rf_bool_wr_opc_reg;
rf_bool_rd_load <= rf_bool_rd_load_reg;
rf_bool_rd_opc <= rf_bool_rd_opc_reg;
iu_IMM_P1_read_opc <= "0";
iu_IMM_write_opc <= "0";
socket_lsu_i1_bus_cntrl <= socket_lsu_i1_bus_cntrl_reg;
socket_lsu_i2_bus_cntrl <= socket_lsu_i2_bus_cntrl_reg;
socket_alu_comp_i1_bus_cntrl <= socket_alu_comp_i1_bus_cntrl_reg;
socket_alu_comp_i2_bus_cntrl <= socket_alu_comp_i2_bus_cntrl_reg;
socket_RF_i1_bus_cntrl <= socket_RF_i1_bus_cntrl_reg;
socket_bool_i1_bus_cntrl <= socket_bool_i1_bus_cntrl_reg;
socket_gcu_i1_bus_cntrl <= socket_gcu_i1_bus_cntrl_reg;
socket_gcu_i2_bus_cntrl <= socket_gcu_i2_bus_cntrl_reg;
socket_lsu_i1_1_bus_cntrl <= socket_lsu_i1_1_bus_cntrl_reg;
socket_lsu_i2_1_bus_cntrl <= socket_lsu_i2_1_bus_cntrl_reg;
socket_lsu_i2_1_1_bus_cntrl <= socket_lsu_i2_1_1_bus_cntrl_reg;
socket_lsu_i1_1_1_bus_cntrl <= socket_lsu_i1_1_1_bus_cntrl_reg;
socket_lsu_i2_1_1_2_1_bus_cntrl <= socket_lsu_i2_1_1_2_1_bus_cntrl_reg;
B1_src_sel <= B1_src_sel_reg;
B1_1_src_sel <= B1_1_src_sel_reg;
simm_B1 <= simm_B1_reg;
simm_B1_1 <= simm_B1_1_reg;
-- generate signal squash_B1
process (grd_B1, move_B1, rf_guard_bool_0, rf_guard_bool_1)
variable sel : integer;
begin --process
-- squash by move NOP encoding
if (conv_integer(unsigned(move_B1(23 downto 21))) = 5) then
squash_B1 <= '1';
else
sel := conv_integer(unsigned(grd_B1));
case sel is
when 1 =>
squash_B1 <= not rf_guard_bool_0;
when 2 =>
squash_B1 <= rf_guard_bool_0;
when 3 =>
squash_B1 <= not rf_guard_bool_1;
when 4 =>
squash_B1 <= rf_guard_bool_1;
when others =>
squash_B1 <= '0';
end case;
end if;
end process;
-- generate signal squash_B1_1
process (grd_B1_1, move_B1_1, rf_guard_bool_0, rf_guard_bool_1)
variable sel : integer;
begin --process
-- squash by move NOP encoding
if (conv_integer(unsigned(move_B1_1(17 downto 15))) = 5) then
squash_B1_1 <= '1';
else
sel := conv_integer(unsigned(grd_B1_1));
case sel is
when 1 =>
squash_B1_1 <= not rf_guard_bool_0;
when 2 =>
squash_B1_1 <= rf_guard_bool_0;
when 3 =>
squash_B1_1 <= not rf_guard_bool_1;
when 4 =>
squash_B1_1 <= rf_guard_bool_1;
when others =>
squash_B1_1 <= '0';
end case;
end if;
end process;
--long immediate write process
process (clk)
begin --process
if (clk'event and clk = '1') then
if (rstx = '0') then
iu_IMM_write_load <= '0';
iu_IMM_write <= (others => '0');
elsif pre_decode_merged_glock = '0' then
if (conv_integer(unsigned(limm_tag)) = 0) then
iu_IMM_write_load <= '0';
iu_IMM_write(31 downto 0) <= tce_sxt("0", 32);
else
iu_IMM_write_load <= '0';
iu_IMM_write(31 downto 0) <= tce_sxt("0", 32);
end if;
end if;
end if;
end process;
-- main decoding process
process (clk)
begin
if (clk'event and clk = '1') then
if (rstx = '0') then
socket_lsu_i1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_bus_cntrl_reg <= (others => '0');
socket_alu_comp_i1_bus_cntrl_reg <= (others => '0');
socket_alu_comp_i2_bus_cntrl_reg <= (others => '0');
socket_alu_comp_o1_bus_cntrl_reg <= (others => '0');
socket_RF_i1_bus_cntrl_reg <= (others => '0');
socket_RF_o1_bus_cntrl_reg <= (others => '0');
socket_bool_i1_bus_cntrl_reg <= (others => '0');
socket_bool_o1_bus_cntrl_reg <= (others => '0');
socket_gcu_i1_bus_cntrl_reg <= (others => '0');
socket_gcu_i2_bus_cntrl_reg <= (others => '0');
socket_gcu_o1_bus_cntrl_reg <= (others => '0');
socket_lsu_i1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_1_bus_cntrl_reg <= (others => '0');
socket_RF_o1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i1_1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_1_bus_cntrl_reg <= (others => '0');
socket_alu_comp_o1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_1_1_2_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_1_1_1_bus_cntrl_reg <= (others => '0');
simm_B1_reg <= (others => '0');
B1_src_sel_reg <= (others => '0');
simm_B1_1_reg <= (others => '0');
B1_1_src_sel_reg <= (others => '0');
fu_DATA_LSU_opc_reg <= (others => '0');
fu_alu_comp_opc_reg <= (others => '0');
fu_PARAM_LSU_opc_reg <= (others => '0');
fu_SP_LSU_opc_reg <= (others => '0');
fu_AQL_FU_opc_reg <= (others => '0');
fu_gcu_opc_reg <= (others => '0');
rf_RF_wr_opc_reg <= (others => '0');
rf_RF_rd_opc_reg <= (others => '0');
rf_bool_wr_opc_reg <= (others => '0');
rf_bool_rd_opc_reg <= (others => '0');
fu_DATA_LSU_in1t_load_reg <= '0';
fu_DATA_LSU_in2_load_reg <= '0';
fu_alu_comp_in1t_load_reg <= '0';
fu_alu_comp_in2_load_reg <= '0';
fu_PARAM_LSU_in1t_load_reg <= '0';
fu_PARAM_LSU_in2_load_reg <= '0';
fu_SP_LSU_in1t_load_reg <= '0';
fu_SP_LSU_in2_load_reg <= '0';
fu_AQL_FU_t1_in_load_reg <= '0';
fu_gcu_pc_load_reg <= '0';
fu_gcu_ra_load_reg <= '0';
rf_RF_wr_load_reg <= '0';
rf_RF_rd_load_reg <= '0';
rf_bool_wr_load_reg <= '0';
rf_bool_rd_load_reg <= '0';
iu_IMM_P1_read_load <= '0';
else
if (db_tta_nreset = '0') then
socket_lsu_i1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_bus_cntrl_reg <= (others => '0');
socket_alu_comp_i1_bus_cntrl_reg <= (others => '0');
socket_alu_comp_i2_bus_cntrl_reg <= (others => '0');
socket_alu_comp_o1_bus_cntrl_reg <= (others => '0');
socket_RF_i1_bus_cntrl_reg <= (others => '0');
socket_RF_o1_bus_cntrl_reg <= (others => '0');
socket_bool_i1_bus_cntrl_reg <= (others => '0');
socket_bool_o1_bus_cntrl_reg <= (others => '0');
socket_gcu_i1_bus_cntrl_reg <= (others => '0');
socket_gcu_i2_bus_cntrl_reg <= (others => '0');
socket_gcu_o1_bus_cntrl_reg <= (others => '0');
socket_lsu_i1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_1_bus_cntrl_reg <= (others => '0');
socket_RF_o1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i1_1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_1_bus_cntrl_reg <= (others => '0');
socket_alu_comp_o1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_1_1_2_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_1_1_1_bus_cntrl_reg <= (others => '0');
simm_B1_reg <= (others => '0');
B1_src_sel_reg <= (others => '0');
simm_B1_1_reg <= (others => '0');
B1_1_src_sel_reg <= (others => '0');
fu_DATA_LSU_opc_reg <= (others => '0');
fu_alu_comp_opc_reg <= (others => '0');
fu_PARAM_LSU_opc_reg <= (others => '0');
fu_SP_LSU_opc_reg <= (others => '0');
fu_AQL_FU_opc_reg <= (others => '0');
fu_gcu_opc_reg <= (others => '0');
rf_RF_wr_opc_reg <= (others => '0');
rf_RF_rd_opc_reg <= (others => '0');
rf_bool_wr_opc_reg <= (others => '0');
rf_bool_rd_opc_reg <= (others => '0');
fu_DATA_LSU_in1t_load_reg <= '0';
fu_DATA_LSU_in2_load_reg <= '0';
fu_alu_comp_in1t_load_reg <= '0';
fu_alu_comp_in2_load_reg <= '0';
fu_PARAM_LSU_in1t_load_reg <= '0';
fu_PARAM_LSU_in2_load_reg <= '0';
fu_SP_LSU_in1t_load_reg <= '0';
fu_SP_LSU_in2_load_reg <= '0';
fu_AQL_FU_t1_in_load_reg <= '0';
fu_gcu_pc_load_reg <= '0';
fu_gcu_ra_load_reg <= '0';
rf_RF_wr_load_reg <= '0';
rf_RF_rd_load_reg <= '0';
rf_bool_wr_load_reg <= '0';
rf_bool_rd_load_reg <= '0';
iu_IMM_P1_read_load <= '0';
elsif (pre_decode_merged_glock = '0') then
-- bus control signals for output mux
if (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 18) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(0, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 19) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(1, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 16) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(2, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 17) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(3, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 20) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(4, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 21) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(5, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 22) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(6, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 23) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(7, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 24) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(8, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 25) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(9, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 26) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(10, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 13))) = 0) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(11, B1_src_sel_reg'length));
end if;
if (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 13))) = 0) then
simm_B1_reg <= tce_sxt(src_B1(12 downto 0), simm_B1_reg'length);
end if;
if (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 21) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(0, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 22) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(1, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 5))) = 4) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(2, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 20) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(3, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 23) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(4, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 24) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(5, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 25) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(6, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 26) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(7, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 27) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(8, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 28) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(9, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 29) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(10, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 7))) = 0) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(11, B1_1_src_sel_reg'length));
end if;
if (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 7))) = 0) then
simm_B1_1_reg <= tce_sxt(src_B1_1(6 downto 0), simm_B1_1_reg'length);
end if;
-- data control signals for output sockets connected to FUs
-- control signals for RF read ports
if (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 16 and true) then
rf_RF_rd_load_reg <= '1';
rf_RF_rd_opc_reg <= tce_ext(src_B1(4 downto 0), rf_RF_rd_opc_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 5))) = 4 and true) then
rf_RF_rd_load_reg <= '1';
rf_RF_rd_opc_reg <= tce_ext(src_B1_1(4 downto 0), rf_RF_rd_opc_reg'length);
else
rf_RF_rd_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 17 and true) then
rf_bool_rd_load_reg <= '1';
rf_bool_rd_opc_reg <= tce_ext(src_B1(0 downto 0), rf_bool_rd_opc_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 20 and true) then
rf_bool_rd_load_reg <= '1';
rf_bool_rd_opc_reg <= tce_ext(src_B1_1(0 downto 0), rf_bool_rd_opc_reg'length);
else
rf_bool_rd_load_reg <= '0';
end if;
--control signals for IU read ports
-- control signals for IU read ports
if (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 22) then
iu_IMM_P1_read_load <= '1';
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 25) then
iu_IMM_P1_read_load <= '1';
else
iu_IMM_P1_read_load <= '0';
end if;
-- control signals for FU inputs
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 3))) = 6) then
fu_DATA_LSU_in1t_load_reg <= '1';
fu_DATA_LSU_opc_reg <= dst_B1(2 downto 0);
socket_lsu_i1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 3))) = 6) then
fu_DATA_LSU_in1t_load_reg <= '1';
fu_DATA_LSU_opc_reg <= dst_B1_1(2 downto 0);
socket_lsu_i1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i1_bus_cntrl_reg'length);
else
fu_DATA_LSU_in1t_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 39) then
fu_DATA_LSU_in2_load_reg <= '1';
socket_lsu_i2_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i2_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 39) then
fu_DATA_LSU_in2_load_reg <= '1';
socket_lsu_i2_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i2_bus_cntrl_reg'length);
else
fu_DATA_LSU_in2_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 4))) = 2) then
fu_alu_comp_in1t_load_reg <= '1';
fu_alu_comp_opc_reg <= dst_B1(3 downto 0);
socket_alu_comp_i1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_alu_comp_i1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 4))) = 2) then
fu_alu_comp_in1t_load_reg <= '1';
fu_alu_comp_opc_reg <= dst_B1_1(3 downto 0);
socket_alu_comp_i1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_alu_comp_i1_bus_cntrl_reg'length);
else
fu_alu_comp_in1t_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 40) then
fu_alu_comp_in2_load_reg <= '1';
socket_alu_comp_i2_bus_cntrl_reg <= conv_std_logic_vector(0, socket_alu_comp_i2_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 40) then
fu_alu_comp_in2_load_reg <= '1';
socket_alu_comp_i2_bus_cntrl_reg <= conv_std_logic_vector(1, socket_alu_comp_i2_bus_cntrl_reg'length);
else
fu_alu_comp_in2_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 3))) = 7) then
fu_PARAM_LSU_in1t_load_reg <= '1';
fu_PARAM_LSU_opc_reg <= dst_B1(2 downto 0);
socket_lsu_i1_1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i1_1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 3))) = 7) then
fu_PARAM_LSU_in1t_load_reg <= '1';
fu_PARAM_LSU_opc_reg <= dst_B1_1(2 downto 0);
socket_lsu_i1_1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i1_1_bus_cntrl_reg'length);
else
fu_PARAM_LSU_in1t_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 42) then
fu_PARAM_LSU_in2_load_reg <= '1';
socket_lsu_i2_1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i2_1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 42) then
fu_PARAM_LSU_in2_load_reg <= '1';
socket_lsu_i2_1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i2_1_bus_cntrl_reg'length);
else
fu_PARAM_LSU_in2_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 3))) = 8) then
fu_SP_LSU_in1t_load_reg <= '1';
fu_SP_LSU_opc_reg <= dst_B1(2 downto 0);
socket_lsu_i2_1_1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i2_1_1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 3))) = 8) then
fu_SP_LSU_in1t_load_reg <= '1';
fu_SP_LSU_opc_reg <= dst_B1_1(2 downto 0);
socket_lsu_i2_1_1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i2_1_1_bus_cntrl_reg'length);
else
fu_SP_LSU_in1t_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 43) then
fu_SP_LSU_in2_load_reg <= '1';
socket_lsu_i1_1_1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i1_1_1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 43) then
fu_SP_LSU_in2_load_reg <= '1';
socket_lsu_i1_1_1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i1_1_1_bus_cntrl_reg'length);
else
fu_SP_LSU_in2_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 38) then
fu_AQL_FU_t1_in_load_reg <= '1';
fu_AQL_FU_opc_reg <= dst_B1(0 downto 0);
socket_lsu_i2_1_1_2_1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i2_1_1_2_1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 38) then
fu_AQL_FU_t1_in_load_reg <= '1';
fu_AQL_FU_opc_reg <= dst_B1_1(0 downto 0);
socket_lsu_i2_1_1_2_1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i2_1_1_2_1_bus_cntrl_reg'length);
else
fu_AQL_FU_t1_in_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 37) then
fu_gcu_pc_load_reg <= '1';
fu_gcu_opc_reg <= dst_B1(0 downto 0);
socket_gcu_i1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_gcu_i1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 37) then
fu_gcu_pc_load_reg <= '1';
fu_gcu_opc_reg <= dst_B1_1(0 downto 0);
socket_gcu_i1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_gcu_i1_bus_cntrl_reg'length);
else
fu_gcu_pc_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 41) then
fu_gcu_ra_load_reg <= '1';
socket_gcu_i2_bus_cntrl_reg <= conv_std_logic_vector(0, socket_gcu_i2_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 41) then
fu_gcu_ra_load_reg <= '1';
socket_gcu_i2_bus_cntrl_reg <= conv_std_logic_vector(1, socket_gcu_i2_bus_cntrl_reg'length);
else
fu_gcu_ra_load_reg <= '0';
end if;
-- control signals for RF inputs
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 5))) = 0 and true) then
rf_RF_wr_load_reg <= '1';
rf_RF_wr_opc_reg <= dst_B1(4 downto 0);
socket_RF_i1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_RF_i1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 5))) = 0 and true) then
rf_RF_wr_load_reg <= '1';
rf_RF_wr_opc_reg <= dst_B1_1(4 downto 0);
socket_RF_i1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_RF_i1_bus_cntrl_reg'length);
else
rf_RF_wr_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 36 and true) then
rf_bool_wr_load_reg <= '1';
rf_bool_wr_opc_reg <= dst_B1(0 downto 0);
socket_bool_i1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_bool_i1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 36 and true) then
rf_bool_wr_load_reg <= '1';
rf_bool_wr_opc_reg <= dst_B1_1(0 downto 0);
socket_bool_i1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_bool_i1_bus_cntrl_reg'length);
else
rf_bool_wr_load_reg <= '0';
end if;
end if;
end if;
end if;
end process;
lock_reg_proc : process (clk)
begin
if (clk'event and clk = '1') then
if (rstx = '0') then
-- Locked during active reset post_decode_merged_glock_r <= '1';
else
post_decode_merged_glock_r <= post_decode_merged_glock;
end if;
end if;
end process lock_reg_proc;
lock_r <= merged_glock_req;
merged_glock_req <= lock_req(0) or lock_req(1) or lock_req(2) or lock_req(3) or lock_req(4);
pre_decode_merged_glock <= lock or merged_glock_req;
post_decode_merged_glock <= pre_decode_merged_glock or decode_fill_lock_reg;
locked <= post_decode_merged_glock_r;
glock(0) <= post_decode_merged_glock; -- to DATA_LSU
glock(1) <= post_decode_merged_glock; -- to alu_comp
glock(2) <= post_decode_merged_glock; -- to PARAM_LSU
glock(3) <= post_decode_merged_glock; -- to SP_LSU
glock(4) <= post_decode_merged_glock; -- to AQL_FU
glock(5) <= post_decode_merged_glock; -- to RF
glock(6) <= post_decode_merged_glock; -- to bool
glock(7) <= post_decode_merged_glock; -- to IMM
glock(8) <= post_decode_merged_glock;
decode_pipeline_fill_lock: process (clk)
begin
if clk'event and clk = '1' then
if rstx = '0' then
decode_fill_lock_reg <= '1';
elsif lock = '0' then
decode_fill_lock_reg <= '0';
end if;
end if;
end process decode_pipeline_fill_lock;
end rtl_andor;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.ffaccel_globals.all;
use work.ffaccel_gcu_opcodes.all;
use work.tce_util.all;
entity ffaccel_decoder is
port (
instructionword : in std_logic_vector(INSTRUCTIONWIDTH-1 downto 0);
pc_load : out std_logic;
ra_load : out std_logic;
pc_opcode : out std_logic_vector(0 downto 0);
lock : in std_logic;
lock_r : out std_logic;
clk : in std_logic;
rstx : in std_logic;
locked : out std_logic;
simm_B1 : out std_logic_vector(31 downto 0);
simm_B1_1 : out std_logic_vector(31 downto 0);
socket_lsu_i1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_lsu_i2_bus_cntrl : out std_logic_vector(0 downto 0);
socket_alu_comp_i1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_alu_comp_i2_bus_cntrl : out std_logic_vector(0 downto 0);
socket_RF_i1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_bool_i1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_gcu_i1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_gcu_i2_bus_cntrl : out std_logic_vector(0 downto 0);
socket_lsu_i1_1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_lsu_i2_1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_lsu_i2_1_1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_lsu_i1_1_1_bus_cntrl : out std_logic_vector(0 downto 0);
socket_lsu_i2_1_1_2_1_bus_cntrl : out std_logic_vector(0 downto 0);
B1_src_sel : out std_logic_vector(3 downto 0);
B1_1_src_sel : out std_logic_vector(3 downto 0);
fu_DATA_LSU_in1t_load : out std_logic;
fu_DATA_LSU_in2_load : out std_logic;
fu_DATA_LSU_opc : out std_logic_vector(2 downto 0);
fu_alu_comp_in1t_load : out std_logic;
fu_alu_comp_in2_load : out std_logic;
fu_alu_comp_opc : out std_logic_vector(3 downto 0);
fu_PARAM_LSU_in1t_load : out std_logic;
fu_PARAM_LSU_in2_load : out std_logic;
fu_PARAM_LSU_opc : out std_logic_vector(2 downto 0);
fu_SP_LSU_in1t_load : out std_logic;
fu_SP_LSU_in2_load : out std_logic;
fu_SP_LSU_opc : out std_logic_vector(2 downto 0);
fu_AQL_FU_t1_in_load : out std_logic;
fu_AQL_FU_opc : out std_logic_vector(0 downto 0);
rf_RF_wr_load : out std_logic;
rf_RF_wr_opc : out std_logic_vector(4 downto 0);
rf_RF_rd_load : out std_logic;
rf_RF_rd_opc : out std_logic_vector(4 downto 0);
rf_bool_wr_load : out std_logic;
rf_bool_wr_opc : out std_logic_vector(0 downto 0);
rf_bool_rd_load : out std_logic;
rf_bool_rd_opc : out std_logic_vector(0 downto 0);
iu_IMM_P1_read_load : out std_logic;
iu_IMM_P1_read_opc : out std_logic_vector(0 downto 0);
iu_IMM_write : out std_logic_vector(31 downto 0);
iu_IMM_write_load : out std_logic;
iu_IMM_write_opc : out std_logic_vector(0 downto 0);
rf_guard_bool_0 : in std_logic;
rf_guard_bool_1 : in std_logic;
lock_req : in std_logic_vector(4 downto 0);
glock : out std_logic_vector(8 downto 0);
db_tta_nreset : in std_logic);
end ffaccel_decoder;
architecture rtl_andor of ffaccel_decoder is
-- signals for source, destination and guard fields
signal move_B1 : std_logic_vector(23 downto 0);
signal src_B1 : std_logic_vector(13 downto 0);
signal dst_B1 : std_logic_vector(6 downto 0);
signal grd_B1 : std_logic_vector(2 downto 0);
signal move_B1_1 : std_logic_vector(17 downto 0);
signal src_B1_1 : std_logic_vector(7 downto 0);
signal dst_B1_1 : std_logic_vector(6 downto 0);
signal grd_B1_1 : std_logic_vector(2 downto 0);
-- signals for dedicated immediate slots
-- signal for long immediate tag
signal limm_tag : std_logic_vector(0 downto 0);
-- squash signals
signal squash_B1 : std_logic;
signal squash_B1_1 : std_logic;
-- socket control signals
signal socket_lsu_i1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_lsu_o1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_lsu_i2_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_alu_comp_i1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_alu_comp_i2_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_alu_comp_o1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_RF_i1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_RF_o1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_bool_i1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_bool_o1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_gcu_i1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_gcu_i2_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_gcu_o1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_lsu_i1_1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_lsu_o1_1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_lsu_i2_1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_RF_o1_1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_lsu_i2_1_1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_lsu_i1_1_1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_lsu_o1_1_1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_alu_comp_o1_1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_lsu_o1_1_1_1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal socket_lsu_i2_1_1_2_1_bus_cntrl_reg : std_logic_vector(0 downto 0);
signal socket_lsu_o1_1_1_1_1_bus_cntrl_reg : std_logic_vector(1 downto 0);
signal simm_B1_reg : std_logic_vector(31 downto 0);
signal B1_src_sel_reg : std_logic_vector(3 downto 0);
signal simm_B1_1_reg : std_logic_vector(31 downto 0);
signal B1_1_src_sel_reg : std_logic_vector(3 downto 0);
-- FU control signals
signal fu_DATA_LSU_in1t_load_reg : std_logic;
signal fu_DATA_LSU_in2_load_reg : std_logic;
signal fu_DATA_LSU_opc_reg : std_logic_vector(2 downto 0);
signal fu_alu_comp_in1t_load_reg : std_logic;
signal fu_alu_comp_in2_load_reg : std_logic;
signal fu_alu_comp_opc_reg : std_logic_vector(3 downto 0);
signal fu_PARAM_LSU_in1t_load_reg : std_logic;
signal fu_PARAM_LSU_in2_load_reg : std_logic;
signal fu_PARAM_LSU_opc_reg : std_logic_vector(2 downto 0);
signal fu_SP_LSU_in1t_load_reg : std_logic;
signal fu_SP_LSU_in2_load_reg : std_logic;
signal fu_SP_LSU_opc_reg : std_logic_vector(2 downto 0);
signal fu_AQL_FU_t1_in_load_reg : std_logic;
signal fu_AQL_FU_opc_reg : std_logic_vector(0 downto 0);
signal fu_gcu_pc_load_reg : std_logic;
signal fu_gcu_ra_load_reg : std_logic;
signal fu_gcu_opc_reg : std_logic_vector(0 downto 0);
-- RF control signals
signal rf_RF_wr_load_reg : std_logic;
signal rf_RF_wr_opc_reg : std_logic_vector(4 downto 0);
signal rf_RF_rd_load_reg : std_logic;
signal rf_RF_rd_opc_reg : std_logic_vector(4 downto 0);
signal rf_bool_wr_load_reg : std_logic;
signal rf_bool_wr_opc_reg : std_logic_vector(0 downto 0);
signal rf_bool_rd_load_reg : std_logic;
signal rf_bool_rd_opc_reg : std_logic_vector(0 downto 0);
signal merged_glock_req : std_logic;
signal pre_decode_merged_glock : std_logic;
signal post_decode_merged_glock : std_logic;
signal post_decode_merged_glock_r : std_logic;
signal decode_fill_lock_reg : std_logic;
begin
-- dismembering of instruction
process (instructionword)
begin --process
move_B1 <= instructionword(24-1 downto 0);
src_B1 <= instructionword(20 downto 7);
dst_B1 <= instructionword(6 downto 0);
grd_B1 <= instructionword(23 downto 21);
move_B1_1 <= instructionword(42-1 downto 24);
src_B1_1 <= instructionword(38 downto 31);
dst_B1_1 <= instructionword(30 downto 24);
grd_B1_1 <= instructionword(41 downto 39);
limm_tag <= instructionword(42 downto 42);
end process;
-- map control registers to outputs
fu_DATA_LSU_in1t_load <= fu_DATA_LSU_in1t_load_reg;
fu_DATA_LSU_in2_load <= fu_DATA_LSU_in2_load_reg;
fu_DATA_LSU_opc <= fu_DATA_LSU_opc_reg;
fu_alu_comp_in1t_load <= fu_alu_comp_in1t_load_reg;
fu_alu_comp_in2_load <= fu_alu_comp_in2_load_reg;
fu_alu_comp_opc <= fu_alu_comp_opc_reg;
fu_PARAM_LSU_in1t_load <= fu_PARAM_LSU_in1t_load_reg;
fu_PARAM_LSU_in2_load <= fu_PARAM_LSU_in2_load_reg;
fu_PARAM_LSU_opc <= fu_PARAM_LSU_opc_reg;
fu_SP_LSU_in1t_load <= fu_SP_LSU_in1t_load_reg;
fu_SP_LSU_in2_load <= fu_SP_LSU_in2_load_reg;
fu_SP_LSU_opc <= fu_SP_LSU_opc_reg;
fu_AQL_FU_t1_in_load <= fu_AQL_FU_t1_in_load_reg;
fu_AQL_FU_opc <= fu_AQL_FU_opc_reg;
ra_load <= fu_gcu_ra_load_reg;
pc_load <= fu_gcu_pc_load_reg;
pc_opcode <= fu_gcu_opc_reg;
rf_RF_wr_load <= rf_RF_wr_load_reg;
rf_RF_wr_opc <= rf_RF_wr_opc_reg;
rf_RF_rd_load <= rf_RF_rd_load_reg;
rf_RF_rd_opc <= rf_RF_rd_opc_reg;
rf_bool_wr_load <= rf_bool_wr_load_reg;
rf_bool_wr_opc <= rf_bool_wr_opc_reg;
rf_bool_rd_load <= rf_bool_rd_load_reg;
rf_bool_rd_opc <= rf_bool_rd_opc_reg;
iu_IMM_P1_read_opc <= "0";
iu_IMM_write_opc <= "0";
socket_lsu_i1_bus_cntrl <= socket_lsu_i1_bus_cntrl_reg;
socket_lsu_i2_bus_cntrl <= socket_lsu_i2_bus_cntrl_reg;
socket_alu_comp_i1_bus_cntrl <= socket_alu_comp_i1_bus_cntrl_reg;
socket_alu_comp_i2_bus_cntrl <= socket_alu_comp_i2_bus_cntrl_reg;
socket_RF_i1_bus_cntrl <= socket_RF_i1_bus_cntrl_reg;
socket_bool_i1_bus_cntrl <= socket_bool_i1_bus_cntrl_reg;
socket_gcu_i1_bus_cntrl <= socket_gcu_i1_bus_cntrl_reg;
socket_gcu_i2_bus_cntrl <= socket_gcu_i2_bus_cntrl_reg;
socket_lsu_i1_1_bus_cntrl <= socket_lsu_i1_1_bus_cntrl_reg;
socket_lsu_i2_1_bus_cntrl <= socket_lsu_i2_1_bus_cntrl_reg;
socket_lsu_i2_1_1_bus_cntrl <= socket_lsu_i2_1_1_bus_cntrl_reg;
socket_lsu_i1_1_1_bus_cntrl <= socket_lsu_i1_1_1_bus_cntrl_reg;
socket_lsu_i2_1_1_2_1_bus_cntrl <= socket_lsu_i2_1_1_2_1_bus_cntrl_reg;
B1_src_sel <= B1_src_sel_reg;
B1_1_src_sel <= B1_1_src_sel_reg;
simm_B1 <= simm_B1_reg;
simm_B1_1 <= simm_B1_1_reg;
-- generate signal squash_B1
process (grd_B1, move_B1, rf_guard_bool_0, rf_guard_bool_1)
variable sel : integer;
begin --process
-- squash by move NOP encoding
if (conv_integer(unsigned(move_B1(23 downto 21))) = 5) then
squash_B1 <= '1';
else
sel := conv_integer(unsigned(grd_B1));
case sel is
when 1 =>
squash_B1 <= not rf_guard_bool_0;
when 2 =>
squash_B1 <= rf_guard_bool_0;
when 3 =>
squash_B1 <= not rf_guard_bool_1;
when 4 =>
squash_B1 <= rf_guard_bool_1;
when others =>
squash_B1 <= '0';
end case;
end if;
end process;
-- generate signal squash_B1_1
process (grd_B1_1, move_B1_1, rf_guard_bool_0, rf_guard_bool_1)
variable sel : integer;
begin --process
-- squash by move NOP encoding
if (conv_integer(unsigned(move_B1_1(17 downto 15))) = 5) then
squash_B1_1 <= '1';
else
sel := conv_integer(unsigned(grd_B1_1));
case sel is
when 1 =>
squash_B1_1 <= not rf_guard_bool_0;
when 2 =>
squash_B1_1 <= rf_guard_bool_0;
when 3 =>
squash_B1_1 <= not rf_guard_bool_1;
when 4 =>
squash_B1_1 <= rf_guard_bool_1;
when others =>
squash_B1_1 <= '0';
end case;
end if;
end process;
--long immediate write process
process (clk)
begin --process
if (clk'event and clk = '1') then
if (rstx = '0') then
iu_IMM_write_load <= '0';
iu_IMM_write <= (others => '0');
elsif pre_decode_merged_glock = '0' then
if (conv_integer(unsigned(limm_tag)) = 0) then
iu_IMM_write_load <= '0';
iu_IMM_write(31 downto 0) <= tce_sxt("0", 32);
else
iu_IMM_write_load <= '0';
iu_IMM_write(31 downto 0) <= tce_sxt("0", 32);
end if;
end if;
end if;
end process;
-- main decoding process
process (clk)
begin
if (clk'event and clk = '1') then
if (rstx = '0') then
socket_lsu_i1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_bus_cntrl_reg <= (others => '0');
socket_alu_comp_i1_bus_cntrl_reg <= (others => '0');
socket_alu_comp_i2_bus_cntrl_reg <= (others => '0');
socket_alu_comp_o1_bus_cntrl_reg <= (others => '0');
socket_RF_i1_bus_cntrl_reg <= (others => '0');
socket_RF_o1_bus_cntrl_reg <= (others => '0');
socket_bool_i1_bus_cntrl_reg <= (others => '0');
socket_bool_o1_bus_cntrl_reg <= (others => '0');
socket_gcu_i1_bus_cntrl_reg <= (others => '0');
socket_gcu_i2_bus_cntrl_reg <= (others => '0');
socket_gcu_o1_bus_cntrl_reg <= (others => '0');
socket_lsu_i1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_1_bus_cntrl_reg <= (others => '0');
socket_RF_o1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i1_1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_1_bus_cntrl_reg <= (others => '0');
socket_alu_comp_o1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_1_1_2_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_1_1_1_bus_cntrl_reg <= (others => '0');
simm_B1_reg <= (others => '0');
B1_src_sel_reg <= (others => '0');
simm_B1_1_reg <= (others => '0');
B1_1_src_sel_reg <= (others => '0');
fu_DATA_LSU_opc_reg <= (others => '0');
fu_alu_comp_opc_reg <= (others => '0');
fu_PARAM_LSU_opc_reg <= (others => '0');
fu_SP_LSU_opc_reg <= (others => '0');
fu_AQL_FU_opc_reg <= (others => '0');
fu_gcu_opc_reg <= (others => '0');
rf_RF_wr_opc_reg <= (others => '0');
rf_RF_rd_opc_reg <= (others => '0');
rf_bool_wr_opc_reg <= (others => '0');
rf_bool_rd_opc_reg <= (others => '0');
fu_DATA_LSU_in1t_load_reg <= '0';
fu_DATA_LSU_in2_load_reg <= '0';
fu_alu_comp_in1t_load_reg <= '0';
fu_alu_comp_in2_load_reg <= '0';
fu_PARAM_LSU_in1t_load_reg <= '0';
fu_PARAM_LSU_in2_load_reg <= '0';
fu_SP_LSU_in1t_load_reg <= '0';
fu_SP_LSU_in2_load_reg <= '0';
fu_AQL_FU_t1_in_load_reg <= '0';
fu_gcu_pc_load_reg <= '0';
fu_gcu_ra_load_reg <= '0';
rf_RF_wr_load_reg <= '0';
rf_RF_rd_load_reg <= '0';
rf_bool_wr_load_reg <= '0';
rf_bool_rd_load_reg <= '0';
iu_IMM_P1_read_load <= '0';
else
if (db_tta_nreset = '0') then
socket_lsu_i1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_bus_cntrl_reg <= (others => '0');
socket_alu_comp_i1_bus_cntrl_reg <= (others => '0');
socket_alu_comp_i2_bus_cntrl_reg <= (others => '0');
socket_alu_comp_o1_bus_cntrl_reg <= (others => '0');
socket_RF_i1_bus_cntrl_reg <= (others => '0');
socket_RF_o1_bus_cntrl_reg <= (others => '0');
socket_bool_i1_bus_cntrl_reg <= (others => '0');
socket_bool_o1_bus_cntrl_reg <= (others => '0');
socket_gcu_i1_bus_cntrl_reg <= (others => '0');
socket_gcu_i2_bus_cntrl_reg <= (others => '0');
socket_gcu_o1_bus_cntrl_reg <= (others => '0');
socket_lsu_i1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_1_bus_cntrl_reg <= (others => '0');
socket_RF_o1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i1_1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_1_bus_cntrl_reg <= (others => '0');
socket_alu_comp_o1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_1_1_bus_cntrl_reg <= (others => '0');
socket_lsu_i2_1_1_2_1_bus_cntrl_reg <= (others => '0');
socket_lsu_o1_1_1_1_1_bus_cntrl_reg <= (others => '0');
simm_B1_reg <= (others => '0');
B1_src_sel_reg <= (others => '0');
simm_B1_1_reg <= (others => '0');
B1_1_src_sel_reg <= (others => '0');
fu_DATA_LSU_opc_reg <= (others => '0');
fu_alu_comp_opc_reg <= (others => '0');
fu_PARAM_LSU_opc_reg <= (others => '0');
fu_SP_LSU_opc_reg <= (others => '0');
fu_AQL_FU_opc_reg <= (others => '0');
fu_gcu_opc_reg <= (others => '0');
rf_RF_wr_opc_reg <= (others => '0');
rf_RF_rd_opc_reg <= (others => '0');
rf_bool_wr_opc_reg <= (others => '0');
rf_bool_rd_opc_reg <= (others => '0');
fu_DATA_LSU_in1t_load_reg <= '0';
fu_DATA_LSU_in2_load_reg <= '0';
fu_alu_comp_in1t_load_reg <= '0';
fu_alu_comp_in2_load_reg <= '0';
fu_PARAM_LSU_in1t_load_reg <= '0';
fu_PARAM_LSU_in2_load_reg <= '0';
fu_SP_LSU_in1t_load_reg <= '0';
fu_SP_LSU_in2_load_reg <= '0';
fu_AQL_FU_t1_in_load_reg <= '0';
fu_gcu_pc_load_reg <= '0';
fu_gcu_ra_load_reg <= '0';
rf_RF_wr_load_reg <= '0';
rf_RF_rd_load_reg <= '0';
rf_bool_wr_load_reg <= '0';
rf_bool_rd_load_reg <= '0';
iu_IMM_P1_read_load <= '0';
elsif (pre_decode_merged_glock = '0') then
-- bus control signals for output mux
if (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 18) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(0, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 19) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(1, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 16) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(2, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 17) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(3, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 20) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(4, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 21) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(5, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 22) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(6, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 23) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(7, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 24) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(8, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 25) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(9, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 26) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(10, B1_src_sel_reg'length));
elsif (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 13))) = 0) then
B1_src_sel_reg <= std_logic_vector(conv_unsigned(11, B1_src_sel_reg'length));
end if;
if (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 13))) = 0) then
simm_B1_reg <= tce_sxt(src_B1(12 downto 0), simm_B1_reg'length);
end if;
if (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 21) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(0, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 22) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(1, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 5))) = 4) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(2, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 20) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(3, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 23) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(4, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 24) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(5, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 25) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(6, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 26) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(7, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 27) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(8, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 28) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(9, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 29) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(10, B1_1_src_sel_reg'length));
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 7))) = 0) then
B1_1_src_sel_reg <= std_logic_vector(conv_unsigned(11, B1_1_src_sel_reg'length));
end if;
if (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 7))) = 0) then
simm_B1_1_reg <= tce_sxt(src_B1_1(6 downto 0), simm_B1_1_reg'length);
end if;
-- data control signals for output sockets connected to FUs
-- control signals for RF read ports
if (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 16 and true) then
rf_RF_rd_load_reg <= '1';
rf_RF_rd_opc_reg <= tce_ext(src_B1(4 downto 0), rf_RF_rd_opc_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 5))) = 4 and true) then
rf_RF_rd_load_reg <= '1';
rf_RF_rd_opc_reg <= tce_ext(src_B1_1(4 downto 0), rf_RF_rd_opc_reg'length);
else
rf_RF_rd_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 17 and true) then
rf_bool_rd_load_reg <= '1';
rf_bool_rd_opc_reg <= tce_ext(src_B1(0 downto 0), rf_bool_rd_opc_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 20 and true) then
rf_bool_rd_load_reg <= '1';
rf_bool_rd_opc_reg <= tce_ext(src_B1_1(0 downto 0), rf_bool_rd_opc_reg'length);
else
rf_bool_rd_load_reg <= '0';
end if;
--control signals for IU read ports
-- control signals for IU read ports
if (squash_B1 = '0' and conv_integer(unsigned(src_B1(13 downto 9))) = 22) then
iu_IMM_P1_read_load <= '1';
elsif (squash_B1_1 = '0' and conv_integer(unsigned(src_B1_1(7 downto 3))) = 25) then
iu_IMM_P1_read_load <= '1';
else
iu_IMM_P1_read_load <= '0';
end if;
-- control signals for FU inputs
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 3))) = 6) then
fu_DATA_LSU_in1t_load_reg <= '1';
fu_DATA_LSU_opc_reg <= dst_B1(2 downto 0);
socket_lsu_i1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 3))) = 6) then
fu_DATA_LSU_in1t_load_reg <= '1';
fu_DATA_LSU_opc_reg <= dst_B1_1(2 downto 0);
socket_lsu_i1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i1_bus_cntrl_reg'length);
else
fu_DATA_LSU_in1t_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 39) then
fu_DATA_LSU_in2_load_reg <= '1';
socket_lsu_i2_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i2_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 39) then
fu_DATA_LSU_in2_load_reg <= '1';
socket_lsu_i2_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i2_bus_cntrl_reg'length);
else
fu_DATA_LSU_in2_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 4))) = 2) then
fu_alu_comp_in1t_load_reg <= '1';
fu_alu_comp_opc_reg <= dst_B1(3 downto 0);
socket_alu_comp_i1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_alu_comp_i1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 4))) = 2) then
fu_alu_comp_in1t_load_reg <= '1';
fu_alu_comp_opc_reg <= dst_B1_1(3 downto 0);
socket_alu_comp_i1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_alu_comp_i1_bus_cntrl_reg'length);
else
fu_alu_comp_in1t_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 40) then
fu_alu_comp_in2_load_reg <= '1';
socket_alu_comp_i2_bus_cntrl_reg <= conv_std_logic_vector(0, socket_alu_comp_i2_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 40) then
fu_alu_comp_in2_load_reg <= '1';
socket_alu_comp_i2_bus_cntrl_reg <= conv_std_logic_vector(1, socket_alu_comp_i2_bus_cntrl_reg'length);
else
fu_alu_comp_in2_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 3))) = 7) then
fu_PARAM_LSU_in1t_load_reg <= '1';
fu_PARAM_LSU_opc_reg <= dst_B1(2 downto 0);
socket_lsu_i1_1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i1_1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 3))) = 7) then
fu_PARAM_LSU_in1t_load_reg <= '1';
fu_PARAM_LSU_opc_reg <= dst_B1_1(2 downto 0);
socket_lsu_i1_1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i1_1_bus_cntrl_reg'length);
else
fu_PARAM_LSU_in1t_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 42) then
fu_PARAM_LSU_in2_load_reg <= '1';
socket_lsu_i2_1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i2_1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 42) then
fu_PARAM_LSU_in2_load_reg <= '1';
socket_lsu_i2_1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i2_1_bus_cntrl_reg'length);
else
fu_PARAM_LSU_in2_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 3))) = 8) then
fu_SP_LSU_in1t_load_reg <= '1';
fu_SP_LSU_opc_reg <= dst_B1(2 downto 0);
socket_lsu_i2_1_1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i2_1_1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 3))) = 8) then
fu_SP_LSU_in1t_load_reg <= '1';
fu_SP_LSU_opc_reg <= dst_B1_1(2 downto 0);
socket_lsu_i2_1_1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i2_1_1_bus_cntrl_reg'length);
else
fu_SP_LSU_in1t_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 43) then
fu_SP_LSU_in2_load_reg <= '1';
socket_lsu_i1_1_1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i1_1_1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 43) then
fu_SP_LSU_in2_load_reg <= '1';
socket_lsu_i1_1_1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i1_1_1_bus_cntrl_reg'length);
else
fu_SP_LSU_in2_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 38) then
fu_AQL_FU_t1_in_load_reg <= '1';
fu_AQL_FU_opc_reg <= dst_B1(0 downto 0);
socket_lsu_i2_1_1_2_1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_lsu_i2_1_1_2_1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 38) then
fu_AQL_FU_t1_in_load_reg <= '1';
fu_AQL_FU_opc_reg <= dst_B1_1(0 downto 0);
socket_lsu_i2_1_1_2_1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_lsu_i2_1_1_2_1_bus_cntrl_reg'length);
else
fu_AQL_FU_t1_in_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 37) then
fu_gcu_pc_load_reg <= '1';
fu_gcu_opc_reg <= dst_B1(0 downto 0);
socket_gcu_i1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_gcu_i1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 37) then
fu_gcu_pc_load_reg <= '1';
fu_gcu_opc_reg <= dst_B1_1(0 downto 0);
socket_gcu_i1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_gcu_i1_bus_cntrl_reg'length);
else
fu_gcu_pc_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 41) then
fu_gcu_ra_load_reg <= '1';
socket_gcu_i2_bus_cntrl_reg <= conv_std_logic_vector(0, socket_gcu_i2_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 41) then
fu_gcu_ra_load_reg <= '1';
socket_gcu_i2_bus_cntrl_reg <= conv_std_logic_vector(1, socket_gcu_i2_bus_cntrl_reg'length);
else
fu_gcu_ra_load_reg <= '0';
end if;
-- control signals for RF inputs
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 5))) = 0 and true) then
rf_RF_wr_load_reg <= '1';
rf_RF_wr_opc_reg <= dst_B1(4 downto 0);
socket_RF_i1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_RF_i1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 5))) = 0 and true) then
rf_RF_wr_load_reg <= '1';
rf_RF_wr_opc_reg <= dst_B1_1(4 downto 0);
socket_RF_i1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_RF_i1_bus_cntrl_reg'length);
else
rf_RF_wr_load_reg <= '0';
end if;
if (squash_B1 = '0' and conv_integer(unsigned(dst_B1(6 downto 1))) = 36 and true) then
rf_bool_wr_load_reg <= '1';
rf_bool_wr_opc_reg <= dst_B1(0 downto 0);
socket_bool_i1_bus_cntrl_reg <= conv_std_logic_vector(0, socket_bool_i1_bus_cntrl_reg'length);
elsif (squash_B1_1 = '0' and conv_integer(unsigned(dst_B1_1(6 downto 1))) = 36 and true) then
rf_bool_wr_load_reg <= '1';
rf_bool_wr_opc_reg <= dst_B1_1(0 downto 0);
socket_bool_i1_bus_cntrl_reg <= conv_std_logic_vector(1, socket_bool_i1_bus_cntrl_reg'length);
else
rf_bool_wr_load_reg <= '0';
end if;
end if;
end if;
end if;
end process;
lock_reg_proc : process (clk)
begin
if (clk'event and clk = '1') then
if (rstx = '0') then
-- Locked during active reset post_decode_merged_glock_r <= '1';
else
post_decode_merged_glock_r <= post_decode_merged_glock;
end if;
end if;
end process lock_reg_proc;
lock_r <= merged_glock_req;
merged_glock_req <= lock_req(0) or lock_req(1) or lock_req(2) or lock_req(3) or lock_req(4);
pre_decode_merged_glock <= lock or merged_glock_req;
post_decode_merged_glock <= pre_decode_merged_glock or decode_fill_lock_reg;
locked <= post_decode_merged_glock_r;
glock(0) <= post_decode_merged_glock; -- to DATA_LSU
glock(1) <= post_decode_merged_glock; -- to alu_comp
glock(2) <= post_decode_merged_glock; -- to PARAM_LSU
glock(3) <= post_decode_merged_glock; -- to SP_LSU
glock(4) <= post_decode_merged_glock; -- to AQL_FU
glock(5) <= post_decode_merged_glock; -- to RF
glock(6) <= post_decode_merged_glock; -- to bool
glock(7) <= post_decode_merged_glock; -- to IMM
glock(8) <= post_decode_merged_glock;
decode_pipeline_fill_lock: process (clk)
begin
if clk'event and clk = '1' then
if rstx = '0' then
decode_fill_lock_reg <= '1';
elsif lock = '0' then
decode_fill_lock_reg <= '0';
end if;
end if;
end process decode_pipeline_fill_lock;
end rtl_andor;
|
-- ======================================================================
-- CBC-DES encryption/decryption testbench
-- tests according to NIST 800-17 special publication
-- Copyright (C) 2011 Torsten Meissner
-------------------------------------------------------------------------
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_cbctdes is
end entity tb_cbctdes;
architecture rtl of tb_cbctdes is
type t_array is array (natural range <>) of std_logic_vector(0 to 63);
constant c_table_test_plain : t_array(0 to 18) :=
(x"01A1D6D039776742", x"5CD54CA83DEF57DA", x"0248D43806F67172",
x"51454B582DDF440A", x"42FD443059577FA2", x"059B5E0851CF143A",
x"0756D8E0774761D2", x"762514B829BF486A", x"3BDD119049372802",
x"26955F6835AF609A", x"164D5E404F275232", x"6B056E18759F5CCA",
x"004BD6EF09176062", x"480D39006EE762F2", x"437540C8698F3CFA",
x"072D43A077075292", x"02FE55778117F12A", x"1D9D5C5018F728C2",
x"305532286D6F295A");
signal s_tdes_answers : t_array(0 to 19);
signal s_reset : std_logic := '0';
signal s_clk : std_logic := '0';
signal s_mode : std_logic := '0';
signal s_start : std_logic := '0';
signal s_iv : std_logic_vector(0 to 63) := (others => '0');
signal s_key1 : std_logic_vector(0 to 63) := (others => '0');
signal s_key2 : std_logic_vector(0 to 63) := (others => '0');
signal s_key3 : std_logic_vector(0 to 63) := (others => '0');
signal s_datain : std_logic_vector(0 to 63) := (others => '0');
signal s_validin : std_logic := '0';
signal s_ready : std_logic := '0';
signal s_dataout : std_logic_vector(0 to 63);
signal s_validout : std_logic := '0';
component cbctdes is
port (
reset_i : in std_logic;
clk_i : in std_logic;
mode_i : in std_logic;
start_i : in std_logic;
iv_i : in std_logic_vector(0 to 63);
key1_i : in std_logic_vector(0 to 63);
key2_i : in std_logic_vector(0 TO 63);
key3_i : in std_logic_vector(0 TO 63);
data_i : in std_logic_vector(0 TO 63);
valid_i : in std_logic;
data_o : out std_logic_vector(0 TO 63);
valid_o : out std_logic;
ready_o : out std_logic
);
end component cbctdes;
begin
s_reset <= '1' after 100 ns;
s_clk <= not(s_clk) after 10 ns;
teststimuliP : process is
begin
s_start <= '0';
s_mode <= '0';
s_validin <= '0';
s_iv <= (others => '0');
s_key1 <= (others => '0');
s_key2 <= (others => '0');
s_key3 <= (others => '0');
s_datain <= (others => '0');
wait until s_reset = '1';
-- ENCRYPTION TESTS
-- cbc known answers test
for index in c_table_test_plain'range loop
wait until rising_edge(s_clk) and s_ready = '1';
s_key1 <= x"1111111111111111";
s_key2 <= x"5555555555555555";
s_key3 <= x"9999999999999999";
s_validin <= '1';
s_datain <= c_table_test_plain(index);
if(index = 0) then
s_start <= '1';
end if;
wait until rising_edge(s_clk);
s_validin <= '0';
s_start <= '0';
end loop;
wait until rising_edge(s_clk);
s_mode <= '0';
s_start <= '0';
s_validin <= '0';
s_key1 <= (others => '0');
s_key2 <= (others => '0');
s_key3 <= (others => '0');
s_datain <= (others => '0');
wait for 1 us;
-- DECRYPTION TESTS
-- cbc known answer test
for index in c_table_test_plain'range loop
wait until rising_edge(s_clk) and s_ready = '1';
s_key1 <= x"1111111111111111";
s_key2 <= x"5555555555555555";
s_key3 <= x"9999999999999999";
s_mode <= '1';
s_validin <= '1';
s_datain <= s_tdes_answers(index);
if(index = 0) then
s_start <= '1';
end if;
wait until rising_edge(s_clk);
s_start <= '0';
s_validin <= '0';
s_mode <= '0';
end loop;
wait until rising_edge(s_clk);
s_mode <= '0';
s_start <= '0';
s_validin <= '0';
s_key1 <= (others => '0');
s_key2 <= (others => '0');
s_key3 <= (others => '0');
s_datain <= (others => '0');
wait;
end process teststimuliP;
testcheckerP : process is
begin
report "# ENCRYPTION TESTS";
for index in c_table_test_plain'range loop
wait until rising_edge(s_clk) and s_validout = '1';
s_tdes_answers(index) <= s_dataout;
end loop;
report "# DECRYPTION TESTS";
report "# tdes known answer test";
for index in c_table_test_plain'range loop
wait until rising_edge(s_clk) and s_validout = '1';
assert (s_dataout = c_table_test_plain(index))
report "decryption error"
severity error;
end loop;
report "# Successfully passed all tests";
wait;
end process testcheckerP;
i_cbctdes : cbctdes
port map (
reset_i => s_reset,
clk_i => s_clk,
start_i => s_start,
mode_i => s_mode,
iv_i => s_iv,
key1_i => s_key1,
key2_i => s_key2,
key3_i => s_key3,
data_i => s_datain,
valid_i => s_validin,
data_o => s_dataout,
valid_o => s_validout,
ready_o => s_ready
);
end architecture rtl;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY design_1_rst_clk_wiz_1_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_clk_wiz_1_100M_0;
ARCHITECTURE design_1_rst_clk_wiz_1_100M_0_arch OF design_1_rst_clk_wiz_1_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_clk_wiz_1_100M_0_arch : ARCHITECTURE IS "design_1_rst_clk_wiz_1_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "design_1_rst_clk_wiz_1_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_clk_wiz_1_100M_0_arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY design_1_rst_clk_wiz_1_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_clk_wiz_1_100M_0;
ARCHITECTURE design_1_rst_clk_wiz_1_100M_0_arch OF design_1_rst_clk_wiz_1_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_clk_wiz_1_100M_0_arch : ARCHITECTURE IS "design_1_rst_clk_wiz_1_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_clk_wiz_1_100M_0_arch: ARCHITECTURE IS "design_1_rst_clk_wiz_1_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "artix7",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_clk_wiz_1_100M_0_arch;
|
-- niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 18;
FIFO_DEPTH : integer := 8;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_data : in std_logic_vector(17 downto 0) := (others => '0'); -- in.data
in_valid : in std_logic := '0'; -- .valid
in_ready : out std_logic; -- .ready
out_data : out std_logic_vector(17 downto 0); -- out.data
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
almost_empty_data : out std_logic;
almost_full_data : out std_logic;
csr_address : in std_logic_vector(1 downto 0) := (others => '0');
csr_read : in std_logic := '0';
csr_readdata : out std_logic_vector(31 downto 0);
csr_write : in std_logic := '0';
csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
in_channel : in std_logic := '0';
in_empty : in std_logic := '0';
in_endofpacket : in std_logic := '0';
in_error : in std_logic := '0';
in_startofpacket : in std_logic := '0';
out_channel : out std_logic;
out_empty : out std_logic;
out_endofpacket : out std_logic;
out_error : out std_logic;
out_startofpacket : out std_logic
);
end entity niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo;
architecture rtl of niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo is
component altera_avalon_sc_fifo is
generic (
SYMBOLS_PER_BEAT : integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS : integer := 1;
USE_STORE_FORWARD : integer := 0;
USE_ALMOST_FULL_IF : integer := 0;
USE_ALMOST_EMPTY_IF : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_data : in std_logic_vector(17 downto 0) := (others => 'X'); -- data
in_valid : in std_logic := 'X'; -- valid
in_ready : out std_logic; -- ready
out_data : out std_logic_vector(17 downto 0); -- data
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
csr_read : in std_logic := 'X'; -- read
csr_write : in std_logic := 'X'; -- write
csr_readdata : out std_logic_vector(31 downto 0); -- readdata
csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
almost_full_data : out std_logic; -- data
almost_empty_data : out std_logic; -- data
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
out_startofpacket : out std_logic; -- startofpacket
out_endofpacket : out std_logic; -- endofpacket
in_empty : in std_logic := 'X'; -- empty
out_empty : out std_logic; -- empty
in_error : in std_logic := 'X'; -- error
out_error : out std_logic; -- error
in_channel : in std_logic := 'X'; -- channel
out_channel : out std_logic -- channel
);
end component altera_avalon_sc_fifo;
begin
sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo : component altera_avalon_sc_fifo
generic map (
SYMBOLS_PER_BEAT => SYMBOLS_PER_BEAT,
BITS_PER_SYMBOL => BITS_PER_SYMBOL,
FIFO_DEPTH => FIFO_DEPTH,
CHANNEL_WIDTH => CHANNEL_WIDTH,
ERROR_WIDTH => ERROR_WIDTH,
USE_PACKETS => USE_PACKETS,
USE_FILL_LEVEL => USE_FILL_LEVEL,
EMPTY_LATENCY => EMPTY_LATENCY,
USE_MEMORY_BLOCKS => USE_MEMORY_BLOCKS,
USE_STORE_FORWARD => USE_STORE_FORWARD,
USE_ALMOST_FULL_IF => USE_ALMOST_FULL_IF,
USE_ALMOST_EMPTY_IF => USE_ALMOST_EMPTY_IF
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_data => in_data, -- in.data
in_valid => in_valid, -- .valid
in_ready => in_ready, -- .ready
out_data => out_data, -- out.data
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
csr_address => "00", -- (terminated)
csr_read => '0', -- (terminated)
csr_write => '0', -- (terminated)
csr_readdata => open, -- (terminated)
csr_writedata => "00000000000000000000000000000000", -- (terminated)
almost_full_data => open, -- (terminated)
almost_empty_data => open, -- (terminated)
in_startofpacket => '0', -- (terminated)
in_endofpacket => '0', -- (terminated)
out_startofpacket => open, -- (terminated)
out_endofpacket => open, -- (terminated)
in_empty => '0', -- (terminated)
out_empty => open, -- (terminated)
in_error => '0', -- (terminated)
out_error => open, -- (terminated)
in_channel => '0', -- (terminated)
out_channel => open -- (terminated)
);
end architecture rtl; -- of niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library IKWZM_SECURE_HASH;
--use IKWZM_SECURE_HASH.SHA1.all;
package lz4_pkg is
-- constants for the SHA-1
constant SYMBOL_BITS : integer := 8;
constant SYMBOLS : integer := 4;
constant REVERSE : integer := 1;
constant WORDS : integer := 1;
constant BLOCK_GAP : integer := 1;
-- Clock period definitions
constant clk_period : time := 10 ns;
component lz4_top
port (
clk_i : in std_logic;
reset_i : in std_logic;
entryStream_i : in std_logic;
outputStream_o : out std_logic;
outputFlag_o : out std_logic
);
end component;
component lz4_entryBuffer is
port (
clk_i : in std_logic;
reset_i : in std_logic;
entryStream_i : in std_logic;
toUTVal_o : out std_logic_vector(31 downto 0);
buffPoint_o : out std_logic_vector(12 downto 0);
-- flags:
Fs : in std_logic_vector(2 downto 0);
eof : out std_logic;
-- data to the output level
pos_i : in std_logic_vector(12 downto 0);
len_i : in std_logic_vector(12 downto 0);
literal_o : out std_logic_vector(31 downto 0);
-- output to the hash
CLR_o : out std_logic;
I_DATA_o : out std_logic_vector(31 downto 0);
I_ENA_o : out std_logic_vector(3 downto 0);
I_DONE_o : out std_logic;
I_LAST_o : out std_logic;
I_VAL_o : out std_logic;
O_RDY_o : out std_logic
);
end component;
component lz4_utval is
port (
clk_i : in std_logic;
reset_i : in std_logic;
fromEntry_i : in std_logic_vector(31 downto 0);
length_o : out std_logic_vector(12 downto 0);
-- flags:
Fs : in std_logic_vector(2 downto 0);
-- output to the hash
CLR_o : out std_logic;
I_DATA_o : out std_logic_vector(31 downto 0);
I_ENA_o : out std_logic_vector(3 downto 0);
I_DONE_o : out std_logic;
I_LAST_o : out std_logic;
I_VAL_o : out std_logic;
O_RDY_o : out std_logic
);
end component;
component lz4_utline is
port (
clk_i : in std_logic;
reset_i : in std_logic;
length_i : in std_logic_vector(12 downto 0);
position_i : in std_logic_vector(12 downto 0);
-- flags:
Fs : in std_logic_vector(2 downto 0);
match : out std_logic;
-- output from the hash
O_DATA_i : in std_logic_vector(159 downto 0);
O_VAL_i : in std_logic;
I_RDY_i : in std_logic;
-- for the dict comp
startpars_o : out std_logic;
dictLine_i : in std_logic_vector(185 downto 0);
todictLine_o : out std_logic_vector(185 downto 0);
-- line used by the out level
lineToOut_o : out std_logic_vector(185 downto 0);
offset_o : out std_logic_vector(12 downto 0)
);
end component;
component lz4_fsm is
port (
clk_i : in std_logic;
reset_i : in std_logic;
match : in std_logic;
eof : in std_logic;
Fs : out std_logic_vector(2 downto 0)
);
end component;
component lz4_dictionary is
port (
clk_i : in std_logic;
reset_i : in std_logic;
-- for the dict comp
startpars_i : in std_logic;
dictLine_o : out std_logic_vector(185 downto 0);
todictLine_i : in std_logic_vector(185 downto 0)
);
end component;
component lz4_assembly is
port (
clk_i : in std_logic;
reset_i : in std_logic;
litLength_i : in std_logic_vector(9 downto 0);
offset_i : in std_logic_vector(9 downto 0);
matchLength_i : in std_logic_vector(9 downto 0);
internalStream_i : in std_logic;
-- main output
outputStream_o : out std_logic;
outputFlag_o : out std_logic
);
end component;
component lz4_entryDict is
port (
clk_i : in std_logic;
reset_i : in std_logic;
entryBytes_i : in std_logic_vector(7 downto 0);
litLength_o : out std_logic_vector(9 downto 0);
offset_o : out std_logic_vector(9 downto 0);
matchLength_o : out std_logic_vector(9 downto 0);
internalStream_o : out std_logic_vector(7 downto 0)
);
end component;
end;
|
-------------------------------------------------------------------------------
-- axis_accelerator_adpater.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2013] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Title : AXI4-Stream Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : axis_accelerator_adapter.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: This is the Accelerator Adapter top-level module. It is
-- implemented as a wrapper that uses buses for all input/output arguments.
-- This top-level module supports up-to eight input/output arguments.
-- Then, it instantiates the "xd_adapter_core", which is a completely
-- parametrizable module.
-------------------------------------------------------------------------------
-- Structure:
--
-- axis_accelerator_adapter.vhd
-- xd_adapter_pkg.vhd
-- axis_accelerator_adapter_core.vhd
-- |-- axi_lite_adapter
-- |-- cdc_sync.vhd
-- |-- xd_input_args_module.vhd
-- |-- xd_s2m_adapter.vhd
-- |-- xd_s2m_converter.vhd
-- |-- xd_s2m_memory_dc.vhd
-- |-- xd_iarg_s2s_adapter.vhd
-- |-- s2s_async_fifo_wt.vhd
-- |-- xd_output_args_module.vhd
-- |-- cdc_sync.vhd
-- |-- xd_m2s_adapter.vhd
-- |-- xd_m2s_converter.vhd
-- |-- xd_m2s_memory_dc.vhd
-- |-- arg_mem_bank.vhd
-- |-- asymmetric_dp_bank_v6.vhd
-- |-- symmetric_dp_bank_v6.vhd
-- |-- dp_bank_sdp_v6.vhd
-- |-- oarg_columnized_mem_bank.vhd
-- |-- srl_fifo_32_wt.vhd
-- |-- xd_oarg_s2s_adapter.vhd
-- |-- s2s_async_fifo_wt.vhd
-- |-- xd_sync_module.vhd
-- |-- cdc_sync.vhd
-- |-- sync_ap_status.vhd
-- |-- async_fifo_dist_wt.vhd
-- |-- xd_input_scalars_module.vhd
-- |-- xd_input_scalars_fifo.vhd
-- |-- xd_output_scalars_module.vhd
-- |-- xd_output_scalars_fifo.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "aclk","clk_div#", "clk_#x"
-- reset signals: "rst", "aresetn","rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- History:
-- ~~~~~~
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-01-31 1.0 pankajk removed perf mon ports, all ports in lower case
-- 2013-05-10 1.1 pankajk Seperated scalar port and brought those to top
-- entity
-- 2013-07-22 2.0 pankajk New scalar ports (*.vld, *.ack) and parameter
-- scalar_mode added to support accelerator IP
-- interface ap_none, ap_hs, ap_vld
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.axis_accelerator_adapter_core;
entity axis_accelerator_adapter is
generic (
-- System generics:
C_FAMILY : string := "virtex7"; -- Xilinx FPGA family
--
C_S_AXI_ADDR_WIDTH : integer := 13;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
--
C_AP_ADAPTER_ID : integer range 0 to 15 :=1;
C_N_INPUT_ARGS : integer := 2;
C_N_OUTPUT_ARGS : integer := 1;
C_ENABLE_STREAM_CLK : integer := 0;
C_PRMRY_IS_ACLK_ASYNC : integer := 1;
C_S_AXIS_HAS_TSTRB : integer := 0;
C_S_AXIS_HAS_TKEEP : integer := 0;
--
C_S_AXIS_TDATA_WIDTH : integer := 64;
C_S_AXIS_TUSER_WIDTH : integer := 8;
C_S_AXIS_TID_WIDTH : integer := 4;
C_S_AXIS_TDEST_WIDTH : integer := 8;
--
C_AP_IARG_TYPE : std_logic_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
C_AP_IARG_MB_DEPTH : std_logic_vector := X"0000000400000004000000040000000400000004000000040000000400000004";
C_AP_IARG_WIDTH : std_logic_vector := X"0000002000000020000000200000002000000020000000200000002000000020";
C_AP_IARG_N_DIM : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_IARG_DIM_1 : std_logic_vector := X"0000040000000400000004000000040000000400000004000000040000000400";
C_AP_IARG_DIM_2 : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_IARG_FORMAT_TYPE : std_logic_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
C_AP_IARG_FORMAT_FACTOR : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_IARG_FORMAT_DIM : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
--
C_AP_IARG_0_DWIDTH : integer := 32;
C_AP_IARG_1_DWIDTH : integer := 32;
C_AP_IARG_2_DWIDTH : integer := 32;
C_AP_IARG_3_DWIDTH : integer := 32;
C_AP_IARG_4_DWIDTH : integer := 32;
C_AP_IARG_5_DWIDTH : integer := 32;
C_AP_IARG_6_DWIDTH : integer := 32;
C_AP_IARG_7_DWIDTH : integer := 32;
--
C_M_AXIS_TDATA_WIDTH : integer := 64;
C_M_AXIS_TUSER_WIDTH : integer := 8;
C_M_AXIS_TID_WIDTH : integer := 4;
C_M_AXIS_TDEST_WIDTH : integer := 8;
--
C_AP_OARG_TYPE : std_logic_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
C_AP_OARG_MB_DEPTH : std_logic_vector := X"0000000400000004000000040000000400000004000000040000000400000004";
C_AP_OARG_WIDTH : std_logic_vector := X"0000002000000020000000200000002000000020000000200000002000000020";
C_AP_OARG_N_DIM : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_OARG_DIM : std_logic_vector := X"0000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000080000000001000000010000000100000008";
C_AP_OARG_DIM_1 : std_logic_vector := X"0000040000000400000004000000040000000400000004000000080000000008";
C_AP_OARG_DIM_2 : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_OARG_FORMAT_TYPE : std_logic_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
C_AP_OARG_FORMAT_FACTOR : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_OARG_FORMAT_DIM : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
--
C_AP_OARG_0_DWIDTH : integer := 32;
C_AP_OARG_1_DWIDTH : integer := 32;
C_AP_OARG_2_DWIDTH : integer := 32;
C_AP_OARG_3_DWIDTH : integer := 32;
C_AP_OARG_4_DWIDTH : integer := 32;
C_AP_OARG_5_DWIDTH : integer := 32;
C_AP_OARG_6_DWIDTH : integer := 32;
C_AP_OARG_7_DWIDTH : integer := 32;
--
C_INPUT_SCALAR_0_WIDTH : integer := 0;
C_INPUT_SCALAR_1_WIDTH : integer := 0;
C_INPUT_SCALAR_2_WIDTH : integer := 0;
C_INPUT_SCALAR_3_WIDTH : integer := 0;
C_INPUT_SCALAR_4_WIDTH : integer := 0;
C_INPUT_SCALAR_5_WIDTH : integer := 0;
C_INPUT_SCALAR_6_WIDTH : integer := 0;
C_INPUT_SCALAR_7_WIDTH : integer := 0;
C_INPUT_SCALAR_8_WIDTH : integer := 0;
C_INPUT_SCALAR_9_WIDTH : integer := 0;
C_INPUT_SCALAR_10_WIDTH : integer := 0;
C_INPUT_SCALAR_11_WIDTH : integer := 0;
C_INPUT_SCALAR_12_WIDTH : integer := 0;
C_INPUT_SCALAR_13_WIDTH : integer := 0;
C_INPUT_SCALAR_14_WIDTH : integer := 0;
C_INPUT_SCALAR_15_WIDTH : integer := 0;
C_OUTPUT_SCALAR_0_WIDTH : integer := 0;
C_OUTPUT_SCALAR_1_WIDTH : integer := 0;
C_OUTPUT_SCALAR_2_WIDTH : integer := 0;
C_OUTPUT_SCALAR_3_WIDTH : integer := 0;
C_OUTPUT_SCALAR_4_WIDTH : integer := 0;
C_OUTPUT_SCALAR_5_WIDTH : integer := 0;
C_OUTPUT_SCALAR_6_WIDTH : integer := 0;
C_OUTPUT_SCALAR_7_WIDTH : integer := 0;
C_OUTPUT_SCALAR_8_WIDTH : integer := 0;
C_OUTPUT_SCALAR_9_WIDTH : integer := 0;
C_OUTPUT_SCALAR_10_WIDTH : integer := 0;
C_OUTPUT_SCALAR_11_WIDTH : integer := 0;
C_OUTPUT_SCALAR_12_WIDTH : integer := 0;
C_OUTPUT_SCALAR_13_WIDTH : integer := 0;
C_OUTPUT_SCALAR_14_WIDTH : integer := 0;
C_OUTPUT_SCALAR_15_WIDTH : integer := 0;
C_N_INOUT_SCALARS : integer := 0;
C_N_INPUT_SCALARS : integer := 0;
C_INPUT_SCALAR_DWIDTH : std_logic_vector := X"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020";
C_AP_ISCALAR_DOUT_WIDTH : integer := 32;
C_INPUT_SCALAR_MODE : std_logic_vector(63 downto 0) := X"0000000000000000";
--
C_N_OUTPUT_SCALARS : integer := 0;
C_OUTPUT_SCALAR_DWIDTH : std_logic_vector := X"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020";
C_AP_OSCALAR_DIN_WIDTH : integer := 32;
C_AP_ISCALAR_IO_DOUT_WIDTH : integer := 32;
C_AP_OSCALAR_IO_DIN_WIDTH : integer := 32;
C_OUTPUT_SCALAR_MODE : std_logic_vector(63 downto 0) := X"0000000000000000";
C_NONE : integer := 2);
port (
-------------------------------
-- AXI4-Lite Slave Interface --
-------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
----------------------------------------------
-- AXI4-Stream slave interface clock reset
----------------------------------------------
s_axis_aclk : in std_logic;
s_axis_aresetn : in std_logic;
----------------------------------------------
-- AXI4-Stream master interface clock reset
----------------------------------------------
m_axis_aclk : in std_logic;
m_axis_aresetn : in std_logic;
----------------------------------------------
-- Accelerator clock --
----------------------------------------------
aclk : in std_logic;
-------------------------------
-- AXI4-Stream Slave Interface --
-------------------------------
s_axis_0_aclk : in std_logic;
s_axis_0_aresetn : in std_logic;
s_axis_0_tvalid : in std_logic;
s_axis_0_tready : out std_logic;
s_axis_0_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_0_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_0_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_0_tlast : in std_logic;
s_axis_0_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_0_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_0_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_1_aclk : in std_logic;
s_axis_1_aresetn : in std_logic;
s_axis_1_tvalid : in std_logic;
s_axis_1_tready : out std_logic;
s_axis_1_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_1_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_1_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_1_tlast : in std_logic;
s_axis_1_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_1_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_1_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_2_aclk : in std_logic;
s_axis_2_aresetn : in std_logic;
s_axis_2_tvalid : in std_logic;
s_axis_2_tready : out std_logic;
s_axis_2_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_2_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_2_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_2_tlast : in std_logic;
s_axis_2_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_2_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_2_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_3_aclk : in std_logic;
s_axis_3_aresetn : in std_logic;
s_axis_3_tvalid : in std_logic;
s_axis_3_tready : out std_logic;
s_axis_3_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_3_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_3_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_3_tlast : in std_logic;
s_axis_3_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_3_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_3_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_4_aclk : in std_logic;
s_axis_4_aresetn : in std_logic;
s_axis_4_tvalid : in std_logic;
s_axis_4_tready : out std_logic;
s_axis_4_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_4_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_4_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_4_tlast : in std_logic;
s_axis_4_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_4_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_4_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_5_aclk : in std_logic;
s_axis_5_aresetn : in std_logic;
s_axis_5_tvalid : in std_logic;
s_axis_5_tready : out std_logic;
s_axis_5_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_5_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_5_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_5_tlast : in std_logic;
s_axis_5_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_5_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_5_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_6_aclk : in std_logic;
s_axis_6_aresetn : in std_logic;
s_axis_6_tvalid : in std_logic;
s_axis_6_tready : out std_logic;
s_axis_6_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_6_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_6_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_6_tlast : in std_logic;
s_axis_6_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_6_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_6_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_7_aclk : in std_logic;
s_axis_7_aresetn : in std_logic;
s_axis_7_tvalid : in std_logic;
s_axis_7_tready : out std_logic;
s_axis_7_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_7_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_7_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_7_tlast : in std_logic;
s_axis_7_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_7_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_7_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
------------------------------------------
-- Accelerator Port input arguments (BRAM)
------------------------------------------
ap_iarg_0_clk : in std_logic;
ap_iarg_0_rst : in std_logic;
ap_iarg_0_addr : in std_logic_vector(31 downto 0);
ap_iarg_0_ce : in std_logic;
ap_iarg_0_we : in std_logic_vector(C_AP_IARG_0_DWIDTH/8-1 downto 0);
ap_iarg_0_din : in std_logic_vector(C_AP_IARG_0_DWIDTH-1 downto 0);
ap_iarg_0_dout : out std_logic_vector(C_AP_IARG_0_DWIDTH-1 downto 0);
---
ap_iarg_1_clk : in std_logic;
ap_iarg_1_rst : in std_logic;
ap_iarg_1_addr : in std_logic_vector(31 downto 0);
ap_iarg_1_ce : in std_logic;
ap_iarg_1_we : in std_logic_vector(C_AP_IARG_1_DWIDTH/8-1 downto 0);
ap_iarg_1_din : in std_logic_vector(C_AP_IARG_1_DWIDTH-1 downto 0);
ap_iarg_1_dout : out std_logic_vector(C_AP_IARG_1_DWIDTH-1 downto 0);
---
ap_iarg_2_clk : in std_logic;
ap_iarg_2_rst : in std_logic;
ap_iarg_2_addr : in std_logic_vector(31 downto 0);
ap_iarg_2_ce : in std_logic;
ap_iarg_2_we : in std_logic_vector(C_AP_IARG_2_DWIDTH/8-1 downto 0);
ap_iarg_2_din : in std_logic_vector(C_AP_IARG_2_DWIDTH-1 downto 0);
ap_iarg_2_dout : out std_logic_vector(C_AP_IARG_2_DWIDTH-1 downto 0);
---
ap_iarg_3_clk : in std_logic;
ap_iarg_3_rst : in std_logic;
ap_iarg_3_addr : in std_logic_vector(31 downto 0);
ap_iarg_3_ce : in std_logic;
ap_iarg_3_we : in std_logic_vector(C_AP_IARG_3_DWIDTH/8-1 downto 0);
ap_iarg_3_din : in std_logic_vector(C_AP_IARG_3_DWIDTH-1 downto 0);
ap_iarg_3_dout : out std_logic_vector(C_AP_IARG_3_DWIDTH-1 downto 0);
---
ap_iarg_4_clk : in std_logic;
ap_iarg_4_rst : in std_logic;
ap_iarg_4_addr : in std_logic_vector(31 downto 0);
ap_iarg_4_ce : in std_logic;
ap_iarg_4_we : in std_logic_vector(C_AP_IARG_4_DWIDTH/8-1 downto 0);
ap_iarg_4_din : in std_logic_vector(C_AP_IARG_4_DWIDTH-1 downto 0);
ap_iarg_4_dout : out std_logic_vector(C_AP_IARG_4_DWIDTH-1 downto 0);
---
ap_iarg_5_clk : in std_logic;
ap_iarg_5_rst : in std_logic;
ap_iarg_5_addr : in std_logic_vector(31 downto 0);
ap_iarg_5_ce : in std_logic;
ap_iarg_5_we : in std_logic_vector(C_AP_IARG_5_DWIDTH/8-1 downto 0);
ap_iarg_5_din : in std_logic_vector(C_AP_IARG_5_DWIDTH-1 downto 0);
ap_iarg_5_dout : out std_logic_vector(C_AP_IARG_5_DWIDTH-1 downto 0);
---
ap_iarg_6_clk : in std_logic;
ap_iarg_6_rst : in std_logic;
ap_iarg_6_addr : in std_logic_vector(31 downto 0);
ap_iarg_6_ce : in std_logic;
ap_iarg_6_we : in std_logic_vector(C_AP_IARG_6_DWIDTH/8-1 downto 0);
ap_iarg_6_din : in std_logic_vector(C_AP_IARG_6_DWIDTH-1 downto 0);
ap_iarg_6_dout : out std_logic_vector(C_AP_IARG_6_DWIDTH-1 downto 0);
---
ap_iarg_7_clk : in std_logic;
ap_iarg_7_rst : in std_logic;
ap_iarg_7_addr : in std_logic_vector(31 downto 0);
ap_iarg_7_ce : in std_logic;
ap_iarg_7_we : in std_logic_vector(C_AP_IARG_7_DWIDTH/8-1 downto 0);
ap_iarg_7_din : in std_logic_vector(C_AP_IARG_7_DWIDTH-1 downto 0);
ap_iarg_7_dout : out std_logic_vector(C_AP_IARG_7_DWIDTH-1 downto 0);
---------------------------------------------
-- Accelerator Port input arguments (FIFO) --
---------------------------------------------
ap_fifo_iarg_0_dout : out std_logic_vector(C_AP_IARG_0_DWIDTH-1 downto 0);
ap_fifo_iarg_0_read : in std_logic;
ap_fifo_iarg_0_empty_n : out std_logic;
ap_fifo_iarg_1_dout : out std_logic_vector(C_AP_IARG_1_DWIDTH-1 downto 0);
ap_fifo_iarg_1_read : in std_logic;
ap_fifo_iarg_1_empty_n : out std_logic;
ap_fifo_iarg_2_dout : out std_logic_vector(C_AP_IARG_2_DWIDTH-1 downto 0);
ap_fifo_iarg_2_read : in std_logic;
ap_fifo_iarg_2_empty_n : out std_logic;
ap_fifo_iarg_3_dout : out std_logic_vector(C_AP_IARG_3_DWIDTH-1 downto 0);
ap_fifo_iarg_3_read : in std_logic;
ap_fifo_iarg_3_empty_n : out std_logic;
ap_fifo_iarg_4_dout : out std_logic_vector(C_AP_IARG_4_DWIDTH-1 downto 0);
ap_fifo_iarg_4_read : in std_logic;
ap_fifo_iarg_4_empty_n : out std_logic;
ap_fifo_iarg_5_dout : out std_logic_vector(C_AP_IARG_5_DWIDTH-1 downto 0);
ap_fifo_iarg_5_read : in std_logic;
ap_fifo_iarg_5_empty_n : out std_logic;
ap_fifo_iarg_6_dout : out std_logic_vector(C_AP_IARG_6_DWIDTH-1 downto 0);
ap_fifo_iarg_6_read : in std_logic;
ap_fifo_iarg_6_empty_n : out std_logic;
ap_fifo_iarg_7_dout : out std_logic_vector(C_AP_IARG_7_DWIDTH-1 downto 0);
ap_fifo_iarg_7_read : in std_logic;
ap_fifo_iarg_7_empty_n : out std_logic;
-------------------------------
--* AXI4-Stream Slave Interface* --
-- Output Arguments
-------------------------------
m_axis_0_aclk : in std_logic;
m_axis_0_aresetn : in std_logic;
m_axis_0_tvalid : out std_logic;
m_axis_0_tready : in std_logic;
m_axis_0_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_0_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_0_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_0_tlast : out std_logic;
m_axis_0_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_0_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_0_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_1_aclk : in std_logic;
m_axis_1_aresetn : in std_logic;
m_axis_1_tvalid : out std_logic;
m_axis_1_tready : in std_logic;
m_axis_1_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_1_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_1_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_1_tlast : out std_logic;
m_axis_1_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_1_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_1_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_2_aclk : in std_logic;
m_axis_2_aresetn : in std_logic;
m_axis_2_tvalid : out std_logic;
m_axis_2_tready : in std_logic;
m_axis_2_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_2_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_2_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_2_tlast : out std_logic;
m_axis_2_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_2_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_2_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_3_aclk : in std_logic;
m_axis_3_aresetn : in std_logic;
m_axis_3_tvalid : out std_logic;
m_axis_3_tready : in std_logic;
m_axis_3_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_3_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_3_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_3_tlast : out std_logic;
m_axis_3_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_3_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_3_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_4_aclk : in std_logic;
m_axis_4_aresetn : in std_logic;
m_axis_4_tvalid : out std_logic;
m_axis_4_tready : in std_logic;
m_axis_4_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_4_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_4_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_4_tlast : out std_logic;
m_axis_4_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_4_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_4_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_5_aclk : in std_logic;
m_axis_5_aresetn : in std_logic;
m_axis_5_tvalid : out std_logic;
m_axis_5_tready : in std_logic;
m_axis_5_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_5_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_5_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_5_tlast : out std_logic;
m_axis_5_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_5_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_5_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_6_aclk : in std_logic;
m_axis_6_aresetn : in std_logic;
m_axis_6_tvalid : out std_logic;
m_axis_6_tready : in std_logic;
m_axis_6_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_6_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_6_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_6_tlast : out std_logic;
m_axis_6_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_6_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_6_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_7_aclk : in std_logic;
m_axis_7_aresetn : in std_logic;
m_axis_7_tvalid : out std_logic;
m_axis_7_tready : in std_logic;
m_axis_7_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_7_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_7_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_7_tlast : out std_logic;
m_axis_7_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_7_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_7_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
----------------------------------------------
-- Accelerator Port output arguments (BRAM) --
----------------------------------------------
--- AP output arguments
ap_oarg_0_clk : in std_logic;
ap_oarg_0_rst : in std_logic;
ap_oarg_0_addr : in std_logic_vector(31 downto 0);
ap_oarg_0_ce : in std_logic;
ap_oarg_0_we : in std_logic_vector(C_AP_OARG_0_DWIDTH/8-1 downto 0);
ap_oarg_0_din : in std_logic_vector(C_AP_OARG_0_DWIDTH-1 downto 0);
ap_oarg_0_dout : out std_logic_vector(C_AP_OARG_0_DWIDTH-1 downto 0);
---
ap_oarg_1_clk : in std_logic;
ap_oarg_1_rst : in std_logic;
ap_oarg_1_addr : in std_logic_vector(31 downto 0);
ap_oarg_1_ce : in std_logic;
ap_oarg_1_we : in std_logic_vector(C_AP_OARG_1_DWIDTH/8-1 downto 0);
ap_oarg_1_din : in std_logic_vector(C_AP_OARG_1_DWIDTH-1 downto 0);
ap_oarg_1_dout : out std_logic_vector(C_AP_OARG_1_DWIDTH-1 downto 0);
---
ap_oarg_2_clk : in std_logic;
ap_oarg_2_rst : in std_logic;
ap_oarg_2_addr : in std_logic_vector(31 downto 0);
ap_oarg_2_ce : in std_logic;
ap_oarg_2_we : in std_logic_vector(C_AP_OARG_2_DWIDTH/8-1 downto 0);
ap_oarg_2_din : in std_logic_vector(C_AP_OARG_2_DWIDTH-1 downto 0);
ap_oarg_2_dout : out std_logic_vector(C_AP_OARG_2_DWIDTH-1 downto 0);
---
ap_oarg_3_clk : in std_logic;
ap_oarg_3_rst : in std_logic;
ap_oarg_3_addr : in std_logic_vector(31 downto 0);
ap_oarg_3_ce : in std_logic;
ap_oarg_3_we : in std_logic_vector(C_AP_OARG_3_DWIDTH/8-1 downto 0);
ap_oarg_3_din : in std_logic_vector(C_AP_OARG_3_DWIDTH-1 downto 0);
ap_oarg_3_dout : out std_logic_vector(C_AP_OARG_3_DWIDTH-1 downto 0);
---
ap_oarg_4_clk : in std_logic;
ap_oarg_4_rst : in std_logic;
ap_oarg_4_addr : in std_logic_vector(31 downto 0);
ap_oarg_4_ce : in std_logic;
ap_oarg_4_we : in std_logic_vector(C_AP_OARG_4_DWIDTH/8-1 downto 0);
ap_oarg_4_din : in std_logic_vector(C_AP_OARG_4_DWIDTH-1 downto 0);
ap_oarg_4_dout : out std_logic_vector(C_AP_OARG_4_DWIDTH-1 downto 0);
---
ap_oarg_5_clk : in std_logic;
ap_oarg_5_rst : in std_logic;
ap_oarg_5_addr : in std_logic_vector(31 downto 0);
ap_oarg_5_ce : in std_logic;
ap_oarg_5_we : in std_logic_vector(C_AP_OARG_5_DWIDTH/8-1 downto 0);
ap_oarg_5_din : in std_logic_vector(C_AP_OARG_5_DWIDTH-1 downto 0);
ap_oarg_5_dout : out std_logic_vector(C_AP_OARG_5_DWIDTH-1 downto 0);
---
ap_oarg_6_clk : in std_logic;
ap_oarg_6_rst : in std_logic;
ap_oarg_6_addr : in std_logic_vector(31 downto 0);
ap_oarg_6_ce : in std_logic;
ap_oarg_6_we : in std_logic_vector(C_AP_OARG_6_DWIDTH/8-1 downto 0);
ap_oarg_6_din : in std_logic_vector(C_AP_OARG_6_DWIDTH-1 downto 0);
ap_oarg_6_dout : out std_logic_vector(C_AP_OARG_6_DWIDTH-1 downto 0);
---
ap_oarg_7_clk : in std_logic;
ap_oarg_7_rst : in std_logic;
ap_oarg_7_addr : in std_logic_vector(31 downto 0);
ap_oarg_7_ce : in std_logic;
ap_oarg_7_we : in std_logic_vector(C_AP_OARG_7_DWIDTH/8-1 downto 0);
ap_oarg_7_din : in std_logic_vector(C_AP_OARG_7_DWIDTH-1 downto 0);
ap_oarg_7_dout : out std_logic_vector(C_AP_OARG_7_DWIDTH-1 downto 0);
----------------------------------------------
-- Accelerator Port output arguments (FIFO) --
----------------------------------------------
ap_fifo_oarg_0_din : in std_logic_vector(C_AP_OARG_0_DWIDTH-1 downto 0);
ap_fifo_oarg_0_write : in std_logic;
ap_fifo_oarg_0_full_n : out std_logic;
ap_fifo_oarg_1_din : in std_logic_vector(C_AP_OARG_1_DWIDTH-1 downto 0);
ap_fifo_oarg_1_write : in std_logic;
ap_fifo_oarg_1_full_n : out std_logic;
ap_fifo_oarg_2_din : in std_logic_vector(C_AP_OARG_2_DWIDTH-1 downto 0);
ap_fifo_oarg_2_write : in std_logic;
ap_fifo_oarg_2_full_n : out std_logic;
ap_fifo_oarg_3_din : in std_logic_vector(C_AP_OARG_3_DWIDTH-1 downto 0);
ap_fifo_oarg_3_write : in std_logic;
ap_fifo_oarg_3_full_n : out std_logic;
ap_fifo_oarg_4_din : in std_logic_vector(C_AP_OARG_4_DWIDTH-1 downto 0);
ap_fifo_oarg_4_write : in std_logic;
ap_fifo_oarg_4_full_n : out std_logic;
ap_fifo_oarg_5_din : in std_logic_vector(C_AP_OARG_5_DWIDTH-1 downto 0);
ap_fifo_oarg_5_write : in std_logic;
ap_fifo_oarg_5_full_n : out std_logic;
ap_fifo_oarg_6_din : in std_logic_vector(C_AP_OARG_6_DWIDTH-1 downto 0);
ap_fifo_oarg_6_write : in std_logic;
ap_fifo_oarg_6_full_n : out std_logic;
ap_fifo_oarg_7_din : in std_logic_vector(C_AP_OARG_7_DWIDTH-1 downto 0);
ap_fifo_oarg_7_write : in std_logic;
ap_fifo_oarg_7_full_n : out std_logic;
----------------------------------------------
-- Accelerator Control Interface --
----------------------------------------------
ap_start : out std_logic;
ap_ready : in std_logic;
ap_done : in std_logic;
ap_continue : out std_logic;
ap_idle : in std_logic;
aresetn : out std_logic;
----------------------------------------------
-- Accelerator Input Scalar Interface --
----------------------------------------------
ap_iscalar_0_dout : out std_logic_vector(C_INPUT_SCALAR_0_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_1_dout : out std_logic_vector(C_INPUT_SCALAR_1_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_2_dout : out std_logic_vector(C_INPUT_SCALAR_2_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_3_dout : out std_logic_vector(C_INPUT_SCALAR_3_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_4_dout : out std_logic_vector(C_INPUT_SCALAR_4_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_5_dout : out std_logic_vector(C_INPUT_SCALAR_5_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_6_dout : out std_logic_vector(C_INPUT_SCALAR_6_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_7_dout : out std_logic_vector(C_INPUT_SCALAR_7_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_8_dout : out std_logic_vector(C_INPUT_SCALAR_8_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_9_dout : out std_logic_vector(C_INPUT_SCALAR_9_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_10_dout : out std_logic_vector(C_INPUT_SCALAR_10_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_11_dout : out std_logic_vector(C_INPUT_SCALAR_11_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_12_dout : out std_logic_vector(C_INPUT_SCALAR_12_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_13_dout : out std_logic_vector(C_INPUT_SCALAR_13_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_14_dout : out std_logic_vector(C_INPUT_SCALAR_14_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_15_dout : out std_logic_vector(C_INPUT_SCALAR_15_WIDTH-1 downto 0) := (others=>'0');
-- Inpput scalar Valid signals (valid for AP_HS & AP_VLD modes)
ap_iscalar_0_vld : out std_logic;
ap_iscalar_1_vld : out std_logic;
ap_iscalar_2_vld : out std_logic;
ap_iscalar_3_vld : out std_logic;
ap_iscalar_4_vld : out std_logic;
ap_iscalar_5_vld : out std_logic;
ap_iscalar_6_vld : out std_logic;
ap_iscalar_7_vld : out std_logic;
ap_iscalar_8_vld : out std_logic;
ap_iscalar_9_vld : out std_logic;
ap_iscalar_10_vld : out std_logic;
ap_iscalar_11_vld : out std_logic;
ap_iscalar_12_vld : out std_logic;
ap_iscalar_13_vld : out std_logic;
ap_iscalar_14_vld : out std_logic;
ap_iscalar_15_vld : out std_logic;
-- Input Scalar ack - (valid for AP_HS mode)
ap_iscalar_0_ack : in std_logic;
ap_iscalar_1_ack : in std_logic;
ap_iscalar_2_ack : in std_logic;
ap_iscalar_3_ack : in std_logic;
ap_iscalar_4_ack : in std_logic;
ap_iscalar_5_ack : in std_logic;
ap_iscalar_6_ack : in std_logic;
ap_iscalar_7_ack : in std_logic;
ap_iscalar_8_ack : in std_logic;
ap_iscalar_9_ack : in std_logic;
ap_iscalar_10_ack : in std_logic;
ap_iscalar_11_ack : in std_logic;
ap_iscalar_12_ack : in std_logic;
ap_iscalar_13_ack : in std_logic;
ap_iscalar_14_ack : in std_logic;
ap_iscalar_15_ack : in std_logic;
----------------------------------------------
-- Accelerator Output Scalar Interface --
----------------------------------------------
ap_oscalar_0_din : in std_logic_vector(C_OUTPUT_SCALAR_0_WIDTH-1 downto 0);
ap_oscalar_1_din : in std_logic_vector(C_OUTPUT_SCALAR_1_WIDTH-1 downto 0);
ap_oscalar_2_din : in std_logic_vector(C_OUTPUT_SCALAR_2_WIDTH-1 downto 0);
ap_oscalar_3_din : in std_logic_vector(C_OUTPUT_SCALAR_3_WIDTH-1 downto 0);
ap_oscalar_4_din : in std_logic_vector(C_OUTPUT_SCALAR_4_WIDTH-1 downto 0);
ap_oscalar_5_din : in std_logic_vector(C_OUTPUT_SCALAR_5_WIDTH-1 downto 0);
ap_oscalar_6_din : in std_logic_vector(C_OUTPUT_SCALAR_6_WIDTH-1 downto 0);
ap_oscalar_7_din : in std_logic_vector(C_OUTPUT_SCALAR_7_WIDTH-1 downto 0);
ap_oscalar_8_din : in std_logic_vector(C_OUTPUT_SCALAR_8_WIDTH-1 downto 0);
ap_oscalar_9_din : in std_logic_vector(C_OUTPUT_SCALAR_9_WIDTH-1 downto 0);
ap_oscalar_10_din : in std_logic_vector(C_OUTPUT_SCALAR_10_WIDTH-1 downto 0);
ap_oscalar_11_din : in std_logic_vector(C_OUTPUT_SCALAR_11_WIDTH-1 downto 0);
ap_oscalar_12_din : in std_logic_vector(C_OUTPUT_SCALAR_12_WIDTH-1 downto 0);
ap_oscalar_13_din : in std_logic_vector(C_OUTPUT_SCALAR_13_WIDTH-1 downto 0);
ap_oscalar_14_din : in std_logic_vector(C_OUTPUT_SCALAR_14_WIDTH-1 downto 0);
ap_oscalar_15_din : in std_logic_vector(C_OUTPUT_SCALAR_15_WIDTH-1 downto 0);
-- Output scalar Valid signals (valid for AP_HS & AP_VLD modes)
ap_oscalar_0_vld : in std_logic;
ap_oscalar_1_vld : in std_logic;
ap_oscalar_2_vld : in std_logic;
ap_oscalar_3_vld : in std_logic;
ap_oscalar_4_vld : in std_logic;
ap_oscalar_5_vld : in std_logic;
ap_oscalar_6_vld : in std_logic;
ap_oscalar_7_vld : in std_logic;
ap_oscalar_8_vld : in std_logic;
ap_oscalar_9_vld : in std_logic;
ap_oscalar_10_vld : in std_logic;
ap_oscalar_11_vld : in std_logic;
ap_oscalar_12_vld : in std_logic;
ap_oscalar_13_vld : in std_logic;
ap_oscalar_14_vld : in std_logic;
ap_oscalar_15_vld : in std_logic;
-- Output Scalar ack - (valid for AP_HS mode)
ap_oscalar_0_ack : out std_logic;
ap_oscalar_1_ack : out std_logic;
ap_oscalar_2_ack : out std_logic;
ap_oscalar_3_ack : out std_logic;
ap_oscalar_4_ack : out std_logic;
ap_oscalar_5_ack : out std_logic;
ap_oscalar_6_ack : out std_logic;
ap_oscalar_7_ack : out std_logic;
ap_oscalar_8_ack : out std_logic;
ap_oscalar_9_ack : out std_logic;
ap_oscalar_10_ack : out std_logic;
ap_oscalar_11_ack : out std_logic;
ap_oscalar_12_ack : out std_logic;
ap_oscalar_13_ack : out std_logic;
ap_oscalar_14_ack : out std_logic;
ap_oscalar_15_ack : out std_logic;
---
interrupt : out std_logic);
end entity;
architecture rtl of axis_accelerator_adapter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
-- Constant declaration
constant C_S_AXIS_TSTRB_WIDTH : integer := C_S_AXIS_TDATA_WIDTH/8;
constant C_S_AXIS_TKEEP_WIDTH : integer := C_S_AXIS_TDATA_WIDTH/8;
constant C_M_AXIS_TSTRB_WIDTH : integer := C_M_AXIS_TDATA_WIDTH/8;
constant C_M_AXIS_TKEEP_WIDTH : integer := C_M_AXIS_TDATA_WIDTH/8;
constant C_MAX_SCALAR_DWIDTH : integer := 32;
constant C_MAX_ARG_DWIDTH : integer := 1024;
constant C_MAX_ARG_SWIDTH : integer := 16; -- Strobe width
constant C_MAX_ARG_AWIDTH : integer := 16;
constant C_MAX_ARG_N_DIM : integer := 4;
constant C_MAX_MB_DEPTH : integer := 8;
constant C_MAX_N_IARGS : integer := 8;
constant C_MAX_N_OARGS : integer := 8;
constant C_MAX_N_ISCALARS : integer := 8;
constant C_MAX_N_OSCALARS : integer := 8;
constant C_MAX_N_IOSCALARS : integer := 8;
constant C_MTBF_STAGES : integer := 4;
-------------------------
-- Scaler Data Width
-------------------------
-- GENERIC GROUPING: INPUT ARGUMENTS:
function calc_iarg_dwidth return std_logic_vector is
variable value : std_logic_vector(C_MAX_N_IARGS*32-1 downto 0) := (others => '0');
begin
value(32*(0+1)-1 downto 32*0) := int2lv(C_AP_IARG_0_DWIDTH);
value(32*(1+1)-1 downto 32*1) := int2lv(C_AP_IARG_1_DWIDTH);
value(32*(2+1)-1 downto 32*2) := int2lv(C_AP_IARG_2_DWIDTH);
value(32*(3+1)-1 downto 32*3) := int2lv(C_AP_IARG_3_DWIDTH);
value(32*(4+1)-1 downto 32*4) := int2lv(C_AP_IARG_4_DWIDTH);
value(32*(5+1)-1 downto 32*5) := int2lv(C_AP_IARG_5_DWIDTH);
value(32*(6+1)-1 downto 32*6) := int2lv(C_AP_IARG_6_DWIDTH);
value(32*(7+1)-1 downto 32*7) := int2lv(C_AP_IARG_7_DWIDTH);
return value;
end function calc_iarg_dwidth;
---------------------------------------------------------
-- GENERIC GROUPING: OUTPUT ARGUMENTS
function calc_oarg_dwidth return std_logic_vector is
variable value : std_logic_vector(C_MAX_N_OARGS*32-1 downto 0) := (others => '0');
begin
value(32*(0+1)-1 downto 32*0) := int2lv(C_AP_OARG_0_DWIDTH);
value(32*(1+1)-1 downto 32*1) := int2lv(C_AP_OARG_1_DWIDTH);
value(32*(2+1)-1 downto 32*2) := int2lv(C_AP_OARG_2_DWIDTH);
value(32*(3+1)-1 downto 32*3) := int2lv(C_AP_OARG_3_DWIDTH);
value(32*(4+1)-1 downto 32*4) := int2lv(C_AP_OARG_4_DWIDTH);
value(32*(5+1)-1 downto 32*5) := int2lv(C_AP_OARG_5_DWIDTH);
value(32*(6+1)-1 downto 32*6) := int2lv(C_AP_OARG_6_DWIDTH);
value(32*(7+1)-1 downto 32*7) := int2lv(C_AP_OARG_7_DWIDTH);
return value;
end function calc_oarg_dwidth;
-------------------------
-- BRAM PRIMITIVE TYPE
-- 7_SERIES : RAMB36E1, ULRASCALE : RAMB36E2
-------------------------
function calc_bram_type return string is
begin
if (C_FAMILY = "virtexu" or C_FAMILY = "kintexu" or C_FAMILY = "artixu" or C_FAMILY = "virtexuplus" or C_FAMILY = "kintexuplus" or C_FAMILY = "zynquplus") then
return "ULTRASCALE";
else
return "7_SERIES";
end if ;
end function calc_bram_type;
constant BRAM_PRIMITIVE_TYPE : string := calc_bram_type;
constant C_AP_OARG_DWIDTH : std_logic_vector(C_MAX_N_OARGS*32-1 downto 0) := calc_oarg_dwidth;
constant C_AP_IARG_DWIDTH : std_logic_vector(C_MAX_N_IARGS*32-1 downto 0) := calc_iarg_dwidth;
-- SUPERBUSSES DECLARATION:
signal s_axis_aclk_i : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_aresetn_i : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_tvalid : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_tready : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_tdata : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TDATA_WIDTH-1 downto 0);
signal s_axis_tstrb : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TSTRB_WIDTH-1 downto 0);
signal s_axis_tkeep : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TKEEP_WIDTH-1 downto 0);
signal s_axis_tlast : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_tid : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TID_WIDTH-1 downto 0);
signal s_axis_tdest : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TDEST_WIDTH-1 downto 0);
signal s_axis_tuser : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TUSER_WIDTH-1 downto 0);
signal m_axis_aclk_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_aresetn_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_tvalid : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_tready : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_tdata : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDATA_WIDTH-1 downto 0);
signal m_axis_tstrb : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TSTRB_WIDTH-1 downto 0);
signal m_axis_tkeep : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TKEEP_WIDTH-1 downto 0);
signal m_axis_tlast : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_tid : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TID_WIDTH-1 downto 0);
signal m_axis_tdest : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0);
signal m_axis_tuser : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TUSER_WIDTH-1 downto 0);
signal ap_iarg_addr : std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_AWIDTH-1 downto 0);
signal ap_iarg_ce : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_iarg_we : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_iarg_din : std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_iarg_dout : std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_oarg_addr : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_AWIDTH-1 downto 0);
signal ap_oarg_ce : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal ap_oarg_we : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal ap_oarg_din : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_oarg_dout : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
-------------------------------------------------------
constant AP_IARG_0_OFFSET : integer := log2(C_AP_IARG_0_DWIDTH/8);
constant AP_IARG_1_OFFSET : integer := log2(C_AP_IARG_1_DWIDTH/8);
constant AP_IARG_2_OFFSET : integer := log2(C_AP_IARG_2_DWIDTH/8);
constant AP_IARG_3_OFFSET : integer := log2(C_AP_IARG_3_DWIDTH/8);
constant AP_IARG_4_OFFSET : integer := log2(C_AP_IARG_4_DWIDTH/8);
constant AP_IARG_5_OFFSET : integer := log2(C_AP_IARG_5_DWIDTH/8);
constant AP_IARG_6_OFFSET : integer := log2(C_AP_IARG_6_DWIDTH/8);
constant AP_IARG_7_OFFSET : integer := log2(C_AP_IARG_7_DWIDTH/8);
constant AP_OARG_0_OFFSET : integer := log2(C_AP_OARG_0_DWIDTH/8);
constant AP_OARG_1_OFFSET : integer := log2(C_AP_OARG_1_DWIDTH/8);
constant AP_OARG_2_OFFSET : integer := log2(C_AP_OARG_2_DWIDTH/8);
constant AP_OARG_3_OFFSET : integer := log2(C_AP_OARG_3_DWIDTH/8);
constant AP_OARG_4_OFFSET : integer := log2(C_AP_OARG_4_DWIDTH/8);
constant AP_OARG_5_OFFSET : integer := log2(C_AP_OARG_5_DWIDTH/8);
constant AP_OARG_6_OFFSET : integer := log2(C_AP_OARG_6_DWIDTH/8);
constant AP_OARG_7_OFFSET : integer := log2(C_AP_OARG_7_DWIDTH/8);
-------------------------------------------------
signal ap_fifo_iarg_dout : std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_fifo_iarg_read : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_fifo_iarg_empty_n : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_fifo_oarg_din : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_fifo_oarg_write : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal ap_fifo_oarg_full_n : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
-------------------------------------------------
-- Scaler signals
signal ap_iscalar_dout_i : std_logic_vector(511 downto 0);
signal ap_oscalar_din_i : std_logic_vector(511 downto 0);
signal ap_oscalar_din_int : std_logic_vector(C_AP_OSCALAR_DIN_WIDTH-1 downto 0);
signal ap_ioscalar_din_int : std_logic_vector(C_AP_OSCALAR_IO_DIN_WIDTH-1 downto 0);
signal ap_oscalar_vld_i : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
signal ap_iscalar_vld_i : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
signal ap_oscalar_ack_i : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
signal ap_iscalar_ack_i : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
signal zeros1 : std_logic_vector(256-C_AP_OSCALAR_DIN_WIDTH-1 downto 0);
signal zeros256 : std_logic_vector(255 downto 0);
begin
zeros1 <= (others => '0');
zeros256 <= (others => '0');
----------------------------------------------
-- Scalar signals assignments
----------------------------------------------
ap_oscalar_vld_i <= ap_oscalar_15_vld & ap_oscalar_14_vld & ap_oscalar_13_vld &
ap_oscalar_12_vld & ap_oscalar_11_vld & ap_oscalar_10_vld &
ap_oscalar_9_vld & ap_oscalar_8_vld & ap_oscalar_7_vld &
ap_oscalar_6_vld & ap_oscalar_5_vld & ap_oscalar_4_vld &
ap_oscalar_3_vld & ap_oscalar_2_vld & ap_oscalar_1_vld &
ap_oscalar_0_vld;
ap_iscalar_ack_i <= ap_iscalar_15_ack & ap_iscalar_14_ack & ap_iscalar_13_ack &
ap_iscalar_12_ack & ap_iscalar_11_ack & ap_iscalar_10_ack &
ap_iscalar_9_ack & ap_iscalar_8_ack & ap_iscalar_7_ack &
ap_iscalar_6_ack & ap_iscalar_5_ack & ap_iscalar_4_ack &
ap_iscalar_3_ack & ap_iscalar_2_ack & ap_iscalar_1_ack &
ap_iscalar_0_ack;
-- Output scalar ack generation
ap_oscalar_0_ack <= ap_oscalar_ack_i(0);
ap_oscalar_1_ack <= ap_oscalar_ack_i(1);
ap_oscalar_2_ack <= ap_oscalar_ack_i(2);
ap_oscalar_3_ack <= ap_oscalar_ack_i(3);
ap_oscalar_4_ack <= ap_oscalar_ack_i(4);
ap_oscalar_5_ack <= ap_oscalar_ack_i(5);
ap_oscalar_6_ack <= ap_oscalar_ack_i(6);
ap_oscalar_7_ack <= ap_oscalar_ack_i(7);
ap_oscalar_8_ack <= ap_oscalar_ack_i(8);
ap_oscalar_9_ack <= ap_oscalar_ack_i(9);
ap_oscalar_10_ack <= ap_oscalar_ack_i(10);
ap_oscalar_11_ack <= ap_oscalar_ack_i(11);
ap_oscalar_12_ack <= ap_oscalar_ack_i(12);
ap_oscalar_13_ack <= ap_oscalar_ack_i(13);
ap_oscalar_14_ack <= ap_oscalar_ack_i(14);
ap_oscalar_15_ack <= ap_oscalar_ack_i(15);
-- input scalar valid generation
ap_iscalar_0_vld <= ap_iscalar_vld_i(0);
ap_iscalar_1_vld <= ap_iscalar_vld_i(1);
ap_iscalar_2_vld <= ap_iscalar_vld_i(2);
ap_iscalar_3_vld <= ap_iscalar_vld_i(3);
ap_iscalar_4_vld <= ap_iscalar_vld_i(4);
ap_iscalar_5_vld <= ap_iscalar_vld_i(5);
ap_iscalar_6_vld <= ap_iscalar_vld_i(6);
ap_iscalar_7_vld <= ap_iscalar_vld_i(7);
ap_iscalar_8_vld <= ap_iscalar_vld_i(8);
ap_iscalar_9_vld <= ap_iscalar_vld_i(9);
ap_iscalar_10_vld <= ap_iscalar_vld_i(10);
ap_iscalar_11_vld <= ap_iscalar_vld_i(11);
ap_iscalar_12_vld <= ap_iscalar_vld_i(12);
ap_iscalar_13_vld <= ap_iscalar_vld_i(13);
ap_iscalar_14_vld <= ap_iscalar_vld_i(14);
ap_iscalar_15_vld <= ap_iscalar_vld_i(15);
----------------------------------------------
-- Output Scalar signals assignments
----------------------------------------------
OSCALER_0_GEN : if (C_N_OUTPUT_SCALARS = 0) generate
begin
ap_oscalar_din_int <= (others=>'0');
end generate OSCALER_0_GEN;
OSCALER_1_GEN : if (C_N_OUTPUT_SCALARS = 1) generate
begin
ap_oscalar_din_int <= ap_oscalar_0_din;
end generate OSCALER_1_GEN;
OSCALER_2_GEN : if (C_N_OUTPUT_SCALARS = 2) generate
begin
ap_oscalar_din_int <= ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_2_GEN;
OSCALER_3_GEN : if (C_N_OUTPUT_SCALARS = 3) generate
begin
ap_oscalar_din_int <= ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_3_GEN;
OSCALER_4_GEN : if (C_N_OUTPUT_SCALARS = 4) generate
begin
ap_oscalar_din_int <= ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_4_GEN;
OSCALER_5_GEN : if (C_N_OUTPUT_SCALARS = 5) generate
begin
ap_oscalar_din_int <= ap_oscalar_4_din & ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_5_GEN;
OSCALER_6_GEN : if (C_N_OUTPUT_SCALARS = 6) generate
begin
ap_oscalar_din_int <= ap_oscalar_5_din & ap_oscalar_4_din & ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_6_GEN;
OSCALER_7_GEN : if (C_N_OUTPUT_SCALARS = 7) generate
begin
ap_oscalar_din_int <= ap_oscalar_6_din & ap_oscalar_5_din & ap_oscalar_4_din & ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_7_GEN;
OSCALER_8_GEN : if (C_N_OUTPUT_SCALARS = 8) generate
begin
ap_oscalar_din_int <= ap_oscalar_7_din & ap_oscalar_6_din & ap_oscalar_5_din & ap_oscalar_4_din & ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_8_GEN;
IOSCALER_0_GEN : if (C_N_INOUT_SCALARS = 0) generate
begin
ap_ioscalar_din_int <= (others=>'0');
end generate IOSCALER_0_GEN;
OSCALER_9_GEN : if (C_N_INOUT_SCALARS = 1) generate
begin
ap_ioscalar_din_int <= ap_oscalar_8_din;
end generate OSCALER_9_GEN;
OSCALER_10_GEN : if (C_N_INOUT_SCALARS = 2) generate
begin
ap_ioscalar_din_int <= ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_10_GEN;
OSCALER_11_GEN : if (C_N_INOUT_SCALARS = 3) generate
begin
ap_ioscalar_din_int <= ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_11_GEN;
OSCALER_12_GEN : if (C_N_INOUT_SCALARS = 4) generate
begin
ap_ioscalar_din_int <= ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_12_GEN;
OSCALER_13_GEN : if (C_N_INOUT_SCALARS = 5) generate
begin
ap_ioscalar_din_int <= ap_oscalar_12_din & ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_13_GEN;
OSCALER_14_GEN : if (C_N_INOUT_SCALARS = 6) generate
begin
ap_ioscalar_din_int <= ap_oscalar_13_din & ap_oscalar_12_din & ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_14_GEN;
OSCALER_15_GEN : if (C_N_INOUT_SCALARS = 7) generate
begin
ap_ioscalar_din_int <= ap_oscalar_14_din & ap_oscalar_13_din & ap_oscalar_12_din & ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_15_GEN;
OSCALER_16_GEN : if (C_N_INOUT_SCALARS = 8) generate
begin
ap_ioscalar_din_int <= ap_oscalar_15_din & ap_oscalar_14_din & ap_oscalar_13_din & ap_oscalar_12_din & ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_16_GEN;
OSCALER_GEN_1 : if (C_N_INOUT_SCALARS > 0 and C_N_OUTPUT_SCALARS > 0) generate
begin
ap_oscalar_din_i(256+C_AP_OSCALAR_IO_DIN_WIDTH-1 downto 0) <= ap_ioscalar_din_int & zeros1 & ap_oscalar_din_int;
OSCALER_ZERO_GEN_1 : if (C_AP_OSCALAR_IO_DIN_WIDTH < 256 ) generate
ap_oscalar_din_i(511 downto 256+C_AP_OSCALAR_IO_DIN_WIDTH) <= (others =>'0') ;
end generate OSCALER_ZERO_GEN_1;
end generate OSCALER_GEN_1;
OSCALER_GEN_2 : if (C_N_INOUT_SCALARS = 0 and C_N_OUTPUT_SCALARS > 0) generate
begin
ap_oscalar_din_i(C_AP_OSCALAR_DIN_WIDTH-1 downto 0) <= ap_oscalar_din_int;
ap_oscalar_din_i(511 downto C_AP_OSCALAR_DIN_WIDTH) <= (others => '0');
end generate OSCALER_GEN_2;
OSCALER_GEN_3 : if (C_N_INOUT_SCALARS > 0 and C_N_OUTPUT_SCALARS = 0) generate
begin
ap_oscalar_din_i(256+C_AP_OSCALAR_IO_DIN_WIDTH-1 downto 0) <= ap_ioscalar_din_int & zeros256 ;
OSCALER_ZERO_GEN_3 : if (C_AP_OSCALAR_IO_DIN_WIDTH < 256 ) generate
ap_oscalar_din_i(511 downto 256+C_AP_OSCALAR_IO_DIN_WIDTH) <= (others =>'0') ;
end generate OSCALER_ZERO_GEN_3;
end generate OSCALER_GEN_3;
OSCALER_GEN_4 : if (C_N_INOUT_SCALARS = 0 and C_N_OUTPUT_SCALARS = 0) generate
begin
ap_oscalar_din_i <= (others => '0');
end generate OSCALER_GEN_4;
----------------------------------------------
-- Input Scalar signals assignments
----------------------------------------------
ISCALER_1_GEN : if (C_N_INPUT_SCALARS > 0) generate
begin
ap_iscalar_0_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 0)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 0)));
end generate ISCALER_1_GEN;
ISCALER_2_GEN : if (C_N_INPUT_SCALARS > 1) generate
begin
ap_iscalar_1_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 1)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 1)));
end generate ISCALER_2_GEN;
ISCALER_3_GEN : if (C_N_INPUT_SCALARS > 2) generate
begin
ap_iscalar_2_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 2)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 2)));
end generate ISCALER_3_GEN;
ISCALER_4_GEN : if (C_N_INPUT_SCALARS > 3) generate
begin
ap_iscalar_3_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 3)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 3)));
end generate ISCALER_4_GEN;
ISCALER_5_GEN : if (C_N_INPUT_SCALARS > 4) generate
begin
ap_iscalar_4_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 4)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 4)));
end generate ISCALER_5_GEN;
ISCALER_6_GEN : if (C_N_INPUT_SCALARS > 5) generate
begin
ap_iscalar_5_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 5)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 5)));
end generate ISCALER_6_GEN;
ISCALER_7_GEN : if (C_N_INPUT_SCALARS > 6) generate
begin
ap_iscalar_6_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 6)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 6)));
end generate ISCALER_7_GEN;
ISCALER_8_GEN : if (C_N_INPUT_SCALARS > 7) generate
begin
ap_iscalar_7_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 7)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 7)));
end generate ISCALER_8_GEN;
ISCALER_9_GEN : if (C_N_INOUT_SCALARS > 0) generate
begin
ap_iscalar_8_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 8)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 8)));
end generate ISCALER_9_GEN;
ISCALER_10_GEN : if (C_N_INOUT_SCALARS > 1) generate
begin
ap_iscalar_9_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 9)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 9)));
end generate ISCALER_10_GEN;
ISCALER_11_GEN : if (C_N_INOUT_SCALARS > 2) generate
begin
ap_iscalar_10_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 10)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 10)));
end generate ISCALER_11_GEN;
ISCALER_12_GEN : if (C_N_INOUT_SCALARS > 3) generate
begin
ap_iscalar_11_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 11)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 11)));
end generate ISCALER_12_GEN;
ISCALER_13_GEN : if (C_N_INOUT_SCALARS > 4) generate
begin
ap_iscalar_12_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 12)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 12)));
end generate ISCALER_13_GEN;
ISCALER_14_GEN : if (C_N_INOUT_SCALARS > 5) generate
begin
ap_iscalar_13_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 13)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 13)));
end generate ISCALER_14_GEN;
ISCALER_15_GEN : if (C_N_INOUT_SCALARS > 6) generate
begin
ap_iscalar_14_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 14)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 14)));
end generate ISCALER_15_GEN;
ISCALER_16_GEN : if (C_N_INOUT_SCALARS > 7) generate
begin
ap_iscalar_15_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 15)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 15)));
end generate ISCALER_16_GEN;
-----------------------------------------------------------------------------------------
-- AXI4-Stream Slave interface signal Generation
-- Single stremaing clock and reset port exposed to user. Asynchronous clocks between the
-- different streaming channel not supported
-----------------------------------------------------------------------------------------
SINGLE_CLK_RST_GEN : if (C_ENABLE_STREAM_CLK = 0) generate
s_axis_aclk_i(0) <= s_axis_aclk;
s_axis_aclk_i(1) <= s_axis_aclk;
s_axis_aclk_i(2) <= s_axis_aclk;
s_axis_aclk_i(3) <= s_axis_aclk;
s_axis_aclk_i(4) <= s_axis_aclk;
s_axis_aclk_i(5) <= s_axis_aclk;
s_axis_aclk_i(6) <= s_axis_aclk;
s_axis_aclk_i(7) <= s_axis_aclk;
s_axis_aresetn_i(0) <= s_axis_aresetn;
s_axis_aresetn_i(1) <= s_axis_aresetn;
s_axis_aresetn_i(2) <= s_axis_aresetn;
s_axis_aresetn_i(3) <= s_axis_aresetn;
s_axis_aresetn_i(4) <= s_axis_aresetn;
s_axis_aresetn_i(5) <= s_axis_aresetn;
s_axis_aresetn_i(6) <= s_axis_aresetn;
s_axis_aresetn_i(7) <= s_axis_aresetn;
m_axis_aclk_i(0) <= m_axis_aclk;
m_axis_aclk_i(1) <= m_axis_aclk;
m_axis_aclk_i(2) <= m_axis_aclk;
m_axis_aclk_i(3) <= m_axis_aclk;
m_axis_aclk_i(4) <= m_axis_aclk;
m_axis_aclk_i(5) <= m_axis_aclk;
m_axis_aclk_i(6) <= m_axis_aclk;
m_axis_aclk_i(7) <= m_axis_aclk;
m_axis_aresetn_i(0) <= m_axis_aresetn;
m_axis_aresetn_i(1) <= m_axis_aresetn;
m_axis_aresetn_i(2) <= m_axis_aresetn;
m_axis_aresetn_i(3) <= m_axis_aresetn;
m_axis_aresetn_i(4) <= m_axis_aresetn;
m_axis_aresetn_i(5) <= m_axis_aresetn;
m_axis_aresetn_i(6) <= m_axis_aresetn;
m_axis_aresetn_i(7) <= m_axis_aresetn;
end generate SINGLE_CLK_RST_GEN;
-----------------------------------------------------------------------------------------
-- AXI4-Stream Slave interface signal Generation
-- Asynchronous clocks between the different streaming channel supported
-----------------------------------------------------------------------------------------
ASYNC_CLK_RST_GEN : if (C_ENABLE_STREAM_CLK = 1) generate
s_axis_aclk_i(0) <= s_axis_0_aclk;
s_axis_aclk_i(1) <= s_axis_1_aclk;
s_axis_aclk_i(2) <= s_axis_2_aclk;
s_axis_aclk_i(3) <= s_axis_3_aclk;
s_axis_aclk_i(4) <= s_axis_4_aclk;
s_axis_aclk_i(5) <= s_axis_5_aclk;
s_axis_aclk_i(6) <= s_axis_6_aclk;
s_axis_aclk_i(7) <= s_axis_7_aclk;
s_axis_aresetn_i(0) <= s_axis_0_aresetn;
s_axis_aresetn_i(1) <= s_axis_1_aresetn;
s_axis_aresetn_i(2) <= s_axis_2_aresetn;
s_axis_aresetn_i(3) <= s_axis_3_aresetn;
s_axis_aresetn_i(4) <= s_axis_4_aresetn;
s_axis_aresetn_i(5) <= s_axis_5_aresetn;
s_axis_aresetn_i(6) <= s_axis_6_aresetn;
s_axis_aresetn_i(7) <= s_axis_7_aresetn;
m_axis_aclk_i(0) <= m_axis_0_aclk;
m_axis_aclk_i(1) <= m_axis_1_aclk;
m_axis_aclk_i(2) <= m_axis_2_aclk;
m_axis_aclk_i(3) <= m_axis_3_aclk;
m_axis_aclk_i(4) <= m_axis_4_aclk;
m_axis_aclk_i(5) <= m_axis_5_aclk;
m_axis_aclk_i(6) <= m_axis_6_aclk;
m_axis_aclk_i(7) <= m_axis_7_aclk;
m_axis_aresetn_i(0) <= m_axis_0_aresetn;
m_axis_aresetn_i(1) <= m_axis_1_aresetn;
m_axis_aresetn_i(2) <= m_axis_2_aresetn;
m_axis_aresetn_i(3) <= m_axis_3_aresetn;
m_axis_aresetn_i(4) <= m_axis_4_aresetn;
m_axis_aresetn_i(5) <= m_axis_5_aresetn;
m_axis_aresetn_i(6) <= m_axis_6_aresetn;
m_axis_aresetn_i(7) <= m_axis_7_aresetn;
end generate ASYNC_CLK_RST_GEN;
-------------------------------------------------------------------------------------------------
-- Assiging default value '1' when TSTRB and TKEEP signals are not present in the Input stream.
-- When Input stream STROBE and KEEP are available, no need to drive default values.
-- This is work around to resolve the Vivado wrapper issue which does not drive default input '1'
-- properly when signla widht is less than 4 bits.
-------------------------------------------------------------------------------------------------
EN_TSTRB_GEN : if (C_S_AXIS_HAS_TSTRB = 1) generate
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(0+1)-1 downto C_S_AXIS_TSTRB_WIDTH*0) <= s_axis_0_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(1+1)-1 downto C_S_AXIS_TSTRB_WIDTH*1) <= s_axis_1_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(2+1)-1 downto C_S_AXIS_TSTRB_WIDTH*2) <= s_axis_2_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(3+1)-1 downto C_S_AXIS_TSTRB_WIDTH*3) <= s_axis_3_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(4+1)-1 downto C_S_AXIS_TSTRB_WIDTH*4) <= s_axis_4_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(5+1)-1 downto C_S_AXIS_TSTRB_WIDTH*5) <= s_axis_5_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(6+1)-1 downto C_S_AXIS_TSTRB_WIDTH*6) <= s_axis_6_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(7+1)-1 downto C_S_AXIS_TSTRB_WIDTH*7) <= s_axis_7_tstrb;
end generate EN_TSTRB_GEN;
NO_TSTRB_GEN : if (C_S_AXIS_HAS_TSTRB = 0) generate
s_axis_tstrb <= (others => '1') ;
end generate NO_TSTRB_GEN;
-- TKEEP generation
EN_TKEEP_GEN : if (C_S_AXIS_HAS_TKEEP = 1) generate
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(0+1)-1 downto C_S_AXIS_TKEEP_WIDTH*0) <= s_axis_0_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(1+1)-1 downto C_S_AXIS_TKEEP_WIDTH*1) <= s_axis_1_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(2+1)-1 downto C_S_AXIS_TKEEP_WIDTH*2) <= s_axis_2_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(3+1)-1 downto C_S_AXIS_TKEEP_WIDTH*3) <= s_axis_3_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(4+1)-1 downto C_S_AXIS_TKEEP_WIDTH*4) <= s_axis_4_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(5+1)-1 downto C_S_AXIS_TKEEP_WIDTH*5) <= s_axis_5_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(6+1)-1 downto C_S_AXIS_TKEEP_WIDTH*6) <= s_axis_6_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(7+1)-1 downto C_S_AXIS_TKEEP_WIDTH*7) <= s_axis_7_tkeep;
end generate EN_TKEEP_GEN;
NO_TKEEP_GEN : if (C_S_AXIS_HAS_TKEEP = 0) generate
s_axis_tkeep <= (others => '1') ;
end generate NO_TKEEP_GEN;
-----------------------------------------------------------------------------------------
-- AXI4-Stream Slave interface signal Generation
-- SUPERBUSES BUILDING: SLAVE AXI STREAMS (INPUT ARGUMENTS):
-- NOTE FOR SIMULATION: This concatenation inserts a delta delay for clocks signals. In
-- the case of input signals causality is preserved becouse another delta delay is
-- inserted during their concatenation. For input signals, there is no problem
-----------------------------------------------------------------------------------------
--AXI4-Stream slave interface TVALID generation
s_axis_tvalid(0) <= s_axis_0_tvalid;
s_axis_tvalid(1) <= s_axis_1_tvalid;
s_axis_tvalid(2) <= s_axis_2_tvalid;
s_axis_tvalid(3) <= s_axis_3_tvalid;
s_axis_tvalid(4) <= s_axis_4_tvalid;
s_axis_tvalid(5) <= s_axis_5_tvalid;
s_axis_tvalid(6) <= s_axis_6_tvalid;
s_axis_tvalid(7) <= s_axis_7_tvalid;
--AXI4-Stream slave interface TREADY generation
s_axis_0_tready <= s_axis_tready(0);
s_axis_1_tready <= s_axis_tready(1);
s_axis_2_tready <= s_axis_tready(2);
s_axis_3_tready <= s_axis_tready(3);
s_axis_4_tready <= s_axis_tready(4);
s_axis_5_tready <= s_axis_tready(5);
s_axis_6_tready <= s_axis_tready(6);
s_axis_7_tready <= s_axis_tready(7);
--AXI4-Stream slave interface TDATA generation
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(0+1)-1 downto C_S_AXIS_TDATA_WIDTH*0) <= s_axis_0_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(1+1)-1 downto C_S_AXIS_TDATA_WIDTH*1) <= s_axis_1_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(2+1)-1 downto C_S_AXIS_TDATA_WIDTH*2) <= s_axis_2_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(3+1)-1 downto C_S_AXIS_TDATA_WIDTH*3) <= s_axis_3_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(4+1)-1 downto C_S_AXIS_TDATA_WIDTH*4) <= s_axis_4_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(5+1)-1 downto C_S_AXIS_TDATA_WIDTH*5) <= s_axis_5_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(6+1)-1 downto C_S_AXIS_TDATA_WIDTH*6) <= s_axis_6_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(7+1)-1 downto C_S_AXIS_TDATA_WIDTH*7) <= s_axis_7_tdata;
--AXI4-Stream slave interface TLAST generation
s_axis_tlast(0) <= s_axis_0_tlast;
s_axis_tlast(1) <= s_axis_1_tlast;
s_axis_tlast(2) <= s_axis_2_tlast;
s_axis_tlast(3) <= s_axis_3_tlast;
s_axis_tlast(4) <= s_axis_4_tlast;
s_axis_tlast(5) <= s_axis_5_tlast;
s_axis_tlast(6) <= s_axis_6_tlast;
s_axis_tlast(7) <= s_axis_7_tlast;
--AXI4-Stream slave interface TID generation
s_axis_tid(C_S_AXIS_TID_WIDTH*(0+1)-1 downto C_S_AXIS_TID_WIDTH*0) <= s_axis_0_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(1+1)-1 downto C_S_AXIS_TID_WIDTH*1) <= s_axis_1_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(2+1)-1 downto C_S_AXIS_TID_WIDTH*2) <= s_axis_2_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(3+1)-1 downto C_S_AXIS_TID_WIDTH*3) <= s_axis_3_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(4+1)-1 downto C_S_AXIS_TID_WIDTH*4) <= s_axis_4_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(5+1)-1 downto C_S_AXIS_TID_WIDTH*5) <= s_axis_5_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(6+1)-1 downto C_S_AXIS_TID_WIDTH*6) <= s_axis_6_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(7+1)-1 downto C_S_AXIS_TID_WIDTH*7) <= s_axis_7_tid;
--AXI4-Stream slave interface TDEST generation
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(0+1)-1 downto C_S_AXIS_TDEST_WIDTH*0) <= s_axis_0_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(1+1)-1 downto C_S_AXIS_TDEST_WIDTH*1) <= s_axis_1_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(2+1)-1 downto C_S_AXIS_TDEST_WIDTH*2) <= s_axis_2_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(3+1)-1 downto C_S_AXIS_TDEST_WIDTH*3) <= s_axis_3_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(4+1)-1 downto C_S_AXIS_TDEST_WIDTH*4) <= s_axis_4_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(5+1)-1 downto C_S_AXIS_TDEST_WIDTH*5) <= s_axis_5_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(6+1)-1 downto C_S_AXIS_TDEST_WIDTH*6) <= s_axis_6_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(7+1)-1 downto C_S_AXIS_TDEST_WIDTH*7) <= s_axis_7_tdest;
--AXI4-Stream slave interface TUSER generation
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(0+1)-1 downto C_S_AXIS_TUSER_WIDTH*0) <= s_axis_0_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(1+1)-1 downto C_S_AXIS_TUSER_WIDTH*1) <= s_axis_1_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(2+1)-1 downto C_S_AXIS_TUSER_WIDTH*2) <= s_axis_2_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(3+1)-1 downto C_S_AXIS_TUSER_WIDTH*3) <= s_axis_3_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(4+1)-1 downto C_S_AXIS_TUSER_WIDTH*4) <= s_axis_4_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(5+1)-1 downto C_S_AXIS_TUSER_WIDTH*5) <= s_axis_5_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(6+1)-1 downto C_S_AXIS_TUSER_WIDTH*6) <= s_axis_6_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(7+1)-1 downto C_S_AXIS_TUSER_WIDTH*7) <= s_axis_7_tuser;
-----------------------------------------------------------------------------------------
-- Accelerator Input Argument interface signal Generation
-- SUPERBUSES BUILDING: AP INPUT ARGUMENTS:
-----------------------------------------------------------------------------------------
-- Input Argument BRAM interface addr generation
ap_iarg_addr(C_MAX_ARG_AWIDTH*(0+1)-1 downto C_MAX_ARG_AWIDTH*0) <= ap_iarg_0_addr(C_MAX_ARG_AWIDTH+AP_IARG_0_OFFSET-1 downto AP_IARG_0_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(1+1)-1 downto C_MAX_ARG_AWIDTH*1) <= ap_iarg_1_addr(C_MAX_ARG_AWIDTH+AP_IARG_1_OFFSET-1 downto AP_IARG_1_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(2+1)-1 downto C_MAX_ARG_AWIDTH*2) <= ap_iarg_2_addr(C_MAX_ARG_AWIDTH+AP_IARG_2_OFFSET-1 downto AP_IARG_2_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(3+1)-1 downto C_MAX_ARG_AWIDTH*3) <= ap_iarg_3_addr(C_MAX_ARG_AWIDTH+AP_IARG_3_OFFSET-1 downto AP_IARG_3_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(4+1)-1 downto C_MAX_ARG_AWIDTH*4) <= ap_iarg_4_addr(C_MAX_ARG_AWIDTH+AP_IARG_4_OFFSET-1 downto AP_IARG_4_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(5+1)-1 downto C_MAX_ARG_AWIDTH*5) <= ap_iarg_5_addr(C_MAX_ARG_AWIDTH+AP_IARG_5_OFFSET-1 downto AP_IARG_5_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(6+1)-1 downto C_MAX_ARG_AWIDTH*6) <= ap_iarg_6_addr(C_MAX_ARG_AWIDTH+AP_IARG_6_OFFSET-1 downto AP_IARG_6_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(7+1)-1 downto C_MAX_ARG_AWIDTH*7) <= ap_iarg_7_addr(C_MAX_ARG_AWIDTH+AP_IARG_7_OFFSET-1 downto AP_IARG_7_OFFSET);
-- Input Argument BRAM interface ce generation
ap_iarg_ce(0) <= ap_iarg_0_ce;
ap_iarg_ce(1) <= ap_iarg_1_ce;
ap_iarg_ce(2) <= ap_iarg_2_ce;
ap_iarg_ce(3) <= ap_iarg_3_ce;
ap_iarg_ce(4) <= ap_iarg_4_ce;
ap_iarg_ce(5) <= ap_iarg_5_ce;
ap_iarg_ce(6) <= ap_iarg_6_ce;
ap_iarg_ce(7) <= ap_iarg_7_ce;
-- Input Argument BRAM interface we generation
ap_iarg_we(0) <= ap_iarg_0_we(0);
ap_iarg_we(1) <= ap_iarg_1_we(0);
ap_iarg_we(2) <= ap_iarg_2_we(0);
ap_iarg_we(3) <= ap_iarg_3_we(0);
ap_iarg_we(4) <= ap_iarg_4_we(0);
ap_iarg_we(5) <= ap_iarg_5_we(0);
ap_iarg_we(6) <= ap_iarg_6_we(0);
ap_iarg_we(7) <= ap_iarg_7_we(0);
-- Input Argument BRAM interface din generation
ap_iarg_din(C_MAX_ARG_DWIDTH*(0+1)-1 downto C_MAX_ARG_DWIDTH*0) <= ext_lv(ap_iarg_0_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(1+1)-1 downto C_MAX_ARG_DWIDTH*1) <= ext_lv(ap_iarg_1_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(2+1)-1 downto C_MAX_ARG_DWIDTH*2) <= ext_lv(ap_iarg_2_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(3+1)-1 downto C_MAX_ARG_DWIDTH*3) <= ext_lv(ap_iarg_3_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(4+1)-1 downto C_MAX_ARG_DWIDTH*4) <= ext_lv(ap_iarg_4_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(5+1)-1 downto C_MAX_ARG_DWIDTH*5) <= ext_lv(ap_iarg_5_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(6+1)-1 downto C_MAX_ARG_DWIDTH*6) <= ext_lv(ap_iarg_6_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(7+1)-1 downto C_MAX_ARG_DWIDTH*7) <= ext_lv(ap_iarg_7_din, C_MAX_ARG_DWIDTH);
-- Input Argument BRAM interface dout generation
ap_iarg_0_dout <= ap_iarg_dout(C_AP_IARG_0_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_MAX_ARG_DWIDTH*0);
ap_iarg_1_dout <= ap_iarg_dout(C_AP_IARG_1_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_MAX_ARG_DWIDTH*1);
ap_iarg_2_dout <= ap_iarg_dout(C_AP_IARG_2_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_MAX_ARG_DWIDTH*2);
ap_iarg_3_dout <= ap_iarg_dout(C_AP_IARG_3_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_MAX_ARG_DWIDTH*3);
ap_iarg_4_dout <= ap_iarg_dout(C_AP_IARG_4_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_MAX_ARG_DWIDTH*4);
ap_iarg_5_dout <= ap_iarg_dout(C_AP_IARG_5_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_MAX_ARG_DWIDTH*5);
ap_iarg_6_dout <= ap_iarg_dout(C_AP_IARG_6_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_MAX_ARG_DWIDTH*6);
ap_iarg_7_dout <= ap_iarg_dout(C_AP_IARG_7_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_MAX_ARG_DWIDTH*7);
-- Input Argument FIFO interface dout generation
ap_fifo_iarg_0_dout <= ap_fifo_iarg_dout(C_AP_IARG_0_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_MAX_ARG_DWIDTH*0);
ap_fifo_iarg_1_dout <= ap_fifo_iarg_dout(C_AP_IARG_1_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_MAX_ARG_DWIDTH*1);
ap_fifo_iarg_2_dout <= ap_fifo_iarg_dout(C_AP_IARG_2_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_MAX_ARG_DWIDTH*2);
ap_fifo_iarg_3_dout <= ap_fifo_iarg_dout(C_AP_IARG_3_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_MAX_ARG_DWIDTH*3);
ap_fifo_iarg_4_dout <= ap_fifo_iarg_dout(C_AP_IARG_4_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_MAX_ARG_DWIDTH*4);
ap_fifo_iarg_5_dout <= ap_fifo_iarg_dout(C_AP_IARG_5_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_MAX_ARG_DWIDTH*5);
ap_fifo_iarg_6_dout <= ap_fifo_iarg_dout(C_AP_IARG_6_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_MAX_ARG_DWIDTH*6);
ap_fifo_iarg_7_dout <= ap_fifo_iarg_dout(C_AP_IARG_7_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_MAX_ARG_DWIDTH*7);
-- Input Argument FIFO interface read generation
ap_fifo_iarg_read(0) <= ap_fifo_iarg_0_read;
ap_fifo_iarg_read(1) <= ap_fifo_iarg_1_read;
ap_fifo_iarg_read(2) <= ap_fifo_iarg_2_read;
ap_fifo_iarg_read(3) <= ap_fifo_iarg_3_read;
ap_fifo_iarg_read(4) <= ap_fifo_iarg_4_read;
ap_fifo_iarg_read(5) <= ap_fifo_iarg_5_read;
ap_fifo_iarg_read(6) <= ap_fifo_iarg_6_read;
ap_fifo_iarg_read(7) <= ap_fifo_iarg_7_read;
-- Input Argument FIFO interface empty generation
ap_fifo_iarg_0_empty_n <= ap_fifo_iarg_empty_n(0);
ap_fifo_iarg_1_empty_n <= ap_fifo_iarg_empty_n(1);
ap_fifo_iarg_2_empty_n <= ap_fifo_iarg_empty_n(2);
ap_fifo_iarg_3_empty_n <= ap_fifo_iarg_empty_n(3);
ap_fifo_iarg_4_empty_n <= ap_fifo_iarg_empty_n(4);
ap_fifo_iarg_5_empty_n <= ap_fifo_iarg_empty_n(5);
ap_fifo_iarg_6_empty_n <= ap_fifo_iarg_empty_n(6);
ap_fifo_iarg_7_empty_n <= ap_fifo_iarg_empty_n(7);
-----------------------------------------------------------------------------------------
-- AXI4-Stream Slave interface signal Generation
-- SUPERBUSES BUILDING: MASTER AXI STREAMS (OUTPUT ARGUMENTS):
-- NOTE FOR SIMULATION: This concatenation inserts a delta delay for clocks signals. In
-- the case of input signals causality is preserved becouse another delta delay is
-- inserted during their concatenation. For input signals, there is no problem
-----------------------------------------------------------------------------------------
--AXI4-Stream master interface TVALID generation
m_axis_0_tvalid <= m_axis_tvalid(0);
m_axis_1_tvalid <= m_axis_tvalid(1);
m_axis_2_tvalid <= m_axis_tvalid(2);
m_axis_3_tvalid <= m_axis_tvalid(3);
m_axis_4_tvalid <= m_axis_tvalid(4);
m_axis_5_tvalid <= m_axis_tvalid(5);
m_axis_6_tvalid <= m_axis_tvalid(6);
m_axis_7_tvalid <= m_axis_tvalid(7);
--AXI4-Stream master interface TREADY generation
m_axis_tready(0) <= m_axis_0_tready;
m_axis_tready(1) <= m_axis_1_tready;
m_axis_tready(2) <= m_axis_2_tready;
m_axis_tready(3) <= m_axis_3_tready;
m_axis_tready(4) <= m_axis_4_tready;
m_axis_tready(5) <= m_axis_5_tready;
m_axis_tready(6) <= m_axis_6_tready;
m_axis_tready(7) <= m_axis_7_tready;
--AXI4-Stream master interface TDATA generation
m_axis_0_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(0+1)-1 downto C_M_AXIS_TDATA_WIDTH*0);
m_axis_1_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(1+1)-1 downto C_M_AXIS_TDATA_WIDTH*1);
m_axis_2_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(2+1)-1 downto C_M_AXIS_TDATA_WIDTH*2);
m_axis_3_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(3+1)-1 downto C_M_AXIS_TDATA_WIDTH*3);
m_axis_4_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(4+1)-1 downto C_M_AXIS_TDATA_WIDTH*4);
m_axis_5_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(5+1)-1 downto C_M_AXIS_TDATA_WIDTH*5);
m_axis_6_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(6+1)-1 downto C_M_AXIS_TDATA_WIDTH*6);
m_axis_7_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(7+1)-1 downto C_M_AXIS_TDATA_WIDTH*7);
--AXI4-Stream master interface TSTRB generation
m_axis_0_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(0+1)-1 downto C_M_AXIS_TSTRB_WIDTH*0);
m_axis_1_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(1+1)-1 downto C_M_AXIS_TSTRB_WIDTH*1);
m_axis_2_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(2+1)-1 downto C_M_AXIS_TSTRB_WIDTH*2);
m_axis_3_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(3+1)-1 downto C_M_AXIS_TSTRB_WIDTH*3);
m_axis_4_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(4+1)-1 downto C_M_AXIS_TSTRB_WIDTH*4);
m_axis_5_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(5+1)-1 downto C_M_AXIS_TSTRB_WIDTH*5);
m_axis_6_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(6+1)-1 downto C_M_AXIS_TSTRB_WIDTH*6);
m_axis_7_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(7+1)-1 downto C_M_AXIS_TSTRB_WIDTH*7);
--AXI4-Stream master interface TKEEP generation
m_axis_0_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(0+1)-1 downto C_M_AXIS_TKEEP_WIDTH*0);
m_axis_1_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(1+1)-1 downto C_M_AXIS_TKEEP_WIDTH*1);
m_axis_2_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(2+1)-1 downto C_M_AXIS_TKEEP_WIDTH*2);
m_axis_3_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(3+1)-1 downto C_M_AXIS_TKEEP_WIDTH*3);
m_axis_4_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(4+1)-1 downto C_M_AXIS_TKEEP_WIDTH*4);
m_axis_5_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(5+1)-1 downto C_M_AXIS_TKEEP_WIDTH*5);
m_axis_6_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(6+1)-1 downto C_M_AXIS_TKEEP_WIDTH*6);
m_axis_7_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(7+1)-1 downto C_M_AXIS_TKEEP_WIDTH*7);
--AXI4-Stream master interface TLAST generation
m_axis_0_tlast <= m_axis_tlast(0);
m_axis_1_tlast <= m_axis_tlast(1);
m_axis_2_tlast <= m_axis_tlast(2);
m_axis_3_tlast <= m_axis_tlast(3);
m_axis_4_tlast <= m_axis_tlast(4);
m_axis_5_tlast <= m_axis_tlast(5);
m_axis_6_tlast <= m_axis_tlast(6);
m_axis_7_tlast <= m_axis_tlast(7);
--AXI4-Stream master interface TID generation
m_axis_0_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(0+1)-1 downto C_M_AXIS_TID_WIDTH*0);
m_axis_1_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(1+1)-1 downto C_M_AXIS_TID_WIDTH*1);
m_axis_2_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(2+1)-1 downto C_M_AXIS_TID_WIDTH*2);
m_axis_3_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(3+1)-1 downto C_M_AXIS_TID_WIDTH*3);
m_axis_4_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(4+1)-1 downto C_M_AXIS_TID_WIDTH*4);
m_axis_5_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(5+1)-1 downto C_M_AXIS_TID_WIDTH*5);
m_axis_6_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(6+1)-1 downto C_M_AXIS_TID_WIDTH*6);
m_axis_7_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(7+1)-1 downto C_M_AXIS_TID_WIDTH*7);
--AXI4-Stream master interface TDEST generation
m_axis_0_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(0+1)-1 downto C_M_AXIS_TDEST_WIDTH*0);
m_axis_1_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(1+1)-1 downto C_M_AXIS_TDEST_WIDTH*1);
m_axis_2_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(2+1)-1 downto C_M_AXIS_TDEST_WIDTH*2);
m_axis_3_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(3+1)-1 downto C_M_AXIS_TDEST_WIDTH*3);
m_axis_4_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(4+1)-1 downto C_M_AXIS_TDEST_WIDTH*4);
m_axis_5_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(5+1)-1 downto C_M_AXIS_TDEST_WIDTH*5);
m_axis_6_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(6+1)-1 downto C_M_AXIS_TDEST_WIDTH*6);
m_axis_7_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(7+1)-1 downto C_M_AXIS_TDEST_WIDTH*7);
--AXI4-Stream master interface TKEEP generation
m_axis_0_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(0+1)-1 downto C_M_AXIS_TUSER_WIDTH*0);
m_axis_1_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(1+1)-1 downto C_M_AXIS_TUSER_WIDTH*1);
m_axis_2_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(2+1)-1 downto C_M_AXIS_TUSER_WIDTH*2);
m_axis_3_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(3+1)-1 downto C_M_AXIS_TUSER_WIDTH*3);
m_axis_4_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(4+1)-1 downto C_M_AXIS_TUSER_WIDTH*4);
m_axis_5_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(5+1)-1 downto C_M_AXIS_TUSER_WIDTH*5);
m_axis_6_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(6+1)-1 downto C_M_AXIS_TUSER_WIDTH*6);
m_axis_7_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(7+1)-1 downto C_M_AXIS_TUSER_WIDTH*7);
-----------------------------------------------------------------------------------------
-- Accelerator Output Argument interface signal Generation
-- SUPERBUSES BUILDING: AP Output ARGUMENTS:
-----------------------------------------------------------------------------------------
-- Output Argument BRAM interface addr generation
ap_oarg_addr(C_MAX_ARG_AWIDTH*(0+1)-1 downto C_MAX_ARG_AWIDTH*0) <= ap_oarg_0_addr(C_MAX_ARG_AWIDTH+AP_OARG_0_OFFSET-1 downto AP_OARG_0_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(1+1)-1 downto C_MAX_ARG_AWIDTH*1) <= ap_oarg_1_addr(C_MAX_ARG_AWIDTH+AP_OARG_1_OFFSET-1 downto AP_OARG_1_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(2+1)-1 downto C_MAX_ARG_AWIDTH*2) <= ap_oarg_2_addr(C_MAX_ARG_AWIDTH+AP_OARG_2_OFFSET-1 downto AP_OARG_2_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(3+1)-1 downto C_MAX_ARG_AWIDTH*3) <= ap_oarg_3_addr(C_MAX_ARG_AWIDTH+AP_OARG_3_OFFSET-1 downto AP_OARG_3_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(4+1)-1 downto C_MAX_ARG_AWIDTH*4) <= ap_oarg_4_addr(C_MAX_ARG_AWIDTH+AP_OARG_4_OFFSET-1 downto AP_OARG_4_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(5+1)-1 downto C_MAX_ARG_AWIDTH*5) <= ap_oarg_5_addr(C_MAX_ARG_AWIDTH+AP_OARG_5_OFFSET-1 downto AP_OARG_5_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(6+1)-1 downto C_MAX_ARG_AWIDTH*6) <= ap_oarg_6_addr(C_MAX_ARG_AWIDTH+AP_OARG_6_OFFSET-1 downto AP_OARG_6_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(7+1)-1 downto C_MAX_ARG_AWIDTH*7) <= ap_oarg_7_addr(C_MAX_ARG_AWIDTH+AP_OARG_7_OFFSET-1 downto AP_OARG_7_OFFSET);
-- Output Argument BRAM interface ce generation
ap_oarg_ce(0) <= ap_oarg_0_ce;
ap_oarg_ce(1) <= ap_oarg_1_ce;
ap_oarg_ce(2) <= ap_oarg_2_ce;
ap_oarg_ce(3) <= ap_oarg_3_ce;
ap_oarg_ce(4) <= ap_oarg_4_ce;
ap_oarg_ce(5) <= ap_oarg_5_ce;
ap_oarg_ce(6) <= ap_oarg_6_ce;
ap_oarg_ce(7) <= ap_oarg_7_ce;
-- Output Argument BRAM interface we generation
ap_oarg_we(0) <= ap_oarg_0_we(0);
ap_oarg_we(1) <= ap_oarg_1_we(0);
ap_oarg_we(2) <= ap_oarg_2_we(0);
ap_oarg_we(3) <= ap_oarg_3_we(0);
ap_oarg_we(4) <= ap_oarg_4_we(0);
ap_oarg_we(5) <= ap_oarg_5_we(0);
ap_oarg_we(6) <= ap_oarg_6_we(0);
ap_oarg_we(7) <= ap_oarg_7_we(0);
-- Output Argument BRAM interface din generation
ap_oarg_din(C_MAX_ARG_DWIDTH*(0+1)-1 downto C_MAX_ARG_DWIDTH*0) <= ext_lv(ap_oarg_0_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(1+1)-1 downto C_MAX_ARG_DWIDTH*1) <= ext_lv(ap_oarg_1_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(2+1)-1 downto C_MAX_ARG_DWIDTH*2) <= ext_lv(ap_oarg_2_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(3+1)-1 downto C_MAX_ARG_DWIDTH*3) <= ext_lv(ap_oarg_3_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(4+1)-1 downto C_MAX_ARG_DWIDTH*4) <= ext_lv(ap_oarg_4_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(5+1)-1 downto C_MAX_ARG_DWIDTH*5) <= ext_lv(ap_oarg_5_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(6+1)-1 downto C_MAX_ARG_DWIDTH*6) <= ext_lv(ap_oarg_6_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(7+1)-1 downto C_MAX_ARG_DWIDTH*7) <= ext_lv(ap_oarg_7_din, C_MAX_ARG_DWIDTH);
-- Output Argument BRAM interface dout generation
ap_oarg_0_dout <= ap_oarg_dout(C_AP_OARG_0_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_MAX_ARG_DWIDTH*0);
ap_oarg_1_dout <= ap_oarg_dout(C_AP_OARG_1_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_MAX_ARG_DWIDTH*1);
ap_oarg_2_dout <= ap_oarg_dout(C_AP_OARG_2_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_MAX_ARG_DWIDTH*2);
ap_oarg_3_dout <= ap_oarg_dout(C_AP_OARG_3_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_MAX_ARG_DWIDTH*3);
ap_oarg_4_dout <= ap_oarg_dout(C_AP_OARG_4_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_MAX_ARG_DWIDTH*4);
ap_oarg_5_dout <= ap_oarg_dout(C_AP_OARG_5_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_MAX_ARG_DWIDTH*5);
ap_oarg_6_dout <= ap_oarg_dout(C_AP_OARG_6_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_MAX_ARG_DWIDTH*6);
ap_oarg_7_dout <= ap_oarg_dout(C_AP_OARG_7_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_MAX_ARG_DWIDTH*7);
-- Output Argument FIFO interface din generation
ap_fifo_oarg_din(C_AP_OARG_0_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_MAX_ARG_DWIDTH*0) <= ap_fifo_oarg_0_din;
ap_fifo_oarg_din(C_AP_OARG_1_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_MAX_ARG_DWIDTH*1) <= ap_fifo_oarg_1_din;
ap_fifo_oarg_din(C_AP_OARG_2_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_MAX_ARG_DWIDTH*2) <= ap_fifo_oarg_2_din;
ap_fifo_oarg_din(C_AP_OARG_3_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_MAX_ARG_DWIDTH*3) <= ap_fifo_oarg_3_din;
ap_fifo_oarg_din(C_AP_OARG_4_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_MAX_ARG_DWIDTH*4) <= ap_fifo_oarg_4_din;
ap_fifo_oarg_din(C_AP_OARG_5_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_MAX_ARG_DWIDTH*5) <= ap_fifo_oarg_5_din;
ap_fifo_oarg_din(C_AP_OARG_6_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_MAX_ARG_DWIDTH*6) <= ap_fifo_oarg_6_din;
ap_fifo_oarg_din(C_AP_OARG_7_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_MAX_ARG_DWIDTH*7) <= ap_fifo_oarg_7_din;
-- Assining unused bits in the vector to default value to reduce synthesis warnings.
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_AP_OARG_0_DWIDTH+C_MAX_ARG_DWIDTH*0) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_AP_OARG_1_DWIDTH+C_MAX_ARG_DWIDTH*1) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_AP_OARG_2_DWIDTH+C_MAX_ARG_DWIDTH*2) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_AP_OARG_3_DWIDTH+C_MAX_ARG_DWIDTH*3) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_AP_OARG_4_DWIDTH+C_MAX_ARG_DWIDTH*4) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_AP_OARG_5_DWIDTH+C_MAX_ARG_DWIDTH*5) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_AP_OARG_6_DWIDTH+C_MAX_ARG_DWIDTH*6) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_AP_OARG_7_DWIDTH+C_MAX_ARG_DWIDTH*7) <= (others => '0');
-- Output Argument FIFO interface fifo_write generation
ap_fifo_oarg_write(0) <= ap_fifo_oarg_0_write;
ap_fifo_oarg_write(1) <= ap_fifo_oarg_1_write;
ap_fifo_oarg_write(2) <= ap_fifo_oarg_2_write;
ap_fifo_oarg_write(3) <= ap_fifo_oarg_3_write;
ap_fifo_oarg_write(4) <= ap_fifo_oarg_4_write;
ap_fifo_oarg_write(5) <= ap_fifo_oarg_5_write;
ap_fifo_oarg_write(6) <= ap_fifo_oarg_6_write;
ap_fifo_oarg_write(7) <= ap_fifo_oarg_7_write;
-- Output Argument FIFO interface fifo_full generation
ap_fifo_oarg_0_full_n <= ap_fifo_oarg_full_n(0);
ap_fifo_oarg_1_full_n <= ap_fifo_oarg_full_n(1);
ap_fifo_oarg_2_full_n <= ap_fifo_oarg_full_n(2);
ap_fifo_oarg_3_full_n <= ap_fifo_oarg_full_n(3);
ap_fifo_oarg_4_full_n <= ap_fifo_oarg_full_n(4);
ap_fifo_oarg_5_full_n <= ap_fifo_oarg_full_n(5);
ap_fifo_oarg_6_full_n <= ap_fifo_oarg_full_n(6);
ap_fifo_oarg_7_full_n <= ap_fifo_oarg_full_n(7);
--------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------
-- XD_ADAPTER_CORE_I : Adapter core logic
-----------------------------------------------------------------------------------------
XD_ADAPTER_CORE_I : entity axis_accelerator_adapter_v2_1_6.axis_accelerator_adapter_core
generic map (
-- System generics:
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => BRAM_PRIMITIVE_TYPE,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_MTBF_STAGES => C_MTBF_STAGES,
--
C_AP_ADAPTER_ID => C_AP_ADAPTER_ID,
C_MAX_SCALAR_DWIDTH => C_MAX_SCALAR_DWIDTH,
C_MAX_ARG_DWIDTH => C_MAX_ARG_DWIDTH,
C_MAX_ARG_AWIDTH => C_MAX_ARG_AWIDTH,
C_MAX_ARG_N_DIM => C_MAX_ARG_N_DIM,
C_MAX_MB_DEPTH => C_MAX_MB_DEPTH,
C_MAX_N_IARGS => C_MAX_N_IARGS,
C_MAX_N_OARGS => C_MAX_N_OARGS,
C_MAX_N_ISCALARS => C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS,
C_MAX_N_OSCALARS => C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS,
C_MAX_N_IOSCALARS => C_MAX_N_IOSCALARS,
--
C_N_INPUT_ARGS => C_N_INPUT_ARGS,
C_N_OUTPUT_ARGS => C_N_OUTPUT_ARGS,
--
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH,
C_S_AXIS_TUSER_WIDTH => C_S_AXIS_TUSER_WIDTH,
C_S_AXIS_TID_WIDTH => C_S_AXIS_TID_WIDTH,
C_S_AXIS_TDEST_WIDTH => C_S_AXIS_TDEST_WIDTH,
--
C_AP_IARG_TYPE => C_AP_IARG_TYPE,
C_AP_IARG_DWIDTH => C_AP_IARG_DWIDTH,
C_AP_IARG_MB_DEPTH => C_AP_IARG_MB_DEPTH,
--
C_AP_IARG_WIDTH => C_AP_IARG_WIDTH,
C_AP_IARG_N_DIM => C_AP_IARG_N_DIM,
C_AP_IARG_DIM_1 => C_AP_IARG_DIM_1,
C_AP_IARG_DIM_2 => C_AP_IARG_DIM_2,
C_AP_IARG_FORMAT_TYPE => C_AP_IARG_FORMAT_TYPE,
C_AP_IARG_FORMAT_FACTOR => C_AP_IARG_FORMAT_FACTOR,
C_AP_IARG_FORMAT_DIM => C_AP_IARG_FORMAT_DIM,
--
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH,
C_M_AXIS_TUSER_WIDTH => C_M_AXIS_TUSER_WIDTH,
C_M_AXIS_TID_WIDTH => C_M_AXIS_TID_WIDTH,
C_M_AXIS_TDEST_WIDTH => C_M_AXIS_TDEST_WIDTH,
--
C_AP_OARG_TYPE => C_AP_OARG_TYPE,
C_AP_OARG_DWIDTH => C_AP_OARG_DWIDTH,
C_AP_OARG_MB_DEPTH => C_AP_OARG_MB_DEPTH,
--
C_AP_OARG_WIDTH => C_AP_OARG_WIDTH,
C_AP_OARG_N_DIM => C_AP_OARG_N_DIM,
C_AP_OARG_DIM => C_AP_OARG_DIM,
C_AP_OARG_DIM_1 => C_AP_OARG_DIM_1,
C_AP_OARG_DIM_2 => C_AP_OARG_DIM_2,
C_AP_OARG_FORMAT_TYPE => C_AP_OARG_FORMAT_TYPE,
C_AP_OARG_FORMAT_FACTOR => C_AP_OARG_FORMAT_FACTOR,
C_AP_OARG_FORMAT_DIM => C_AP_OARG_FORMAT_DIM,
--
C_N_INOUT_SCALARS => C_N_INOUT_SCALARS,
C_N_INPUT_SCALARS => C_N_INPUT_SCALARS,
C_INPUT_SCALAR_DWIDTH => C_INPUT_SCALAR_DWIDTH,
C_AP_ISCALAR_DOUT_WIDTH => C_AP_ISCALAR_DOUT_WIDTH,
C_INPUT_SCALAR_MODE => C_INPUT_SCALAR_MODE,
--
C_OUTPUT_SCALAR_MODE => C_OUTPUT_SCALAR_MODE,
C_N_OUTPUT_SCALARS => C_N_OUTPUT_SCALARS,
C_OUTPUT_SCALAR_DWIDTH => C_OUTPUT_SCALAR_DWIDTH,
C_AP_OSCALAR_DIN_WIDTH => C_AP_OSCALAR_DIN_WIDTH,
C_AP_ISCALAR_IO_DOUT_WIDTH => C_AP_ISCALAR_IO_DOUT_WIDTH,
C_AP_OSCALAR_IO_DIN_WIDTH => C_AP_OSCALAR_IO_DIN_WIDTH)
port map (
-- SLAVE AXI LITE:
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
--- Slave AXI streams (input arguments)
s_axis_aclk => s_axis_aclk_i,
s_axis_aresetn => s_axis_aresetn_i,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => s_axis_tstrb,
s_axis_tkeep => s_axis_tkeep,
s_axis_tlast => s_axis_tlast,
s_axis_tid => s_axis_tid,
s_axis_tdest => s_axis_tdest,
s_axis_tuser => s_axis_tuser,
--- AP input arguments
ap_iarg_addr => ap_iarg_addr,
ap_iarg_ce => ap_iarg_ce,
ap_iarg_we => ap_iarg_we,
ap_iarg_din => ap_iarg_din,
ap_iarg_dout => ap_iarg_dout,
---
ap_fifo_iarg_dout => ap_fifo_iarg_dout,
ap_fifo_iarg_read => ap_fifo_iarg_read,
ap_fifo_iarg_empty_n => ap_fifo_iarg_empty_n,
--- Master AXI streams (output arguments)
m_axis_aclk => m_axis_aclk_i,
m_axis_aresetn => m_axis_aresetn_i,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tstrb => m_axis_tstrb,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast,
m_axis_tid => m_axis_tid,
m_axis_tdest => m_axis_tdest,
m_axis_tuser => m_axis_tuser,
--- AP output arguments
ap_oarg_addr => ap_oarg_addr,
ap_oarg_ce => ap_oarg_ce,
ap_oarg_we => ap_oarg_we,
ap_oarg_din => ap_oarg_din,
ap_oarg_dout => ap_oarg_dout,
---
ap_fifo_oarg_din => ap_fifo_oarg_din,
ap_fifo_oarg_write => ap_fifo_oarg_write,
ap_fifo_oarg_full_n => ap_fifo_oarg_full_n,
---
ap_clk => aclk,
ap_rst => aresetn,
-- AP control handshaking:
ap_start => ap_start,
ap_ready => ap_ready,
ap_done => ap_done,
ap_continue => ap_continue,
ap_idle => ap_idle,
---
ap_iscalar_dout => ap_iscalar_dout_i,
ap_oscalar_din => ap_oscalar_din_i,
ap_oscalar_vld => ap_oscalar_vld_i,
ap_oscalar_ack => ap_oscalar_ack_i,
ap_iscalar_vld => ap_iscalar_vld_i,
ap_iscalar_ack => ap_iscalar_ack_i,
---
interrupt => interrupt);
end rtl;
|
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Generic SRAM interface. Tested with:
-- 16 Mbit Renesas R1LV1616RSA-7S and 8 Mbit Cypress CY62157EV30.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.lfsr_pkg.all;
entity sram_interface is
generic (
-- SRAM address width
addr_width_g : positive := 20;
-- SRAM data width
data_width_g : positive := 16;
-- Number of clock cycles to finish read operations
read_delay_g : positive := 3;
-- Number of clock cycles to finish write operations
write_delay_g : positive := 3);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
addr_i : in std_ulogic_vector(addr_width_g - 1 downto 0);
rd_en_i : in std_ulogic;
wr_en_i : in std_ulogic;
data_i : in std_ulogic_vector(data_width_g - 1 downto 0);
data_o : out std_ulogic_vector(data_width_g - 1 downto 0);
data_en_o : out std_ulogic;
busy_o : out std_ulogic;
done_o : out std_ulogic;
-- SRAM signals
sram_addr_o : out std_ulogic_vector(addr_width_g - 1 downto 0);
sram_data_i : in std_ulogic_vector(data_width_g - 1 downto 0);
sram_data_o : out std_ulogic_vector(data_width_g - 1 downto 0);
sram_cs1_n_o : out std_ulogic;
sram_cs2_o : out std_ulogic;
sram_we_n_o : out std_ulogic;
sram_oe_n_o : out std_ulogic;
sram_le_n_o : out std_ulogic;
sram_ue_n_o : out std_ulogic;
sram_byte_n_o : out std_ulogic);
end entity sram_interface;
architecture rtl of sram_interface is
------------------------------------------------------------------------------
-- Functions
------------------------------------------------------------------------------
function max (l, r : integer) return integer is
begin
if l > r then return l;
else return r;
end if;
end function max;
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- LFSR counter bit length
constant len_c : natural := lfsr_length(max(read_delay_g, write_delay_g));
-- LFSR counter initial value
constant seed_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_seed(len_c);
-- LFSR counter strobe value
constant rd_max_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_shift(seed_c, read_delay_g - 1);
constant wr_max_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_shift(seed_c, write_delay_g - 1);
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal data : std_ulogic_vector(data_width_g - 1 downto 0);
signal data_en : std_ulogic;
signal done : std_ulogic;
signal sram_addr : std_ulogic_vector(addr_width_g - 1 downto 0);
signal sram_data : std_ulogic_vector(data_width_g - 1 downto 0);
signal sram_cs : std_ulogic;
signal sram_cs_n : std_ulogic;
signal sram_we_n : std_ulogic;
signal sram_oe_n : std_ulogic;
signal count : std_ulogic_vector(len_c - 1 downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
data_o <= data;
data_en_o <= data_en;
busy_o <= sram_cs;
done_o <= done;
sram_addr_o <= sram_addr;
sram_data_o <= sram_data;
sram_cs1_n_o <= sram_cs_n;
sram_cs2_o <= sram_cs;
sram_we_n_o <= sram_we_n;
sram_oe_n_o <= sram_oe_n;
sram_le_n_o <= '0';
sram_ue_n_o <= '0';
sram_byte_n_o <= '1';
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- SRAM interface
intf : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
data <= (others => '0');
data_en <= '0';
done <= '0';
sram_addr <= (others => '0');
sram_data <= (others => '0');
sram_cs <= '0';
sram_cs_n <= '1';
sram_we_n <= '1';
sram_oe_n <= '1';
count <= seed_c;
end procedure reset;
begin -- process intf
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
-- Default values for flags
done <= '0';
data_en <= '0';
if sram_cs = '0' then
-- SRAM is idle
if rd_en_i /= wr_en_i then
-- Common settings for read and write operations
sram_addr <= addr_i;
sram_cs <= '1';
sram_cs_n <= '0';
end if;
if rd_en_i = '1' and wr_en_i = '0' then
-- Read operation
sram_we_n <= '1';
sram_oe_n <= '0';
elsif rd_en_i = '0' and wr_en_i = '1' then
-- Write operation
sram_data <= data_i;
sram_we_n <= '0';
sram_oe_n <= '1';
end if;
else
-- SRAM is busy
if (sram_oe_n = '0' and count = rd_max_c) or (sram_we_n = '0' and count = wr_max_c) then
-- Counter reached num_delay_g
reset;
if sram_oe_n = '0' then
data <= sram_data_i;
data_en <= '1';
end if;
done <= '1';
else
-- Increment counter
count <= lfsr_shift(count);
end if;
end if;
end if;
end if;
end process intf;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library lib;
use lib.controller.all;
use lib.general.all;
use lib.io.all;
entity spaceinvaders is
generic
(
rx : integer := 160; -- H resolution
ry : integer := 120; -- W resolution
cpu_num : integer := ALIENS_PER_LINE; -- aliens per line (set in io.vhd)
cpu_lines : integer := ALIEN_LINES; -- number of lines (set in io.vhd)
py : integer := 110; --
alien_w : integer := 11; -- enemy width
alien_h : integer := 8; -- enemy height
player_w : integer := 13; -- player width
player_h : integer := 6 -- player height
);
port
(
------------------------ Clock Input ------------------------
CLOCK_24 : in STD_LOGIC_VECTOR (1 downto 0); -- 24 MHz
CLOCK_50 : in STD_LOGIC; -- 50 MHz
CLOCK_27 : in STD_LOGIC; -- 27 MHz
------------------------ Push Button ------------------------
KEY : in STD_LOGIC_VECTOR (3 downto 0); -- Pushbutton[3:0]
------------------------ 7-SEG Display ------------------------
HEX0 : out STD_LOGIC_VECTOR (6 downto 0);
HEX1 : out STD_LOGIC_VECTOR (6 downto 0);
HEX2 : out STD_LOGIC_VECTOR (6 downto 0);
HEX3 : out STD_LOGIC_VECTOR (6 downto 0);
---------------------------- LED ----------------------------
LEDG : out STD_LOGIC_VECTOR (7 downto 0); -- LED Green[7:0]
------------------------ PS2 --------------------------------
PS2_DAT : inout STD_LOGIC; -- PS2 Data
PS2_CLK : inout STD_LOGIC; -- PS2 Clock
------------------------ VGA --------------------------------
VGA_R, VGA_G, VGA_B : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
VGA_HS, VGA_VS : OUT STD_LOGIC
);
end entity;
architecture Behavior of spaceinvaders is
--------------------------- CLK/RESET ------------------------------
signal clock_s,reset_s,reset: std_logic;
SIGNAL state : GAME_STATE;
------------------------ PLAYER ----------------------------
signal move_s,shot_s,shot_e_s: std_logic;
signal controls: std_logic_vector(2 downto 0);
signal position_x_s: integer range 0 to rx;
signal position_y_s: integer range 0 to ry;
signal shot_y_s: integer range 0 to ry;
signal shot_x_s: integer range 0 to rx;
signal shot_r_s: std_logic;
------------------------ CPU --------------------------------
signal cpu_arr_x: pos_arr_xt;
signal cpu_arr_y: pos_arr_yt;
signal cpu_arr_e: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_arr_c: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_arr_m: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_arr_d: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal cpu_game_over: std_logic_vector(cpu_num*cpu_lines-1 downto 0);
signal turn: std_logic;
signal shot_enemy_y_s: integer range 0 to ry;
signal shot_enemy_x_s: integer range 0 to rx;
signal shot_enemy_e_s: std_logic;
signal shot_enemy_r_s: std_logic;
signal enemy_shooting: std_logic;
signal clk_enemy_shoot: std_logic;
signal player_death, player_reset : std_logic;
signal player_death_by_alien : std_logic;
signal player_exploding,pc_dead_delay : std_logic;
type PC_STATE_TYPE is (ALIVE, EXPLODING, DEAD);
signal pc_state : PC_STATE_TYPE;
signal game_over,game_over_by_lives : std_logic;
signal game_win : std_logic;
------------------------ HEX --------------------------------
signal hex_s: std_logic_vector(27 downto 0);
signal rnd_s,cmb_s: integer;
signal choosen_enemy : integer;
type hex_arr_t is array(cpu_num-1 downto 0) of std_logic_vector(6 downto 0);
signal hex0_arr,hex1_arr,hex2_arr,hex3_arr: hex_arr_t;
signal lives : natural range 0 to 4 := 4;
begin
----------------------------------------------------------------
-- Game reset
----------------------------------------------------------------
reset <= not(KEY(0)); -- Push Button 0
----------------------------------------------------------------
----------------------------------------------------------------
-- Keyboard control
----------------------------------------------------------------
control: kbd_input
port map
( CLOCK_24(0), not(reset_s), KEY(1), PS2_DAT, PS2_CLK, SHOT_S, MOVE_S, CONTROLS );
----------------------------------------------------------------
----------------------------------------------------------------
-- VGA
----------------------------------------------------------------
vga: vga_module
generic map (
rx,
ry,
cpu_num*cpu_lines
)
port map
(
CLOCK_27, NOT(reset),
state,
POSITION_X_S,
POSITION_Y_S,
player_exploding,
SHOT_X_S,
SHOT_Y_S,
shot_enemy_x_s,
shot_enemy_y_s,
cpu_arr_e,
cpu_arr_d,
cpu_arr_x,
cpu_arr_y,
VGA_R, VGA_G, VGA_B, VGA_HS, VGA_VS
);
----------------------------------------------------------------
----------------------------------------------------------------
-- Player
----------------------------------------------------------------
-- Player controller
player: pc
generic map
(
clock_div => 1000000,
res_x=>rx,
res_y=>ry,
aux_x=>player_w,
aux_y=>player_h,
pos_y=>py
)
port map
( reset_s OR player_reset, move_s and not(player_exploding), controls(0), CLOCK_50, clock_s, position_x_s, position_y_s);
-- Player shot
pc_shooter: shot
generic map
(
clock_div => 500000,
res_x=>rx,
res_y=>ry,
aux_x=>player_w,
aux_y=>player_h
)
port map
(CLOCK_50, reset_s or shot_r_s, shot_s and not(player_exploding), position_x_s, position_y_s,shot_e_s,shot_x_s,shot_y_s);
-- Player dead sprite
pc_delay: clock_counter
generic map ( 18000000 )
port map ( CLOCK_27, pc_dead_delay );
process (pc_dead_delay)
begin
if reset_s = '1' or player_reset = '1' then
player_exploding <= '0';
player_reset <= '0';
pc_state <= ALIVE;
elsif player_death = '1' then
player_exploding <= '1';
pc_state <= EXPLODING;
elsif rising_edge(pc_dead_delay) then
case pc_state is
when ALIVE =>
when EXPLODING =>
pc_state <= DEAD;
when DEAD =>
player_reset <= '1';
player_exploding <= '0';
end case;
end if;
end process;
----------------------------------------------------------------
----------------------------------------------------------------
-- Aliens generator
----------------------------------------------------------------
-- Verify if any enemy reached one of the sides
turn <= '0' when cpu_arr_m = (cpu_arr_m'range => '0') else '1';
-- Generate enemies
generate_cpu:
for i in 0 to (cpu_num*cpu_lines-1) generate
cpu_x: cpu
generic map
(
res_x => rx,
res_y => ry,
pos_x => 15+(18*(i mod cpu_num)),
pos_y => 15+10*(i/cpu_num),
aux_x => alien_w,
aux_y => alien_h,
clock_div => 18000000 -- 18000000
)
port map
(reset_s,cpu_arr_c(i),CLOCK_50,turn,cpu_arr_m(i),cpu_arr_e(i),cpu_arr_x(i),cpu_arr_y(i),cpu_arr_d(i),cpu_game_over(i));
collision_x: collisor
generic map
( res_x=>rx,
res_y=>ry,
w=>alien_w,
h=>alien_h,
clock_div=>100
)
port map
(CLOCK_27, cpu_arr_e(i) and shot_e_s, shot_x_s,cpu_arr_x(i),shot_y_s,cpu_arr_y(i),cpu_arr_c(i));
end generate;
----------------------------------------------------------------
----------------------------------------------------------------
-- ALIEN SHOOTER
----------------------------------------------------------------
enemy_shot_clock: clock_counter
generic map ( 27000000 )
port map ( CLOCK_27, clk_enemy_shoot );
-- Randomly select an alive enemy to shoot
PROCESS (clk_enemy_shoot)
BEGIN
if rising_edge(clk_enemy_shoot) then
choosen_enemy <= rnd_s;
enemy_shooting <= cpu_arr_e(choosen_enemy);
end if;
end process;
cpu_x_shooter: shot
generic map
(
clock_div => 1000000, -- 2500000
res_x=>rx,
res_y=>ry,
aux_x=>alien_w,
aux_y=>0,
flag_up=>'0'
)
port map
(CLOCK_50, reset_s OR shot_enemy_r_s, enemy_shooting, cpu_arr_x(choosen_enemy), cpu_arr_y(choosen_enemy),shot_enemy_e_s,shot_enemy_x_s,shot_enemy_y_s);
-- ALIEN SHOOT COLLISION WITH PLAYER
collision_x: collisor
generic map
( res_x=>rx,
res_y=>ry,
w=>player_w,
h=>player_h,
clock_div=>100
)
port map
(CLOCK_27, shot_enemy_e_s, shot_enemy_x_s, position_x_s, shot_enemy_y_s, position_y_s, shot_enemy_r_s);
shot_r_s <= '0' when cpu_arr_c = (cpu_arr_c'range => '0') else '1';
----------------------------------------------------------------
----------------------------------------------------------------
-- GAME STATE MACHINE
----------------------------------------------------------------
spaceinvaders_fsm:
PROCESS (reset,CLOCK_27)
BEGIN
IF reset = '1' THEN
reset_s <= '1';
state <= START;
ELSIF rising_edge(CLOCK_27) THEN
CASE state IS
WHEN START =>
reset_s <= '0';
IF controls(1) = '1' THEN
reset_s <= '1';
state <= PLAYING;
END IF;
WHEN PLAYING =>
reset_s <= '0';
IF game_over = '1' THEN
state <= GAME_OVER_STATE;
ELSIF game_win = '1' THEN
state <= WIN;
END IF;
WHEN GAME_OVER_STATE | WIN =>
IF controls(1) = '1' THEN
reset_s <= '1';
state <= PLAYING;
END IF;
END CASE;
END IF;
END PROCESS;
----------------------------------------------------------------
----------------------------------------------------------------
-- Live system
----------------------------------------------------------------
-- Death verification
player_death_by_alien <= '0' when cpu_game_over = (cpu_game_over'range => '0') else '1';
player_death <= shot_enemy_r_s;
-- lives: asynchronous reverse counter
process (player_death, reset_s)
begin
if reset_s = '1' then
lives <= 4;
elsif rising_edge(player_death) then
lives <= lives - 1;
end if;
end process;
-- Game win verification
game_win <= '1' when cpu_arr_e = (cpu_arr_e'range => '0') else '0';
-- Game over verification
game_over_by_lives <= '1' when lives = 0 else '0'; -- game over when lives = 0
game_over <= (player_death_by_alien OR game_over_by_lives) and not (player_exploding); -- game over when aliens reach player
-- Lives counter (shown in LEDS)
with lives select
LEDG(0) <= '0' when 0 | 1,
'1' when others;
with lives select
LEDG(1) <= '0' when 0 | 1 | 2,
'1' when others;
with lives select
LEDG(2) <= '1' when 4,
'0' when others;
----------------------------------------------------------------
----------------------------------------------------------------
-- Random number generator
----------------------------------------------------------------
rnd: random_gen
generic map ( cpu_num*cpu_lines )
port map ( clk_enemy_shoot, clock_50, rnd_s);
----------------------------------------------------------------
-- Score system
----------------------------------------------------------------
show_score: score
port map(shot_r_s, reset_s, hex_s); -- shot_r_s as clock
HEX0 <= hex_s(6 downto 0);
HEX1 <= hex_s(13 downto 7);
HEX2 <= hex_s(20 downto 14);
HEX3 <= hex_s(27 downto 21);
----------------------------------------------------------------
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
package rec04_pkg is
type myrec is record
a : std_logic_vector (3 downto 0);
b : std_logic;
end record;
end rec04_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
package rec04_pkg is
type myrec is record
a : std_logic_vector (3 downto 0);
b : std_logic;
end record;
end rec04_pkg;
|
--////////////////////////////////////////////////////////////////////////////////
--// ____ ____
--// / /\/ /
--// /___/ \ / Vendor: Xilinx
--// \ \ \/ Version : 2.6
--// \ \ Application : 7 Series FPGAs Transceivers Wizard
--// / / Filename :v7_adc16dx370_sync_block.vhd
--// /___/ /\
--// \ \ / \
--// \___\/\___\
--//
--//
--
-- Description: Used on signals crossing from one clock domain to
-- another, this is a flip-flop pair, with both flops
-- placed together with RLOCs into the same slice. Thus
-- the routing delay between the two is minimum to safe-
-- guard against metastability issues.
--
--
-- Module v7_adc16dx370_sync_block
-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
--
--
-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity sync_block is
generic (
INITIALISE : bit_vector(1 downto 0) := "00"
);
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
end sync_block;
architecture structural of sync_block is
-- Internal Signals
signal data_sync1 : std_logic;
-- These attributes will stop Vivado translating the desired flip-flops into an
-- SRL based shift register.
attribute ASYNC_REG : string;
attribute ASYNC_REG of data_sync : label is "TRUE";
attribute ASYNC_REG of data_sync_reg : label is "TRUE";
-- These attributes will stop timing errors being reported on the target flip-flop during back annotated SDF simulation.
attribute MSGON : string;
attribute MSGON of data_sync : label is "FALSE";
attribute MSGON of data_sync_reg : label is "FALSE";
-- These attributes will stop XST translating the desired flip-flops into an
-- SRL based shift register.
attribute shreg_extract : string;
attribute shreg_extract of data_sync : label is "no";
attribute shreg_extract of data_sync_reg : label is "no";
begin
data_sync : FD
generic map (
INIT => INITIALISE(0)
)
port map (
C => clk,
D => data_in,
Q => data_sync1
);
data_sync_reg : FD
generic map (
INIT => INITIALISE(1)
)
port map (
C => clk,
D => data_sync1,
Q => data_out
);
end structural;
|
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_pkg.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : 8b/10b Decoder package file
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
---------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
-------------------------------------------------------------------------------
-- Package Declaration
-------------------------------------------------------------------------------
PACKAGE decode_8b10b_pkg IS
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
CONSTANT TFF : TIME := 2 ns;
CONSTANT CONST_NEG : STRING (1 TO 2) := "00";
CONSTANT CONST_POS : STRING (1 TO 2) := "01";
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
FUNCTION int_to_str_1bit (
bit : INTEGER
) RETURN STRING;
FUNCTION bint_2_sl (
X : INTEGER
) RETURN STD_LOGIC;
FUNCTION concat_sinit (
integer_run_disp : INTEGER;
integer_kout : INTEGER;
string_dout : STRING
) RETURN STRING;
FUNCTION str_to_slv(
bitsin : STRING;
nbits : INTEGER
) RETURN STD_LOGIC_VECTOR;
FUNCTION calc_init_val_rd (
SINIT_VAL : STRING(10 DOWNTO 1)
) RETURN INTEGER;
FUNCTION has_bport (
C_HAS_BPORTS : INTEGER;
has_aport : INTEGER
) RETURN INTEGER;
END decode_8b10b_pkg;
-------------------------------------------------------------------------------
-- Package Body
-------------------------------------------------------------------------------
PACKAGE BODY decode_8b10b_pkg IS
-------------------------------------------------------------------------------
-- Convert binary integer (0 or 1) into a single-character-string ("0" or "1")
-------------------------------------------------------------------------------
FUNCTION int_to_str_1bit(bit : INTEGER) RETURN STRING IS
BEGIN
IF (bit = 1) THEN
RETURN "1";
ELSE
RETURN "0";
END IF;
END int_to_str_1bit;
-------------------------------------------------------------------------------
-- Convert binary integer (0 or 1) into std_logic ('0' or '1')
-------------------------------------------------------------------------------
FUNCTION bint_2_sl (X : INTEGER) RETURN STD_LOGIC IS
BEGIN
IF (X = 0) THEN
RETURN '0';
ELSE
RETURN '1';
END IF;
END bint_2_sl;
-------------------------------------------------------------------------------
-- Calculate the SINIT value for the inferred BRAM using the generics:
-- C_SINIT_DOUT, C_SINIT_KOUT, and C_SINIT_RUN_DISP
-------------------------------------------------------------------------------
FUNCTION concat_sinit(
integer_run_disp : INTEGER;
integer_kout : INTEGER;
string_dout : STRING)
RETURN STRING IS
VARIABLE tmp_sym_disp : STRING(1 TO 2);
CONSTANT TMP_CODE_ERR : STRING(1 TO 1) := "0";
CONSTANT TMP_KOUT_0 : STRING(1 TO 1) := "0";
CONSTANT TMP_KOUT_1 : STRING(1 TO 1) := "1";
VARIABLE tmp_str : STRING(1 TO 14);
BEGIN
IF (integer_run_disp = 1) THEN
tmp_sym_disp := CONST_POS; -- D0.0+ has sym_disp of pos
ELSE
tmp_sym_disp := CONST_NEG; -- D0.0- has sym_disp of neg
END IF;
IF (integer_kout = 1) THEN
tmp_str := tmp_sym_disp & tmp_sym_disp & TMP_CODE_ERR &
TMP_KOUT_1 & string_dout;
ELSE
tmp_str := tmp_sym_disp & tmp_sym_disp & TMP_CODE_ERR &
TMP_KOUT_0 & string_dout;
END IF;
RETURN tmp_str;
END concat_sinit;
-----------------------------------------------------------------------------
-- Convert a string containing 1's and 0's into a std_logic_vector of
-- width nbits
-----------------------------------------------------------------------------
FUNCTION str_to_slv(
bitsin : STRING;
nbits : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE ret : STD_LOGIC_VECTOR(bitsin'range);
VARIABLE ret0s : STD_LOGIC_VECTOR(1 TO nbits) := (OTHERS => '0');
VARIABLE retpadded : STD_LOGIC_VECTOR(1 TO nbits) := (OTHERS => '0');
VARIABLE offset : INTEGER := 0;
BEGIN
IF(bitsin'length = 0) THEN -- Make all '0's
RETURN ret0s;
END IF;
IF(bitsin'length < nbits) THEN -- pad MSBs with '0's
offset := nbits - bitsin'length;
FOR i IN bitsin'range LOOP
IF bitsin(i) = '1' THEN
retpadded(i+offset) := '1';
ELSIF (bitsin(i) = 'X' OR bitsin(i) = 'x') THEN
retpadded(i+offset) := 'X';
ELSIF (bitsin(i) = 'Z' OR bitsin(i) = 'z') THEN
retpadded(i+offset) := 'Z';
ELSIF (bitsin(i) = '0') THEN
retpadded(i+offset) := '0';
END IF;
END LOOP;
retpadded(1 TO offset) := (OTHERS => '0');
RETURN retpadded;
END IF;
FOR i IN bitsin'range LOOP
IF bitsin(i) = '1' THEN
ret(i) := '1';
ELSIF (bitsin(i) = 'X' OR bitsin(i) = 'x') THEN
ret(i) := 'X';
ELSIF (bitsin(i) = 'Z' OR bitsin(i) = 'z') THEN
ret(i) := 'Z';
ELSIF (bitsin(i) = '0') THEN
ret(i) := '0';
END IF;
END LOOP;
RETURN ret;
END str_to_slv;
-----------------------------------------------------------------------------
-- Translate the SINIT string value from the core wrapper to
-- C_SINIT_RUN_DISP
-----------------------------------------------------------------------------
FUNCTION calc_init_val_rd (SINIT_VAL : STRING(10 DOWNTO 1)) RETURN INTEGER IS
VARIABLE tmp_init_val : INTEGER;
BEGIN
CASE SINIT_VAL IS
WHEN "0000000001" => tmp_init_val := 1; --D.0.0 (pos)
WHEN "0000000000" => tmp_init_val := 0; --D.0.0 (neg)
WHEN "0100101001" => tmp_init_val := 1; --D.10.2 (pos)
WHEN "0100101000" => tmp_init_val := 0; --D.10.2 (neg)
WHEN "1011010101" => tmp_init_val := 1; --D.21.5 (pos)
WHEN "1011010100" => tmp_init_val := 0; --D.21.5 (neg)
WHEN OTHERS => tmp_init_val := 0; --invalid init value
END CASE;
RETURN tmp_init_val;
END calc_init_val_rd;
-----------------------------------------------------------------------------
-- If C_HAS_BPORTS = 1, then the optional B ports are configured the
-- same as the optional A ports
-- If C_HAS_BPORTS = 0, then the optional B ports are disabled (= 0)
-----------------------------------------------------------------------------
FUNCTION has_bport (
C_HAS_BPORTS : INTEGER;
has_aport : INTEGER)
RETURN INTEGER IS
VARIABLE has_bport : INTEGER;
BEGIN
IF (C_HAS_BPORTS = 1) THEN
has_bport := has_aport;
ELSE
has_bport := 0;
END IF;
RETURN has_bport;
END has_bport;
END decode_8b10b_pkg;
|
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_pkg.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : 8b/10b Decoder package file
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
---------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
-------------------------------------------------------------------------------
-- Package Declaration
-------------------------------------------------------------------------------
PACKAGE decode_8b10b_pkg IS
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
CONSTANT TFF : TIME := 2 ns;
CONSTANT CONST_NEG : STRING (1 TO 2) := "00";
CONSTANT CONST_POS : STRING (1 TO 2) := "01";
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
FUNCTION int_to_str_1bit (
bit : INTEGER
) RETURN STRING;
FUNCTION bint_2_sl (
X : INTEGER
) RETURN STD_LOGIC;
FUNCTION concat_sinit (
integer_run_disp : INTEGER;
integer_kout : INTEGER;
string_dout : STRING
) RETURN STRING;
FUNCTION str_to_slv(
bitsin : STRING;
nbits : INTEGER
) RETURN STD_LOGIC_VECTOR;
FUNCTION calc_init_val_rd (
SINIT_VAL : STRING(10 DOWNTO 1)
) RETURN INTEGER;
FUNCTION has_bport (
C_HAS_BPORTS : INTEGER;
has_aport : INTEGER
) RETURN INTEGER;
END decode_8b10b_pkg;
-------------------------------------------------------------------------------
-- Package Body
-------------------------------------------------------------------------------
PACKAGE BODY decode_8b10b_pkg IS
-------------------------------------------------------------------------------
-- Convert binary integer (0 or 1) into a single-character-string ("0" or "1")
-------------------------------------------------------------------------------
FUNCTION int_to_str_1bit(bit : INTEGER) RETURN STRING IS
BEGIN
IF (bit = 1) THEN
RETURN "1";
ELSE
RETURN "0";
END IF;
END int_to_str_1bit;
-------------------------------------------------------------------------------
-- Convert binary integer (0 or 1) into std_logic ('0' or '1')
-------------------------------------------------------------------------------
FUNCTION bint_2_sl (X : INTEGER) RETURN STD_LOGIC IS
BEGIN
IF (X = 0) THEN
RETURN '0';
ELSE
RETURN '1';
END IF;
END bint_2_sl;
-------------------------------------------------------------------------------
-- Calculate the SINIT value for the inferred BRAM using the generics:
-- C_SINIT_DOUT, C_SINIT_KOUT, and C_SINIT_RUN_DISP
-------------------------------------------------------------------------------
FUNCTION concat_sinit(
integer_run_disp : INTEGER;
integer_kout : INTEGER;
string_dout : STRING)
RETURN STRING IS
VARIABLE tmp_sym_disp : STRING(1 TO 2);
CONSTANT TMP_CODE_ERR : STRING(1 TO 1) := "0";
CONSTANT TMP_KOUT_0 : STRING(1 TO 1) := "0";
CONSTANT TMP_KOUT_1 : STRING(1 TO 1) := "1";
VARIABLE tmp_str : STRING(1 TO 14);
BEGIN
IF (integer_run_disp = 1) THEN
tmp_sym_disp := CONST_POS; -- D0.0+ has sym_disp of pos
ELSE
tmp_sym_disp := CONST_NEG; -- D0.0- has sym_disp of neg
END IF;
IF (integer_kout = 1) THEN
tmp_str := tmp_sym_disp & tmp_sym_disp & TMP_CODE_ERR &
TMP_KOUT_1 & string_dout;
ELSE
tmp_str := tmp_sym_disp & tmp_sym_disp & TMP_CODE_ERR &
TMP_KOUT_0 & string_dout;
END IF;
RETURN tmp_str;
END concat_sinit;
-----------------------------------------------------------------------------
-- Convert a string containing 1's and 0's into a std_logic_vector of
-- width nbits
-----------------------------------------------------------------------------
FUNCTION str_to_slv(
bitsin : STRING;
nbits : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE ret : STD_LOGIC_VECTOR(bitsin'range);
VARIABLE ret0s : STD_LOGIC_VECTOR(1 TO nbits) := (OTHERS => '0');
VARIABLE retpadded : STD_LOGIC_VECTOR(1 TO nbits) := (OTHERS => '0');
VARIABLE offset : INTEGER := 0;
BEGIN
IF(bitsin'length = 0) THEN -- Make all '0's
RETURN ret0s;
END IF;
IF(bitsin'length < nbits) THEN -- pad MSBs with '0's
offset := nbits - bitsin'length;
FOR i IN bitsin'range LOOP
IF bitsin(i) = '1' THEN
retpadded(i+offset) := '1';
ELSIF (bitsin(i) = 'X' OR bitsin(i) = 'x') THEN
retpadded(i+offset) := 'X';
ELSIF (bitsin(i) = 'Z' OR bitsin(i) = 'z') THEN
retpadded(i+offset) := 'Z';
ELSIF (bitsin(i) = '0') THEN
retpadded(i+offset) := '0';
END IF;
END LOOP;
retpadded(1 TO offset) := (OTHERS => '0');
RETURN retpadded;
END IF;
FOR i IN bitsin'range LOOP
IF bitsin(i) = '1' THEN
ret(i) := '1';
ELSIF (bitsin(i) = 'X' OR bitsin(i) = 'x') THEN
ret(i) := 'X';
ELSIF (bitsin(i) = 'Z' OR bitsin(i) = 'z') THEN
ret(i) := 'Z';
ELSIF (bitsin(i) = '0') THEN
ret(i) := '0';
END IF;
END LOOP;
RETURN ret;
END str_to_slv;
-----------------------------------------------------------------------------
-- Translate the SINIT string value from the core wrapper to
-- C_SINIT_RUN_DISP
-----------------------------------------------------------------------------
FUNCTION calc_init_val_rd (SINIT_VAL : STRING(10 DOWNTO 1)) RETURN INTEGER IS
VARIABLE tmp_init_val : INTEGER;
BEGIN
CASE SINIT_VAL IS
WHEN "0000000001" => tmp_init_val := 1; --D.0.0 (pos)
WHEN "0000000000" => tmp_init_val := 0; --D.0.0 (neg)
WHEN "0100101001" => tmp_init_val := 1; --D.10.2 (pos)
WHEN "0100101000" => tmp_init_val := 0; --D.10.2 (neg)
WHEN "1011010101" => tmp_init_val := 1; --D.21.5 (pos)
WHEN "1011010100" => tmp_init_val := 0; --D.21.5 (neg)
WHEN OTHERS => tmp_init_val := 0; --invalid init value
END CASE;
RETURN tmp_init_val;
END calc_init_val_rd;
-----------------------------------------------------------------------------
-- If C_HAS_BPORTS = 1, then the optional B ports are configured the
-- same as the optional A ports
-- If C_HAS_BPORTS = 0, then the optional B ports are disabled (= 0)
-----------------------------------------------------------------------------
FUNCTION has_bport (
C_HAS_BPORTS : INTEGER;
has_aport : INTEGER)
RETURN INTEGER IS
VARIABLE has_bport : INTEGER;
BEGIN
IF (C_HAS_BPORTS = 1) THEN
has_bport := has_aport;
ELSE
has_bport := 0;
END IF;
RETURN has_bport;
END has_bport;
END decode_8b10b_pkg;
|
---------------------------------------------------------------------------
--
-- Module : decode_8b10b_pkg.vhd
--
-- Version : 1.1
--
-- Last Update : 2008-10-31
--
-- Project : 8b/10b Decoder Reference Design
--
-- Description : 8b/10b Decoder package file
--
-- Company : Xilinx, Inc.
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
---------------------------------------------------------------------------
--
-- History
--
-- Date Version Description
--
-- 10/31/2008 1.1 Initial release
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
-------------------------------------------------------------------------------
-- Package Declaration
-------------------------------------------------------------------------------
PACKAGE decode_8b10b_pkg IS
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
CONSTANT TFF : TIME := 2 ns;
CONSTANT CONST_NEG : STRING (1 TO 2) := "00";
CONSTANT CONST_POS : STRING (1 TO 2) := "01";
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
FUNCTION int_to_str_1bit (
bit : INTEGER
) RETURN STRING;
FUNCTION bint_2_sl (
X : INTEGER
) RETURN STD_LOGIC;
FUNCTION concat_sinit (
integer_run_disp : INTEGER;
integer_kout : INTEGER;
string_dout : STRING
) RETURN STRING;
FUNCTION str_to_slv(
bitsin : STRING;
nbits : INTEGER
) RETURN STD_LOGIC_VECTOR;
FUNCTION calc_init_val_rd (
SINIT_VAL : STRING(10 DOWNTO 1)
) RETURN INTEGER;
FUNCTION has_bport (
C_HAS_BPORTS : INTEGER;
has_aport : INTEGER
) RETURN INTEGER;
END decode_8b10b_pkg;
-------------------------------------------------------------------------------
-- Package Body
-------------------------------------------------------------------------------
PACKAGE BODY decode_8b10b_pkg IS
-------------------------------------------------------------------------------
-- Convert binary integer (0 or 1) into a single-character-string ("0" or "1")
-------------------------------------------------------------------------------
FUNCTION int_to_str_1bit(bit : INTEGER) RETURN STRING IS
BEGIN
IF (bit = 1) THEN
RETURN "1";
ELSE
RETURN "0";
END IF;
END int_to_str_1bit;
-------------------------------------------------------------------------------
-- Convert binary integer (0 or 1) into std_logic ('0' or '1')
-------------------------------------------------------------------------------
FUNCTION bint_2_sl (X : INTEGER) RETURN STD_LOGIC IS
BEGIN
IF (X = 0) THEN
RETURN '0';
ELSE
RETURN '1';
END IF;
END bint_2_sl;
-------------------------------------------------------------------------------
-- Calculate the SINIT value for the inferred BRAM using the generics:
-- C_SINIT_DOUT, C_SINIT_KOUT, and C_SINIT_RUN_DISP
-------------------------------------------------------------------------------
FUNCTION concat_sinit(
integer_run_disp : INTEGER;
integer_kout : INTEGER;
string_dout : STRING)
RETURN STRING IS
VARIABLE tmp_sym_disp : STRING(1 TO 2);
CONSTANT TMP_CODE_ERR : STRING(1 TO 1) := "0";
CONSTANT TMP_KOUT_0 : STRING(1 TO 1) := "0";
CONSTANT TMP_KOUT_1 : STRING(1 TO 1) := "1";
VARIABLE tmp_str : STRING(1 TO 14);
BEGIN
IF (integer_run_disp = 1) THEN
tmp_sym_disp := CONST_POS; -- D0.0+ has sym_disp of pos
ELSE
tmp_sym_disp := CONST_NEG; -- D0.0- has sym_disp of neg
END IF;
IF (integer_kout = 1) THEN
tmp_str := tmp_sym_disp & tmp_sym_disp & TMP_CODE_ERR &
TMP_KOUT_1 & string_dout;
ELSE
tmp_str := tmp_sym_disp & tmp_sym_disp & TMP_CODE_ERR &
TMP_KOUT_0 & string_dout;
END IF;
RETURN tmp_str;
END concat_sinit;
-----------------------------------------------------------------------------
-- Convert a string containing 1's and 0's into a std_logic_vector of
-- width nbits
-----------------------------------------------------------------------------
FUNCTION str_to_slv(
bitsin : STRING;
nbits : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE ret : STD_LOGIC_VECTOR(bitsin'range);
VARIABLE ret0s : STD_LOGIC_VECTOR(1 TO nbits) := (OTHERS => '0');
VARIABLE retpadded : STD_LOGIC_VECTOR(1 TO nbits) := (OTHERS => '0');
VARIABLE offset : INTEGER := 0;
BEGIN
IF(bitsin'length = 0) THEN -- Make all '0's
RETURN ret0s;
END IF;
IF(bitsin'length < nbits) THEN -- pad MSBs with '0's
offset := nbits - bitsin'length;
FOR i IN bitsin'range LOOP
IF bitsin(i) = '1' THEN
retpadded(i+offset) := '1';
ELSIF (bitsin(i) = 'X' OR bitsin(i) = 'x') THEN
retpadded(i+offset) := 'X';
ELSIF (bitsin(i) = 'Z' OR bitsin(i) = 'z') THEN
retpadded(i+offset) := 'Z';
ELSIF (bitsin(i) = '0') THEN
retpadded(i+offset) := '0';
END IF;
END LOOP;
retpadded(1 TO offset) := (OTHERS => '0');
RETURN retpadded;
END IF;
FOR i IN bitsin'range LOOP
IF bitsin(i) = '1' THEN
ret(i) := '1';
ELSIF (bitsin(i) = 'X' OR bitsin(i) = 'x') THEN
ret(i) := 'X';
ELSIF (bitsin(i) = 'Z' OR bitsin(i) = 'z') THEN
ret(i) := 'Z';
ELSIF (bitsin(i) = '0') THEN
ret(i) := '0';
END IF;
END LOOP;
RETURN ret;
END str_to_slv;
-----------------------------------------------------------------------------
-- Translate the SINIT string value from the core wrapper to
-- C_SINIT_RUN_DISP
-----------------------------------------------------------------------------
FUNCTION calc_init_val_rd (SINIT_VAL : STRING(10 DOWNTO 1)) RETURN INTEGER IS
VARIABLE tmp_init_val : INTEGER;
BEGIN
CASE SINIT_VAL IS
WHEN "0000000001" => tmp_init_val := 1; --D.0.0 (pos)
WHEN "0000000000" => tmp_init_val := 0; --D.0.0 (neg)
WHEN "0100101001" => tmp_init_val := 1; --D.10.2 (pos)
WHEN "0100101000" => tmp_init_val := 0; --D.10.2 (neg)
WHEN "1011010101" => tmp_init_val := 1; --D.21.5 (pos)
WHEN "1011010100" => tmp_init_val := 0; --D.21.5 (neg)
WHEN OTHERS => tmp_init_val := 0; --invalid init value
END CASE;
RETURN tmp_init_val;
END calc_init_val_rd;
-----------------------------------------------------------------------------
-- If C_HAS_BPORTS = 1, then the optional B ports are configured the
-- same as the optional A ports
-- If C_HAS_BPORTS = 0, then the optional B ports are disabled (= 0)
-----------------------------------------------------------------------------
FUNCTION has_bport (
C_HAS_BPORTS : INTEGER;
has_aport : INTEGER)
RETURN INTEGER IS
VARIABLE has_bport : INTEGER;
BEGIN
IF (C_HAS_BPORTS = 1) THEN
has_bport := has_aport;
ELSE
has_bport := 0;
END IF;
RETURN has_bport;
END has_bport;
END decode_8b10b_pkg;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_k3_k4_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_k3_k4_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_shadow_k3_k4_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_shadow_k3_k4_e
--
architecture rtl of inst_shadow_k3_k4_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:34:57 10/21/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/Levi/P23_Bidirectional_Universal_Shift_Register/Universal_Shift_Register_tb.vhd
-- Project Name: P23_Bidirectional_Universal_Shift_Register
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Universal_Shift_Register
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Universal_Shift_Register_tb IS
END Universal_Shift_Register_tb;
ARCHITECTURE behavior OF Universal_Shift_Register_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Universal_Shift_Register
PORT(
Clr : IN std_logic;
S0 : IN std_logic;
S1 : IN std_logic;
Clk : IN std_logic;
SerialL : IN std_logic;
SerialR : IN std_logic;
ParallelInput : IN std_logic_vector(3 downto 0);
Output : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal Clr : std_logic := '0';
signal S0 : std_logic := '0';
signal S1 : std_logic := '0';
signal Clk : std_logic := '0';
signal SerialL : std_logic := '0';
signal SerialR : std_logic := '0';
signal ParallelInput : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal Output : std_logic_vector(3 downto 0);
-- Clock period definitions
constant Clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Universal_Shift_Register PORT MAP (
Clr => Clr,
S0 => S0,
S1 => S1,
Clk => Clk,
SerialL => SerialL,
SerialR => SerialR,
ParallelInput => ParallelInput,
Output => Output
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
-- clear 1
Clr <= '1';
wait for Clk_period*1;
-- show input 3
Clr <= '0';
ParallelInput <= "0110";
S1 <= '1'; S0 <= '1';
wait for Clk_period*1;
-- clear
Clr <= '1';
wait for Clk_period*1;
-- show input 3
Clr <= '0';
S1 <= '1'; S0 <= '1';
ParallelInput <= "0110";
wait for Clk_period*1;
-- shift R 4,5
S1 <= '0'; S0 <= '1';
SerialR <= '1';
wait for Clk_period*3;
S1 <= '0'; S0 <= '1';
SerialR <= '0';
wait for Clk_period*1;
S1 <= '0'; S0 <= '1';
SerialR <= '1';
-- show input 3
S1 <= '1'; S0 <= '1';
ParallelInput <= "0110";
wait for Clk_period*1;
-- Shift L 6,7
S1 <= '1'; S0 <= '0';
SerialL <= '1';
wait for Clk_period*2;
S1 <= '1'; S0 <= '0';
SerialL <= '0';
wait for Clk_period*1;
S1 <= '1'; S0 <= '0';
SerialL <= '1';
-- nothing
S1 <= '0'; S0 <= '0';
wait for Clk_period*1;
-- show input 3
S1 <= '1'; S0 <= '1';
ParallelInput <= "0110";
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplier_tb is
end entity;
architecture multiplier_tb_arq of multiplier_tb is
signal op_1_in : std_logic_vector(31 downto 0) := (others => '0');
signal op_2_in : std_logic_vector(31 downto 0) := (others => '0');
signal result_out : std_logic_vector(63 downto 0) := (others => '0');
component multiplier is
port(
op_1_in: in std_logic_vector(31 downto 0) := (others => '0');
op_2_in: in std_logic_vector(31 downto 0) := (others => '0');
result_out: out std_logic_vector(63 downto 0) := (others => '0')
);
end component;
begin
multiplier_0 : multiplier
port map(
op_1_in => op_1_in,
op_2_in => op_2_in,
result_out => result_out
);
process
type pattern_type is record
o1 : std_logic_vector(31 downto 0);
o2 : std_logic_vector(31 downto 0);
r : std_logic_vector(63 downto 0);
end record;
-- The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array := (
( "00000000000000000000000000000000","00000000000000000000000000000000","0000000000000000000000000000000000000000000000000000000000000000"),
( "00000000000000000000000000000010","00000000000000000000000000000010","0000000000000000000000000000000000000000000000000000000000000100"),
( "00000000000000000000010000000000","00000000000000000000001000000000","0000000000000000000000000000000000000000000010000000000000000000"),
( "11111111111111111111111111111111","11111111111111111111111111111111","1111111111111111111111111111111000000000000000000000000000000001")
);
begin
for i in patterns'range loop
-- Set the inputs.
op_1_in <= patterns(i).o1;
op_2_in <= patterns(i).o2;
wait for 1 ns;
assert patterns(i).r = result_out report "BAD RESULT, GOT: " & integer'image(to_integer(unsigned(result_out)));
-- Check the outputs.
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:03:57 04/05/2017
-- Design Name:
-- Module Name: master - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MASTER is
Port ( ADC_DOA : in STD_LOGIC_VECTOR (13 downto 0);
ADC_DOB : in STD_LOGIC_VECTOR (13 downto 0);
ADC_BUSY : in STD_LOGIC;
CLK : in STD_LOGIC;
POS : in STD_LOGIC_VECTOR(19 downto 0);
DATA : in STD_LOGIC;
Line : out STD_LOGIC_VECTOR (63 downto 0);
Blank : out STD_LOGIC_VECTOR (15 downto 0);
ADDR : out STD_LOGIC_VECTOR (13 downto 0);
VGA_COLOR : out STD_LOGIC_VECTOR(2 downto 0);
AMP_WE : out STD_LOGIC;
ADC_Start : out STD_LOGIC;
AMP_DI : out STD_LOGIC_VECTOR (7 downto 0));
end MASTER;
architecture Behavioral of MASTER is
-- constant SIDE : integer := 50;
constant SIDE : signed ( 10 downto 0 ) := to_signed( 50, 11);
constant VMAX : signed ( 10 downto 0 ) := to_signed( 600, 11);
constant HMAX : signed ( 10 downto 0 ) := to_signed( 800, 11);
-- constant HMAX : integer := 800;
-- signal BOX_HPOS : integer range -100 to 1000 := 400;
signal BOX_HPOS : signed( 10 downto 0) := to_signed( 400, 11 );
signal BOX_VPOS : signed( 10 downto 0) := to_signed( 300, 11 );
-- signal BOX_VPOS : integer range -100 to 1000 := 300;
signal HPOS : signed( 10 downto 0) := to_signed( 0, 11 );
signal VPOS : signed( 10 downto 0) := to_signed( 0, 11 );
-- signal HPOS : integer range 0 to 800 := 0;
-- signal VPOS : integer range 0 to 600 := 0;
begin
HPOS <= signed('0' & POS(19 downto 10));
VPOS <= signed('0' & POS(9 downto 0));
AMP_WE <= '1' when HPOS = 0 and VPOS = 0 else '0';
AMP_DI <= X"11";
ADC_Start <= '1' when HPOS = HMAX and VPOS = VMAX else '0';
Blank <= X"0F0F";
Line <= "00" & ADC_DOA & X"0000" & "00" & ADC_DOB & X"0000";
BOX: process (CLK, HPOS, VPOS)
begin
if rising_edge(CLK) then
if HPOS = 0 and VPOS = 0 then
BOX_HPOS <= BOX_HPOS - signed(ADC_DOA(13 downto 11));
BOX_VPOS <= BOX_VPOS + signed(ADC_DOB(13 downto 11));
end if;
if BOX_HPOS < 0 then
BOX_HPOS <= to_signed(0, 11);
elsif BOX_HPOS > HMAX - SIDE then
BOX_HPOS <= HMAX - SIDE;
end if;
if BOX_VPOS < 0 then
BOX_VPOS <= to_signed(0, 11);
elsif BOX_VPOS > VMAX - SIDE then
BOX_VPOS <= VMAX - SIDE;
end if;
-- if HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE then
-- VGA_COLOR <= B"101";
-- else
-- VGA_COLOR <= B"001";
-- end if;
end if;
end process BOX;
-- BOX_HPOS <= BOX_HPOS + to_integer(signed(ADC_DOA(13 downto 12)));
ADDR <= STD_LOGIC_VECTOR(VPOS(9 downto 3)) & STD_LOGIC_VECTOR(HPOS(9 downto 3));
VGA_COLOR <= B"101" when HPOS > BOX_HPOS and HPOS < BOX_HPOS + SIDE and VPOS > BOX_VPOS and VPOS < BOX_VPOS + SIDE else DATA & DATA & not DATA;
end Behavioral;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- Vector parts driven by expr
--
ENTITY AssignToASlice1 IS
PORT(
clk : IN STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
data_out : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
rst_n : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF AssignToASlice1 IS
BEGIN
data_out <= data_in(2) & data_in(1) & data_in(0);
END ARCHITECTURE;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented by
/ Altera and Xilinx in their software.
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ The input must have ranges of type for example (0 to 7)(high downto low)
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fixed_float_types.all;
use work.fixed_generic_pkg.all;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity butterfly is
generic(
SPEED_opt : T_speed;
EXTEND_opt : boolean
);
port(
clk : in std_ulogic;
input : in sulv_v;
output : out sulv_v
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture butterfly_1 of butterfly is
signal aux_in : u_sfixed_v(input'range)
(input'element'high downto input'element'low);
signal aux_out : u_sfixed_v(input'range)
(input'element'high+1 downto input'element'low);
/*================================================================================================*/
/*================================================================================================*/
begin
butterfly_core_s_1:
entity work.butterfly_core_s
generic map(
SPEED_opt => SPEED_opt,
EXTEND_opt => EXTEND_opt,
RANGE1_LEFT => input'left,
RANGE1_RIGHT => input'right,
RANGE2_LEFT => input'element'left,
RANGE2_RIGHT => input'element'right
)
port map(
clk => clk,
input => aux_in,
output => aux_out
);
generate_ports:
for i in input'range generate
begin
aux_in(i) <= to_sfixed(input(i), aux_in(i));
output(i) <= to_sulv(aux_out(i));
end;
end generate;
end architecture; |
-- file: clkGen_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clkGen_tb is
end clkGen_tb;
architecture test of clkGen_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(3 downto 1);
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(3 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clkGen_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(3 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(3 downto 1)
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clkGen_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
-- file: clkGen_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clkGen_tb is
end clkGen_tb;
architecture test of clkGen_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(3 downto 1);
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(3 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clkGen_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(3 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(3 downto 1)
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clkGen_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
-- file: clkGen_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clkGen_tb is
end clkGen_tb;
architecture test of clkGen_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(3 downto 1);
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(3 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clkGen_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(3 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(3 downto 1)
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clkGen_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
-------------------------------------------------------------------------------
-- Title : Gigabit Ethernet Package
-- Project : General Purpose Core
-------------------------------------------------------------------------------
-- File : Eth1000BaseXPkg.vhd
-- Author : Kurtis Nishimura
-------------------------------------------------------------------------------
-- Description:
-- Gigabit ethernet constants & types.
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.UtilityPkg.all;
package Eth1000BaseXPkg is
-----------------------------------------------------
-- Constants
-----------------------------------------------------
-- 8B10B Characters
constant K_COM_C : slv(7 downto 0) := "10111100"; -- K28.5, 0xBC
constant D_215_C : slv(7 downto 0) := "10110101"; -- D21.5, 0xB5
constant D_022_C : slv(7 downto 0) := "01000010"; -- D2.2, 0x42
constant D_056_C : slv(7 downto 0) := "11000101"; -- D5.6, 0xC5
constant D_162_C : slv(7 downto 0) := "01010000"; -- D16.2, 0x50
-- Ordered sets
constant OS_C1_C : slv(15 downto 0) := D_215_C & K_COM_C; -- /C1/ 0xB5BC
constant OS_C2_C : slv(15 downto 0) := D_022_C & K_COM_C; -- /C2/ 0x42BC
constant OS_I1_C : slv(15 downto 0) := D_056_C & K_COM_C; -- /I1/ 0xC5BC
constant OS_I2_C : slv(15 downto 0) := D_162_C & K_COM_C; -- /I2/ 0x50BC
constant K_SOP_C : slv( 7 downto 0) := "11111011"; -- K27.7, 0xFB /S/ Start of packet
constant K_EOP_C : slv( 7 downto 0) := "11111101"; -- K29.7, 0xFD /T/ End of packet
constant K_CAR_C : slv( 7 downto 0) := "11110111"; -- K23.7, 0xF7 /R/ Carrier extend
constant K_ERR_C : slv( 7 downto 0) := "11111110"; -- K30.7, 0xFE /V/ Error propagation
constant OS_BL_C : slv(15 downto 0) := (others => '0'); -- Breaklink 0x0000
-- Configuration registers
-- No pause frames supported
constant OS_CN_C : slv(15 downto 0) := x"0020"; -- Configuration reg, ack bit unset
constant OS_CA_C : slv(15 downto 0) := x"4020"; -- Configuration reg, ack bit set
-- Pause frames supported (this version of autonegotiation is not implemented yet)
-- constant OS_CN_C : slv(15 downto 0) := x"01a0"; --Config reg, no ack
-- constant OS_CA_C : slv(15 downto 0) := x"41a0"; --Config reg, with ack
-- Link timer, assuming 62.5 MHz (spec is 10 ms [+ 10 ms - 0 ms])
constant LINK_TIMER_C : natural := 937500; -- 937500 (0xE4E1C) cycles @ 62.5 MHz, ~15 ms
type EthRxPhyLaneInType is record
data : slv(15 downto 0); -- PHY receive data
dataK : slv( 1 downto 0); -- PHY receive data is K character
dispErr : slv( 1 downto 0); -- PHY receive data has disparity error
decErr : slv( 1 downto 0); -- PHY receive data not in table
end record EthRxPhyLaneInType;
constant ETH_RX_PHY_LANE_IN_INIT_C : EthRxPhyLaneInType := (
data => (others => '0'),
dataK => (others => '0'),
dispErr => (others => '0'),
decErr => (others => '0')
);
type EthRxPhyLaneInArray is array (natural range <>) of EthRxPhyLaneInType;
type EthTxPhyLaneOutType is record
data : slv(15 downto 0); -- PHY transmit data
dataK : slv(1 downto 0); -- PHY transmit data is K character
valid : sl;
end record EthTxPhyLaneOutType;
constant ETH_TX_PHY_LANE_OUT_INIT_C : EthTxPhyLaneOutType := (
data => (others => '0'),
dataK => (others => '0'),
valid => '0'
);
type EthTxPhyLaneOutArray is array (natural range <>) of EthTxPhyLaneOutType;
end Eth1000BaseXPkg;
package body Eth1000BaseXPkg is
end package body Eth1000BaseXPkg;
|
--This is an autogenerated file
--Do not modify it by hand
--Generated at 2017-12-14T16:53:23+13:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.enforcement_types_WaterBoilerEnforcer.all;
entity enforcer_WaterBoilerEnforcer_P2 is
port
(
clk : in std_logic;
reset : in std_logic;
t : in unsigned(63 downto 0); --current time in nanoseconds
e : out std_logic; --if enforcement occured
--the input signals
--the enforce signals
q : in enforced_signals_WaterBoilerEnforcer;
q_prime : out enforced_signals_WaterBoilerEnforcer
);
end entity;
architecture behaviour of enforcer_WaterBoilerEnforcer_P2 is
signal trigger_Top : std_logic := '0';
signal trigger_Top_time : unsigned(63 downto 0) := (others => '0');
begin
--trigger process
process(reset, clk, q, t)
variable q_enf: enforced_signals_WaterBoilerEnforcer;
begin
if(rising_edge(clk)) then
--default values
q_enf := q;
e <= '0';
--policies begin
if((trigger_Top = '1') and (q_enf.Aop = '1') ) then
e <= '1';
--recover
q_enf.Aop := '1';
end if;
--Triggers begin (triggers are after policies because a policy might edit a value that a trigger depends on)
if(trigger_Top = '0' and ((q_enf.Pboiler >= to_unsigned(100, 8)))) then
trigger_Top <= '1';
trigger_Top_time <= t;
end if;
q_prime <= q_enf;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.dma_bus_pkg.all;
entity io_to_dma_bridge is
generic (
g_ignore_stop : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
c64_stopped : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
dma_req : out t_dma_req;
dma_resp : in t_dma_resp );
end entity;
architecture rtl of io_to_dma_bridge is
signal dma_req_i : t_dma_req := c_dma_req_init;
begin
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if dma_resp.rack='1' then
dma_req_i.request <= '0';
if dma_req_i.read_writen='0' then -- was write
io_resp.ack <= '1';
end if;
end if;
if dma_resp.dack='1' then
io_resp.data <= dma_resp.data;
io_resp.ack <= '1';
end if;
if io_req.write='1' or io_req.read = '1' then
dma_req_i.address <= io_req.address(15 downto 0);
dma_req_i.read_writen <= io_req.read;
dma_req_i.data <= io_req.data;
if c64_stopped='1' or g_ignore_stop then
dma_req_i.request <= '1';
else
io_resp.ack <= '1';
end if;
end if;
if reset='1' then
dma_req_i.request <= '0';
end if;
end if;
end process;
dma_req <= dma_req_i;
end architecture;
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiply_add is
end entity alt_dspbuilder_multiply_add;
architecture rtl of alt_dspbuilder_multiply_add is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiply_add is
end entity alt_dspbuilder_multiply_add;
architecture rtl of alt_dspbuilder_multiply_add is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiply_add is
end entity alt_dspbuilder_multiply_add;
architecture rtl of alt_dspbuilder_multiply_add is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_multiply_add is
end entity alt_dspbuilder_multiply_add;
architecture rtl of alt_dspbuilder_multiply_add is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff2.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff2 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (20 DOWNTO 0)
);
END lpm_dff2;
ARCHITECTURE SYN OF lpm_dff2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (20 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (20 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(20 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 21
)
PORT MAP (
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "21"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "21"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 21 0 INPUT NODEFVAL data[20..0]
-- Retrieval info: USED_PORT: q 0 0 21 0 OUTPUT NODEFVAL q[20..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 21 0 @q 0 0 21 0
-- Retrieval info: CONNECT: @data 0 0 21 0 data 0 0 21 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram03 is
port (
clk_i : std_logic;
addr_i : std_logic_vector(3 downto 0);
data_i : std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
wen_i : std_logic);
end sram03;
architecture behav of sram03 is
type mem_type is array (0 to 15) of std_logic_vector (7 downto 0);
signal mem : mem_type;
begin
process (clk_i, addr_i)
variable addr : natural range mem_type'range;
begin
if rising_edge(clk_i) then
addr := to_integer (unsigned (addr_i));
if wen_i = '1' then
mem (addr) <= data_i;
end if;
data_o <= mem (addr);
end if;
end process;
end behav;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_overlay:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_overlay_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_overlay_0_0;
ARCHITECTURE system_vga_overlay_0_0_arch OF system_vga_overlay_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_overlay_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_overlay IS
PORT (
clk : IN STD_LOGIC;
rgb_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_overlay;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_overlay
PORT MAP (
clk => clk,
rgb_0 => rgb_0,
rgb_1 => rgb_1,
rgb => rgb
);
END system_vga_overlay_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_overlay:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_overlay_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_overlay_0_0;
ARCHITECTURE system_vga_overlay_0_0_arch OF system_vga_overlay_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_overlay_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_overlay IS
PORT (
clk : IN STD_LOGIC;
rgb_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_overlay;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_overlay
PORT MAP (
clk => clk,
rgb_0 => rgb_0,
rgb_1 => rgb_1,
rgb => rgb
);
END system_vga_overlay_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_overlay:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_overlay_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_overlay_0_0;
ARCHITECTURE system_vga_overlay_0_0_arch OF system_vga_overlay_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_overlay_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_overlay IS
PORT (
clk : IN STD_LOGIC;
rgb_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_overlay;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_overlay
PORT MAP (
clk => clk,
rgb_0 => rgb_0,
rgb_1 => rgb_1,
rgb => rgb
);
END system_vga_overlay_0_0_arch;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file RAM.vhd when simulating
-- the core, RAM. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY RAM IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END RAM;
ARCHITECTURE RAM_a OF RAM IS
-- synthesis translate_off
COMPONENT wrapped_RAM
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_RAM USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 1,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 32,
c_read_width_b => 32,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 32,
c_write_width_b => 32,
c_xdevicefamily => "spartan3a"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_RAM
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END RAM_a;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_r is
generic(
NUM_BITS : positive := 163
);
port(
R_div_2 : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
P_div_2 : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
S_div_2 : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
c_3 : in STD_LOGIC;
c_0 : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
R : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_r is
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
Celda_r_process: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
R <= (others => '0');
else
if c_3 = '1' and C_0 = '1' then
R <= R_div_2 xor P_div_2 xor S_div_2;
elsif c_3 = '1' and C_0 = '0' then
R <= R_div_2 xor P_div_2;
elsif c_3 = '0' and C_0 = '1' then
R <= R_div_2 xor S_div_2;
else
R <= R_div_2;
end if;
end if;
end if;
end process;
end behave; |
--Top Entity
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FREQ_CNT IS
PORT(
RST: IN STD_LOGIC;
CLK_IN_1HZ: IN STD_LOGIC;
CLK_DISP: IN STD_LOGIC;
TEST_CLK: IN STD_LOGIC;
MEASURE_CLK: IN STD_LOGIC;
CHOOSE: IN STD_LOGIC;
DATA_RANGE: IN STD_LOGIC;
BEEP: OUT STD_LOGIC;
RANGE_DISP: OUT STD_LOGIC;
DATA2LED: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SEL2LED: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENTITY FREQ_CNT;
ARCHITECTURE ART OF FREQ_CNT IS
COMPONENT DIV_FREQ IS
PORT( CLK_IN_1HZ: IN STD_LOGIC;
RST: IN STD_LOGIC;
CLK_OUT_05HZ: OUT STD_LOGIC);
END COMPONENT;
COMPONENT SEL_SIGNAL IS
PORT( TEST_CLK: IN STD_LOGIC;
MEASURE_CLK: IN STD_LOGIC;
CHOOSE: IN STD_LOGIC;
CLK: OUT STD_LOGIC);
END COMPONENT;
COMPONENT COUNT IS
PORT( CLK: IN STD_LOGIC;
CLK_OUT_05HZ: IN STD_LOGIC;
RST: IN STD_LOGIC;
D1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D3: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CARRY: OUT STD_LOGIC;
READ_EN: OUT STD_LOGIC);
END COMPONENT;
COMPONENT ALERT IS
PORT( DATA_RANGE: IN STD_LOGIC;
CARRY_LABEL: IN STD_LOGIC;
D1_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D4_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D1_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
BEEP: OUT STD_LOGIC;
RANGE_DISP: OUT STD_LOGIC);
END COMPONENT;
COMPONENT D_LATCH IS
PORT( LATCH_EN: IN STD_LOGIC;
D1_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_IN: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
D1_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D2_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
D3_OUT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT LED_DISP IS
PORT( CLK_DISP: IN STD_LOGIC;
DATA_IN_1: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_IN_2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA_IN_3: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DATA2LED: OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
SEL2LED: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT;
SIGNAL WIRE1: STD_LOGIC;
SIGNAL WIRE2: STD_LOGIC;
SIGNAL WIRE3: STD_LOGIC;
SIGNAL WIRE4: STD_LOGIC;
SIGNAL WIRE_C_D1: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_C_D2: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_C_D3: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_C_D4: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_A_D1: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_A_D2: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_A_D3: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_L_D1: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_L_D2: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL WIRE_L_D3: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
INST_DIV_FREQ: DIV_FREQ
PORT MAP(CLK_IN_1HZ => CLK_IN_1HZ,
RST => RST,
CLK_OUT_05HZ => WIRE1);
INST_SEL_SIGNAL: SEL_SIGNAL
PORT MAP(TEST_CLK => TEST_CLK,
MEASURE_CLK => MEASURE_CLK,
CHOOSE => CHOOSE,
CLK => WIRE2);
INST_COUNT: COUNT
PORT MAP(CLK => WIRE2,
CLK_OUT_05HZ => WIRE1,
RST => RST,
D1 => WIRE_C_D1,
D2 => WIRE_C_D2,
D3 => WIRE_C_D3,
D4 => WIRE_C_D4,
CARRY => WIRE3,
READ_EN => WIRE4);
INST_ALERT: ALERT
PORT MAP(DATA_RANGE => DATA_RANGE,
CARRY_LABEL => WIRE3,
D1_IN => WIRE_C_D1,
D2_IN => WIRE_C_D2,
D3_IN => WIRE_C_D3,
D4_IN => WIRE_C_D4,
D1_OUT => WIRE_A_D1,
D2_OUT => WIRE_A_D2,
D3_OUT => WIRE_A_D3,
BEEP => BEEP,
RANGE_DISP => RANGE_DISP);
INST_D_LATCH: D_LATCH
PORT MAP(LATCH_EN => WIRE4,
D1_IN => WIRE_A_D1,
D2_IN => WIRE_A_D2,
D3_IN => WIRE_A_D3,
D1_OUT => WIRE_L_D1,
D2_OUT => WIRE_L_D2,
D3_OUT => WIRE_L_D3);
INST_LED_DISP: LED_DISP
PORT MAP(CLK_DISP => CLK_DISP,
DATA_IN_1 => WIRE_L_D1,
DATA_IN_2 => WIRE_L_D2,
DATA_IN_3 => WIRE_L_D3,
DATA2LED => DATA2LED,
SEL2LED => SEL2LED);
END ARCHITECTURE ART;
|
Subsets and Splits