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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc839.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s03b01x00p03n01i00839ent_a is
end c01s03b01x00p03n01i00839ent_a;
architecture c01s03b01x00p03n01i00839arch_a of c01s03b01x00p03n01i00839ent_a is
begin
AC_BLK : block
signal B : BIT;
begin
B <= '1';
end block;
end c01s03b01x00p03n01i00839arch_a;
ENTITY c01s03b01x00p03n01i00839ent IS
END c01s03b01x00p03n01i00839ent;
ARCHITECTURE c01s03b01x00p03n01i00839arch OF c01s03b01x00p03n01i00839ent IS
BEGIN
A_BLK : block
component C
end component;
begin
L1 : C;
L2 : C;
L3 : C;
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s03b01x00p03n01i00839"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s03b01x00p03n01i00839arch;
configuration c01s03b01x00p03n01i00839cfg of c01s03b01x00p03n01i00839ent is
--- Failure_here; Missing architecture name
for A_BLK
for L1 : C
use entity work.c01s03b01x00p03n01i00839ent_a (c01s03b01x00p03n01i00839arch_a) ;
end for;
for L2 : C
use entity work.c01s03b01x00p03n01i00839ent_a (c01s03b01x00p03n01i00839arch_a) ;
end for;
for L3 : C
use entity work.c01s03b01x00p03n01i00839ent_a (c01s03b01x00p03n01i00839arch_a) ;
end for;
end for;
end c01s03b01x00p03n01i00839cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc839.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s03b01x00p03n01i00839ent_a is
end c01s03b01x00p03n01i00839ent_a;
architecture c01s03b01x00p03n01i00839arch_a of c01s03b01x00p03n01i00839ent_a is
begin
AC_BLK : block
signal B : BIT;
begin
B <= '1';
end block;
end c01s03b01x00p03n01i00839arch_a;
ENTITY c01s03b01x00p03n01i00839ent IS
END c01s03b01x00p03n01i00839ent;
ARCHITECTURE c01s03b01x00p03n01i00839arch OF c01s03b01x00p03n01i00839ent IS
BEGIN
A_BLK : block
component C
end component;
begin
L1 : C;
L2 : C;
L3 : C;
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s03b01x00p03n01i00839"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s03b01x00p03n01i00839arch;
configuration c01s03b01x00p03n01i00839cfg of c01s03b01x00p03n01i00839ent is
--- Failure_here; Missing architecture name
for A_BLK
for L1 : C
use entity work.c01s03b01x00p03n01i00839ent_a (c01s03b01x00p03n01i00839arch_a) ;
end for;
for L2 : C
use entity work.c01s03b01x00p03n01i00839ent_a (c01s03b01x00p03n01i00839arch_a) ;
end for;
for L3 : C
use entity work.c01s03b01x00p03n01i00839ent_a (c01s03b01x00p03n01i00839arch_a) ;
end for;
end for;
end c01s03b01x00p03n01i00839cfg;
|
-- fsm.vhd: Finite State Machine
-- Author(s):
--
library ieee;
use ieee.std_logic_1164.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity fsm is
port(
CLK : in std_logic;
RESET : in std_logic;
-- Input signals
KEY : in std_logic_vector(15 downto 0);
CNT_OF : in std_logic;
-- Output signals
FSM_CNT_CE : out std_logic;
FSM_MX_MEM : out std_logic;
FSM_MX_LCD : out std_logic;
FSM_LCD_WR : out std_logic;
FSM_LCD_CLR : out std_logic
);
end entity fsm;
-- ----------------------------------------------------------------------------
-- Architecture declaration
-- ----------------------------------------------------------------------------
architecture behavioral of fsm is
type t_state is (IDLE, ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7_1, ST7_2, ST8_1,
ST8_2, ST9_1, ST9_2, ST10_1, ST10_2, ST11, SKIP, PRINT_OK, PRINT_WRONG);
signal present_state, next_state : t_state;
begin
-- -------------------------------------------------------
sync_logic : process(RESET, CLK)
begin
if (RESET = '1') then
present_state <= ST0;
elsif (CLK'event AND CLK = '1') then
present_state <= next_state;
end if;
end process sync_logic;
-- -------------------------------------------------------
next_state_logic : process(present_state, KEY, CNT_OF)
begin
case (present_state) is
-- - - - - - - - - - - - - - - - - - - - - - -
when IDLE =>
next_state <= IDLE;
if (KEY(15) = '1') then
next_state <= ST0;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST0 =>
next_state <= ST0;
if (KEY(1) = '1') then
next_state <= ST1;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST1 =>
next_state <= ST1;
if (KEY(4) = '1') then
next_state <= ST2;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST2 =>
next_state <= ST2;
if (KEY(6) = '1') then
next_state <= ST3;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST3 =>
next_state <= ST3;
if (KEY(0) = '1') then
next_state <= ST4;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST4 =>
next_state <= ST4;
if (KEY(6) = '1') then
next_state <= ST5;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST5 =>
next_state <= ST5;
if (KEY(4) = '1') then
next_state <= ST6;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST6 =>
next_state <= ST6;
if (KEY(7) = '1') then
next_state <= ST7_1;
elsif (KEY(8) = '1') then
next_state <= ST7_2;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST7_1 =>
next_state <= ST7_1;
if (KEY(2) = '1') then
next_state <= ST8_1;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST7_2 =>
next_state <= ST7_2;
if (KEY(9) = '1') then
next_state <= ST8_2;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST8_1 =>
next_state <= ST8_1;
if (KEY(6) = '1') then
next_state <= ST9_1;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST8_2 =>
next_state <= ST8_2;
if (KEY(4) = '1') then
next_state <= ST9_2;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST9_1 =>
next_state <= ST9_1;
if (KEY(2) = '1') then
next_state <= ST10_1;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST9_2 =>
next_state <= ST9_2;
if (KEY(6) = '1') then
next_state <= ST10_2;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST10_1 =>
next_state <= ST10_1;
if (KEY(4) = '1') then
next_state <= ST11;
elsif (KEY(15) = '1') then
next_state <= PRINT_WRONG;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST10_2 =>
next_state <= ST10_2;
if (KEY(15) = '1') then
next_state <= PRINT_OK;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when ST11 =>
next_state <= ST11;
if (KEY(15) = '1') then
next_state <= PRINT_OK;
elsif (KEY(14 downto 0) /= "000000000000000") then
next_state <= SKIP;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when SKIP =>
next_state <= SKIP;
if (KEY(15) = '1') then
next_state <= PRINT_WRONG;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_OK =>
next_state <= PRINT_OK;
if (CNT_OF = '1') then
next_state <= IDLE;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_WRONG =>
next_state <= PRINT_WRONG;
if (CNT_OF = '1') then
next_state <= IDLE;
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when others =>
next_state <= IDLE;
end case;
end process next_state_logic;
-- -------------------------------------------------------
output_logic : process(present_state, KEY)
begin
FSM_CNT_CE <= '0';
FSM_MX_MEM <= '0';
FSM_MX_LCD <= '0';
FSM_LCD_WR <= '0';
FSM_LCD_CLR <= '0';
case (present_state) is
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_OK =>
FSM_MX_MEM <= '1';
FSM_CNT_CE <= '1';
FSM_MX_LCD <= '1';
FSM_LCD_WR <= '1';
-- - - - - - - - - - - - - - - - - - - - - - -
when PRINT_WRONG =>
FSM_CNT_CE <= '1';
FSM_MX_LCD <= '1';
FSM_LCD_WR <= '1';
-- - - - - - - - - - - - - - - - - - - - - - -
when IDLE =>
if (KEY(15) = '1') then
FSM_LCD_CLR <= '1';
end if;
-- - - - - - - - - - - - - - - - - - - - - - -
when others =>
if (KEY(14 downto 0) /= "000000000000000") then
FSM_LCD_WR <= '1';
end if;
if (KEY(15) = '1') then
FSM_LCD_CLR <= '1';
end if;
end case;
end process output_logic;
end architecture behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity topo_comparadores is
port (SEQ_3, SEQ_2, SEQ_1, SEQ_0 : IN STD_LOGIC_VECTOR(4 downto 0);
CONTA_DES: IN STD_LOGIC_VECTOR(9 downto 0);
TESTE_PASS: IN STD_LOGIC;
PASS_CERTO, SALDO : OUT STD_LOGIC
);
end topo_comparadores;
architecture topo_comparadores_arch of topo_comparadores is
signal SEQ3_0: std_logic_vector(19 downto 0);
signal OK: std_logic;
component comparador
port (SEQ3_0: in std_logic_vector(19 downto 0);
OK: out std_logic
);
end component;
component comparador10
port (CONTA_DES: in std_logic_vector(9 downto 0);
SALDO: out std_logic
);
end component;
begin
SEQ3_0 <= SEQ_3 & SEQ_2 & SEQ_1 & SEQ_0;--os sinais de 5 bits que vem da saída dos registradores são concatenados em um único sinal na entrada do comparador.
PASS_CERTO <= TESTE_PASS and OK;--sinal criado para receber a saída TESTE_PASS da máquina de controle e a saída do comparador da senha.
L0: comparador port map (SEQ3_0, OK);
L1: comparador10 port map (CONTA_DES, SALDO);
end topo_comparadores_arch; |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 03:32:34 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_block_design_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : gcd_block_design_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_asr : in STD_LOGIC;
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => p_1_in,
I2 => p_2_in,
I3 => \^scndry_out\,
I4 => asr_lpf(0),
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(1),
I2 => p_3_out(2),
I3 => \^scndry_out\,
I4 => p_3_out(0),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => dcm_locked,
I1 => lpf_exr,
I2 => lpf_asr,
I3 => Q,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
port (
MB_out : out STD_LOGIC;
Bsr_out : out STD_LOGIC;
Pr_out : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
signal \^bsr_out\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^mb_out\ : STD_LOGIC;
signal \^pr_out\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Bsr_out <= \^bsr_out\;
MB_out <= \^mb_out\;
Pr_out <= \^pr_out\;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr_out\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr_out\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mb_out\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^mb_out\,
S => lpf_int
);
SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0090"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(4),
I2 => seq_cnt(3),
I3 => seq_cnt(5),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr_out\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr_out\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9000"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(4),
I2 => seq_cnt(3),
I3 => seq_cnt(5),
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mb_out\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0018"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(0),
I2 => seq_cnt(2),
I3 => seq_cnt(1),
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0480"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr_out\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr_out\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
signal Bsr_out : STD_LOGIC;
signal MB_out : STD_LOGIC;
signal Pr_out : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal lpf_int : STD_LOGIC;
attribute box_type : string;
attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE";
attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE";
attribute box_type of FDRE_inst : label is "PRIMITIVE";
attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Bsr_out,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
FDRE_inst: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => MB_out,
Q => mb_reset,
R => '0'
);
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Pr_out,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4,
Bsr_out => Bsr_out,
MB_out => MB_out,
Pr_out => Pr_out,
lpf_int => lpf_int,
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd_block_design_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2018.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0";
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
-- $Id: $
-- File name: tb_ClkDivide.vhd
-- Created: 2/29/2012
-- Author: David Kauer
-- Lab Section: 2
-- Version: 1.0 Initial Test Bench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_SpiClkDivide is
generic( CLK_PERIOD : Time := 10 ns );
end tb_SpiClkDivide;
architecture TEST of tb_SpiClkDivide is
function UINT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
return STD_LOGIC_VECTOR is
begin
return std_logic_vector(to_unsigned(X, NumBits));
end;
function STD_LOGIC_TO_UINT( X: std_logic_vector)
return integer is
begin
return to_integer(unsigned(x));
end;
component SpiClkDivide
PORT(
clk : in std_logic;
resetN : in std_logic;
sclEnable : in std_logic;
tsrEnable : out std_logic;
scl : out std_logic
);
end component;
signal clk : std_logic;
signal resetN : std_logic;
signal sclEnable : std_logic;
signal tsrEnable : std_logic;
signal scl : std_logic;
begin
process
begin
clk <= '1';
wait for CLK_PERIOD/2;
clk <= '0';
wait for CLK_PERIOD/2;
end process;
DUT: SpiClkDivide port map(
clk => clk,
resetN => resetN,
tsrEnable => tsrEnable,
sclEnable => sclEnable,
scl => scl
);
process
begin
sclEnable <= '1';
-- run for 1000 ns
resetN <= '0';
wait for 10 ns;
resetN <= '1';
wait;
end process;
end TEST;
|
-- Hello world program.
use std.textio.all; -- Imports the standard textio package.
-- Defines a design entity, without any ports.
entity hello_world is
end hello_world;
architecture behaviour of hello_world is
begin
process
variable l : line;
begin
write (l, String'("Hello world!"));
writeline (output, l);
wait;
end process;
end behaviour;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL data_count : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(37-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(37-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(37-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(37-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 24 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 37,
C_DOUT_WIDTH => 37,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 37,
C_DIN_WIDTH => 37,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 37,
C_DIN_WIDTH => 37,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : fifo_37x512_hf_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
-- megafunction wizard: %ALTFP_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altfp_add_sub
-- ============================================================
-- File Name: fp_sub.vhd
-- Megafunction Name(s):
-- altfp_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_add_sub CBX_AUTO_BLACKBOX="ALL" DENORMAL_SUPPORT="NO" DEVICE_FAMILY="Cyclone II" DIRECTION="SUB" OPTIMIZE="SPEED" PIPELINE=7 REDUCED_FUNCTIONALITY="NO" WIDTH_EXP=8 WIDTH_MAN=23 aclr clk_en clock dataa datab result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_altfp_add_sub 2010:03:24:20:34:20:SJ cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_cycloneii 2010:03:24:20:34:20:SJ cbx_lpm_add_sub 2010:03:24:20:34:20:SJ cbx_lpm_compare 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ cbx_stratix 2010:03:24:20:34:20:SJ cbx_stratixii 2010:03:24:20:34:20:SJ VERSION_END
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=26 WIDTHDIST=5 aclr clk_en clock data distance result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources = reg 27
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altbarrel_shift_h0e IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END fp_sub_altbarrel_shift_h0e;
ARCHITECTURE RTL OF fp_sub_altbarrel_shift_h0e IS
SIGNAL dir_pipe : STD_LOGIC_VECTOR(0 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL sbit_piper1d : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w680w681w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w675w676w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w701w702w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w696w697w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w723w724w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w718w719w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w745w746w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w740w741w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w767w768w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w762w763w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w670w671w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w691w692w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w713w714w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w735w736w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w757w758w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w680w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w675w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w701w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w696w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w723w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w718w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w745w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w740w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w767w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w762w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range665w679w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range687w700w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range708w722w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range730w744w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_dir_w_range752w766w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range668w670w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range689w691w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range711w713w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range733w735w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_sel_w_range755w757w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w680w681w682w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w701w702w703w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w723w724w725w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w745w746w747w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w767w768w769w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w683w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w704w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w726w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w748w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w770w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w674w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w678w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w695w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w699w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w717w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w721w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w739w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w743w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w761w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w765w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range665w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range687w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range708w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range730w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_dir_w_range752w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range728w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range750w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range663w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range686w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sbit_w_range706w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range668w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range689w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range711w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range733w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_sel_w_range755w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_lbarrel_shift_w_smux_w_range771w : STD_LOGIC_VECTOR (25 DOWNTO 0);
BEGIN
loop0 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w680w681w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w680w(0) AND wire_lbarrel_shift_w678w(i);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w675w676w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w675w(0) AND wire_lbarrel_shift_w674w(i);
END GENERATE loop1;
loop2 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w701w702w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w701w(0) AND wire_lbarrel_shift_w699w(i);
END GENERATE loop2;
loop3 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w696w697w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w696w(0) AND wire_lbarrel_shift_w695w(i);
END GENERATE loop3;
loop4 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w723w724w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w723w(0) AND wire_lbarrel_shift_w721w(i);
END GENERATE loop4;
loop5 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w718w719w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w718w(0) AND wire_lbarrel_shift_w717w(i);
END GENERATE loop5;
loop6 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w745w746w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w745w(0) AND wire_lbarrel_shift_w743w(i);
END GENERATE loop6;
loop7 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w740w741w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w740w(0) AND wire_lbarrel_shift_w739w(i);
END GENERATE loop7;
loop8 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w767w768w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w767w(0) AND wire_lbarrel_shift_w765w(i);
END GENERATE loop8;
loop9 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w762w763w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w762w(0) AND wire_lbarrel_shift_w761w(i);
END GENERATE loop9;
loop10 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w670w671w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range668w670w(0) AND wire_lbarrel_shift_w_sbit_w_range663w(i);
END GENERATE loop10;
loop11 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w691w692w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range689w691w(0) AND wire_lbarrel_shift_w_sbit_w_range686w(i);
END GENERATE loop11;
loop12 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w713w714w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range711w713w(0) AND wire_lbarrel_shift_w_sbit_w_range706w(i);
END GENERATE loop12;
loop13 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w735w736w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range733w735w(0) AND wire_lbarrel_shift_w_sbit_w_range728w(i);
END GENERATE loop13;
loop14 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w757w758w(i) <= wire_lbarrel_shift_w_lg_w_sel_w_range755w757w(0) AND wire_lbarrel_shift_w_sbit_w_range750w(i);
END GENERATE loop14;
wire_lbarrel_shift_w_lg_w_sel_w_range668w680w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range665w679w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w675w(0) <= wire_lbarrel_shift_w_sel_w_range668w(0) AND wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w701w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range687w700w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w696w(0) <= wire_lbarrel_shift_w_sel_w_range689w(0) AND wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w723w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range708w722w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w718w(0) <= wire_lbarrel_shift_w_sel_w_range711w(0) AND wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w745w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range730w744w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w740w(0) <= wire_lbarrel_shift_w_sel_w_range733w(0) AND wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w767w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_lg_w_dir_w_range752w766w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w762w(0) <= wire_lbarrel_shift_w_sel_w_range755w(0) AND wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range665w679w(0) <= NOT wire_lbarrel_shift_w_dir_w_range665w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range687w700w(0) <= NOT wire_lbarrel_shift_w_dir_w_range687w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range708w722w(0) <= NOT wire_lbarrel_shift_w_dir_w_range708w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range730w744w(0) <= NOT wire_lbarrel_shift_w_dir_w_range730w(0);
wire_lbarrel_shift_w_lg_w_dir_w_range752w766w(0) <= NOT wire_lbarrel_shift_w_dir_w_range752w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range668w670w(0) <= NOT wire_lbarrel_shift_w_sel_w_range668w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range689w691w(0) <= NOT wire_lbarrel_shift_w_sel_w_range689w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range711w713w(0) <= NOT wire_lbarrel_shift_w_sel_w_range711w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range733w735w(0) <= NOT wire_lbarrel_shift_w_sel_w_range733w(0);
wire_lbarrel_shift_w_lg_w_sel_w_range755w757w(0) <= NOT wire_lbarrel_shift_w_sel_w_range755w(0);
loop15 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w680w681w682w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w680w681w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w675w676w(i);
END GENERATE loop15;
loop16 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w701w702w703w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w701w702w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w696w697w(i);
END GENERATE loop16;
loop17 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w723w724w725w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w723w724w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w718w719w(i);
END GENERATE loop17;
loop18 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w745w746w747w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w745w746w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w740w741w(i);
END GENERATE loop18;
loop19 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w767w768w769w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w767w768w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w762w763w(i);
END GENERATE loop19;
loop20 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w683w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range668w680w681w682w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range668w670w671w(i);
END GENERATE loop20;
loop21 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w704w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range689w701w702w703w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range689w691w692w(i);
END GENERATE loop21;
loop22 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w726w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range711w723w724w725w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range711w713w714w(i);
END GENERATE loop22;
loop23 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w748w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range733w745w746w747w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range733w735w736w(i);
END GENERATE loop23;
loop24 : FOR i IN 0 TO 25 GENERATE
wire_lbarrel_shift_w770w(i) <= wire_lbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range755w767w768w769w(i) OR wire_lbarrel_shift_w_lg_w_lg_w_sel_w_range755w757w758w(i);
END GENERATE loop24;
dir_w <= ( dir_pipe(0) & dir_w(3 DOWNTO 0) & direction_w);
direction_w <= '0';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( sbit_piper1d & smux_w(103 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_lbarrel_shift_w770w & wire_lbarrel_shift_w748w & wire_lbarrel_shift_w726w & wire_lbarrel_shift_w704w & wire_lbarrel_shift_w683w);
wire_lbarrel_shift_w674w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_lbarrel_shift_w678w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_lbarrel_shift_w695w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_lbarrel_shift_w699w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_lbarrel_shift_w717w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_lbarrel_shift_w721w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_lbarrel_shift_w739w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_lbarrel_shift_w743w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_lbarrel_shift_w761w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_lbarrel_shift_w765w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_lbarrel_shift_w_dir_w_range665w(0) <= dir_w(0);
wire_lbarrel_shift_w_dir_w_range687w(0) <= dir_w(1);
wire_lbarrel_shift_w_dir_w_range708w(0) <= dir_w(2);
wire_lbarrel_shift_w_dir_w_range730w(0) <= dir_w(3);
wire_lbarrel_shift_w_dir_w_range752w(0) <= dir_w(4);
wire_lbarrel_shift_w_sbit_w_range728w <= sbit_w(103 DOWNTO 78);
wire_lbarrel_shift_w_sbit_w_range750w <= sbit_w(129 DOWNTO 104);
wire_lbarrel_shift_w_sbit_w_range663w <= sbit_w(25 DOWNTO 0);
wire_lbarrel_shift_w_sbit_w_range686w <= sbit_w(51 DOWNTO 26);
wire_lbarrel_shift_w_sbit_w_range706w <= sbit_w(77 DOWNTO 52);
wire_lbarrel_shift_w_sel_w_range668w(0) <= sel_w(0);
wire_lbarrel_shift_w_sel_w_range689w(0) <= sel_w(1);
wire_lbarrel_shift_w_sel_w_range711w(0) <= sel_w(2);
wire_lbarrel_shift_w_sel_w_range733w(0) <= sel_w(3);
wire_lbarrel_shift_w_sel_w_range755w(0) <= sel_w(4);
wire_lbarrel_shift_w_smux_w_range771w <= smux_w(129 DOWNTO 104);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dir_pipe <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dir_pipe(0) <= ( dir_w(4));
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sbit_piper1d <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sbit_piper1d <= wire_lbarrel_shift_w_smux_w_range771w;
END IF;
END IF;
END PROCESS;
END RTL; --fp_sub_altbarrel_shift_h0e
--altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone II" SHIFTDIR="RIGHT" WIDTH=26 WIDTHDIST=5 data distance result
--VERSION_BEGIN 9.1SP2 cbx_altbarrel_shift 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altbarrel_shift_6hb IS
PORT
(
data : IN STD_LOGIC_VECTOR (25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (25 DOWNTO 0)
);
END fp_sub_altbarrel_shift_6hb;
ARCHITECTURE RTL OF fp_sub_altbarrel_shift_6hb IS
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w794w795w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w789w790w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w815w816w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w810w811w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w837w838w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w832w833w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w859w860w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w854w855w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w881w882w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w876w877w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w784w785w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w805w806w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w827w828w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w849w850w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w871w872w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w794w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w789w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w815w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w810w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w837w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w832w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w859w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w854w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w881w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w876w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range779w793w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range801w814w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range822w836w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range844w858w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_dir_w_range866w880w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range782w784w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range803w805w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range825w827w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range847w849w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_sel_w_range869w871w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w794w795w796w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w815w816w817w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w837w838w839w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w859w860w861w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w881w882w883w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w797w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w818w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w840w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w862w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w884w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dir_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL direction_w : STD_LOGIC;
SIGNAL pad_w : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sbit_w : STD_LOGIC_VECTOR (155 DOWNTO 0);
SIGNAL sel_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL smux_w : STD_LOGIC_VECTOR (129 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w788w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w792w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w809w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w813w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w831w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w835w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w853w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w857w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w875w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w879w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range779w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range801w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range822w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range844w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_dir_w_range866w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range842w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range864w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range777w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range800w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sbit_w_range820w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range782w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range803w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range825w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range847w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_rbarrel_shift_w_sel_w_range869w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
loop25 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w794w795w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w794w(0) AND wire_rbarrel_shift_w792w(i);
END GENERATE loop25;
loop26 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w789w790w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w789w(0) AND wire_rbarrel_shift_w788w(i);
END GENERATE loop26;
loop27 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w815w816w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w815w(0) AND wire_rbarrel_shift_w813w(i);
END GENERATE loop27;
loop28 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w810w811w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w810w(0) AND wire_rbarrel_shift_w809w(i);
END GENERATE loop28;
loop29 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w837w838w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w837w(0) AND wire_rbarrel_shift_w835w(i);
END GENERATE loop29;
loop30 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w832w833w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w832w(0) AND wire_rbarrel_shift_w831w(i);
END GENERATE loop30;
loop31 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w859w860w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w859w(0) AND wire_rbarrel_shift_w857w(i);
END GENERATE loop31;
loop32 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w854w855w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w854w(0) AND wire_rbarrel_shift_w853w(i);
END GENERATE loop32;
loop33 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w881w882w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w881w(0) AND wire_rbarrel_shift_w879w(i);
END GENERATE loop33;
loop34 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w876w877w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w876w(0) AND wire_rbarrel_shift_w875w(i);
END GENERATE loop34;
loop35 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w784w785w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range782w784w(0) AND wire_rbarrel_shift_w_sbit_w_range777w(i);
END GENERATE loop35;
loop36 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w805w806w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range803w805w(0) AND wire_rbarrel_shift_w_sbit_w_range800w(i);
END GENERATE loop36;
loop37 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w827w828w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range825w827w(0) AND wire_rbarrel_shift_w_sbit_w_range820w(i);
END GENERATE loop37;
loop38 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w849w850w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range847w849w(0) AND wire_rbarrel_shift_w_sbit_w_range842w(i);
END GENERATE loop38;
loop39 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w871w872w(i) <= wire_rbarrel_shift_w_lg_w_sel_w_range869w871w(0) AND wire_rbarrel_shift_w_sbit_w_range864w(i);
END GENERATE loop39;
wire_rbarrel_shift_w_lg_w_sel_w_range782w794w(0) <= wire_rbarrel_shift_w_sel_w_range782w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range779w793w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range782w789w(0) <= wire_rbarrel_shift_w_sel_w_range782w(0) AND wire_rbarrel_shift_w_dir_w_range779w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w815w(0) <= wire_rbarrel_shift_w_sel_w_range803w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range801w814w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w810w(0) <= wire_rbarrel_shift_w_sel_w_range803w(0) AND wire_rbarrel_shift_w_dir_w_range801w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w837w(0) <= wire_rbarrel_shift_w_sel_w_range825w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range822w836w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w832w(0) <= wire_rbarrel_shift_w_sel_w_range825w(0) AND wire_rbarrel_shift_w_dir_w_range822w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w859w(0) <= wire_rbarrel_shift_w_sel_w_range847w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range844w858w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w854w(0) <= wire_rbarrel_shift_w_sel_w_range847w(0) AND wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w881w(0) <= wire_rbarrel_shift_w_sel_w_range869w(0) AND wire_rbarrel_shift_w_lg_w_dir_w_range866w880w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w876w(0) <= wire_rbarrel_shift_w_sel_w_range869w(0) AND wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range779w793w(0) <= NOT wire_rbarrel_shift_w_dir_w_range779w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range801w814w(0) <= NOT wire_rbarrel_shift_w_dir_w_range801w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range822w836w(0) <= NOT wire_rbarrel_shift_w_dir_w_range822w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range844w858w(0) <= NOT wire_rbarrel_shift_w_dir_w_range844w(0);
wire_rbarrel_shift_w_lg_w_dir_w_range866w880w(0) <= NOT wire_rbarrel_shift_w_dir_w_range866w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range782w784w(0) <= NOT wire_rbarrel_shift_w_sel_w_range782w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range803w805w(0) <= NOT wire_rbarrel_shift_w_sel_w_range803w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range825w827w(0) <= NOT wire_rbarrel_shift_w_sel_w_range825w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range847w849w(0) <= NOT wire_rbarrel_shift_w_sel_w_range847w(0);
wire_rbarrel_shift_w_lg_w_sel_w_range869w871w(0) <= NOT wire_rbarrel_shift_w_sel_w_range869w(0);
loop40 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w794w795w796w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w794w795w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w789w790w(i);
END GENERATE loop40;
loop41 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w815w816w817w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w815w816w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w810w811w(i);
END GENERATE loop41;
loop42 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w837w838w839w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w837w838w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w832w833w(i);
END GENERATE loop42;
loop43 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w859w860w861w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w859w860w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w854w855w(i);
END GENERATE loop43;
loop44 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w881w882w883w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w881w882w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w876w877w(i);
END GENERATE loop44;
loop45 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w797w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range782w794w795w796w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range782w784w785w(i);
END GENERATE loop45;
loop46 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w818w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range803w815w816w817w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range803w805w806w(i);
END GENERATE loop46;
loop47 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w840w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range825w837w838w839w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range825w827w828w(i);
END GENERATE loop47;
loop48 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w862w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range847w859w860w861w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range847w849w850w(i);
END GENERATE loop48;
loop49 : FOR i IN 0 TO 25 GENERATE
wire_rbarrel_shift_w884w(i) <= wire_rbarrel_shift_w_lg_w_lg_w_lg_w_sel_w_range869w881w882w883w(i) OR wire_rbarrel_shift_w_lg_w_lg_w_sel_w_range869w871w872w(i);
END GENERATE loop49;
dir_w <= ( dir_w(4 DOWNTO 0) & direction_w);
direction_w <= '1';
pad_w <= (OTHERS => '0');
result <= sbit_w(155 DOWNTO 130);
sbit_w <= ( smux_w(129 DOWNTO 0) & data);
sel_w <= ( distance(4 DOWNTO 0));
smux_w <= ( wire_rbarrel_shift_w884w & wire_rbarrel_shift_w862w & wire_rbarrel_shift_w840w & wire_rbarrel_shift_w818w & wire_rbarrel_shift_w797w);
wire_rbarrel_shift_w788w <= ( pad_w(0) & sbit_w(25 DOWNTO 1));
wire_rbarrel_shift_w792w <= ( sbit_w(24 DOWNTO 0) & pad_w(0));
wire_rbarrel_shift_w809w <= ( pad_w(1 DOWNTO 0) & sbit_w(51 DOWNTO 28));
wire_rbarrel_shift_w813w <= ( sbit_w(49 DOWNTO 26) & pad_w(1 DOWNTO 0));
wire_rbarrel_shift_w831w <= ( pad_w(3 DOWNTO 0) & sbit_w(77 DOWNTO 56));
wire_rbarrel_shift_w835w <= ( sbit_w(73 DOWNTO 52) & pad_w(3 DOWNTO 0));
wire_rbarrel_shift_w853w <= ( pad_w(7 DOWNTO 0) & sbit_w(103 DOWNTO 86));
wire_rbarrel_shift_w857w <= ( sbit_w(95 DOWNTO 78) & pad_w(7 DOWNTO 0));
wire_rbarrel_shift_w875w <= ( pad_w(15 DOWNTO 0) & sbit_w(129 DOWNTO 120));
wire_rbarrel_shift_w879w <= ( sbit_w(113 DOWNTO 104) & pad_w(15 DOWNTO 0));
wire_rbarrel_shift_w_dir_w_range779w(0) <= dir_w(0);
wire_rbarrel_shift_w_dir_w_range801w(0) <= dir_w(1);
wire_rbarrel_shift_w_dir_w_range822w(0) <= dir_w(2);
wire_rbarrel_shift_w_dir_w_range844w(0) <= dir_w(3);
wire_rbarrel_shift_w_dir_w_range866w(0) <= dir_w(4);
wire_rbarrel_shift_w_sbit_w_range842w <= sbit_w(103 DOWNTO 78);
wire_rbarrel_shift_w_sbit_w_range864w <= sbit_w(129 DOWNTO 104);
wire_rbarrel_shift_w_sbit_w_range777w <= sbit_w(25 DOWNTO 0);
wire_rbarrel_shift_w_sbit_w_range800w <= sbit_w(51 DOWNTO 26);
wire_rbarrel_shift_w_sbit_w_range820w <= sbit_w(77 DOWNTO 52);
wire_rbarrel_shift_w_sel_w_range782w(0) <= sel_w(0);
wire_rbarrel_shift_w_sel_w_range803w(0) <= sel_w(1);
wire_rbarrel_shift_w_sel_w_range825w(0) <= sel_w(2);
wire_rbarrel_shift_w_sel_w_range847w(0) <= sel_w(3);
wire_rbarrel_shift_w_sel_w_range869w(0) <= sel_w(4);
END RTL; --fp_sub_altbarrel_shift_6hb
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=32 WIDTHAD=5 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_3e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_3e8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_3e8 IS
BEGIN
q(0) <= ( data(1));
zero <= (NOT (data(0) OR data(1)));
END RTL; --fp_sub_altpriority_encoder_3e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_6e8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_6e8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_6e8 IS
SIGNAL wire_altpriority_encoder13_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder13_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero920w921w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero922w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_zero920w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_w_lg_w_lg_zero922w923w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder14_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder14_w_lg_zero920w & wire_altpriority_encoder14_w_lg_w_lg_zero922w923w);
zero <= (wire_altpriority_encoder13_zero AND wire_altpriority_encoder14_zero);
altpriority_encoder13 : fp_sub_altpriority_encoder_3e8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder13_q,
zero => wire_altpriority_encoder13_zero
);
wire_altpriority_encoder14_w_lg_w_lg_zero920w921w(0) <= wire_altpriority_encoder14_w_lg_zero920w(0) AND wire_altpriority_encoder14_q(0);
wire_altpriority_encoder14_w_lg_zero922w(0) <= wire_altpriority_encoder14_zero AND wire_altpriority_encoder13_q(0);
wire_altpriority_encoder14_w_lg_zero920w(0) <= NOT wire_altpriority_encoder14_zero;
wire_altpriority_encoder14_w_lg_w_lg_zero922w923w(0) <= wire_altpriority_encoder14_w_lg_zero922w(0) OR wire_altpriority_encoder14_w_lg_w_lg_zero920w921w(0);
altpriority_encoder14 : fp_sub_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder14_q,
zero => wire_altpriority_encoder14_zero
);
END RTL; --fp_sub_altpriority_encoder_6e8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_be8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_be8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_be8 IS
SIGNAL wire_altpriority_encoder11_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder11_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero910w911w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero912w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_zero910w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_w_lg_w_lg_zero912w913w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder12_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder12_w_lg_zero910w & wire_altpriority_encoder12_w_lg_w_lg_zero912w913w);
zero <= (wire_altpriority_encoder11_zero AND wire_altpriority_encoder12_zero);
altpriority_encoder11 : fp_sub_altpriority_encoder_6e8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder11_q,
zero => wire_altpriority_encoder11_zero
);
loop50 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero910w911w(i) <= wire_altpriority_encoder12_w_lg_zero910w(0) AND wire_altpriority_encoder12_q(i);
END GENERATE loop50;
loop51 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_zero912w(i) <= wire_altpriority_encoder12_zero AND wire_altpriority_encoder11_q(i);
END GENERATE loop51;
wire_altpriority_encoder12_w_lg_zero910w(0) <= NOT wire_altpriority_encoder12_zero;
loop52 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder12_w_lg_w_lg_zero912w913w(i) <= wire_altpriority_encoder12_w_lg_zero912w(i) OR wire_altpriority_encoder12_w_lg_w_lg_zero910w911w(i);
END GENERATE loop52;
altpriority_encoder12 : fp_sub_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder12_q,
zero => wire_altpriority_encoder12_zero
);
END RTL; --fp_sub_altpriority_encoder_be8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_3v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END fp_sub_altpriority_encoder_3v7;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_3v7 IS
BEGIN
q(0) <= ( data(1));
END RTL; --fp_sub_altpriority_encoder_3v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_6v7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END fp_sub_altpriority_encoder_6v7;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_6v7 IS
SIGNAL wire_altpriority_encoder17_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero945w946w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero947w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_zero945w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_w_lg_w_lg_zero947w948w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder18_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_3v7
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_3e8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder18_w_lg_zero945w & wire_altpriority_encoder18_w_lg_w_lg_zero947w948w);
altpriority_encoder17 : fp_sub_altpriority_encoder_3v7
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder17_q
);
wire_altpriority_encoder18_w_lg_w_lg_zero945w946w(0) <= wire_altpriority_encoder18_w_lg_zero945w(0) AND wire_altpriority_encoder18_q(0);
wire_altpriority_encoder18_w_lg_zero947w(0) <= wire_altpriority_encoder18_zero AND wire_altpriority_encoder17_q(0);
wire_altpriority_encoder18_w_lg_zero945w(0) <= NOT wire_altpriority_encoder18_zero;
wire_altpriority_encoder18_w_lg_w_lg_zero947w948w(0) <= wire_altpriority_encoder18_w_lg_zero947w(0) OR wire_altpriority_encoder18_w_lg_w_lg_zero945w946w(0);
altpriority_encoder18 : fp_sub_altpriority_encoder_3e8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder18_q,
zero => wire_altpriority_encoder18_zero
);
END RTL; --fp_sub_altpriority_encoder_6v7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_bv7 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END fp_sub_altpriority_encoder_bv7;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_bv7 IS
SIGNAL wire_altpriority_encoder15_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero936w937w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero938w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_zero936w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_w_lg_w_lg_zero938w939w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder16_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_6v7
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_6e8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder16_w_lg_zero936w & wire_altpriority_encoder16_w_lg_w_lg_zero938w939w);
altpriority_encoder15 : fp_sub_altpriority_encoder_6v7
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder15_q
);
loop53 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero936w937w(i) <= wire_altpriority_encoder16_w_lg_zero936w(0) AND wire_altpriority_encoder16_q(i);
END GENERATE loop53;
loop54 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_zero938w(i) <= wire_altpriority_encoder16_zero AND wire_altpriority_encoder15_q(i);
END GENERATE loop54;
wire_altpriority_encoder16_w_lg_zero936w(0) <= NOT wire_altpriority_encoder16_zero;
loop55 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder16_w_lg_w_lg_zero938w939w(i) <= wire_altpriority_encoder16_w_lg_zero938w(i) OR wire_altpriority_encoder16_w_lg_w_lg_zero936w937w(i);
END GENERATE loop55;
altpriority_encoder16 : fp_sub_altpriority_encoder_6e8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder16_q,
zero => wire_altpriority_encoder16_zero
);
END RTL; --fp_sub_altpriority_encoder_bv7
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_r08 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END fp_sub_altpriority_encoder_r08;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_r08 IS
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero901w902w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero903w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_zero901w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_w_lg_w_lg_zero903w904w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder10_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder9_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_bv7
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder10_w_lg_zero901w & wire_altpriority_encoder10_w_lg_w_lg_zero903w904w);
loop56 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero901w902w(i) <= wire_altpriority_encoder10_w_lg_zero901w(0) AND wire_altpriority_encoder10_q(i);
END GENERATE loop56;
loop57 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_zero903w(i) <= wire_altpriority_encoder10_zero AND wire_altpriority_encoder9_q(i);
END GENERATE loop57;
wire_altpriority_encoder10_w_lg_zero901w(0) <= NOT wire_altpriority_encoder10_zero;
loop58 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder10_w_lg_w_lg_zero903w904w(i) <= wire_altpriority_encoder10_w_lg_zero903w(i) OR wire_altpriority_encoder10_w_lg_w_lg_zero901w902w(i);
END GENERATE loop58;
altpriority_encoder10 : fp_sub_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder10_q,
zero => wire_altpriority_encoder10_zero
);
altpriority_encoder9 : fp_sub_altpriority_encoder_bv7
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder9_q
);
END RTL; --fp_sub_altpriority_encoder_r08
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_rf8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_rf8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_rf8 IS
SIGNAL wire_altpriority_encoder19_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder19_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero957w958w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero959w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_zero957w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_w_lg_w_lg_zero959w960w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder20_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_be8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder20_w_lg_zero957w & wire_altpriority_encoder20_w_lg_w_lg_zero959w960w);
zero <= (wire_altpriority_encoder19_zero AND wire_altpriority_encoder20_zero);
altpriority_encoder19 : fp_sub_altpriority_encoder_be8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder19_q,
zero => wire_altpriority_encoder19_zero
);
loop59 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero957w958w(i) <= wire_altpriority_encoder20_w_lg_zero957w(0) AND wire_altpriority_encoder20_q(i);
END GENERATE loop59;
loop60 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_zero959w(i) <= wire_altpriority_encoder20_zero AND wire_altpriority_encoder19_q(i);
END GENERATE loop60;
wire_altpriority_encoder20_w_lg_zero957w(0) <= NOT wire_altpriority_encoder20_zero;
loop61 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder20_w_lg_w_lg_zero959w960w(i) <= wire_altpriority_encoder20_w_lg_zero959w(i) OR wire_altpriority_encoder20_w_lg_w_lg_zero957w958w(i);
END GENERATE loop61;
altpriority_encoder20 : fp_sub_altpriority_encoder_be8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder20_q,
zero => wire_altpriority_encoder20_zero
);
END RTL; --fp_sub_altpriority_encoder_rf8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_qb6 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END fp_sub_altpriority_encoder_qb6;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_qb6 IS
SIGNAL wire_altpriority_encoder7_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero892w893w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero894w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_zero892w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_w_lg_w_lg_zero894w895w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder8_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_r08
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_rf8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder8_w_lg_zero892w & wire_altpriority_encoder8_w_lg_w_lg_zero894w895w);
altpriority_encoder7 : fp_sub_altpriority_encoder_r08
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder7_q
);
loop62 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i) <= wire_altpriority_encoder8_w_lg_zero892w(0) AND wire_altpriority_encoder8_q(i);
END GENERATE loop62;
loop63 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_zero894w(i) <= wire_altpriority_encoder8_zero AND wire_altpriority_encoder7_q(i);
END GENERATE loop63;
wire_altpriority_encoder8_w_lg_zero892w(0) <= NOT wire_altpriority_encoder8_zero;
loop64 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder8_w_lg_w_lg_zero894w895w(i) <= wire_altpriority_encoder8_w_lg_zero894w(i) OR wire_altpriority_encoder8_w_lg_w_lg_zero892w893w(i);
END GENERATE loop64;
altpriority_encoder8 : fp_sub_altpriority_encoder_rf8
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder8_q,
zero => wire_altpriority_encoder8_zero
);
END RTL; --fp_sub_altpriority_encoder_qb6
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=32 WIDTHAD=5 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=16 WIDTHAD=4 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q zero
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_nh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_nh8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_nh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_data_range1004w1005w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_data_range1004w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder27_w_lg_w_data_range1004w1005w(0) <= NOT wire_altpriority_encoder27_w_data_range1004w(0);
q <= ( wire_altpriority_encoder27_w_lg_w_data_range1004w1005w);
zero <= (NOT (data(0) OR data(1)));
wire_altpriority_encoder27_w_data_range1004w(0) <= data(0);
END RTL; --fp_sub_altpriority_encoder_nh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_qh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_qh8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_qh8 IS
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero996w997w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero998w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_zero996w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_w_lg_w_lg_zero998w999w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder27_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder28_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder28_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder27_zero & wire_altpriority_encoder27_w_lg_w_lg_zero998w999w);
zero <= (wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_zero);
wire_altpriority_encoder27_w_lg_w_lg_zero996w997w(0) <= wire_altpriority_encoder27_w_lg_zero996w(0) AND wire_altpriority_encoder27_q(0);
wire_altpriority_encoder27_w_lg_zero998w(0) <= wire_altpriority_encoder27_zero AND wire_altpriority_encoder28_q(0);
wire_altpriority_encoder27_w_lg_zero996w(0) <= NOT wire_altpriority_encoder27_zero;
wire_altpriority_encoder27_w_lg_w_lg_zero998w999w(0) <= wire_altpriority_encoder27_w_lg_zero998w(0) OR wire_altpriority_encoder27_w_lg_w_lg_zero996w997w(0);
altpriority_encoder27 : fp_sub_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder27_q,
zero => wire_altpriority_encoder27_zero
);
altpriority_encoder28 : fp_sub_altpriority_encoder_nh8
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder28_q,
zero => wire_altpriority_encoder28_zero
);
END RTL; --fp_sub_altpriority_encoder_qh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_vh8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_vh8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_vh8 IS
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero986w987w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero988w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_zero986w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_w_lg_w_lg_zero988w989w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder25_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder26_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder26_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder25_zero & wire_altpriority_encoder25_w_lg_w_lg_zero988w989w);
zero <= (wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_zero);
loop65 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero986w987w(i) <= wire_altpriority_encoder25_w_lg_zero986w(0) AND wire_altpriority_encoder25_q(i);
END GENERATE loop65;
loop66 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_zero988w(i) <= wire_altpriority_encoder25_zero AND wire_altpriority_encoder26_q(i);
END GENERATE loop66;
wire_altpriority_encoder25_w_lg_zero986w(0) <= NOT wire_altpriority_encoder25_zero;
loop67 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder25_w_lg_w_lg_zero988w989w(i) <= wire_altpriority_encoder25_w_lg_zero988w(i) OR wire_altpriority_encoder25_w_lg_w_lg_zero986w987w(i);
END GENERATE loop67;
altpriority_encoder25 : fp_sub_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder25_q,
zero => wire_altpriority_encoder25_zero
);
altpriority_encoder26 : fp_sub_altpriority_encoder_qh8
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder26_q,
zero => wire_altpriority_encoder26_zero
);
END RTL; --fp_sub_altpriority_encoder_vh8
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_fj8 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END fp_sub_altpriority_encoder_fj8;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_fj8 IS
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero976w977w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero978w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_zero976w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_w_lg_w_lg_zero978w979w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder23_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder24_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder24_zero : STD_LOGIC;
COMPONENT fp_sub_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder23_zero & wire_altpriority_encoder23_w_lg_w_lg_zero978w979w);
zero <= (wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_zero);
loop68 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero976w977w(i) <= wire_altpriority_encoder23_w_lg_zero976w(0) AND wire_altpriority_encoder23_q(i);
END GENERATE loop68;
loop69 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_zero978w(i) <= wire_altpriority_encoder23_zero AND wire_altpriority_encoder24_q(i);
END GENERATE loop69;
wire_altpriority_encoder23_w_lg_zero976w(0) <= NOT wire_altpriority_encoder23_zero;
loop70 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder23_w_lg_w_lg_zero978w979w(i) <= wire_altpriority_encoder23_w_lg_zero978w(i) OR wire_altpriority_encoder23_w_lg_w_lg_zero976w977w(i);
END GENERATE loop70;
altpriority_encoder23 : fp_sub_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder23_q,
zero => wire_altpriority_encoder23_zero
);
altpriority_encoder24 : fp_sub_altpriority_encoder_vh8
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder24_q,
zero => wire_altpriority_encoder24_zero
);
END RTL; --fp_sub_altpriority_encoder_fj8
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=16 WIDTHAD=4 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=8 WIDTHAD=3 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=4 WIDTHAD=2 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="YES" WIDTH=2 WIDTHAD=1 data q
--VERSION_BEGIN 9.1SP2 cbx_altpriority_encoder 2010:03:24:20:34:20:SJ cbx_mgl 2010:03:24:20:44:08:SJ VERSION_END
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_n28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END fp_sub_altpriority_encoder_n28;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_n28 IS
SIGNAL wire_altpriority_encoder34_w_lg_w_data_range1038w1039w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder34_w_data_range1038w : STD_LOGIC_VECTOR (0 DOWNTO 0);
BEGIN
wire_altpriority_encoder34_w_lg_w_data_range1038w1039w(0) <= NOT wire_altpriority_encoder34_w_data_range1038w(0);
q <= ( wire_altpriority_encoder34_w_lg_w_data_range1038w1039w);
wire_altpriority_encoder34_w_data_range1038w(0) <= data(0);
END RTL; --fp_sub_altpriority_encoder_n28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_q28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END fp_sub_altpriority_encoder_q28;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_q28 IS
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1033w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_zero1031w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder33_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder34_q : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_nh8
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_n28
PORT
(
data : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder33_zero & wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w);
wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w(0) <= wire_altpriority_encoder33_w_lg_zero1031w(0) AND wire_altpriority_encoder33_q(0);
wire_altpriority_encoder33_w_lg_zero1033w(0) <= wire_altpriority_encoder33_zero AND wire_altpriority_encoder34_q(0);
wire_altpriority_encoder33_w_lg_zero1031w(0) <= NOT wire_altpriority_encoder33_zero;
wire_altpriority_encoder33_w_lg_w_lg_zero1033w1034w(0) <= wire_altpriority_encoder33_w_lg_zero1033w(0) OR wire_altpriority_encoder33_w_lg_w_lg_zero1031w1032w(0);
altpriority_encoder33 : fp_sub_altpriority_encoder_nh8
PORT MAP (
data => data(1 DOWNTO 0),
q => wire_altpriority_encoder33_q,
zero => wire_altpriority_encoder33_zero
);
altpriority_encoder34 : fp_sub_altpriority_encoder_n28
PORT MAP (
data => data(3 DOWNTO 2),
q => wire_altpriority_encoder34_q
);
END RTL; --fp_sub_altpriority_encoder_q28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_v28 IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END fp_sub_altpriority_encoder_v28;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_v28 IS
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1024w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_zero1022w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_altpriority_encoder31_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder32_q : STD_LOGIC_VECTOR (1 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_qh8
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_q28
PORT
(
data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder31_zero & wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w);
loop71 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w(i) <= wire_altpriority_encoder31_w_lg_zero1022w(0) AND wire_altpriority_encoder31_q(i);
END GENERATE loop71;
loop72 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_zero1024w(i) <= wire_altpriority_encoder31_zero AND wire_altpriority_encoder32_q(i);
END GENERATE loop72;
wire_altpriority_encoder31_w_lg_zero1022w(0) <= NOT wire_altpriority_encoder31_zero;
loop73 : FOR i IN 0 TO 1 GENERATE
wire_altpriority_encoder31_w_lg_w_lg_zero1024w1025w(i) <= wire_altpriority_encoder31_w_lg_zero1024w(i) OR wire_altpriority_encoder31_w_lg_w_lg_zero1022w1023w(i);
END GENERATE loop73;
altpriority_encoder31 : fp_sub_altpriority_encoder_qh8
PORT MAP (
data => data(3 DOWNTO 0),
q => wire_altpriority_encoder31_q,
zero => wire_altpriority_encoder31_zero
);
altpriority_encoder32 : fp_sub_altpriority_encoder_q28
PORT MAP (
data => data(7 DOWNTO 4),
q => wire_altpriority_encoder32_q
);
END RTL; --fp_sub_altpriority_encoder_v28
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_f48 IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END fp_sub_altpriority_encoder_f48;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_f48 IS
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1015w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_zero1013w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL wire_altpriority_encoder29_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder30_q : STD_LOGIC_VECTOR (2 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_vh8
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_v28
PORT
(
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder29_zero & wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w);
loop74 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w(i) <= wire_altpriority_encoder29_w_lg_zero1013w(0) AND wire_altpriority_encoder29_q(i);
END GENERATE loop74;
loop75 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_zero1015w(i) <= wire_altpriority_encoder29_zero AND wire_altpriority_encoder30_q(i);
END GENERATE loop75;
wire_altpriority_encoder29_w_lg_zero1013w(0) <= NOT wire_altpriority_encoder29_zero;
loop76 : FOR i IN 0 TO 2 GENERATE
wire_altpriority_encoder29_w_lg_w_lg_zero1015w1016w(i) <= wire_altpriority_encoder29_w_lg_zero1015w(i) OR wire_altpriority_encoder29_w_lg_w_lg_zero1013w1014w(i);
END GENERATE loop76;
altpriority_encoder29 : fp_sub_altpriority_encoder_vh8
PORT MAP (
data => data(7 DOWNTO 0),
q => wire_altpriority_encoder29_q,
zero => wire_altpriority_encoder29_zero
);
altpriority_encoder30 : fp_sub_altpriority_encoder_v28
PORT MAP (
data => data(15 DOWNTO 8),
q => wire_altpriority_encoder30_q
);
END RTL; --fp_sub_altpriority_encoder_f48
--synthesis_resources =
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altpriority_encoder_e48 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END fp_sub_altpriority_encoder_e48;
ARCHITECTURE RTL OF fp_sub_altpriority_encoder_e48 IS
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero967w968w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero969w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_zero967w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_w_lg_w_lg_zero969w970w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_altpriority_encoder21_zero : STD_LOGIC;
SIGNAL wire_altpriority_encoder22_q : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT fp_sub_altpriority_encoder_fj8
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
zero : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_f48
PORT
(
data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= ( wire_altpriority_encoder21_zero & wire_altpriority_encoder21_w_lg_w_lg_zero969w970w);
loop77 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero967w968w(i) <= wire_altpriority_encoder21_w_lg_zero967w(0) AND wire_altpriority_encoder21_q(i);
END GENERATE loop77;
loop78 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_zero969w(i) <= wire_altpriority_encoder21_zero AND wire_altpriority_encoder22_q(i);
END GENERATE loop78;
wire_altpriority_encoder21_w_lg_zero967w(0) <= NOT wire_altpriority_encoder21_zero;
loop79 : FOR i IN 0 TO 3 GENERATE
wire_altpriority_encoder21_w_lg_w_lg_zero969w970w(i) <= wire_altpriority_encoder21_w_lg_zero969w(i) OR wire_altpriority_encoder21_w_lg_w_lg_zero967w968w(i);
END GENERATE loop79;
altpriority_encoder21 : fp_sub_altpriority_encoder_fj8
PORT MAP (
data => data(15 DOWNTO 0),
q => wire_altpriority_encoder21_q,
zero => wire_altpriority_encoder21_zero
);
altpriority_encoder22 : fp_sub_altpriority_encoder_f48
PORT MAP (
data => data(31 DOWNTO 16),
q => wire_altpriority_encoder22_q
);
END RTL; --fp_sub_altpriority_encoder_e48
LIBRARY lpm;
USE lpm.all;
--synthesis_resources = lpm_add_sub 14 lpm_compare 1 reg 282
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub_altfp_add_sub_24k IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sub_altfp_add_sub_24k;
ARCHITECTURE RTL OF fp_sub_altfp_add_sub_24k IS
SIGNAL wire_lbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_data : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_leading_zeroes_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_data : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_trailing_zeros_cnt_q : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL both_inputs_are_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL data_exp_dffe1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL dataa_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL datab_man_dffe1 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL datab_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL denormal_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_adj_dffe21 : STD_LOGIC_VECTOR(1 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_out_dffe5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe21 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_res_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_output_sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinite_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL infinity_magnitude_sub_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinite_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_add_sub_res_mag_dffe21 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_add_sub_res_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_dffe31 : STD_LOGIC_VECTOR(25 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_leading_zeros_dffe31 : STD_LOGIC_VECTOR(4 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_out_dffe5 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_dffe4 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_res_is_not_zero_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL need_complement_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL round_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL rounded_res_infinity_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_out_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_res_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sticky_bit_dffe31 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL zero_man_sign_dffe21 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_add_sub1_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub2_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub3_result : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_add_sub4_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub5_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_add_sub6_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout366w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_cout367w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_2comp_res_lower_cout : STD_LOGIC;
SIGNAL wire_man_2comp_res_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_gnd : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_vcc : STD_LOGIC;
SIGNAL wire_man_2comp_res_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_cout354w355w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout353w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_cout354w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_add_sub_lower_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper0_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_add_sub_upper1_result : STD_LOGIC_VECTOR (13 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout579w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_cout580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_lower_cout : STD_LOGIC;
SIGNAL wire_man_res_rounding_add_sub_lower_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_man_res_rounding_add_sub_upper1_result : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL wire_trailing_zeros_limit_comparator_agb : STD_LOGIC;
SIGNAL wire_w248w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w267w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w397w407w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_denormal_result_w558w559w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w275w278w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_exp_amb_mux_w275w276w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w639w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w648w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w629w654w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w642w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_nan_w630w651w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_input_datab_infinite_dffe15_wo338w339w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w292w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w397w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w383w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w412w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w587w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w637w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w646w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo330w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo323w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo314w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w279w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w273w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w640w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w649w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w643w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w652w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo337w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo376w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w33w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_a_all_one_w_range84w220w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_b_all_one_w_range86w226w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range540w542w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range543w544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range545w546w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range547w548w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range553w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_max_w_range555w561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range601w604w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range605w607w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range608w610w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range611w613w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range614w616w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range617w619w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_rounded_res_max_w_range620w622w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w379w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_zero_w634w635w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_dffe25_wo491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_add_sub_w2342w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_aligned_datab_sign_dffe15_wo336w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_denormal_result_w558w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_dffe15_wo316w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_exp_amb_mux_w275w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_infinity_w629w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_nan_w630w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w628w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_denormal_dffe11_wo233w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_infinite_dffe11_wo246w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_dataa_zero_dffe11_wo245w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_denormal_dffe11_wo252w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe11_wo265w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_infinite_dffe15_wo338w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_datab_zero_dffe11_wo264w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_is_not_zero_dffe4_wo627w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_man_res_not_zero_dffe26_wo503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_need_complement_dffe22_wo373w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe1_wo343w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_a_not_zero_w_range215w219w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_add_sub_w_range372w375w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_b_not_zero_w_range218w225w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w640w641w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_force_infinity_w649w650w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_lg_force_zero_w634w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_sticky_bit_dffe27_wo402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range141w142w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range147w148w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range153w154w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range159w160w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range165w166w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range171w172w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range177w178w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range183w184w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range189w190w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range195w196w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range201w202w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range207w208w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range213w214w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range17w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range27w28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range37w38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range47w48w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range57w58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range67w68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range93w94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range77w78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range99w100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range105w106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range111w112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range117w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range123w124w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range129w130w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_dataa_range135w136w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range144w145w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range150w151w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range156w157w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range162w163w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range168w169w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range174w175w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range180w181w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range186w187w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range192w193w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range198w199w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range90w91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range204w205w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range210w211w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range216w217w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range20w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range30w31w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range40w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range50w51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range60w61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range70w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range96w97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range80w81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range102w103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range108w109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range114w115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range120w121w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range126w127w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range132w133w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_datab_range138w139w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range516w519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range520w522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range523w525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range526w528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range529w531w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range532w534w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range535w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_res_not_zero_w_range538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range417w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range448w450w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range451w453w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range454w456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range457w459w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range460w462w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range463w465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range466w468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range469w471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range472w474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range475w477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range421w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range478w480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range481w483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range484w486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range487w489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range424w426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range427w429w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range430w432w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range433w435w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range436w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range439w441w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range442w444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_res_not_zero_w2_range445w447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL add_sub_dffe25_wi : STD_LOGIC;
SIGNAL add_sub_dffe25_wo : STD_LOGIC;
SIGNAL add_sub_w2 : STD_LOGIC;
SIGNAL adder_upper_w : STD_LOGIC_VECTOR (12 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_dataa_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_dataa_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_dataa_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_dataa_sign_w : STD_LOGIC;
SIGNAL aligned_datab_exp_dffe12_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe12_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe13_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe14_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_dffe15_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_exp_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe12_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe14_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_dffe15_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL aligned_datab_man_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL aligned_datab_sign_dffe12_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe12_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe13_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe14_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wi : STD_LOGIC;
SIGNAL aligned_datab_sign_dffe15_wo : STD_LOGIC;
SIGNAL aligned_datab_sign_w : STD_LOGIC;
SIGNAL borrow_w : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe1_wo : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wi : STD_LOGIC;
SIGNAL both_inputs_are_infinite_dffe25_wo : STD_LOGIC;
SIGNAL data_exp_dffe1_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL data_exp_dffe1_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL dataa_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL dataa_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL dataa_sign_dffe1_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe1_wo : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wi : STD_LOGIC;
SIGNAL dataa_sign_dffe25_wo : STD_LOGIC;
SIGNAL datab_dffe11_wi : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_dffe11_wo : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL datab_man_dffe1_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_man_dffe1_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL datab_sign_dffe1_wi : STD_LOGIC;
SIGNAL datab_sign_dffe1_wo : STD_LOGIC;
SIGNAL denormal_flag_w : STD_LOGIC;
SIGNAL denormal_res_dffe32_wi : STD_LOGIC;
SIGNAL denormal_res_dffe32_wo : STD_LOGIC;
SIGNAL denormal_res_dffe33_wi : STD_LOGIC;
SIGNAL denormal_res_dffe33_wo : STD_LOGIC;
SIGNAL denormal_res_dffe3_wi : STD_LOGIC;
SIGNAL denormal_res_dffe3_wo : STD_LOGIC;
SIGNAL denormal_res_dffe41_wi : STD_LOGIC;
SIGNAL denormal_res_dffe41_wo : STD_LOGIC;
SIGNAL denormal_res_dffe42_wi : STD_LOGIC;
SIGNAL denormal_res_dffe42_wo : STD_LOGIC;
SIGNAL denormal_res_dffe4_wi : STD_LOGIC;
SIGNAL denormal_res_dffe4_wo : STD_LOGIC;
SIGNAL denormal_result_w : STD_LOGIC;
SIGNAL exp_a_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_a_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_adj_0pads : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL exp_adj_dffe21_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe21_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe23_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wi : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adj_dffe26_wo : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjust_by_add2 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment2_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_datab_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_adjustment_add_sub_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_all_zeros_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_amb_mux_dffe13_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe13_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe14_wo : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wi : STD_LOGIC;
SIGNAL exp_amb_mux_dffe15_wo : STD_LOGIC;
SIGNAL exp_amb_mux_w : STD_LOGIC;
SIGNAL exp_amb_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_b_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_b_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bma_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_diff_abs_exceed_max_w : STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL exp_diff_abs_max_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL exp_diff_abs_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe41_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_dffe42_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_intermediate_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_dffe5_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe21_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe22_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe23_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe25_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe26_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe27_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe2_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe32_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe33_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe3_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_dffe4_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_res_not_zero_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_dataa_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_res_rounding_adder_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_rounded_res_infinity_w : STD_LOGIC;
SIGNAL exp_rounded_res_max_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounded_res_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_rounding_adjustment_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL force_infinity_w : STD_LOGIC;
SIGNAL force_nan_w : STD_LOGIC;
SIGNAL force_zero_w : STD_LOGIC;
SIGNAL guard_bit_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe1_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe21_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe22_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe23_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe25_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe26_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe27_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe2_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe31_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe32_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe33_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe3_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe41_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe42_wo : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wi : STD_LOGIC;
SIGNAL infinite_output_sign_dffe4_wo : STD_LOGIC;
SIGNAL infinite_res_dff32_wi : STD_LOGIC;
SIGNAL infinite_res_dff32_wo : STD_LOGIC;
SIGNAL infinite_res_dff33_wi : STD_LOGIC;
SIGNAL infinite_res_dff33_wo : STD_LOGIC;
SIGNAL infinite_res_dffe3_wi : STD_LOGIC;
SIGNAL infinite_res_dffe3_wo : STD_LOGIC;
SIGNAL infinite_res_dffe41_wi : STD_LOGIC;
SIGNAL infinite_res_dffe41_wo : STD_LOGIC;
SIGNAL infinite_res_dffe42_wi : STD_LOGIC;
SIGNAL infinite_res_dffe42_wo : STD_LOGIC;
SIGNAL infinite_res_dffe4_wi : STD_LOGIC;
SIGNAL infinite_res_dffe4_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe21_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe22_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe23_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe26_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe27_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe2_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe31_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe32_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe33_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe3_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe41_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe42_wo : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wi : STD_LOGIC;
SIGNAL infinity_magnitude_sub_dffe4_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_denormal_w : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_dataa_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_dataa_infinite_w : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_dataa_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_dataa_nan_w : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_dataa_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_dataa_zero_w : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_denormal_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_denormal_w : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe13_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe14_wo : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wi : STD_LOGIC;
SIGNAL input_datab_infinite_dffe15_wo : STD_LOGIC;
SIGNAL input_datab_infinite_w : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wi : STD_LOGIC;
SIGNAL input_datab_nan_dffe12_wo : STD_LOGIC;
SIGNAL input_datab_nan_w : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wi : STD_LOGIC;
SIGNAL input_datab_zero_dffe11_wo : STD_LOGIC;
SIGNAL input_datab_zero_w : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe1_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe21_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe22_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe23_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe25_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe26_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe27_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe2_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe31_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe32_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe33_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe3_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe41_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe42_wo : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wi : STD_LOGIC;
SIGNAL input_is_infinite_dffe4_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe13_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe14_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe15_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe1_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe21_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe22_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe23_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe25_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe26_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe27_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe2_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe31_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe32_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe33_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe3_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe41_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe42_wo : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wi : STD_LOGIC;
SIGNAL input_is_nan_dffe4_wo : STD_LOGIC;
SIGNAL man_2comp_res_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_2comp_res_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_a_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_add_sub_dataa_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_datab_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe21_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe23_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wi : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe26_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wi : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_dffe27_wo : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_mag_w2 : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_add_sub_res_sign_dffe21_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe23_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe26_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wi : STD_LOGIC;
SIGNAL man_add_sub_res_sign_dffe27_wo : STD_LOGIC;
SIGNAL man_add_sub_res_sign_w2 : STD_LOGIC;
SIGNAL man_add_sub_w : STD_LOGIC_VECTOR (27 DOWNTO 0);
SIGNAL man_all_zeros_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_b_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_dffe31_wo : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_intermediate_res_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_leading_zeros_cnt_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_leading_zeros_dffe31_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL man_nan_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_out_dffe5_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_dffe4_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_res_is_not_zero_dffe31_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe31_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe32_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe33_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe3_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe41_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe42_wo : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wi : STD_LOGIC;
SIGNAL man_res_is_not_zero_dffe4_wo : STD_LOGIC;
SIGNAL man_res_mag_w2 : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_not_zero_dffe23_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe23_wo : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wi : STD_LOGIC;
SIGNAL man_res_not_zero_dffe26_wo : STD_LOGIC;
SIGNAL man_res_not_zero_w2 : STD_LOGIC_VECTOR (24 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_datab_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_rounding_add_sub_w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL man_res_w3 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_rounded_res_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_rounding_add_value_w : STD_LOGIC;
SIGNAL man_smaller_dffe13_wi : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_dffe13_wo : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL man_smaller_w : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL need_complement_dffe22_wi : STD_LOGIC;
SIGNAL need_complement_dffe22_wo : STD_LOGIC;
SIGNAL need_complement_dffe2_wi : STD_LOGIC;
SIGNAL need_complement_dffe2_wo : STD_LOGIC;
SIGNAL pos_sign_bit_ext : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL priority_encoder_1pads_w : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL round_bit_dffe21_wi : STD_LOGIC;
SIGNAL round_bit_dffe21_wo : STD_LOGIC;
SIGNAL round_bit_dffe23_wi : STD_LOGIC;
SIGNAL round_bit_dffe23_wo : STD_LOGIC;
SIGNAL round_bit_dffe26_wi : STD_LOGIC;
SIGNAL round_bit_dffe26_wo : STD_LOGIC;
SIGNAL round_bit_dffe31_wi : STD_LOGIC;
SIGNAL round_bit_dffe31_wo : STD_LOGIC;
SIGNAL round_bit_dffe32_wi : STD_LOGIC;
SIGNAL round_bit_dffe32_wo : STD_LOGIC;
SIGNAL round_bit_dffe33_wi : STD_LOGIC;
SIGNAL round_bit_dffe33_wo : STD_LOGIC;
SIGNAL round_bit_dffe3_wi : STD_LOGIC;
SIGNAL round_bit_dffe3_wo : STD_LOGIC;
SIGNAL round_bit_w : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wi : STD_LOGIC;
SIGNAL rounded_res_infinity_dffe4_wo : STD_LOGIC;
SIGNAL rshift_distance_dffe13_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe13_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe14_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wi : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_dffe15_wo : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL rshift_distance_w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sign_dffe31_wi : STD_LOGIC;
SIGNAL sign_dffe31_wo : STD_LOGIC;
SIGNAL sign_dffe32_wi : STD_LOGIC;
SIGNAL sign_dffe32_wo : STD_LOGIC;
SIGNAL sign_dffe33_wi : STD_LOGIC;
SIGNAL sign_dffe33_wo : STD_LOGIC;
SIGNAL sign_out_dffe5_wi : STD_LOGIC;
SIGNAL sign_out_dffe5_wo : STD_LOGIC;
SIGNAL sign_res_dffe3_wi : STD_LOGIC;
SIGNAL sign_res_dffe3_wo : STD_LOGIC;
SIGNAL sign_res_dffe41_wi : STD_LOGIC;
SIGNAL sign_res_dffe41_wo : STD_LOGIC;
SIGNAL sign_res_dffe42_wi : STD_LOGIC;
SIGNAL sign_res_dffe42_wo : STD_LOGIC;
SIGNAL sign_res_dffe4_wi : STD_LOGIC;
SIGNAL sign_res_dffe4_wo : STD_LOGIC;
SIGNAL sticky_bit_cnt_dataa_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_datab_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_cnt_res_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sticky_bit_dffe1_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe1_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe21_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe22_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe23_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe25_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe26_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe27_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe2_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe31_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe32_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe33_wo : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wi : STD_LOGIC;
SIGNAL sticky_bit_dffe3_wo : STD_LOGIC;
SIGNAL sticky_bit_w : STD_LOGIC;
SIGNAL trailing_zeros_limit_w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL zero_man_sign_dffe21_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe21_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe22_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe23_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe26_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe27_wo : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wi : STD_LOGIC;
SIGNAL zero_man_sign_dffe2_wo : STD_LOGIC;
SIGNAL wire_w_aligned_dataa_exp_dffe15_wo_range315w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_aligned_datab_exp_dffe15_wo_range313w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_dataa_range141w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range147w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range153w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range159w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range165w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range171w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range177w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range183w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range189w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range195w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range201w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range207w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range213w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range117w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range123w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range129w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_range135w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range242w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_dataa_dffe11_wo_range232w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_datab_range144w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range150w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range156w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range162w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range168w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range174w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range180w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range186w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range192w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range198w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range204w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range210w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range216w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range50w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range120w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range126w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range132w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_range138w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range261w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_datab_dffe11_wo_range251w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range7w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_all_one_w_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range2w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range29w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_a_not_zero_w_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range533w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_adjustment2_add_sub_w_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_amb_w_range274w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range9w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_all_one_w_range86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_b_not_zero_w_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_bma_w_range272w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range282w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range286w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_exceed_max_w_range289w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range290w : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range284w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_diff_abs_w_range287w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range540w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range545w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range547w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_max_w_range555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range529w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range532w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range535w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_res_not_zero_w_range538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range601w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range605w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range608w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range611w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range614w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range617w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_max_w_range620w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range603w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range606w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range609w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range612w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range615w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range618w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_rounded_res_w_range621w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range143w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range149w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range155w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range161w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range167w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range173w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range179w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range185w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range191w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range197w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range203w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range209w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range215w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range125w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_a_not_zero_w_range137w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range449w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range452w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range458w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range461w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range464w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range425w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range428w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range431w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe21_wo_range440w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range396w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range411w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range387w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range413w : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_w_man_add_sub_res_mag_dffe27_wo_range381w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_add_sub_w_range372w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range146w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range152w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range164w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range170w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range176w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range182w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range188w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range194w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range200w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range206w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range212w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range218w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range122w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range128w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range134w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_b_not_zero_w_range140w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range451w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range454w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range457w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range460w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range427w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range430w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range433w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_not_zero_w2_range445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range584w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range588w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_w_man_res_rounding_add_sub_w_range585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT fp_sub_altbarrel_shift_h0e
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altbarrel_shift_6hb
PORT
(
data : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
distance : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_qb6
PORT
(
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT fp_sub_altpriority_encoder_e48
PORT
(
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
wire_gnd <= '0';
wire_vcc <= '1';
wire_w248w(0) <= wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) AND wire_w_lg_input_dataa_zero_dffe11_wo245w(0);
wire_w267w(0) <= wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) AND wire_w_lg_input_datab_zero_dffe11_wo264w(0);
wire_w_lg_w397w407w(0) <= wire_w397w(0) AND sticky_bit_dffe27_wo;
loop80 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND exp_res_dffe4_wo(i);
END GENERATE loop80;
loop81 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i) <= wire_w_lg_w_lg_force_zero_w634w635w(0) AND man_res_dffe4_wo(i);
END GENERATE loop81;
loop82 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_denormal_result_w558w559w(i) <= wire_w_lg_denormal_result_w558w(0) AND wire_w_exp_adjustment2_add_sub_w_range557w(i);
END GENERATE loop82;
loop83 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND aligned_dataa_man_dffe15_w(i);
END GENERATE loop83;
loop84 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_rbarrel_shift_result(i);
END GENERATE loop84;
loop85 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w(i) <= wire_w_lg_exp_amb_mux_dffe15_wo316w(0) AND wire_w_aligned_dataa_exp_dffe15_wo_range315w(i);
END GENERATE loop85;
loop86 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w275w278w(i) <= wire_w_lg_exp_amb_mux_w275w(0) AND aligned_datab_man_dffe12_wo(i);
END GENERATE loop86;
loop87 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_exp_amb_mux_w275w276w(i) <= wire_w_lg_exp_amb_mux_w275w(0) AND wire_w_exp_amb_w_range274w(i);
END GENERATE loop87;
loop88 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w629w639w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i);
END GENERATE loop88;
loop89 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w629w648w(i) <= wire_w_lg_force_infinity_w629w(0) AND wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i);
END GENERATE loop89;
wire_w_lg_w_lg_force_infinity_w629w654w(0) <= wire_w_lg_force_infinity_w629w(0) AND sign_res_dffe4_wo;
loop90 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_nan_w630w642w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w640w641w(i);
END GENERATE loop90;
loop91 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_nan_w630w651w(i) <= wire_w_lg_force_nan_w630w(0) AND wire_w_lg_w_lg_force_infinity_w649w650w(i);
END GENERATE loop91;
loop92 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range242w(i);
END GENERATE loop92;
loop93 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w(i) <= wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) AND wire_w_dataa_dffe11_wo_range232w(i);
END GENERATE loop93;
wire_w_lg_w_lg_input_dataa_infinite_dffe11_wo246w247w(0) <= wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) AND wire_w_lg_input_dataa_denormal_dffe11_wo233w(0);
loop94 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range261w(i);
END GENERATE loop94;
loop95 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w(i) <= wire_w_lg_input_datab_denormal_dffe11_wo252w(0) AND wire_w_datab_dffe11_wo_range251w(i);
END GENERATE loop95;
wire_w_lg_w_lg_input_datab_infinite_dffe11_wo265w266w(0) <= wire_w_lg_input_datab_infinite_dffe11_wo265w(0) AND wire_w_lg_input_datab_denormal_dffe11_wo252w(0);
wire_w_lg_w_lg_input_datab_infinite_dffe15_wo338w339w(0) <= wire_w_lg_input_datab_infinite_dffe15_wo338w(0) AND aligned_dataa_sign_dffe15_wo;
wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0) <= wire_w_lg_man_res_not_zero_dffe26_wo503w(0) AND zero_man_sign_dffe26_wo;
loop96 : FOR i IN 0 TO 4 GENERATE
wire_w292w(i) <= wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w(0) AND wire_w_exp_diff_abs_w_range290w(i);
END GENERATE loop96;
wire_w397w(0) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop97 : FOR i IN 0 TO 1 GENERATE
wire_w383w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND exp_adjust_by_add1(i);
END GENERATE loop97;
loop98 : FOR i IN 0 TO 25 GENERATE
wire_w412w(i) <= wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range411w(i);
END GENERATE loop98;
loop99 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w(i) <= wire_w_lg_w_man_add_sub_w_range372w375w(0) AND man_add_sub_w(i);
END GENERATE loop99;
loop100 : FOR i IN 0 TO 22 GENERATE
wire_w587w(i) <= wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) AND wire_w_man_res_rounding_add_sub_w_range584w(i);
END GENERATE loop100;
loop101 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_zero_w634w637w(i) <= wire_w_lg_force_zero_w634w(0) AND exp_all_zeros_w(i);
END GENERATE loop101;
loop102 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_zero_w634w646w(i) <= wire_w_lg_force_zero_w634w(0) AND man_all_zeros_w(i);
END GENERATE loop102;
loop103 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo330w(i) <= exp_amb_mux_dffe15_wo AND aligned_datab_man_dffe15_w(i);
END GENERATE loop103;
loop104 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo323w(i) <= exp_amb_mux_dffe15_wo AND wire_rbarrel_shift_result(i);
END GENERATE loop104;
loop105 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_dffe15_wo314w(i) <= exp_amb_mux_dffe15_wo AND wire_w_aligned_datab_exp_dffe15_wo_range313w(i);
END GENERATE loop105;
loop106 : FOR i IN 0 TO 23 GENERATE
wire_w_lg_exp_amb_mux_w279w(i) <= exp_amb_mux_w AND aligned_dataa_man_dffe12_wo(i);
END GENERATE loop106;
loop107 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_exp_amb_mux_w273w(i) <= exp_amb_mux_w AND wire_w_exp_bma_w_range272w(i);
END GENERATE loop107;
loop108 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_infinity_w640w(i) <= force_infinity_w AND exp_all_ones_w(i);
END GENERATE loop108;
loop109 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_infinity_w649w(i) <= force_infinity_w AND man_all_zeros_w(i);
END GENERATE loop109;
loop110 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_force_nan_w643w(i) <= force_nan_w AND exp_all_ones_w(i);
END GENERATE loop110;
loop111 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_force_nan_w652w(i) <= force_nan_w AND man_nan_w(i);
END GENERATE loop111;
wire_w_lg_input_datab_infinite_dffe15_wo337w(0) <= input_datab_infinite_dffe15_wo AND wire_w_lg_aligned_datab_sign_dffe15_wo336w(0);
wire_w_lg_need_complement_dffe22_wo376w(0) <= need_complement_dffe22_wo AND wire_w_lg_w_man_add_sub_w_range372w375w(0);
wire_w_lg_w_dataa_range17w23w(0) <= wire_w_dataa_range17w(0) AND wire_w_exp_a_all_one_w_range7w(0);
wire_w_lg_w_dataa_range27w33w(0) <= wire_w_dataa_range27w(0) AND wire_w_exp_a_all_one_w_range24w(0);
wire_w_lg_w_dataa_range37w43w(0) <= wire_w_dataa_range37w(0) AND wire_w_exp_a_all_one_w_range34w(0);
wire_w_lg_w_dataa_range47w53w(0) <= wire_w_dataa_range47w(0) AND wire_w_exp_a_all_one_w_range44w(0);
wire_w_lg_w_dataa_range57w63w(0) <= wire_w_dataa_range57w(0) AND wire_w_exp_a_all_one_w_range54w(0);
wire_w_lg_w_dataa_range67w73w(0) <= wire_w_dataa_range67w(0) AND wire_w_exp_a_all_one_w_range64w(0);
wire_w_lg_w_dataa_range77w83w(0) <= wire_w_dataa_range77w(0) AND wire_w_exp_a_all_one_w_range74w(0);
wire_w_lg_w_datab_range20w25w(0) <= wire_w_datab_range20w(0) AND wire_w_exp_b_all_one_w_range9w(0);
wire_w_lg_w_datab_range30w35w(0) <= wire_w_datab_range30w(0) AND wire_w_exp_b_all_one_w_range26w(0);
wire_w_lg_w_datab_range40w45w(0) <= wire_w_datab_range40w(0) AND wire_w_exp_b_all_one_w_range36w(0);
wire_w_lg_w_datab_range50w55w(0) <= wire_w_datab_range50w(0) AND wire_w_exp_b_all_one_w_range46w(0);
wire_w_lg_w_datab_range60w65w(0) <= wire_w_datab_range60w(0) AND wire_w_exp_b_all_one_w_range56w(0);
wire_w_lg_w_datab_range70w75w(0) <= wire_w_datab_range70w(0) AND wire_w_exp_b_all_one_w_range66w(0);
wire_w_lg_w_datab_range80w85w(0) <= wire_w_datab_range80w(0) AND wire_w_exp_b_all_one_w_range76w(0);
wire_w_lg_w_exp_a_all_one_w_range84w220w(0) <= wire_w_exp_a_all_one_w_range84w(0) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0);
wire_w_lg_w_exp_b_all_one_w_range86w226w(0) <= wire_w_exp_b_all_one_w_range86w(0) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0);
loop112 : FOR i IN 0 TO 4 GENERATE
wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w(i) <= wire_w_exp_diff_abs_exceed_max_w_range289w(0) AND exp_diff_abs_max_w(i);
END GENERATE loop112;
wire_w_lg_w_exp_res_max_w_range540w542w(0) <= wire_w_exp_res_max_w_range540w(0) AND wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_max_w_range543w544w(0) <= wire_w_exp_res_max_w_range543w(0) AND wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_max_w_range545w546w(0) <= wire_w_exp_res_max_w_range545w(0) AND wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_max_w_range547w548w(0) <= wire_w_exp_res_max_w_range547w(0) AND wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_max_w_range549w550w(0) <= wire_w_exp_res_max_w_range549w(0) AND wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_max_w_range551w552w(0) <= wire_w_exp_res_max_w_range551w(0) AND wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_max_w_range553w554w(0) <= wire_w_exp_res_max_w_range553w(0) AND wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_max_w_range555w561w(0) <= wire_w_exp_res_max_w_range555w(0) AND wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0);
wire_w_lg_w_exp_rounded_res_max_w_range601w604w(0) <= wire_w_exp_rounded_res_max_w_range601w(0) AND wire_w_exp_rounded_res_w_range603w(0);
wire_w_lg_w_exp_rounded_res_max_w_range605w607w(0) <= wire_w_exp_rounded_res_max_w_range605w(0) AND wire_w_exp_rounded_res_w_range606w(0);
wire_w_lg_w_exp_rounded_res_max_w_range608w610w(0) <= wire_w_exp_rounded_res_max_w_range608w(0) AND wire_w_exp_rounded_res_w_range609w(0);
wire_w_lg_w_exp_rounded_res_max_w_range611w613w(0) <= wire_w_exp_rounded_res_max_w_range611w(0) AND wire_w_exp_rounded_res_w_range612w(0);
wire_w_lg_w_exp_rounded_res_max_w_range614w616w(0) <= wire_w_exp_rounded_res_max_w_range614w(0) AND wire_w_exp_rounded_res_w_range615w(0);
wire_w_lg_w_exp_rounded_res_max_w_range617w619w(0) <= wire_w_exp_rounded_res_max_w_range617w(0) AND wire_w_exp_rounded_res_w_range618w(0);
wire_w_lg_w_exp_rounded_res_max_w_range620w622w(0) <= wire_w_exp_rounded_res_max_w_range620w(0) AND wire_w_exp_rounded_res_w_range621w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0);
loop113 : FOR i IN 0 TO 1 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND exp_adjust_by_add2(i);
END GENERATE loop113;
loop114 : FOR i IN 0 TO 25 GENERATE
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w(i) <= wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) AND wire_w_man_add_sub_res_mag_dffe27_wo_range413w(i);
END GENERATE loop114;
loop115 : FOR i IN 0 TO 27 GENERATE
wire_w_lg_w_man_add_sub_w_range372w379w(i) <= wire_w_man_add_sub_w_range372w(0) AND man_2comp_res_w(i);
END GENERATE loop115;
loop116 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w(i) <= wire_w_man_res_rounding_add_sub_w_range585w(0) AND wire_w_man_res_rounding_add_sub_w_range588w(i);
END GENERATE loop116;
wire_w_lg_w_lg_force_zero_w634w635w(0) <= NOT wire_w_lg_force_zero_w634w(0);
wire_w_lg_add_sub_dffe25_wo491w(0) <= NOT add_sub_dffe25_wo;
wire_w_lg_add_sub_w2342w(0) <= NOT add_sub_w2;
wire_w_lg_aligned_datab_sign_dffe15_wo336w(0) <= NOT aligned_datab_sign_dffe15_wo;
wire_w_lg_denormal_result_w558w(0) <= NOT denormal_result_w;
wire_w_lg_exp_amb_mux_dffe15_wo316w(0) <= NOT exp_amb_mux_dffe15_wo;
wire_w_lg_exp_amb_mux_w275w(0) <= NOT exp_amb_mux_w;
wire_w_lg_force_infinity_w629w(0) <= NOT force_infinity_w;
wire_w_lg_force_nan_w630w(0) <= NOT force_nan_w;
wire_w_lg_force_zero_w628w(0) <= NOT force_zero_w;
wire_w_lg_input_dataa_denormal_dffe11_wo233w(0) <= NOT input_dataa_denormal_dffe11_wo;
wire_w_lg_input_dataa_infinite_dffe11_wo246w(0) <= NOT input_dataa_infinite_dffe11_wo;
wire_w_lg_input_dataa_zero_dffe11_wo245w(0) <= NOT input_dataa_zero_dffe11_wo;
wire_w_lg_input_datab_denormal_dffe11_wo252w(0) <= NOT input_datab_denormal_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe11_wo265w(0) <= NOT input_datab_infinite_dffe11_wo;
wire_w_lg_input_datab_infinite_dffe15_wo338w(0) <= NOT input_datab_infinite_dffe15_wo;
wire_w_lg_input_datab_zero_dffe11_wo264w(0) <= NOT input_datab_zero_dffe11_wo;
wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0) <= NOT man_res_is_not_zero_dffe4_wo;
wire_w_lg_man_res_not_zero_dffe26_wo503w(0) <= NOT man_res_not_zero_dffe26_wo;
wire_w_lg_need_complement_dffe22_wo373w(0) <= NOT need_complement_dffe22_wo;
wire_w_lg_sticky_bit_dffe1_wo343w(0) <= NOT sticky_bit_dffe1_wo;
wire_w_lg_w_exp_adjustment2_add_sub_w_range511w560w(0) <= NOT wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w291w(0) <= NOT wire_w_exp_diff_abs_exceed_max_w_range289w(0);
wire_w_lg_w_man_a_not_zero_w_range215w219w(0) <= NOT wire_w_man_a_not_zero_w_range215w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range387w390w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0);
wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) <= NOT wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0);
wire_w_lg_w_man_add_sub_w_range372w375w(0) <= NOT wire_w_man_add_sub_w_range372w(0);
wire_w_lg_w_man_b_not_zero_w_range218w225w(0) <= NOT wire_w_man_b_not_zero_w_range218w(0);
wire_w_lg_w_man_res_rounding_add_sub_w_range585w586w(0) <= NOT wire_w_man_res_rounding_add_sub_w_range585w(0);
loop117 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w637w638w(i) <= wire_w_lg_w_lg_force_zero_w634w637w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w636w(i);
END GENERATE loop117;
loop118 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_w_lg_force_zero_w634w646w647w(i) <= wire_w_lg_w_lg_force_zero_w634w646w(i) OR wire_w_lg_w_lg_w_lg_force_zero_w634w635w645w(i);
END GENERATE loop118;
loop119 : FOR i IN 0 TO 7 GENERATE
wire_w_lg_w_lg_force_infinity_w640w641w(i) <= wire_w_lg_force_infinity_w640w(i) OR wire_w_lg_w_lg_force_infinity_w629w639w(i);
END GENERATE loop119;
loop120 : FOR i IN 0 TO 22 GENERATE
wire_w_lg_w_lg_force_infinity_w649w650w(i) <= wire_w_lg_force_infinity_w649w(i) OR wire_w_lg_w_lg_force_infinity_w629w648w(i);
END GENERATE loop120;
wire_w_lg_force_zero_w634w(0) <= force_zero_w OR denormal_flag_w;
wire_w_lg_sticky_bit_dffe27_wo402w(0) <= sticky_bit_dffe27_wo OR wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0);
wire_w_lg_w_dataa_range141w142w(0) <= wire_w_dataa_range141w(0) OR wire_w_man_a_not_zero_w_range137w(0);
wire_w_lg_w_dataa_range147w148w(0) <= wire_w_dataa_range147w(0) OR wire_w_man_a_not_zero_w_range143w(0);
wire_w_lg_w_dataa_range153w154w(0) <= wire_w_dataa_range153w(0) OR wire_w_man_a_not_zero_w_range149w(0);
wire_w_lg_w_dataa_range159w160w(0) <= wire_w_dataa_range159w(0) OR wire_w_man_a_not_zero_w_range155w(0);
wire_w_lg_w_dataa_range165w166w(0) <= wire_w_dataa_range165w(0) OR wire_w_man_a_not_zero_w_range161w(0);
wire_w_lg_w_dataa_range171w172w(0) <= wire_w_dataa_range171w(0) OR wire_w_man_a_not_zero_w_range167w(0);
wire_w_lg_w_dataa_range177w178w(0) <= wire_w_dataa_range177w(0) OR wire_w_man_a_not_zero_w_range173w(0);
wire_w_lg_w_dataa_range183w184w(0) <= wire_w_dataa_range183w(0) OR wire_w_man_a_not_zero_w_range179w(0);
wire_w_lg_w_dataa_range189w190w(0) <= wire_w_dataa_range189w(0) OR wire_w_man_a_not_zero_w_range185w(0);
wire_w_lg_w_dataa_range195w196w(0) <= wire_w_dataa_range195w(0) OR wire_w_man_a_not_zero_w_range191w(0);
wire_w_lg_w_dataa_range87w88w(0) <= wire_w_dataa_range87w(0) OR wire_w_man_a_not_zero_w_range12w(0);
wire_w_lg_w_dataa_range201w202w(0) <= wire_w_dataa_range201w(0) OR wire_w_man_a_not_zero_w_range197w(0);
wire_w_lg_w_dataa_range207w208w(0) <= wire_w_dataa_range207w(0) OR wire_w_man_a_not_zero_w_range203w(0);
wire_w_lg_w_dataa_range213w214w(0) <= wire_w_dataa_range213w(0) OR wire_w_man_a_not_zero_w_range209w(0);
wire_w_lg_w_dataa_range17w18w(0) <= wire_w_dataa_range17w(0) OR wire_w_exp_a_not_zero_w_range2w(0);
wire_w_lg_w_dataa_range27w28w(0) <= wire_w_dataa_range27w(0) OR wire_w_exp_a_not_zero_w_range19w(0);
wire_w_lg_w_dataa_range37w38w(0) <= wire_w_dataa_range37w(0) OR wire_w_exp_a_not_zero_w_range29w(0);
wire_w_lg_w_dataa_range47w48w(0) <= wire_w_dataa_range47w(0) OR wire_w_exp_a_not_zero_w_range39w(0);
wire_w_lg_w_dataa_range57w58w(0) <= wire_w_dataa_range57w(0) OR wire_w_exp_a_not_zero_w_range49w(0);
wire_w_lg_w_dataa_range67w68w(0) <= wire_w_dataa_range67w(0) OR wire_w_exp_a_not_zero_w_range59w(0);
wire_w_lg_w_dataa_range93w94w(0) <= wire_w_dataa_range93w(0) OR wire_w_man_a_not_zero_w_range89w(0);
wire_w_lg_w_dataa_range77w78w(0) <= wire_w_dataa_range77w(0) OR wire_w_exp_a_not_zero_w_range69w(0);
wire_w_lg_w_dataa_range99w100w(0) <= wire_w_dataa_range99w(0) OR wire_w_man_a_not_zero_w_range95w(0);
wire_w_lg_w_dataa_range105w106w(0) <= wire_w_dataa_range105w(0) OR wire_w_man_a_not_zero_w_range101w(0);
wire_w_lg_w_dataa_range111w112w(0) <= wire_w_dataa_range111w(0) OR wire_w_man_a_not_zero_w_range107w(0);
wire_w_lg_w_dataa_range117w118w(0) <= wire_w_dataa_range117w(0) OR wire_w_man_a_not_zero_w_range113w(0);
wire_w_lg_w_dataa_range123w124w(0) <= wire_w_dataa_range123w(0) OR wire_w_man_a_not_zero_w_range119w(0);
wire_w_lg_w_dataa_range129w130w(0) <= wire_w_dataa_range129w(0) OR wire_w_man_a_not_zero_w_range125w(0);
wire_w_lg_w_dataa_range135w136w(0) <= wire_w_dataa_range135w(0) OR wire_w_man_a_not_zero_w_range131w(0);
wire_w_lg_w_datab_range144w145w(0) <= wire_w_datab_range144w(0) OR wire_w_man_b_not_zero_w_range140w(0);
wire_w_lg_w_datab_range150w151w(0) <= wire_w_datab_range150w(0) OR wire_w_man_b_not_zero_w_range146w(0);
wire_w_lg_w_datab_range156w157w(0) <= wire_w_datab_range156w(0) OR wire_w_man_b_not_zero_w_range152w(0);
wire_w_lg_w_datab_range162w163w(0) <= wire_w_datab_range162w(0) OR wire_w_man_b_not_zero_w_range158w(0);
wire_w_lg_w_datab_range168w169w(0) <= wire_w_datab_range168w(0) OR wire_w_man_b_not_zero_w_range164w(0);
wire_w_lg_w_datab_range174w175w(0) <= wire_w_datab_range174w(0) OR wire_w_man_b_not_zero_w_range170w(0);
wire_w_lg_w_datab_range180w181w(0) <= wire_w_datab_range180w(0) OR wire_w_man_b_not_zero_w_range176w(0);
wire_w_lg_w_datab_range186w187w(0) <= wire_w_datab_range186w(0) OR wire_w_man_b_not_zero_w_range182w(0);
wire_w_lg_w_datab_range192w193w(0) <= wire_w_datab_range192w(0) OR wire_w_man_b_not_zero_w_range188w(0);
wire_w_lg_w_datab_range198w199w(0) <= wire_w_datab_range198w(0) OR wire_w_man_b_not_zero_w_range194w(0);
wire_w_lg_w_datab_range90w91w(0) <= wire_w_datab_range90w(0) OR wire_w_man_b_not_zero_w_range15w(0);
wire_w_lg_w_datab_range204w205w(0) <= wire_w_datab_range204w(0) OR wire_w_man_b_not_zero_w_range200w(0);
wire_w_lg_w_datab_range210w211w(0) <= wire_w_datab_range210w(0) OR wire_w_man_b_not_zero_w_range206w(0);
wire_w_lg_w_datab_range216w217w(0) <= wire_w_datab_range216w(0) OR wire_w_man_b_not_zero_w_range212w(0);
wire_w_lg_w_datab_range20w21w(0) <= wire_w_datab_range20w(0) OR wire_w_exp_b_not_zero_w_range5w(0);
wire_w_lg_w_datab_range30w31w(0) <= wire_w_datab_range30w(0) OR wire_w_exp_b_not_zero_w_range22w(0);
wire_w_lg_w_datab_range40w41w(0) <= wire_w_datab_range40w(0) OR wire_w_exp_b_not_zero_w_range32w(0);
wire_w_lg_w_datab_range50w51w(0) <= wire_w_datab_range50w(0) OR wire_w_exp_b_not_zero_w_range42w(0);
wire_w_lg_w_datab_range60w61w(0) <= wire_w_datab_range60w(0) OR wire_w_exp_b_not_zero_w_range52w(0);
wire_w_lg_w_datab_range70w71w(0) <= wire_w_datab_range70w(0) OR wire_w_exp_b_not_zero_w_range62w(0);
wire_w_lg_w_datab_range96w97w(0) <= wire_w_datab_range96w(0) OR wire_w_man_b_not_zero_w_range92w(0);
wire_w_lg_w_datab_range80w81w(0) <= wire_w_datab_range80w(0) OR wire_w_exp_b_not_zero_w_range72w(0);
wire_w_lg_w_datab_range102w103w(0) <= wire_w_datab_range102w(0) OR wire_w_man_b_not_zero_w_range98w(0);
wire_w_lg_w_datab_range108w109w(0) <= wire_w_datab_range108w(0) OR wire_w_man_b_not_zero_w_range104w(0);
wire_w_lg_w_datab_range114w115w(0) <= wire_w_datab_range114w(0) OR wire_w_man_b_not_zero_w_range110w(0);
wire_w_lg_w_datab_range120w121w(0) <= wire_w_datab_range120w(0) OR wire_w_man_b_not_zero_w_range116w(0);
wire_w_lg_w_datab_range126w127w(0) <= wire_w_datab_range126w(0) OR wire_w_man_b_not_zero_w_range122w(0);
wire_w_lg_w_datab_range132w133w(0) <= wire_w_datab_range132w(0) OR wire_w_man_b_not_zero_w_range128w(0);
wire_w_lg_w_datab_range138w139w(0) <= wire_w_datab_range138w(0) OR wire_w_man_b_not_zero_w_range134w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w(0) <= wire_w_exp_diff_abs_exceed_max_w_range282w(0) OR wire_w_exp_diff_abs_w_range284w(0);
wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w(0) <= wire_w_exp_diff_abs_exceed_max_w_range286w(0) OR wire_w_exp_diff_abs_w_range287w(0);
wire_w_lg_w_exp_res_not_zero_w_range516w519w(0) <= wire_w_exp_res_not_zero_w_range516w(0) OR wire_w_exp_adjustment2_add_sub_w_range518w(0);
wire_w_lg_w_exp_res_not_zero_w_range520w522w(0) <= wire_w_exp_res_not_zero_w_range520w(0) OR wire_w_exp_adjustment2_add_sub_w_range521w(0);
wire_w_lg_w_exp_res_not_zero_w_range523w525w(0) <= wire_w_exp_res_not_zero_w_range523w(0) OR wire_w_exp_adjustment2_add_sub_w_range524w(0);
wire_w_lg_w_exp_res_not_zero_w_range526w528w(0) <= wire_w_exp_res_not_zero_w_range526w(0) OR wire_w_exp_adjustment2_add_sub_w_range527w(0);
wire_w_lg_w_exp_res_not_zero_w_range529w531w(0) <= wire_w_exp_res_not_zero_w_range529w(0) OR wire_w_exp_adjustment2_add_sub_w_range530w(0);
wire_w_lg_w_exp_res_not_zero_w_range532w534w(0) <= wire_w_exp_res_not_zero_w_range532w(0) OR wire_w_exp_adjustment2_add_sub_w_range533w(0);
wire_w_lg_w_exp_res_not_zero_w_range535w537w(0) <= wire_w_exp_res_not_zero_w_range535w(0) OR wire_w_exp_adjustment2_add_sub_w_range536w(0);
wire_w_lg_w_exp_res_not_zero_w_range538w539w(0) <= wire_w_exp_res_not_zero_w_range538w(0) OR wire_w_exp_adjustment2_add_sub_w_range511w(0);
wire_w_lg_w_man_res_not_zero_w2_range417w420w(0) <= wire_w_man_res_not_zero_w2_range417w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0);
wire_w_lg_w_man_res_not_zero_w2_range448w450w(0) <= wire_w_man_res_not_zero_w2_range448w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0);
wire_w_lg_w_man_res_not_zero_w2_range451w453w(0) <= wire_w_man_res_not_zero_w2_range451w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0);
wire_w_lg_w_man_res_not_zero_w2_range454w456w(0) <= wire_w_man_res_not_zero_w2_range454w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0);
wire_w_lg_w_man_res_not_zero_w2_range457w459w(0) <= wire_w_man_res_not_zero_w2_range457w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0);
wire_w_lg_w_man_res_not_zero_w2_range460w462w(0) <= wire_w_man_res_not_zero_w2_range460w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0);
wire_w_lg_w_man_res_not_zero_w2_range463w465w(0) <= wire_w_man_res_not_zero_w2_range463w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0);
wire_w_lg_w_man_res_not_zero_w2_range466w468w(0) <= wire_w_man_res_not_zero_w2_range466w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0);
wire_w_lg_w_man_res_not_zero_w2_range469w471w(0) <= wire_w_man_res_not_zero_w2_range469w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0);
wire_w_lg_w_man_res_not_zero_w2_range472w474w(0) <= wire_w_man_res_not_zero_w2_range472w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0);
wire_w_lg_w_man_res_not_zero_w2_range475w477w(0) <= wire_w_man_res_not_zero_w2_range475w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0);
wire_w_lg_w_man_res_not_zero_w2_range421w423w(0) <= wire_w_man_res_not_zero_w2_range421w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0);
wire_w_lg_w_man_res_not_zero_w2_range478w480w(0) <= wire_w_man_res_not_zero_w2_range478w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0);
wire_w_lg_w_man_res_not_zero_w2_range481w483w(0) <= wire_w_man_res_not_zero_w2_range481w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0);
wire_w_lg_w_man_res_not_zero_w2_range484w486w(0) <= wire_w_man_res_not_zero_w2_range484w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0);
wire_w_lg_w_man_res_not_zero_w2_range487w489w(0) <= wire_w_man_res_not_zero_w2_range487w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0);
wire_w_lg_w_man_res_not_zero_w2_range424w426w(0) <= wire_w_man_res_not_zero_w2_range424w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0);
wire_w_lg_w_man_res_not_zero_w2_range427w429w(0) <= wire_w_man_res_not_zero_w2_range427w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0);
wire_w_lg_w_man_res_not_zero_w2_range430w432w(0) <= wire_w_man_res_not_zero_w2_range430w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0);
wire_w_lg_w_man_res_not_zero_w2_range433w435w(0) <= wire_w_man_res_not_zero_w2_range433w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0);
wire_w_lg_w_man_res_not_zero_w2_range436w438w(0) <= wire_w_man_res_not_zero_w2_range436w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0);
wire_w_lg_w_man_res_not_zero_w2_range439w441w(0) <= wire_w_man_res_not_zero_w2_range439w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0);
wire_w_lg_w_man_res_not_zero_w2_range442w444w(0) <= wire_w_man_res_not_zero_w2_range442w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0);
wire_w_lg_w_man_res_not_zero_w2_range445w447w(0) <= wire_w_man_res_not_zero_w2_range445w(0) OR wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0);
add_sub_dffe25_wi <= add_sub_w2;
add_sub_dffe25_wo <= add_sub_dffe25_wi;
add_sub_w2 <= (dataa_sign_dffe1_wo XOR datab_sign_dffe1_wo);
adder_upper_w <= man_intermediate_res_w(25 DOWNTO 13);
aligned_dataa_exp_dffe12_wi <= aligned_dataa_exp_w;
aligned_dataa_exp_dffe12_wo <= aligned_dataa_exp_dffe12_wi;
aligned_dataa_exp_dffe13_wi <= aligned_dataa_exp_dffe12_wo;
aligned_dataa_exp_dffe13_wo <= aligned_dataa_exp_dffe13_wi;
aligned_dataa_exp_dffe14_wi <= aligned_dataa_exp_dffe13_wo;
aligned_dataa_exp_dffe14_wo <= aligned_dataa_exp_dffe14_wi;
aligned_dataa_exp_dffe15_wi <= aligned_dataa_exp_dffe14_wo;
aligned_dataa_exp_dffe15_wo <= aligned_dataa_exp_dffe15_wi;
aligned_dataa_exp_w <= ( "0" & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w234w);
aligned_dataa_man_dffe12_wi <= aligned_dataa_man_w(25 DOWNTO 2);
aligned_dataa_man_dffe12_wo <= aligned_dataa_man_dffe12_wi;
aligned_dataa_man_dffe13_wi <= aligned_dataa_man_dffe12_wo;
aligned_dataa_man_dffe13_wo <= aligned_dataa_man_dffe13_wi;
aligned_dataa_man_dffe14_wi <= aligned_dataa_man_dffe13_wo;
aligned_dataa_man_dffe14_wo <= aligned_dataa_man_dffe14_wi;
aligned_dataa_man_dffe15_w <= ( aligned_dataa_man_dffe15_wo & "00");
aligned_dataa_man_dffe15_wi <= aligned_dataa_man_dffe14_wo;
aligned_dataa_man_dffe15_wo <= aligned_dataa_man_dffe15_wi;
aligned_dataa_man_w <= ( wire_w248w & wire_w_lg_w_lg_input_dataa_denormal_dffe11_wo233w243w & "00");
aligned_dataa_sign_dffe12_wi <= aligned_dataa_sign_w;
aligned_dataa_sign_dffe12_wo <= aligned_dataa_sign_dffe12_wi;
aligned_dataa_sign_dffe13_wi <= aligned_dataa_sign_dffe12_wo;
aligned_dataa_sign_dffe13_wo <= aligned_dataa_sign_dffe13_wi;
aligned_dataa_sign_dffe14_wi <= aligned_dataa_sign_dffe13_wo;
aligned_dataa_sign_dffe14_wo <= aligned_dataa_sign_dffe14_wi;
aligned_dataa_sign_dffe15_wi <= aligned_dataa_sign_dffe14_wo;
aligned_dataa_sign_dffe15_wo <= aligned_dataa_sign_dffe15_wi;
aligned_dataa_sign_w <= dataa_dffe11_wo(31);
aligned_datab_exp_dffe12_wi <= aligned_datab_exp_w;
aligned_datab_exp_dffe12_wo <= aligned_datab_exp_dffe12_wi;
aligned_datab_exp_dffe13_wi <= aligned_datab_exp_dffe12_wo;
aligned_datab_exp_dffe13_wo <= aligned_datab_exp_dffe13_wi;
aligned_datab_exp_dffe14_wi <= aligned_datab_exp_dffe13_wo;
aligned_datab_exp_dffe14_wo <= aligned_datab_exp_dffe14_wi;
aligned_datab_exp_dffe15_wi <= aligned_datab_exp_dffe14_wo;
aligned_datab_exp_dffe15_wo <= aligned_datab_exp_dffe15_wi;
aligned_datab_exp_w <= ( "0" & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w253w);
aligned_datab_man_dffe12_wi <= aligned_datab_man_w(25 DOWNTO 2);
aligned_datab_man_dffe12_wo <= aligned_datab_man_dffe12_wi;
aligned_datab_man_dffe13_wi <= aligned_datab_man_dffe12_wo;
aligned_datab_man_dffe13_wo <= aligned_datab_man_dffe13_wi;
aligned_datab_man_dffe14_wi <= aligned_datab_man_dffe13_wo;
aligned_datab_man_dffe14_wo <= aligned_datab_man_dffe14_wi;
aligned_datab_man_dffe15_w <= ( aligned_datab_man_dffe15_wo & "00");
aligned_datab_man_dffe15_wi <= aligned_datab_man_dffe14_wo;
aligned_datab_man_dffe15_wo <= aligned_datab_man_dffe15_wi;
aligned_datab_man_w <= ( wire_w267w & wire_w_lg_w_lg_input_datab_denormal_dffe11_wo252w262w & "00");
aligned_datab_sign_dffe12_wi <= aligned_datab_sign_w;
aligned_datab_sign_dffe12_wo <= aligned_datab_sign_dffe12_wi;
aligned_datab_sign_dffe13_wi <= aligned_datab_sign_dffe12_wo;
aligned_datab_sign_dffe13_wo <= aligned_datab_sign_dffe13_wi;
aligned_datab_sign_dffe14_wi <= aligned_datab_sign_dffe13_wo;
aligned_datab_sign_dffe14_wo <= aligned_datab_sign_dffe14_wi;
aligned_datab_sign_dffe15_wi <= aligned_datab_sign_dffe14_wo;
aligned_datab_sign_dffe15_wo <= aligned_datab_sign_dffe15_wi;
aligned_datab_sign_w <= datab_dffe11_wo(31);
borrow_w <= (wire_w_lg_sticky_bit_dffe1_wo343w(0) AND wire_w_lg_add_sub_w2342w(0));
both_inputs_are_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo AND input_datab_infinite_dffe15_wo);
both_inputs_are_infinite_dffe1_wo <= both_inputs_are_infinite_dffe1;
both_inputs_are_infinite_dffe25_wi <= both_inputs_are_infinite_dffe1_wo;
both_inputs_are_infinite_dffe25_wo <= both_inputs_are_infinite_dffe25_wi;
data_exp_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w317w OR wire_w_lg_exp_amb_mux_dffe15_wo314w);
data_exp_dffe1_wo <= data_exp_dffe1;
dataa_dffe11_wi <= dataa;
dataa_dffe11_wo <= dataa_dffe11_wi;
dataa_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w324w OR wire_w_lg_exp_amb_mux_dffe15_wo323w);
dataa_man_dffe1_wo <= dataa_man_dffe1;
dataa_sign_dffe1_wi <= aligned_dataa_sign_dffe15_wo;
dataa_sign_dffe1_wo <= dataa_sign_dffe1;
dataa_sign_dffe25_wi <= dataa_sign_dffe1_wo;
dataa_sign_dffe25_wo <= dataa_sign_dffe25_wi;
datab_dffe11_wi <= datab;
datab_dffe11_wo <= datab_dffe11_wi;
datab_man_dffe1_wi <= (wire_w_lg_w_lg_exp_amb_mux_dffe15_wo316w331w OR wire_w_lg_exp_amb_mux_dffe15_wo330w);
datab_man_dffe1_wo <= datab_man_dffe1;
datab_sign_dffe1_wi <= aligned_datab_sign_dffe15_wo;
datab_sign_dffe1_wo <= datab_sign_dffe1;
denormal_flag_w <= (((wire_w_lg_force_nan_w630w(0) AND wire_w_lg_force_infinity_w629w(0)) AND wire_w_lg_force_zero_w628w(0)) AND denormal_res_dffe4_wo);
denormal_res_dffe32_wi <= denormal_result_w;
denormal_res_dffe32_wo <= denormal_res_dffe32_wi;
denormal_res_dffe33_wi <= denormal_res_dffe32_wo;
denormal_res_dffe33_wo <= denormal_res_dffe33_wi;
denormal_res_dffe3_wi <= denormal_res_dffe33_wo;
denormal_res_dffe3_wo <= denormal_res_dffe3;
denormal_res_dffe41_wi <= denormal_res_dffe42_wo;
denormal_res_dffe41_wo <= denormal_res_dffe41_wi;
denormal_res_dffe42_wi <= denormal_res_dffe3_wo;
denormal_res_dffe42_wo <= denormal_res_dffe42_wi;
denormal_res_dffe4_wi <= denormal_res_dffe41_wo;
denormal_res_dffe4_wo <= denormal_res_dffe4;
denormal_result_w <= ((NOT exp_res_not_zero_w(8)) OR exp_adjustment2_add_sub_w(8));
exp_a_all_one_w <= ( wire_w_lg_w_dataa_range77w83w & wire_w_lg_w_dataa_range67w73w & wire_w_lg_w_dataa_range57w63w & wire_w_lg_w_dataa_range47w53w & wire_w_lg_w_dataa_range37w43w & wire_w_lg_w_dataa_range27w33w & wire_w_lg_w_dataa_range17w23w & dataa(23));
exp_a_not_zero_w <= ( wire_w_lg_w_dataa_range77w78w & wire_w_lg_w_dataa_range67w68w & wire_w_lg_w_dataa_range57w58w & wire_w_lg_w_dataa_range47w48w & wire_w_lg_w_dataa_range37w38w & wire_w_lg_w_dataa_range27w28w & wire_w_lg_w_dataa_range17w18w & dataa(23));
exp_adj_0pads <= (OTHERS => '0');
exp_adj_dffe21_wi <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w384w OR wire_w383w);
exp_adj_dffe21_wo <= exp_adj_dffe21;
exp_adj_dffe23_wi <= exp_adj_dffe21_wo;
exp_adj_dffe23_wo <= exp_adj_dffe23_wi;
exp_adj_dffe26_wi <= exp_adj_dffe23_wo;
exp_adj_dffe26_wo <= exp_adj_dffe26_wi;
exp_adjust_by_add1 <= "01";
exp_adjust_by_add2 <= "10";
exp_adjustment2_add_sub_dataa_w <= exp_value;
exp_adjustment2_add_sub_datab_w <= exp_adjustment_add_sub_w;
exp_adjustment2_add_sub_w <= wire_add_sub5_result;
exp_adjustment_add_sub_dataa_w <= ( priority_encoder_1pads_w & wire_leading_zeroes_cnt_q);
exp_adjustment_add_sub_datab_w <= ( exp_adj_0pads & exp_adj_dffe26_wo);
exp_adjustment_add_sub_w <= wire_add_sub4_result;
exp_all_ones_w <= (OTHERS => '1');
exp_all_zeros_w <= (OTHERS => '0');
exp_amb_mux_dffe13_wi <= exp_amb_mux_w;
exp_amb_mux_dffe13_wo <= exp_amb_mux_dffe13_wi;
exp_amb_mux_dffe14_wi <= exp_amb_mux_dffe13_wo;
exp_amb_mux_dffe14_wo <= exp_amb_mux_dffe14_wi;
exp_amb_mux_dffe15_wi <= exp_amb_mux_dffe14_wo;
exp_amb_mux_dffe15_wo <= exp_amb_mux_dffe15_wi;
exp_amb_mux_w <= exp_amb_w(8);
exp_amb_w <= wire_add_sub1_result;
exp_b_all_one_w <= ( wire_w_lg_w_datab_range80w85w & wire_w_lg_w_datab_range70w75w & wire_w_lg_w_datab_range60w65w & wire_w_lg_w_datab_range50w55w & wire_w_lg_w_datab_range40w45w & wire_w_lg_w_datab_range30w35w & wire_w_lg_w_datab_range20w25w & datab(23));
exp_b_not_zero_w <= ( wire_w_lg_w_datab_range80w81w & wire_w_lg_w_datab_range70w71w & wire_w_lg_w_datab_range60w61w & wire_w_lg_w_datab_range50w51w & wire_w_lg_w_datab_range40w41w & wire_w_lg_w_datab_range30w31w & wire_w_lg_w_datab_range20w21w & datab(23));
exp_bma_w <= wire_add_sub2_result;
exp_diff_abs_exceed_max_w <= ( wire_w_lg_w_exp_diff_abs_exceed_max_w_range286w288w & wire_w_lg_w_exp_diff_abs_exceed_max_w_range282w285w & exp_diff_abs_w(5));
exp_diff_abs_max_w <= (OTHERS => '1');
exp_diff_abs_w <= (wire_w_lg_w_lg_exp_amb_mux_w275w276w OR wire_w_lg_exp_amb_mux_w273w);
exp_intermediate_res_dffe41_wi <= exp_intermediate_res_dffe42_wo;
exp_intermediate_res_dffe41_wo <= exp_intermediate_res_dffe41_wi;
exp_intermediate_res_dffe42_wi <= exp_intermediate_res_w;
exp_intermediate_res_dffe42_wo <= exp_intermediate_res_dffe42_wi;
exp_intermediate_res_w <= exp_res_dffe3_wo;
exp_out_dffe5_wi <= (wire_w_lg_force_nan_w643w OR wire_w_lg_w_lg_force_nan_w630w642w);
exp_out_dffe5_wo <= exp_out_dffe5;
exp_res_dffe21_wi <= exp_res_dffe27_wo;
exp_res_dffe21_wo <= exp_res_dffe21;
exp_res_dffe22_wi <= exp_res_dffe2_wo;
exp_res_dffe22_wo <= exp_res_dffe22_wi;
exp_res_dffe23_wi <= exp_res_dffe21_wo;
exp_res_dffe23_wo <= exp_res_dffe23_wi;
exp_res_dffe25_wi <= data_exp_dffe1_wo;
exp_res_dffe25_wo <= exp_res_dffe25_wi;
exp_res_dffe26_wi <= exp_res_dffe23_wo;
exp_res_dffe26_wo <= exp_res_dffe26_wi;
exp_res_dffe27_wi <= exp_res_dffe22_wo;
exp_res_dffe27_wo <= exp_res_dffe27_wi;
exp_res_dffe2_wi <= exp_res_dffe25_wo;
exp_res_dffe2_wo <= exp_res_dffe2;
exp_res_dffe32_wi <= wire_w_lg_w_lg_denormal_result_w558w559w;
exp_res_dffe32_wo <= exp_res_dffe32_wi;
exp_res_dffe33_wi <= exp_res_dffe32_wo;
exp_res_dffe33_wo <= exp_res_dffe33_wi;
exp_res_dffe3_wi <= exp_res_dffe33_wo;
exp_res_dffe3_wo <= exp_res_dffe3;
exp_res_dffe4_wi <= exp_rounded_res_w;
exp_res_dffe4_wo <= exp_res_dffe4;
exp_res_max_w <= ( wire_w_lg_w_exp_res_max_w_range553w554w & wire_w_lg_w_exp_res_max_w_range551w552w & wire_w_lg_w_exp_res_max_w_range549w550w & wire_w_lg_w_exp_res_max_w_range547w548w & wire_w_lg_w_exp_res_max_w_range545w546w & wire_w_lg_w_exp_res_max_w_range543w544w & wire_w_lg_w_exp_res_max_w_range540w542w & exp_adjustment2_add_sub_w(0));
exp_res_not_zero_w <= ( wire_w_lg_w_exp_res_not_zero_w_range538w539w & wire_w_lg_w_exp_res_not_zero_w_range535w537w & wire_w_lg_w_exp_res_not_zero_w_range532w534w & wire_w_lg_w_exp_res_not_zero_w_range529w531w & wire_w_lg_w_exp_res_not_zero_w_range526w528w & wire_w_lg_w_exp_res_not_zero_w_range523w525w & wire_w_lg_w_exp_res_not_zero_w_range520w522w & wire_w_lg_w_exp_res_not_zero_w_range516w519w & exp_adjustment2_add_sub_w(0));
exp_res_rounding_adder_dataa_w <= ( "0" & exp_intermediate_res_dffe41_wo);
exp_res_rounding_adder_w <= wire_add_sub6_result;
exp_rounded_res_infinity_w <= exp_rounded_res_max_w(7);
exp_rounded_res_max_w <= ( wire_w_lg_w_exp_rounded_res_max_w_range620w622w & wire_w_lg_w_exp_rounded_res_max_w_range617w619w & wire_w_lg_w_exp_rounded_res_max_w_range614w616w & wire_w_lg_w_exp_rounded_res_max_w_range611w613w & wire_w_lg_w_exp_rounded_res_max_w_range608w610w & wire_w_lg_w_exp_rounded_res_max_w_range605w607w & wire_w_lg_w_exp_rounded_res_max_w_range601w604w & exp_rounded_res_w(0));
exp_rounded_res_w <= exp_res_rounding_adder_w(7 DOWNTO 0);
exp_rounding_adjustment_w <= ( "00000000" & man_res_rounding_add_sub_w(24));
exp_value <= ( "0" & exp_res_dffe26_wo);
force_infinity_w <= ((input_is_infinite_dffe4_wo OR rounded_res_infinity_dffe4_wo) OR infinite_res_dffe4_wo);
force_nan_w <= (infinity_magnitude_sub_dffe4_wo OR input_is_nan_dffe4_wo);
force_zero_w <= wire_w_lg_man_res_is_not_zero_dffe4_wo627w(0);
guard_bit_dffe3_wo <= man_res_w3(0);
infinite_output_sign_dffe1_wi <= (wire_w_lg_w_lg_input_datab_infinite_dffe15_wo338w339w(0) OR wire_w_lg_input_datab_infinite_dffe15_wo337w(0));
infinite_output_sign_dffe1_wo <= infinite_output_sign_dffe1;
infinite_output_sign_dffe21_wi <= infinite_output_sign_dffe27_wo;
infinite_output_sign_dffe21_wo <= infinite_output_sign_dffe21;
infinite_output_sign_dffe22_wi <= infinite_output_sign_dffe2_wo;
infinite_output_sign_dffe22_wo <= infinite_output_sign_dffe22_wi;
infinite_output_sign_dffe23_wi <= infinite_output_sign_dffe21_wo;
infinite_output_sign_dffe23_wo <= infinite_output_sign_dffe23_wi;
infinite_output_sign_dffe25_wi <= infinite_output_sign_dffe1_wo;
infinite_output_sign_dffe25_wo <= infinite_output_sign_dffe25_wi;
infinite_output_sign_dffe26_wi <= infinite_output_sign_dffe23_wo;
infinite_output_sign_dffe26_wo <= infinite_output_sign_dffe26_wi;
infinite_output_sign_dffe27_wi <= infinite_output_sign_dffe22_wo;
infinite_output_sign_dffe27_wo <= infinite_output_sign_dffe27_wi;
infinite_output_sign_dffe2_wi <= infinite_output_sign_dffe25_wo;
infinite_output_sign_dffe2_wo <= infinite_output_sign_dffe2;
infinite_output_sign_dffe31_wi <= infinite_output_sign_dffe26_wo;
infinite_output_sign_dffe31_wo <= infinite_output_sign_dffe31;
infinite_output_sign_dffe32_wi <= infinite_output_sign_dffe31_wo;
infinite_output_sign_dffe32_wo <= infinite_output_sign_dffe32_wi;
infinite_output_sign_dffe33_wi <= infinite_output_sign_dffe32_wo;
infinite_output_sign_dffe33_wo <= infinite_output_sign_dffe33_wi;
infinite_output_sign_dffe3_wi <= infinite_output_sign_dffe33_wo;
infinite_output_sign_dffe3_wo <= infinite_output_sign_dffe3;
infinite_output_sign_dffe41_wi <= infinite_output_sign_dffe42_wo;
infinite_output_sign_dffe41_wo <= infinite_output_sign_dffe41_wi;
infinite_output_sign_dffe42_wi <= infinite_output_sign_dffe3_wo;
infinite_output_sign_dffe42_wo <= infinite_output_sign_dffe42_wi;
infinite_output_sign_dffe4_wi <= infinite_output_sign_dffe41_wo;
infinite_output_sign_dffe4_wo <= infinite_output_sign_dffe4;
infinite_res_dff32_wi <= wire_w_lg_w_exp_res_max_w_range555w561w(0);
infinite_res_dff32_wo <= infinite_res_dff32_wi;
infinite_res_dff33_wi <= infinite_res_dff32_wo;
infinite_res_dff33_wo <= infinite_res_dff33_wi;
infinite_res_dffe3_wi <= infinite_res_dff33_wo;
infinite_res_dffe3_wo <= infinite_res_dffe3;
infinite_res_dffe41_wi <= infinite_res_dffe42_wo;
infinite_res_dffe41_wo <= infinite_res_dffe41_wi;
infinite_res_dffe42_wi <= infinite_res_dffe3_wo;
infinite_res_dffe42_wo <= infinite_res_dffe42_wi;
infinite_res_dffe4_wi <= infinite_res_dffe41_wo;
infinite_res_dffe4_wo <= infinite_res_dffe4;
infinity_magnitude_sub_dffe21_wi <= infinity_magnitude_sub_dffe27_wo;
infinity_magnitude_sub_dffe21_wo <= infinity_magnitude_sub_dffe21;
infinity_magnitude_sub_dffe22_wi <= infinity_magnitude_sub_dffe2_wo;
infinity_magnitude_sub_dffe22_wo <= infinity_magnitude_sub_dffe22_wi;
infinity_magnitude_sub_dffe23_wi <= infinity_magnitude_sub_dffe21_wo;
infinity_magnitude_sub_dffe23_wo <= infinity_magnitude_sub_dffe23_wi;
infinity_magnitude_sub_dffe26_wi <= infinity_magnitude_sub_dffe23_wo;
infinity_magnitude_sub_dffe26_wo <= infinity_magnitude_sub_dffe26_wi;
infinity_magnitude_sub_dffe27_wi <= infinity_magnitude_sub_dffe22_wo;
infinity_magnitude_sub_dffe27_wo <= infinity_magnitude_sub_dffe27_wi;
infinity_magnitude_sub_dffe2_wi <= (wire_w_lg_add_sub_dffe25_wo491w(0) AND both_inputs_are_infinite_dffe25_wo);
infinity_magnitude_sub_dffe2_wo <= infinity_magnitude_sub_dffe2;
infinity_magnitude_sub_dffe31_wi <= infinity_magnitude_sub_dffe26_wo;
infinity_magnitude_sub_dffe31_wo <= infinity_magnitude_sub_dffe31;
infinity_magnitude_sub_dffe32_wi <= infinity_magnitude_sub_dffe31_wo;
infinity_magnitude_sub_dffe32_wo <= infinity_magnitude_sub_dffe32_wi;
infinity_magnitude_sub_dffe33_wi <= infinity_magnitude_sub_dffe32_wo;
infinity_magnitude_sub_dffe33_wo <= infinity_magnitude_sub_dffe33_wi;
infinity_magnitude_sub_dffe3_wi <= infinity_magnitude_sub_dffe33_wo;
infinity_magnitude_sub_dffe3_wo <= infinity_magnitude_sub_dffe3;
infinity_magnitude_sub_dffe41_wi <= infinity_magnitude_sub_dffe42_wo;
infinity_magnitude_sub_dffe41_wo <= infinity_magnitude_sub_dffe41_wi;
infinity_magnitude_sub_dffe42_wi <= infinity_magnitude_sub_dffe3_wo;
infinity_magnitude_sub_dffe42_wo <= infinity_magnitude_sub_dffe42_wi;
infinity_magnitude_sub_dffe4_wi <= infinity_magnitude_sub_dffe41_wo;
infinity_magnitude_sub_dffe4_wo <= infinity_magnitude_sub_dffe4;
input_dataa_denormal_dffe11_wi <= input_dataa_denormal_w;
input_dataa_denormal_dffe11_wo <= input_dataa_denormal_dffe11_wi;
input_dataa_denormal_w <= ((NOT exp_a_not_zero_w(7)) AND man_a_not_zero_w(22));
input_dataa_infinite_dffe11_wi <= input_dataa_infinite_w;
input_dataa_infinite_dffe11_wo <= input_dataa_infinite_dffe11_wi;
input_dataa_infinite_dffe12_wi <= input_dataa_infinite_dffe11_wo;
input_dataa_infinite_dffe12_wo <= input_dataa_infinite_dffe12_wi;
input_dataa_infinite_dffe13_wi <= input_dataa_infinite_dffe12_wo;
input_dataa_infinite_dffe13_wo <= input_dataa_infinite_dffe13_wi;
input_dataa_infinite_dffe14_wi <= input_dataa_infinite_dffe13_wo;
input_dataa_infinite_dffe14_wo <= input_dataa_infinite_dffe14_wi;
input_dataa_infinite_dffe15_wi <= input_dataa_infinite_dffe14_wo;
input_dataa_infinite_dffe15_wo <= input_dataa_infinite_dffe15_wi;
input_dataa_infinite_w <= wire_w_lg_w_exp_a_all_one_w_range84w220w(0);
input_dataa_nan_dffe11_wi <= input_dataa_nan_w;
input_dataa_nan_dffe11_wo <= input_dataa_nan_dffe11_wi;
input_dataa_nan_dffe12_wi <= input_dataa_nan_dffe11_wo;
input_dataa_nan_dffe12_wo <= input_dataa_nan_dffe12_wi;
input_dataa_nan_w <= (exp_a_all_one_w(7) AND man_a_not_zero_w(22));
input_dataa_zero_dffe11_wi <= input_dataa_zero_w;
input_dataa_zero_dffe11_wo <= input_dataa_zero_dffe11_wi;
input_dataa_zero_w <= ((NOT exp_a_not_zero_w(7)) AND wire_w_lg_w_man_a_not_zero_w_range215w219w(0));
input_datab_denormal_dffe11_wi <= input_datab_denormal_w;
input_datab_denormal_dffe11_wo <= input_datab_denormal_dffe11_wi;
input_datab_denormal_w <= ((NOT exp_b_not_zero_w(7)) AND man_b_not_zero_w(22));
input_datab_infinite_dffe11_wi <= input_datab_infinite_w;
input_datab_infinite_dffe11_wo <= input_datab_infinite_dffe11_wi;
input_datab_infinite_dffe12_wi <= input_datab_infinite_dffe11_wo;
input_datab_infinite_dffe12_wo <= input_datab_infinite_dffe12_wi;
input_datab_infinite_dffe13_wi <= input_datab_infinite_dffe12_wo;
input_datab_infinite_dffe13_wo <= input_datab_infinite_dffe13_wi;
input_datab_infinite_dffe14_wi <= input_datab_infinite_dffe13_wo;
input_datab_infinite_dffe14_wo <= input_datab_infinite_dffe14_wi;
input_datab_infinite_dffe15_wi <= input_datab_infinite_dffe14_wo;
input_datab_infinite_dffe15_wo <= input_datab_infinite_dffe15_wi;
input_datab_infinite_w <= wire_w_lg_w_exp_b_all_one_w_range86w226w(0);
input_datab_nan_dffe11_wi <= input_datab_nan_w;
input_datab_nan_dffe11_wo <= input_datab_nan_dffe11_wi;
input_datab_nan_dffe12_wi <= input_datab_nan_dffe11_wo;
input_datab_nan_dffe12_wo <= input_datab_nan_dffe12_wi;
input_datab_nan_w <= (exp_b_all_one_w(7) AND man_b_not_zero_w(22));
input_datab_zero_dffe11_wi <= input_datab_zero_w;
input_datab_zero_dffe11_wo <= input_datab_zero_dffe11_wi;
input_datab_zero_w <= ((NOT exp_b_not_zero_w(7)) AND wire_w_lg_w_man_b_not_zero_w_range218w225w(0));
input_is_infinite_dffe1_wi <= (input_dataa_infinite_dffe15_wo OR input_datab_infinite_dffe15_wo);
input_is_infinite_dffe1_wo <= input_is_infinite_dffe1;
input_is_infinite_dffe21_wi <= input_is_infinite_dffe27_wo;
input_is_infinite_dffe21_wo <= input_is_infinite_dffe21;
input_is_infinite_dffe22_wi <= input_is_infinite_dffe2_wo;
input_is_infinite_dffe22_wo <= input_is_infinite_dffe22_wi;
input_is_infinite_dffe23_wi <= input_is_infinite_dffe21_wo;
input_is_infinite_dffe23_wo <= input_is_infinite_dffe23_wi;
input_is_infinite_dffe25_wi <= input_is_infinite_dffe1_wo;
input_is_infinite_dffe25_wo <= input_is_infinite_dffe25_wi;
input_is_infinite_dffe26_wi <= input_is_infinite_dffe23_wo;
input_is_infinite_dffe26_wo <= input_is_infinite_dffe26_wi;
input_is_infinite_dffe27_wi <= input_is_infinite_dffe22_wo;
input_is_infinite_dffe27_wo <= input_is_infinite_dffe27_wi;
input_is_infinite_dffe2_wi <= input_is_infinite_dffe25_wo;
input_is_infinite_dffe2_wo <= input_is_infinite_dffe2;
input_is_infinite_dffe31_wi <= input_is_infinite_dffe26_wo;
input_is_infinite_dffe31_wo <= input_is_infinite_dffe31;
input_is_infinite_dffe32_wi <= input_is_infinite_dffe31_wo;
input_is_infinite_dffe32_wo <= input_is_infinite_dffe32_wi;
input_is_infinite_dffe33_wi <= input_is_infinite_dffe32_wo;
input_is_infinite_dffe33_wo <= input_is_infinite_dffe33_wi;
input_is_infinite_dffe3_wi <= input_is_infinite_dffe33_wo;
input_is_infinite_dffe3_wo <= input_is_infinite_dffe3;
input_is_infinite_dffe41_wi <= input_is_infinite_dffe42_wo;
input_is_infinite_dffe41_wo <= input_is_infinite_dffe41_wi;
input_is_infinite_dffe42_wi <= input_is_infinite_dffe3_wo;
input_is_infinite_dffe42_wo <= input_is_infinite_dffe42_wi;
input_is_infinite_dffe4_wi <= input_is_infinite_dffe41_wo;
input_is_infinite_dffe4_wo <= input_is_infinite_dffe4;
input_is_nan_dffe13_wi <= (input_dataa_nan_dffe12_wo OR input_datab_nan_dffe12_wo);
input_is_nan_dffe13_wo <= input_is_nan_dffe13_wi;
input_is_nan_dffe14_wi <= input_is_nan_dffe13_wo;
input_is_nan_dffe14_wo <= input_is_nan_dffe14_wi;
input_is_nan_dffe15_wi <= input_is_nan_dffe14_wo;
input_is_nan_dffe15_wo <= input_is_nan_dffe15_wi;
input_is_nan_dffe1_wi <= input_is_nan_dffe15_wo;
input_is_nan_dffe1_wo <= input_is_nan_dffe1;
input_is_nan_dffe21_wi <= input_is_nan_dffe27_wo;
input_is_nan_dffe21_wo <= input_is_nan_dffe21;
input_is_nan_dffe22_wi <= input_is_nan_dffe2_wo;
input_is_nan_dffe22_wo <= input_is_nan_dffe22_wi;
input_is_nan_dffe23_wi <= input_is_nan_dffe21_wo;
input_is_nan_dffe23_wo <= input_is_nan_dffe23_wi;
input_is_nan_dffe25_wi <= input_is_nan_dffe1_wo;
input_is_nan_dffe25_wo <= input_is_nan_dffe25_wi;
input_is_nan_dffe26_wi <= input_is_nan_dffe23_wo;
input_is_nan_dffe26_wo <= input_is_nan_dffe26_wi;
input_is_nan_dffe27_wi <= input_is_nan_dffe22_wo;
input_is_nan_dffe27_wo <= input_is_nan_dffe27_wi;
input_is_nan_dffe2_wi <= input_is_nan_dffe25_wo;
input_is_nan_dffe2_wo <= input_is_nan_dffe2;
input_is_nan_dffe31_wi <= input_is_nan_dffe26_wo;
input_is_nan_dffe31_wo <= input_is_nan_dffe31;
input_is_nan_dffe32_wi <= input_is_nan_dffe31_wo;
input_is_nan_dffe32_wo <= input_is_nan_dffe32_wi;
input_is_nan_dffe33_wi <= input_is_nan_dffe32_wo;
input_is_nan_dffe33_wo <= input_is_nan_dffe33_wi;
input_is_nan_dffe3_wi <= input_is_nan_dffe33_wo;
input_is_nan_dffe3_wo <= input_is_nan_dffe3;
input_is_nan_dffe41_wi <= input_is_nan_dffe42_wo;
input_is_nan_dffe41_wo <= input_is_nan_dffe41_wi;
input_is_nan_dffe42_wi <= input_is_nan_dffe3_wo;
input_is_nan_dffe42_wo <= input_is_nan_dffe42_wi;
input_is_nan_dffe4_wi <= input_is_nan_dffe41_wo;
input_is_nan_dffe4_wo <= input_is_nan_dffe4;
man_2comp_res_dataa_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_2comp_res_datab_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_2comp_res_w <= ( wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w & wire_man_2comp_res_lower_result);
man_a_not_zero_w <= ( wire_w_lg_w_dataa_range213w214w & wire_w_lg_w_dataa_range207w208w & wire_w_lg_w_dataa_range201w202w & wire_w_lg_w_dataa_range195w196w & wire_w_lg_w_dataa_range189w190w & wire_w_lg_w_dataa_range183w184w & wire_w_lg_w_dataa_range177w178w & wire_w_lg_w_dataa_range171w172w & wire_w_lg_w_dataa_range165w166w & wire_w_lg_w_dataa_range159w160w & wire_w_lg_w_dataa_range153w154w & wire_w_lg_w_dataa_range147w148w & wire_w_lg_w_dataa_range141w142w & wire_w_lg_w_dataa_range135w136w & wire_w_lg_w_dataa_range129w130w & wire_w_lg_w_dataa_range123w124w & wire_w_lg_w_dataa_range117w118w & wire_w_lg_w_dataa_range111w112w & wire_w_lg_w_dataa_range105w106w & wire_w_lg_w_dataa_range99w100w & wire_w_lg_w_dataa_range93w94w & wire_w_lg_w_dataa_range87w88w & dataa(0));
man_add_sub_dataa_w <= ( pos_sign_bit_ext & dataa_man_dffe1_wo);
man_add_sub_datab_w <= ( pos_sign_bit_ext & datab_man_dffe1_wo);
man_add_sub_res_mag_dffe21_wi <= man_res_mag_w2;
man_add_sub_res_mag_dffe21_wo <= man_add_sub_res_mag_dffe21;
man_add_sub_res_mag_dffe23_wi <= man_add_sub_res_mag_dffe21_wo;
man_add_sub_res_mag_dffe23_wo <= man_add_sub_res_mag_dffe23_wi;
man_add_sub_res_mag_dffe26_wi <= man_add_sub_res_mag_dffe23_wo;
man_add_sub_res_mag_dffe26_wo <= man_add_sub_res_mag_dffe26_wi;
man_add_sub_res_mag_dffe27_wi <= man_add_sub_res_mag_w2;
man_add_sub_res_mag_dffe27_wo <= man_add_sub_res_mag_dffe27_wi;
man_add_sub_res_mag_w2 <= (wire_w_lg_w_man_add_sub_w_range372w379w OR wire_w_lg_w_lg_w_man_add_sub_w_range372w375w378w);
man_add_sub_res_sign_dffe21_wo <= man_add_sub_res_sign_dffe21;
man_add_sub_res_sign_dffe23_wi <= man_add_sub_res_sign_dffe21_wo;
man_add_sub_res_sign_dffe23_wo <= man_add_sub_res_sign_dffe23_wi;
man_add_sub_res_sign_dffe26_wi <= man_add_sub_res_sign_dffe23_wo;
man_add_sub_res_sign_dffe26_wo <= man_add_sub_res_sign_dffe26_wi;
man_add_sub_res_sign_dffe27_wi <= man_add_sub_res_sign_w2;
man_add_sub_res_sign_dffe27_wo <= man_add_sub_res_sign_dffe27_wi;
man_add_sub_res_sign_w2 <= (wire_w_lg_need_complement_dffe22_wo376w(0) OR (wire_w_lg_need_complement_dffe22_wo373w(0) AND man_add_sub_w(27)));
man_add_sub_w <= ( wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w & wire_man_add_sub_lower_result);
man_all_zeros_w <= (OTHERS => '0');
man_b_not_zero_w <= ( wire_w_lg_w_datab_range216w217w & wire_w_lg_w_datab_range210w211w & wire_w_lg_w_datab_range204w205w & wire_w_lg_w_datab_range198w199w & wire_w_lg_w_datab_range192w193w & wire_w_lg_w_datab_range186w187w & wire_w_lg_w_datab_range180w181w & wire_w_lg_w_datab_range174w175w & wire_w_lg_w_datab_range168w169w & wire_w_lg_w_datab_range162w163w & wire_w_lg_w_datab_range156w157w & wire_w_lg_w_datab_range150w151w & wire_w_lg_w_datab_range144w145w & wire_w_lg_w_datab_range138w139w & wire_w_lg_w_datab_range132w133w & wire_w_lg_w_datab_range126w127w & wire_w_lg_w_datab_range120w121w & wire_w_lg_w_datab_range114w115w & wire_w_lg_w_datab_range108w109w & wire_w_lg_w_datab_range102w103w & wire_w_lg_w_datab_range96w97w & wire_w_lg_w_datab_range90w91w & datab(0));
man_dffe31_wo <= man_dffe31;
man_intermediate_res_w <= ( "00" & man_res_w3);
man_leading_zeros_cnt_w <= man_leading_zeros_dffe31_wo;
man_leading_zeros_dffe31_wi <= (NOT wire_leading_zeroes_cnt_q);
man_leading_zeros_dffe31_wo <= man_leading_zeros_dffe31;
man_nan_w <= "10000000000000000000000";
man_out_dffe5_wi <= (wire_w_lg_force_nan_w652w OR wire_w_lg_w_lg_force_nan_w630w651w);
man_out_dffe5_wo <= man_out_dffe5;
man_res_dffe4_wi <= man_rounded_res_w;
man_res_dffe4_wo <= man_res_dffe4;
man_res_is_not_zero_dffe31_wi <= man_res_not_zero_dffe26_wo;
man_res_is_not_zero_dffe31_wo <= man_res_is_not_zero_dffe31;
man_res_is_not_zero_dffe32_wi <= man_res_is_not_zero_dffe31_wo;
man_res_is_not_zero_dffe32_wo <= man_res_is_not_zero_dffe32_wi;
man_res_is_not_zero_dffe33_wi <= man_res_is_not_zero_dffe32_wo;
man_res_is_not_zero_dffe33_wo <= man_res_is_not_zero_dffe33_wi;
man_res_is_not_zero_dffe3_wi <= man_res_is_not_zero_dffe33_wo;
man_res_is_not_zero_dffe3_wo <= man_res_is_not_zero_dffe3;
man_res_is_not_zero_dffe41_wi <= man_res_is_not_zero_dffe42_wo;
man_res_is_not_zero_dffe41_wo <= man_res_is_not_zero_dffe41_wi;
man_res_is_not_zero_dffe42_wi <= man_res_is_not_zero_dffe3_wo;
man_res_is_not_zero_dffe42_wo <= man_res_is_not_zero_dffe42_wi;
man_res_is_not_zero_dffe4_wi <= man_res_is_not_zero_dffe41_wo;
man_res_is_not_zero_dffe4_wo <= man_res_is_not_zero_dffe4;
man_res_mag_w2 <= (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w414w OR wire_w412w);
man_res_not_zero_dffe23_wi <= man_res_not_zero_w2(24);
man_res_not_zero_dffe23_wo <= man_res_not_zero_dffe23_wi;
man_res_not_zero_dffe26_wi <= man_res_not_zero_dffe23_wo;
man_res_not_zero_dffe26_wo <= man_res_not_zero_dffe26_wi;
man_res_not_zero_w2 <= ( wire_w_lg_w_man_res_not_zero_w2_range487w489w & wire_w_lg_w_man_res_not_zero_w2_range484w486w & wire_w_lg_w_man_res_not_zero_w2_range481w483w & wire_w_lg_w_man_res_not_zero_w2_range478w480w & wire_w_lg_w_man_res_not_zero_w2_range475w477w & wire_w_lg_w_man_res_not_zero_w2_range472w474w & wire_w_lg_w_man_res_not_zero_w2_range469w471w & wire_w_lg_w_man_res_not_zero_w2_range466w468w & wire_w_lg_w_man_res_not_zero_w2_range463w465w & wire_w_lg_w_man_res_not_zero_w2_range460w462w & wire_w_lg_w_man_res_not_zero_w2_range457w459w & wire_w_lg_w_man_res_not_zero_w2_range454w456w & wire_w_lg_w_man_res_not_zero_w2_range451w453w & wire_w_lg_w_man_res_not_zero_w2_range448w450w & wire_w_lg_w_man_res_not_zero_w2_range445w447w & wire_w_lg_w_man_res_not_zero_w2_range442w444w & wire_w_lg_w_man_res_not_zero_w2_range439w441w & wire_w_lg_w_man_res_not_zero_w2_range436w438w & wire_w_lg_w_man_res_not_zero_w2_range433w435w & wire_w_lg_w_man_res_not_zero_w2_range430w432w & wire_w_lg_w_man_res_not_zero_w2_range427w429w & wire_w_lg_w_man_res_not_zero_w2_range424w426w & wire_w_lg_w_man_res_not_zero_w2_range421w423w & wire_w_lg_w_man_res_not_zero_w2_range417w420w & man_add_sub_res_mag_dffe21_wo(1));
man_res_rounding_add_sub_datab_w <= ( "0000000000000000000000000" & man_rounding_add_value_w);
man_res_rounding_add_sub_w <= ( wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w & wire_man_res_rounding_add_sub_lower_result);
man_res_w3 <= wire_lbarrel_shift_result(25 DOWNTO 2);
man_rounded_res_w <= (wire_w_lg_w_man_res_rounding_add_sub_w_range585w589w OR wire_w587w);
man_rounding_add_value_w <= (round_bit_dffe3_wo AND (sticky_bit_dffe3_wo OR guard_bit_dffe3_wo));
man_smaller_dffe13_wi <= man_smaller_w;
man_smaller_dffe13_wo <= man_smaller_dffe13_wi;
man_smaller_w <= (wire_w_lg_exp_amb_mux_w279w OR wire_w_lg_w_lg_exp_amb_mux_w275w278w);
need_complement_dffe22_wi <= need_complement_dffe2_wo;
need_complement_dffe22_wo <= need_complement_dffe22_wi;
need_complement_dffe2_wi <= dataa_sign_dffe25_wo;
need_complement_dffe2_wo <= need_complement_dffe2;
pos_sign_bit_ext <= (OTHERS => '0');
priority_encoder_1pads_w <= (OTHERS => '1');
result <= ( sign_out_dffe5_wo & exp_out_dffe5_wo & man_out_dffe5_wo);
round_bit_dffe21_wi <= round_bit_w;
round_bit_dffe21_wo <= round_bit_dffe21;
round_bit_dffe23_wi <= round_bit_dffe21_wo;
round_bit_dffe23_wo <= round_bit_dffe23_wi;
round_bit_dffe26_wi <= round_bit_dffe23_wo;
round_bit_dffe26_wo <= round_bit_dffe26_wi;
round_bit_dffe31_wi <= round_bit_dffe26_wo;
round_bit_dffe31_wo <= round_bit_dffe31;
round_bit_dffe32_wi <= round_bit_dffe31_wo;
round_bit_dffe32_wo <= round_bit_dffe32_wi;
round_bit_dffe33_wi <= round_bit_dffe32_wo;
round_bit_dffe33_wo <= round_bit_dffe33_wi;
round_bit_dffe3_wi <= round_bit_dffe33_wo;
round_bit_dffe3_wo <= round_bit_dffe3;
round_bit_w <= ((((wire_w397w(0) AND man_add_sub_res_mag_dffe27_wo(0)) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(1))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND man_add_sub_res_mag_dffe27_wo(2))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND man_add_sub_res_mag_dffe27_wo(2)));
rounded_res_infinity_dffe4_wi <= exp_rounded_res_infinity_w;
rounded_res_infinity_dffe4_wo <= rounded_res_infinity_dffe4;
rshift_distance_dffe13_wi <= rshift_distance_w;
rshift_distance_dffe13_wo <= rshift_distance_dffe13_wi;
rshift_distance_dffe14_wi <= rshift_distance_dffe13_wo;
rshift_distance_dffe14_wo <= rshift_distance_dffe14_wi;
rshift_distance_dffe15_wi <= rshift_distance_dffe14_wo;
rshift_distance_dffe15_wo <= rshift_distance_dffe15_wi;
rshift_distance_w <= (wire_w_lg_w_exp_diff_abs_exceed_max_w_range289w293w OR wire_w292w);
sign_dffe31_wi <= ((man_res_not_zero_dffe26_wo AND man_add_sub_res_sign_dffe26_wo) OR wire_w_lg_w_lg_man_res_not_zero_dffe26_wo503w504w(0));
sign_dffe31_wo <= sign_dffe31;
sign_dffe32_wi <= sign_dffe31_wo;
sign_dffe32_wo <= sign_dffe32_wi;
sign_dffe33_wi <= sign_dffe32_wo;
sign_dffe33_wo <= sign_dffe33_wi;
sign_out_dffe5_wi <= (wire_w_lg_force_nan_w630w(0) AND ((force_infinity_w AND infinite_output_sign_dffe4_wo) OR wire_w_lg_w_lg_force_infinity_w629w654w(0)));
sign_out_dffe5_wo <= sign_out_dffe5;
sign_res_dffe3_wi <= sign_dffe33_wo;
sign_res_dffe3_wo <= sign_res_dffe3;
sign_res_dffe41_wi <= sign_res_dffe42_wo;
sign_res_dffe41_wo <= sign_res_dffe41_wi;
sign_res_dffe42_wi <= sign_res_dffe3_wo;
sign_res_dffe42_wo <= sign_res_dffe42_wi;
sign_res_dffe4_wi <= sign_res_dffe41_wo;
sign_res_dffe4_wo <= sign_res_dffe4;
sticky_bit_cnt_dataa_w <= ( "0" & rshift_distance_dffe15_wo);
sticky_bit_cnt_datab_w <= ( "0" & wire_trailing_zeros_cnt_q);
sticky_bit_cnt_res_w <= wire_add_sub3_result;
sticky_bit_dffe1_wi <= wire_trailing_zeros_limit_comparator_agb;
sticky_bit_dffe1_wo <= sticky_bit_dffe1;
sticky_bit_dffe21_wi <= sticky_bit_w;
sticky_bit_dffe21_wo <= sticky_bit_dffe21;
sticky_bit_dffe22_wi <= sticky_bit_dffe2_wo;
sticky_bit_dffe22_wo <= sticky_bit_dffe22_wi;
sticky_bit_dffe23_wi <= sticky_bit_dffe21_wo;
sticky_bit_dffe23_wo <= sticky_bit_dffe23_wi;
sticky_bit_dffe25_wi <= sticky_bit_dffe1_wo;
sticky_bit_dffe25_wo <= sticky_bit_dffe25_wi;
sticky_bit_dffe26_wi <= sticky_bit_dffe23_wo;
sticky_bit_dffe26_wo <= sticky_bit_dffe26_wi;
sticky_bit_dffe27_wi <= sticky_bit_dffe22_wo;
sticky_bit_dffe27_wo <= sticky_bit_dffe27_wi;
sticky_bit_dffe2_wi <= sticky_bit_dffe25_wo;
sticky_bit_dffe2_wo <= sticky_bit_dffe2;
sticky_bit_dffe31_wi <= sticky_bit_dffe26_wo;
sticky_bit_dffe31_wo <= sticky_bit_dffe31;
sticky_bit_dffe32_wi <= sticky_bit_dffe31_wo;
sticky_bit_dffe32_wo <= sticky_bit_dffe32_wi;
sticky_bit_dffe33_wi <= sticky_bit_dffe32_wo;
sticky_bit_dffe33_wo <= sticky_bit_dffe33_wi;
sticky_bit_dffe3_wi <= sticky_bit_dffe33_wo;
sticky_bit_dffe3_wo <= sticky_bit_dffe3;
sticky_bit_w <= (((wire_w_lg_w397w407w(0) OR ((wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w382w(0) AND man_add_sub_res_mag_dffe27_wo(25)) AND wire_w_lg_sticky_bit_dffe27_wo402w(0))) OR (wire_w_lg_w_man_add_sub_res_mag_dffe27_wo_range381w391w(0) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1)))) OR ((man_add_sub_res_mag_dffe27_wo(26) AND man_add_sub_res_mag_dffe27_wo(25)) AND (wire_w_lg_sticky_bit_dffe27_wo402w(0) OR man_add_sub_res_mag_dffe27_wo(1))));
trailing_zeros_limit_w <= "000010";
zero_man_sign_dffe21_wi <= zero_man_sign_dffe27_wo;
zero_man_sign_dffe21_wo <= zero_man_sign_dffe21;
zero_man_sign_dffe22_wi <= zero_man_sign_dffe2_wo;
zero_man_sign_dffe22_wo <= zero_man_sign_dffe22_wi;
zero_man_sign_dffe23_wi <= zero_man_sign_dffe21_wo;
zero_man_sign_dffe23_wo <= zero_man_sign_dffe23_wi;
zero_man_sign_dffe26_wi <= zero_man_sign_dffe23_wo;
zero_man_sign_dffe26_wo <= zero_man_sign_dffe26_wi;
zero_man_sign_dffe27_wi <= zero_man_sign_dffe22_wo;
zero_man_sign_dffe27_wo <= zero_man_sign_dffe27_wi;
zero_man_sign_dffe2_wi <= (dataa_sign_dffe25_wo AND add_sub_dffe25_wo);
zero_man_sign_dffe2_wo <= zero_man_sign_dffe2;
wire_w_aligned_dataa_exp_dffe15_wo_range315w <= aligned_dataa_exp_dffe15_wo(7 DOWNTO 0);
wire_w_aligned_datab_exp_dffe15_wo_range313w <= aligned_datab_exp_dffe15_wo(7 DOWNTO 0);
wire_w_dataa_range141w(0) <= dataa(10);
wire_w_dataa_range147w(0) <= dataa(11);
wire_w_dataa_range153w(0) <= dataa(12);
wire_w_dataa_range159w(0) <= dataa(13);
wire_w_dataa_range165w(0) <= dataa(14);
wire_w_dataa_range171w(0) <= dataa(15);
wire_w_dataa_range177w(0) <= dataa(16);
wire_w_dataa_range183w(0) <= dataa(17);
wire_w_dataa_range189w(0) <= dataa(18);
wire_w_dataa_range195w(0) <= dataa(19);
wire_w_dataa_range87w(0) <= dataa(1);
wire_w_dataa_range201w(0) <= dataa(20);
wire_w_dataa_range207w(0) <= dataa(21);
wire_w_dataa_range213w(0) <= dataa(22);
wire_w_dataa_range17w(0) <= dataa(24);
wire_w_dataa_range27w(0) <= dataa(25);
wire_w_dataa_range37w(0) <= dataa(26);
wire_w_dataa_range47w(0) <= dataa(27);
wire_w_dataa_range57w(0) <= dataa(28);
wire_w_dataa_range67w(0) <= dataa(29);
wire_w_dataa_range93w(0) <= dataa(2);
wire_w_dataa_range77w(0) <= dataa(30);
wire_w_dataa_range99w(0) <= dataa(3);
wire_w_dataa_range105w(0) <= dataa(4);
wire_w_dataa_range111w(0) <= dataa(5);
wire_w_dataa_range117w(0) <= dataa(6);
wire_w_dataa_range123w(0) <= dataa(7);
wire_w_dataa_range129w(0) <= dataa(8);
wire_w_dataa_range135w(0) <= dataa(9);
wire_w_dataa_dffe11_wo_range242w <= dataa_dffe11_wo(22 DOWNTO 0);
wire_w_dataa_dffe11_wo_range232w <= dataa_dffe11_wo(30 DOWNTO 23);
wire_w_datab_range144w(0) <= datab(10);
wire_w_datab_range150w(0) <= datab(11);
wire_w_datab_range156w(0) <= datab(12);
wire_w_datab_range162w(0) <= datab(13);
wire_w_datab_range168w(0) <= datab(14);
wire_w_datab_range174w(0) <= datab(15);
wire_w_datab_range180w(0) <= datab(16);
wire_w_datab_range186w(0) <= datab(17);
wire_w_datab_range192w(0) <= datab(18);
wire_w_datab_range198w(0) <= datab(19);
wire_w_datab_range90w(0) <= datab(1);
wire_w_datab_range204w(0) <= datab(20);
wire_w_datab_range210w(0) <= datab(21);
wire_w_datab_range216w(0) <= datab(22);
wire_w_datab_range20w(0) <= datab(24);
wire_w_datab_range30w(0) <= datab(25);
wire_w_datab_range40w(0) <= datab(26);
wire_w_datab_range50w(0) <= datab(27);
wire_w_datab_range60w(0) <= datab(28);
wire_w_datab_range70w(0) <= datab(29);
wire_w_datab_range96w(0) <= datab(2);
wire_w_datab_range80w(0) <= datab(30);
wire_w_datab_range102w(0) <= datab(3);
wire_w_datab_range108w(0) <= datab(4);
wire_w_datab_range114w(0) <= datab(5);
wire_w_datab_range120w(0) <= datab(6);
wire_w_datab_range126w(0) <= datab(7);
wire_w_datab_range132w(0) <= datab(8);
wire_w_datab_range138w(0) <= datab(9);
wire_w_datab_dffe11_wo_range261w <= datab_dffe11_wo(22 DOWNTO 0);
wire_w_datab_dffe11_wo_range251w <= datab_dffe11_wo(30 DOWNTO 23);
wire_w_exp_a_all_one_w_range7w(0) <= exp_a_all_one_w(0);
wire_w_exp_a_all_one_w_range24w(0) <= exp_a_all_one_w(1);
wire_w_exp_a_all_one_w_range34w(0) <= exp_a_all_one_w(2);
wire_w_exp_a_all_one_w_range44w(0) <= exp_a_all_one_w(3);
wire_w_exp_a_all_one_w_range54w(0) <= exp_a_all_one_w(4);
wire_w_exp_a_all_one_w_range64w(0) <= exp_a_all_one_w(5);
wire_w_exp_a_all_one_w_range74w(0) <= exp_a_all_one_w(6);
wire_w_exp_a_all_one_w_range84w(0) <= exp_a_all_one_w(7);
wire_w_exp_a_not_zero_w_range2w(0) <= exp_a_not_zero_w(0);
wire_w_exp_a_not_zero_w_range19w(0) <= exp_a_not_zero_w(1);
wire_w_exp_a_not_zero_w_range29w(0) <= exp_a_not_zero_w(2);
wire_w_exp_a_not_zero_w_range39w(0) <= exp_a_not_zero_w(3);
wire_w_exp_a_not_zero_w_range49w(0) <= exp_a_not_zero_w(4);
wire_w_exp_a_not_zero_w_range59w(0) <= exp_a_not_zero_w(5);
wire_w_exp_a_not_zero_w_range69w(0) <= exp_a_not_zero_w(6);
wire_w_exp_adjustment2_add_sub_w_range518w(0) <= exp_adjustment2_add_sub_w(1);
wire_w_exp_adjustment2_add_sub_w_range521w(0) <= exp_adjustment2_add_sub_w(2);
wire_w_exp_adjustment2_add_sub_w_range524w(0) <= exp_adjustment2_add_sub_w(3);
wire_w_exp_adjustment2_add_sub_w_range527w(0) <= exp_adjustment2_add_sub_w(4);
wire_w_exp_adjustment2_add_sub_w_range530w(0) <= exp_adjustment2_add_sub_w(5);
wire_w_exp_adjustment2_add_sub_w_range533w(0) <= exp_adjustment2_add_sub_w(6);
wire_w_exp_adjustment2_add_sub_w_range557w <= exp_adjustment2_add_sub_w(7 DOWNTO 0);
wire_w_exp_adjustment2_add_sub_w_range536w(0) <= exp_adjustment2_add_sub_w(7);
wire_w_exp_adjustment2_add_sub_w_range511w(0) <= exp_adjustment2_add_sub_w(8);
wire_w_exp_amb_w_range274w <= exp_amb_w(7 DOWNTO 0);
wire_w_exp_b_all_one_w_range9w(0) <= exp_b_all_one_w(0);
wire_w_exp_b_all_one_w_range26w(0) <= exp_b_all_one_w(1);
wire_w_exp_b_all_one_w_range36w(0) <= exp_b_all_one_w(2);
wire_w_exp_b_all_one_w_range46w(0) <= exp_b_all_one_w(3);
wire_w_exp_b_all_one_w_range56w(0) <= exp_b_all_one_w(4);
wire_w_exp_b_all_one_w_range66w(0) <= exp_b_all_one_w(5);
wire_w_exp_b_all_one_w_range76w(0) <= exp_b_all_one_w(6);
wire_w_exp_b_all_one_w_range86w(0) <= exp_b_all_one_w(7);
wire_w_exp_b_not_zero_w_range5w(0) <= exp_b_not_zero_w(0);
wire_w_exp_b_not_zero_w_range22w(0) <= exp_b_not_zero_w(1);
wire_w_exp_b_not_zero_w_range32w(0) <= exp_b_not_zero_w(2);
wire_w_exp_b_not_zero_w_range42w(0) <= exp_b_not_zero_w(3);
wire_w_exp_b_not_zero_w_range52w(0) <= exp_b_not_zero_w(4);
wire_w_exp_b_not_zero_w_range62w(0) <= exp_b_not_zero_w(5);
wire_w_exp_b_not_zero_w_range72w(0) <= exp_b_not_zero_w(6);
wire_w_exp_bma_w_range272w <= exp_bma_w(7 DOWNTO 0);
wire_w_exp_diff_abs_exceed_max_w_range282w(0) <= exp_diff_abs_exceed_max_w(0);
wire_w_exp_diff_abs_exceed_max_w_range286w(0) <= exp_diff_abs_exceed_max_w(1);
wire_w_exp_diff_abs_exceed_max_w_range289w(0) <= exp_diff_abs_exceed_max_w(2);
wire_w_exp_diff_abs_w_range290w <= exp_diff_abs_w(4 DOWNTO 0);
wire_w_exp_diff_abs_w_range284w(0) <= exp_diff_abs_w(6);
wire_w_exp_diff_abs_w_range287w(0) <= exp_diff_abs_w(7);
wire_w_exp_res_max_w_range540w(0) <= exp_res_max_w(0);
wire_w_exp_res_max_w_range543w(0) <= exp_res_max_w(1);
wire_w_exp_res_max_w_range545w(0) <= exp_res_max_w(2);
wire_w_exp_res_max_w_range547w(0) <= exp_res_max_w(3);
wire_w_exp_res_max_w_range549w(0) <= exp_res_max_w(4);
wire_w_exp_res_max_w_range551w(0) <= exp_res_max_w(5);
wire_w_exp_res_max_w_range553w(0) <= exp_res_max_w(6);
wire_w_exp_res_max_w_range555w(0) <= exp_res_max_w(7);
wire_w_exp_res_not_zero_w_range516w(0) <= exp_res_not_zero_w(0);
wire_w_exp_res_not_zero_w_range520w(0) <= exp_res_not_zero_w(1);
wire_w_exp_res_not_zero_w_range523w(0) <= exp_res_not_zero_w(2);
wire_w_exp_res_not_zero_w_range526w(0) <= exp_res_not_zero_w(3);
wire_w_exp_res_not_zero_w_range529w(0) <= exp_res_not_zero_w(4);
wire_w_exp_res_not_zero_w_range532w(0) <= exp_res_not_zero_w(5);
wire_w_exp_res_not_zero_w_range535w(0) <= exp_res_not_zero_w(6);
wire_w_exp_res_not_zero_w_range538w(0) <= exp_res_not_zero_w(7);
wire_w_exp_rounded_res_max_w_range601w(0) <= exp_rounded_res_max_w(0);
wire_w_exp_rounded_res_max_w_range605w(0) <= exp_rounded_res_max_w(1);
wire_w_exp_rounded_res_max_w_range608w(0) <= exp_rounded_res_max_w(2);
wire_w_exp_rounded_res_max_w_range611w(0) <= exp_rounded_res_max_w(3);
wire_w_exp_rounded_res_max_w_range614w(0) <= exp_rounded_res_max_w(4);
wire_w_exp_rounded_res_max_w_range617w(0) <= exp_rounded_res_max_w(5);
wire_w_exp_rounded_res_max_w_range620w(0) <= exp_rounded_res_max_w(6);
wire_w_exp_rounded_res_w_range603w(0) <= exp_rounded_res_w(1);
wire_w_exp_rounded_res_w_range606w(0) <= exp_rounded_res_w(2);
wire_w_exp_rounded_res_w_range609w(0) <= exp_rounded_res_w(3);
wire_w_exp_rounded_res_w_range612w(0) <= exp_rounded_res_w(4);
wire_w_exp_rounded_res_w_range615w(0) <= exp_rounded_res_w(5);
wire_w_exp_rounded_res_w_range618w(0) <= exp_rounded_res_w(6);
wire_w_exp_rounded_res_w_range621w(0) <= exp_rounded_res_w(7);
wire_w_man_a_not_zero_w_range12w(0) <= man_a_not_zero_w(0);
wire_w_man_a_not_zero_w_range143w(0) <= man_a_not_zero_w(10);
wire_w_man_a_not_zero_w_range149w(0) <= man_a_not_zero_w(11);
wire_w_man_a_not_zero_w_range155w(0) <= man_a_not_zero_w(12);
wire_w_man_a_not_zero_w_range161w(0) <= man_a_not_zero_w(13);
wire_w_man_a_not_zero_w_range167w(0) <= man_a_not_zero_w(14);
wire_w_man_a_not_zero_w_range173w(0) <= man_a_not_zero_w(15);
wire_w_man_a_not_zero_w_range179w(0) <= man_a_not_zero_w(16);
wire_w_man_a_not_zero_w_range185w(0) <= man_a_not_zero_w(17);
wire_w_man_a_not_zero_w_range191w(0) <= man_a_not_zero_w(18);
wire_w_man_a_not_zero_w_range197w(0) <= man_a_not_zero_w(19);
wire_w_man_a_not_zero_w_range89w(0) <= man_a_not_zero_w(1);
wire_w_man_a_not_zero_w_range203w(0) <= man_a_not_zero_w(20);
wire_w_man_a_not_zero_w_range209w(0) <= man_a_not_zero_w(21);
wire_w_man_a_not_zero_w_range215w(0) <= man_a_not_zero_w(22);
wire_w_man_a_not_zero_w_range95w(0) <= man_a_not_zero_w(2);
wire_w_man_a_not_zero_w_range101w(0) <= man_a_not_zero_w(3);
wire_w_man_a_not_zero_w_range107w(0) <= man_a_not_zero_w(4);
wire_w_man_a_not_zero_w_range113w(0) <= man_a_not_zero_w(5);
wire_w_man_a_not_zero_w_range119w(0) <= man_a_not_zero_w(6);
wire_w_man_a_not_zero_w_range125w(0) <= man_a_not_zero_w(7);
wire_w_man_a_not_zero_w_range131w(0) <= man_a_not_zero_w(8);
wire_w_man_a_not_zero_w_range137w(0) <= man_a_not_zero_w(9);
wire_w_man_add_sub_res_mag_dffe21_wo_range443w(0) <= man_add_sub_res_mag_dffe21_wo(10);
wire_w_man_add_sub_res_mag_dffe21_wo_range446w(0) <= man_add_sub_res_mag_dffe21_wo(11);
wire_w_man_add_sub_res_mag_dffe21_wo_range449w(0) <= man_add_sub_res_mag_dffe21_wo(12);
wire_w_man_add_sub_res_mag_dffe21_wo_range452w(0) <= man_add_sub_res_mag_dffe21_wo(13);
wire_w_man_add_sub_res_mag_dffe21_wo_range455w(0) <= man_add_sub_res_mag_dffe21_wo(14);
wire_w_man_add_sub_res_mag_dffe21_wo_range458w(0) <= man_add_sub_res_mag_dffe21_wo(15);
wire_w_man_add_sub_res_mag_dffe21_wo_range461w(0) <= man_add_sub_res_mag_dffe21_wo(16);
wire_w_man_add_sub_res_mag_dffe21_wo_range464w(0) <= man_add_sub_res_mag_dffe21_wo(17);
wire_w_man_add_sub_res_mag_dffe21_wo_range467w(0) <= man_add_sub_res_mag_dffe21_wo(18);
wire_w_man_add_sub_res_mag_dffe21_wo_range470w(0) <= man_add_sub_res_mag_dffe21_wo(19);
wire_w_man_add_sub_res_mag_dffe21_wo_range473w(0) <= man_add_sub_res_mag_dffe21_wo(20);
wire_w_man_add_sub_res_mag_dffe21_wo_range476w(0) <= man_add_sub_res_mag_dffe21_wo(21);
wire_w_man_add_sub_res_mag_dffe21_wo_range479w(0) <= man_add_sub_res_mag_dffe21_wo(22);
wire_w_man_add_sub_res_mag_dffe21_wo_range482w(0) <= man_add_sub_res_mag_dffe21_wo(23);
wire_w_man_add_sub_res_mag_dffe21_wo_range485w(0) <= man_add_sub_res_mag_dffe21_wo(24);
wire_w_man_add_sub_res_mag_dffe21_wo_range488w(0) <= man_add_sub_res_mag_dffe21_wo(25);
wire_w_man_add_sub_res_mag_dffe21_wo_range419w(0) <= man_add_sub_res_mag_dffe21_wo(2);
wire_w_man_add_sub_res_mag_dffe21_wo_range422w(0) <= man_add_sub_res_mag_dffe21_wo(3);
wire_w_man_add_sub_res_mag_dffe21_wo_range425w(0) <= man_add_sub_res_mag_dffe21_wo(4);
wire_w_man_add_sub_res_mag_dffe21_wo_range428w(0) <= man_add_sub_res_mag_dffe21_wo(5);
wire_w_man_add_sub_res_mag_dffe21_wo_range431w(0) <= man_add_sub_res_mag_dffe21_wo(6);
wire_w_man_add_sub_res_mag_dffe21_wo_range434w(0) <= man_add_sub_res_mag_dffe21_wo(7);
wire_w_man_add_sub_res_mag_dffe21_wo_range437w(0) <= man_add_sub_res_mag_dffe21_wo(8);
wire_w_man_add_sub_res_mag_dffe21_wo_range440w(0) <= man_add_sub_res_mag_dffe21_wo(9);
wire_w_man_add_sub_res_mag_dffe27_wo_range396w(0) <= man_add_sub_res_mag_dffe27_wo(0);
wire_w_man_add_sub_res_mag_dffe27_wo_range411w <= man_add_sub_res_mag_dffe27_wo(25 DOWNTO 0);
wire_w_man_add_sub_res_mag_dffe27_wo_range387w(0) <= man_add_sub_res_mag_dffe27_wo(25);
wire_w_man_add_sub_res_mag_dffe27_wo_range413w <= man_add_sub_res_mag_dffe27_wo(26 DOWNTO 1);
wire_w_man_add_sub_res_mag_dffe27_wo_range381w(0) <= man_add_sub_res_mag_dffe27_wo(26);
wire_w_man_add_sub_w_range372w(0) <= man_add_sub_w(27);
wire_w_man_b_not_zero_w_range15w(0) <= man_b_not_zero_w(0);
wire_w_man_b_not_zero_w_range146w(0) <= man_b_not_zero_w(10);
wire_w_man_b_not_zero_w_range152w(0) <= man_b_not_zero_w(11);
wire_w_man_b_not_zero_w_range158w(0) <= man_b_not_zero_w(12);
wire_w_man_b_not_zero_w_range164w(0) <= man_b_not_zero_w(13);
wire_w_man_b_not_zero_w_range170w(0) <= man_b_not_zero_w(14);
wire_w_man_b_not_zero_w_range176w(0) <= man_b_not_zero_w(15);
wire_w_man_b_not_zero_w_range182w(0) <= man_b_not_zero_w(16);
wire_w_man_b_not_zero_w_range188w(0) <= man_b_not_zero_w(17);
wire_w_man_b_not_zero_w_range194w(0) <= man_b_not_zero_w(18);
wire_w_man_b_not_zero_w_range200w(0) <= man_b_not_zero_w(19);
wire_w_man_b_not_zero_w_range92w(0) <= man_b_not_zero_w(1);
wire_w_man_b_not_zero_w_range206w(0) <= man_b_not_zero_w(20);
wire_w_man_b_not_zero_w_range212w(0) <= man_b_not_zero_w(21);
wire_w_man_b_not_zero_w_range218w(0) <= man_b_not_zero_w(22);
wire_w_man_b_not_zero_w_range98w(0) <= man_b_not_zero_w(2);
wire_w_man_b_not_zero_w_range104w(0) <= man_b_not_zero_w(3);
wire_w_man_b_not_zero_w_range110w(0) <= man_b_not_zero_w(4);
wire_w_man_b_not_zero_w_range116w(0) <= man_b_not_zero_w(5);
wire_w_man_b_not_zero_w_range122w(0) <= man_b_not_zero_w(6);
wire_w_man_b_not_zero_w_range128w(0) <= man_b_not_zero_w(7);
wire_w_man_b_not_zero_w_range134w(0) <= man_b_not_zero_w(8);
wire_w_man_b_not_zero_w_range140w(0) <= man_b_not_zero_w(9);
wire_w_man_res_not_zero_w2_range417w(0) <= man_res_not_zero_w2(0);
wire_w_man_res_not_zero_w2_range448w(0) <= man_res_not_zero_w2(10);
wire_w_man_res_not_zero_w2_range451w(0) <= man_res_not_zero_w2(11);
wire_w_man_res_not_zero_w2_range454w(0) <= man_res_not_zero_w2(12);
wire_w_man_res_not_zero_w2_range457w(0) <= man_res_not_zero_w2(13);
wire_w_man_res_not_zero_w2_range460w(0) <= man_res_not_zero_w2(14);
wire_w_man_res_not_zero_w2_range463w(0) <= man_res_not_zero_w2(15);
wire_w_man_res_not_zero_w2_range466w(0) <= man_res_not_zero_w2(16);
wire_w_man_res_not_zero_w2_range469w(0) <= man_res_not_zero_w2(17);
wire_w_man_res_not_zero_w2_range472w(0) <= man_res_not_zero_w2(18);
wire_w_man_res_not_zero_w2_range475w(0) <= man_res_not_zero_w2(19);
wire_w_man_res_not_zero_w2_range421w(0) <= man_res_not_zero_w2(1);
wire_w_man_res_not_zero_w2_range478w(0) <= man_res_not_zero_w2(20);
wire_w_man_res_not_zero_w2_range481w(0) <= man_res_not_zero_w2(21);
wire_w_man_res_not_zero_w2_range484w(0) <= man_res_not_zero_w2(22);
wire_w_man_res_not_zero_w2_range487w(0) <= man_res_not_zero_w2(23);
wire_w_man_res_not_zero_w2_range424w(0) <= man_res_not_zero_w2(2);
wire_w_man_res_not_zero_w2_range427w(0) <= man_res_not_zero_w2(3);
wire_w_man_res_not_zero_w2_range430w(0) <= man_res_not_zero_w2(4);
wire_w_man_res_not_zero_w2_range433w(0) <= man_res_not_zero_w2(5);
wire_w_man_res_not_zero_w2_range436w(0) <= man_res_not_zero_w2(6);
wire_w_man_res_not_zero_w2_range439w(0) <= man_res_not_zero_w2(7);
wire_w_man_res_not_zero_w2_range442w(0) <= man_res_not_zero_w2(8);
wire_w_man_res_not_zero_w2_range445w(0) <= man_res_not_zero_w2(9);
wire_w_man_res_rounding_add_sub_w_range584w <= man_res_rounding_add_sub_w(22 DOWNTO 0);
wire_w_man_res_rounding_add_sub_w_range588w <= man_res_rounding_add_sub_w(23 DOWNTO 1);
wire_w_man_res_rounding_add_sub_w_range585w(0) <= man_res_rounding_add_sub_w(24);
lbarrel_shift : fp_sub_altbarrel_shift_h0e
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
data => man_dffe31_wo,
distance => man_leading_zeros_cnt_w,
result => wire_lbarrel_shift_result
);
wire_rbarrel_shift_data <= ( man_smaller_dffe13_wo & "00");
rbarrel_shift : fp_sub_altbarrel_shift_6hb
PORT MAP (
data => wire_rbarrel_shift_data,
distance => rshift_distance_dffe13_wo,
result => wire_rbarrel_shift_result
);
wire_leading_zeroes_cnt_data <= ( man_add_sub_res_mag_dffe21_wo(25 DOWNTO 1) & "1" & "000000");
leading_zeroes_cnt : fp_sub_altpriority_encoder_qb6
PORT MAP (
data => wire_leading_zeroes_cnt_data,
q => wire_leading_zeroes_cnt_q
);
wire_trailing_zeros_cnt_data <= ( "111111111" & man_smaller_dffe13_wo(22 DOWNTO 0));
trailing_zeros_cnt : fp_sub_altpriority_encoder_e48
PORT MAP (
data => wire_trailing_zeros_cnt_data,
q => wire_trailing_zeros_cnt_q
);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN both_inputs_are_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN both_inputs_are_infinite_dffe1 <= both_inputs_are_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN data_exp_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN data_exp_dffe1 <= data_exp_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_man_dffe1 <= dataa_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN dataa_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN dataa_sign_dffe1 <= dataa_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_man_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_man_dffe1 <= datab_man_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN datab_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN datab_sign_dffe1 <= datab_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe3 <= denormal_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN denormal_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN denormal_res_dffe4 <= denormal_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_adj_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_adj_dffe21 <= exp_adj_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_out_dffe5 <= exp_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe2 <= exp_res_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe21 <= exp_res_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe3 <= exp_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_res_dffe4 <= exp_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe1 <= infinite_output_sign_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe2 <= infinite_output_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe21 <= infinite_output_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe3 <= infinite_output_sign_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe31 <= infinite_output_sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_output_sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_output_sign_dffe4 <= infinite_output_sign_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe3 <= infinite_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinite_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinite_res_dffe4 <= infinite_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe2 <= infinity_magnitude_sub_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe21 <= infinity_magnitude_sub_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe3 <= infinity_magnitude_sub_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe31 <= infinity_magnitude_sub_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN infinity_magnitude_sub_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN infinity_magnitude_sub_dffe4 <= infinity_magnitude_sub_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe1 <= input_is_infinite_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe2 <= input_is_infinite_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe21 <= input_is_infinite_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe3 <= input_is_infinite_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe31 <= input_is_infinite_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinite_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinite_dffe4 <= input_is_infinite_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe1 <= input_is_nan_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe2 <= input_is_nan_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe21 <= input_is_nan_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe3 <= input_is_nan_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe31 <= input_is_nan_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_dffe4 <= input_is_nan_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_mag_dffe21 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_mag_dffe21 <= man_add_sub_res_mag_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_add_sub_res_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_add_sub_res_sign_dffe21 <= man_add_sub_res_sign_dffe27_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_dffe31 <= man_add_sub_res_mag_dffe26_wo;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_leading_zeros_dffe31 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_leading_zeros_dffe31 <= man_leading_zeros_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_out_dffe5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_out_dffe5 <= man_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_dffe4 <= man_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe3 <= man_res_is_not_zero_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe31 <= man_res_is_not_zero_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_res_is_not_zero_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_res_is_not_zero_dffe4 <= man_res_is_not_zero_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN need_complement_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN need_complement_dffe2 <= need_complement_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe21 <= round_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe3 <= round_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_bit_dffe31 <= round_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN rounded_res_infinity_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN rounded_res_infinity_dffe4 <= rounded_res_infinity_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe31 <= sign_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_out_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_out_dffe5 <= sign_out_dffe5_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe3 <= sign_res_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_res_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_res_dffe4 <= sign_res_dffe4_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe1 <= sticky_bit_dffe1_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe2 <= sticky_bit_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe21 <= sticky_bit_dffe21_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe3 <= sticky_bit_dffe3_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sticky_bit_dffe31 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sticky_bit_dffe31 <= sticky_bit_dffe31_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe2 <= zero_man_sign_dffe2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_man_sign_dffe21 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_man_sign_dffe21 <= zero_man_sign_dffe21_wi;
END IF;
END IF;
END PROCESS;
add_sub1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => aligned_dataa_exp_w,
datab => aligned_datab_exp_w,
result => wire_add_sub1_result
);
add_sub2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => aligned_datab_exp_w,
datab => aligned_dataa_exp_w,
result => wire_add_sub2_result
);
add_sub3 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
dataa => sticky_bit_cnt_dataa_w,
datab => sticky_bit_cnt_datab_w,
result => wire_add_sub3_result
);
add_sub4 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_adjustment_add_sub_dataa_w,
datab => exp_adjustment_add_sub_datab_w,
result => wire_add_sub4_result
);
add_sub5 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => exp_adjustment2_add_sub_dataa_w,
datab => exp_adjustment2_add_sub_datab_w,
result => wire_add_sub5_result
);
add_sub6 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => exp_res_rounding_adder_dataa_w,
datab => exp_rounding_adjustment_w,
result => wire_add_sub6_result
);
loop121 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) <= wire_man_2comp_res_lower_w_lg_cout367w(0) AND wire_man_2comp_res_upper0_result(i);
END GENERATE loop121;
loop122 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_cout366w(i) <= wire_man_2comp_res_lower_cout AND wire_man_2comp_res_upper1_result(i);
END GENERATE loop122;
wire_man_2comp_res_lower_w_lg_cout367w(0) <= NOT wire_man_2comp_res_lower_cout;
loop123 : FOR i IN 0 TO 13 GENERATE
wire_man_2comp_res_lower_w_lg_w_lg_w_lg_cout367w368w369w(i) <= wire_man_2comp_res_lower_w_lg_w_lg_cout367w368w(i) OR wire_man_2comp_res_lower_w_lg_cout366w(i);
END GENERATE loop123;
man_2comp_res_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_2comp_res_lower_cout,
dataa => man_2comp_res_dataa_w(13 DOWNTO 0),
datab => man_2comp_res_datab_w(13 DOWNTO 0),
result => wire_man_2comp_res_lower_result
);
man_2comp_res_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper0_result
);
man_2comp_res_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_2comp_res_dataa_w(27 DOWNTO 14),
datab => man_2comp_res_datab_w(27 DOWNTO 14),
result => wire_man_2comp_res_upper1_result
);
loop124 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) <= wire_man_add_sub_lower_w_lg_cout354w(0) AND wire_man_add_sub_upper0_result(i);
END GENERATE loop124;
loop125 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_cout353w(i) <= wire_man_add_sub_lower_cout AND wire_man_add_sub_upper1_result(i);
END GENERATE loop125;
wire_man_add_sub_lower_w_lg_cout354w(0) <= NOT wire_man_add_sub_lower_cout;
loop126 : FOR i IN 0 TO 13 GENERATE
wire_man_add_sub_lower_w_lg_w_lg_w_lg_cout354w355w356w(i) <= wire_man_add_sub_lower_w_lg_w_lg_cout354w355w(i) OR wire_man_add_sub_lower_w_lg_cout353w(i);
END GENERATE loop126;
man_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => borrow_w,
clken => clk_en,
clock => clock,
cout => wire_man_add_sub_lower_cout,
dataa => man_add_sub_dataa_w(13 DOWNTO 0),
datab => man_add_sub_datab_w(13 DOWNTO 0),
result => wire_man_add_sub_lower_result
);
man_add_sub_upper0 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_gnd,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper0_result
);
man_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 14,
lpm_hint => "USE_WYS=ON"
)
PORT MAP (
aclr => aclr,
add_sub => add_sub_w2,
cin => wire_vcc,
clken => clk_en,
clock => clock,
dataa => man_add_sub_dataa_w(27 DOWNTO 14),
datab => man_add_sub_datab_w(27 DOWNTO 14),
result => wire_man_add_sub_upper1_result
);
loop127 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) AND adder_upper_w(i);
END GENERATE loop127;
loop128 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i) <= wire_man_res_rounding_add_sub_lower_cout AND wire_man_res_rounding_add_sub_upper1_result(i);
END GENERATE loop128;
wire_man_res_rounding_add_sub_lower_w_lg_cout580w(0) <= NOT wire_man_res_rounding_add_sub_lower_cout;
loop129 : FOR i IN 0 TO 12 GENERATE
wire_man_res_rounding_add_sub_lower_w_lg_w_lg_w_lg_cout580w581w582w(i) <= wire_man_res_rounding_add_sub_lower_w_lg_w_lg_cout580w581w(i) OR wire_man_res_rounding_add_sub_lower_w_lg_cout579w(i);
END GENERATE loop129;
man_res_rounding_add_sub_lower : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cout => wire_man_res_rounding_add_sub_lower_cout,
dataa => man_intermediate_res_w(12 DOWNTO 0),
datab => man_res_rounding_add_sub_datab_w(12 DOWNTO 0),
result => wire_man_res_rounding_add_sub_lower_result
);
man_res_rounding_add_sub_upper1 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 13
)
PORT MAP (
cin => wire_vcc,
dataa => man_intermediate_res_w(25 DOWNTO 13),
datab => man_res_rounding_add_sub_datab_w(25 DOWNTO 13),
result => wire_man_res_rounding_add_sub_upper1_result
);
trailing_zeros_limit_comparator : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 6
)
PORT MAP (
agb => wire_trailing_zeros_limit_comparator_agb,
dataa => sticky_bit_cnt_res_w,
datab => trailing_zeros_limit_w
);
END RTL; --fp_sub_altfp_add_sub_24k
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fp_sub IS
PORT
(
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sub;
ARCHITECTURE RTL OF fp_sub IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT fp_sub_altfp_add_sub_24k
PORT (
aclr : IN STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(31 DOWNTO 0);
fp_sub_altfp_add_sub_24k_component : fp_sub_altfp_add_sub_24k
PORT MAP (
aclr => aclr,
clk_en => clk_en,
clock => clock,
datab => datab,
dataa => dataa,
result => sub_wire0
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO"
-- Retrieval info: CONSTANT: DIRECTION STRING "SUB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "7"
-- Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fp_sub_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
library verilog;
use verilog.vl_types.all;
entity meio_somador3 is
port(
a : in vl_logic;
b : in vl_logic;
c : in vl_logic;
soma : out vl_logic;
cout : out vl_logic
);
end meio_somador3;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY genAND IS
GENERIC
(
size : integer
);
PORT
(
input0 : IN std_logic_vector(size-1 downto 0);
input1 : IN std_logic_vector(size-1 downto 0);
output : OUT std_logic_vector(size-1 downto 0)
);
END genAND;
ARCHITECTURE behavior OF genAND IS
BEGIN
output <= input0 AND input1;
END behavior; |
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity epdm_tb is
generic
(
TUNING_WORD_N : positive := 22
);
end entity;
architecture rtl of epdm_tb is
-- Main clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
signal clk : std_logic := '0';
signal reset : std_logic;
signal sig : std_logic;
signal mod_lvl : unsigned(2 downto 0);
signal mod_lvl_f : std_logic;
signal sig_lh : std_logic;
signal sig_ll : std_logic;
signal sig_rh : std_logic;
signal sig_rl : std_logic;
begin
DUT_inst: entity work.epdm(rtl)
port map
(
clk => clk,
reset => reset,
mod_lvl_in => mod_lvl,
mod_lvl_in_f => mod_lvl_f,
sig_in => sig,
sig_lh_out => sig_lh,
sig_ll_out => sig_ll,
sig_rh_out => sig_rh,
sig_rl_out => sig_rl
);
sig_gen_p: entity work.phase_accumulator(rtl)
generic map
(
ACCUM_BITS_N => 32,
TUNING_WORD_N => TUNING_WORD_N
)
port map
(
clk => clk,
reset => reset,
tuning_word_in => to_unsigned(2**TUNING_WORD_N / 2 - 1,
TUNING_WORD_N),
sig_out => sig
);
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
mod_lvl_gen: process(clk, reset)
variable mod_lvl_v : unsigned(2 downto 0);
variable cycle_count : unsigned(3 downto 0);
variable last_state : std_logic;
begin
if reset = '1' then
mod_lvl_v := to_unsigned(4, mod_lvl_v'length);
mod_lvl <= mod_lvl_v;
cycle_count := (others => '0');
last_state := sig;
mod_lvl_f <= '0';
elsif rising_edge(clk) then
if mod_lvl_f = '1' then
mod_lvl_f <= '0';
end if;
if not sig = last_state and sig = '1' then
cycle_count := cycle_count + 1;
-- Increase pulse density every 12 rising edges
if cycle_count = 12 then
cycle_count := (others => '0');
if mod_lvl = 0 then
mod_lvl_v := to_unsigned(4, mod_lvl_v'length);
else
mod_lvl_v := mod_lvl_v - 1;
end if;
mod_lvl <= mod_lvl_v;
mod_lvl_f <= '1';
end if;
end if;
last_state := sig;
end if;
end process;
-- Make sure same side high- and low-side are never on at the same time
assert not (sig_lh = sig_ll and sig_lh = '1')
report "Left h = l" severity warning;
assert not (sig_rh = sig_rl and sig_rh = '1')
report "Right h = l" severity warning;
end;
|
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_nios2_performance_monitors is
end usb_system_cpu_nios2_performance_monitors;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rom.vhd when simulating
-- the core, rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END rom;
ARCHITECTURE rom_a OF rom IS
-- synthesis translate_off
COMPONENT wrapped_rom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rom USE ENTITY XilinxCoreLib.blk_mem_gen_v6_3(behavioral)
GENERIC MAP (
c_addra_width => 15,
c_addrb_width => 15,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file_name => "rom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 32768,
c_read_depth_b => 32768,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 32768,
c_write_depth_b => 32768,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END rom_a;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DPBSCFIFO40x64WC IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END DPBSCFIFO40x64WC;
ARCHITECTURE DPBSCFIFO40x64WC_arch OF DPBSCFIFO40x64WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO40x64WC_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 40,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 40,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 1,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 62,
C_PROG_FULL_THRESH_NEGATE_VAL => 61,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 64,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 6,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 64,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 6,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
data_count => data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DPBSCFIFO40x64WC_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DPBSCFIFO40x64WC IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END DPBSCFIFO40x64WC;
ARCHITECTURE DPBSCFIFO40x64WC_arch OF DPBSCFIFO40x64WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO40x64WC_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 40,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 40,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 1,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 62,
C_PROG_FULL_THRESH_NEGATE_VAL => 61,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 64,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 6,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 64,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 6,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
data_count => data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DPBSCFIFO40x64WC_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DPBSCFIFO40x64WC IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END DPBSCFIFO40x64WC;
ARCHITECTURE DPBSCFIFO40x64WC_arch OF DPBSCFIFO40x64WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO40x64WC_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 40,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 40,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 1,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 62,
C_PROG_FULL_THRESH_NEGATE_VAL => 61,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 64,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 6,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 64,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 6,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
data_count => data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DPBSCFIFO40x64WC_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:12.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v12_0;
USE fifo_generator_v12_0.fifo_generator_v12_0;
ENTITY DPBSCFIFO40x64WC IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END DPBSCFIFO40x64WC;
ARCHITECTURE DPBSCFIFO40x64WC_arch OF DPBSCFIFO40x64WC IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF DPBSCFIFO40x64WC_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v12_0 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(39 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(39 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v12_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v12_0
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 6,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 40,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 40,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 1,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 0,
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "512x72",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 62,
C_PROG_FULL_THRESH_NEGATE_VAL => 61,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 6,
C_RD_DEPTH => 64,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 6,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 6,
C_WR_DEPTH => 64,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 6,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => '0',
srst => srst,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
data_count => data_count,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END DPBSCFIFO40x64WC_arch;
|
-- Testebench gerado via script.
-- Data: Qua,20/07/2011-13:51:40
-- Autor: rogerio
-- Comentario: Teste da entidade or3.
library ieee;
use ieee.std_logic_1164.all;
entity or3_tb is
end or3_tb;
architecture logica of or3_tb is
-- Declaração do componente.
component or3
port (a,b,c: in std_logic; y: out std_logic);
end component;
-- Especifica qual a entidade está vinculada com o componente.
for or3_0: or3 use entity work.or3;
signal s_t_a, s_t_b, s_t_c, s_t_y: std_logic;
begin
-- Instanciação do Componente.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
or3_0: or3 port map (a=>s_t_a,b=>s_t_b,c=>s_t_c,y=>s_t_y);
-- Processo que faz o trabalho.
process
-- Um registro é criado com as entradas e saídas da entidade.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- entradas.
vi_a,vi_b,vi_c: std_logic;
-- saídas.
vo_y: std_logic;
end record;
-- Os padrões de entrada são aplicados (injetados) às entradas.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
(
('0', '0', '0', '0'),
('0', '0', '1', '1'),
('0', '1', '0', '1'),
('0', '1', '1', '1'),
('1', '0', '0', '1'),
('1', '0', '1', '1'),
('1', '1', '0', '1'),
('1', '1', '1', '1')
);
begin
-- Checagem de padrões.
for i in patterns'range loop
-- Injeta as entradas.
s_t_a <= patterns(i).vi_a;
s_t_b <= patterns(i).vi_b;
s_t_c <= patterns(i).vi_c;
-- Aguarda os resultados.
wait for 1 ns;
-- Checa o resultado com a saída esperada no padrão.
assert s_t_y = patterns(i).vo_y report "Valor de s_t_y não confere com o resultado esperado." severity error;
end loop;
assert false report "Fim do teste." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end logica;
|
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all; -- UNSIGNED function
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity RegBank is generic (
async_reset : boolean;
fpu_ena : boolean
);
port (
i_clk : in std_logic; -- CPU clock
i_nrst : in std_logic; -- Reset. Active LOW.
i_radr1 : in std_logic_vector(5 downto 0); -- Port 1 read address
o_rdata1 : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Port 1 read value
o_rhazard1 : out std_logic;
i_radr2 : in std_logic_vector(5 downto 0); -- Port 2 read address
o_rdata2 : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Port 2 read value
o_rhazard2 : out std_logic;
i_waddr : in std_logic_vector(5 downto 0); -- Writing value
i_wena : in std_logic; -- Writing is enabled
i_whazard : in std_logic;
i_wtag : in std_logic_vector(3 downto 0);
i_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Writing value
o_wtag : out std_logic_vector(3 downto 0);
i_dport_addr : in std_logic_vector(5 downto 0); -- Debug port address
i_dport_ena : in std_logic; -- Debug port is enabled
i_dport_write : in std_logic; -- Debug port write is enabled
i_dport_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Debug port write value
o_dport_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0);-- Debug port read value
o_ra : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Return address for branch predictor
o_sp : out std_logic_vector(RISCV_ARCH-1 downto 0) -- Stack Pointer for the borders control
);
end;
architecture arch_RegBank of RegBank is
constant REG_MSB : integer := 4 + conv_integer(fpu_ena);
constant REGS_TOTAL : integer := 2**(REG_MSB + 1);
type reg_score_type is record
val : std_logic_vector(RISCV_ARCH-1 downto 0);
tag : std_logic_vector(3 downto 0);
hazard : std_logic;
end record;
type MemoryType is array (0 to REGS_TOTAL-1) of reg_score_type;
type RegistersType is record
mem : MemoryType;
end record;
signal r, rin : RegistersType;
begin
comb : process(i_nrst, i_radr1, i_radr2, i_waddr, i_wena, i_whazard, i_wtag, i_wdata,
i_dport_ena, i_dport_write, i_dport_addr, i_dport_wdata, r)
variable v : RegistersType;
variable int_waddr : integer;
variable int_daddr : integer;
begin
for i in 0 to REGS_TOTAL-1 loop
v.mem(i).hazard := r.mem(i).hazard;
v.mem(i).val := r.mem(i).val;
v.mem(i).tag := r.mem(i).tag;
end loop;
int_waddr := conv_integer(i_waddr(REG_MSB downto 0));
int_daddr := conv_integer(i_dport_addr(REG_MSB downto 0));
--! Debug port has higher priority. Collision must be controlled by SW
if (i_dport_ena and i_dport_write) = '1' then
if or_reduce(i_dport_addr) = '1' then
v.mem(int_daddr).val := i_dport_wdata;
v.mem(int_daddr).hazard := '0';
end if;
elsif i_wena = '1' and or_reduce(i_waddr(REG_MSB downto 0)) = '1' then
if i_wtag = r.mem(int_waddr).tag then
v.mem(int_waddr).hazard := i_whazard;
v.mem(int_waddr).val := i_wdata;
v.mem(int_waddr).tag := r.mem(int_waddr).tag + 1;
end if;
end if;
if not async_reset and i_nrst = '0' then
v.mem(Reg_Zero).hazard := '0';
v.mem(Reg_Zero).val := (others => '0');
v.mem(Reg_Zero).tag := (others => '0');
for i in 1 to REGS_TOTAL-1 loop
v.mem(i).hazard := '0';
v.mem(i).val := X"00000000FEEDFACE";
v.mem(i).tag := (others => '0');
end loop;
end if;
rin <= v;
end process;
o_rdata1 <= r.mem(conv_integer(i_radr1(REG_MSB downto 0))).val;
o_rhazard1 <= r.mem(conv_integer(i_radr1(REG_MSB downto 0))).hazard;
o_rdata2 <= r.mem(conv_integer(i_radr2(REG_MSB downto 0))).val;
o_rhazard2 <= r.mem(conv_integer(i_radr2(REG_MSB downto 0))).hazard;
o_wtag <= r.mem(conv_integer(i_waddr(REG_MSB downto 0))).tag;
o_dport_rdata <= r.mem(conv_integer(i_dport_addr(REG_MSB downto 0))).val;
o_ra <= r.mem(Reg_ra).val;
o_sp <= r.mem(Reg_sp).val;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r.mem(Reg_Zero).hazard <= '0';
r.mem(Reg_Zero).val <= (others => '0');
r.mem(Reg_Zero).tag <= (others => '0');
for i in 1 to REGS_TOTAL-1 loop
r.mem(i).hazard <= '0';
r.mem(i).val <= X"00000000FEEDFACE";
r.mem(i).tag <= (others => '0');
end loop;
elsif rising_edge(i_clk) then
for i in 0 to REGS_TOTAL-1 loop
r.mem(i).hazard <= rin.mem(i).hazard;
r.mem(i).val <= rin.mem(i).val;
r.mem(i).tag <= rin.mem(i).tag;
end loop;
end if;
end process;
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity fulladder is
port(a, b, c_in : in std_logic;
sum, c_out : out std_logic);
end entity fulladder;
architecture structeral of fulladder is
begin
sum <= a xor b xor c_in;
c_out <= (a and b) or (a and c_in) or (b and c_in);
end architecture;
|
-------------------------------------------------------------------------------
-- leon3_zc702_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity leon3_zc702_stub is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_arready : out STD_LOGIC;
S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arvalid : in STD_LOGIC;
S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_awready : out STD_LOGIC;
S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awvalid : in STD_LOGIC;
S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_bready : in STD_LOGIC;
S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_bvalid : out STD_LOGIC;
S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_rlast : out STD_LOGIC;
S_AXI_GP0_rready : in STD_LOGIC;
S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_rvalid : out STD_LOGIC;
S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_wlast : in STD_LOGIC;
S_AXI_GP0_wready : out STD_LOGIC;
S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_wvalid : in STD_LOGIC
);
end leon3_zc702_stub;
architecture STRUCTURE of leon3_zc702_stub is
signal clk : std_logic := '0';
signal clk0 : std_logic := '0';
signal clk1 : std_logic := '0';
signal rst : std_logic := '0';
type memstatetype is (idle, read1, read2, read3, write1, write2, write3);
type blane is array (0 to 2**18-1) of natural;
type memtype is array (0 to 3) of blane;
constant abits : integer := 20;
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**abits)-1)) of BYTE;
type regtype is record
memstate : memstatetype;
addr : integer;
arlen : integer;
mem : memtype;
rcnt : integer;
end record;
signal S_AXI_GP0_rvalid_i : std_logic;
signal r, rin : regtype;
begin
clk0 <= not clk0 after 6.0 ns; -- 83.33 MHz
clk1 <= not clk1 after 2.5 ns; -- 200 MHz
rst <= '1' after 1 us;
S_AXI_GP0_rvalid <= S_AXI_GP0_rvalid_i;
FCLK_CLK0 <= clk0;
clk <= clk0;
FCLK_CLK1 <= clk1;
-- FCLK_CLK2 <= clk2;
-- FCLK_CLK3 <= clk3;
FCLK_RESET0_N <= rst;
mem0 : process(clk)
variable MEMA : MEM;
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is "ram.srec";
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable memstate : memstatetype;
variable addr : integer;
-- variable len : integer;
-- variable mem : memtype;
variable rcnt : integer;
begin
if FIRST then
-- if clear = 1 then MEMA := (others => X"00"); end if;
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
recaddr(31 downto abits) := (others => '0');
ai := conv_integer(recaddr);
for i in 0 to 15 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
elsif rising_edge(clk) then
case memstate is
when idle =>
S_AXI_GP0_arready <= '0'; S_AXI_GP0_rvalid_i <= '0'; S_AXI_GP0_rlast <= '0';
S_AXI_GP0_awready <= '0'; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '0';
if S_AXI_GP0_arvalid = '1' then
memstate := read1; S_AXI_GP0_arready <= '1';
elsif S_AXI_GP0_awvalid = '1' then
memstate := write1; S_AXI_GP0_awready <= '1';
end if;
when read1 =>
addr:= conv_integer(S_AXI_GP0_araddr(19 downto 0));
len := conv_integer(S_AXI_GP0_arlen);
S_AXI_GP0_arready <= '0'; memstate := read2; rcnt := 23;
when read2 =>
if rcnt /= 0 then rcnt := rcnt - 1;
else
S_AXI_GP0_rvalid_i <= '1';
if len = 0 then S_AXI_GP0_rlast <= '1'; end if;
if (S_AXI_GP0_rready and S_AXI_GP0_rvalid_i) = '1' then
if len = 0 then
S_AXI_GP0_rlast <= '0'; S_AXI_GP0_rvalid_i <= '0';
memstate := idle;
else
addr := addr + 4; len := len - 1;
if len = 0 then S_AXI_GP0_rlast <= '1'; end if;
end if;
end if;
for i in 0 to 3 loop
S_AXI_GP0_rdata(i*8+7 downto i*8) <= MEMA(addr+3-i);
end loop;
end if;
when write1 =>
addr:= conv_integer(S_AXI_GP0_awaddr(19 downto 0));
len := conv_integer(S_AXI_GP0_awlen);
S_AXI_GP0_awready <= '0'; memstate := write2; rcnt := 0;
when write2 =>
if rcnt /= 0 then rcnt := rcnt - 1;
else
memstate := write3;
S_AXI_GP0_wready <= '1';
end if;
when write3 =>
if S_AXI_GP0_wvalid = '1' then
for i in 0 to 3 loop
if S_AXI_GP0_wstrb(i) = '1' then
MEMA(addr+3-i) := S_AXI_GP0_wdata(i*8+7 downto i*8);
end if;
end loop;
if (len = 0) or (S_AXI_GP0_wlast = '1') then
memstate := idle; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '1';
else
addr := addr + 1; len := len - 1;
end if;
end if;
when others =>
end case;
end if;
end process;
S_AXI_GP0_bid <= (others => '0');
S_AXI_GP0_bresp <= (others => '0');
S_AXI_GP0_rresp <= (others => '0');
S_AXI_GP0_rid <= (others => '0');
DDR_addr <= (others => '0');
DDR_ba <= (others => '0');
DDR_cas_n <= '0';
DDR_ck_n <= '0';
DDR_ck_p <= '0';
DDR_cke <= '0';
DDR_cs_n <= '0';
DDR_dm <= (others => '0');
DDR_dq <= (others => '0');
DDR_dqs_n <= (others => '0');
DDR_dqs_p <= (others => '0');
DDR_odt <= '0';
DDR_ras_n <= '0';
DDR_reset_n <= '0';
DDR_we_n <= '0';
FIXED_IO_ddr_vrn <= '0';
FIXED_IO_ddr_vrp <= '0';
FIXED_IO_mio <= (others => '0');
FIXED_IO_ps_clk <= '0';
FIXED_IO_ps_porb <= '0';
FIXED_IO_ps_srstb <= '0';
end architecture STRUCTURE;
|
-------------------------------------------------------------------------------
-- leon3_zc702_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity leon3_zc702_stub is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_arready : out STD_LOGIC;
S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arvalid : in STD_LOGIC;
S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_awready : out STD_LOGIC;
S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awvalid : in STD_LOGIC;
S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_bready : in STD_LOGIC;
S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_bvalid : out STD_LOGIC;
S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_rlast : out STD_LOGIC;
S_AXI_GP0_rready : in STD_LOGIC;
S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_rvalid : out STD_LOGIC;
S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_wlast : in STD_LOGIC;
S_AXI_GP0_wready : out STD_LOGIC;
S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_wvalid : in STD_LOGIC
);
end leon3_zc702_stub;
architecture STRUCTURE of leon3_zc702_stub is
signal clk : std_logic := '0';
signal clk0 : std_logic := '0';
signal clk1 : std_logic := '0';
signal rst : std_logic := '0';
type memstatetype is (idle, read1, read2, read3, write1, write2, write3);
type blane is array (0 to 2**18-1) of natural;
type memtype is array (0 to 3) of blane;
constant abits : integer := 20;
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**abits)-1)) of BYTE;
type regtype is record
memstate : memstatetype;
addr : integer;
arlen : integer;
mem : memtype;
rcnt : integer;
end record;
signal S_AXI_GP0_rvalid_i : std_logic;
signal r, rin : regtype;
begin
clk0 <= not clk0 after 6.0 ns; -- 83.33 MHz
clk1 <= not clk1 after 2.5 ns; -- 200 MHz
rst <= '1' after 1 us;
S_AXI_GP0_rvalid <= S_AXI_GP0_rvalid_i;
FCLK_CLK0 <= clk0;
clk <= clk0;
FCLK_CLK1 <= clk1;
-- FCLK_CLK2 <= clk2;
-- FCLK_CLK3 <= clk3;
FCLK_RESET0_N <= rst;
mem0 : process(clk)
variable MEMA : MEM;
variable L1 : line;
variable FIRST : boolean := true;
variable ADR : std_logic_vector(19 downto 0);
variable BUF : std_logic_vector(31 downto 0);
variable CH : character;
variable ai : integer := 0;
variable len : integer := 0;
file TCF : text open read_mode is "ram.srec";
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable memstate : memstatetype;
variable addr : integer;
-- variable len : integer;
-- variable mem : memtype;
variable rcnt : integer;
begin
if FIRST then
-- if clear = 1 then MEMA := (others => X"00"); end if;
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
when "0010" =>
hread(L1, recaddr(23 downto 0));
when "0011" =>
hread(L1, recaddr);
when others => next;
end case;
hread(L1, recdata);
recaddr(31 downto abits) := (others => '0');
ai := conv_integer(recaddr);
for i in 0 to 15 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
if ai = 0 then
ai := 1;
end if;
end if;
end if;
end if;
end loop;
FIRST := false;
elsif rising_edge(clk) then
case memstate is
when idle =>
S_AXI_GP0_arready <= '0'; S_AXI_GP0_rvalid_i <= '0'; S_AXI_GP0_rlast <= '0';
S_AXI_GP0_awready <= '0'; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '0';
if S_AXI_GP0_arvalid = '1' then
memstate := read1; S_AXI_GP0_arready <= '1';
elsif S_AXI_GP0_awvalid = '1' then
memstate := write1; S_AXI_GP0_awready <= '1';
end if;
when read1 =>
addr:= conv_integer(S_AXI_GP0_araddr(19 downto 0));
len := conv_integer(S_AXI_GP0_arlen);
S_AXI_GP0_arready <= '0'; memstate := read2; rcnt := 23;
when read2 =>
if rcnt /= 0 then rcnt := rcnt - 1;
else
S_AXI_GP0_rvalid_i <= '1';
if len = 0 then S_AXI_GP0_rlast <= '1'; end if;
if (S_AXI_GP0_rready and S_AXI_GP0_rvalid_i) = '1' then
if len = 0 then
S_AXI_GP0_rlast <= '0'; S_AXI_GP0_rvalid_i <= '0';
memstate := idle;
else
addr := addr + 4; len := len - 1;
if len = 0 then S_AXI_GP0_rlast <= '1'; end if;
end if;
end if;
for i in 0 to 3 loop
S_AXI_GP0_rdata(i*8+7 downto i*8) <= MEMA(addr+3-i);
end loop;
end if;
when write1 =>
addr:= conv_integer(S_AXI_GP0_awaddr(19 downto 0));
len := conv_integer(S_AXI_GP0_awlen);
S_AXI_GP0_awready <= '0'; memstate := write2; rcnt := 0;
when write2 =>
if rcnt /= 0 then rcnt := rcnt - 1;
else
memstate := write3;
S_AXI_GP0_wready <= '1';
end if;
when write3 =>
if S_AXI_GP0_wvalid = '1' then
for i in 0 to 3 loop
if S_AXI_GP0_wstrb(i) = '1' then
MEMA(addr+3-i) := S_AXI_GP0_wdata(i*8+7 downto i*8);
end if;
end loop;
if (len = 0) or (S_AXI_GP0_wlast = '1') then
memstate := idle; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '1';
else
addr := addr + 1; len := len - 1;
end if;
end if;
when others =>
end case;
end if;
end process;
S_AXI_GP0_bid <= (others => '0');
S_AXI_GP0_bresp <= (others => '0');
S_AXI_GP0_rresp <= (others => '0');
S_AXI_GP0_rid <= (others => '0');
DDR_addr <= (others => '0');
DDR_ba <= (others => '0');
DDR_cas_n <= '0';
DDR_ck_n <= '0';
DDR_ck_p <= '0';
DDR_cke <= '0';
DDR_cs_n <= '0';
DDR_dm <= (others => '0');
DDR_dq <= (others => '0');
DDR_dqs_n <= (others => '0');
DDR_dqs_p <= (others => '0');
DDR_odt <= '0';
DDR_ras_n <= '0';
DDR_reset_n <= '0';
DDR_we_n <= '0';
FIXED_IO_ddr_vrn <= '0';
FIXED_IO_ddr_vrp <= '0';
FIXED_IO_mio <= (others => '0');
FIXED_IO_ps_clk <= '0';
FIXED_IO_ps_porb <= '0';
FIXED_IO_ps_srstb <= '0';
end architecture STRUCTURE;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Thu Nov 6 15:55:45 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\io.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.1 2004/04/06 11:04:57 wig Exp $
-- $Date: 2004/04/06 11:04:57 $
-- $Log: inst_a_e-e.vhd,v $
-- Revision 1.1 2004/04/06 11:04:57 wig
-- Adding result/io
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.17 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_a_e
--
entity inst_a_e is
-- Generics:
-- No Generated Generics for Entity inst_a_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_a_e
p_mix_sig_in_01_gi : in std_ulogic;
p_mix_sig_in_03_gi : in std_ulogic_vector(7 downto 0);
p_mix_sig_io_05_gc : inout std_ulogic_vector(5 downto 0);
p_mix_sig_io_06_gc : inout std_ulogic_vector(6 downto 0);
p_mix_sig_out_02_go : out std_ulogic;
p_mix_sig_out_04_go : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity inst_a_e
);
end inst_a_e;
--
-- End of Generated Entity inst_a_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company: Laboratoire Leprince-Ringuet
-- Engineer:
--
-- Create Date: 11:58:40 10/14/2011
-- Design Name:
-- Module Name: eth_tx_stream - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity eth_tx_stream is Port(
CLK125 : in STD_LOGIC;
RESET : in STD_LOGIC;
TXD : out STD_LOGIC_VECTOR(7 downto 0);
TXCTRL : out STD_LOGIC;--phy data valid
--TXC : out STD_LOGIC;--gigabit phy tx clock
ETH_TX_STREAM : in STD_LOGIC_VECTOR(9 downto 0));
end eth_tx_stream;
architecture Behavioral of eth_tx_stream is
type multiple is ARRAY(7 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal data_dly : multiple;
signal frm_dly : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal txdat_reg : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal txen_reg : STD_LOGIC;
signal txdat : STD_LOGIC_VECTOR(7 downto 0) := x"00";
signal txcontrol : STD_LOGIC := '0';
signal outcnt : unsigned(2 downto 0) := "000";
signal invert_clk : std_logic;
begin
TXD <= txdat;
TXCTRL <= txcontrol;
process(CLK125,RESET)
begin
if RESET = '0' then
for i in 0 to 7 loop
data_dly(i) <= x"00";
end loop;
frm_dly <= x"00";
txdat_reg <= x"00";
txen_reg <= '0';
txdat <= x"00";
txcontrol <= '0';
elsif CLK125'event and CLK125 = '1' then
if ETH_TX_STREAM(9) = '1' then
--delay the data by eight bytes to insert the preamble
data_dly(0) <= ETH_TX_STREAM(7 downto 0);
data_dly(7 downto 1) <= data_dly(6 downto 0);
frm_dly <= frm_dly(6 downto 0) & ETH_TX_STREAM(8);
--register the data byte to send
if frm_dly(7) = '1' then
txdat_reg <= data_dly(7);
elsif frm_dly(6) = '1' then
txdat_reg <= x"D5";
else
txdat_reg <= x"55";
end if;
txen_reg <= ETH_TX_STREAM(8) or frm_dly(7);
--handle the 100Mbps/1000Mbps modes
outcnt <= "000";
txdat <= txdat_reg;
txcontrol <= txen_reg;
else
if outcnt < "111" then
outcnt <= outcnt + "001";
else
outcnt <= outcnt;
end if;
if outcnt = "100" then
txdat <= x"0" & txdat(7 downto 4);
--else
--txdat <= txdat;
end if;
txcontrol <= txcontrol;
end if;
end if;
end process;
end Behavioral; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY prbs_tb IS
END prbs_tb;
ARCHITECTURE behavior OF prbs_tb IS
-- Component Declaration
COMPONENT PRBS
PORT ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
output : out STD_LOGIC);
END COMPONENT;
SIGNAL clk : std_logic;
SIGNAL rst : std_logic;
SIGNAL enable : std_logic;
SIGNAL output : STD_LOGIC;
CONSTANT clk_period: TIME := 10 ns;
BEGIN
-- Component Instantiation
uut: PRBS PORT MAP(
clk => clk,
rst => rst,
enable => enable,
output => output
);
-- Generar los estimulos
stim_process : PROCESS
BEGIN
rst <= '1';
enable <= '0';
wait for 100 ns;
rst <= '0';
wait until rising_edge(clk);
FOR i IN 1 TO 25 LOOP
enable <= '1';
wait for clk_period;
enable <= '0';
wait for 3*clk_period;
END LOOP;
END PROCESS stim_process;
-- Generar el reloj
clk_process : PROCESS
BEGIN
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
END PROCESS clk_process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:15:39 04/13/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab2/ProgramCounter/ProgramCounter/IM_tb.vhd
-- Project Name: ProgramCounter
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Instruction_Memory_TL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY IM_tb IS
END IM_tb;
ARCHITECTURE behavior OF IM_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Instruction_Memory_TL
PORT(
CLK : IN std_logic;
RST : IN std_logic;
BRANCH : IN std_logic;
BRNCH_ADR : IN std_logic_vector(11 downto 0);
RA : OUT std_logic_vector(3 downto 0);
RB : OUT std_logic_vector(3 downto 0);
OP : OUT std_logic_vector(3 downto 0);
IMM : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal JMP : std_logic := '0';
signal OFFSET : std_logic_vector(11 downto 0) := (others => '0');
signal RTN : std_logic := '0';
--Outputs
signal RA : std_logic_vector(3 downto 0);
signal RB : std_logic_vector(3 downto 0);
signal OP : std_logic_vector(3 downto 0);
signal IMM : std_logic_vector(7 downto 0);
signal INS_OFFSET : std_logic_vector(11 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Instruction_Memory_TL PORT MAP (
CLK => CLK,
RST => RST,
JMP => JMP,
OFFSET => OFFSET,
RTN => RTN,
RA => RA,
RB => RB,
OP => OP,
IMM => IMM,
INS_OFFSET => INS_OFFSET
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
RST <= '1';
wait for 100 ns;
RST <= '0';
wait for CLK_period*20;
BRNCH_ADR
-- OFFSET <= "111111111100";
-- JMP <= '1';
--
-- wait for CLK_period;
--
-- JMP <= '0';
--
-- wait for CLK_period*3;
--
-- RTN <= '1';
--
-- wait for CLK_period;
-- insert stimulus here
wait;
end process;
END;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity network_driver is
end entity network_driver;
architecture test of network_driver is
constant target_host_id : natural := 10;
constant my_host_id : natural := 5;
type pkt_types is (control_pkt, other_pkt);
type pkt_header is record
dest, src : natural;
pkt_type : pkt_types;
seq : natural;
end record;
begin
-- code from book
network_driver : process is
constant seq_modulo : natural := 2**5;
subtype seq_number is natural range 0 to seq_modulo-1;
variable next_seq_number : seq_number := 0;
-- . . .
-- not in book
variable new_header : pkt_header;
-- end not in book
impure function generate_seq_number return seq_number is
variable number : seq_number;
begin
number := next_seq_number;
next_seq_number := (next_seq_number + 1) mod seq_modulo;
return number;
end function generate_seq_number;
begin -- network_driver
-- not in book
wait for 10 ns;
-- end not in book
-- . . .
new_header := pkt_header'( dest => target_host_id,
src => my_host_id,
pkt_type => control_pkt,
seq => generate_seq_number );
-- . . .
end process network_driver;
-- end code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity network_driver is
end entity network_driver;
architecture test of network_driver is
constant target_host_id : natural := 10;
constant my_host_id : natural := 5;
type pkt_types is (control_pkt, other_pkt);
type pkt_header is record
dest, src : natural;
pkt_type : pkt_types;
seq : natural;
end record;
begin
-- code from book
network_driver : process is
constant seq_modulo : natural := 2**5;
subtype seq_number is natural range 0 to seq_modulo-1;
variable next_seq_number : seq_number := 0;
-- . . .
-- not in book
variable new_header : pkt_header;
-- end not in book
impure function generate_seq_number return seq_number is
variable number : seq_number;
begin
number := next_seq_number;
next_seq_number := (next_seq_number + 1) mod seq_modulo;
return number;
end function generate_seq_number;
begin -- network_driver
-- not in book
wait for 10 ns;
-- end not in book
-- . . .
new_header := pkt_header'( dest => target_host_id,
src => my_host_id,
pkt_type => control_pkt,
seq => generate_seq_number );
-- . . .
end process network_driver;
-- end code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity network_driver is
end entity network_driver;
architecture test of network_driver is
constant target_host_id : natural := 10;
constant my_host_id : natural := 5;
type pkt_types is (control_pkt, other_pkt);
type pkt_header is record
dest, src : natural;
pkt_type : pkt_types;
seq : natural;
end record;
begin
-- code from book
network_driver : process is
constant seq_modulo : natural := 2**5;
subtype seq_number is natural range 0 to seq_modulo-1;
variable next_seq_number : seq_number := 0;
-- . . .
-- not in book
variable new_header : pkt_header;
-- end not in book
impure function generate_seq_number return seq_number is
variable number : seq_number;
begin
number := next_seq_number;
next_seq_number := (next_seq_number + 1) mod seq_modulo;
return number;
end function generate_seq_number;
begin -- network_driver
-- not in book
wait for 10 ns;
-- end not in book
-- . . .
new_header := pkt_header'( dest => target_host_id,
src => my_host_id,
pkt_type => control_pkt,
seq => generate_seq_number );
-- . . .
end process network_driver;
-- end code from book
end architecture test;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:13 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_stub.vhdl
-- Design : system_rgb565_to_rgb888_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb565_to_rgb888_0_0 is
Port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_rgb565_to_rgb888_0_0;
architecture stub of system_rgb565_to_rgb888_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rgb_565[15:0],rgb_888[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb565_to_rgb888,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:13 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_stub.vhdl
-- Design : system_rgb565_to_rgb888_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb565_to_rgb888_0_0 is
Port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_rgb565_to_rgb888_0_0;
architecture stub of system_rgb565_to_rgb888_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rgb_565[15:0],rgb_888[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb565_to_rgb888,Vivado 2016.4";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:13 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_stub.vhdl
-- Design : system_rgb565_to_rgb888_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb565_to_rgb888_0_0 is
Port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_rgb565_to_rgb888_0_0;
architecture stub of system_rgb565_to_rgb888_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rgb_565[15:0],rgb_888[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb565_to_rgb888,Vivado 2016.4";
begin
end;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33328)
`protect data_block
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3/dAJ8HmwfHxMfCrDbOXVnz2bFR+RiPEepctrzfPvyx9AB1cvtwyxNFn4QT4nrxjD6SbGZGeA9G/
qLz9odYu5S4s4Ep8NYD6+RkLg+8LRjvYlmOA7npYpRn6kuDzQVs1HMSKgAQIcwtpjGZ1q7c756HV
CFhKrHmaLXVIIBjbC15QgSrtklBiaMiMWP6aG8aH8kN0Rtc/js5ygY7xtUQIsdWPakBfCWnY6WLE
vXgC004RfnRWNDNEUz55p+oc9LQEvFlRB/9nl+siRX1zRZYQy24g6SC+JDJQARXefByfRR81V27C
DtavMfUwzFEsGqmmkr/sLrdXQJpuKL/ywZFQf0TyHN24xiTpf/JDEkLZjZ9Ub98PA4DN5Fmdsr3Q
vIIWNZkXfZaGLuC+VbgOvuaVwCXUbQ09FNsp5By+K3SFXn3hz/CP1TCZVQSsJbfCEsJdjOXGY4+J
wC37bCRTiF0+uB0hMZLr54XkYlxcmtQEC9FRoVtayYkAzZPsTGUgjlbx2zZ4fXUrxPMgcPJIa34Q
CPNUFLtf6F+a+awSKqbTIAXB5R18hIR+9ob3ow6Gyxjl3qojm8agUjbtdVm3bIRTZU0jO+4yu/wL
LFeTbGI3cGxUIq2dEqlv6RA8JzE3rdz9UBeT6zgufe6BbYSNzeHuD/lqYIyvL+q5Z5KxzpXJCfER
FfqUlNgUWIswRx/uP2Dsi3/PF6kgvmjEVjaw3lt22WH9WgLNYUwDTpk4x+W8CQNOLzNtYEJkDoKo
MtfroaK7+AZHni53hhBQv5PFIwMjXfNnZmGC2ERbAbCbMIlDu+Vxxw==
`protect end_protected
|
entity foo is end;
architecture bar of foo is
type BIT is ('0', '1');
type COMP is record
a : BIT;
b : BIT;
end record;
procedure prok is begin
-- name
X := '0';
-- positional array aggregate
(X,Y) := "00";
-- named array aggregate
(1 => X, 0 => Y) := "00";
-- mixed array aggregate
(X, 1 => Y) := "00";
-- positional record aggregate
(X,Y) := Z;
-- named record aggregate
(a => X, b => Y) := Z;
-- mixed record aggregate
(X, b => Y) := Z;
end;
begin end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNUWBUDS4L is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000011";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNUWBUDS4L is
Begin
-- Constant
output <= "000000000000000000000011";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNUWBUDS4L is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000011";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNUWBUDS4L is
Begin
-- Constant
output <= "000000000000000000000011";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNUWBUDS4L is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000011";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNUWBUDS4L is
Begin
-- Constant
output <= "000000000000000000000011";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNUWBUDS4L is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000011";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNUWBUDS4L is
Begin
-- Constant
output <= "000000000000000000000011";
end architecture; |
library verilog;
use verilog.vl_types.all;
entity NbitCounter_vlg_sample_tst is
port(
clear : in vl_logic;
clk : in vl_logic;
enable : in vl_logic;
sampler_tx : out vl_logic
);
end NbitCounter_vlg_sample_tst;
|
altaccumulate3_inst : altaccumulate3 PORT MAP (
aclr => aclr_sig,
clken => clken_sig,
clock => clock_sig,
data => data_sig,
result => result_sig
);
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rom is
port(
clk: in std_logic;
address: in unsigned(10 downto 0); -- 2^11 addresses
data: out unsigned(14 downto 0) --words are 15 bits wide
);
end entity;
architecture a_rom of rom is
type mem is array (0 to 64) of unsigned(14 downto 0);
constant rom_values : mem := (
0 => "101010000100001",-- lda #33
1 => "100111110100000",-- mov r5,A ;r5 is the max_number
2 => "101010000000110",-- lda #6
3 => "100111100100000",-- mov r1,A ;r1 is the square root of max_number
4 => "101010000000001",-- lda #1
5 => "100111110000000",-- mov r4,A ;r4 is 1
6 => "101010000000000",-- lda #0
7 => "100111100000000",-- mov r0,A ;r0 is 0
8 => "101010000000010",-- lda #2 ;generate on RAM the list of numbers from 2 to max_number
9 => "100111111000000",--list: mov H,A
10 => "101100000000000",-- sta
11 => "000110000000000",-- add r4
12 => "010110100000000",-- cmp r5
13 => "110011111111100",-- blt list
14 => "101010000000001",-- lda #1 ;initializes ram_iterator
15 => "100111101100000",-- mov r3,A
16 => "100111011100000",--loop: mov A,H
17 => "010100100000000",-- cmp r1
18 => "011100000010001",-- beq finish ;if all possible multiple numbers are gone, branch to finish
19 => "100101111100000",-- mov A,r3
20 => "000110000000000",-- add r4 ;else, increment ram_iterator
21 => "100111101100000",-- mov r3,A
22 => "100111111000000",-- mov H,A
23 => "101000000000000",-- lda
24 => "010100000000000",-- cmp r0 ;if value fetched from memory is 0, branch to the next iteration
25 => "011111111110111",-- beq loop
26 => "100111011100000",--eliminate:mov A,H ;else, eliminate multiple numbers of ram_iterator
27 => "000101100000000",-- add r3 ;starts to eliminate from the next multiple number
28 => "100111111000000",-- mov H,A
29 => "101010000000000",-- lda #0 ;replaces the multiple number with 0 inside the memory
30 => "101100000000000",-- sta
31 => "100111011100000",-- mov A,H
32 => "010110100000000",-- cmp r5
33 => "110011111111001",-- blt eliminate ;loops until it reaches the max_number
34 => "011011111101110",-- bra loop
35 => "101010000000010",--finish: lda #2 ;generate on RAM the list of numbers from 2 to max number
36 => "100111111000000",--display: mov H,A
37 => "101000000000000",-- lda
38 => "010100000000000",-- cmp r0
39 => "011100000000010",-- beq not_prime
40 => "100111101000000",-- mov r2,A
41 => "100111011100000",--not_prime:mov A,H
42 => "000110000000000",-- add r4
43 => "010110100000000",-- cmp r5
44 => "110011111111000",-- blt display
others => (others=>'0')
);
begin
process(clk)
begin
if(rising_edge(clk)) then
data <= rom_values(to_integer(address));
end if;
end process;
end architecture;
-----------PROGRAMS-------------
-------------LAB5-------------
-- 0 => "101010000000101", --lda #5
-- 1 => "100111101100000", --mov r3,A
-- 2 => "101010000001000", --lda #8
-- 3 => "100111110000000", --mov r4,A
-- 4 => "000101100000000", --add r3
-- 5 => "100111110100000", --mov r5,A
-- 6 => "101010000000001", --lda #1
-- 7 => "100111100000000", --mov r0,A
-- 8 => "100110111100000", --mov A,r5
-- 9 => "001000000000000", --sub r0
-- 10 => "100111110100000", --mov r5,A
-- 11 => "011000000000010", --bra 0x0D
-- 12 => "000000000000000", --nop
-- 13 => "100110101100000", --mov r3,r5
-- 14 => "011011111110101", --bra 0x03
------------------LAB 6-------------------------
-- 0 => "101010000000101", --lda #5
-- 1 => "100111101100000", --mov r3,A
-- 2 => "010101100000000", --cmp r3
-- 3 => "011100000000100", --beq 0x07
-- 4 => "100111110100000", --mov r5,A
-- 5 => "101010000000001", --lda #1
-- 6 => "101010000000010", --lda #2
-- 7 => "101010000000100", --lda #4
-- 8 => "010101100000000", --cmp r3
-- 9 => "110000000000110", --bmi 0x0F
------------------LAB 7-------------------------
-- --stores 4 on address 30 and stores 5 on address 31
-- 0 => "101010000011110", -- lda #30
-- 1 => "100111111000000", -- mov r6,A
-- 2 => "101010000000100", -- lda #4
-- 3 => "101100000000000", -- sta
-- 4 => "101010000011111", -- lda #31
-- 5 => "100111111000000", -- mov r6,A
-- 6 => "101010000000101", -- lda #5
-- 7 => "101100000000000", -- sta
--
-- --load values in 30 and 31 and moves it to r0 and r1 respectively
-- 8 => "101010000011110", -- lda #30
-- 9 => "100111111000000", -- mov r6,A
-- 10 => "101000000000000", -- lda
-- 11 => "100111100000000", -- mov r0,A
-- 12 => "101010000011111", -- lda #31
-- 13 => "100111111000000", -- mov r6,A
-- 14 => "101000000000000", -- lda
-- 15 => "100111100100000", -- mov r1,A
--
-- --stores 10 at address 30
-- 16 => "101010000011110", -- lda #30
-- 17 => "100111111000000", -- mov r6,A
-- 18 => "101010000001010", -- lda #10
-- 19 => "101100000000000", -- sta
--
-- --stores 1 at address 1
-- 20 => "101010000000001", -- lda #1
-- 21 => "100111111000000", -- mov r6,A
-- 22 => "101100000000000", -- sta
--
-- --loads address 1 and store it on r2
-- 23 => "101000000000000", -- lda
-- 24 => "100111101000000", -- mov r2,A
--
-- --loads address 30 and store it on r3
-- 25 => "101010000011110", -- lda #30
-- 26 => "100111111000000", -- mov r6,A
-- 27 => "101000000000000", -- lda
-- 28 => "100111101100000", -- mov r3,A
-- |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias3,
S => net7
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net7,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias3,
S => net9
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net10
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net11
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net11,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net12,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net12
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
|
-- $Id: sys_conf2_sim.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n2 (for test bench)
--
-- Dependencies: -
-- Tool versions: xst 11.4; ghdl 0.26
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec
-- to 60 cycles (1 usec). This affects the pulse generators (usec) and
-- mainly the autobauder. A break will be detected after 128 msec periods,
-- this in simulation after 128 usec or 6400 cycles. This is compatible with
-- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
constant sys_conf_clkudiv_usecdiv : integer := 20; -- default usec
constant sys_conf_clksdiv_usecdiv : integer := 12; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
end package sys_conf;
|
-- $Id: sys_conf2_sim.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop2_n2 (for test bench)
--
-- Dependencies: -
-- Tool versions: xst 11.4; ghdl 0.26
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- in simulation a usec is shortened to 12 cycles (0.2 usec) and a msec
-- to 60 cycles (1 usec). This affects the pulse generators (usec) and
-- mainly the autobauder. A break will be detected after 128 msec periods,
-- this in simulation after 128 usec or 6400 cycles. This is compatible with
-- bitrates of 115200 baud or higher (115200 <-> 8.68 usec <-> 521 cycles)
constant sys_conf_clkudiv_usecdiv : integer := 20; -- default usec
constant sys_conf_clksdiv_usecdiv : integer := 12; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 5; -- shortened !
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_uart_cdinit : integer := 1-1; -- 1 cycle/bit in sim
end package sys_conf;
|
library ieee;
use ieee.std_logic_1164.all;
entity add32 is
port ( a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
cin : in std_logic;
sum : out std_logic_vector(31 downto 0);
cout : out std_logic);
end entity add32;
architecture Behavioral of add32 is
component fadd
port ( a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end component fadd;
signal c : std_logic_vector(0 to 32);
begin
c(0) <= cin;
stages : for I in 0 to 31 generate
adder : fadd port map(a(I), b(I), c(I) , sum(I), c(I+1));
end generate stages;
cout <= c(32);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vComponents.all;
package vga_mouse_pkg is
--- TOP LEVEL COMPONENTS ---
component mousecomp
port (
clk : in std_logic;
resolution : in std_logic;
rst : in std_logic;
switch : in std_logic;
left : out std_logic;
middle : out std_logic;
new_event : out std_logic;
right : out std_logic;
busy : out std_logic;
xpos : out std_logic_vector(9 downto 0);
ypos : out std_logic_vector(9 downto 0);
zpos : out std_logic_vector(3 downto 0);
ps2_clk : inout std_logic;
ps2_data : inout std_logic
);
end component;
component vgacomp is
port (
clk : in std_logic;
clk_25 : in std_logic;
clk_40 : in std_logic;
rst : in std_logic;
resolution : in std_logic;
click : in std_logic;
bgsw : in std_logic_vector(2 downto 0);
xpos : in std_logic_vector(9 downto 0);
ypos : in std_logic_vector(9 downto 0);
hsync : out std_logic;
vsync : out std_logic;
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(2 downto 1)
);
end component;
component cdiv
port (
clk : in std_logic;
tcvl : in integer;
cout : out std_logic
);
end component;
--- DIGITAL CLK MANAGERS ---
component dcm_25mhz
port (
clkin_in : in std_logic;
clkdv_out : out std_logic;
-- clkin_ibufg_out : out std_logic;
clk0_out : out std_logic := '0'
);
end component;
component dcm_40mhz
port (
clkin_in : in std_logic;
clkdv_out : out std_logic;
-- clkin_ibufg_out : out std_logic;
clk0_out : out std_logic := '0'
);
end component;
--- PS/2 MOUSE ---
component mouse_controller
port (
clk : in std_logic;
rst : in std_logic;
read : in std_logic;
err : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
xpos : out std_logic_vector(9 downto 0);
ypos : out std_logic_vector(9 downto 0);
zpos : out std_logic_vector(3 downto 0);
left : out std_logic;
middle : out std_logic;
right : out std_logic;
new_event : out std_logic;
tx_data : out std_logic_vector(7 downto 0);
write : out std_logic;
value : in std_logic_vector(9 downto 0);
setx : in std_logic;
sety : in std_logic;
setmax_x : in std_logic;
setmax_y : in std_logic
);
end component;
component resolution_mouse_informer
port (
clk : in std_logic;
rst : in std_logic;
resolution : in std_logic;
switch : in std_logic;
value : out std_logic_vector(9 downto 0);
setx : out std_logic;
sety : out std_logic;
setmax_x : out std_logic;
setmax_y : out std_logic
);
end component;
component ps2interface
port (
ps2_clk : inout std_logic;
ps2_data : inout std_logic;
clk : in std_logic;
rst : in std_logic;
tx_data : in std_logic_vector(7 downto 0);
write : in std_logic;
rx_data : out std_logic_vector(7 downto 0);
read : out std_logic;
busy : out std_logic;
err : out std_logic
);
end component;
--- MOUSE CURSOR ---
component mouse_displayer is
port (
clk : in std_logic;
pixel_clk: in std_logic;
xpos : in std_logic_vector(9 downto 0);
ypos : in std_logic_vector(9 downto 0);
hcount : in std_logic_vector(10 downto 0);
vcount : in std_logic_vector(10 downto 0);
blank : in std_logic;
click : in std_logic;
red_in : in std_logic_vector(2 downto 0);
green_in : in std_logic_vector(2 downto 0);
blue_in : in std_logic_vector(2 downto 1);
red_out : out std_logic_vector(2 downto 0);
green_out: out std_logic_vector(2 downto 0);
blue_out : out std_logic_vector(2 downto 1)
);
end component;
--- VGA ---
component vga_controller_640_60
port (
rst : in std_logic;
pixel_clk : in std_logic;
HS : out std_logic;
VS : out std_logic;
blank : out std_logic;
hcount : out std_logic_vector(10 downto 0);
vcount : out std_logic_vector(10 downto 0)
);
end component;
component vga_controller_800_60
port (
rst : in std_logic;
HS : out std_logic;
VS : out std_logic;
blank : out std_logic;
pixel_clk : in std_logic;
vcount : out std_logic_vector (10 downto 0);
hcount : out std_logic_vector (10 downto 0)
);
end component;
component vga_res_sel
port (
resolution : in std_logic;
HS_640_60 : in std_logic;
VS_640_60 : in std_logic;
HS_800_60 : in std_logic;
VS_800_60 : in std_logic;
red_25 : in std_logic_vector(2 downto 0);
green_25 : in std_logic_vector(2 downto 0);
blue_25 : in std_logic_vector(2 downto 1);
red_40 : in std_logic_vector(2 downto 0);
green_40 : in std_logic_vector(2 downto 0);
blue_40 : in std_logic_vector(2 downto 1);
hs : out std_logic; -- Horizontal sync
vs : out std_logic; -- Vertical sync
red : out std_logic_vector(2 downto 0);
green : out std_logic_vector(2 downto 0);
blue : out std_logic_vector(2 downto 1)
);
end component;
end vga_mouse_pkg;
|
-------------------------------------------------------------------------------
-- Title : data_crc.vhd
-------------------------------------------------------------------------------
-- File : data_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity data_crc_tb is
end data_crc_tb;
architecture tb of data_crc_tb is
signal clock : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0);
signal crc : std_logic_vector(15 downto 0);
signal valid : std_logic := '0';
signal sync : std_logic := '0';
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant test_array : t_byte_array := (
X"80", X"06", X"00", X"01", X"00", X"00", X"40", X"00" );
begin
i_mut: entity work.usb1_data_crc
port map (
clock => clock,
sync => sync,
valid => valid,
data_in => data_in,
crc => crc );
clock <= not clock after 10 ns;
p_test: process
begin
wait until clock='1';
wait until clock='1';
sync <= '1';
wait until clock='1';
sync <= '0';
for i in test_array'range loop
data_in <= test_array(i);
valid <= '1';
wait until clock = '1';
end loop;
valid <= '0';
wait;
end process;
end tb;
|
-------------------------------------------------------------------------------
-- Title : data_crc.vhd
-------------------------------------------------------------------------------
-- File : data_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity data_crc_tb is
end data_crc_tb;
architecture tb of data_crc_tb is
signal clock : std_logic := '0';
signal data_in : std_logic_vector(7 downto 0);
signal crc : std_logic_vector(15 downto 0);
signal valid : std_logic := '0';
signal sync : std_logic := '0';
type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant test_array : t_byte_array := (
X"80", X"06", X"00", X"01", X"00", X"00", X"40", X"00" );
begin
i_mut: entity work.usb1_data_crc
port map (
clock => clock,
sync => sync,
valid => valid,
data_in => data_in,
crc => crc );
clock <= not clock after 10 ns;
p_test: process
begin
wait until clock='1';
wait until clock='1';
sync <= '1';
wait until clock='1';
sync <= '0';
for i in test_array'range loop
data_in <= test_array(i);
valid <= '1';
wait until clock = '1';
end loop;
valid <= '0';
wait;
end process;
end tb;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: altpll1.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altpll1 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END altpll1;
ARCHITECTURE SYN OF altpll1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 11,
clk0_duty_cycle => 50,
clk0_multiply_by => 6,
clk0_phase_shift => "0",
clk1_divide_by => 9,
clk1_duty_cycle => 50,
clk1_multiply_by => 4,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone II",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "11"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "14.727273"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "324.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "6"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "14.74560000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_1164 package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (PAR 1164),
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package body std_logic_1164 is
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
type stdlogic_1d is array (STD_ULOGIC) of STD_ULOGIC;
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
constant resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', 'X', '0', '0', '0', '0', 'X'), -- | 0 |
('U', 'X', 'X', '1', '1', '1', '1', '1', 'X'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X'), -- | Z |
('U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X'), -- | W |
('U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X'), -- | L |
('U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X'), -- | H |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := 'Z'; -- weakest state default
begin
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
if (s'length = 1) then return s(s'low);
else
for i in s'range loop
result := resolution_table(result, s(i));
end loop;
end if;
return result;
end function resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
constant and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U'), -- | U |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | X |
('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 1 |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | Z |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- | W |
('0', '0', '0', '0', '0', '0', '0', '0', '0'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | H |
('U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X') -- | - |
);
-- truth table for "or" function
constant or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U'), -- | U |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | Z |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | H |
('U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X') -- | - |
);
-- truth table for "xor" function
constant xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X'), -- | H |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X') -- | - |
);
-- truth table for "not" function
constant not_table : stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
('U', 'X', '1', '0', 'X', 'X', '1', '0', 'X');
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (and_table(l, r));
end function "and";
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (not_table (and_table(l, r)));
end function "nand";
function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (or_table(l, r));
end function "or";
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (not_table (or_table(l, r)));
end function "nor";
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return (xor_table(l, r));
end function "xor";
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01 is
begin
return not_table(xor_table(l, r));
end function "xnor";
function "not" (l : STD_ULOGIC) return UX01 is
begin
return (not_table(l));
end function "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""and"": "
& "arguments of overloaded 'and' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := and_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nand"": "
& "arguments of overloaded 'nand' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(and_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""or"": "
& "arguments of overloaded 'or' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := or_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""nor"": "
& "arguments of overloaded 'nor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(or_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xor"": "
& "arguments of overloaded 'xor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := xor_table (lv(i), rv(i));
end loop;
end if;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
if (l'length /= r'length) then
assert false
report "STD_LOGIC_1164.""xnor"": "
& "arguments of overloaded 'xnor' operator are not of the same length"
severity failure;
else
for i in result'range loop
result(i) := not_table(xor_table (lv(i), rv(i)));
end loop;
end if;
return result;
end function "xnor";
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => 'X');
begin
for i in result'range loop
result(i) := not_table(lv(i));
end loop;
return result;
end function "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := and_table (lv(i), r);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := and_table (l, rv(i));
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(and_table (lv(i), r));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(and_table (l, rv(i)));
end loop;
return result;
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := or_table (lv(i), r);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := or_table (l, rv(i));
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(or_table (lv(i), r));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(or_table (l, rv(i)));
end loop;
return result;
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := xor_table (lv(i), r);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := xor_table (l, rv(i));
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
begin
for i in result'range loop
result(i) := not_table(xor_table (lv(i), r));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias rv : STD_ULOGIC_VECTOR (1 to r'length) is r;
variable result : STD_ULOGIC_VECTOR (1 to r'length);
begin
for i in result'range loop
result(i) := not_table(xor_table (l, rv(i)));
end loop;
return result;
end function "xnor";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := and_table (l(i), result);
end loop;
return result;
end function "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '1';
begin
for i in l'reverse_range loop
result := and_table (l(i), result);
end loop;
return not_table(result);
end function "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := or_table (l(i), result);
end loop;
return result;
end function "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := or_table (l(i), result);
end loop;
return not_table(result);
end function "nor";
-------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := xor_table (l(i), result);
end loop;
return result;
end function "xor";
-------------------------------------------------------------------
-- xnor
-------------------------------------------------------------------
function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC is
variable result : STD_ULOGIC := '0';
begin
for i in l'reverse_range loop
result := xor_table (l(i), result);
end loop;
return not_table(result);
end function "xnor";
-------------------------------------------------------------------
-- shift operators
-------------------------------------------------------------------
-------------------------------------------------------------------
-- sll
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(1 to l'length - r) := lv(r + 1 to l'length);
else
result := l srl -r;
end if;
return result;
end function "sll";
-------------------------------------------------------------------
-- srl
-------------------------------------------------------------------
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
begin
if r >= 0 then
result(r + 1 to l'length) := lv(1 to l'length - r);
else
result := l sll -r;
end if;
return result;
end function "srl";
-------------------------------------------------------------------
-- rol
-------------------------------------------------------------------
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length);
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(1 to l'length - rm) := lv(rm + 1 to l'length);
result(l'length - rm + 1 to l'length) := lv(1 to rm);
else
result := l ror -r;
end if;
return result;
end function "rol";
-------------------------------------------------------------------
-- ror
-------------------------------------------------------------------
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER)
return STD_ULOGIC_VECTOR
is
alias lv : STD_ULOGIC_VECTOR (1 to l'length) is l;
variable result : STD_ULOGIC_VECTOR (1 to l'length) := (others => '0');
constant rm : INTEGER := r mod l'length;
begin
if r >= 0 then
result(rm + 1 to l'length) := lv(1 to l'length - rm);
result(1 to rm) := lv(l'length - rm + 1 to l'length);
else
result := l rol -r;
end if;
return result;
end function "ror";
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
type logic_x01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01;
type logic_x01z_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of X01Z;
type logic_ux01_table is array (STD_ULOGIC'low to STD_ULOGIC'high) of UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
constant cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT is
begin
case s is
when '0' | 'L' => return ('0');
when '1' | 'H' => return ('1');
when others => return xmap;
end case;
end function To_bit;
--------------------------------------------------------------------
function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0')
return BIT_VECTOR
is
alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : BIT_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
case sv(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := xmap;
end case;
end loop;
return result;
end function To_bitvector;
--------------------------------------------------------------------
function To_StdULogic (b : BIT) return STD_ULOGIC is
begin
case b is
when '0' => return '0';
when '1' => return '1';
end case;
end function To_StdULogic;
--------------------------------------------------------------------
function To_StdLogicVector (b : BIT_VECTOR)
return STD_LOGIC_VECTOR
is
alias bv : BIT_VECTOR (b'length-1 downto 0) is b;
variable result : STD_LOGIC_VECTOR (b'length-1 downto 0);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_StdLogicVector;
--------------------------------------------------------------------
function To_StdLogicVector (s : STD_ULOGIC_VECTOR)
return STD_LOGIC_VECTOR
is
alias sv : STD_ULOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : STD_LOGIC_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
result(i) := sv(i);
end loop;
return result;
end function To_StdLogicVector;
--------------------------------------------------------------------
function To_StdULogicVector (b : BIT_VECTOR)
return STD_ULOGIC_VECTOR
is
alias bv : BIT_VECTOR (b'length-1 downto 0) is b;
variable result : STD_ULOGIC_VECTOR (b'length-1 downto 0);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_StdULogicVector;
--------------------------------------------------------------------
function To_StdULogicVector (s : STD_LOGIC_VECTOR)
return STD_ULOGIC_VECTOR
is
alias sv : STD_LOGIC_VECTOR (s'length-1 downto 0) is s;
variable result : STD_ULOGIC_VECTOR (s'length-1 downto 0);
begin
for i in result'range loop
result(i) := sv(i);
end loop;
return result;
end function To_StdULogicVector;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_01
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR
is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
variable BAD_ELEMENT : BOOLEAN := false;
alias XS : STD_ULOGIC_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' | 'L' => RESULT(I) := '0';
when '1' | 'H' => RESULT(I) := '1';
when others => BAD_ELEMENT := true;
end case;
end loop;
if BAD_ELEMENT then
for I in RESULT'range loop
RESULT(I) := xmap; -- standard fixup
end loop;
end if;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0') return STD_ULOGIC is
begin
case s is
when '0' | 'L' => RETURN '0';
when '1' | 'H' => RETURN '1';
when others => return xmap;
end case;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR
is
variable RESULT : STD_ULOGIC_VECTOR(s'length-1 downto 0);
alias XS : BIT_VECTOR(s'length-1 downto 0) is s;
begin
for I in RESULT'range loop
case XS(I) is
when '0' => RESULT(I) := '0';
when '1' => RESULT(I) := '1';
end case;
end loop;
return RESULT;
end function TO_01;
-------------------------------------------------------------------
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0') return STD_ULOGIC is
begin
case s is
when '0' => RETURN '0';
when '1' => RETURN '1';
end case;
end function TO_01;
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01 (sv(i));
end loop;
return result;
end function To_X01;
--------------------------------------------------------------------
function To_X01 (s : STD_ULOGIC) return X01 is
begin
return (cvt_to_x01(s));
end function To_X01;
--------------------------------------------------------------------
function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_X01;
--------------------------------------------------------------------
function To_X01 (b : BIT) return X01 is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_X01;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_x01z (sv(i));
end loop;
return result;
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (s : STD_ULOGIC) return X01Z is
begin
return (cvt_to_x01z(s));
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_X01Z;
--------------------------------------------------------------------
function To_X01Z (b : BIT) return X01Z is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_X01Z;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
alias sv : STD_ULOGIC_VECTOR (1 to s'length) is s;
variable result : STD_ULOGIC_VECTOR (1 to s'length);
begin
for i in result'range loop
result(i) := cvt_to_ux01 (sv(i));
end loop;
return result;
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (s : STD_ULOGIC) return UX01 is
begin
return (cvt_to_ux01(s));
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR is
alias bv : BIT_VECTOR (1 to b'length) is b;
variable result : STD_ULOGIC_VECTOR (1 to b'length);
begin
for i in result'range loop
case bv(i) is
when '0' => result(i) := '0';
when '1' => result(i) := '1';
end case;
end loop;
return result;
end function To_UX01;
--------------------------------------------------------------------
function To_UX01 (b : BIT) return UX01 is
begin
case b is
when '0' => return('0');
when '1' => return('1');
end case;
end function To_UX01;
function "??" (l : STD_ULOGIC) return BOOLEAN is
begin
return l = '1' or l = 'H';
end function "??";
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '1') and
(To_X01(s'last_value) = '0'));
end function rising_edge;
function falling_edge (signal s : STD_ULOGIC) return BOOLEAN is
begin
return (s'event and (To_X01(s) = '0') and
(To_X01(s'last_value) = '1'));
end function falling_edge;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
for i in s'range loop
case s(i) is
when 'U' | 'X' | 'Z' | 'W' | '-' => return true;
when others => null;
end case;
end loop;
return false;
end function Is_X;
--------------------------------------------------------------------
function Is_X (s : STD_ULOGIC) return BOOLEAN is
begin
case s is
when 'U' | 'X' | 'Z' | 'W' | '-' => return true;
when others => null;
end case;
return false;
end function Is_X;
-------------------------------------------------------------------
-- string conversion and write operations
-------------------------------------------------------------------
function TO_OSTRING (value : STD_ULOGIC_VECTOR) return STRING is
constant result_length : NATURAL := (value'length+2)/3;
variable pad : STD_ULOGIC_VECTOR(1 to result_length*3 - value'length);
variable padded_value : STD_ULOGIC_VECTOR(1 to result_length*3);
variable result : STRING(1 to result_length);
variable tri : STD_ULOGIC_VECTOR(1 to 3);
begin
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
padded_value := pad & value;
for i in 1 to result_length loop
tri := To_X01Z(padded_value(3*i-2 to 3*i));
case tri is
when o"0" => result(i) := '0';
when o"1" => result(i) := '1';
when o"2" => result(i) := '2';
when o"3" => result(i) := '3';
when o"4" => result(i) := '4';
when o"5" => result(i) := '5';
when o"6" => result(i) := '6';
when o"7" => result(i) := '7';
when "ZZZ" => result(i) := 'Z';
when others => result(i) := 'X';
end case;
end loop;
return result;
end function TO_OSTRING;
function TO_HSTRING (value : STD_ULOGIC_VECTOR) return STRING is
constant result_length : NATURAL := (value'length+3)/4;
variable pad : STD_ULOGIC_VECTOR(1 to result_length*4 - value'length);
variable padded_value : STD_ULOGIC_VECTOR(1 to result_length*4);
variable result : STRING(1 to result_length);
variable quad : STD_ULOGIC_VECTOR(1 to 4);
begin
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
padded_value := pad & value;
for i in 1 to result_length loop
quad := To_X01Z(padded_value(4*i-3 to 4*i));
case quad is
when x"0" => result(i) := '0';
when x"1" => result(i) := '1';
when x"2" => result(i) := '2';
when x"3" => result(i) := '3';
when x"4" => result(i) := '4';
when x"5" => result(i) := '5';
when x"6" => result(i) := '6';
when x"7" => result(i) := '7';
when x"8" => result(i) := '8';
when x"9" => result(i) := '9';
when x"A" => result(i) := 'A';
when x"B" => result(i) := 'B';
when x"C" => result(i) := 'C';
when x"D" => result(i) := 'D';
when x"E" => result(i) := 'E';
when x"F" => result(i) := 'F';
when "ZZZZ" => result(i) := 'Z';
when others => result(i) := 'X';
end case;
end loop;
return result;
end function TO_HSTRING;
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable c : CHARACTER;
variable left : positive;
begin
while L /= null and L.all'length /= 0 loop
left := L.all'left;
c := L.all(left);
if (c = ' ' or c = NBSP or c = HT) then
read (L, c);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
skip_whitespace (L);
read (L, c, readOk);
if not readOk then
GOOD := false;
else
if char_to_MVL9plus(c) = error then
GOOD := false;
else
VALUE := char_to_MVL9(c);
GOOD := true;
end if;
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
read (L, c, readOk);
i := 0;
GOOD := true;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
GOOD := false;
return;
elsif c = '_' then
if i = 0 then
GOOD := false; -- Begins with an "_"
return;
elsif lastu then
GOOD := false; -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then
GOOD := false; -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
GOOD := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
begin
VALUE := 'U'; -- initialize to a "U"
skip_whitespace (L);
read (L, c, readOk);
if not readOk then
report "STD_LOGIC_1164.READ(STD_ULOGIC) "
& "End of string encountered"
severity error;
return;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
else
VALUE := char_to_MVL9(c);
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (L, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write(L, MVL9_to_char(VALUE), JUSTIFIED, FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
variable s : STRING(1 to VALUE'length);
alias m : STD_ULOGIC_VECTOR(1 to VALUE'length) is VALUE;
begin
for i in 1 to VALUE'length loop
s(i) := MVL9_to_char(m(i));
end loop;
write(L, s, JUSTIFIED, FIELD);
end procedure WRITE;
procedure Char2TriBits (C : in CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case C is
when '0' => RESULT := o"0"; GOOD := true;
when '1' => RESULT := o"1"; GOOD := true;
when '2' => RESULT := o"2"; GOOD := true;
when '3' => RESULT := o"3"; GOOD := true;
when '4' => RESULT := o"4"; GOOD := true;
when '5' => RESULT := o"5"; GOOD := true;
when '6' => RESULT := o"6"; GOOD := true;
when '7' => RESULT := o"7"; GOOD := true;
when 'Z' => RESULT := "ZZZ"; GOOD := true;
when 'X' => RESULT := "XXX"; GOOD := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & C &
"', expected an Octal character (0-7)."
severity error;
GOOD := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
read (L, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
elsif c = '_' then
if i = 0 then
GOOD := false; -- Begins with an "_"
return;
elsif lastu then
GOOD := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
GOOD := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
else
GOOD := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
read (L, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case C is
when '0' => RESULT := x"0"; GOOD := true;
when '1' => RESULT := x"1"; GOOD := true;
when '2' => RESULT := x"2"; GOOD := true;
when '3' => RESULT := x"3"; GOOD := true;
when '4' => RESULT := x"4"; GOOD := true;
when '5' => RESULT := x"5"; GOOD := true;
when '6' => RESULT := x"6"; GOOD := true;
when '7' => RESULT := x"7"; GOOD := true;
when '8' => RESULT := x"8"; GOOD := true;
when '9' => RESULT := x"9"; GOOD := true;
when 'A' | 'a' => RESULT := x"A"; GOOD := true;
when 'B' | 'b' => RESULT := x"B"; GOOD := true;
when 'C' | 'c' => RESULT := x"C"; GOOD := true;
when 'D' | 'd' => RESULT := x"D"; GOOD := true;
when 'E' | 'e' => RESULT := x"E"; GOOD := true;
when 'F' | 'f' => RESULT := x"F"; GOOD := true;
when 'Z' => RESULT := "ZZZZ"; GOOD := true;
when 'X' => RESULT := "XXXX"; GOOD := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Error: Read a '" & C &
"', expected a Hex character (0-F)."
severity error;
GOOD := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then
read (L, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
elsif c = '_' then
if i = 0 then
GOOD := false; -- Begins with an "_"
return;
elsif lastu then
GOOD := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
GOOD := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
GOOD := false; -- vector was truncated.
else
GOOD := true;
VALUE := sv (pad to sv'high);
end if;
else
GOOD := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (L, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or (sv (0 to pad-1)) = '1' then
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, TO_OSTRING(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, TO_HSTRING (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-----------------------------------------------------------------------------
-- BEGIN NVC ADDITIONS
-----------------------------------------------------------------------------
-- The standard specifies the matching relational operators on
-- STD_ULOGIC are predefined but they are implemented here in VHDL for
-- convenience. These functions are not exported from the package and
-- cannot be called directly by user code. Instead the compiler emits
-- calls to these functions when lowering the predefined operators.
type match_table_t is array (std_ulogic, std_ulogic) of std_ulogic;
constant match_eq_table : match_table_t := (
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1' ),
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ),
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ),
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ),
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ),
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ),
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ),
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ),
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ) );
function nvc_rel_match_eq (l, r : std_ulogic) return std_ulogic is
begin
return match_eq_table(l, r);
end function;
constant match_lt_table : match_table_t := (
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'X' ),
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ),
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ),
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ),
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ),
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ),
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ),
( 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) );
function nvc_rel_match_lt (l, r : std_ulogic) return std_ulogic is
begin
assert l /= '-' and r /= '-'
report "STD_LOGIC_1164: '-' operand for matching ordering operator"
severity ERROR;
return match_lt_table(l, r);
end function;
function nvc_rel_match_leq (l, r : std_ulogic) return std_ulogic is
begin
assert l /= '-' and r /= '-'
report "STD_LOGIC_1164: '-' operand for matching ordering operator"
severity ERROR;
return match_lt_table(l, r) or match_eq_table(l, r);
end function;
end package body std_logic_1164;
|
------------------------------------------------------------------------------
-- "numeric_std_additions" package contains the additions to the standard
-- "numeric_std" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.numeric_std_additions.all;
-- (this package is independant of "std_logic_1164_additions")
-- Last Modified: $Date: 2007/09/27 14:46:32 $
-- RCS ID: $Id: numeric_std_additions.vhdl,v 1.9 2007/09/27 14:46:32 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package numeric_std_additions is
-- Make these a subtype of "signed" and "unsigned" for compatability
-- type UNRESOLVED_UNSIGNED is array (NATURAL range <>) of STD_ULOGIC;
-- type UNRESOLVED_SIGNED is array (NATURAL range <>) of STD_ULOGIC;
subtype UNRESOLVED_UNSIGNED is UNSIGNED;
subtype UNRESOLVED_SIGNED is SIGNED;
-- alias U_UNSIGNED is UNRESOLVED_UNSIGNED;
-- alias U_SIGNED is UNRESOLVED_SIGNED;
subtype U_UNSIGNED is UNSIGNED;
subtype U_SIGNED is SIGNED;
-- Id: A.3R
function "+"(L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- Result subtype: UNSIGNED(L'RANGE)
-- Result: Similar to A.3 where R is a one bit UNSIGNED
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.4R
function "+"(L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- Result subtype: SIGNED(L'RANGE)
-- Result: Similar to A.4 where R is bit 0 of a non-negative
-- SIGNED
-- Id: A.4L
function "+"(L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.4 where L is bit 0 of a non-negative
-- SIGNED
-- Id: A.9R
function "-"(L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- Result subtype: UNSIGNED(L'RANGE)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.10R
function "-"(L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- Result subtype: SIGNED(L'RANGE)
-- Result: Similar to A.10 where R is bit 0 of a non-negative
-- SIGNED
-- Id: A.10L
function "-"(L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.10 where R is bit 0 of a non-negative
-- SIGNED
-- Id: M.2B
-- %%% function "?=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?/=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic;
function \?=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?/=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?/=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?>\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?>=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?<\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?<=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?/=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?>\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?>=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?<\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?<=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: terms compared per STD_LOGIC_1164 intent,
-- returns an 'X' if a metavalue is passed
-- Id: M.3B
-- %%% function "?=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?/=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?>" (L, R : SIGNED) return std_ulogic;
-- %%% function "?>=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?<" (L, R : SIGNED) return std_ulogic;
-- %%% function "?<=" (L, R : SIGNED) return std_ulogic;
function \?=\ (L, R : SIGNED) return STD_ULOGIC;
function \?/=\ (L, R : SIGNED) return STD_ULOGIC;
function \?>\ (L, R : SIGNED) return STD_ULOGIC;
function \?>=\ (L, R : SIGNED) return STD_ULOGIC;
function \?<\ (L, R : SIGNED) return STD_ULOGIC;
function \?<=\ (L, R : SIGNED) return STD_ULOGIC;
function \?=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?/=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?>\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?>=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?<\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?<=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?/=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?>\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?>=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?<\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?<=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
-- Result subtype: std_ulogic
-- Result: terms compared per STD_LOGIC_1164 intent,
-- returns an 'X' if a metavalue is passed
-- size_res versions of these functions (Bugzilla 165)
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE_RES'length-1 downto 0)
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED (SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED (SIZE_RES'length-1 downto 0)
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- Overloaded functions from "std_logic_1164"
function To_X01 (s : UNSIGNED) return UNSIGNED;
function To_X01 (s : SIGNED) return SIGNED;
function To_X01Z (s : UNSIGNED) return UNSIGNED;
function To_X01Z (s : SIGNED) return SIGNED;
function To_UX01 (s : UNSIGNED) return UNSIGNED;
function To_UX01 (s : SIGNED) return SIGNED;
function Is_X (s : UNSIGNED) return BOOLEAN;
function Is_X (s : SIGNED) return BOOLEAN;
function "sla" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
function "sla" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
function "sra" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
function "sra" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Returns the maximum (or minimum) of the two numbers provided.
-- All types (both inputs and the output) must be the same.
-- These override the implicit funcitons, using the local ">" operator
function maximum (
l, r : UNSIGNED) -- inputs
return UNSIGNED;
function maximum (
l, r : SIGNED) -- inputs
return SIGNED;
function minimum (
l, r : UNSIGNED) -- inputs
return UNSIGNED;
function minimum (
l, r : SIGNED) -- inputs
return SIGNED;
function maximum (
l : UNSIGNED; r : NATURAL) -- inputs
return UNSIGNED;
function maximum (
l : SIGNED; r : INTEGER) -- inputs
return SIGNED;
function minimum (
l : UNSIGNED; r : NATURAL) -- inputs
return UNSIGNED;
function minimum (
l : SIGNED; r : INTEGER) -- inputs
return SIGNED;
function maximum (
l : NATURAL; r : UNSIGNED) -- inputs
return UNSIGNED;
function maximum (
l : INTEGER; r : SIGNED) -- inputs
return SIGNED;
function minimum (
l : NATURAL; r : UNSIGNED) -- inputs
return UNSIGNED;
function minimum (
l : INTEGER; r : SIGNED) -- inputs
return SIGNED;
-- Finds the first "Y" in the input string. Returns an integer index
-- into that string. If "Y" does not exist in the string, then the
-- "find_rightmost" returns arg'low -1, and "find_leftmost" returns -1
function find_rightmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_rightmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_leftmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_leftmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function TO_UNRESOLVED_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with
-- the specified SIZE.
alias TO_U_UNSIGNED is
TO_UNRESOLVED_UNSIGNED[NATURAL, NATURAL return UNRESOLVED_UNSIGNED];
function TO_UNRESOLVED_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to an UNRESOLVED_SIGNED vector of the specified SIZE.
alias TO_U_SIGNED is
TO_UNRESOLVED_SIGNED[NATURAL, NATURAL return UNRESOLVED_SIGNED];
-- L.15
function "and" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.16
function "and" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.17
function "or" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.18
function "or" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.19
function "nand" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.20
function "nand" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.21
function "nor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.22
function "nor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.23
function "xor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.24
function "xor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.25
function "xnor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.26
function "xnor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.27
function "and" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.28
function "and" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.29
function "or" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.30
function "or" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.31
function "nand" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.32
function "nand" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.33
function "nor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.34
function "nor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.35
function "xor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.36
function "xor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.37
function "xnor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.38
function "xnor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- %%% remove 12 functions (old syntax)
function and_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
function nand_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
function or_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
function nor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
function xor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
function xnor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
function and_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
function nand_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
function or_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
function nor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
function xor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
function xnor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( l : SIGNED ) RETURN std_ulogic;
-- function "nand" ( l : SIGNED ) RETURN std_ulogic;
-- function "or" ( l : SIGNED ) RETURN std_ulogic;
-- function "nor" ( l : SIGNED ) RETURN std_ulogic;
-- function "xor" ( l : SIGNED ) RETURN std_ulogic;
-- function "xnor" ( l : SIGNED ) RETURN std_ulogic;
-- function "and" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "nand" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "or" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "nor" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "xor" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "xnor" ( l : UNSIGNED ) RETURN std_ulogic;
-- rtl_synthesis off
-- pragma synthesis_off
-------------------------------------------------------------------
-- string functions
-------------------------------------------------------------------
function to_string (value : UNSIGNED) return STRING;
function to_string (value : SIGNED) return STRING;
-- explicitly defined operations
alias to_bstring is to_string [UNSIGNED return STRING];
alias to_bstring is to_string [SIGNED return STRING];
alias to_binary_string is to_string [UNSIGNED return STRING];
alias to_binary_string is to_string [SIGNED return STRING];
function to_ostring (value : UNSIGNED) return STRING;
function to_ostring (value : SIGNED) return STRING;
alias to_octal_string is to_ostring [UNSIGNED return STRING];
alias to_octal_string is to_ostring [SIGNED return STRING];
function to_hstring (value : UNSIGNED) return STRING;
function to_hstring (value : SIGNED) return STRING;
alias to_hex_string is to_hstring [UNSIGNED return STRING];
alias to_hex_string is to_hstring [SIGNED return STRING];
procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out UNSIGNED);
procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out SIGNED);
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, UNSIGNED, BOOLEAN];
alias BREAD is READ [LINE, SIGNED, BOOLEAN];
alias BREAD is READ [LINE, UNSIGNED];
alias BREAD is READ [LINE, SIGNED];
alias BINARY_READ is READ [LINE, UNSIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, SIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, UNSIGNED];
alias BINARY_READ is READ [LINE, SIGNED];
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure OREAD (L : inout LINE; VALUE : out SIGNED);
alias OCTAL_READ is OREAD [LINE, UNSIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, SIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNSIGNED];
alias OCTAL_READ is OREAD [LINE, SIGNED];
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure HREAD (L : inout LINE; VALUE : out SIGNED);
alias HEX_READ is HREAD [LINE, UNSIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, SIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNSIGNED];
alias HEX_READ is HREAD [LINE, SIGNED];
alias BWRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, SIGNED, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, SIGNED, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
end package numeric_std_additions;
package body numeric_std_additions is
constant NAU : UNSIGNED(0 downto 1) := (others => '0');
constant NAS : SIGNED(0 downto 1) := (others => '0');
constant NO_WARNING : BOOLEAN := false; -- default to emit warnings
function MAX (left, right : INTEGER) return INTEGER is
begin
if left > right then return left;
else return right;
end if;
end function MAX;
-- Id: A.3R
function "+"(L : UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.4R
function "+"(L : SIGNED; R: STD_ULOGIC) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.4L
function "+"(L : STD_ULOGIC; R: SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.9R
function "-"(L : UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10R
function "-"(L : SIGNED; R: STD_ULOGIC) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-"(L : STD_ULOGIC; R: SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | X |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | W |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | H |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ) -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ ( l, r : STD_ULOGIC ) return STD_ULOGIC is
variable value : STD_ULOGIC;
begin
return match_logic_table (l, r);
end function \?=\;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- "?=" operator is similar to "std_match", but returns a std_ulogic..
-- Id: M.2B
function \?=\ (L, R: UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\(LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% Replace with the following function
-- function "?=" (L, R: UNSIGNED) return std_ulogic is
-- end function "?=";
-- Id: M.3B
function \?=\ (L, R: SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% Replace with the following function
-- function "?=" (L, R: signed) return std_ulogic is
-- end function "?=";
-- Id: C.75
function \?=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?=\ (TO_UNSIGNED(L, R'length), R);
end function \?=\;
-- Id: C.76
function \?=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?=\ (TO_SIGNED(L, R'length), R);
end function \?=\;
-- Id: C.77
function \?=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?=\ (L, TO_UNSIGNED(R, L'length));
end function \?=\;
-- Id: C.78
function \?=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?=\ (L, TO_SIGNED(R, L'length));
end function \?=\;
function \?/=\ (L, R : UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% function "?/=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?/=";
function \?/=\ (L, R : SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% function "?/=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?/=";
-- Id: C.75
function \?/=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?/=\ (TO_UNSIGNED(L, R'length), R);
end function \?/=\;
-- Id: C.76
function \?/=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?/=\ (TO_SIGNED(L, R'length), R);
end function \?/=\;
-- Id: C.77
function \?/=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?/=\ (L, TO_UNSIGNED(R, L'length));
end function \?/=\;
-- Id: C.78
function \?/=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?/=\ (L, TO_SIGNED(R, L'length));
end function \?/=\;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>"\;
function \?>\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?>";
-- Id: C.57
function \?>\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?>\ (TO_UNSIGNED(L, R'length), R);
end function \?>\;
-- Id: C.58
function \?>\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?>\ (TO_SIGNED(L, R'length),R);
end function \?>\;
-- Id: C.59
function \?>\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?>\ (L, TO_UNSIGNED(R, L'length));
end function \?>\;
-- Id: C.60
function \?>\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?>\ (L, TO_SIGNED(R, L'length));
end function \?>\;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?>=\ (TO_UNSIGNED(L, R'length), R);
end function \?>=\;
-- Id: C.64
function \?>=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?>=\ (TO_SIGNED(L, R'length),R);
end function \?>=\;
-- Id: C.65
function \?>=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?>=\ (L, TO_UNSIGNED(R, L'length));
end function \?>=\;
-- Id: C.66
function \?>=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?>=\ (L, TO_SIGNED(R, L'length));
end function \?>=\;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<";
function \?<\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?<";
-- Id: C.57
function \?<\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?<\ (TO_UNSIGNED(L, R'length), R);
end function \?<\;
-- Id: C.58
function \?<\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?<\ (TO_SIGNED(L, R'length),R);
end function \?<\;
-- Id: C.59
function \?<\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?<\ (L, TO_UNSIGNED(R, L'length));
end function \?<\;
-- Id: C.60
function \?<\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?<\ (L, TO_SIGNED(R, L'length));
end function \?<\;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<=";
function \?<=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?<=";
-- Id: C.63
function \?<=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?<=\ (TO_UNSIGNED(L, R'length), R);
end function \?<=\;
-- Id: C.64
function \?<=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?<=\ (TO_SIGNED(L, R'length),R);
end function \?<=\;
-- Id: C.65
function \?<=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?<=\ (L, TO_UNSIGNED(R, L'length));
end function \?<=\;
-- Id: C.66
function \?<=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?<=\ (L, TO_SIGNED(R, L'length));
end function \?<=\;
-- size_res versions of these functions (Bugzilla 165)
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED)
return SIGNED is
begin
return TO_SIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_SIGNED;
function RESIZE (ARG, SIZE_RES : SIGNED)
return SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- Id: S.9
function "sll" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
-- begin LCS-2006-120
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
-- These functions are in std_logic_1164 and are defined for
-- std_logic_vector. They are overloaded here.
function To_X01 ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_X01 (STD_LOGIC_VECTOR (s)));
end function To_X01;
function To_X01 ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_X01 (STD_LOGIC_VECTOR (s)));
end function To_X01;
function To_X01Z ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_X01Z (STD_LOGIC_VECTOR (s)));
end function To_X01Z;
function To_X01Z ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_X01Z (STD_LOGIC_VECTOR (s)));
end function To_X01Z;
function To_UX01 ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_UX01 (STD_LOGIC_VECTOR (s)));
end function To_UX01;
function To_UX01 ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_UX01 (STD_LOGIC_VECTOR (s)));
end function To_UX01;
function Is_X ( s : UNSIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X ( s : SIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
-----------------------------------------------------------------------------
-- New/updated functions for VHDL-200X fast track
-----------------------------------------------------------------------------
-- Returns the maximum (or minimum) of the two numbers provided.
-- All types (both inputs and the output) must be the same.
-- These override the implicit functions, using the local ">" operator
-- UNSIGNED output
function MAXIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- signed output
function MAXIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- UNSIGNED output
function MINIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- signed output
function MINIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNSIGNED)
return UNSIGNED is
begin
return MINIMUM(TO_UNSIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.40
function MINIMUM (L : INTEGER; R : SIGNED)
return SIGNED is
begin
return MINIMUM(TO_SIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.41
function MINIMUM (L : UNSIGNED; R : NATURAL)
return UNSIGNED is
begin
return MINIMUM(L, TO_UNSIGNED(R, L'length));
end function MINIMUM;
-- Id: C.42
function MINIMUM (L : SIGNED; R : INTEGER)
return SIGNED is
begin
return MINIMUM(L, TO_SIGNED(R, L'length));
end function MINIMUM;
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNSIGNED)
return UNSIGNED is
begin
return MAXIMUM(TO_UNSIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.46
function MAXIMUM (L : INTEGER; R : SIGNED)
return SIGNED is
begin
return MAXIMUM(TO_SIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L : UNSIGNED; R : NATURAL)
return UNSIGNED is
begin
return MAXIMUM(L, TO_UNSIGNED(R, L'length));
end function MAXIMUM;
-- Id: C.48
function MAXIMUM (L : SIGNED; R : INTEGER)
return SIGNED is
begin
return MAXIMUM(L, TO_SIGNED(R, L'length));
end function MAXIMUM;
function find_rightmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : UNSIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'reverse_range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_rightmost;
function find_rightmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : SIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'reverse_range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_rightmost;
function find_leftmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : UNSIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_leftmost;
function find_leftmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : SIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_leftmost;
function TO_UNRESOLVED_UNSIGNED (ARG, SIZE : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(to_unsigned (arg, size));
end function TO_UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with
-- the specified SIZE.
function TO_UNRESOLVED_SIGNED (ARG : INTEGER; SIZE : NATURAL)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(to_signed (arg, size));
end function TO_UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to an UNRESOLVED_SIGNED vector of the specified SIZE.
-- Performs the boolean operation on every bit in the vector
-- L.15
function "and" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-- L.16
function "and" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-- L.17
function "or" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-- L.18
function "or" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-- L.19
function "nand" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-- L.20
function "nand" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-- L.21
function "nor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-- L.22
function "nor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-- L.23
function "xor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-- L.24
function "xor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-- L.25
function "xnor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-- L.26
function "xnor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-- L.27
function "and" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-- L.28
function "and" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-- L.29
function "or" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-- L.30
function "or" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-- L.31
function "nand" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-- L.32
function "nand" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-- L.33
function "nor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-- L.34
function "nor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-- L.35
function "xor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-- L.36
function "xor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-- L.37
function "xnor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-- L.38
function "xnor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
--------------------------------------------------------------------------
-- Reduction operations
--------------------------------------------------------------------------
-- %%% Remove the following 12 funcitons (old syntax)
function and_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return and_reduce (UNSIGNED ( l ));
end function and_reduce;
function and_reduce ( l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '1'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "and" (BUS_int(BUS_int'right),BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := and_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := and_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "and" (Upper, Lower);
end if;
end if;
return Result;
end function and_reduce;
function nand_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not" (and_reduce ( l ));
end function nand_reduce;
function nand_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not" (and_reduce (l ));
end function nand_reduce;
function or_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return or_reduce (UNSIGNED ( l ));
end function or_reduce;
function or_reduce (l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "or" (BUS_int(BUS_int'right), BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := or_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := or_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "or" (Upper, Lower);
end if;
end if;
return Result;
end function or_reduce;
function nor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
function nor_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
function xor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return xor_reduce (UNSIGNED ( l ));
end function xor_reduce;
function xor_reduce (l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "xor" (BUS_int(BUS_int'right), BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := xor_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := xor_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "xor" (Upper, Lower);
end if;
end if;
return Result;
end function xor_reduce;
function xnor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
function xnor_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% Replace the above with the following 12 functions (New syntax)
-- function "and" ( l : SIGNED ) return std_ulogic is
-- begin
-- return and (std_logic_vector ( l ));
-- end function "and";
-- function "and" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return and (std_logic_vector ( l ));
-- end function "and";
-- function "nand" ( l : SIGNED ) return std_ulogic is
-- begin
-- return nand (std_logic_vector ( l ));
-- end function "nand";
-- function "nand" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return nand (std_logic_vector ( l ));
-- end function "nand";
-- function "or" ( l : SIGNED ) return std_ulogic is
-- begin
-- return or (std_logic_vector ( l ));
-- end function "or";
-- function "or" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return or (std_logic_vector ( l ));
-- end function "or";
-- function "nor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return nor (std_logic_vector ( l ));
-- end function "nor";
-- function "nor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return nor (std_logic_vector ( l ));
-- end function "nor";
-- function "xor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return xor (std_logic_vector ( l ));
-- end function "xor";
-- function "xor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return xor (std_logic_vector ( l ));
-- end function "xor";
-- function "xnor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return xnor (std_logic_vector ( l ));
-- end function "xnor";
-- function "xnor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return xnor (std_logic_vector ( l ));
-- end function "xnor";
-- rtl_synthesis off
-- pragma synthesis_off
-------------------------------------------------------------------
-- TO_STRING
-------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
function to_string (value : UNSIGNED) return STRING is
alias ivalue : UNSIGNED(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char( iValue(i) );
end loop;
return result;
end if;
end function to_string;
function to_string (value : SIGNED) return STRING is
alias ivalue : SIGNED(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char( iValue(i) );
end loop;
return result;
end if;
end function to_string;
function to_hstring (value : SIGNED) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => value(value'high)); -- Extend sign bit
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function to_ostring (value : SIGNED) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => value (value'high)); -- Extend sign bit
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_hstring (value : UNSIGNED) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function to_ostring (value : UNSIGNED) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-----------------------------------------------------------------------------
-- Read and Write routines
-----------------------------------------------------------------------------
-- Routines copied from the "std_logic_1164_additions" package
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := true;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then
good := false; -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
-- purpose: or reduction
function or_reduce (
arg : STD_ULOGIC_VECTOR)
return STD_ULOGIC is
variable uarg : UNSIGNED (arg'range);
begin
uarg := unsigned(arg);
return or_reduce (uarg);
end function or_reduce;
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
-- End copied code.
procedure READ (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := SIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out SIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := SIGNED (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_string(VALUE), JUSTIFIED, FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_string(VALUE), JUSTIFIED, FIELD);
end procedure WRITE;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.OREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.HREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- rtl_synthesis on
-- pragma synthesis_on
end package body numeric_std_additions;
|
------------------------------------------------------------------------------
-- "numeric_std_additions" package contains the additions to the standard
-- "numeric_std" package proposed by the VHDL-200X-ft working group.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.numeric_std_additions.all;
-- (this package is independant of "std_logic_1164_additions")
-- Last Modified: $Date: 2007/09/27 14:46:32 $
-- RCS ID: $Id: numeric_std_additions.vhdl,v 1.9 2007/09/27 14:46:32 l435385 Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
package numeric_std_additions is
-- Make these a subtype of "signed" and "unsigned" for compatability
-- type UNRESOLVED_UNSIGNED is array (NATURAL range <>) of STD_ULOGIC;
-- type UNRESOLVED_SIGNED is array (NATURAL range <>) of STD_ULOGIC;
subtype UNRESOLVED_UNSIGNED is UNSIGNED;
subtype UNRESOLVED_SIGNED is SIGNED;
-- alias U_UNSIGNED is UNRESOLVED_UNSIGNED;
-- alias U_SIGNED is UNRESOLVED_SIGNED;
subtype U_UNSIGNED is UNSIGNED;
subtype U_SIGNED is SIGNED;
-- Id: A.3R
function "+"(L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- Result subtype: UNSIGNED(L'RANGE)
-- Result: Similar to A.3 where R is a one bit UNSIGNED
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.4R
function "+"(L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- Result subtype: SIGNED(L'RANGE)
-- Result: Similar to A.4 where R is bit 0 of a non-negative
-- SIGNED
-- Id: A.4L
function "+"(L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.4 where L is bit 0 of a non-negative
-- SIGNED
-- Id: A.9R
function "-"(L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- Result subtype: UNSIGNED(L'RANGE)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.10R
function "-"(L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- Result subtype: SIGNED(L'RANGE)
-- Result: Similar to A.10 where R is bit 0 of a non-negative
-- SIGNED
-- Id: A.10L
function "-"(L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- Result subtype: UNSIGNED(R'RANGE)
-- Result: Similar to A.10 where R is bit 0 of a non-negative
-- SIGNED
-- Id: M.2B
-- %%% function "?=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?/=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic;
function \?=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?/=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC;
function \?=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?/=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?>\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?>=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?<\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?<=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC;
function \?=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?/=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?>\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?>=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?<\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
function \?<=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: terms compared per STD_LOGIC_1164 intent,
-- returns an 'X' if a metavalue is passed
-- Id: M.3B
-- %%% function "?=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?/=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?>" (L, R : SIGNED) return std_ulogic;
-- %%% function "?>=" (L, R : SIGNED) return std_ulogic;
-- %%% function "?<" (L, R : SIGNED) return std_ulogic;
-- %%% function "?<=" (L, R : SIGNED) return std_ulogic;
function \?=\ (L, R : SIGNED) return STD_ULOGIC;
function \?/=\ (L, R : SIGNED) return STD_ULOGIC;
function \?>\ (L, R : SIGNED) return STD_ULOGIC;
function \?>=\ (L, R : SIGNED) return STD_ULOGIC;
function \?<\ (L, R : SIGNED) return STD_ULOGIC;
function \?<=\ (L, R : SIGNED) return STD_ULOGIC;
function \?=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?/=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?>\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?>=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?<\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?<=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC;
function \?=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?/=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?>\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?>=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?<\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
function \?<=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC;
-- Result subtype: std_ulogic
-- Result: terms compared per STD_LOGIC_1164 intent,
-- returns an 'X' if a metavalue is passed
-- size_res versions of these functions (Bugzilla 165)
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE_RES'length-1 downto 0)
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : UNSIGNED) return UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED (SIZE_RES'length-1 downto 0)
function RESIZE (ARG, SIZE_RES : SIGNED) return SIGNED;
-- Result subtype: UNRESOLVED_SIGNED (SIZE_RES'length-1 downto 0)
-----------------------------------------------------------------------------
-- New/updated funcitons for VHDL-200X fast track
-----------------------------------------------------------------------------
-- Overloaded functions from "std_logic_1164"
function To_X01 (s : UNSIGNED) return UNSIGNED;
function To_X01 (s : SIGNED) return SIGNED;
function To_X01Z (s : UNSIGNED) return UNSIGNED;
function To_X01Z (s : SIGNED) return SIGNED;
function To_UX01 (s : UNSIGNED) return UNSIGNED;
function To_UX01 (s : SIGNED) return SIGNED;
function Is_X (s : UNSIGNED) return BOOLEAN;
function Is_X (s : SIGNED) return BOOLEAN;
function "sla" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
function "sla" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
function "sra" (ARG : SIGNED; COUNT : INTEGER) return SIGNED;
function "sra" (ARG : UNSIGNED; COUNT : INTEGER) return UNSIGNED;
-- Returns the maximum (or minimum) of the two numbers provided.
-- All types (both inputs and the output) must be the same.
-- These override the implicit funcitons, using the local ">" operator
function maximum (
l, r : UNSIGNED) -- inputs
return UNSIGNED;
function maximum (
l, r : SIGNED) -- inputs
return SIGNED;
function minimum (
l, r : UNSIGNED) -- inputs
return UNSIGNED;
function minimum (
l, r : SIGNED) -- inputs
return SIGNED;
function maximum (
l : UNSIGNED; r : NATURAL) -- inputs
return UNSIGNED;
function maximum (
l : SIGNED; r : INTEGER) -- inputs
return SIGNED;
function minimum (
l : UNSIGNED; r : NATURAL) -- inputs
return UNSIGNED;
function minimum (
l : SIGNED; r : INTEGER) -- inputs
return SIGNED;
function maximum (
l : NATURAL; r : UNSIGNED) -- inputs
return UNSIGNED;
function maximum (
l : INTEGER; r : SIGNED) -- inputs
return SIGNED;
function minimum (
l : NATURAL; r : UNSIGNED) -- inputs
return UNSIGNED;
function minimum (
l : INTEGER; r : SIGNED) -- inputs
return SIGNED;
-- Finds the first "Y" in the input string. Returns an integer index
-- into that string. If "Y" does not exist in the string, then the
-- "find_rightmost" returns arg'low -1, and "find_leftmost" returns -1
function find_rightmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_rightmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_leftmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function find_leftmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER;
function TO_UNRESOLVED_UNSIGNED (ARG, SIZE : NATURAL) return UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with
-- the specified SIZE.
alias TO_U_UNSIGNED is
TO_UNRESOLVED_UNSIGNED[NATURAL, NATURAL return UNRESOLVED_UNSIGNED];
function TO_UNRESOLVED_SIGNED (ARG : INTEGER; SIZE : NATURAL) return UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to an UNRESOLVED_SIGNED vector of the specified SIZE.
alias TO_U_SIGNED is
TO_UNRESOLVED_SIGNED[NATURAL, NATURAL return UNRESOLVED_SIGNED];
-- L.15
function "and" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.16
function "and" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.17
function "or" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.18
function "or" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.19
function "nand" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.20
function "nand" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.21
function "nor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.22
function "nor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.23
function "xor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.24
function "xor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.25
function "xnor" (L : STD_ULOGIC; R : UNSIGNED) return UNSIGNED;
-- L.26
function "xnor" (L : UNSIGNED; R : STD_ULOGIC) return UNSIGNED;
-- L.27
function "and" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.28
function "and" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.29
function "or" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.30
function "or" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.31
function "nand" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.32
function "nand" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.33
function "nor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.34
function "nor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.35
function "xor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.36
function "xor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- L.37
function "xnor" (L : STD_ULOGIC; R : SIGNED) return SIGNED;
-- L.38
function "xnor" (L : SIGNED; R : STD_ULOGIC) return SIGNED;
-- %%% remove 12 functions (old syntax)
function and_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
function nand_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
function or_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
function nor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
function xor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
function xnor_reduce(l : SIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
function and_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of and'ing all of the bits of the vector.
function nand_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nand'ing all of the bits of the vector.
function or_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of or'ing all of the bits of the vector.
function nor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of nor'ing all of the bits of the vector.
function xor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xor'ing all of the bits of the vector.
function xnor_reduce(l : UNSIGNED) return STD_ULOGIC;
-- Result subtype: STD_LOGIC.
-- Result: Result of xnor'ing all of the bits of the vector.
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( l : SIGNED ) RETURN std_ulogic;
-- function "nand" ( l : SIGNED ) RETURN std_ulogic;
-- function "or" ( l : SIGNED ) RETURN std_ulogic;
-- function "nor" ( l : SIGNED ) RETURN std_ulogic;
-- function "xor" ( l : SIGNED ) RETURN std_ulogic;
-- function "xnor" ( l : SIGNED ) RETURN std_ulogic;
-- function "and" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "nand" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "or" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "nor" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "xor" ( l : UNSIGNED ) RETURN std_ulogic;
-- function "xnor" ( l : UNSIGNED ) RETURN std_ulogic;
-- rtl_synthesis off
-- pragma synthesis_off
-------------------------------------------------------------------
-- string functions
-------------------------------------------------------------------
function to_string (value : UNSIGNED) return STRING;
function to_string (value : SIGNED) return STRING;
-- explicitly defined operations
alias to_bstring is to_string [UNSIGNED return STRING];
alias to_bstring is to_string [SIGNED return STRING];
alias to_binary_string is to_string [UNSIGNED return STRING];
alias to_binary_string is to_string [SIGNED return STRING];
function to_ostring (value : UNSIGNED) return STRING;
function to_ostring (value : SIGNED) return STRING;
alias to_octal_string is to_ostring [UNSIGNED return STRING];
alias to_octal_string is to_ostring [SIGNED return STRING];
function to_hstring (value : UNSIGNED) return STRING;
function to_hstring (value : SIGNED) return STRING;
alias to_hex_string is to_hstring [UNSIGNED return STRING];
alias to_hex_string is to_hstring [SIGNED return STRING];
procedure READ(L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out UNSIGNED);
procedure READ(L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure READ(L : inout LINE; VALUE : out SIGNED);
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, UNSIGNED, BOOLEAN];
alias BREAD is READ [LINE, SIGNED, BOOLEAN];
alias BREAD is READ [LINE, UNSIGNED];
alias BREAD is READ [LINE, SIGNED];
alias BINARY_READ is READ [LINE, UNSIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, SIGNED, BOOLEAN];
alias BINARY_READ is READ [LINE, UNSIGNED];
alias BINARY_READ is READ [LINE, SIGNED];
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure OREAD (L : inout LINE; VALUE : out SIGNED);
alias OCTAL_READ is OREAD [LINE, UNSIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, SIGNED, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, UNSIGNED];
alias OCTAL_READ is OREAD [LINE, SIGNED];
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out SIGNED; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED);
procedure HREAD (L : inout LINE; VALUE : out SIGNED);
alias HEX_READ is HREAD [LINE, UNSIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, SIGNED, BOOLEAN];
alias HEX_READ is HREAD [LINE, UNSIGNED];
alias HEX_READ is HREAD [LINE, SIGNED];
alias BWRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, SIGNED, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias OCTAL_WRITE is OWRITE [LINE, SIGNED, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, UNSIGNED, SIDE, WIDTH];
alias HEX_WRITE is HWRITE [LINE, SIGNED, SIDE, WIDTH];
-- rtl_synthesis on
-- pragma synthesis_on
end package numeric_std_additions;
package body numeric_std_additions is
constant NAU : UNSIGNED(0 downto 1) := (others => '0');
constant NAS : SIGNED(0 downto 1) := (others => '0');
constant NO_WARNING : BOOLEAN := false; -- default to emit warnings
function MAX (left, right : INTEGER) return INTEGER is
begin
if left > right then return left;
else return right;
end if;
end function MAX;
-- Id: A.3R
function "+"(L : UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.4R
function "+"(L : SIGNED; R: STD_ULOGIC) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L + XR);
end function "+";
-- Id: A.4L
function "+"(L : STD_ULOGIC; R: SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL + R);
end function "+";
-- Id: A.9R
function "-"(L : UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
variable XR : UNSIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
variable XL : UNSIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
-- Id: A.10R
function "-"(L : SIGNED; R: STD_ULOGIC) return SIGNED is
variable XR : SIGNED(L'length-1 downto 0) := (others => '0');
begin
XR(0) := R;
return (L - XR);
end function "-";
-- Id: A.10L
function "-"(L : STD_ULOGIC; R: SIGNED) return SIGNED is
variable XL : SIGNED(R'length-1 downto 0) := (others => '0');
begin
XL(0) := L;
return (XL - R);
end function "-";
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | X |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | W |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | H |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ) -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ ( l, r : STD_ULOGIC ) return STD_ULOGIC is
variable value : STD_ULOGIC;
begin
return match_logic_table (l, r);
end function \?=\;
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- "?=" operator is similar to "std_match", but returns a std_ulogic..
-- Id: M.2B
function \?=\ (L, R: UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin
-- Logically identical to an "=" operator.
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\(LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% Replace with the following function
-- function "?=" (L, R: UNSIGNED) return std_ulogic is
-- end function "?=";
-- Id: M.3B
function \?=\ (L, R: SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '1';
for i in LX'low to LX'high loop
result1 := \?=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- %%% Replace with the following function
-- function "?=" (L, R: signed) return std_ulogic is
-- end function "?=";
-- Id: C.75
function \?=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?=\ (TO_UNSIGNED(L, R'length), R);
end function \?=\;
-- Id: C.76
function \?=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?=\ (TO_SIGNED(L, R'length), R);
end function \?=\;
-- Id: C.77
function \?=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?=\ (L, TO_UNSIGNED(R, L'length));
end function \?=\;
-- Id: C.78
function \?=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?=\ (L, TO_SIGNED(R, L'length));
end function \?=\;
function \?/=\ (L, R : UNSIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : UNSIGNED(L_LEFT downto 0) is L;
alias XR : UNSIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : UNSIGNED(SIZE-1 downto 0);
variable RX : UNSIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% function "?/=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?/=";
function \?/=\ (L, R : SIGNED) return STD_ULOGIC is
constant L_LEFT : INTEGER := L'length-1;
constant R_LEFT : INTEGER := R'length-1;
alias XL : SIGNED(L_LEFT downto 0) is L;
alias XR : SIGNED(R_LEFT downto 0) is R;
constant SIZE : NATURAL := MAX(L'length, R'length);
variable LX : SIGNED(SIZE-1 downto 0);
variable RX : SIGNED(SIZE-1 downto 0);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'length < 1) or (R'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?/="": null detected, returning X"
severity warning;
return 'X';
else
LX := RESIZE(XL, SIZE);
RX := RESIZE(XR, SIZE);
result := '0';
for i in LX'low to LX'high loop
result1 := \?/=\ (LX(i), RX(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- %%% function "?/=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?/=";
-- Id: C.75
function \?/=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?/=\ (TO_UNSIGNED(L, R'length), R);
end function \?/=\;
-- Id: C.76
function \?/=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?/=\ (TO_SIGNED(L, R'length), R);
end function \?/=\;
-- Id: C.77
function \?/=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?/=\ (L, TO_UNSIGNED(R, L'length));
end function \?/=\;
-- Id: C.78
function \?/=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?/=\ (L, TO_SIGNED(R, L'length));
end function \?/=\;
function \?>\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>"\;
function \?>\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- %%% function "?>" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?>";
-- Id: C.57
function \?>\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?>\ (TO_UNSIGNED(L, R'length), R);
end function \?>\;
-- Id: C.58
function \?>\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?>\ (TO_SIGNED(L, R'length),R);
end function \?>\;
-- Id: C.59
function \?>\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?>\ (L, TO_UNSIGNED(R, L'length));
end function \?>\;
-- Id: C.60
function \?>\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?>\ (L, TO_SIGNED(R, L'length));
end function \?>\;
function \?>=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?>="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?>="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- %%% function "?>=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?>=";
function \?>=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?>=\ (TO_UNSIGNED(L, R'length), R);
end function \?>=\;
-- Id: C.64
function \?>=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?>=\ (TO_SIGNED(L, R'length),R);
end function \?>=\;
-- Id: C.65
function \?>=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?>=\ (L, TO_UNSIGNED(R, L'length));
end function \?>=\;
-- Id: C.66
function \?>=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?>=\ (L, TO_SIGNED(R, L'length));
end function \?>=\;
function \?<\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<";
function \?<\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<"": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<"": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- %%% function "?<" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?<";
-- Id: C.57
function \?<\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?<\ (TO_UNSIGNED(L, R'length), R);
end function \?<\;
-- Id: C.58
function \?<\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?<\ (TO_SIGNED(L, R'length),R);
end function \?<\;
-- Id: C.59
function \?<\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?<\ (L, TO_UNSIGNED(R, L'length));
end function \?<\;
-- Id: C.60
function \?<\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?<\ (L, TO_SIGNED(R, L'length));
end function \?<\;
function \?<=\ (L, R : UNSIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : UNSIGNED) return std_ulogic is
-- %%% end function "?<=";
function \?<=\ (L, R : SIGNED) return STD_ULOGIC is
begin
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "NUMERIC_STD.""?<="": null detected, returning X"
severity warning;
return 'X';
else
for i in L'range loop
if L(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
for i in R'range loop
if R(i) = '-' then
report "NUMERIC_STD.""?<="": '-' found in compare string"
severity error;
return 'X';
end if;
end loop;
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- %%% function "?<=" (L, R : SIGNED) return std_ulogic is
-- %%% end function "?<=";
-- Id: C.63
function \?<=\ (L : NATURAL; R : UNSIGNED) return STD_ULOGIC is
begin
return \?<=\ (TO_UNSIGNED(L, R'length), R);
end function \?<=\;
-- Id: C.64
function \?<=\ (L : INTEGER; R : SIGNED) return STD_ULOGIC is
begin
return \?<=\ (TO_SIGNED(L, R'length),R);
end function \?<=\;
-- Id: C.65
function \?<=\ (L : UNSIGNED; R : NATURAL) return STD_ULOGIC is
begin
return \?<=\ (L, TO_UNSIGNED(R, L'length));
end function \?<=\;
-- Id: C.66
function \?<=\ (L : SIGNED; R : INTEGER) return STD_ULOGIC is
begin
return \?<=\ (L, TO_SIGNED(R, L'length));
end function \?<=\;
-- size_res versions of these functions (Bugzilla 165)
function TO_UNSIGNED (ARG : NATURAL; SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_UNSIGNED;
function TO_SIGNED (ARG : INTEGER; SIZE_RES : SIGNED)
return SIGNED is
begin
return TO_SIGNED (ARG => ARG,
SIZE => SIZE_RES'length);
end function TO_SIGNED;
function RESIZE (ARG, SIZE_RES : SIGNED)
return SIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
function RESIZE (ARG, SIZE_RES : UNSIGNED)
return UNSIGNED is
begin
return RESIZE (ARG => ARG,
NEW_SIZE => SIZE_RES'length);
end function RESIZE;
-- Id: S.9
function "sll" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.10 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), -COUNT));
end if;
end function "sll";
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.12 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT));
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "srl";
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.14 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_LEFT(ARG, COUNT);
else
return ROTATE_RIGHT(ARG, -COUNT);
end if;
end function "rol";
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
------------------------------------------------------------------------------
-- Note: Function S.16 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return ROTATE_RIGHT(ARG, COUNT);
else
return ROTATE_LEFT(ARG, -COUNT);
end if;
end function "ror";
-- begin LCS-2006-120
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.18 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.18
function "sla" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_LEFT(ARG, COUNT);
else
return SHIFT_RIGHT(ARG, -COUNT);
end if;
end function "sla";
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : UNSIGNED; COUNT : INTEGER)
return UNSIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
------------------------------------------------------------------------------
-- Note: Function S.20 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.20
function "sra" (ARG : SIGNED; COUNT : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(ARG, COUNT);
else
return SHIFT_LEFT(ARG, -COUNT);
end if;
end function "sra";
-- These functions are in std_logic_1164 and are defined for
-- std_logic_vector. They are overloaded here.
function To_X01 ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_X01 (STD_LOGIC_VECTOR (s)));
end function To_X01;
function To_X01 ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_X01 (STD_LOGIC_VECTOR (s)));
end function To_X01;
function To_X01Z ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_X01Z (STD_LOGIC_VECTOR (s)));
end function To_X01Z;
function To_X01Z ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_X01Z (STD_LOGIC_VECTOR (s)));
end function To_X01Z;
function To_UX01 ( s : UNSIGNED ) return UNSIGNED is
begin
return UNSIGNED (To_UX01 (STD_LOGIC_VECTOR (s)));
end function To_UX01;
function To_UX01 ( s : SIGNED ) return SIGNED is
begin
return SIGNED (To_UX01 (STD_LOGIC_VECTOR (s)));
end function To_UX01;
function Is_X ( s : UNSIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
function Is_X ( s : SIGNED ) return BOOLEAN is
begin
return Is_X (STD_LOGIC_VECTOR (s));
end function Is_X;
-----------------------------------------------------------------------------
-- New/updated functions for VHDL-200X fast track
-----------------------------------------------------------------------------
-- Returns the maximum (or minimum) of the two numbers provided.
-- All types (both inputs and the output) must be the same.
-- These override the implicit functions, using the local ">" operator
-- UNSIGNED output
function MAXIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- signed output
function MAXIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return R01;
else
return L01;
end if;
end function MAXIMUM;
-- UNSIGNED output
function MINIMUM (L, R : UNSIGNED) return UNSIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAU;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- signed output
function MINIMUM (L, R : SIGNED) return SIGNED is
constant SIZE : NATURAL := MAX(L'length, R'length);
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length < 1) or (R'length < 1)) then return NAS;
end if;
L01 := TO_01(RESIZE(L, SIZE), 'X');
if (L01(L01'left) = 'X') then return L01;
end if;
R01 := TO_01(RESIZE(R, SIZE), 'X');
if (R01(R01'left) = 'X') then return R01;
end if;
if L01 < R01 then
return L01;
else
return R01;
end if;
end function MINIMUM;
-- Id: C.39
function MINIMUM (L : NATURAL; R : UNSIGNED)
return UNSIGNED is
begin
return MINIMUM(TO_UNSIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.40
function MINIMUM (L : INTEGER; R : SIGNED)
return SIGNED is
begin
return MINIMUM(TO_SIGNED(L, R'length), R);
end function MINIMUM;
-- Id: C.41
function MINIMUM (L : UNSIGNED; R : NATURAL)
return UNSIGNED is
begin
return MINIMUM(L, TO_UNSIGNED(R, L'length));
end function MINIMUM;
-- Id: C.42
function MINIMUM (L : SIGNED; R : INTEGER)
return SIGNED is
begin
return MINIMUM(L, TO_SIGNED(R, L'length));
end function MINIMUM;
-- Id: C.45
function MAXIMUM (L : NATURAL; R : UNSIGNED)
return UNSIGNED is
begin
return MAXIMUM(TO_UNSIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.46
function MAXIMUM (L : INTEGER; R : SIGNED)
return SIGNED is
begin
return MAXIMUM(TO_SIGNED(L, R'length), R);
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L : UNSIGNED; R : NATURAL)
return UNSIGNED is
begin
return MAXIMUM(L, TO_UNSIGNED(R, L'length));
end function MAXIMUM;
-- Id: C.48
function MAXIMUM (L : SIGNED; R : INTEGER)
return SIGNED is
begin
return MAXIMUM(L, TO_SIGNED(R, L'length));
end function MAXIMUM;
function find_rightmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : UNSIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'reverse_range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_rightmost;
function find_rightmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : SIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'reverse_range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_rightmost;
function find_leftmost (
arg : UNSIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : UNSIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_leftmost;
function find_leftmost (
arg : SIGNED; -- vector argument
y : STD_ULOGIC) -- look for this bit
return INTEGER is
alias xarg : SIGNED(arg'length-1 downto 0) is arg;
begin
for_loop: for i in xarg'range loop
if \?=\ (xarg(i), y) = '1' then
return i;
end if;
end loop;
return -1;
end function find_leftmost;
function TO_UNRESOLVED_UNSIGNED (ARG, SIZE : NATURAL)
return UNRESOLVED_UNSIGNED is
begin
return UNRESOLVED_UNSIGNED(to_unsigned (arg, size));
end function TO_UNRESOLVED_UNSIGNED;
-- Result subtype: UNRESOLVED_UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a nonnegative INTEGER to an UNRESOLVED_UNSIGNED vector with
-- the specified SIZE.
function TO_UNRESOLVED_SIGNED (ARG : INTEGER; SIZE : NATURAL)
return UNRESOLVED_SIGNED is
begin
return UNRESOLVED_SIGNED(to_signed (arg, size));
end function TO_UNRESOLVED_SIGNED;
-- Result subtype: UNRESOLVED_SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to an UNRESOLVED_SIGNED vector of the specified SIZE.
-- Performs the boolean operation on every bit in the vector
-- L.15
function "and" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-- L.16
function "and" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-- L.17
function "or" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-- L.18
function "or" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-- L.19
function "nand" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-- L.20
function "nand" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-- L.21
function "nor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-- L.22
function "nor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-- L.23
function "xor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-- L.24
function "xor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-- L.25
function "xnor" (L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
alias rv : UNSIGNED ( 1 to r'length ) is r;
variable result : UNSIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-- L.26
function "xnor" (L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
alias lv : UNSIGNED ( 1 to l'length ) is l;
variable result : UNSIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
-- L.27
function "and" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "and" (l, rv(i));
end loop;
return result;
end function "and";
-- L.28
function "and" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "and" (lv(i), r);
end loop;
return result;
end function "and";
-- L.29
function "or" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "or" (l, rv(i));
end loop;
return result;
end function "or";
-- L.30
function "or" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "or" (lv(i), r);
end loop;
return result;
end function "or";
-- L.31
function "nand" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("and" (l, rv(i)));
end loop;
return result;
end function "nand";
-- L.32
function "nand" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("and" (lv(i), r));
end loop;
return result;
end function "nand";
-- L.33
function "nor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("or" (l, rv(i)));
end loop;
return result;
end function "nor";
-- L.34
function "nor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("or" (lv(i), r));
end loop;
return result;
end function "nor";
-- L.35
function "xor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "xor" (l, rv(i));
end loop;
return result;
end function "xor";
-- L.36
function "xor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "xor" (lv(i), r);
end loop;
return result;
end function "xor";
-- L.37
function "xnor" (L: STD_ULOGIC; R: SIGNED) return SIGNED is
alias rv : SIGNED ( 1 to r'length ) is r;
variable result : SIGNED ( 1 to r'length );
begin
for i in result'range loop
result(i) := "not"("xor" (l, rv(i)));
end loop;
return result;
end function "xnor";
-- L.38
function "xnor" (L: SIGNED; R: STD_ULOGIC) return SIGNED is
alias lv : SIGNED ( 1 to l'length ) is l;
variable result : SIGNED ( 1 to l'length );
begin
for i in result'range loop
result(i) := "not"("xor" (lv(i), r));
end loop;
return result;
end function "xnor";
--------------------------------------------------------------------------
-- Reduction operations
--------------------------------------------------------------------------
-- %%% Remove the following 12 funcitons (old syntax)
function and_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return and_reduce (UNSIGNED ( l ));
end function and_reduce;
function and_reduce ( l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '1'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "and" (BUS_int(BUS_int'right),BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := and_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := and_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "and" (Upper, Lower);
end if;
end if;
return Result;
end function and_reduce;
function nand_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not" (and_reduce ( l ));
end function nand_reduce;
function nand_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not" (and_reduce (l ));
end function nand_reduce;
function or_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return or_reduce (UNSIGNED ( l ));
end function or_reduce;
function or_reduce (l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "or" (BUS_int(BUS_int'right), BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := or_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := or_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "or" (Upper, Lower);
end if;
end if;
return Result;
end function or_reduce;
function nor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
function nor_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not"(or_reduce(l));
end function nor_reduce;
function xor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return xor_reduce (UNSIGNED ( l ));
end function xor_reduce;
function xor_reduce (l : UNSIGNED ) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : UNSIGNED ( l'length - 1 downto 0 );
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (l'length >= 1) then
BUS_int := to_ux01 (l);
if ( BUS_int'length = 1 ) then
Result := BUS_int ( BUS_int'left );
elsif ( BUS_int'length = 2 ) then
Result := "xor" (BUS_int(BUS_int'right), BUS_int(BUS_int'left));
else
Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
Upper := xor_reduce ( BUS_int ( BUS_int'left downto Half ));
Lower := xor_reduce ( BUS_int ( Half - 1 downto BUS_int'right ));
Result := "xor" (Upper, Lower);
end if;
end if;
return Result;
end function xor_reduce;
function xnor_reduce (l : SIGNED ) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
function xnor_reduce (l : UNSIGNED ) return STD_ULOGIC is
begin
return "not"(xor_reduce(l));
end function xnor_reduce;
-- %%% Replace the above with the following 12 functions (New syntax)
-- function "and" ( l : SIGNED ) return std_ulogic is
-- begin
-- return and (std_logic_vector ( l ));
-- end function "and";
-- function "and" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return and (std_logic_vector ( l ));
-- end function "and";
-- function "nand" ( l : SIGNED ) return std_ulogic is
-- begin
-- return nand (std_logic_vector ( l ));
-- end function "nand";
-- function "nand" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return nand (std_logic_vector ( l ));
-- end function "nand";
-- function "or" ( l : SIGNED ) return std_ulogic is
-- begin
-- return or (std_logic_vector ( l ));
-- end function "or";
-- function "or" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return or (std_logic_vector ( l ));
-- end function "or";
-- function "nor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return nor (std_logic_vector ( l ));
-- end function "nor";
-- function "nor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return nor (std_logic_vector ( l ));
-- end function "nor";
-- function "xor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return xor (std_logic_vector ( l ));
-- end function "xor";
-- function "xor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return xor (std_logic_vector ( l ));
-- end function "xor";
-- function "xnor" ( l : SIGNED ) return std_ulogic is
-- begin
-- return xnor (std_logic_vector ( l ));
-- end function "xnor";
-- function "xnor" ( l : UNSIGNED ) return std_ulogic is
-- begin
-- return xnor (std_logic_vector ( l ));
-- end function "xnor";
-- rtl_synthesis off
-- pragma synthesis_off
-------------------------------------------------------------------
-- TO_STRING
-------------------------------------------------------------------
-- Type and constant definitions used to map STD_ULOGIC values
-- into/from character values.
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' '); -- NULL array
function to_string (value : UNSIGNED) return STRING is
alias ivalue : UNSIGNED(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char( iValue(i) );
end loop;
return result;
end if;
end function to_string;
function to_string (value : SIGNED) return STRING is
alias ivalue : SIGNED(1 to value'length) is value;
variable result : STRING(1 to value'length);
begin
if value'length < 1 then
return NUS;
else
for i in ivalue'range loop
result(i) := MVL9_to_char( iValue(i) );
end loop;
return result;
end if;
end function to_string;
function to_hstring (value : SIGNED) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => value(value'high)); -- Extend sign bit
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function to_ostring (value : SIGNED) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => value (value'high)); -- Extend sign bit
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
function to_hstring (value : UNSIGNED) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_hstring;
function to_ostring (value : UNSIGNED) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & STD_LOGIC_VECTOR (value);
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return result;
end if;
end function to_ostring;
-----------------------------------------------------------------------------
-- Read and Write routines
-----------------------------------------------------------------------------
-- Routines copied from the "std_logic_1164_additions" package
-- purpose: Skips white space
procedure skip_whitespace (
L : inout LINE) is
variable readOk : BOOLEAN;
variable c : CHARACTER;
begin
while L /= null and L.all'length /= 0 loop
if (L.all(1) = ' ' or L.all(1) = NBSP or L.all(1) = HT) then
read (l, c, readOk);
else
exit;
end if;
end loop;
end procedure skip_whitespace;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, readOk);
i := 0;
good := true;
while i < VALUE'length loop
if not readOk then -- Bail out if there was a bad read
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
elsif (char_to_MVL9plus(c) = error) then
good := false; -- Illegal character
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then -- reading done
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
else
good := true; -- read into a null array
end if;
end procedure READ;
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable m : STD_ULOGIC;
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable mv : STD_ULOGIC_VECTOR(0 to VALUE'length-1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, readOk);
i := 0;
while i < VALUE'length loop
if readOk = false then -- Bail out if there was a bad read
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
elsif char_to_MVL9plus(c) = error then
report
"STD_LOGIC_1164.READ(STD_ULOGIC_VECTOR) Error: Character '" &
c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
mv(i) := char_to_MVL9(c);
i := i + 1;
if i > mv'high then
VALUE := mv;
return;
end if;
lastu := false;
end if;
read(L, c, readOk);
end loop;
end if;
end procedure READ;
-- purpose: or reduction
function or_reduce (
arg : STD_ULOGIC_VECTOR)
return STD_ULOGIC is
variable uarg : UNSIGNED (arg'range);
begin
uarg := unsigned(arg);
return or_reduce (uarg);
end function or_reduce;
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.HREAD Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- Null input string, skips whitespace
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+3)/4;
constant pad : INTEGER := ne*4 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then -- non Null input string
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.HREAD "
& "End of string encountered"
severity error;
return;
end if;
if c = '_' then
if i = 0 then
report "STD_LOGIC_1164.HREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.HREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2QuadBits(c, sv(4*i to 4*i+3), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.HREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure HREAD;
-- Octal Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_ULOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"STD_LOGIC_1164.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
good := false;
end case;
end procedure Char2TriBits;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR;
GOOD : out BOOLEAN) is
variable ok : BOOLEAN;
variable c : CHARACTER;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
good := false;
return;
elsif c = '_' then
if i = 0 then
good := false; -- Begins with an "_"
return;
elsif lastu then
good := false; -- "__" detected
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, false);
if not ok then
good := false;
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
good := false; -- vector was truncated.
else
good := true;
VALUE := sv (pad to sv'high);
end if;
else
good := true; -- read into a null array
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR) is
variable c : CHARACTER;
variable ok : BOOLEAN;
constant ne : INTEGER := (VALUE'length+2)/3;
constant pad : INTEGER := ne*3 - VALUE'length;
variable sv : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
variable i : INTEGER;
variable lastu : BOOLEAN := false; -- last character was an "_"
begin
VALUE := (VALUE'range => 'U'); -- initialize to a "U"
Skip_whitespace (L);
if VALUE'length > 0 then
read (l, c, ok);
i := 0;
while i < ne loop
-- Bail out if there was a bad read
if not ok then
report "STD_LOGIC_1164.OREAD "
& "End of string encountered"
severity error;
return;
elsif c = '_' then
if i = 0 then
report "STD_LOGIC_1164.OREAD "
& "String begins with an ""_""" severity error;
return;
elsif lastu then
report "STD_LOGIC_1164.OREAD "
& "Two underscores detected in input string ""__"""
severity error;
return;
else
lastu := true;
end if;
else
Char2TriBits(c, sv(3*i to 3*i+2), ok, true);
if not ok then
return;
end if;
i := i + 1;
lastu := false;
end if;
if i < ne then
read(L, c, ok);
end if;
end loop;
if or_reduce (sv (0 to pad-1)) = '1' then -- %%% replace with "or"
report "STD_LOGIC_1164.OREAD Vector truncated"
severity error;
else
VALUE := sv (pad to sv'high);
end if;
end if;
end procedure OREAD;
-- End copied code.
procedure READ (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := SIGNED(ivalue);
end procedure READ;
procedure READ (L : inout LINE; VALUE : out SIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
READ (L => L,
VALUE => ivalue);
VALUE := SIGNED (ivalue);
end procedure READ;
procedure WRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_string(VALUE), JUSTIFIED, FIELD);
end procedure WRITE;
procedure WRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_string(VALUE), JUSTIFIED, FIELD);
end procedure WRITE;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
-- Bail out if there was a bad read
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
OREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure OREAD;
procedure OREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (value'length+2)/3;
constant pad : INTEGER := ne*3 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
OREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.OREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure OREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED;
GOOD : out BOOLEAN) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue,
GOOD => GOOD);
VALUE := UNSIGNED(ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED;
GOOD : out BOOLEAN) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable ok : BOOLEAN;
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue, -- Read padded STRING
GOOD => ok);
if not ok then
GOOD := false;
return;
end if;
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
GOOD := false;
else
GOOD := true;
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out UNSIGNED) is
variable ivalue : STD_ULOGIC_VECTOR(value'range);
begin
HREAD (L => L,
VALUE => ivalue);
VALUE := UNSIGNED (ivalue);
end procedure HREAD;
procedure HREAD (L : inout LINE; VALUE : out SIGNED) is
constant ne : INTEGER := (value'length+3)/4;
constant pad : INTEGER := ne*4 - value'length;
variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4-1);
variable expected_padding : STD_ULOGIC_VECTOR(0 to pad-1);
begin
HREAD (L => L,
VALUE => ivalue); -- Read padded string
expected_padding := (others => ivalue(pad));
if ivalue(0 to pad-1) /= expected_padding then
assert false
report "NUMERIC_STD.HREAD Error: Signed vector truncated"
severity error;
else
VALUE := UNRESOLVED_SIGNED (ivalue (pad to ivalue'high));
end if;
end procedure HREAD;
procedure OWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure OWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_ostring(VALUE), JUSTIFIED, FIELD);
end procedure OWRITE;
procedure HWRITE (L : inout LINE; VALUE : in UNSIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
procedure HWRITE (L : inout LINE; VALUE : in SIGNED;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0) is
begin
write (L, to_hstring (VALUE), JUSTIFIED, FIELD);
end procedure HWRITE;
-- rtl_synthesis on
-- pragma synthesis_on
end package body numeric_std_additions;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc422.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00422ent IS
END c03s02b01x01p19n01i00422ent;
ARCHITECTURE c03s02b01x01p19n01i00422arch OF c03s02b01x01p19n01i00422ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
constant C1 : boolean_cons_vectorofvector := (others => (others => true));
function complex_scalar(s : boolean_cons_vectorofvector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_cons_vectorofvector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_cons_vectorofvector;
signal S2 : boolean_cons_vectorofvector;
signal S3 : boolean_cons_vectorofvector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00422"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00422 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00422arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc422.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00422ent IS
END c03s02b01x01p19n01i00422ent;
ARCHITECTURE c03s02b01x01p19n01i00422arch OF c03s02b01x01p19n01i00422ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
constant C1 : boolean_cons_vectorofvector := (others => (others => true));
function complex_scalar(s : boolean_cons_vectorofvector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_cons_vectorofvector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_cons_vectorofvector;
signal S2 : boolean_cons_vectorofvector;
signal S3 : boolean_cons_vectorofvector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00422"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00422 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00422arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc422.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00422ent IS
END c03s02b01x01p19n01i00422ent;
ARCHITECTURE c03s02b01x01p19n01i00422arch OF c03s02b01x01p19n01i00422ent IS
type boolean_cons_vector is array (15 downto 0) of boolean;
type boolean_cons_vectorofvector is array (0 to 15) of boolean_cons_vector;
constant C1 : boolean_cons_vectorofvector := (others => (others => true));
function complex_scalar(s : boolean_cons_vectorofvector) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_cons_vectorofvector is
begin
return C1;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_cons_vectorofvector;
signal S2 : boolean_cons_vectorofvector;
signal S3 : boolean_cons_vectorofvector := C1;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C1) and (S2 = C1))
report "***PASSED TEST: c03s02b01x01p19n01i00422"
severity NOTE;
assert ((S1 = C1) and (S2 = C1))
report "***FAILED TEST: c03s02b01x01p19n01i00422 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00422arch;
|
architecture structure of FIFOSyncTop is
component FIFODualPortRam
Generic (
DataWidth : integer range 2 to 64 := 8;
AdressWidth : integer range 2 to 10 := 4);
Port (
Reset_n_i : in STD_LOGIC;
ClkA : in STD_LOGIC;
DataA_i : in STD_LOGIC_VECTOR (DataWidth - 1 downto 0);
AdressA_i : in STD_LOGIC_VECTOR (AdressWidth - 1 downto 0);
WriteEnableA_i : in STD_LOGIC;
DataB_o : out STD_LOGIC_VECTOR (DataWidth - 1 downto 0);
AdressB_i : in STD_LOGIC_VECTOR (AdressWidth - 1 downto 0));
end component;
component FIFOBinaryCounter
Generic (
AdressWidth : integer range 2 to 10 := 4);
Port (
Reset_n : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkEnable_i : in STD_LOGIC;
Binary_o : out STD_LOGIC_VECTOR (AdressWidth - 1 downto 0);
BinaryMSB_o : out STD_LOGIC);
end component;
component FIFOSyncCmp
Generic (
AdressWidth : integer range 2 to 10 := 4);
Port (
PointerA_i : in STD_LOGIC_VECTOR (AdressWidth - 1 downto 0);
PointerB_i : in STD_LOGIC_VECTOR (AdressWidth - 1 downto 0);
MSBPointerA_i : in STD_LOGIC;
MSBPointerB_i : in STD_LOGIC;
FIFOFull_o : out STD_LOGIC;
FIFOEmpty_o : out STD_LOGIC);
end component;
signal AdressA : STD_LOGIC_VECTOR (AdressWidth - 1 downto 0);
signal AdressB : STD_LOGIC_VECTOR (AdressWidth - 1 downto 0);
signal MSBAdressA : STD_LOGIC;
signal MSBAdressB : STD_LOGIC;
begin
DualPortRam: FIFODualPortRam
Generic Map (
DataWidth => DataWidth,
AdressWidth => AdressWidth)
Port Map (
Reset_n_i => Reset_n,
ClkA => Clk,
DataA_i => DataA_i,
AdressA_i => AdressA,
WriteEnableA_i => WriteA_i,
DataB_o => DataB_o,
AdressB_i => AdressB);
WriteCounter: FIFOBinaryCounter
Generic Map (
AdressWidth => AdressWidth)
Port Map (
Reset_n => Reset_n,
Clk => Clk,
ClkEnable_i => WriteA_i,
Binary_o => AdressA,
BinaryMSB_o => MSBAdressA);
ReadCounter: FIFOBinaryCounter
Generic Map (
AdressWidth => AdressWidth)
Port Map (
Reset_n => Reset_n,
Clk => Clk,
ClkEnable_i => ReadNextB_i,
Binary_o => AdressB,
BinaryMSB_o => MSBAdressB);
SyncCmp: FIFOSyncCmp
Generic Map (
AdressWidth => AdressWidth)
Port Map (
PointerA_i => AdressA,
PointerB_i => AdressB,
MSBPointerA_i => MSBAdressA,
MSBPointerB_i => MSBAdressB,
FIFOFull_o => FIFOFull_o,
FIFOEmpty_o => FIFOEmpty_o);
end structure;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.axistream_bfm_pkg.all;
use work.transaction_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_cmd_pkg is
alias t_operation is work.transaction_pkg.t_operation;
--===============================================================================================
-- t_vvc_cmd_record
-- - Record type used for communication with the VVC
--===============================================================================================
type t_vvc_cmd_record is record
-- VVC dedicated fields
data_array : t_byte_array(0 to C_VVC_CMD_DATA_MAX_BYTES-1);
data_array_length : integer range -10 to C_VVC_CMD_DATA_MAX_BYTES; -- Some negative numbers have special meaning in axistreamStartTransmits()
-- If you need support for more bits per data byte, replace this with a wider type:
user_array : t_user_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
user_array_length : natural range 1 to C_VVC_CMD_DATA_MAX_WORDS; -- One user_array entry per word (clock cycle)
strb_array : t_strb_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
strb_array_length : natural range 1 to C_VVC_CMD_DATA_MAX_WORDS; -- One strb_array entry per word (clock cycle)
id_array : t_id_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
id_array_length : natural range 1 to C_VVC_CMD_DATA_MAX_WORDS; -- One id_array entry per word (clock cycle)
dest_array : t_dest_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
dest_array_length : natural range 1 to C_VVC_CMD_DATA_MAX_WORDS; -- One dest_array entry per word (clock cycle)
-- Common VVC fields
operation : t_operation;
proc_call : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
data_routing : t_data_routing;
cmd_idx : natural;
command_type : t_immediate_or_queued;
msg_id : t_msg_id;
gen_integer_array : t_integer_array(0 to 1); -- Increase array length if needed
gen_boolean : boolean; -- Generic boolean
timeout : time;
alert_level : t_alert_level;
delay : time;
quietness : t_quietness;
parent_msg_id_panel : t_msg_id_panel;
end record;
constant C_VVC_CMD_DEFAULT : t_vvc_cmd_record := (
data_array => (others => (others => '0')),
data_array_length => 1,
user_array => (others => (others => '0')),
user_array_length => 1,
strb_array => (others => (others => '0')),
strb_array_length => 1,
id_array => (others => (others => '0')),
id_array_length => 1,
dest_array => (others => (others => '0')),
dest_array_length => 1,
-- Common VVC fields
operation => NO_OPERATION,
proc_call => (others => NUL),
msg => (others => NUL),
data_routing => NA,
cmd_idx => 0,
command_type => NO_COMMAND_TYPE,
msg_id => NO_ID,
gen_integer_array => (others => -1),
gen_boolean => false,
timeout => 0 ns,
alert_level => FAILURE,
delay => 0 ns,
quietness => NON_QUIET,
parent_msg_id_panel => C_UNUSED_MSG_ID_PANEL
);
--===============================================================================================
-- shared_vvc_cmd
-- - Shared variable used for transmitting VVC commands
--===============================================================================================
shared variable shared_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
--===============================================================================================
-- t_vvc_result, t_vvc_result_queue_element, t_vvc_response and shared_vvc_response :
--
-- - Used for storing the result of a BFM procedure called by the VVC,
-- so that the result can be transported from the VVC to for example a sequencer via
-- fetch_result() as described in VVC_Framework_common_methods_QuickRef
--
-- - t_vvc_result includes the return value of the procedure in the BFM.
-- It can also be defined as a record if multiple values shall be transported from the BFM
--===============================================================================================
type t_vvc_result is record
data_array : t_byte_array(0 to C_VVC_CMD_DATA_MAX_BYTES-1);
data_length : natural;
user_array : t_user_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
strb_array : t_strb_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
id_array : t_id_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
dest_array : t_dest_array(0 to C_VVC_CMD_DATA_MAX_WORDS-1);
end record;
type t_vvc_result_queue_element is record
cmd_idx : natural; -- from UVVM handshake mechanism
result : t_vvc_result;
end record;
type t_vvc_response is record
fetch_is_accepted : boolean;
transaction_result : t_transaction_result;
result : t_vvc_result;
end record;
shared variable shared_vvc_response : t_vvc_response;
--===============================================================================================
-- t_last_received_cmd_idx :
-- - Used to store the last queued cmd in vvc interpreter.
--===============================================================================================
type t_last_received_cmd_idx is array (t_channel range <>,natural range <>) of integer;
--===============================================================================================
-- shared_vvc_last_received_cmd_idx
-- - Shared variable used to get last queued index from vvc to sequencer
--===============================================================================================
shared variable shared_vvc_last_received_cmd_idx : t_last_received_cmd_idx(t_channel'left to t_channel'right, 0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => (others => -1));
--===============================================================================================
-- Procedures
--===============================================================================================
function to_string(
result : t_vvc_result
) return string;
end package vvc_cmd_pkg;
package body vvc_cmd_pkg is
-- Custom to_string overload needed when result is of a type that haven't got one already
function to_string(
result : t_vvc_result
) return string is
begin
return to_string(result.data_length) & " Bytes";
end;
end package body vvc_cmd_pkg;
|
-- cb20_gpio_block_0_avalon_slave_0_translator.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_gpio_block_0_avalon_slave_0_translator is
generic (
AV_ADDRESS_W : integer := 4;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 17;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(16 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(3 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_chipselect : out std_logic;
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_response : in std_logic_vector(1 downto 0) := (others => '0');
av_writebyteenable : out std_logic_vector(3 downto 0);
av_writeresponserequest : out std_logic;
av_writeresponsevalid : in std_logic := '0';
uav_clken : in std_logic := '0';
uav_response : out std_logic_vector(1 downto 0);
uav_writeresponserequest : in std_logic := '0';
uav_writeresponsevalid : out std_logic
);
end entity cb20_gpio_block_0_avalon_slave_0_translator;
architecture rtl of cb20_gpio_block_0_avalon_slave_0_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
USE_READRESPONSE : integer := 0;
USE_WRITERESPONSE : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(16 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(3 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_byteenable : out std_logic_vector(3 downto 0); -- byteenable
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_chipselect : out std_logic; -- chipselect
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic; -- outputenable
uav_response : out std_logic_vector(1 downto 0); -- response
av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response
uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest
uav_writeresponsevalid : out std_logic; -- writeresponsevalid
av_writeresponserequest : out std_logic; -- writeresponserequest
av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid
);
end component altera_merlin_slave_translator;
begin
gpio_block_0_avalon_slave_0_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
USE_READRESPONSE => USE_READRESPONSE,
USE_WRITERESPONSE => USE_WRITERESPONSE,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_byteenable => av_byteenable, -- .byteenable
av_waitrequest => av_waitrequest, -- .waitrequest
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_chipselect => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open, -- (terminated)
uav_response => open, -- (terminated)
av_response => "00", -- (terminated)
uav_writeresponserequest => '0', -- (terminated)
uav_writeresponsevalid => open, -- (terminated)
av_writeresponserequest => open, -- (terminated)
av_writeresponsevalid => '0' -- (terminated)
);
end architecture rtl; -- of cb20_gpio_block_0_avalon_slave_0_translator
|
-- NEED RESULT: ARCH00673: Variable values persist over simulation time passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00673
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 4.3.1.3 (5)
-- 4.3.1.3 (6)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00673)
-- ENT00673_Test_Bench(ARCH00673_Test_Bench)
--
-- REVISION HISTORY:
--
-- 1-SEP-1987 - initial revision
-- 8-APR-1988 - JW: made correct1 a parameter to p1
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00673 of E00000 is
type state is ( state1 , state2 , state3 ) ;
signal s_state : state := state1 ;
signal correct1 : boolean := true ;
signal correct2 : boolean := true ;
procedure p1 (signal correct1: inout boolean) is
variable v_integer : integer := 5 ;
variable v_string : string (1 to 5) ;
begin
v_string := "abcde" ;
wait on s_state ;
correct1 <= correct1 and v_integer = 5 and v_string = "abcde" ;
end p1 ;
begin
process
begin
p1(correct1) ;
end process ;
process
variable v_integer : integer := 5 ;
variable v_string : string (1 to 5) ;
begin
v_string := "abcde" ;
s_state <= state3 ;
wait on s_state ;
correct2 <= correct2 and v_integer = 5 and v_string = "abcde" ;
end process ;
process (s_state)
begin
if s_state = state3 then
test_report ( "ARCH00673" ,
"Variable values persist over simulation time" ,
correct1 and correct2) ;
end if ;
end process ;
end ARCH00673 ;
--
entity ENT00673_Test_Bench is
end ENT00673_Test_Bench ;
architecture ARCH00673_Test_Bench of ENT00673_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00673 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00673_Test_Bench ;
--
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pixel_difference_2d is
Port ( i_clk : in STD_LOGIC;
i_reset : in STD_LOGIC;
i_R : in STD_LOGIC_VECTOR (7 downto 0);
i_G : in STD_LOGIC_VECTOR (7 downto 0);
i_B : in STD_LOGIC_VECTOR (7 downto 0);
i_framevalid : in STD_LOGIC;
i_linevalid : in STD_LOGIC;
o_focusvalue : out STD_LOGIC_VECTOR(31 downto 0);
o_dv : out STD_LOGIC
);
end pixel_difference_2d;
architecture Behavioral of pixel_difference_2d is
COMPONENT color_space_converter
PORT(
i_clk : IN std_logic;
i_reset : IN std_logic;
i_R : IN std_logic_vector(7 downto 0);
i_G : IN std_logic_vector(7 downto 0);
i_B : IN std_logic_vector(7 downto 0);
i_framevalid : IN std_logic;
i_linevalid : IN std_logic;
o_Y : OUT std_logic_vector(7 downto 0);
o_framevalid : OUT std_logic;
o_linevalid : OUT std_logic
);
END COMPONENT;
COMPONENT focus_calculation_pixel_difference_2d
PORT(
i_clk : IN std_logic;
i_reset : IN std_logic;
i_framevalid : IN std_logic;
i_linevalid : IN std_logic;
i_Y : IN std_logic_vector(7 downto 0);
o_focusvalue : OUT std_logic_vector(31 downto 0);
o_dv : OUT std_logic
);
END COMPONENT;
signal s_framevalid : STD_LOGIC;
signal s_linevalid : STD_LOGIC;
signal s_Y : STD_LOGIC_VECTOR(7 downto 0);
begin
Inst_color_space_converter: color_space_converter PORT MAP(
i_clk => i_clk,
i_reset => i_reset,
i_R => i_R,
i_G => i_G,
i_B => i_B,
i_framevalid => i_framevalid,
i_linevalid => i_linevalid,
o_Y => s_Y,
o_framevalid => s_framevalid,
o_linevalid => s_linevalid
);
Inst_focus_calculation: focus_calculation_pixel_difference_2d PORT MAP(
i_clk => i_clk,
i_reset => i_reset,
i_framevalid => s_framevalid,
i_linevalid => s_linevalid,
i_Y => s_Y,
o_focusvalue => o_focusvalue,
o_dv => o_dv
);
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity color_mapper is
port(
BallX : in vl_logic;
BallY : in vl_logic;
Ball_size : in vl_logic;
BlockX : in vl_logic;
BlockY : in vl_logic;
Block_size : in vl_logic;
DrawX : in vl_logic_vector(9 downto 0);
DrawY : in vl_logic_vector(9 downto 0);
block_ready : in vl_logic_vector(2 downto 0);
Red : out vl_logic_vector(7 downto 0);
Green : out vl_logic_vector(7 downto 0);
Blue : out vl_logic_vector(7 downto 0)
);
end color_mapper;
|
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: BRAM_ROM_SCREEN
-- AUTHORS: Tomáš Bannert <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity BRAM_ROM_SCREEN is
Port (
CLK : in std_logic;
ROM_ADDR : in std_logic_vector(11 downto 0);
ROM_DOUT : out std_logic_vector(8 downto 0)
);
end BRAM_ROM_SCREEN;
architecture FULL of BRAM_ROM_SCREEN is
type rom_t is array (0 to 4095) of std_logic_vector(0 to 8);
constant ROM : rom_t :=
(
-- main screen
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --1.r
"000000000",
"000000000",
"000000000",
"110010100",
"000001100",
"000010100",
"000000000",
"000011100",
"000000000",
"110010100",
"000001100",
"000010100",
"000000000",
"000011100",
"000001100",
"000010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --2.r
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --3.r
"000000000",
"000000000",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"010001100",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"000011100",
"000001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --4.r
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --5.r
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --6.r
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --7.r
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --8.r
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000001100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"000011100",
"000000000",
"000000000",
"000001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --9.r
"000011100",
"000010100",
"000000000",
"110010100",
"000011100",
"000000000",
"110010100",
"000000000",
"000010100",
"000000000",
"000011100",
"000010100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"110010100",
"000000000",
"000010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --10.r
"010001100",
"000000000",
"000001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"100010100",
"000011100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --11.r
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000011100",
"000001100",
"000011100",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000011100",
"000001100",
"000011100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --12.r
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --13.r
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --14.r
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001001100",
"001101100",
"001110100",
"001111100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --15.r
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --16.r
--game screen
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --1.r
"000000000",
"000110100",
"000111100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --2.r
"000000000",
"000101100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000101", -- KOMP0
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --3.r
"000000000",
"000101100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --4.r
"000000000",
"000101100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000110", -- KOMP1
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --5.r
"000000000",
"000101100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --6.r
"000000000",
"000101100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000111", -- KOMP2
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --7.r
"000000000",
"000101100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --8.r
"000000000",
"000101100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000001", -- KOMP3
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --9.r
"000000000",
"000101100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --10.r
"000000000",
"000100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000010", -- KOMP4
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --11.r
"001011100",
"001010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --12.r
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --13.r
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001000100",
"000111100",
"000111100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --14.r
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --15.r
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --16.r
-- win screen
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --1.ř.
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000001100",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --2.ř.
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"110010100",
"000001100",
"000010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --3.ř.
"000000000",
"000000000",
"100010100",
"000011100",
"010010100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --4.ř.
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"100010100",
"000001100",
"000011100",
"000001100",
"010010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --5.ř.
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000001100",
"000000000",
"000000000",
"000000000",
"000001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --6.ř.
"000000000",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --7.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --8.ř.
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000011100",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"110010100",
"000001100",
"000011100",
"000001100",
"000010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --9.ř.
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000011100",
"000010100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --10.ř.
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"100010100",
"000011100",
"000000000",
"100010100",
"000001100",
"010010100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --11.ř.
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --12.ř.
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"110010100",
"000010100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --13.ř.
"000000000",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"000000000",
"100010100",
"000011100",
"000001100",
"010010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --14.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --15.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --16.r
-- lose screen
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000011100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --1.ř.
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000001100",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --2.ř.
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"100010100",
"010001100",
"000010100",
"110010100",
"000001100",
"000010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --3.ř.
"000000000",
"000000000",
"100010100",
"000011100",
"010010100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"100010100",
"000001100",
"010010100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --4.ř.
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000001100",
"000000000",
"000000000",
"110010100",
"010010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --5.ř.
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000001100",
"000000000",
"000000000",
"000000000",
"000001100",
"000000000",
"000000000",
"000000000",
"000000000",
"110010100",
"000001100",
"010010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --6.ř.
"000000000",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"000000000",
"000000000",
"100010100",
"000001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --7.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --8.ř.
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000001100",
"000000000",
"000000000",
"000000000",
"000001100",
"000001100",
"000000000",
"000011100",
"000001100",
"000010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --9.ř.
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --10.ř.
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000001100",
"000000000",
"000000000",
"000011100",
"000001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --11.ř.
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --12.ř.
"000000000",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"000000000",
"000001100",
"000000000",
"000000000",
"000001100",
"000001100",
"000000000",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --13.ř.
"000000000",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --14.r.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --15.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --16.ř.
-- lvl2
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --1.ř.
"010001100",
"000000000",
"000000000",
"000000000",
"000011100",
"000001100",
"000010100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000011100",
"000001100",
"000010100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --2.ř.
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --3.ř.
"010001100",
"000000000",
"000000000",
"000000000",
"000011100",
"000001100",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000011100",
"000001100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --4.ř.
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --5.ř.
"000011100",
"000001100",
"010010100",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --6.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --7.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --8.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"001100100",
"001100100",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --9.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --10.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --11.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --12.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --13.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --14.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001001100",
"001101100",
"001110100",
"001111100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --15.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --16.ř.
-- lvl3
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --1.ř.
"010001100",
"000000000",
"000000000",
"000000000",
"000011100",
"000001100",
"000010100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000011100",
"000001100",
"000010100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --2.ř.
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --3.ř.
"010001100",
"000000000",
"000000000",
"000000000",
"000011100",
"000001100",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000011100",
"000001100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --4.ř.
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --5.ř.
"000011100",
"000001100",
"010010100",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --6.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --7.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --8.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"001100100",
"001100100",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --9.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --10.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --11.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --12.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --13.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"001100100",
"001100100",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --14.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001001100",
"001101100",
"001110100",
"001111100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --15.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --16.ř.
-- lvl4
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --1.ř.
"010001100",
"000000000",
"000000000",
"000000000",
"000011100",
"000001100",
"000010100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000011100",
"000001100",
"000010100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --2.ř.
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --3.ř.
"010001100",
"000000000",
"000000000",
"000000000",
"000011100",
"000001100",
"000000000",
"000000000",
"010001100",
"000000000",
"010001100",
"000000000",
"000011100",
"000001100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --4.ř.
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --5.ř.
"000011100",
"000001100",
"010010100",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"000000000",
"010001100",
"000000000",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"000011100",
"000001100",
"010010100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --6.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --7.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --8.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --9.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --10.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"000000000",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --11.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"000000000",
"000000000",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --12.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"001100100",
"001100100",
"001100100",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --13.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001100100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --14.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"001001100",
"001101100",
"001110100",
"001111100",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --15.ř.
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000",
"000000000", --16.ř.
others => (others => '0')
);
begin
process (CLK)
begin
if (rising_edge(CLK)) then
ROM_DOUT <= ROM(to_integer(unsigned(ROM_ADDR)));
end if;
end process;
end FULL;
|
-- 2-input single-bit multiplexer
-- this circuit takes two single-bit inputs and selects one to output based on a select signal
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_2_single_bit is
port (
-- inputs
in_signal_0 : in std_logic;
in_signal_1 : in std_logic;
-- select signal
input_select : in std_logic;
-- output
out_signal : out std_logic
);
end entity mux_2_single_bit;
architecture mux_2_single_bit_arch of mux_2_single_bit is
-- this circuit requires no internal signals
begin
-- design implementation
mux : process(in_signal_0, in_signal_1, input_select)
begin
-- select 0 is input 0
if input_select = '0' then
out_signal <= in_signal_0;
-- select 1 is input 1
elsif input_select = '1' then
out_signal <= in_signal_1;
-- otherwise invalid select signal, output 0
else
out_signal <= '0';
end if;
end process mux;
end architecture mux_2_single_bit_arch; |
-- Projeto gerado via script.
-- Data: Sáb,31/12/2011-01:19:07
-- Autor: rogerio
-- Comentario: Descrição da Entidade: or2.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity or2 is
port (a, b: in std_logic; y: out std_logic);
end or2;
architecture logica of or2 is
begin
-- Comandos.
y <= a or b;
end logica;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: iface
-- File: iface.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Package with type declarations for module interconnections
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
package iface is
subtype clk_type is std_logic;
------------------------------------------------------------------------------
-- Add I/Os for custom peripherals in the records below
------------------------------------------------------------------------------
-- peripheral inputs
type io_in_type is record
piol : std_logic_vector(15 downto 0); -- I/O port inputs
pci_arb_req_n : std_logic_vector(0 to 3);
end record;
-- peripheral outputs
type io_out_type is record
piol : std_logic_vector(15 downto 0); -- I/O port outputs
piodir : std_logic_vector(15 downto 0); -- I/O port direction
errorn : std_logic; -- CPU in error mode
wdog : std_logic; -- watchdog output
pci_arb_gnt_n : std_logic_vector(0 to 3);
end record;
------------------------------------------------------------------------------
-- IU register file signals
type rf_in_type is record
rd1addr : std_logic_vector(RABITS-1 downto 0); -- read address 1
rd2addr : std_logic_vector(RABITS-1 downto 0); -- read address 2
wraddr : std_logic_vector(RABITS-1 downto 0); -- write address
wrdata : std_logic_vector(RDBITS-1 downto 0); -- write data
ren1 : std_logic; -- read 1 enable
ren2 : std_logic; -- read 2 enable
wren : std_logic; -- write enable
end record;
type rf_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
-- co-processor register file signals
type rf_cp_in_type is record
rd1addr : std_logic_vector(3 downto 0); -- read address 1
rd2addr : std_logic_vector(3 downto 0); -- read address 2
wraddr : std_logic_vector(3 downto 0); -- write address
wrdata : std_logic_vector(RDBITS-1 downto 0); -- write data
ren1 : std_logic; -- read 1 enable
ren2 : std_logic; -- read 2 enable
wren : std_logic; -- write enable
end record;
type rf_cp_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
-- instruction cache diagnostic access inputs
type icdiag_in_type is record
addr : std_logic_vector(31 downto 0); -- memory stage address
enable : std_logic;
read : std_logic;
tag : std_logic;
flush : std_logic;
end record;
-- data cache controller inputs
type dcache_in_type is record
asi : std_logic_vector(7 downto 0); -- ASI for load/store
maddress : std_logic_vector(31 downto 0); -- memory stage address
eaddress : std_logic_vector(31 downto 0); -- execute stage address
edata : std_logic_vector(31 downto 0); -- execute stage data
size : std_logic_vector(1 downto 0);
signed : std_logic;
enaddr : std_logic;
eenaddr : std_logic;
nullify : std_logic;
lock : std_logic;
read : std_logic;
write : std_logic;
flush : std_logic;
dsuen : std_logic;
end record;
-- data cache controller outputs
type dcache_out_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
mexc : std_logic; -- memory exception
hold : std_logic;
mds : std_logic;
werr : std_logic; -- memory write error
icdiag : icdiag_in_type;
dsudata : std_logic_vector(31 downto 0);
end record;
type icache_in_type is record
rpc : std_logic_vector(31 downto PCLOW); -- raw address (npc)
fpc : std_logic_vector(31 downto PCLOW); -- latched address (fpc)
dpc : std_logic_vector(31 downto PCLOW); -- latched address (dpc)
rbranch : std_logic; -- Instruction branch
fbranch : std_logic; -- Instruction branch
nullify : std_logic; -- instruction nullify
su : std_logic; -- super-user
flush : std_logic; -- flush icache
end record;
type icache_out_type is record
data : std_logic_vector(31 downto 0);
exception : std_logic;
hold : std_logic;
flush : std_logic; -- flush in progress
diagrdy : std_logic; -- diagnostic access ready
diagdata : std_logic_vector(31 downto 0); -- diagnostic data
mds : std_logic; -- memory data strobe
end record;
type memory_ic_in_type is record
address : std_logic_vector(31 downto 0); -- memory address
burst : std_logic; -- burst request
req : std_logic; -- memory cycle request
su : std_logic; -- supervisor address space
flush : std_logic; -- flush in progress
end record;
type memory_ic_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
grant : std_logic; --
retry : std_logic; --
mexc : std_logic; -- memory exception
burst : std_logic; -- memory burst enable
ics : std_logic_vector(1 downto 0); -- icache state (from CCR)
cache : std_logic; -- cacheable data
end record;
type memory_dc_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
asi : std_logic_vector(3 downto 0); -- ASI for load/store
size : std_logic_vector(1 downto 0);
burst : std_logic;
read : std_logic;
req : std_logic;
flush : std_logic; -- flush in progress
lock : std_logic;
su : std_logic;
end record;
type memory_dc_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
grant : std_logic; --
retry : std_logic; --
mexc : std_logic; -- memory exception
werr : std_logic; -- memory write error
dcs : std_logic_vector(1 downto 0);
iflush : std_logic; -- flush icache (from CCR)
dflush : std_logic; -- flush dcache (from CCR)
cache : std_logic; -- cacheable data
dsnoop : std_logic; -- snoop enable
ba : std_logic; -- bus active (used for snooping)
bg : std_logic; -- bus grant (used for snooping)
end record;
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
end record;
type memory_out_type is record
address : std_logic_vector(27 downto 0);
data : std_logic_vector(31 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
iosn : std_logic;
romsn : std_logic_vector(1 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
read : std_logic;
end record;
type pio_in_type is record
piol : std_logic_vector(15 downto 0);
pioh : std_logic_vector(15 downto 0);
end record;
type pio_out_type is record
irq : std_logic_vector(3 downto 0);
piol : std_logic_vector(31 downto 0);
piodir : std_logic_vector(17 downto 0);
io8lsb : std_logic_vector(7 downto 0);
rxd : std_logic_vector(1 downto 0);
ctsn : std_logic_vector(1 downto 0);
wrio : std_logic;
end record;
type wprot_out_type is record
wprothit : std_logic;
end record;
type ahbstat_out_type is record
ahberr : std_logic;
end record;
type mctrl_out_type is record
pioh : std_logic_vector(15 downto 0);
end record;
type itram_in_type is record
tag : std_logic_vector(ITAG_BITS - ILINE_SIZE - 1 downto 0);
valid : std_logic_vector(ILINE_SIZE -1 downto 0);
enable : std_logic;
write : std_logic;
end record;
type itram_out_type is record
tag : std_logic_vector(ITAG_BITS - ILINE_SIZE -1 downto 0);
valid : std_logic_vector(ILINE_SIZE -1 downto 0);
end record;
type idram_in_type is record
address : std_logic_vector((IOFFSET_BITS + ILINE_BITS -1) downto 0);
data : std_logic_vector(31 downto 0);
enable : std_logic;
write : std_logic;
end record;
type idram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type dtram_in_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE - 1 downto 0);
valid : std_logic_vector(DLINE_SIZE -1 downto 0);
enable : std_logic;
write : std_logic;
end record;
type dtram_out_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE -1 downto 0);
valid : std_logic_vector(DLINE_SIZE -1 downto 0);
end record;
type dtramsn_in_type is record
enable : std_logic;
write : std_logic;
address : std_logic_vector((DOFFSET_BITS-1) downto 0);
end record;
type dtramsn_out_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE -1 downto 0);
end record;
type ddram_in_type is record
address : std_logic_vector((DOFFSET_BITS + DLINE_BITS -1) downto 0);
data : std_logic_vector(31 downto 0);
enable : std_logic;
write : std_logic;
end record;
type ddram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type icram_in_type is record
itramin : itram_in_type;
idramin : idram_in_type;
end record;
type icram_out_type is record
itramout : itram_out_type;
idramout : idram_out_type;
end record;
type dcram_in_type is record
dtramin : dtram_in_type;
ddramin : ddram_in_type;
dtraminsn : dtramsn_in_type;
end record;
type dcram_out_type is record
dtramout : dtram_out_type;
ddramout : ddram_out_type;
dtramoutsn : dtramsn_out_type;
end record;
type cram_in_type is record
icramin : icram_in_type;
dcramin : dcram_in_type;
end record;
type cram_out_type is record
icramout : icram_out_type;
dcramout : dcram_out_type;
end record;
type irq_in_type is record
irq : std_logic_vector(15 downto 1);
intack : std_logic;
irl : std_logic_vector(3 downto 0);
end record;
type irq_out_type is record
irl : std_logic_vector(3 downto 0);
end record;
type irq2_in_type is record
irq : std_logic_vector(31 downto 0);
end record;
type irq2_out_type is record
irq : std_logic;
end record;
type timers_out_type is record
irq : std_logic_vector(1 downto 0);
tick : std_logic;
wdog : std_logic;
end record;
type uart_in_type is record
rxd : std_logic;
ctsn : std_logic;
scaler : std_logic_vector(7 downto 0);
end record;
type uart_out_type is record
rxen : std_logic;
txen : std_logic;
flow : std_logic;
irq : std_logic;
rtsn : std_logic;
txd : std_logic;
end record;
type clkgen_in_type is record
iholdn : std_logic; -- Instruction hold
imdsn : std_logic; -- Instruction memory data strobe
dholdn : std_logic; -- Data hold
dmdsn : std_logic; -- Data memory data strobe
fpuholdn : std_logic; -- FPU/CP busy
end record;
type clkgen_out_type is record
clk : clk_type; -- Common clock
clkn : clk_type; -- inverted clock
iuclk : clk_type; -- Processor clock
dclk : clk_type; -- Data latch clock
iclk : clk_type; -- Instruction latch clock
pciclk : clk_type; -- PCI config-block clock
holdn : std_logic; -- Instruction latch clock
end record;
-- iu pipeline control type (defined here to be visible to debug and coprocessor)
type pipeline_control_type is record
inst : std_logic_vector(31 downto 0); -- instruction word
pc : std_logic_vector(31 downto PCLOW); -- program counter
annul : std_logic; -- instruction annul
cnt : std_logic_vector(1 downto 0); -- cycle number (multi-cycle inst)
ld : std_logic; -- load cycle
pv : std_logic; -- PC valid
rett : std_logic; -- RETT indicator
trap : std_logic; -- trap pending flag
tt : std_logic_vector(5 downto 0); -- trap type
rd : std_logic_vector(RABITS-1 downto 0); -- destination register address
end record;
-- Stucture for FPU/CP control
type cp_in_type is record
flush : std_logic; -- pipeline flush
exack : std_logic; -- CP exception acknowledge
dannul : std_logic; -- decode stage annul
dtrap : std_logic; -- decode stage trap
dcnt : std_logic_vector(1 downto 0); -- decode stage cycle counter
dinst : std_logic_vector(31 downto 0); -- decode stage instruction
ex : pipeline_control_type; -- iu pipeline ctrl (ex)
me : pipeline_control_type; -- iu pipeline ctrl (me)
wr : pipeline_control_type; -- iu pipeline ctrl (wr)
lddata : std_logic_vector(31 downto 0); -- load data
end record;
type cp_out_type is record
data : std_logic_vector(31 downto 0); -- store data
exc : std_logic; -- CP exception
cc : std_logic_vector(1 downto 0); -- CP condition codes
ccv : std_logic; -- CP condition codes valid
holdn : std_logic; -- CP pipeline hold
ldlock : std_logic; -- CP load/store interlock
end record;
-- iu debug port
type iu_debug_in_type is record
dsuen : std_logic; -- DSU enable
dbreak : std_logic; -- debug break-in
btrapa : std_logic; -- break on IU trap
btrape : std_logic; -- break on IU trap
berror : std_logic; -- break on IU error mode
bwatch : std_logic; -- break on IU watchpoint
bsoft : std_logic; -- break on software breakpoint (TA 1)
rerror : std_logic; -- reset processor error mode
step : std_logic; -- single step
denable : std_logic; -- diagnostic register access enable
dwrite : std_logic; -- read/write
daddr : std_logic_vector(20 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
end record;
type iu_debug_out_type is record
clk : std_logic;
rst : std_logic;
holdn : std_logic;
ex : pipeline_control_type;
me : pipeline_control_type;
wr : pipeline_control_type;
write_reg : std_logic;
mresult : std_logic_vector(31 downto 0);
result : std_logic_vector(31 downto 0);
trap : std_logic;
error : std_logic;
dmode : std_logic;
dmode2 : std_logic;
vdmode : std_logic;
dbreak : std_logic;
tt : std_logic_vector(7 downto 0);
psrtt : std_logic_vector(7 downto 0);
psrpil : std_logic_vector(3 downto 0);
diagrdy : std_logic;
ddata : std_logic_vector(31 downto 0); -- diagnostic data
end record;
type iu_in_type is record
irl : std_logic_vector(3 downto 0); -- interrupt request level
debug : iu_debug_in_type;
end record;
type iu_out_type is record
error : std_logic;
intack : std_logic;
irqvec : std_logic_vector(3 downto 0);
ipend : std_logic;
debug : iu_debug_out_type;
end record;
-- Meiko FPU interface
type fpu_in_type is record
FpInst : std_logic_vector(9 downto 0);
FpOp : std_logic;
FpLd : std_logic;
Reset : std_logic;
fprf_dout1 : std_logic_vector(63 downto 0);
fprf_dout2 : std_logic_vector(63 downto 0);
RoundingMode : std_logic_vector(1 downto 0);
ss_scan_mode : std_logic;
fp_ctl_scan_in : std_logic;
fpuholdn : std_logic;
end record;
type fpu_out_type is record
FpBusy : std_logic;
FracResult : std_logic_vector(54 downto 3);
ExpResult : std_logic_vector(10 downto 0);
SignResult : std_logic;
SNnotDB : std_logic;
Excep : std_logic_vector(5 downto 0);
ConditionCodes : std_logic_vector(1 downto 0);
fp_ctl_scan_out : std_logic;
end record;
type cp_unit_in_type is record -- coprocessor execution unit input
op1 : std_logic_vector (63 downto 0); -- operand 1
op2 : std_logic_vector (63 downto 0); -- operand 2
opcode : std_logic_vector (9 downto 0); -- opcode
start : std_logic; -- start
load : std_logic; -- load operands
flush : std_logic; -- cancel operation
end record;
type cp_unit_out_type is record -- coprocessor execution unit output
res : std_logic_vector (63 downto 0); -- result
cc : std_logic_vector (1 downto 0); -- condition codes
exc : std_logic_vector (5 downto 0); -- exception
busy : std_logic; -- eu busy
end record;
type rst_type is record
syncrst : std_logic; -- synchronous reset
rawrst : std_logic; -- asynchronous reset
end record;
-- pci_[in|out]_type groups all EXTERNAL pci ports in unidirectional form
-- as well as the required enable signals for the pads
type pci_in_type is record
pci_rst_in_n : std_logic;
pci_clk_in : std_logic;
pci_gnt_in_n : std_logic;
pci_idsel_in : std_logic;
pci_adin : std_logic_vector(31 downto 0);
pci_cbein_n : std_logic_vector(3 downto 0);
pci_frame_in_n : std_logic;
pci_irdy_in_n : std_logic;
pci_trdy_in_n : std_logic;
pci_devsel_in_n : std_logic;
pci_stop_in_n : std_logic;
pci_lock_in_n : std_logic;
pci_perr_in_n : std_logic;
pci_serr_in_n : std_logic;
pci_par_in : std_logic;
pci_host : std_logic;
pci_66 : std_logic;
pme_status : std_logic;
end record;
type pci_out_type is record
pci_aden_n : std_logic_vector(31 downto 0);
pci_cbe0_en_n : std_logic;
pci_cbe1_en_n : std_logic;
pci_cbe2_en_n : std_logic;
pci_cbe3_en_n : std_logic;
pci_frame_en_n : std_logic;
pci_irdy_en_n : std_logic;
pci_ctrl_en_n : std_logic;
pci_perr_en_n : std_logic;
pci_par_en_n : std_logic;
pci_req_en_n : std_logic;
pci_lock_en_n : std_logic;
pci_serr_en_n : std_logic;
pci_int_en_n : std_logic;
pci_req_out_n : std_logic;
pci_adout : std_logic_vector(31 downto 0);
pci_cbeout_n : std_logic_vector(3 downto 0);
pci_frame_out_n : std_logic;
pci_irdy_out_n : std_logic;
pci_trdy_out_n : std_logic;
pci_devsel_out_n : std_logic;
pci_stop_out_n : std_logic;
pci_perr_out_n : std_logic;
pci_serr_out_n : std_logic;
pci_par_out : std_logic;
pci_lock_out_n : std_logic;
power_state : std_logic_vector(1 downto 0);
pme_enable : std_logic;
pme_clear : std_logic;
pci_int_out_n : std_logic;
end record;
type div_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
y : std_logic_vector(32 downto 0); -- Y (MSB divident)
flush : std_logic;
signed : std_logic;
start : std_logic;
end record;
type div_out_type is record
ready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(31 downto 0); -- div result
end record;
type mul_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
y : std_logic_vector(7 downto 0); -- Y (MSB MAC register)
asr18 : std_logic_vector(31 downto 0); -- LSB MAC register
end record;
type mul_out_type is record
ready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(63 downto 0); -- mul result
end record;
type ahb_dma_in_type is record
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(31 downto 0);
start : std_logic;
burst : std_logic;
write : std_logic;
size : std_logic_vector(1 downto 0);
end record;
type ahb_dma_out_type is record
start : std_logic;
active : std_logic;
ready : std_logic;
retry : std_logic;
mexc : std_logic;
haddr : std_logic_vector(9 downto 0);
rdata : std_logic_vector(31 downto 0);
end record;
type actpci_be_in_type is record
mem_ad_int : std_logic_vector(31 downto 0);
mem_data : std_logic_vector(31 downto 0);
dp_done : std_logic;
dp_start : std_logic;
rd_be_now : std_logic;
rd_cyc : std_logic;
wr_be_now : std_logic_vector(3 downto 0);
wr_cyc : std_logic;
bar0_mem_cyc : std_logic;
busy : std_logic_vector(3 downto 0);
master_active : std_logic;
be_gnt : std_logic;
end record;
type actpci_be_out_type is record
rd_be_rdy : std_logic;
wr_be_rdy : std_logic;
error : std_logic;
busy : std_logic;
mem_data : std_logic_vector(31 downto 0);
cs_controln : std_logic;
rd_controln : std_logic;
wr_controln : std_logic;
control_add : std_logic_vector(1 downto 0);
ext_intn : std_logic;
be_req : std_logic;
end record;
type dsu_in_type is record
dsuen : std_logic;
dsubre : std_logic;
end record;
type dsu_out_type is record
dsuact : std_logic;
ntrace : std_logic;
freezetime : std_logic;
lresp : std_logic;
dresp : std_logic;
dsuen : std_logic;
dsubre : std_logic;
end record;
type dcom_in_type is record
dsurx : std_logic;
end record;
type dcom_out_type is record
dsutx : std_logic;
end record;
type dsuif_in_type is record
dsui : dsu_in_type;
dcomi : dcom_in_type;
end record;
type dsuif_out_type is record
dsuo : dsu_out_type;
dcomo : dcom_out_type;
end record;
type dcom_uart_in_type is record
rxd : std_logic;
read : std_logic;
write : std_logic;
data : std_logic_vector(7 downto 0);
dsuen : std_logic;
end record;
type dcom_uart_out_type is record
txd : std_logic;
dready : std_logic;
tsempty : std_logic;
thempty : std_logic;
lock : std_logic;
enable : std_logic;
data : std_logic_vector(7 downto 0);
end record;
type tracebuf_in_type is record
addr : std_logic_vector(TBUFABITS downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
type dsumem_in_type is record
pbufi : tracebuf_in_type;
abufi : tracebuf_in_type;
end record;
type dsumem_out_type is record
pbufo : tracebuf_out_type;
abufo : tracebuf_out_type;
end record;
-- -----------------------------------------------
type ddm_in_type is record -- added for DDM
button0 : std_logic;
button1 : std_logic;
button2 : std_logic;
button3 : std_logic;
audioin : std_logic;
end record;
type ddm_out_type is record
digit0 : std_logic_vector(6 downto 0);
digit1 : std_logic_vector(6 downto 0);
audioout : std_logic;
lr_out : std_logic;
shift_clk : std_logic;
mclk : std_logic;
dispen : std_logic;
end record;
-- -----------------------------------------------
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: iface
-- File: iface.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Package with type declarations for module interconnections
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.config.all;
use work.sparcv8.all;
package iface is
subtype clk_type is std_logic;
------------------------------------------------------------------------------
-- Add I/Os for custom peripherals in the records below
------------------------------------------------------------------------------
-- peripheral inputs
type io_in_type is record
piol : std_logic_vector(15 downto 0); -- I/O port inputs
pci_arb_req_n : std_logic_vector(0 to 3);
end record;
-- peripheral outputs
type io_out_type is record
piol : std_logic_vector(15 downto 0); -- I/O port outputs
piodir : std_logic_vector(15 downto 0); -- I/O port direction
errorn : std_logic; -- CPU in error mode
wdog : std_logic; -- watchdog output
pci_arb_gnt_n : std_logic_vector(0 to 3);
end record;
------------------------------------------------------------------------------
-- IU register file signals
type rf_in_type is record
rd1addr : std_logic_vector(RABITS-1 downto 0); -- read address 1
rd2addr : std_logic_vector(RABITS-1 downto 0); -- read address 2
wraddr : std_logic_vector(RABITS-1 downto 0); -- write address
wrdata : std_logic_vector(RDBITS-1 downto 0); -- write data
ren1 : std_logic; -- read 1 enable
ren2 : std_logic; -- read 2 enable
wren : std_logic; -- write enable
end record;
type rf_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
-- co-processor register file signals
type rf_cp_in_type is record
rd1addr : std_logic_vector(3 downto 0); -- read address 1
rd2addr : std_logic_vector(3 downto 0); -- read address 2
wraddr : std_logic_vector(3 downto 0); -- write address
wrdata : std_logic_vector(RDBITS-1 downto 0); -- write data
ren1 : std_logic; -- read 1 enable
ren2 : std_logic; -- read 2 enable
wren : std_logic; -- write enable
end record;
type rf_cp_out_type is record
data1 : std_logic_vector(RDBITS-1 downto 0); -- read data 1
data2 : std_logic_vector(RDBITS-1 downto 0); -- read data 2
end record;
-- instruction cache diagnostic access inputs
type icdiag_in_type is record
addr : std_logic_vector(31 downto 0); -- memory stage address
enable : std_logic;
read : std_logic;
tag : std_logic;
flush : std_logic;
end record;
-- data cache controller inputs
type dcache_in_type is record
asi : std_logic_vector(7 downto 0); -- ASI for load/store
maddress : std_logic_vector(31 downto 0); -- memory stage address
eaddress : std_logic_vector(31 downto 0); -- execute stage address
edata : std_logic_vector(31 downto 0); -- execute stage data
size : std_logic_vector(1 downto 0);
signed : std_logic;
enaddr : std_logic;
eenaddr : std_logic;
nullify : std_logic;
lock : std_logic;
read : std_logic;
write : std_logic;
flush : std_logic;
dsuen : std_logic;
end record;
-- data cache controller outputs
type dcache_out_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
mexc : std_logic; -- memory exception
hold : std_logic;
mds : std_logic;
werr : std_logic; -- memory write error
icdiag : icdiag_in_type;
dsudata : std_logic_vector(31 downto 0);
end record;
type icache_in_type is record
rpc : std_logic_vector(31 downto PCLOW); -- raw address (npc)
fpc : std_logic_vector(31 downto PCLOW); -- latched address (fpc)
dpc : std_logic_vector(31 downto PCLOW); -- latched address (dpc)
rbranch : std_logic; -- Instruction branch
fbranch : std_logic; -- Instruction branch
nullify : std_logic; -- instruction nullify
su : std_logic; -- super-user
flush : std_logic; -- flush icache
end record;
type icache_out_type is record
data : std_logic_vector(31 downto 0);
exception : std_logic;
hold : std_logic;
flush : std_logic; -- flush in progress
diagrdy : std_logic; -- diagnostic access ready
diagdata : std_logic_vector(31 downto 0); -- diagnostic data
mds : std_logic; -- memory data strobe
end record;
type memory_ic_in_type is record
address : std_logic_vector(31 downto 0); -- memory address
burst : std_logic; -- burst request
req : std_logic; -- memory cycle request
su : std_logic; -- supervisor address space
flush : std_logic; -- flush in progress
end record;
type memory_ic_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
grant : std_logic; --
retry : std_logic; --
mexc : std_logic; -- memory exception
burst : std_logic; -- memory burst enable
ics : std_logic_vector(1 downto 0); -- icache state (from CCR)
cache : std_logic; -- cacheable data
end record;
type memory_dc_in_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
asi : std_logic_vector(3 downto 0); -- ASI for load/store
size : std_logic_vector(1 downto 0);
burst : std_logic;
read : std_logic;
req : std_logic;
flush : std_logic; -- flush in progress
lock : std_logic;
su : std_logic;
end record;
type memory_dc_out_type is record
data : std_logic_vector(31 downto 0); -- memory data
ready : std_logic; -- cycle ready
grant : std_logic; --
retry : std_logic; --
mexc : std_logic; -- memory exception
werr : std_logic; -- memory write error
dcs : std_logic_vector(1 downto 0);
iflush : std_logic; -- flush icache (from CCR)
dflush : std_logic; -- flush dcache (from CCR)
cache : std_logic; -- cacheable data
dsnoop : std_logic; -- snoop enable
ba : std_logic; -- bus active (used for snooping)
bg : std_logic; -- bus grant (used for snooping)
end record;
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
end record;
type memory_out_type is record
address : std_logic_vector(27 downto 0);
data : std_logic_vector(31 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
iosn : std_logic;
romsn : std_logic_vector(1 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
read : std_logic;
end record;
type pio_in_type is record
piol : std_logic_vector(15 downto 0);
pioh : std_logic_vector(15 downto 0);
end record;
type pio_out_type is record
irq : std_logic_vector(3 downto 0);
piol : std_logic_vector(31 downto 0);
piodir : std_logic_vector(17 downto 0);
io8lsb : std_logic_vector(7 downto 0);
rxd : std_logic_vector(1 downto 0);
ctsn : std_logic_vector(1 downto 0);
wrio : std_logic;
end record;
type wprot_out_type is record
wprothit : std_logic;
end record;
type ahbstat_out_type is record
ahberr : std_logic;
end record;
type mctrl_out_type is record
pioh : std_logic_vector(15 downto 0);
end record;
type itram_in_type is record
tag : std_logic_vector(ITAG_BITS - ILINE_SIZE - 1 downto 0);
valid : std_logic_vector(ILINE_SIZE -1 downto 0);
enable : std_logic;
write : std_logic;
end record;
type itram_out_type is record
tag : std_logic_vector(ITAG_BITS - ILINE_SIZE -1 downto 0);
valid : std_logic_vector(ILINE_SIZE -1 downto 0);
end record;
type idram_in_type is record
address : std_logic_vector((IOFFSET_BITS + ILINE_BITS -1) downto 0);
data : std_logic_vector(31 downto 0);
enable : std_logic;
write : std_logic;
end record;
type idram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type dtram_in_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE - 1 downto 0);
valid : std_logic_vector(DLINE_SIZE -1 downto 0);
enable : std_logic;
write : std_logic;
end record;
type dtram_out_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE -1 downto 0);
valid : std_logic_vector(DLINE_SIZE -1 downto 0);
end record;
type dtramsn_in_type is record
enable : std_logic;
write : std_logic;
address : std_logic_vector((DOFFSET_BITS-1) downto 0);
end record;
type dtramsn_out_type is record
tag : std_logic_vector(DTAG_BITS - DLINE_SIZE -1 downto 0);
end record;
type ddram_in_type is record
address : std_logic_vector((DOFFSET_BITS + DLINE_BITS -1) downto 0);
data : std_logic_vector(31 downto 0);
enable : std_logic;
write : std_logic;
end record;
type ddram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type icram_in_type is record
itramin : itram_in_type;
idramin : idram_in_type;
end record;
type icram_out_type is record
itramout : itram_out_type;
idramout : idram_out_type;
end record;
type dcram_in_type is record
dtramin : dtram_in_type;
ddramin : ddram_in_type;
dtraminsn : dtramsn_in_type;
end record;
type dcram_out_type is record
dtramout : dtram_out_type;
ddramout : ddram_out_type;
dtramoutsn : dtramsn_out_type;
end record;
type cram_in_type is record
icramin : icram_in_type;
dcramin : dcram_in_type;
end record;
type cram_out_type is record
icramout : icram_out_type;
dcramout : dcram_out_type;
end record;
type irq_in_type is record
irq : std_logic_vector(15 downto 1);
intack : std_logic;
irl : std_logic_vector(3 downto 0);
end record;
type irq_out_type is record
irl : std_logic_vector(3 downto 0);
end record;
type irq2_in_type is record
irq : std_logic_vector(31 downto 0);
end record;
type irq2_out_type is record
irq : std_logic;
end record;
type timers_out_type is record
irq : std_logic_vector(1 downto 0);
tick : std_logic;
wdog : std_logic;
end record;
type uart_in_type is record
rxd : std_logic;
ctsn : std_logic;
scaler : std_logic_vector(7 downto 0);
end record;
type uart_out_type is record
rxen : std_logic;
txen : std_logic;
flow : std_logic;
irq : std_logic;
rtsn : std_logic;
txd : std_logic;
end record;
type clkgen_in_type is record
iholdn : std_logic; -- Instruction hold
imdsn : std_logic; -- Instruction memory data strobe
dholdn : std_logic; -- Data hold
dmdsn : std_logic; -- Data memory data strobe
fpuholdn : std_logic; -- FPU/CP busy
end record;
type clkgen_out_type is record
clk : clk_type; -- Common clock
clkn : clk_type; -- inverted clock
iuclk : clk_type; -- Processor clock
dclk : clk_type; -- Data latch clock
iclk : clk_type; -- Instruction latch clock
pciclk : clk_type; -- PCI config-block clock
holdn : std_logic; -- Instruction latch clock
end record;
-- iu pipeline control type (defined here to be visible to debug and coprocessor)
type pipeline_control_type is record
inst : std_logic_vector(31 downto 0); -- instruction word
pc : std_logic_vector(31 downto PCLOW); -- program counter
annul : std_logic; -- instruction annul
cnt : std_logic_vector(1 downto 0); -- cycle number (multi-cycle inst)
ld : std_logic; -- load cycle
pv : std_logic; -- PC valid
rett : std_logic; -- RETT indicator
trap : std_logic; -- trap pending flag
tt : std_logic_vector(5 downto 0); -- trap type
rd : std_logic_vector(RABITS-1 downto 0); -- destination register address
end record;
-- Stucture for FPU/CP control
type cp_in_type is record
flush : std_logic; -- pipeline flush
exack : std_logic; -- CP exception acknowledge
dannul : std_logic; -- decode stage annul
dtrap : std_logic; -- decode stage trap
dcnt : std_logic_vector(1 downto 0); -- decode stage cycle counter
dinst : std_logic_vector(31 downto 0); -- decode stage instruction
ex : pipeline_control_type; -- iu pipeline ctrl (ex)
me : pipeline_control_type; -- iu pipeline ctrl (me)
wr : pipeline_control_type; -- iu pipeline ctrl (wr)
lddata : std_logic_vector(31 downto 0); -- load data
end record;
type cp_out_type is record
data : std_logic_vector(31 downto 0); -- store data
exc : std_logic; -- CP exception
cc : std_logic_vector(1 downto 0); -- CP condition codes
ccv : std_logic; -- CP condition codes valid
holdn : std_logic; -- CP pipeline hold
ldlock : std_logic; -- CP load/store interlock
end record;
-- iu debug port
type iu_debug_in_type is record
dsuen : std_logic; -- DSU enable
dbreak : std_logic; -- debug break-in
btrapa : std_logic; -- break on IU trap
btrape : std_logic; -- break on IU trap
berror : std_logic; -- break on IU error mode
bwatch : std_logic; -- break on IU watchpoint
bsoft : std_logic; -- break on software breakpoint (TA 1)
rerror : std_logic; -- reset processor error mode
step : std_logic; -- single step
denable : std_logic; -- diagnostic register access enable
dwrite : std_logic; -- read/write
daddr : std_logic_vector(20 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
end record;
type iu_debug_out_type is record
clk : std_logic;
rst : std_logic;
holdn : std_logic;
ex : pipeline_control_type;
me : pipeline_control_type;
wr : pipeline_control_type;
write_reg : std_logic;
mresult : std_logic_vector(31 downto 0);
result : std_logic_vector(31 downto 0);
trap : std_logic;
error : std_logic;
dmode : std_logic;
dmode2 : std_logic;
vdmode : std_logic;
dbreak : std_logic;
tt : std_logic_vector(7 downto 0);
psrtt : std_logic_vector(7 downto 0);
psrpil : std_logic_vector(3 downto 0);
diagrdy : std_logic;
ddata : std_logic_vector(31 downto 0); -- diagnostic data
end record;
type iu_in_type is record
irl : std_logic_vector(3 downto 0); -- interrupt request level
debug : iu_debug_in_type;
end record;
type iu_out_type is record
error : std_logic;
intack : std_logic;
irqvec : std_logic_vector(3 downto 0);
ipend : std_logic;
debug : iu_debug_out_type;
end record;
-- Meiko FPU interface
type fpu_in_type is record
FpInst : std_logic_vector(9 downto 0);
FpOp : std_logic;
FpLd : std_logic;
Reset : std_logic;
fprf_dout1 : std_logic_vector(63 downto 0);
fprf_dout2 : std_logic_vector(63 downto 0);
RoundingMode : std_logic_vector(1 downto 0);
ss_scan_mode : std_logic;
fp_ctl_scan_in : std_logic;
fpuholdn : std_logic;
end record;
type fpu_out_type is record
FpBusy : std_logic;
FracResult : std_logic_vector(54 downto 3);
ExpResult : std_logic_vector(10 downto 0);
SignResult : std_logic;
SNnotDB : std_logic;
Excep : std_logic_vector(5 downto 0);
ConditionCodes : std_logic_vector(1 downto 0);
fp_ctl_scan_out : std_logic;
end record;
type cp_unit_in_type is record -- coprocessor execution unit input
op1 : std_logic_vector (63 downto 0); -- operand 1
op2 : std_logic_vector (63 downto 0); -- operand 2
opcode : std_logic_vector (9 downto 0); -- opcode
start : std_logic; -- start
load : std_logic; -- load operands
flush : std_logic; -- cancel operation
end record;
type cp_unit_out_type is record -- coprocessor execution unit output
res : std_logic_vector (63 downto 0); -- result
cc : std_logic_vector (1 downto 0); -- condition codes
exc : std_logic_vector (5 downto 0); -- exception
busy : std_logic; -- eu busy
end record;
type rst_type is record
syncrst : std_logic; -- synchronous reset
rawrst : std_logic; -- asynchronous reset
end record;
-- pci_[in|out]_type groups all EXTERNAL pci ports in unidirectional form
-- as well as the required enable signals for the pads
type pci_in_type is record
pci_rst_in_n : std_logic;
pci_clk_in : std_logic;
pci_gnt_in_n : std_logic;
pci_idsel_in : std_logic;
pci_adin : std_logic_vector(31 downto 0);
pci_cbein_n : std_logic_vector(3 downto 0);
pci_frame_in_n : std_logic;
pci_irdy_in_n : std_logic;
pci_trdy_in_n : std_logic;
pci_devsel_in_n : std_logic;
pci_stop_in_n : std_logic;
pci_lock_in_n : std_logic;
pci_perr_in_n : std_logic;
pci_serr_in_n : std_logic;
pci_par_in : std_logic;
pci_host : std_logic;
pci_66 : std_logic;
pme_status : std_logic;
end record;
type pci_out_type is record
pci_aden_n : std_logic_vector(31 downto 0);
pci_cbe0_en_n : std_logic;
pci_cbe1_en_n : std_logic;
pci_cbe2_en_n : std_logic;
pci_cbe3_en_n : std_logic;
pci_frame_en_n : std_logic;
pci_irdy_en_n : std_logic;
pci_ctrl_en_n : std_logic;
pci_perr_en_n : std_logic;
pci_par_en_n : std_logic;
pci_req_en_n : std_logic;
pci_lock_en_n : std_logic;
pci_serr_en_n : std_logic;
pci_int_en_n : std_logic;
pci_req_out_n : std_logic;
pci_adout : std_logic_vector(31 downto 0);
pci_cbeout_n : std_logic_vector(3 downto 0);
pci_frame_out_n : std_logic;
pci_irdy_out_n : std_logic;
pci_trdy_out_n : std_logic;
pci_devsel_out_n : std_logic;
pci_stop_out_n : std_logic;
pci_perr_out_n : std_logic;
pci_serr_out_n : std_logic;
pci_par_out : std_logic;
pci_lock_out_n : std_logic;
power_state : std_logic_vector(1 downto 0);
pme_enable : std_logic;
pme_clear : std_logic;
pci_int_out_n : std_logic;
end record;
type div_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
y : std_logic_vector(32 downto 0); -- Y (MSB divident)
flush : std_logic;
signed : std_logic;
start : std_logic;
end record;
type div_out_type is record
ready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(31 downto 0); -- div result
end record;
type mul_in_type is record
op1 : std_logic_vector(32 downto 0); -- operand 1
op2 : std_logic_vector(32 downto 0); -- operand 2
flush : std_logic;
signed : std_logic;
start : std_logic;
mac : std_logic;
y : std_logic_vector(7 downto 0); -- Y (MSB MAC register)
asr18 : std_logic_vector(31 downto 0); -- LSB MAC register
end record;
type mul_out_type is record
ready : std_logic;
icc : std_logic_vector(3 downto 0); -- ICC
result : std_logic_vector(63 downto 0); -- mul result
end record;
type ahb_dma_in_type is record
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(31 downto 0);
start : std_logic;
burst : std_logic;
write : std_logic;
size : std_logic_vector(1 downto 0);
end record;
type ahb_dma_out_type is record
start : std_logic;
active : std_logic;
ready : std_logic;
retry : std_logic;
mexc : std_logic;
haddr : std_logic_vector(9 downto 0);
rdata : std_logic_vector(31 downto 0);
end record;
type actpci_be_in_type is record
mem_ad_int : std_logic_vector(31 downto 0);
mem_data : std_logic_vector(31 downto 0);
dp_done : std_logic;
dp_start : std_logic;
rd_be_now : std_logic;
rd_cyc : std_logic;
wr_be_now : std_logic_vector(3 downto 0);
wr_cyc : std_logic;
bar0_mem_cyc : std_logic;
busy : std_logic_vector(3 downto 0);
master_active : std_logic;
be_gnt : std_logic;
end record;
type actpci_be_out_type is record
rd_be_rdy : std_logic;
wr_be_rdy : std_logic;
error : std_logic;
busy : std_logic;
mem_data : std_logic_vector(31 downto 0);
cs_controln : std_logic;
rd_controln : std_logic;
wr_controln : std_logic;
control_add : std_logic_vector(1 downto 0);
ext_intn : std_logic;
be_req : std_logic;
end record;
type dsu_in_type is record
dsuen : std_logic;
dsubre : std_logic;
end record;
type dsu_out_type is record
dsuact : std_logic;
ntrace : std_logic;
freezetime : std_logic;
lresp : std_logic;
dresp : std_logic;
dsuen : std_logic;
dsubre : std_logic;
end record;
type dcom_in_type is record
dsurx : std_logic;
end record;
type dcom_out_type is record
dsutx : std_logic;
end record;
type dsuif_in_type is record
dsui : dsu_in_type;
dcomi : dcom_in_type;
end record;
type dsuif_out_type is record
dsuo : dsu_out_type;
dcomo : dcom_out_type;
end record;
type dcom_uart_in_type is record
rxd : std_logic;
read : std_logic;
write : std_logic;
data : std_logic_vector(7 downto 0);
dsuen : std_logic;
end record;
type dcom_uart_out_type is record
txd : std_logic;
dready : std_logic;
tsempty : std_logic;
thempty : std_logic;
lock : std_logic;
enable : std_logic;
data : std_logic_vector(7 downto 0);
end record;
type tracebuf_in_type is record
addr : std_logic_vector(TBUFABITS downto 0);
data : std_logic_vector(127 downto 0);
enable : std_logic;
write : std_logic_vector(3 downto 0);
end record;
type tracebuf_out_type is record
data : std_logic_vector(127 downto 0);
end record;
type dsumem_in_type is record
pbufi : tracebuf_in_type;
abufi : tracebuf_in_type;
end record;
type dsumem_out_type is record
pbufo : tracebuf_out_type;
abufo : tracebuf_out_type;
end record;
-- -----------------------------------------------
type ddm_in_type is record -- added for DDM
button0 : std_logic;
button1 : std_logic;
button2 : std_logic;
button3 : std_logic;
audioin : std_logic;
end record;
type ddm_out_type is record
digit0 : std_logic_vector(6 downto 0);
digit1 : std_logic_vector(6 downto 0);
audioout : std_logic;
lr_out : std_logic;
shift_clk : std_logic;
mclk : std_logic;
dispen : std_logic;
end record;
-- -----------------------------------------------
end;
|
use work.pkg.all;
package body other_pkg is
procedure other_proc(variable rec : inout rec_t) is
begin
proc(default_prot, rec);
end;
procedure other_proc(variable rec : inout other_rec_t) is
begin
proc(default_prot, rec);
end;
end package body;
|
use work.pkg.all;
package body other_pkg is
procedure other_proc(variable rec : inout rec_t) is
begin
proc(default_prot, rec);
end;
procedure other_proc(variable rec : inout other_rec_t) is
begin
proc(default_prot, rec);
end;
end package body;
|
use work.pkg.all;
package body other_pkg is
procedure other_proc(variable rec : inout rec_t) is
begin
proc(default_prot, rec);
end;
procedure other_proc(variable rec : inout other_rec_t) is
begin
proc(default_prot, rec);
end;
end package body;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY top IS
END top;
ARCHITECTURE behavior OF top IS
component packet_simulation port(
clock : IN std_logic;
data_valid: out std_logic;
data_out : out std_logic_vector(7 downto 0);
start_packet: out std_logic;
end_packet : out std_logic
);end component;
component parser port (
clk_read : in STD_LOGIC;
reset : in STD_LOGIC;
start_packet : in STD_LOGIC;
end_packet : in STD_LOGIC;
data_valid : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(7 downto 0);
eventID: out std_logic_vector(31 downto 0);
triggerID: out std_logic_vector(31 downto 0);
deviceID: out std_logic_vector(15 downto 0);
dataWORD: out std_logic_vector(31 downto 0);
out_data: out std_logic
);end component;
component devicefilter port(
deviceID: in std_logic_vector(15 downto 0);
in_data: in std_logic;
clock: in std_logic;
channel_offset: out std_logic_vector(15 downto 0);
accepted: out std_logic
);end component;
component tdc_parser port(
in_data:in std_logic;
dataWORD: in std_logic_vector(31 downto 0);
channel_offset: in std_logic_vector(15 downto 0);
eventID: in std_logic_vector(31 downto 0);
triggerID: in std_logic_vector(31 downto 0);
out_data: out std_logic;
time_isrising:out std_logic;
time_channel: out std_logic_vector(15 downto 0);
time_epoch: out std_logic_vector(27 downto 0);
time_fine: out std_logic_vector(9 downto 0);
time_coasser:out std_logic_vector(10 downto 0)
);end component;
signal clock : std_logic:='0';
signal reset : std_logic:='0';
signal data_valid : std_logic:='0';
signal start_packet : std_logic;
signal end_packet : std_logic;
signal data_bus : std_logic_vector(7 downto 0);
signal beforefilter:std_logic:='0';
signal afterfilter:std_logic:='0';
signal data_word: std_logic_vector(31 downto 0);
signal deviceID: std_logic_vector(15 downto 0);
signal eventID: std_logic_vector(31 downto 0);
signal triggerID: std_logic_vector(31 downto 0);
signal channel_offset: std_logic_vector(15 downto 0);
signal tdc_data: std_logic;
signal time_channel: std_logic_vector(15 downto 0);
signal time_isrising: std_logic;
signal time_epoch: std_logic_vector(27 downto 0);
signal time_fine: std_logic_vector(9 downto 0);
signal time_coasser: std_logic_vector(10 downto 0);
constant clock_period : time := 10 ns;
BEGIN
uut: packet_simulation PORT MAP (
clock => clock,
data_valid => data_valid,
data_out => data_bus,
start_packet => start_packet,
end_packet => end_packet
);
parse:parser port map (
clk_read => clock,
reset => reset,
start_packet => start_packet,
end_packet => end_packet,
data_valid => data_valid,
data_in => data_bus,
eventID => eventID,
triggerID => triggerID,
deviceID => deviceID,
dataWORD => data_word,
out_data => beforefilter
);
filter:devicefilter port map (
deviceID => deviceID,
in_data => beforefilter,
clock => clock,
channel_offset => channel_offset,
accepted => afterfilter
);
tdc:tdc_parser port map(
in_data => afterfilter,
dataWORD => data_word,
channel_offset => channel_offset,
eventID => eventID,
triggerID => triggerID,
out_data => tdc_data,
time_isrising => time_isrising,
time_channel => time_channel,
time_epoch => time_epoch,
time_fine => time_fine,
time_coasser => time_coasser
);
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
stim_proc: process
begin
wait;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
package wbgen2_pkg is
component wbgen2_dpssram
generic (
g_data_width : natural;
g_size : natural;
g_addr_width : natural;
g_dual_clock : boolean;
g_use_bwsel : boolean);
port (
clk_a_i : in std_logic;
clk_b_i : in std_logic;
addr_a_i : in std_logic_vector(g_addr_width-1 downto 0);
addr_b_i : in std_logic_vector(g_addr_width-1 downto 0);
data_a_i : in std_logic_vector(g_data_width-1 downto 0);
data_b_i : in std_logic_vector(g_data_width-1 downto 0);
data_a_o : out std_logic_vector(g_data_width-1 downto 0);
data_b_o : out std_logic_vector(g_data_width-1 downto 0);
bwsel_a_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
bwsel_b_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
rd_a_i : in std_logic;
rd_b_i : in std_logic;
wr_a_i : in std_logic;
wr_b_i : in std_logic);
end component;
component wbgen2_eic
generic (
g_num_interrupts : natural;
g_irq00_mode : integer;
g_irq01_mode : integer;
g_irq02_mode : integer;
g_irq03_mode : integer;
g_irq04_mode : integer;
g_irq05_mode : integer;
g_irq06_mode : integer;
g_irq07_mode : integer;
g_irq08_mode : integer;
g_irq09_mode : integer;
g_irq0a_mode : integer;
g_irq0b_mode : integer;
g_irq0c_mode : integer;
g_irq0d_mode : integer;
g_irq0e_mode : integer;
g_irq0f_mode : integer;
g_irq10_mode : integer;
g_irq11_mode : integer;
g_irq12_mode : integer;
g_irq13_mode : integer;
g_irq14_mode : integer;
g_irq15_mode : integer;
g_irq16_mode : integer;
g_irq17_mode : integer;
g_irq18_mode : integer;
g_irq19_mode : integer;
g_irq1a_mode : integer;
g_irq1b_mode : integer;
g_irq1c_mode : integer;
g_irq1d_mode : integer;
g_irq1e_mode : integer;
g_irq1f_mode : integer);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
irq_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_ack_o : out std_logic_vector(g_num_interrupts-1 downto 0);
reg_imr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
reg_ier_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_ier_wr_stb_i : in std_logic;
reg_idr_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_idr_wr_stb_i : in std_logic;
reg_isr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
reg_isr_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_isr_wr_stb_i : in std_logic;
wb_irq_o : out std_logic);
end component;
component wbgen2_fifo_async
generic (
g_size : integer;
g_width : integer;
g_usedw_size : integer);
port (
rd_clk_i : in std_logic;
rd_req_i : in std_logic;
rd_data_o : out std_logic_vector(g_width-1 downto 0);
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
wr_clk_i : in std_logic;
wr_req_i : in std_logic;
wr_data_i : in std_logic_vector(g_width-1 downto 0);
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0));
end component;
component wbgen2_fifo_sync
generic (
g_width : integer;
g_size : integer;
g_usedw_size : integer);
port (
clk_i : in std_logic;
wr_data_i : in std_logic_vector(g_width-1 downto 0);
wr_req_i : in std_logic;
rd_data_o : out std_logic_vector(g_width-1 downto 0);
rd_req_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0));
end component;
end wbgen2_pkg;
|
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 22:10:00 12/14/2016
-- Design Name: i2s_tx_tb.vhd
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This is a i2s tx modul Testbench.
-- Two 24 bit shift registers clock data to a D/A.
-- Key Features:
-- - configure receiver/transmitter, clock master/slave
-- word select master/slave
-- - ARM AMBA AXI4-Lite Bus (in future)
-- - Justification modes: normal, left, right
-- - Up to 8 I2S instances, configurable in different ways
-- - Testmodes
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.i2s_pkg.all;
use ieee.std_logic_textio.all;
entity i2s_tx_tb is
end entity i2s_tx_tb;
architecture sim of i2s_tx_tb is
signal sl_reset : std_logic := '0';
signal sl_clock : std_logic := '0';
signal slv_addr : std_logic_vector(c_addr-1 downto 0);
signal slv_l_channel : std_logic_vector(23 downto 0);
signal slv_r_channel : std_logic_vector(23 downto 0);
signal sl_wclk : std_logic;
signal sl_bclk : std_logic;
signal sl_sdata : std_logic;
begin
sl_clock <= not sl_clock after 10 ns;
sl_reset <= '0' after 20 ns, '1' after 60 ns;
uut: i2s_tx port map (
reset_n => sl_reset,
mclk => sl_clock,
-- input
i2s_in.l_channel => slv_l_channel,
i2s_in.r_channel => slv_r_channel,
-- output
i2s_out.wclk => sl_wclk,
i2s_out.bclk => sl_bclk,
i2s_out.sdata => sl_sdata
);
end sim;
|
entity tb_func04 is
end tb_func04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func04 is
signal a, b, r : std_logic_vector(7 downto 0);
begin
dut: entity work.func04
port map (a, b, r);
process
begin
a <= x"5d";
b <= x"78";
wait for 1 ns;
assert r = x"79" severity failure;
a <= x"0f";
b <= x"f0";
wait for 1 ns;
assert r = x"f3" severity failure;
wait;
end process;
end behav;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (5);
constant CFG_CLKDIV : integer := (3);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020605#;
constant CFG_ETH_ENL : integer := 16#000987#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- PCIEXP interface
constant CFG_PCIEXP : integer := 0;
constant CFG_PCIE_TYPE : integer := 0;
constant CFG_PCIE_SIM_MAS : integer := 0;
constant CFG_PCIEXPVID : integer := 16#0#;
constant CFG_PCIEXPDID : integer := 16#0#;
constant CFG_NO_OF_LANES : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- megafunction wizard: %LPM_MULT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_mult
-- ============================================================
-- File Name: mult.vhd
-- Megafunction Name(s):
-- lpm_mult
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY mult IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (16 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (16 DOWNTO 0)
);
END mult;
ARCHITECTURE SYN OF mult IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (16 DOWNTO 0);
SIGNAL sub_wire1_bv : BIT_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_mult
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_widtha : NATURAL;
lpm_widthb : NATURAL;
lpm_widthp : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (16 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (16 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(7 DOWNTO 0) <= "00111100";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
result <= sub_wire0(16 DOWNTO 0);
lpm_mult_component : lpm_mult
GENERIC MAP (
lpm_hint => "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 17,
lpm_widthb => 8,
lpm_widthp => 17
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0"
-- Retrieval info: PRIVATE: B_isConstant NUMERIC "1"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "60"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedMult NUMERIC "0"
-- Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
-- Retrieval info: PRIVATE: ValidConstant NUMERIC "1"
-- Retrieval info: PRIVATE: WidthA NUMERIC "17"
-- Retrieval info: PRIVATE: WidthB NUMERIC "8"
-- Retrieval info: PRIVATE: WidthP NUMERIC "17"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: optimize NUMERIC "0"
-- Retrieval info: CONSTANT: LPM_HINT STRING "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
-- Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "17"
-- Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "17"
-- Retrieval info: USED_PORT: dataa 0 0 17 0 INPUT NODEFVAL dataa[16..0]
-- Retrieval info: USED_PORT: result 0 0 17 0 OUTPUT NODEFVAL result[16..0]
-- Retrieval info: CONNECT: @dataa 0 0 17 0 dataa 0 0 17 0
-- Retrieval info: CONNECT: result 0 0 17 0 @result 0 0 17 0
-- Retrieval info: CONNECT: @datab 0 0 8 0 60 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL mult.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mult.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mult.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mult.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mult_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mult_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mult_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
library ieee;
use ieee.std_logic_1164.all;
entity test is
port(
tx : out std_logic);
end entity;
architecture tb of test is
begin
process
procedure transmit(data : std_logic_vector;
signal tx : out std_logic) is
variable norm : std_logic_vector(data'length - 1 downto 0) := data;
procedure send(value : std_logic) is
begin
tx <= value;
wait for 10 ns;
end procedure;
variable count : natural := 0;
begin
report natural'image (norm'left);
report natural'image (norm'right);
for i in norm'reverse_range loop
send(norm(i));
report to_string(i);
count := count + 1;
end loop;
assert count = 8 severity failure;
end procedure;
begin
transmit(x"55", tx);
wait;
end process;
end architecture;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.4.1 (win64) Build 2117270 Tue Jan 30 15:32:00 MST 2018
-- Date : Thu Apr 5 01:27:51 2018
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.vhdl
-- Design : design_1_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.4.1";
begin
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:50:16 10/22/2015
-- Design Name:
-- Module Name: four_bit_nand - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity four_bit_nand is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
y : in STD_LOGIC_VECTOR (3 downto 0);
nnd : out STD_LOGIC_VECTOR (3 downto 0));
end four_bit_nand;
architecture Behavioral of four_bit_nand is
begin
nnd(0) <= not (x(0) and y(0));
nnd(1) <= not (x(1) and y(1));
nnd(2) <= not (x(2) and y(2));
nnd(3) <= not (x(3) and y(3));
end Behavioral;
|
-- Copyright (c) 2019 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Simulation model for non-pipelined multiplier
-------------------------------------------------------------------------------
-- File : mul_dsp_comb_sim.vhdl
-- Author : Kati Tervo
-- Company :
-- Created : 2019-03-10
-- Last update: 2019-03-10
-- Platform :
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2019-03-10 1.0 katte Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mul_dsp48 is
generic (
latency_g : integer
); port(
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic;
load_in : in std_logic;
operand_a_in : in std_logic_vector(32-1 downto 0);
operand_b_in : in std_logic_vector(32-1 downto 0);
operand_c_in : in std_logic_vector(32-1 downto 0);
result_out : out std_logic_vector(32-1 downto 0)
);
end mul_dsp48;
architecture rtl of mul_dsp48 is
signal mul_result : std_logic_vector(64 - 1 downto 0);
signal result : std_logic_vector(32 - 1 downto 0);
type result_arr is array (latency_g downto 0)
of std_logic_vector(32-1 downto 0);
signal result_r : result_arr;
begin
mul_result <= std_logic_vector(unsigned(operand_a_in)
* unsigned(operand_b_in));
result <= std_logic_vector(unsigned(mul_result(32-1 downto 0))
+ unsigned(operand_c_in));
comb: if latency_g = 0 generate
result_out <= result;
end generate;
sync: if latency_g > 0 generate
operation_sync : process(clk)
begin
if rising_edge(clk) then
if rstx = '0' then
result_r <= (others => (others => '0'));
elsif glock_in = '0' then
if load_in = '1' then
result_r(0) <= result;
end if;
result_r(result_r'high downto 1) <= result_r(result_r'high-1 downto 0);
end if;
end if;
end process;
result_out <= result_r(latency_g-1);
end generate;
end rtl;
|
-- Copyright (c) 2019 Tampere University.
--
-- This file is part of TTA-Based Codesign Environment (TCE).
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
-------------------------------------------------------------------------------
-- Title : Simulation model for non-pipelined multiplier
-------------------------------------------------------------------------------
-- File : mul_dsp_comb_sim.vhdl
-- Author : Kati Tervo
-- Company :
-- Created : 2019-03-10
-- Last update: 2019-03-10
-- Platform :
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2019-03-10 1.0 katte Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mul_dsp48 is
generic (
latency_g : integer
); port(
clk : in std_logic;
rstx : in std_logic;
glock_in : in std_logic;
load_in : in std_logic;
operand_a_in : in std_logic_vector(32-1 downto 0);
operand_b_in : in std_logic_vector(32-1 downto 0);
operand_c_in : in std_logic_vector(32-1 downto 0);
result_out : out std_logic_vector(32-1 downto 0)
);
end mul_dsp48;
architecture rtl of mul_dsp48 is
signal mul_result : std_logic_vector(64 - 1 downto 0);
signal result : std_logic_vector(32 - 1 downto 0);
type result_arr is array (latency_g downto 0)
of std_logic_vector(32-1 downto 0);
signal result_r : result_arr;
begin
mul_result <= std_logic_vector(unsigned(operand_a_in)
* unsigned(operand_b_in));
result <= std_logic_vector(unsigned(mul_result(32-1 downto 0))
+ unsigned(operand_c_in));
comb: if latency_g = 0 generate
result_out <= result;
end generate;
sync: if latency_g > 0 generate
operation_sync : process(clk)
begin
if rising_edge(clk) then
if rstx = '0' then
result_r <= (others => (others => '0'));
elsif glock_in = '0' then
if load_in = '1' then
result_r(0) <= result;
end if;
result_r(result_r'high downto 1) <= result_r(result_r'high-1 downto 0);
end if;
end if;
end process;
result_out <= result_r(latency_g-1);
end generate;
end rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fx2_fifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fx2_fifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fx2_fifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
|
----------------------------------------------------------------------------------
-- Company: Bell Labs
-- Engineer: Timo Pfau
--
-- Create Date: 14:18:24 07/29/2011
-- Design Name:
-- Module Name: uart_tx - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
----------------------------------------------------------------------------------
-- Entity
----------------------------------------------------------------------------------
entity uart_tx is
generic (
use_handshake : boolean := true;
log2_oversampling : integer := 4);
port (
RST : in std_logic;
WRCLK : in std_logic;
CLKOSX : in std_logic;
WREN : in std_logic;
CTS : in std_logic;
WRCOUNT : out std_logic_vector(10 downto 0);
RDCOUNT : out std_logic_vector(10 downto 0);
WRDATA : in std_logic_vector(7 downto 0);
WRRDY : out std_logic;
TXD : out std_logic);
end uart_tx;
----------------------------------------------------------------------------------
-- Architecture
----------------------------------------------------------------------------------
architecture rtl of uart_tx is
----------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------
type STATE_TYPE is (st0_idle, st1_send_start_bit, st2_send_data_bits, st3_send_stop_bit);
signal STATE, NEXT_STATE : STATE_TYPE;
signal FIFO_FULL : std_logic;
signal FIFO_EMPTY : std_logic;
signal RDEN : std_logic;
signal RDDATA : std_logic_vector(7 downto 0);
-- signal RDCOUNT : std_logic_vector(10 downto 0);
-- signal WRCOUNT : std_logic_vector(10 downto 0);
signal DIVCTR : std_logic_vector(log2_oversampling-1 downto 0);
signal DIVPULSE : std_logic;
signal BYTECTR : std_logic_vector(2 downto 0);
signal BYTECTRINC : std_logic;
signal TXDATA : std_logic;
signal NEXT_TXDATA : std_logic;
begin
----------------------------------------------------------------------------------
-- Component Instantiation
----------------------------------------------------------------------------------
-- Dual-Clock First-In, First-Out (FIFO) RAM Buffer
FIFO_inst : FIFO_DUALCLOCK_MACRO
generic map (
DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6"
ALMOST_FULL_OFFSET => X"000F", -- Sets almost full threshold
ALMOST_EMPTY_OFFSET => X"000F", -- Sets the almost empty threshold
DATA_WIDTH => 8, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
FIFO_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
FIRST_WORD_FALL_THROUGH => FALSE) -- Sets the FIFO FWFT to TRUE or FALSE
port map (
ALMOSTEMPTY => open, -- 1-bit output almost empty
ALMOSTFULL => FIFO_FULL, -- 1-bit output almost full
DO => RDDATA, -- Output data, width defined by DATA_WIDTH parameter
EMPTY => FIFO_EMPTY, -- 1-bit output empty
FULL => open, -- 1-bit output full
RDCOUNT => RDCOUNT, -- Output read count, width determined by FIFO depth
RDERR => open, -- 1-bit output read error
WRCOUNT => WRCOUNT, -- Output write count, width determined by FIFO depth
WRERR => open, -- 1-bit output write error
DI => WRDATA, -- Input data, width defined by DATA_WIDTH parameter
RDCLK => CLKOSX, -- 1-bit input read clock
RDEN => RDEN, -- 1-bit input read enable
RST => RST, -- 1-bit input reset
WRCLK => WRCLK, -- 1-bit input write clock
WREN => WREN); -- 1-bit input write enable
----------------------------------------------------------------------------------
-- Concurrent Statements
----------------------------------------------------------------------------------
-- Write ready signal for FIFO
WRRDY <= not FIFO_FULL;
-- Register for FSM
sync_proc : process (CLKOSX, RST)
begin
if RST = '1' then
STATE <= st0_idle;
TXDATA <= '1';
TXD <= '1';
elsif rising_edge(CLKOSX) then
STATE <= NEXT_STATE;
TXDATA <= NEXT_TXDATA;
TXD <= TXDATA;
end if;
end process sync_proc;
-- Finite state machine (FSM)
fsm_proc : process (STATE, TXDATA, CTS, DIVPULSE, FIFO_EMPTY, RDDATA, BYTECTR)
begin
-- Default values
NEXT_STATE <= STATE; --default is to stay in current state
NEXT_TXDATA <= TXDATA;
RDEN <= '0';
BYTECTRINC <= '0';
if (DIVPULSE = '1') then
case STATE is
when st0_idle =>
if (FIFO_EMPTY = '0') and (CTS = '0' or not use_handshake) then
NEXT_STATE <= st1_send_start_bit;
NEXT_TXDATA <= '0';
RDEN <= '1';
BYTECTRINC <= '1';
end if;
when st1_send_start_bit =>
NEXT_STATE <= st2_send_data_bits;
NEXT_TXDATA <= RDDATA(conv_integer(BYTECTR));
BYTECTRINC <= '1';
when st2_send_data_bits =>
NEXT_TXDATA <= RDDATA(conv_integer(BYTECTR));
if (BYTECTR = "111") then
NEXT_STATE <= st3_send_stop_bit;
else
BYTECTRINC <= '1';
end if;
when st3_send_stop_bit =>
NEXT_STATE <= st0_idle;
NEXT_TXDATA <= '1';
when others => null;
end case;
end if;
end process fsm_proc;
-- Clock enable pulse
DIVPULSE <= '1' when (DIVCTR = 2**log2_oversampling-1) else '0';
-- Counter
ctr_proc : process (CLKOSX, RST)
begin
if RST = '1' then
DIVCTR <= (others => '0');
BYTECTR <= (others => '1');
elsif rising_edge(CLKOSX) then
DIVCTR <= DIVCTR + 1;
if BYTECTRINC = '1' then
BYTECTR <= BYTECTR + 1;
end if;
end if;
end process ctr_proc;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Bell Labs
-- Engineer: Timo Pfau
--
-- Create Date: 14:18:24 07/29/2011
-- Design Name:
-- Module Name: uart_tx - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
----------------------------------------------------------------------------------
-- Entity
----------------------------------------------------------------------------------
entity uart_tx is
generic (
use_handshake : boolean := true;
log2_oversampling : integer := 4);
port (
RST : in std_logic;
WRCLK : in std_logic;
CLKOSX : in std_logic;
WREN : in std_logic;
CTS : in std_logic;
WRCOUNT : out std_logic_vector(10 downto 0);
RDCOUNT : out std_logic_vector(10 downto 0);
WRDATA : in std_logic_vector(7 downto 0);
WRRDY : out std_logic;
TXD : out std_logic);
end uart_tx;
----------------------------------------------------------------------------------
-- Architecture
----------------------------------------------------------------------------------
architecture rtl of uart_tx is
----------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------
type STATE_TYPE is (st0_idle, st1_send_start_bit, st2_send_data_bits, st3_send_stop_bit);
signal STATE, NEXT_STATE : STATE_TYPE;
signal FIFO_FULL : std_logic;
signal FIFO_EMPTY : std_logic;
signal RDEN : std_logic;
signal RDDATA : std_logic_vector(7 downto 0);
-- signal RDCOUNT : std_logic_vector(10 downto 0);
-- signal WRCOUNT : std_logic_vector(10 downto 0);
signal DIVCTR : std_logic_vector(log2_oversampling-1 downto 0);
signal DIVPULSE : std_logic;
signal BYTECTR : std_logic_vector(2 downto 0);
signal BYTECTRINC : std_logic;
signal TXDATA : std_logic;
signal NEXT_TXDATA : std_logic;
begin
----------------------------------------------------------------------------------
-- Component Instantiation
----------------------------------------------------------------------------------
-- Dual-Clock First-In, First-Out (FIFO) RAM Buffer
FIFO_inst : FIFO_DUALCLOCK_MACRO
generic map (
DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6"
ALMOST_FULL_OFFSET => X"000F", -- Sets almost full threshold
ALMOST_EMPTY_OFFSET => X"000F", -- Sets the almost empty threshold
DATA_WIDTH => 8, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
FIFO_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
FIRST_WORD_FALL_THROUGH => FALSE) -- Sets the FIFO FWFT to TRUE or FALSE
port map (
ALMOSTEMPTY => open, -- 1-bit output almost empty
ALMOSTFULL => FIFO_FULL, -- 1-bit output almost full
DO => RDDATA, -- Output data, width defined by DATA_WIDTH parameter
EMPTY => FIFO_EMPTY, -- 1-bit output empty
FULL => open, -- 1-bit output full
RDCOUNT => RDCOUNT, -- Output read count, width determined by FIFO depth
RDERR => open, -- 1-bit output read error
WRCOUNT => WRCOUNT, -- Output write count, width determined by FIFO depth
WRERR => open, -- 1-bit output write error
DI => WRDATA, -- Input data, width defined by DATA_WIDTH parameter
RDCLK => CLKOSX, -- 1-bit input read clock
RDEN => RDEN, -- 1-bit input read enable
RST => RST, -- 1-bit input reset
WRCLK => WRCLK, -- 1-bit input write clock
WREN => WREN); -- 1-bit input write enable
----------------------------------------------------------------------------------
-- Concurrent Statements
----------------------------------------------------------------------------------
-- Write ready signal for FIFO
WRRDY <= not FIFO_FULL;
-- Register for FSM
sync_proc : process (CLKOSX, RST)
begin
if RST = '1' then
STATE <= st0_idle;
TXDATA <= '1';
TXD <= '1';
elsif rising_edge(CLKOSX) then
STATE <= NEXT_STATE;
TXDATA <= NEXT_TXDATA;
TXD <= TXDATA;
end if;
end process sync_proc;
-- Finite state machine (FSM)
fsm_proc : process (STATE, TXDATA, CTS, DIVPULSE, FIFO_EMPTY, RDDATA, BYTECTR)
begin
-- Default values
NEXT_STATE <= STATE; --default is to stay in current state
NEXT_TXDATA <= TXDATA;
RDEN <= '0';
BYTECTRINC <= '0';
if (DIVPULSE = '1') then
case STATE is
when st0_idle =>
if (FIFO_EMPTY = '0') and (CTS = '0' or not use_handshake) then
NEXT_STATE <= st1_send_start_bit;
NEXT_TXDATA <= '0';
RDEN <= '1';
BYTECTRINC <= '1';
end if;
when st1_send_start_bit =>
NEXT_STATE <= st2_send_data_bits;
NEXT_TXDATA <= RDDATA(conv_integer(BYTECTR));
BYTECTRINC <= '1';
when st2_send_data_bits =>
NEXT_TXDATA <= RDDATA(conv_integer(BYTECTR));
if (BYTECTR = "111") then
NEXT_STATE <= st3_send_stop_bit;
else
BYTECTRINC <= '1';
end if;
when st3_send_stop_bit =>
NEXT_STATE <= st0_idle;
NEXT_TXDATA <= '1';
when others => null;
end case;
end if;
end process fsm_proc;
-- Clock enable pulse
DIVPULSE <= '1' when (DIVCTR = 2**log2_oversampling-1) else '0';
-- Counter
ctr_proc : process (CLKOSX, RST)
begin
if RST = '1' then
DIVCTR <= (others => '0');
BYTECTR <= (others => '1');
elsif rising_edge(CLKOSX) then
DIVCTR <= DIVCTR + 1;
if BYTECTRINC = '1' then
BYTECTR <= BYTECTR + 1;
end if;
end if;
end process ctr_proc;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Bell Labs
-- Engineer: Timo Pfau
--
-- Create Date: 14:18:24 07/29/2011
-- Design Name:
-- Module Name: uart_tx - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
----------------------------------------------------------------------------------
-- Entity
----------------------------------------------------------------------------------
entity uart_tx is
generic (
use_handshake : boolean := true;
log2_oversampling : integer := 4);
port (
RST : in std_logic;
WRCLK : in std_logic;
CLKOSX : in std_logic;
WREN : in std_logic;
CTS : in std_logic;
WRCOUNT : out std_logic_vector(10 downto 0);
RDCOUNT : out std_logic_vector(10 downto 0);
WRDATA : in std_logic_vector(7 downto 0);
WRRDY : out std_logic;
TXD : out std_logic);
end uart_tx;
----------------------------------------------------------------------------------
-- Architecture
----------------------------------------------------------------------------------
architecture rtl of uart_tx is
----------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------
type STATE_TYPE is (st0_idle, st1_send_start_bit, st2_send_data_bits, st3_send_stop_bit);
signal STATE, NEXT_STATE : STATE_TYPE;
signal FIFO_FULL : std_logic;
signal FIFO_EMPTY : std_logic;
signal RDEN : std_logic;
signal RDDATA : std_logic_vector(7 downto 0);
-- signal RDCOUNT : std_logic_vector(10 downto 0);
-- signal WRCOUNT : std_logic_vector(10 downto 0);
signal DIVCTR : std_logic_vector(log2_oversampling-1 downto 0);
signal DIVPULSE : std_logic;
signal BYTECTR : std_logic_vector(2 downto 0);
signal BYTECTRINC : std_logic;
signal TXDATA : std_logic;
signal NEXT_TXDATA : std_logic;
begin
----------------------------------------------------------------------------------
-- Component Instantiation
----------------------------------------------------------------------------------
-- Dual-Clock First-In, First-Out (FIFO) RAM Buffer
FIFO_inst : FIFO_DUALCLOCK_MACRO
generic map (
DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6"
ALMOST_FULL_OFFSET => X"000F", -- Sets almost full threshold
ALMOST_EMPTY_OFFSET => X"000F", -- Sets the almost empty threshold
DATA_WIDTH => 8, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
FIFO_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
FIRST_WORD_FALL_THROUGH => FALSE) -- Sets the FIFO FWFT to TRUE or FALSE
port map (
ALMOSTEMPTY => open, -- 1-bit output almost empty
ALMOSTFULL => FIFO_FULL, -- 1-bit output almost full
DO => RDDATA, -- Output data, width defined by DATA_WIDTH parameter
EMPTY => FIFO_EMPTY, -- 1-bit output empty
FULL => open, -- 1-bit output full
RDCOUNT => RDCOUNT, -- Output read count, width determined by FIFO depth
RDERR => open, -- 1-bit output read error
WRCOUNT => WRCOUNT, -- Output write count, width determined by FIFO depth
WRERR => open, -- 1-bit output write error
DI => WRDATA, -- Input data, width defined by DATA_WIDTH parameter
RDCLK => CLKOSX, -- 1-bit input read clock
RDEN => RDEN, -- 1-bit input read enable
RST => RST, -- 1-bit input reset
WRCLK => WRCLK, -- 1-bit input write clock
WREN => WREN); -- 1-bit input write enable
----------------------------------------------------------------------------------
-- Concurrent Statements
----------------------------------------------------------------------------------
-- Write ready signal for FIFO
WRRDY <= not FIFO_FULL;
-- Register for FSM
sync_proc : process (CLKOSX, RST)
begin
if RST = '1' then
STATE <= st0_idle;
TXDATA <= '1';
TXD <= '1';
elsif rising_edge(CLKOSX) then
STATE <= NEXT_STATE;
TXDATA <= NEXT_TXDATA;
TXD <= TXDATA;
end if;
end process sync_proc;
-- Finite state machine (FSM)
fsm_proc : process (STATE, TXDATA, CTS, DIVPULSE, FIFO_EMPTY, RDDATA, BYTECTR)
begin
-- Default values
NEXT_STATE <= STATE; --default is to stay in current state
NEXT_TXDATA <= TXDATA;
RDEN <= '0';
BYTECTRINC <= '0';
if (DIVPULSE = '1') then
case STATE is
when st0_idle =>
if (FIFO_EMPTY = '0') and (CTS = '0' or not use_handshake) then
NEXT_STATE <= st1_send_start_bit;
NEXT_TXDATA <= '0';
RDEN <= '1';
BYTECTRINC <= '1';
end if;
when st1_send_start_bit =>
NEXT_STATE <= st2_send_data_bits;
NEXT_TXDATA <= RDDATA(conv_integer(BYTECTR));
BYTECTRINC <= '1';
when st2_send_data_bits =>
NEXT_TXDATA <= RDDATA(conv_integer(BYTECTR));
if (BYTECTR = "111") then
NEXT_STATE <= st3_send_stop_bit;
else
BYTECTRINC <= '1';
end if;
when st3_send_stop_bit =>
NEXT_STATE <= st0_idle;
NEXT_TXDATA <= '1';
when others => null;
end case;
end if;
end process fsm_proc;
-- Clock enable pulse
DIVPULSE <= '1' when (DIVCTR = 2**log2_oversampling-1) else '0';
-- Counter
ctr_proc : process (CLKOSX, RST)
begin
if RST = '1' then
DIVCTR <= (others => '0');
BYTECTR <= (others => '1');
elsif rising_edge(CLKOSX) then
DIVCTR <= DIVCTR + 1;
if BYTECTRINC = '1' then
BYTECTR <= BYTECTR + 1;
end if;
end if;
end process ctr_proc;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: Bell Labs
-- Engineer: Timo Pfau
--
-- Create Date: 14:18:24 07/29/2011
-- Design Name:
-- Module Name: uart_tx - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Libraries
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
----------------------------------------------------------------------------------
-- Entity
----------------------------------------------------------------------------------
entity uart_tx is
generic (
use_handshake : boolean := true;
log2_oversampling : integer := 4);
port (
RST : in std_logic;
WRCLK : in std_logic;
CLKOSX : in std_logic;
WREN : in std_logic;
CTS : in std_logic;
WRCOUNT : out std_logic_vector(10 downto 0);
RDCOUNT : out std_logic_vector(10 downto 0);
WRDATA : in std_logic_vector(7 downto 0);
WRRDY : out std_logic;
TXD : out std_logic);
end uart_tx;
----------------------------------------------------------------------------------
-- Architecture
----------------------------------------------------------------------------------
architecture rtl of uart_tx is
----------------------------------------------------------------------------------
-- Signals
----------------------------------------------------------------------------------
type STATE_TYPE is (st0_idle, st1_send_start_bit, st2_send_data_bits, st3_send_stop_bit);
signal STATE, NEXT_STATE : STATE_TYPE;
signal FIFO_FULL : std_logic;
signal FIFO_EMPTY : std_logic;
signal RDEN : std_logic;
signal RDDATA : std_logic_vector(7 downto 0);
-- signal RDCOUNT : std_logic_vector(10 downto 0);
-- signal WRCOUNT : std_logic_vector(10 downto 0);
signal DIVCTR : std_logic_vector(log2_oversampling-1 downto 0);
signal DIVPULSE : std_logic;
signal BYTECTR : std_logic_vector(2 downto 0);
signal BYTECTRINC : std_logic;
signal TXDATA : std_logic;
signal NEXT_TXDATA : std_logic;
begin
----------------------------------------------------------------------------------
-- Component Instantiation
----------------------------------------------------------------------------------
-- Dual-Clock First-In, First-Out (FIFO) RAM Buffer
FIFO_inst : FIFO_DUALCLOCK_MACRO
generic map (
DEVICE => "VIRTEX6", -- Target Device: "VIRTEX5", "VIRTEX6"
ALMOST_FULL_OFFSET => X"000F", -- Sets almost full threshold
ALMOST_EMPTY_OFFSET => X"000F", -- Sets the almost empty threshold
DATA_WIDTH => 8, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
FIFO_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
FIRST_WORD_FALL_THROUGH => FALSE) -- Sets the FIFO FWFT to TRUE or FALSE
port map (
ALMOSTEMPTY => open, -- 1-bit output almost empty
ALMOSTFULL => FIFO_FULL, -- 1-bit output almost full
DO => RDDATA, -- Output data, width defined by DATA_WIDTH parameter
EMPTY => FIFO_EMPTY, -- 1-bit output empty
FULL => open, -- 1-bit output full
RDCOUNT => RDCOUNT, -- Output read count, width determined by FIFO depth
RDERR => open, -- 1-bit output read error
WRCOUNT => WRCOUNT, -- Output write count, width determined by FIFO depth
WRERR => open, -- 1-bit output write error
DI => WRDATA, -- Input data, width defined by DATA_WIDTH parameter
RDCLK => CLKOSX, -- 1-bit input read clock
RDEN => RDEN, -- 1-bit input read enable
RST => RST, -- 1-bit input reset
WRCLK => WRCLK, -- 1-bit input write clock
WREN => WREN); -- 1-bit input write enable
----------------------------------------------------------------------------------
-- Concurrent Statements
----------------------------------------------------------------------------------
-- Write ready signal for FIFO
WRRDY <= not FIFO_FULL;
-- Register for FSM
sync_proc : process (CLKOSX, RST)
begin
if RST = '1' then
STATE <= st0_idle;
TXDATA <= '1';
TXD <= '1';
elsif rising_edge(CLKOSX) then
STATE <= NEXT_STATE;
TXDATA <= NEXT_TXDATA;
TXD <= TXDATA;
end if;
end process sync_proc;
-- Finite state machine (FSM)
fsm_proc : process (STATE, TXDATA, CTS, DIVPULSE, FIFO_EMPTY, RDDATA, BYTECTR)
begin
-- Default values
NEXT_STATE <= STATE; --default is to stay in current state
NEXT_TXDATA <= TXDATA;
RDEN <= '0';
BYTECTRINC <= '0';
if (DIVPULSE = '1') then
case STATE is
when st0_idle =>
if (FIFO_EMPTY = '0') and (CTS = '0' or not use_handshake) then
NEXT_STATE <= st1_send_start_bit;
NEXT_TXDATA <= '0';
RDEN <= '1';
BYTECTRINC <= '1';
end if;
when st1_send_start_bit =>
NEXT_STATE <= st2_send_data_bits;
NEXT_TXDATA <= RDDATA(conv_integer(BYTECTR));
BYTECTRINC <= '1';
when st2_send_data_bits =>
NEXT_TXDATA <= RDDATA(conv_integer(BYTECTR));
if (BYTECTR = "111") then
NEXT_STATE <= st3_send_stop_bit;
else
BYTECTRINC <= '1';
end if;
when st3_send_stop_bit =>
NEXT_STATE <= st0_idle;
NEXT_TXDATA <= '1';
when others => null;
end case;
end if;
end process fsm_proc;
-- Clock enable pulse
DIVPULSE <= '1' when (DIVCTR = 2**log2_oversampling-1) else '0';
-- Counter
ctr_proc : process (CLKOSX, RST)
begin
if RST = '1' then
DIVCTR <= (others => '0');
BYTECTR <= (others => '1');
elsif rising_edge(CLKOSX) then
DIVCTR <= DIVCTR + 1;
if BYTECTRINC = '1' then
BYTECTR <= BYTECTR + 1;
end if;
end if;
end process ctr_proc;
end rtl;
|
entity arith1 is
end entity;
architecture test of arith1 is
begin
proc1: process is
variable x, y : integer;
begin
x := 3;
y := 12;
wait for 1 ns;
assert x + y = 15;
assert x - y = -9;
assert x * y = 36;
assert x / 12 = 0;
assert x = 3;
assert y = 12;
assert x /= y;
assert x < y;
assert y > x;
assert x <= y;
assert y >= x;
assert (- x) = -3;
assert x ** y = 531441;
x := -34;
assert abs x = 34;
assert abs y = 12;
y := 3;
assert 5 mod y = 2;
assert 5 rem y = 2;
assert (-5) rem y = -2;
assert (-5) mod y = 2;
assert x = +x;
wait;
end process;
end architecture;
|
architecture rtl of fifo is
begin
GEN_LABEL : case expression generate
end generate;
GEN_LABEL : case expression generate
end GENERATE;
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7968)
`protect data_block
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`protect end_protected
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_06.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
package mem_pkg is
subtype word is bit_vector(0 to 31);
type word_array is array (natural range <>) of word;
procedure load_array ( words : out word_array; file_name : string );
end package mem_pkg;
package body mem_pkg is
procedure load_array ( words : out word_array; file_name : string ) is
-- words'path_name = ":project:mem_pkg:load_array:words"
use std.textio.all;
file load_file : text open read_mode is file_name;
-- load_file'path_name = ":project:mem_pkg:load_array:load_file"
procedure read_line is
-- read_line'path_name = ":project:mem_pkg:load_array:read_line:"
variable current_line : line;
-- current_line'path_name =
-- ":project:mem_pkg:load_array:read_line:current_line"
begin
-- . . .
-- not in book
report current_line'path_name;
-- end not in book
end procedure read_line;
begin -- load_array
-- . . .
-- not in book
report mem_pkg'path_name;
report words'path_name;
report load_file'path_name;
report read_line'path_name;
read_line;
-- end not in book
end procedure load_array;
end package body mem_pkg;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_06.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
package mem_pkg is
subtype word is bit_vector(0 to 31);
type word_array is array (natural range <>) of word;
procedure load_array ( words : out word_array; file_name : string );
end package mem_pkg;
package body mem_pkg is
procedure load_array ( words : out word_array; file_name : string ) is
-- words'path_name = ":project:mem_pkg:load_array:words"
use std.textio.all;
file load_file : text open read_mode is file_name;
-- load_file'path_name = ":project:mem_pkg:load_array:load_file"
procedure read_line is
-- read_line'path_name = ":project:mem_pkg:load_array:read_line:"
variable current_line : line;
-- current_line'path_name =
-- ":project:mem_pkg:load_array:read_line:current_line"
begin
-- . . .
-- not in book
report current_line'path_name;
-- end not in book
end procedure read_line;
begin -- load_array
-- . . .
-- not in book
report mem_pkg'path_name;
report words'path_name;
report load_file'path_name;
report read_line'path_name;
read_line;
-- end not in book
end procedure load_array;
end package body mem_pkg;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_06.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
package mem_pkg is
subtype word is bit_vector(0 to 31);
type word_array is array (natural range <>) of word;
procedure load_array ( words : out word_array; file_name : string );
end package mem_pkg;
package body mem_pkg is
procedure load_array ( words : out word_array; file_name : string ) is
-- words'path_name = ":project:mem_pkg:load_array:words"
use std.textio.all;
file load_file : text open read_mode is file_name;
-- load_file'path_name = ":project:mem_pkg:load_array:load_file"
procedure read_line is
-- read_line'path_name = ":project:mem_pkg:load_array:read_line:"
variable current_line : line;
-- current_line'path_name =
-- ":project:mem_pkg:load_array:read_line:current_line"
begin
-- . . .
-- not in book
report current_line'path_name;
-- end not in book
end procedure read_line;
begin -- load_array
-- . . .
-- not in book
report mem_pkg'path_name;
report words'path_name;
report load_file'path_name;
report read_line'path_name;
read_line;
-- end not in book
end procedure load_array;
end package body mem_pkg;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:46:06 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_microblaze_0_axi_intc_0/system_microblaze_0_axi_intc_0_sim_netlist.vhdl
-- Design : system_microblaze_0_axi_intc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0_address_decoder is
port (
p_17_in : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ : out STD_LOGIC;
ip2bus_wrack_prev2 : out STD_LOGIC;
Or128_vec2stdlogic : out STD_LOGIC;
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\ : out STD_LOGIC;
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\ : out STD_LOGIC;
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\ : out STD_LOGIC;
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\ : out STD_LOGIC;
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\ : out STD_LOGIC;
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\ : out STD_LOGIC;
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\ : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
ip2bus_rdack_prev2 : out STD_LOGIC;
Or128_vec2stdlogic19_out : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\ : out STD_LOGIC;
\mer_int_reg[0]\ : out STD_LOGIC;
\mer_int_reg[1]\ : out STD_LOGIC;
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
ip2bus_wrack_int_d1 : in STD_LOGIC;
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\ : in STD_LOGIC;
p_0_in2_in : in STD_LOGIC;
p_0_in5_in : in STD_LOGIC;
p_0_in8_in : in STD_LOGIC;
p_0_in11_in : in STD_LOGIC;
p_0_in14_in : in STD_LOGIC;
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\ : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
ip2bus_wrack : in STD_LOGIC;
is_read : in STD_LOGIC;
ip2bus_rdack : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]_0\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]\ : in STD_LOGIC;
\Douta_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[3]\ : in STD_LOGIC;
\REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[2]\ : in STD_LOGIC;
\bus2ip_addr_i_reg[3]_0\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]_0\ : in STD_LOGIC;
\bus2ip_addr_i_reg[3]_1\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]_1\ : in STD_LOGIC;
\bus2ip_addr_i_reg[3]_2\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]_2\ : in STD_LOGIC;
\bus2ip_addr_i_reg[3]_3\ : in STD_LOGIC;
\bus2ip_addr_i_reg[5]_3\ : in STD_LOGIC;
\bus2ip_addr_i_reg[6]\ : in STD_LOGIC;
ip2bus_rdack_int_d1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 6 downto 0 );
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1\ : in STD_LOGIC;
p_0_in118_in : in STD_LOGIC;
p_0_in107_in : in STD_LOGIC;
p_0_in96_in : in STD_LOGIC;
p_0_in85_in : in STD_LOGIC;
p_0_in74_in : in STD_LOGIC;
p_0_in64_in : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ : in STD_LOGIC;
p_0_in59_in : in STD_LOGIC;
p_0_in57_in : in STD_LOGIC;
p_0_in55_in : in STD_LOGIC;
p_0_in53_in : in STD_LOGIC;
p_0_in51_in : in STD_LOGIC;
p_0_in49_in : in STD_LOGIC;
\mer_int_reg[0]_0\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
bus2ip_rnw_i_reg : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_microblaze_0_axi_intc_0_address_decoder : entity is "address_decoder";
end system_microblaze_0_axi_intc_0_address_decoder;
architecture STRUCTURE of system_microblaze_0_axi_intc_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\ : STD_LOGIC;
signal \^sie_gen.sie_bit_gen[0].sie_reg[0]\ : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \eqOp__2\ : STD_LOGIC;
signal ip2bus_wrack_int_d1_i_2_n_0 : STD_LOGIC;
signal ip2bus_wrack_int_d1_i_3_n_0 : STD_LOGIC;
signal ip2bus_wrack_int_d1_i_4_n_0 : STD_LOGIC;
signal ip2bus_wrack_int_d1_i_5_n_0 : STD_LOGIC;
signal p_10_in : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_11_in : STD_LOGIC;
signal p_11_out : STD_LOGIC;
signal p_12_in : STD_LOGIC;
signal p_13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_14_in : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_15_in : STD_LOGIC;
signal p_15_out : STD_LOGIC;
signal p_16_in : STD_LOGIC;
signal \^p_17_in\ : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal p_3_out : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_in : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pselect_hit_i_0 : STD_LOGIC;
signal pselect_hit_i_1 : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_5_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \REG_GEN[0].IMR_FAST_MODE_GEN.imr[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \REG_GEN[0].ier[0]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_2\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of ip2bus_wrack_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of ip2bus_wrack_int_d1_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \mer_int[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \s_axi_rdata_i[31]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axi_rdata_i[6]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axi_rdata_i[6]_i_5\ : label is "soft_lutpair1";
begin
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ <= \^sie_gen.sie_bit_gen[0].sie_reg[0]\;
p_17_in <= \^p_17_in\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => Q,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[0].cie[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(0),
O => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\
);
\CIE_GEN.CIE_BIT_GEN[1].cie[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => p_0_in59_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(1),
O => \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\
);
\CIE_GEN.CIE_BIT_GEN[2].cie[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => p_0_in57_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(2),
O => \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\
);
\CIE_GEN.CIE_BIT_GEN[3].cie[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => p_0_in55_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(3),
O => \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\
);
\CIE_GEN.CIE_BIT_GEN[4].cie[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => p_0_in53_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(4),
O => \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\
);
\CIE_GEN.CIE_BIT_GEN[5].cie[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => p_0_in51_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(5),
O => \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\
);
\CIE_GEN.CIE_BIT_GEN[6].cie[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => s_axi_aresetn,
I1 => p_0_in49_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => p_12_in,
I4 => s_axi_wdata(6),
O => \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
O => \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1_n_0\,
Q => \^p_17_in\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
O => p_5_out
);
\GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_5_out,
Q => p_7_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
O => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(2),
I1 => \bus2ip_addr_i_reg[8]\(4),
I2 => Q,
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(3),
O => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1_n_0\,
Q => p_6_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_3_out
);
\GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_3_out,
Q => p_5_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_2_out
);
\GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_2_out,
Q => p_4_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_1_out
);
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_1_out,
Q => p_3_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_15_out
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEFFFFF"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(5),
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => Q,
I3 => \bus2ip_addr_i_reg[8]\(4),
I4 => \bus2ip_addr_i_reg[8]\(2),
O => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_15_out,
Q => p_2_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFCF8FFFFFFFF"
)
port map (
I0 => is_write_reg,
I1 => \eqOp__2\,
I2 => ip2bus_wrack,
I3 => is_read,
I4 => ip2bus_rdack,
I5 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(5),
I1 => \bus2ip_addr_i_reg[8]\(6),
I2 => Q,
O => pselect_hit_i_0
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
O => \eqOp__2\
);
\GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => pselect_hit_i_0,
Q => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
O => p_14_out
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_14_out,
Q => p_16_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
O => p_13_out
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_13_out,
Q => p_15_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0\
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000010"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(2),
I1 => \bus2ip_addr_i_reg[8]\(4),
I2 => Q,
I3 => \bus2ip_addr_i_reg[8]\(6),
I4 => \bus2ip_addr_i_reg[8]\(5),
I5 => \bus2ip_addr_i_reg[8]\(3),
O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1_n_0\,
Q => p_14_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_11_out
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_11_out,
Q => p_13_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_10_out
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_10_out,
Q => p_12_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00080000"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(0),
I3 => \bus2ip_addr_i_reg[8]\(3),
I4 => pselect_hit_i_1,
O => p_9_out
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(4),
I1 => Q,
I2 => \bus2ip_addr_i_reg[8]\(6),
I3 => \bus2ip_addr_i_reg[8]\(5),
O => pselect_hit_i_1
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_9_out,
Q => p_11_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(3),
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_2_n_0\,
O => p_8_out
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_8_out,
Q => p_10_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(1),
O => p_7_out
);
\GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_7_out,
Q => p_9_in,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_2_n_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \bus2ip_addr_i_reg[8]\(0),
O => p_6_out
);
\GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => p_6_out,
Q => p_8_in,
R => cs_ce_clr
);
\REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\,
O => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\
);
\REG_GEN[0].IMR_FAST_MODE_GEN.imr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_9_in,
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
O => bus2ip_wrce(1)
);
\REG_GEN[0].ier[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => p_15_in,
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
O => \bus2ip_wrce__0\(0)
);
\REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => p_0_in14_in,
O => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\
);
\REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => p_0_in11_in,
O => \REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\
);
\REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => p_0_in8_in,
O => \REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\
);
\REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => p_0_in5_in,
O => \REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\
);
\REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => p_0_in2_in,
O => \REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\
);
\REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_14_in,
I2 => \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\,
O => \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\
);
\SIE_GEN.SIE_BIT_GEN[0].sie[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(0),
I3 => s_axi_aresetn,
I4 => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1\,
O => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\
);
\SIE_GEN.SIE_BIT_GEN[1].sie[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(1),
I3 => s_axi_aresetn,
I4 => p_0_in118_in,
O => \SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\
);
\SIE_GEN.SIE_BIT_GEN[2].sie[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(2),
I3 => s_axi_aresetn,
I4 => p_0_in107_in,
O => \SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\
);
\SIE_GEN.SIE_BIT_GEN[3].sie[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(3),
I3 => s_axi_aresetn,
I4 => p_0_in96_in,
O => \SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\
);
\SIE_GEN.SIE_BIT_GEN[4].sie[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(4),
I3 => s_axi_aresetn,
I4 => p_0_in85_in,
O => \SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\
);
\SIE_GEN.SIE_BIT_GEN[5].sie[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(5),
I3 => s_axi_aresetn,
I4 => p_0_in74_in,
O => \SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\
);
\SIE_GEN.SIE_BIT_GEN[6].sie[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_13_in,
I2 => s_axi_wdata(6),
I3 => s_axi_aresetn,
I4 => p_0_in64_in,
O => \SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\
);
ip2bus_rdack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFCCC8"
)
port map (
I0 => p_14_in,
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => ip2bus_wrack_int_d1_i_4_n_0,
I4 => \s_axi_rdata_i[31]_i_3_n_0\,
I5 => ip2bus_rdack_int_d1,
O => ip2bus_rdack_prev2
);
ip2bus_rdack_int_d1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFAAFEAA"
)
port map (
I0 => \s_axi_rdata_i[31]_i_3_n_0\,
I1 => ip2bus_wrack_int_d1_i_4_n_0,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I4 => p_14_in,
O => Or128_vec2stdlogic19_out
);
ip2bus_wrack_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FF32"
)
port map (
I0 => ip2bus_wrack_int_d1_i_4_n_0,
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => ip2bus_wrack_int_d1_i_3_n_0,
I3 => ip2bus_wrack_int_d1_i_2_n_0,
I4 => ip2bus_wrack_int_d1,
O => ip2bus_wrack_prev2
);
ip2bus_wrack_int_d1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"AFAE"
)
port map (
I0 => ip2bus_wrack_int_d1_i_2_n_0,
I1 => ip2bus_wrack_int_d1_i_3_n_0,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => ip2bus_wrack_int_d1_i_4_n_0,
O => Or128_vec2stdlogic
);
ip2bus_wrack_int_d1_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF00FE"
)
port map (
I0 => p_14_in,
I1 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I2 => p_10_in,
I3 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I4 => p_15_in,
O => ip2bus_wrack_int_d1_i_2_n_0
);
ip2bus_wrack_int_d1_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_16_in,
I1 => p_9_in,
I2 => \^p_17_in\,
I3 => p_8_in,
I4 => p_11_in,
O => ip2bus_wrack_int_d1_i_3_n_0
);
ip2bus_wrack_int_d1_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => p_5_in,
I1 => p_4_in,
I2 => p_7_in,
I3 => p_6_in,
I4 => ip2bus_wrack_int_d1_i_5_n_0,
O => ip2bus_wrack_int_d1_i_4_n_0
);
ip2bus_wrack_int_d1_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_2_in,
I1 => p_3_in,
I2 => p_13_in,
I3 => p_12_in,
O => ip2bus_wrack_int_d1_i_5_n_0
);
\mer_int[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => p_10_in,
I2 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I3 => \mer_int_reg[0]_0\,
O => \mer_int_reg[0]\
);
\mer_int[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF20"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => p_10_in,
I3 => p_0_in,
O => \mer_int_reg[1]\
);
ram_reg_0_15_0_0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
O => bus2ip_wrce(0)
);
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE0E0E0"
)
port map (
I0 => \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[5]\,
I2 => \s_axi_rdata_i[6]_i_4_n_0\,
I3 => \Douta_reg[31]\(0),
I4 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(0)
);
\s_axi_rdata_i[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(10),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(10)
);
\s_axi_rdata_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(11),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(11)
);
\s_axi_rdata_i[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(12),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(12)
);
\s_axi_rdata_i[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(13),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(13)
);
\s_axi_rdata_i[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(14),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(14)
);
\s_axi_rdata_i[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(15),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(15)
);
\s_axi_rdata_i[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(16),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(16)
);
\s_axi_rdata_i[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(17),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(17)
);
\s_axi_rdata_i[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(18),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(18)
);
\s_axi_rdata_i[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(19),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(19)
);
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE0E0E0"
)
port map (
I0 => \REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1]\,
I1 => \bus2ip_addr_i_reg[5]\,
I2 => \s_axi_rdata_i[6]_i_4_n_0\,
I3 => \Douta_reg[31]\(1),
I4 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(1)
);
\s_axi_rdata_i[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(20),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(20)
);
\s_axi_rdata_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(21),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(21)
);
\s_axi_rdata_i[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(22),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(22)
);
\s_axi_rdata_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(23),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(23)
);
\s_axi_rdata_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(24),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(24)
);
\s_axi_rdata_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(25),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(25)
);
\s_axi_rdata_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(26),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(26)
);
\s_axi_rdata_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(27),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(27)
);
\s_axi_rdata_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(28),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(28)
);
\s_axi_rdata_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(29),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(29)
);
\s_axi_rdata_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFE00FE00FE00"
)
port map (
I0 => \bus2ip_addr_i_reg[3]\,
I1 => \bus2ip_addr_i_reg[5]\,
I2 => \REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2]\,
I3 => \s_axi_rdata_i[6]_i_4_n_0\,
I4 => \Douta_reg[31]\(2),
I5 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(2)
);
\s_axi_rdata_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(30),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(30)
);
\s_axi_rdata_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(31),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(31)
);
\s_axi_rdata_i[31]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE00"
)
port map (
I0 => ip2bus_wrack_int_d1_i_3_n_0,
I1 => p_10_in,
I2 => p_15_in,
I3 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
O => \s_axi_rdata_i[31]_i_3_n_0\
);
\s_axi_rdata_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFE00FE00FE00"
)
port map (
I0 => \bus2ip_addr_i_reg[2]\,
I1 => \bus2ip_addr_i_reg[3]_0\,
I2 => \bus2ip_addr_i_reg[5]_0\,
I3 => \s_axi_rdata_i[6]_i_4_n_0\,
I4 => \Douta_reg[31]\(3),
I5 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(3)
);
\s_axi_rdata_i[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFE00FE00FE00"
)
port map (
I0 => \bus2ip_addr_i_reg[2]\,
I1 => \bus2ip_addr_i_reg[3]_1\,
I2 => \bus2ip_addr_i_reg[5]_1\,
I3 => \s_axi_rdata_i[6]_i_4_n_0\,
I4 => \Douta_reg[31]\(4),
I5 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(4)
);
\s_axi_rdata_i[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFE00FE00FE00"
)
port map (
I0 => \bus2ip_addr_i_reg[2]\,
I1 => \bus2ip_addr_i_reg[3]_2\,
I2 => \bus2ip_addr_i_reg[5]_2\,
I3 => \s_axi_rdata_i[6]_i_4_n_0\,
I4 => \Douta_reg[31]\(5),
I5 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(5)
);
\s_axi_rdata_i[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFE00FE00FE00"
)
port map (
I0 => \bus2ip_addr_i_reg[2]\,
I1 => \bus2ip_addr_i_reg[3]_3\,
I2 => \bus2ip_addr_i_reg[5]_3\,
I3 => \s_axi_rdata_i[6]_i_4_n_0\,
I4 => \Douta_reg[31]\(6),
I5 => \s_axi_rdata_i[6]_i_5_n_0\,
O => D(6)
);
\s_axi_rdata_i[6]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AAA8"
)
port map (
I0 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I1 => p_15_in,
I2 => p_10_in,
I3 => ip2bus_wrack_int_d1_i_3_n_0,
I4 => \bus2ip_addr_i_reg[6]\,
O => \s_axi_rdata_i[6]_i_4_n_0\
);
\s_axi_rdata_i[6]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => p_15_in,
I3 => p_10_in,
I4 => ip2bus_wrack_int_d1_i_3_n_0,
O => \s_axi_rdata_i[6]_i_5_n_0\
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(7),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(7)
);
\s_axi_rdata_i[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(8),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(8)
);
\s_axi_rdata_i[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800080FF800080"
)
port map (
I0 => \Douta_reg[31]\(9),
I1 => \^sie_gen.sie_bit_gen[0].sie_reg[0]\,
I2 => \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg_n_0_[16]\,
I3 => \s_axi_rdata_i[31]_i_3_n_0\,
I4 => \bus2ip_addr_i_reg[2]\,
I5 => \bus2ip_addr_i_reg[6]\,
O => D(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0_shared_ram_ivar is
port (
Douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
interrupt_address : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_wrce : in STD_LOGIC_VECTOR ( 0 to 0 );
\bus2ip_addr_i_reg[5]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ivar_index_axi_clk : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_microblaze_0_axi_intc_0_shared_ram_ivar : entity is "shared_ram_ivar";
end system_microblaze_0_axi_intc_0_shared_ram_ivar;
architecture STRUCTURE of system_microblaze_0_axi_intc_0_shared_ram_ivar is
signal Doutb0 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ram_reg_0_15_0_0_n_1 : STD_LOGIC;
signal ram_reg_0_15_10_10_n_1 : STD_LOGIC;
signal ram_reg_0_15_11_11_n_1 : STD_LOGIC;
signal ram_reg_0_15_12_12_n_1 : STD_LOGIC;
signal ram_reg_0_15_13_13_n_1 : STD_LOGIC;
signal ram_reg_0_15_14_14_n_1 : STD_LOGIC;
signal ram_reg_0_15_15_15_n_1 : STD_LOGIC;
signal ram_reg_0_15_16_16_n_1 : STD_LOGIC;
signal ram_reg_0_15_17_17_n_1 : STD_LOGIC;
signal ram_reg_0_15_18_18_n_1 : STD_LOGIC;
signal ram_reg_0_15_19_19_n_1 : STD_LOGIC;
signal ram_reg_0_15_1_1_n_1 : STD_LOGIC;
signal ram_reg_0_15_20_20_n_1 : STD_LOGIC;
signal ram_reg_0_15_21_21_n_1 : STD_LOGIC;
signal ram_reg_0_15_22_22_n_1 : STD_LOGIC;
signal ram_reg_0_15_23_23_n_1 : STD_LOGIC;
signal ram_reg_0_15_24_24_n_1 : STD_LOGIC;
signal ram_reg_0_15_25_25_n_1 : STD_LOGIC;
signal ram_reg_0_15_26_26_n_1 : STD_LOGIC;
signal ram_reg_0_15_27_27_n_1 : STD_LOGIC;
signal ram_reg_0_15_28_28_n_1 : STD_LOGIC;
signal ram_reg_0_15_29_29_n_1 : STD_LOGIC;
signal ram_reg_0_15_2_2_n_1 : STD_LOGIC;
signal ram_reg_0_15_30_30_n_1 : STD_LOGIC;
signal ram_reg_0_15_31_31_n_1 : STD_LOGIC;
signal ram_reg_0_15_3_3_n_1 : STD_LOGIC;
signal ram_reg_0_15_4_4_n_1 : STD_LOGIC;
signal ram_reg_0_15_5_5_n_1 : STD_LOGIC;
signal ram_reg_0_15_6_6_n_1 : STD_LOGIC;
signal ram_reg_0_15_7_7_n_1 : STD_LOGIC;
signal ram_reg_0_15_8_8_n_1 : STD_LOGIC;
signal ram_reg_0_15_9_9_n_1 : STD_LOGIC;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_0_0 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_10_10 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_11_11 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_12_12 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_13_13 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_14_14 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_15_15 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_16_16 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_17_17 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_18_18 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_19_19 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_1_1 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_20_20 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_21_21 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_22_22 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_23_23 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_24_24 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_25_25 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_26_26 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_27_27 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_28_28 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_29_29 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_2_2 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_30_30 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_31_31 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_3_3 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_4_4 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_5_5 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_6_6 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_7_7 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_8_8 : label is "RAM16X1D";
attribute XILINX_LEGACY_PRIM of ram_reg_0_15_9_9 : label is "RAM16X1D";
begin
\Douta_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_0_0_n_1,
Q => Douta(0),
R => '0'
);
\Douta_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_10_10_n_1,
Q => Douta(10),
R => '0'
);
\Douta_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_11_11_n_1,
Q => Douta(11),
R => '0'
);
\Douta_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_12_12_n_1,
Q => Douta(12),
R => '0'
);
\Douta_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_13_13_n_1,
Q => Douta(13),
R => '0'
);
\Douta_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_14_14_n_1,
Q => Douta(14),
R => '0'
);
\Douta_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_15_15_n_1,
Q => Douta(15),
R => '0'
);
\Douta_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_16_16_n_1,
Q => Douta(16),
R => '0'
);
\Douta_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_17_17_n_1,
Q => Douta(17),
R => '0'
);
\Douta_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_18_18_n_1,
Q => Douta(18),
R => '0'
);
\Douta_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_19_19_n_1,
Q => Douta(19),
R => '0'
);
\Douta_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_1_1_n_1,
Q => Douta(1),
R => '0'
);
\Douta_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_20_20_n_1,
Q => Douta(20),
R => '0'
);
\Douta_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_21_21_n_1,
Q => Douta(21),
R => '0'
);
\Douta_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_22_22_n_1,
Q => Douta(22),
R => '0'
);
\Douta_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_23_23_n_1,
Q => Douta(23),
R => '0'
);
\Douta_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_24_24_n_1,
Q => Douta(24),
R => '0'
);
\Douta_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_25_25_n_1,
Q => Douta(25),
R => '0'
);
\Douta_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_26_26_n_1,
Q => Douta(26),
R => '0'
);
\Douta_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_27_27_n_1,
Q => Douta(27),
R => '0'
);
\Douta_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_28_28_n_1,
Q => Douta(28),
R => '0'
);
\Douta_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_29_29_n_1,
Q => Douta(29),
R => '0'
);
\Douta_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_2_2_n_1,
Q => Douta(2),
R => '0'
);
\Douta_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_30_30_n_1,
Q => Douta(30),
R => '0'
);
\Douta_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_31_31_n_1,
Q => Douta(31),
R => '0'
);
\Douta_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_3_3_n_1,
Q => Douta(3),
R => '0'
);
\Douta_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_4_4_n_1,
Q => Douta(4),
R => '0'
);
\Douta_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_5_5_n_1,
Q => Douta(5),
R => '0'
);
\Douta_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_6_6_n_1,
Q => Douta(6),
R => '0'
);
\Douta_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_7_7_n_1,
Q => Douta(7),
R => '0'
);
\Douta_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_8_8_n_1,
Q => Douta(8),
R => '0'
);
\Douta_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ram_reg_0_15_9_9_n_1,
Q => Douta(9),
R => '0'
);
\Doutb_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(0),
Q => interrupt_address(0),
R => '0'
);
\Doutb_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(10),
Q => interrupt_address(10),
R => '0'
);
\Doutb_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(11),
Q => interrupt_address(11),
R => '0'
);
\Doutb_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(12),
Q => interrupt_address(12),
R => '0'
);
\Doutb_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(13),
Q => interrupt_address(13),
R => '0'
);
\Doutb_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(14),
Q => interrupt_address(14),
R => '0'
);
\Doutb_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(15),
Q => interrupt_address(15),
R => '0'
);
\Doutb_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(16),
Q => interrupt_address(16),
R => '0'
);
\Doutb_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(17),
Q => interrupt_address(17),
R => '0'
);
\Doutb_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(18),
Q => interrupt_address(18),
R => '0'
);
\Doutb_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(19),
Q => interrupt_address(19),
R => '0'
);
\Doutb_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(1),
Q => interrupt_address(1),
R => '0'
);
\Doutb_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(20),
Q => interrupt_address(20),
R => '0'
);
\Doutb_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(21),
Q => interrupt_address(21),
R => '0'
);
\Doutb_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(22),
Q => interrupt_address(22),
R => '0'
);
\Doutb_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(23),
Q => interrupt_address(23),
R => '0'
);
\Doutb_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(24),
Q => interrupt_address(24),
R => '0'
);
\Doutb_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(25),
Q => interrupt_address(25),
R => '0'
);
\Doutb_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(26),
Q => interrupt_address(26),
R => '0'
);
\Doutb_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(27),
Q => interrupt_address(27),
R => '0'
);
\Doutb_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(28),
Q => interrupt_address(28),
R => '0'
);
\Doutb_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(29),
Q => interrupt_address(29),
R => '0'
);
\Doutb_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(2),
Q => interrupt_address(2),
R => '0'
);
\Doutb_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(30),
Q => interrupt_address(30),
R => '0'
);
\Doutb_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(31),
Q => interrupt_address(31),
R => '0'
);
\Doutb_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(3),
Q => interrupt_address(3),
R => '0'
);
\Doutb_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(4),
Q => interrupt_address(4),
R => '0'
);
\Doutb_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(5),
Q => interrupt_address(5),
R => '0'
);
\Doutb_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(6),
Q => interrupt_address(6),
R => '0'
);
\Doutb_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(7),
Q => interrupt_address(7),
R => '0'
);
\Doutb_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(8),
Q => interrupt_address(8),
R => '0'
);
\Doutb_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Doutb0(9),
Q => interrupt_address(9),
R => '0'
);
ram_reg_0_15_0_0: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(0),
DPO => Doutb0(0),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_0_0_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_10_10: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(10),
DPO => Doutb0(10),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_10_10_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_11_11: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(11),
DPO => Doutb0(11),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_11_11_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_12_12: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(12),
DPO => Doutb0(12),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_12_12_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_13_13: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(13),
DPO => Doutb0(13),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_13_13_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_14_14: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(14),
DPO => Doutb0(14),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_14_14_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_15_15: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(15),
DPO => Doutb0(15),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_15_15_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_16_16: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(16),
DPO => Doutb0(16),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_16_16_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_17_17: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(17),
DPO => Doutb0(17),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_17_17_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_18_18: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(18),
DPO => Doutb0(18),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_18_18_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_19_19: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(19),
DPO => Doutb0(19),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_19_19_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_1_1: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(1),
DPO => Doutb0(1),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_1_1_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_20_20: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(20),
DPO => Doutb0(20),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_20_20_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_21_21: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(21),
DPO => Doutb0(21),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_21_21_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_22_22: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(22),
DPO => Doutb0(22),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_22_22_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_23_23: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(23),
DPO => Doutb0(23),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_23_23_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_24_24: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(24),
DPO => Doutb0(24),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_24_24_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_25_25: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(25),
DPO => Doutb0(25),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_25_25_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_26_26: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(26),
DPO => Doutb0(26),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_26_26_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_27_27: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(27),
DPO => Doutb0(27),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_27_27_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_28_28: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(28),
DPO => Doutb0(28),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_28_28_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_29_29: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(29),
DPO => Doutb0(29),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_29_29_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_2_2: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(2),
DPO => Doutb0(2),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_2_2_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_30_30: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(30),
DPO => Doutb0(30),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_30_30_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_31_31: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(31),
DPO => Doutb0(31),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_31_31_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_3_3: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(3),
DPO => Doutb0(3),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_3_3_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_4_4: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"0000FFFF"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(4),
DPO => Doutb0(4),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_4_4_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_5_5: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(5),
DPO => Doutb0(5),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_5_5_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_6_6: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(6),
DPO => Doutb0(6),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_6_6_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_7_7: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(7),
DPO => Doutb0(7),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_7_7_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_8_8: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(8),
DPO => Doutb0(8),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_8_8_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
ram_reg_0_15_9_9: unisim.vcomponents.RAM32X1D
generic map(
INIT => X"00000000"
)
port map (
A0 => \bus2ip_addr_i_reg[5]\(0),
A1 => \bus2ip_addr_i_reg[5]\(1),
A2 => \bus2ip_addr_i_reg[5]\(2),
A3 => \bus2ip_addr_i_reg[5]\(3),
A4 => '0',
D => s_axi_wdata(9),
DPO => Doutb0(9),
DPRA0 => ivar_index_axi_clk(0),
DPRA1 => ivar_index_axi_clk(1),
DPRA2 => ivar_index_axi_clk(2),
DPRA3 => '0',
DPRA4 => '0',
SPO => ram_reg_0_15_9_9_n_1,
WCLK => s_axi_aclk,
WE => bus2ip_wrce(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0_intc_core is
port (
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]_0\ : out STD_LOGIC;
SS : out STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in14_in : out STD_LOGIC;
p_0_in11_in : out STD_LOGIC;
p_0_in8_in : out STD_LOGIC;
p_0_in5_in : out STD_LOGIC;
p_0_in2_in : out STD_LOGIC;
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]_0\ : out STD_LOGIC;
\IVR_GEN.ivr_reg[1]_0\ : out STD_LOGIC;
p_0_in28_in : out STD_LOGIC;
p_0_in26_in : out STD_LOGIC;
p_0_in24_in : out STD_LOGIC;
p_0_in22_in : out STD_LOGIC;
p_0_in20_in : out STD_LOGIC;
p_0_in19_in : out STD_LOGIC;
irq : out STD_LOGIC;
\REG_GEN[0].ier_reg[0]_0\ : out STD_LOGIC;
p_0_in118_in : out STD_LOGIC;
p_0_in107_in : out STD_LOGIC;
p_0_in96_in : out STD_LOGIC;
p_0_in85_in : out STD_LOGIC;
p_0_in74_in : out STD_LOGIC;
p_0_in64_in : out STD_LOGIC;
\REG_GEN[0].ier_reg[0]_1\ : out STD_LOGIC;
p_0_in59_in : out STD_LOGIC;
p_0_in57_in : out STD_LOGIC;
p_0_in55_in : out STD_LOGIC;
p_0_in53_in : out STD_LOGIC;
p_0_in51_in : out STD_LOGIC;
p_0_in49_in : out STD_LOGIC;
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0\ : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\IVR_GEN.ivr_reg[1]_1\ : out STD_LOGIC;
p_1_in29_in : out STD_LOGIC;
p_1_in27_in : out STD_LOGIC;
p_1_in25_in : out STD_LOGIC;
p_1_in23_in : out STD_LOGIC;
p_1_in21_in : out STD_LOGIC;
p_1_in : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]_0\ : out STD_LOGIC;
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_1\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
Douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
interrupt_address : out STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC;
intr : in STD_LOGIC_VECTOR ( 6 downto 0 );
Bus_RNW_reg_reg : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
Bus_RNW_reg_reg_4 : in STD_LOGIC;
Bus_RNW_reg_reg_5 : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]_0\ : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]_0\ : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]_0\ : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]_0\ : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]_0\ : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\ : in STD_LOGIC;
Bus_RNW_reg_reg_6 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\bus2ip_addr_i_reg[5]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
processor_ack : in STD_LOGIC_VECTOR ( 1 downto 0 );
Bus_RNW_reg_reg_7 : in STD_LOGIC;
Bus_RNW_reg_reg_8 : in STD_LOGIC;
Bus_RNW_reg_reg_9 : in STD_LOGIC;
Bus_RNW_reg_reg_10 : in STD_LOGIC;
Bus_RNW_reg_reg_11 : in STD_LOGIC;
Bus_RNW_reg_reg_12 : in STD_LOGIC;
Bus_RNW_reg_reg_13 : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
p_17_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_microblaze_0_axi_intc_0_intc_core : entity is "intc_core";
end system_microblaze_0_axi_intc_0_intc_core;
architecture STRUCTURE of system_microblaze_0_axi_intc_0_intc_core is
signal \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1_n_0\ : STD_LOGIC;
signal \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1_n_0\ : STD_LOGIC;
signal \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr[1]_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr[2]_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr[4]_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.intr_d1_reg_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr[5]_i_1_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.intr_d1_reg_n_0\ : STD_LOGIC;
signal \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg_n_0_[1]\ : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg_n_0_[1]\ : signal is "true";
signal \INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr[6]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[0]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[1]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[2]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[3]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[4]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[5]_i_1_n_0\ : STD_LOGIC;
signal \IPR_GEN.ipr[6]_i_1_n_0\ : STD_LOGIC;
signal \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_3_n_0\ : STD_LOGIC;
signal \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_4_n_0\ : STD_LOGIC;
signal \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2_n_0\ : STD_LOGIC;
signal \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0]\ : STD_LOGIC;
signal \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1]\ : STD_LOGIC;
signal \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1_n_0\ : STD_LOGIC;
signal \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[0]_i_1_n_0\ : STD_LOGIC;
signal \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[1]_i_1_n_0\ : STD_LOGIC;
signal \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[2]_i_1_n_0\ : STD_LOGIC;
signal \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[1]_0\ : STD_LOGIC;
signal \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\ : STD_LOGIC;
signal \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_1\ : STD_LOGIC;
signal \IVR_GEN.ivr[0]_i_2_n_0\ : STD_LOGIC;
signal \IVR_GEN.ivr[1]_i_1_n_0\ : STD_LOGIC;
signal \IVR_GEN.ivr[1]_i_2_n_0\ : STD_LOGIC;
signal \IVR_GEN.ivr[1]_i_3_n_0\ : STD_LOGIC;
signal \IVR_GEN.ivr[2]_i_1_n_0\ : STD_LOGIC;
signal \^ivr_gen.ivr_reg[1]_0\ : STD_LOGIC;
signal \^ivr_gen.ivr_reg[1]_1\ : STD_LOGIC;
signal Irq_i : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_3_n_0\ : STD_LOGIC;
signal \^reg_gen[0].iar_fast_mode_gen.iar_reg[0]_0\ : STD_LOGIC;
signal \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0]\ : STD_LOGIC;
signal \^reg_gen[0].ier_reg[0]_0\ : STD_LOGIC;
signal \^reg_gen[0].ier_reg[0]_1\ : STD_LOGIC;
signal \REG_GEN[0].isr[0]_i_2_n_0\ : STD_LOGIC;
signal \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_3_n_0\ : STD_LOGIC;
signal \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1]\ : STD_LOGIC;
signal \REG_GEN[1].isr[1]_i_2_n_0\ : STD_LOGIC;
signal \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_3_n_0\ : STD_LOGIC;
signal \REG_GEN[2].isr[2]_i_2_n_0\ : STD_LOGIC;
signal \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_3_n_0\ : STD_LOGIC;
signal \REG_GEN[3].isr[3]_i_2_n_0\ : STD_LOGIC;
signal \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_3_n_0\ : STD_LOGIC;
signal \REG_GEN[4].isr[4]_i_2_n_0\ : STD_LOGIC;
signal \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_3_n_0\ : STD_LOGIC;
signal \REG_GEN[5].isr[5]_i_2_n_0\ : STD_LOGIC;
signal \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_1_n_0\ : STD_LOGIC;
signal \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_3_n_0\ : STD_LOGIC;
signal \^reg_gen[6].iar_fast_mode_gen.iar_reg[6]_0\ : STD_LOGIC;
signal \REG_GEN[6].isr[6]_i_2_n_0\ : STD_LOGIC;
signal \^ss\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal ack_or : STD_LOGIC;
signal ack_or_i : STD_LOGIC;
signal ack_or_i_2_n_0 : STD_LOGIC;
signal current_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal first_ack : STD_LOGIC;
signal first_ack_active : STD_LOGIC;
signal hw_intr : STD_LOGIC_VECTOR ( 6 downto 0 );
signal idle_and_irq : STD_LOGIC;
signal idle_and_irq_d1 : STD_LOGIC;
signal in_idle : STD_LOGIC;
signal intr_d1 : STD_LOGIC;
signal intr_ff : STD_LOGIC_VECTOR ( 0 to 1 );
attribute async_reg of intr_ff : signal is "true";
signal irq_gen : STD_LOGIC;
signal irq_gen_i_1_n_0 : STD_LOGIC;
signal irq_gen_i_2_n_0 : STD_LOGIC;
signal ivar_index_axi_clk : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ivar_index_sample_en : STD_LOGIC;
signal ivar_index_sample_en_i : STD_LOGIC;
signal ivr_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \^p_0_in107_in\ : STD_LOGIC;
signal \^p_0_in118_in\ : STD_LOGIC;
signal \^p_0_in11_in\ : STD_LOGIC;
signal \^p_0_in14_in\ : STD_LOGIC;
signal \^p_0_in19_in\ : STD_LOGIC;
signal \^p_0_in20_in\ : STD_LOGIC;
signal \^p_0_in22_in\ : STD_LOGIC;
signal \^p_0_in24_in\ : STD_LOGIC;
signal \^p_0_in26_in\ : STD_LOGIC;
signal \^p_0_in28_in\ : STD_LOGIC;
signal \^p_0_in2_in\ : STD_LOGIC;
signal \^p_0_in49_in\ : STD_LOGIC;
signal \^p_0_in51_in\ : STD_LOGIC;
signal \^p_0_in53_in\ : STD_LOGIC;
signal \^p_0_in55_in\ : STD_LOGIC;
signal \^p_0_in57_in\ : STD_LOGIC;
signal \^p_0_in59_in\ : STD_LOGIC;
signal \^p_0_in5_in\ : STD_LOGIC;
signal \^p_0_in64_in\ : STD_LOGIC;
signal \^p_0_in74_in\ : STD_LOGIC;
signal \^p_0_in85_in\ : STD_LOGIC;
signal \^p_0_in8_in\ : STD_LOGIC;
signal \^p_0_in96_in\ : STD_LOGIC;
signal p_17_out : STD_LOGIC;
signal \^p_1_in\ : STD_LOGIC;
signal \^p_1_in21_in\ : STD_LOGIC;
signal \^p_1_in23_in\ : STD_LOGIC;
signal \^p_1_in25_in\ : STD_LOGIC;
signal \^p_1_in27_in\ : STD_LOGIC;
signal \^p_1_in29_in\ : STD_LOGIC;
signal \p_1_out__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute async_reg of \p_1_out__0\ : signal is "true";
signal p_21_out : STD_LOGIC;
signal p_25_out : STD_LOGIC;
signal p_29_out : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_33_out : STD_LOGIC;
signal p_37_out : STD_LOGIC;
signal p_3_in : STD_LOGIC;
signal p_41_out : STD_LOGIC;
signal p_42_out : STD_LOGIC;
signal p_43_out : STD_LOGIC;
signal p_44_out : STD_LOGIC;
signal p_45_out : STD_LOGIC;
signal p_46_out : STD_LOGIC;
signal p_47_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_in : STD_LOGIC;
signal p_5_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal second_ack : STD_LOGIC;
signal second_ack_sync_d1 : STD_LOGIC;
signal second_ack_sync_d2 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1\ : label is "soft_lutpair28";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of \INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1\ : label is "soft_lutpair27";
attribute ASYNC_REG_boolean of \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[0]\ : label is std.standard.true;
attribute KEEP of \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[0]\ : label is "yes";
attribute ASYNC_REG_boolean of \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[1]\ : label is std.standard.true;
attribute KEEP of \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of \IPR_GEN.ipr[3]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \IPR_GEN.ipr[5]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.idle_and_irq_d1_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_sample_en_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \IVR_GEN.ivr[1]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \IVR_GEN.ivr[1]_i_3\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \IVR_GEN.ivr[2]_i_1\ : label is "soft_lutpair27";
begin
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]_0\ <= \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[1]_0\;
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0\ <= \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\;
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_1\ <= \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_1\;
\IVR_GEN.ivr_reg[1]_0\ <= \^ivr_gen.ivr_reg[1]_0\;
\IVR_GEN.ivr_reg[1]_1\ <= \^ivr_gen.ivr_reg[1]_1\;
Q(0) <= \^q\(0);
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]_0\ <= \^reg_gen[0].iar_fast_mode_gen.iar_reg[0]_0\;
\REG_GEN[0].ier_reg[0]_0\ <= \^reg_gen[0].ier_reg[0]_0\;
\REG_GEN[0].ier_reg[0]_1\ <= \^reg_gen[0].ier_reg[0]_1\;
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]_0\ <= \^reg_gen[6].iar_fast_mode_gen.iar_reg[6]_0\;
SS(0) <= \^ss\(0);
p_0_in <= \^p_0_in\;
p_0_in107_in <= \^p_0_in107_in\;
p_0_in118_in <= \^p_0_in118_in\;
p_0_in11_in <= \^p_0_in11_in\;
p_0_in14_in <= \^p_0_in14_in\;
p_0_in19_in <= \^p_0_in19_in\;
p_0_in20_in <= \^p_0_in20_in\;
p_0_in22_in <= \^p_0_in22_in\;
p_0_in24_in <= \^p_0_in24_in\;
p_0_in26_in <= \^p_0_in26_in\;
p_0_in28_in <= \^p_0_in28_in\;
p_0_in2_in <= \^p_0_in2_in\;
p_0_in49_in <= \^p_0_in49_in\;
p_0_in51_in <= \^p_0_in51_in\;
p_0_in53_in <= \^p_0_in53_in\;
p_0_in55_in <= \^p_0_in55_in\;
p_0_in57_in <= \^p_0_in57_in\;
p_0_in59_in <= \^p_0_in59_in\;
p_0_in5_in <= \^p_0_in5_in\;
p_0_in64_in <= \^p_0_in64_in\;
p_0_in74_in <= \^p_0_in74_in\;
p_0_in85_in <= \^p_0_in85_in\;
p_0_in8_in <= \^p_0_in8_in\;
p_0_in96_in <= \^p_0_in96_in\;
p_1_in <= \^p_1_in\;
p_1_in21_in <= \^p_1_in21_in\;
p_1_in23_in <= \^p_1_in23_in\;
p_1_in25_in <= \^p_1_in25_in\;
p_1_in27_in <= \^p_1_in27_in\;
p_1_in29_in <= \^p_1_in29_in\;
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"32"
)
port map (
I0 => processor_ack(0),
I1 => processor_ack(1),
I2 => first_ack_active,
O => \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1_n_0\
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_active_i_1_n_0\,
Q => first_ack_active,
R => \^ss\(0)
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => processor_ack(0),
I1 => processor_ack(1),
O => \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1_n_0\
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.first_ack_i_1_n_0\,
Q => first_ack,
R => \^ss\(0)
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => first_ack_active,
I1 => processor_ack(1),
O => \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_i_1_n_0\
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_i_1_n_0\,
Q => second_ack,
R => \^ss\(0)
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_sync_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => second_ack,
Q => second_ack_sync_d1,
R => \^ss\(0)
);
\ACK_EN_SYNC_ON_AXI_CLK_GEN.NO_CASCADE_MASTER.second_ack_sync_d2_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => second_ack_sync_d1,
Q => second_ack_sync_d2,
R => \^ss\(0)
);
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\,
Q => \^reg_gen[0].ier_reg[0]_1\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]_0\,
Q => \^p_0_in59_in\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]_0\,
Q => \^p_0_in57_in\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]_0\,
Q => \^p_0_in55_in\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]_0\,
Q => \^p_0_in53_in\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]_0\,
Q => \^p_0_in51_in\,
R => '0'
);
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]_0\,
Q => \^p_0_in49_in\,
R => '0'
);
\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => hw_intr(0),
I1 => intr(0),
I2 => s_axi_aresetn,
I3 => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0]\,
O => \INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0\
);
\INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[0].LVL_DETECT_GEN.hw_intr[0]_i_1_n_0\,
Q => hw_intr(0),
R => '0'
);
\INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => intr(1),
Q => intr_ff(0),
R => '0'
);
\INTR_DETECT_GEN[1].ASYNC_GEN.intr_ff_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => intr_ff(0),
Q => intr_ff(1),
R => '0'
);
\INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AE00"
)
port map (
I0 => hw_intr(1),
I1 => intr_ff(1),
I2 => intr_d1,
I3 => s_axi_aresetn,
I4 => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1]\,
O => \INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr[1]_i_1_n_0\
);
\INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[1].EDGE_DETECT_GEN.hw_intr[1]_i_1_n_0\,
Q => hw_intr(1),
R => '0'
);
\INTR_DETECT_GEN[1].EDGE_DETECT_GEN.intr_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr_ff(1),
Q => intr_d1,
R => \^ss\(0)
);
\INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => hw_intr(2),
I1 => intr(2),
I2 => s_axi_aresetn,
I3 => p_2_in,
O => \INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr[2]_i_1_n_0\
);
\INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[2].LVL_DETECT_GEN.hw_intr[2]_i_1_n_0\,
Q => hw_intr(2),
R => '0'
);
\INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => hw_intr(3),
I1 => intr(3),
I2 => s_axi_aresetn,
I3 => p_3_in,
O => \INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1_n_0\
);
\INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[3].LVL_DETECT_GEN.hw_intr[3]_i_1_n_0\,
Q => hw_intr(3),
R => '0'
);
\INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AE00"
)
port map (
I0 => hw_intr(4),
I1 => intr(4),
I2 => \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.intr_d1_reg_n_0\,
I3 => s_axi_aresetn,
I4 => p_4_in,
O => \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr[4]_i_1_n_0\
);
\INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.hw_intr[4]_i_1_n_0\,
Q => hw_intr(4),
R => '0'
);
\INTR_DETECT_GEN[4].EDGE_DETECT_GEN.intr_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr(4),
Q => \INTR_DETECT_GEN[4].EDGE_DETECT_GEN.intr_d1_reg_n_0\,
R => \^ss\(0)
);
\INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AE00"
)
port map (
I0 => hw_intr(5),
I1 => intr(5),
I2 => \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.intr_d1_reg_n_0\,
I3 => s_axi_aresetn,
I4 => p_5_in,
O => \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr[5]_i_1_n_0\
);
\INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.hw_intr[5]_i_1_n_0\,
Q => hw_intr(5),
R => '0'
);
\INTR_DETECT_GEN[5].EDGE_DETECT_GEN.intr_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => intr(5),
Q => \INTR_DETECT_GEN[5].EDGE_DETECT_GEN.intr_d1_reg_n_0\,
R => \^ss\(0)
);
\INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => intr(6),
Q => \p_1_out__0\(0),
R => '0'
);
\INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \p_1_out__0\(0),
Q => \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg_n_0_[1]\,
R => '0'
);
\INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => hw_intr(6),
I1 => \INTR_DETECT_GEN[6].ASYNC_GEN.intr_ff_reg_n_0_[1]\,
I2 => s_axi_aresetn,
I3 => p_6_in,
O => \INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr[6]_i_1_n_0\
);
\INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INTR_DETECT_GEN[6].LVL_DETECT_GEN.hw_intr[6]_i_1_n_0\,
Q => hw_intr(6),
R => '0'
);
\IPR_GEN.ipr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^ivr_gen.ivr_reg[1]_1\,
I1 => \^ivr_gen.ivr_reg[1]_0\,
O => \IPR_GEN.ipr[0]_i_1_n_0\
);
\IPR_GEN.ipr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_1_in29_in\,
I1 => \^p_0_in28_in\,
O => \IPR_GEN.ipr[1]_i_1_n_0\
);
\IPR_GEN.ipr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_1_in27_in\,
I1 => \^p_0_in26_in\,
O => \IPR_GEN.ipr[2]_i_1_n_0\
);
\IPR_GEN.ipr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_1_in25_in\,
I1 => \^p_0_in24_in\,
O => \IPR_GEN.ipr[3]_i_1_n_0\
);
\IPR_GEN.ipr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_1_in23_in\,
I1 => \^p_0_in22_in\,
O => \IPR_GEN.ipr[4]_i_1_n_0\
);
\IPR_GEN.ipr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_1_in21_in\,
I1 => \^p_0_in20_in\,
O => \IPR_GEN.ipr[5]_i_1_n_0\
);
\IPR_GEN.ipr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_1_in\,
I1 => \^p_0_in19_in\,
O => \IPR_GEN.ipr[6]_i_1_n_0\
);
\IPR_GEN.ipr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[0]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(0),
R => \^ss\(0)
);
\IPR_GEN.ipr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[1]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(1),
R => \^ss\(0)
);
\IPR_GEN.ipr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[2]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(2),
R => \^ss\(0)
);
\IPR_GEN.ipr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[3]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(3),
R => \^ss\(0)
);
\IPR_GEN.ipr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[4]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(4),
R => \^ss\(0)
);
\IPR_GEN.ipr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[5]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(5),
R => \^ss\(0)
);
\IPR_GEN.ipr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IPR_GEN.ipr[6]_i_1_n_0\,
Q => \s_axi_rdata_i_reg[6]\(6),
R => \^ss\(0)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.Irq_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^ss\(0)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.Irq_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0]\,
I1 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1]\,
O => Irq_i
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.Irq_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Irq_i,
Q => irq,
R => \^ss\(0)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000737F404C"
)
port map (
I0 => first_ack,
I1 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0]\,
I2 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2_n_0\,
I3 => ack_or,
I4 => ivar_index_sample_en,
I5 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1]\,
O => current_state(0)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00C05500"
)
port map (
I0 => second_ack_sync_d2,
I1 => first_ack,
I2 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2_n_0\,
I3 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1]\,
I4 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0]\,
O => current_state(1)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFAFCFA0C0AFC0A0"
)
port map (
I0 => \^p_0_in14_in\,
I1 => \^p_0_in8_in\,
I2 => ivar_index_axi_clk(0),
I3 => ivar_index_axi_clk(1),
I4 => \^reg_gen[0].iar_fast_mode_gen.iar_reg[0]_0\,
I5 => \^p_0_in11_in\,
O => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_3_n_0\
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00CCF0AA"
)
port map (
I0 => \^p_0_in5_in\,
I1 => \^reg_gen[6].iar_fast_mode_gen.iar_reg[6]_0\,
I2 => \^p_0_in2_in\,
I3 => ivar_index_axi_clk(0),
I4 => ivar_index_axi_clk(1),
O => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_4_n_0\
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => current_state(0),
Q => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0]\,
R => \^ss\(0)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => current_state(1),
Q => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1]\,
R => \^ss\(0)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_3_n_0\,
I1 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state[1]_i_4_n_0\,
O => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg[1]_i_2_n_0\,
S => ivar_index_axi_clk(2)
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[0]\,
I1 => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.current_state_reg_n_0_[1]\,
O => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1_n_0\
);
\IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IRQ_LEVEL_GEN.IRQ_LEVEL_FAST_ON_AXI_CLK_GEN.in_idle_i_1_n_0\,
Q => in_idle,
R => \^ss\(0)
);
\IVAR_FAST_MODE_GEN.IVAR_REG_MEM_AXI_CLK_GEN.IVAR_REG_MEM_I\: entity work.system_microblaze_0_axi_intc_0_shared_ram_ivar
port map (
Douta(31 downto 0) => Douta(31 downto 0),
\bus2ip_addr_i_reg[5]\(3 downto 0) => \bus2ip_addr_i_reg[5]\(3 downto 0),
bus2ip_wrce(0) => bus2ip_wrce(0),
interrupt_address(31 downto 0) => interrupt_address(31 downto 0),
ivar_index_axi_clk(2 downto 0) => ivar_index_axi_clk(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0)
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.idle_and_irq_d1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\,
I1 => in_idle,
I2 => irq_gen,
O => idle_and_irq
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.idle_and_irq_d1_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => idle_and_irq,
Q => idle_and_irq_d1,
R => \^ss\(0)
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFF00008000"
)
port map (
I0 => \^q\(0),
I1 => irq_gen,
I2 => in_idle,
I3 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\,
I4 => idle_and_irq_d1,
I5 => ivar_index_axi_clk(0),
O => \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[0]_i_1_n_0\
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFF00008000"
)
port map (
I0 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[1]_0\,
I1 => irq_gen,
I2 => in_idle,
I3 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\,
I4 => idle_and_irq_d1,
I5 => ivar_index_axi_clk(1),
O => \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[1]_i_1_n_0\
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFF00008000"
)
port map (
I0 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_1\,
I1 => irq_gen,
I2 => in_idle,
I3 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\,
I4 => idle_and_irq_d1,
I5 => ivar_index_axi_clk(2),
O => \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[2]_i_1_n_0\
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[0]_i_1_n_0\,
Q => ivar_index_axi_clk(0),
R => \^ss\(0)
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[1]_i_1_n_0\,
Q => ivar_index_axi_clk(1),
R => \^ss\(0)
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk[2]_i_1_n_0\,
Q => ivar_index_axi_clk(2),
R => \^ss\(0)
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_sample_en_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => irq_gen,
I1 => in_idle,
I2 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\,
I3 => idle_and_irq_d1,
O => ivar_index_sample_en_i
);
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_sample_en_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ivar_index_sample_en_i,
Q => ivar_index_sample_en,
R => \^ss\(0)
);
\IVR_GEN.ivr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF002A002A002A"
)
port map (
I0 => \IVR_GEN.ivr[0]_i_2_n_0\,
I1 => \^p_0_in26_in\,
I2 => \^p_1_in27_in\,
I3 => \IPR_GEN.ipr[0]_i_1_n_0\,
I4 => \^p_1_in29_in\,
I5 => \^p_0_in28_in\,
O => ivr_in(0)
);
\IVR_GEN.ivr[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"88888888F888FFFF"
)
port map (
I0 => \^p_1_in25_in\,
I1 => \^p_0_in24_in\,
I2 => \^p_0_in20_in\,
I3 => \^p_1_in21_in\,
I4 => \IPR_GEN.ipr[6]_i_1_n_0\,
I5 => \IPR_GEN.ipr[4]_i_1_n_0\,
O => \IVR_GEN.ivr[0]_i_2_n_0\
);
\IVR_GEN.ivr[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555555F7F7F7"
)
port map (
I0 => s_axi_aresetn,
I1 => \IVR_GEN.ivr[1]_i_2_n_0\,
I2 => \IVR_GEN.ivr[1]_i_3_n_0\,
I3 => \^ivr_gen.ivr_reg[1]_0\,
I4 => \^ivr_gen.ivr_reg[1]_1\,
I5 => \IPR_GEN.ipr[1]_i_1_n_0\,
O => \IVR_GEN.ivr[1]_i_1_n_0\
);
\IVR_GEN.ivr[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^p_0_in20_in\,
I1 => \^p_1_in21_in\,
I2 => \^p_0_in22_in\,
I3 => \^p_1_in23_in\,
O => \IVR_GEN.ivr[1]_i_2_n_0\
);
\IVR_GEN.ivr[1]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \^p_0_in24_in\,
I1 => \^p_1_in25_in\,
I2 => \^p_0_in26_in\,
I3 => \^p_1_in27_in\,
O => \IVR_GEN.ivr[1]_i_3_n_0\
);
\IVR_GEN.ivr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_aresetn,
I1 => irq_gen_i_2_n_0,
O => \IVR_GEN.ivr[2]_i_1_n_0\
);
\IVR_GEN.ivr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => s_axi_aclk,
CE => '1',
D => ivr_in(0),
Q => \^q\(0),
S => \^ss\(0)
);
\IVR_GEN.ivr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IVR_GEN.ivr[1]_i_1_n_0\,
Q => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[1]_0\,
R => '0'
);
\IVR_GEN.ivr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \IVR_GEN.ivr[2]_i_1_n_0\,
Q => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_1\,
R => '0'
);
\REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_7,
I1 => \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_3_n_0\,
I2 => second_ack,
I3 => s_axi_wdata(0),
I4 => s_axi_aresetn,
I5 => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0]\,
O => \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_1_n_0\
);
\REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000040"
)
port map (
I0 => ivar_index_axi_clk(2),
I1 => \^reg_gen[0].iar_fast_mode_gen.iar_reg[0]_0\,
I2 => second_ack,
I3 => ivar_index_axi_clk(0),
I4 => ivar_index_axi_clk(1),
O => \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_3_n_0\
);
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[0].IAR_FAST_MODE_GEN.iar[0]_i_1_n_0\,
Q => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0]\,
R => '0'
);
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(0),
Q => \^reg_gen[0].iar_fast_mode_gen.iar_reg[0]_0\,
R => \^ss\(0)
);
\REG_GEN[0].ier[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^ivr_gen.ivr_reg[1]_0\,
I1 => s_axi_aresetn,
I2 => \^reg_gen[0].ier_reg[0]_1\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^reg_gen[0].ier_reg[0]_0\,
I5 => s_axi_wdata(0),
O => p_41_out
);
\REG_GEN[0].ier_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_41_out,
Q => \^ivr_gen.ivr_reg[1]_0\,
R => '0'
);
\REG_GEN[0].isr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0]\,
I1 => s_axi_aresetn,
O => p_48_out
);
\REG_GEN[0].isr[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(0),
I1 => s_axi_wdata(0),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^ivr_gen.ivr_reg[1]_1\,
O => \REG_GEN[0].isr[0]_i_2_n_0\
);
\REG_GEN[0].isr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[0].isr[0]_i_2_n_0\,
Q => \^ivr_gen.ivr_reg[1]_1\,
R => p_48_out
);
\REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_8,
I1 => \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_3_n_0\,
I2 => first_ack,
I3 => s_axi_wdata(1),
I4 => s_axi_aresetn,
I5 => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1]\,
O => \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_1_n_0\
);
\REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00400000"
)
port map (
I0 => ivar_index_axi_clk(2),
I1 => \^p_0_in14_in\,
I2 => first_ack,
I3 => ivar_index_axi_clk(1),
I4 => ivar_index_axi_clk(0),
O => \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_3_n_0\
);
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[1].IAR_FAST_MODE_GEN.iar[1]_i_1_n_0\,
Q => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1]\,
R => '0'
);
\REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(1),
Q => \^p_0_in14_in\,
R => \^ss\(0)
);
\REG_GEN[1].ier[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^p_0_in28_in\,
I1 => s_axi_aresetn,
I2 => \^p_0_in59_in\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^p_0_in118_in\,
I5 => s_axi_wdata(1),
O => p_37_out
);
\REG_GEN[1].ier_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_37_out,
Q => \^p_0_in28_in\,
R => '0'
);
\REG_GEN[1].isr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1]\,
I1 => s_axi_aresetn,
O => p_47_out
);
\REG_GEN[1].isr[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(1),
I1 => s_axi_wdata(1),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^p_1_in29_in\,
O => \REG_GEN[1].isr[1]_i_2_n_0\
);
\REG_GEN[1].isr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[1].isr[1]_i_2_n_0\,
Q => \^p_1_in29_in\,
R => p_47_out
);
\REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_9,
I1 => \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_3_n_0\,
I2 => second_ack,
I3 => s_axi_wdata(2),
I4 => s_axi_aresetn,
I5 => p_2_in,
O => \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_1_n_0\
);
\REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00400000"
)
port map (
I0 => ivar_index_axi_clk(2),
I1 => \^p_0_in11_in\,
I2 => second_ack,
I3 => ivar_index_axi_clk(0),
I4 => ivar_index_axi_clk(1),
O => \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_3_n_0\
);
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[2].IAR_FAST_MODE_GEN.iar[2]_i_1_n_0\,
Q => p_2_in,
R => '0'
);
\REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(2),
Q => \^p_0_in11_in\,
R => \^ss\(0)
);
\REG_GEN[2].ier[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^p_0_in26_in\,
I1 => s_axi_aresetn,
I2 => \^p_0_in57_in\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^p_0_in107_in\,
I5 => s_axi_wdata(2),
O => p_33_out
);
\REG_GEN[2].ier_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_33_out,
Q => \^p_0_in26_in\,
R => '0'
);
\REG_GEN[2].isr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => p_2_in,
I1 => s_axi_aresetn,
O => p_46_out
);
\REG_GEN[2].isr[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(2),
I1 => s_axi_wdata(2),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^p_1_in27_in\,
O => \REG_GEN[2].isr[2]_i_2_n_0\
);
\REG_GEN[2].isr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[2].isr[2]_i_2_n_0\,
Q => \^p_1_in27_in\,
R => p_46_out
);
\REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_10,
I1 => \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_3_n_0\,
I2 => second_ack,
I3 => s_axi_wdata(3),
I4 => s_axi_aresetn,
I5 => p_3_in,
O => \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_1_n_0\
);
\REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"08000000"
)
port map (
I0 => ivar_index_axi_clk(0),
I1 => ivar_index_axi_clk(1),
I2 => ivar_index_axi_clk(2),
I3 => second_ack,
I4 => \^p_0_in8_in\,
O => \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_3_n_0\
);
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[3].IAR_FAST_MODE_GEN.iar[3]_i_1_n_0\,
Q => p_3_in,
R => '0'
);
\REG_GEN[3].IMR_FAST_MODE_GEN.imr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(3),
Q => \^p_0_in8_in\,
R => \^ss\(0)
);
\REG_GEN[3].ier[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^p_0_in24_in\,
I1 => s_axi_aresetn,
I2 => \^p_0_in55_in\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^p_0_in96_in\,
I5 => s_axi_wdata(3),
O => p_29_out
);
\REG_GEN[3].ier_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_29_out,
Q => \^p_0_in24_in\,
R => '0'
);
\REG_GEN[3].isr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => p_3_in,
I1 => s_axi_aresetn,
O => p_45_out
);
\REG_GEN[3].isr[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(3),
I1 => s_axi_wdata(3),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^p_1_in25_in\,
O => \REG_GEN[3].isr[3]_i_2_n_0\
);
\REG_GEN[3].isr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[3].isr[3]_i_2_n_0\,
Q => \^p_1_in25_in\,
R => p_45_out
);
\REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_11,
I1 => \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_3_n_0\,
I2 => first_ack,
I3 => s_axi_wdata(4),
I4 => s_axi_aresetn,
I5 => p_4_in,
O => \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_1_n_0\
);
\REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => ivar_index_axi_clk(2),
I1 => \^p_0_in5_in\,
I2 => first_ack,
I3 => ivar_index_axi_clk(0),
I4 => ivar_index_axi_clk(1),
O => \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_3_n_0\
);
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[4].IAR_FAST_MODE_GEN.iar[4]_i_1_n_0\,
Q => p_4_in,
R => '0'
);
\REG_GEN[4].IMR_FAST_MODE_GEN.imr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(4),
Q => \^p_0_in5_in\,
R => \^ss\(0)
);
\REG_GEN[4].ier[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^p_0_in22_in\,
I1 => s_axi_aresetn,
I2 => \^p_0_in53_in\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^p_0_in85_in\,
I5 => s_axi_wdata(4),
O => p_25_out
);
\REG_GEN[4].ier_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_25_out,
Q => \^p_0_in22_in\,
R => '0'
);
\REG_GEN[4].isr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => p_4_in,
I1 => s_axi_aresetn,
O => p_44_out
);
\REG_GEN[4].isr[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(4),
I1 => s_axi_wdata(4),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^p_1_in23_in\,
O => \REG_GEN[4].isr[4]_i_2_n_0\
);
\REG_GEN[4].isr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[4].isr[4]_i_2_n_0\,
Q => \^p_1_in23_in\,
R => p_44_out
);
\REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_12,
I1 => \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_3_n_0\,
I2 => first_ack,
I3 => s_axi_wdata(5),
I4 => s_axi_aresetn,
I5 => p_5_in,
O => \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_1_n_0\
);
\REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => ivar_index_axi_clk(2),
I1 => \^p_0_in2_in\,
I2 => first_ack,
I3 => ivar_index_axi_clk(1),
I4 => ivar_index_axi_clk(0),
O => \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_3_n_0\
);
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[5].IAR_FAST_MODE_GEN.iar[5]_i_1_n_0\,
Q => p_5_in,
R => '0'
);
\REG_GEN[5].IMR_FAST_MODE_GEN.imr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(5),
Q => \^p_0_in2_in\,
R => \^ss\(0)
);
\REG_GEN[5].ier[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^p_0_in20_in\,
I1 => s_axi_aresetn,
I2 => \^p_0_in51_in\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^p_0_in74_in\,
I5 => s_axi_wdata(5),
O => p_21_out
);
\REG_GEN[5].ier_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_21_out,
Q => \^p_0_in20_in\,
R => '0'
);
\REG_GEN[5].isr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => p_5_in,
I1 => s_axi_aresetn,
O => p_43_out
);
\REG_GEN[5].isr[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(5),
I1 => s_axi_wdata(5),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^p_1_in21_in\,
O => \REG_GEN[5].isr[5]_i_2_n_0\
);
\REG_GEN[5].isr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[5].isr[5]_i_2_n_0\,
Q => \^p_1_in21_in\,
R => p_43_out
);
\REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EA400000"
)
port map (
I0 => Bus_RNW_reg_reg_13,
I1 => \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_3_n_0\,
I2 => second_ack,
I3 => s_axi_wdata(6),
I4 => s_axi_aresetn,
I5 => p_6_in,
O => \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_1_n_0\
);
\REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00800000"
)
port map (
I0 => ivar_index_axi_clk(2),
I1 => \^reg_gen[6].iar_fast_mode_gen.iar_reg[6]_0\,
I2 => second_ack,
I3 => ivar_index_axi_clk(0),
I4 => ivar_index_axi_clk(1),
O => \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_3_n_0\
);
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[6].IAR_FAST_MODE_GEN.iar[6]_i_1_n_0\,
Q => p_6_in,
R => '0'
);
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(6),
Q => \^reg_gen[6].iar_fast_mode_gen.iar_reg[6]_0\,
R => \^ss\(0)
);
\REG_GEN[6].ier[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0C0C080C0C0008"
)
port map (
I0 => \^p_0_in19_in\,
I1 => s_axi_aresetn,
I2 => \^p_0_in49_in\,
I3 => \bus2ip_wrce__0\(0),
I4 => \^p_0_in64_in\,
I5 => s_axi_wdata(6),
O => p_17_out
);
\REG_GEN[6].ier_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_17_out,
Q => \^p_0_in19_in\,
R => '0'
);
\REG_GEN[6].isr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => p_6_in,
I1 => s_axi_aresetn,
O => p_42_out
);
\REG_GEN[6].isr[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFCFFAAAA0C00"
)
port map (
I0 => hw_intr(6),
I1 => s_axi_wdata(6),
I2 => Bus_RNW_reg,
I3 => p_17_in,
I4 => \^p_0_in\,
I5 => \^p_1_in\,
O => \REG_GEN[6].isr[6]_i_2_n_0\
);
\REG_GEN[6].isr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \REG_GEN[6].isr[6]_i_2_n_0\,
Q => \^p_1_in\,
R => p_42_out
);
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg,
Q => \^reg_gen[0].ier_reg[0]_0\,
R => '0'
);
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_0,
Q => \^p_0_in118_in\,
R => '0'
);
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_1,
Q => \^p_0_in107_in\,
R => '0'
);
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_2,
Q => \^p_0_in96_in\,
R => '0'
);
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_3,
Q => \^p_0_in85_in\,
R => '0'
);
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_4,
Q => \^p_0_in74_in\,
R => '0'
);
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_5,
Q => \^p_0_in64_in\,
R => '0'
);
ack_or_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => ack_or_i_2_n_0,
I1 => p_6_in,
I2 => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg_n_0_[1]\,
I3 => p_3_in,
O => ack_or_i
);
ack_or_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => p_4_in,
I1 => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg_n_0_[0]\,
I2 => p_2_in,
I3 => p_5_in,
O => ack_or_i_2_n_0
);
ack_or_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ack_or_i,
Q => ack_or,
R => \^ss\(0)
);
irq_gen_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFF8F8F8"
)
port map (
I0 => \^p_0_in19_in\,
I1 => \^p_1_in\,
I2 => irq_gen_i_2_n_0,
I3 => \^p_0_in20_in\,
I4 => \^p_1_in21_in\,
I5 => \IPR_GEN.ipr[4]_i_1_n_0\,
O => irq_gen_i_1_n_0
);
irq_gen_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEEEFEEEFEEE"
)
port map (
I0 => \IPR_GEN.ipr[1]_i_1_n_0\,
I1 => \IPR_GEN.ipr[0]_i_1_n_0\,
I2 => \^p_1_in27_in\,
I3 => \^p_0_in26_in\,
I4 => \^p_1_in25_in\,
I5 => \^p_0_in24_in\,
O => irq_gen_i_2_n_0
);
irq_gen_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => irq_gen_i_1_n_0,
Q => irq_gen,
R => \^ss\(0)
);
\mer_int_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\,
Q => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_0\,
R => \^ss\(0)
);
\mer_int_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_reg_6,
Q => \^p_0_in\,
R => \^ss\(0)
);
\s_axi_rdata_i[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000800080008000"
)
port map (
I0 => \^q\(0),
I1 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[1]_0\,
I2 => \^ivar_index_sync_on_axi_clk_gen.ivar_index_axi_clk_reg[2]_1\,
I3 => \bus2ip_addr_i_reg[5]\(2),
I4 => \bus2ip_addr_i_reg[5]\(0),
I5 => \bus2ip_addr_i_reg[5]\(1),
O => \s_axi_rdata_i_reg[3]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0_slave_attachment is
port (
p_17_in : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
ip2bus_wrack_prev2 : out STD_LOGIC;
Or128_vec2stdlogic : out STD_LOGIC;
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\ : out STD_LOGIC;
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\ : out STD_LOGIC;
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\ : out STD_LOGIC;
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\ : out STD_LOGIC;
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\ : out STD_LOGIC;
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\ : out STD_LOGIC;
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_rdack_prev2 : out STD_LOGIC;
Or128_vec2stdlogic19_out : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\ : out STD_LOGIC;
\mer_int_reg[0]\ : out STD_LOGIC;
\mer_int_reg[1]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
ip2bus_wrack_int_d1 : in STD_LOGIC;
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\ : in STD_LOGIC;
p_0_in2_in : in STD_LOGIC;
p_0_in5_in : in STD_LOGIC;
p_0_in8_in : in STD_LOGIC;
p_0_in11_in : in STD_LOGIC;
p_0_in14_in : in STD_LOGIC;
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\ : in STD_LOGIC;
ip2bus_wrack : in STD_LOGIC;
ip2bus_rdack : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\Douta_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\IPR_GEN.ipr_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\REG_GEN[0].ier_reg[0]\ : in STD_LOGIC;
\REG_GEN[0].isr_reg[0]\ : in STD_LOGIC;
p_0_in28_in : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
p_0_in26_in : in STD_LOGIC;
p_1_in27_in : in STD_LOGIC;
p_0_in24_in : in STD_LOGIC;
p_1_in25_in : in STD_LOGIC;
p_0_in22_in : in STD_LOGIC;
p_1_in23_in : in STD_LOGIC;
p_0_in20_in : in STD_LOGIC;
p_1_in21_in : in STD_LOGIC;
p_0_in19_in : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\IVR_GEN.ivr_reg[0]\ : in STD_LOGIC;
\mer_int_reg[0]_0\ : in STD_LOGIC;
\IVR_GEN.ivr_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in : in STD_LOGIC;
\IVR_GEN.ivr_reg[1]\ : in STD_LOGIC;
\IVR_GEN.ivr_reg[2]\ : in STD_LOGIC;
ip2bus_rdack_int_d1 : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 6 downto 0 );
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1\ : in STD_LOGIC;
p_0_in118_in : in STD_LOGIC;
p_0_in107_in : in STD_LOGIC;
p_0_in96_in : in STD_LOGIC;
p_0_in85_in : in STD_LOGIC;
p_0_in74_in : in STD_LOGIC;
p_0_in64_in : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ : in STD_LOGIC;
p_0_in59_in : in STD_LOGIC;
p_0_in57_in : in STD_LOGIC;
p_0_in55_in : in STD_LOGIC;
p_0_in53_in : in STD_LOGIC;
p_0_in51_in : in STD_LOGIC;
p_0_in49_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_microblaze_0_axi_intc_0_slave_attachment : entity is "slave_attachment";
end system_microblaze_0_axi_intc_0_slave_attachment;
architecture STRUCTURE of system_microblaze_0_axi_intc_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal IP2Bus_Data : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal bus2ip_addr : STD_LOGIC_VECTOR ( 8 downto 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[5]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[6]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[7]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i_i_1_n_0 : STD_LOGIC;
signal bus2ip_rnw_i_reg_n_0 : STD_LOGIC;
signal ip2bus_error : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \s_axi_bresp_i[1]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_5_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_6_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \bus2ip_addr_i[8]_i_2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \s_axi_rdata_i[2]_i_3\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \s_axi_rdata_i[31]_i_4\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \s_axi_rdata_i[3]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \s_axi_rdata_i[4]_i_3\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \s_axi_rdata_i[5]_i_3\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \s_axi_rdata_i[6]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair16";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
s_axi_arready <= \^s_axi_arready\;
s_axi_bresp(0) <= \^s_axi_bresp\(0);
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1_n_0\
);
I_DECODER: entity work.system_microblaze_0_axi_intc_0_address_decoder
port map (
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\ => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\,
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\ => \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\,
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\ => \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\,
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\ => \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\,
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\ => \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\,
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\ => \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\,
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\ => \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\,
D(31 downto 0) => IP2Bus_Data(31 downto 0),
\Douta_reg[31]\(31 downto 0) => \Douta_reg[31]\(31 downto 0),
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
Or128_vec2stdlogic => Or128_vec2stdlogic,
Or128_vec2stdlogic19_out => Or128_vec2stdlogic19_out,
Q => start2,
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\ => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\,
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\ => \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\,
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]_0\ => \s_axi_rdata_i[0]_i_2_n_0\,
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\ => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\,
\REG_GEN[1].IMR_FAST_MODE_GEN.imr_reg[1]\ => \s_axi_rdata_i[1]_i_2_n_0\,
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\ => \REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\,
\REG_GEN[2].IMR_FAST_MODE_GEN.imr_reg[2]\ => \s_axi_rdata_i[2]_i_4_n_0\,
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\ => \REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\,
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\ => \REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\,
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\ => \REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\,
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\ => \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\,
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\ => \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\ => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1\ => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1\,
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\ => \SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\,
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\ => \SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\,
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\ => \SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\,
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\ => \SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\,
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\ => \SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\,
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\ => \SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\,
\bus2ip_addr_i_reg[2]\ => \s_axi_rdata_i[31]_i_4_n_0\,
\bus2ip_addr_i_reg[3]\ => \s_axi_rdata_i[2]_i_2_n_0\,
\bus2ip_addr_i_reg[3]_0\ => \s_axi_rdata_i[3]_i_2_n_0\,
\bus2ip_addr_i_reg[3]_1\ => \s_axi_rdata_i[4]_i_2_n_0\,
\bus2ip_addr_i_reg[3]_2\ => \s_axi_rdata_i[5]_i_2_n_0\,
\bus2ip_addr_i_reg[3]_3\ => \s_axi_rdata_i[6]_i_2_n_0\,
\bus2ip_addr_i_reg[5]\ => \s_axi_rdata_i[2]_i_3_n_0\,
\bus2ip_addr_i_reg[5]_0\ => \s_axi_rdata_i[3]_i_3_n_0\,
\bus2ip_addr_i_reg[5]_1\ => \s_axi_rdata_i[4]_i_3_n_0\,
\bus2ip_addr_i_reg[5]_2\ => \s_axi_rdata_i[5]_i_3_n_0\,
\bus2ip_addr_i_reg[5]_3\ => \s_axi_rdata_i[6]_i_3_n_0\,
\bus2ip_addr_i_reg[6]\ => \s_axi_rdata_i[31]_i_5_n_0\,
\bus2ip_addr_i_reg[8]\(6 downto 4) => bus2ip_addr(8 downto 6),
\bus2ip_addr_i_reg[8]\(3 downto 0) => \^q\(3 downto 0),
bus2ip_rnw_i_reg => bus2ip_rnw_i_reg_n_0,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_rdack_int_d1 => ip2bus_rdack_int_d1,
ip2bus_rdack_prev2 => ip2bus_rdack_prev2,
ip2bus_wrack => ip2bus_wrack,
ip2bus_wrack_int_d1 => ip2bus_wrack_int_d1,
ip2bus_wrack_prev2 => ip2bus_wrack_prev2,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
\mer_int_reg[0]\ => \mer_int_reg[0]\,
\mer_int_reg[0]_0\ => \mer_int_reg[0]_0\,
\mer_int_reg[1]\ => \mer_int_reg[1]\,
p_0_in => p_0_in,
p_0_in107_in => p_0_in107_in,
p_0_in118_in => p_0_in118_in,
p_0_in11_in => p_0_in11_in,
p_0_in14_in => p_0_in14_in,
p_0_in2_in => p_0_in2_in,
p_0_in49_in => p_0_in49_in,
p_0_in51_in => p_0_in51_in,
p_0_in53_in => p_0_in53_in,
p_0_in55_in => p_0_in55_in,
p_0_in57_in => p_0_in57_in,
p_0_in59_in => p_0_in59_in,
p_0_in5_in => p_0_in5_in,
p_0_in64_in => p_0_in64_in,
p_0_in74_in => p_0_in74_in,
p_0_in85_in => p_0_in85_in,
p_0_in8_in => p_0_in8_in,
p_0_in96_in => p_0_in96_in,
p_17_in => p_17_in,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0)
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(0),
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(1),
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(2),
O => \bus2ip_addr_i[4]_i_1_n_0\
);
\bus2ip_addr_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(3),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(3),
O => \bus2ip_addr_i[5]_i_1_n_0\
);
\bus2ip_addr_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(4),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(4),
O => \bus2ip_addr_i[6]_i_1_n_0\
);
\bus2ip_addr_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(5),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(5),
O => \bus2ip_addr_i[7]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020202"
)
port map (
I0 => s_axi_arvalid,
I1 => state(1),
I2 => state(0),
I3 => s_axi_awvalid,
I4 => s_axi_wvalid,
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFB0008"
)
port map (
I0 => s_axi_araddr(6),
I1 => s_axi_arvalid,
I2 => state(0),
I3 => state(1),
I4 => s_axi_awaddr(6),
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => \^q\(0),
R => rst
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => \^q\(1),
R => rst
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[4]_i_1_n_0\,
Q => \^q\(2),
R => rst
);
\bus2ip_addr_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[5]_i_1_n_0\,
Q => \^q\(3),
R => rst
);
\bus2ip_addr_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[6]_i_1_n_0\,
Q => bus2ip_addr(6),
R => rst
);
\bus2ip_addr_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[7]_i_1_n_0\,
Q => bus2ip_addr(7),
R => rst
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(8),
R => rst
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i_i_1_n_0
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => bus2ip_rnw_i_i_1_n_0,
Q => bus2ip_rnw_i_reg_n_0,
R => rst
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => rst
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => rst
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => SS(0),
Q => rst,
R => '0'
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => is_read,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I5 => ip2bus_rdack,
O => \^s_axi_arready\
);
\s_axi_bresp_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => ip2bus_error,
I1 => state(1),
I2 => state(0),
I3 => \^s_axi_bresp\(0),
O => \s_axi_bresp_i[1]_i_1_n_0\
);
\s_axi_bresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_bresp_i[1]_i_1_n_0\,
Q => \^s_axi_bresp\(0),
R => rst
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF02FF02FF0200"
)
port map (
I0 => \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\,
I1 => \^q\(2),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \s_axi_rdata_i[0]_i_3_n_0\,
I5 => \s_axi_rdata_i[0]_i_4_n_0\,
O => \s_axi_rdata_i[0]_i_2_n_0\
);
\s_axi_rdata_i[0]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8C008000"
)
port map (
I0 => \mer_int_reg[0]_0\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \IVR_GEN.ivr_reg[0]_0\(0),
O => \s_axi_rdata_i[0]_i_3_n_0\
);
\s_axi_rdata_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1505110114041000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(0),
I4 => \REG_GEN[0].ier_reg[0]\,
I5 => \REG_GEN[0].isr_reg[0]\,
O => \s_axi_rdata_i[0]_i_4_n_0\
);
\s_axi_rdata_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"02FF02FF02FF0200"
)
port map (
I0 => p_0_in14_in,
I1 => \^q\(2),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \s_axi_rdata_i[1]_i_3_n_0\,
I5 => \s_axi_rdata_i[1]_i_4_n_0\,
O => \s_axi_rdata_i[1]_i_2_n_0\
);
\s_axi_rdata_i[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"8C008000"
)
port map (
I0 => p_0_in,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \IVR_GEN.ivr_reg[1]\,
O => \s_axi_rdata_i[1]_i_3_n_0\
);
\s_axi_rdata_i[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1505110114041000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(1),
I4 => p_0_in28_in,
I5 => p_1_in29_in,
O => \s_axi_rdata_i[1]_i_4_n_0\
);
\s_axi_rdata_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A0A220228082000"
)
port map (
I0 => \s_axi_rdata_i[6]_i_6_n_0\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(2),
I4 => p_0_in26_in,
I5 => p_1_in27_in,
O => \s_axi_rdata_i[2]_i_2_n_0\
);
\s_axi_rdata_i[2]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(3),
I1 => \^q\(2),
I2 => \^q\(0),
I3 => \^q\(1),
O => \s_axi_rdata_i[2]_i_3_n_0\
);
\s_axi_rdata_i[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"00220C0000220000"
)
port map (
I0 => p_0_in11_in,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \IVR_GEN.ivr_reg[2]\,
O => \s_axi_rdata_i[2]_i_4_n_0\
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i[31]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"000AC000"
)
port map (
I0 => \^q\(0),
I1 => \IVR_GEN.ivr_reg[0]\,
I2 => \^q\(2),
I3 => \^q\(1),
I4 => \^q\(3),
O => \s_axi_rdata_i[31]_i_4_n_0\
);
\s_axi_rdata_i[31]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bus2ip_addr(6),
I1 => bus2ip_addr(8),
I2 => bus2ip_addr(7),
O => \s_axi_rdata_i[31]_i_5_n_0\
);
\s_axi_rdata_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A0A220228082000"
)
port map (
I0 => \s_axi_rdata_i[6]_i_6_n_0\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(3),
I4 => p_0_in24_in,
I5 => p_1_in25_in,
O => \s_axi_rdata_i[3]_i_2_n_0\
);
\s_axi_rdata_i[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(2),
I3 => p_0_in8_in,
O => \s_axi_rdata_i[3]_i_3_n_0\
);
\s_axi_rdata_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A0A220228082000"
)
port map (
I0 => \s_axi_rdata_i[6]_i_6_n_0\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(4),
I4 => p_0_in22_in,
I5 => p_1_in23_in,
O => \s_axi_rdata_i[4]_i_2_n_0\
);
\s_axi_rdata_i[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(2),
I3 => p_0_in5_in,
O => \s_axi_rdata_i[4]_i_3_n_0\
);
\s_axi_rdata_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A0A220228082000"
)
port map (
I0 => \s_axi_rdata_i[6]_i_6_n_0\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(5),
I4 => p_0_in20_in,
I5 => p_1_in21_in,
O => \s_axi_rdata_i[5]_i_2_n_0\
);
\s_axi_rdata_i[5]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(2),
I3 => p_0_in2_in,
O => \s_axi_rdata_i[5]_i_3_n_0\
);
\s_axi_rdata_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A0A220228082000"
)
port map (
I0 => \s_axi_rdata_i[6]_i_6_n_0\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \IPR_GEN.ipr_reg[6]\(6),
I4 => p_0_in19_in,
I5 => p_1_in,
O => \s_axi_rdata_i[6]_i_2_n_0\
);
\s_axi_rdata_i[6]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(2),
I3 => \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\,
O => \s_axi_rdata_i[6]_i_3_n_0\
);
\s_axi_rdata_i[6]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(2),
I1 => \^q\(3),
O => \s_axi_rdata_i[6]_i_6_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(0),
Q => s_axi_rdata(0),
R => rst
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(10),
Q => s_axi_rdata(10),
R => rst
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(11),
Q => s_axi_rdata(11),
R => rst
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(12),
Q => s_axi_rdata(12),
R => rst
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(13),
Q => s_axi_rdata(13),
R => rst
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(14),
Q => s_axi_rdata(14),
R => rst
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(15),
Q => s_axi_rdata(15),
R => rst
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(16),
Q => s_axi_rdata(16),
R => rst
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(17),
Q => s_axi_rdata(17),
R => rst
);
\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(18),
Q => s_axi_rdata(18),
R => rst
);
\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(19),
Q => s_axi_rdata(19),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(1),
Q => s_axi_rdata(1),
R => rst
);
\s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(20),
Q => s_axi_rdata(20),
R => rst
);
\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(21),
Q => s_axi_rdata(21),
R => rst
);
\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(22),
Q => s_axi_rdata(22),
R => rst
);
\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(23),
Q => s_axi_rdata(23),
R => rst
);
\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(24),
Q => s_axi_rdata(24),
R => rst
);
\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(25),
Q => s_axi_rdata(25),
R => rst
);
\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(26),
Q => s_axi_rdata(26),
R => rst
);
\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(27),
Q => s_axi_rdata(27),
R => rst
);
\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(28),
Q => s_axi_rdata(28),
R => rst
);
\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(29),
Q => s_axi_rdata(29),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(2),
Q => s_axi_rdata(2),
R => rst
);
\s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(30),
Q => s_axi_rdata(30),
R => rst
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(31),
Q => s_axi_rdata(31),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(3),
Q => s_axi_rdata(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(4),
Q => s_axi_rdata(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(5),
Q => s_axi_rdata(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(6),
Q => s_axi_rdata(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(7),
Q => s_axi_rdata(7),
R => rst
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(8),
Q => s_axi_rdata(8),
R => rst
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => IP2Bus_Data(9),
Q => s_axi_rdata(9),
R => rst
);
\s_axi_rresp_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"070F0F0F"
)
port map (
I0 => s_axi_wstrb(1),
I1 => s_axi_wstrb(2),
I2 => bus2ip_rnw_i_reg_n_0,
I3 => s_axi_wstrb(0),
I4 => s_axi_wstrb(3),
O => ip2bus_error
);
\s_axi_rresp_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => ip2bus_error,
Q => s_axi_rresp(0),
R => rst
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => rst
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => is_write_reg_n_0,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I5 => ip2bus_wrack,
O => \^s_axi_wready\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000F0008"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => state(1),
I3 => state(0),
I4 => s_axi_arvalid,
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => rst
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"55FFE4E4"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => \^s_axi_wready\,
I3 => \state1__2\,
I4 => state(0),
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"3AFF3AF0"
)
port map (
I0 => \^s_axi_arready\,
I1 => \state1__2\,
I2 => state(1),
I3 => state(0),
I4 => \state[1]_i_3_n_0\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0_axi_lite_ipif is
port (
p_17_in : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 0 to 0 );
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 0 to 0 );
ip2bus_wrack_prev2 : out STD_LOGIC;
Or128_vec2stdlogic : out STD_LOGIC;
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\ : out STD_LOGIC;
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\ : out STD_LOGIC;
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\ : out STD_LOGIC;
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\ : out STD_LOGIC;
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\ : out STD_LOGIC;
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\ : out STD_LOGIC;
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_rdack_prev2 : out STD_LOGIC;
Or128_vec2stdlogic19_out : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\ : out STD_LOGIC;
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\ : out STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\ : out STD_LOGIC;
\mer_int_reg[0]\ : out STD_LOGIC;
\mer_int_reg[1]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
ip2bus_wrack_int_d1 : in STD_LOGIC;
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\ : in STD_LOGIC;
p_0_in2_in : in STD_LOGIC;
p_0_in5_in : in STD_LOGIC;
p_0_in8_in : in STD_LOGIC;
p_0_in11_in : in STD_LOGIC;
p_0_in14_in : in STD_LOGIC;
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\ : in STD_LOGIC;
ip2bus_wrack : in STD_LOGIC;
ip2bus_rdack : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\Douta_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\IPR_GEN.ipr_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\REG_GEN[0].ier_reg[0]\ : in STD_LOGIC;
\REG_GEN[0].isr_reg[0]\ : in STD_LOGIC;
p_0_in28_in : in STD_LOGIC;
p_1_in29_in : in STD_LOGIC;
p_0_in26_in : in STD_LOGIC;
p_1_in27_in : in STD_LOGIC;
p_0_in24_in : in STD_LOGIC;
p_1_in25_in : in STD_LOGIC;
p_0_in22_in : in STD_LOGIC;
p_1_in23_in : in STD_LOGIC;
p_0_in20_in : in STD_LOGIC;
p_1_in21_in : in STD_LOGIC;
p_0_in19_in : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\IVR_GEN.ivr_reg[0]\ : in STD_LOGIC;
\mer_int_reg[0]_0\ : in STD_LOGIC;
\IVR_GEN.ivr_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_0_in : in STD_LOGIC;
\IVR_GEN.ivr_reg[1]\ : in STD_LOGIC;
\IVR_GEN.ivr_reg[2]\ : in STD_LOGIC;
ip2bus_rdack_int_d1 : in STD_LOGIC;
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 6 downto 0 );
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\ : in STD_LOGIC;
p_0_in118_in : in STD_LOGIC;
p_0_in107_in : in STD_LOGIC;
p_0_in96_in : in STD_LOGIC;
p_0_in85_in : in STD_LOGIC;
p_0_in74_in : in STD_LOGIC;
p_0_in64_in : in STD_LOGIC;
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ : in STD_LOGIC;
p_0_in59_in : in STD_LOGIC;
p_0_in57_in : in STD_LOGIC;
p_0_in55_in : in STD_LOGIC;
p_0_in53_in : in STD_LOGIC;
p_0_in51_in : in STD_LOGIC;
p_0_in49_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_microblaze_0_axi_intc_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_microblaze_0_axi_intc_0_axi_lite_ipif;
architecture STRUCTURE of system_microblaze_0_axi_intc_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_microblaze_0_axi_intc_0_slave_attachment
port map (
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\ => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ => \CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\,
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\ => \CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\,
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\ => \CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\,
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\ => \CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\,
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\ => \CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\,
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\ => \CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\,
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\ => \CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\,
\Douta_reg[31]\(31 downto 0) => \Douta_reg[31]\(31 downto 0),
\IPR_GEN.ipr_reg[6]\(6 downto 0) => \IPR_GEN.ipr_reg[6]\(6 downto 0),
\IVR_GEN.ivr_reg[0]\ => \IVR_GEN.ivr_reg[0]\,
\IVR_GEN.ivr_reg[0]_0\(0) => \IVR_GEN.ivr_reg[0]_0\(0),
\IVR_GEN.ivr_reg[1]\ => \IVR_GEN.ivr_reg[1]\,
\IVR_GEN.ivr_reg[2]\ => \IVR_GEN.ivr_reg[2]\,
Or128_vec2stdlogic => Or128_vec2stdlogic,
Or128_vec2stdlogic19_out => Or128_vec2stdlogic19_out,
Q(3 downto 0) => Q(3 downto 0),
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\ => \REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\,
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\ => \REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\,
\REG_GEN[0].ier_reg[0]\ => \REG_GEN[0].ier_reg[0]\,
\REG_GEN[0].isr_reg[0]\ => \REG_GEN[0].isr_reg[0]\,
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\ => \REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\,
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\ => \REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\,
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\ => \REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\,
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\ => \REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\,
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\ => \REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\,
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\ => \REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\,
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\ => \REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ => Bus_RNW_reg,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\ => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_1\ => \SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\,
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\ => \SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\,
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\ => \SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\,
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\ => \SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\,
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\ => \SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\,
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\ => \SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\,
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\ => \SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\,
SS(0) => SS(0),
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
ip2bus_rdack => ip2bus_rdack,
ip2bus_rdack_int_d1 => ip2bus_rdack_int_d1,
ip2bus_rdack_prev2 => ip2bus_rdack_prev2,
ip2bus_wrack => ip2bus_wrack,
ip2bus_wrack_int_d1 => ip2bus_wrack_int_d1,
ip2bus_wrack_prev2 => ip2bus_wrack_prev2,
\mer_int_reg[0]\ => \mer_int_reg[0]\,
\mer_int_reg[0]_0\ => \mer_int_reg[0]_0\,
\mer_int_reg[1]\ => \mer_int_reg[1]\,
p_0_in => p_0_in,
p_0_in107_in => p_0_in107_in,
p_0_in118_in => p_0_in118_in,
p_0_in11_in => p_0_in11_in,
p_0_in14_in => p_0_in14_in,
p_0_in19_in => p_0_in19_in,
p_0_in20_in => p_0_in20_in,
p_0_in22_in => p_0_in22_in,
p_0_in24_in => p_0_in24_in,
p_0_in26_in => p_0_in26_in,
p_0_in28_in => p_0_in28_in,
p_0_in2_in => p_0_in2_in,
p_0_in49_in => p_0_in49_in,
p_0_in51_in => p_0_in51_in,
p_0_in53_in => p_0_in53_in,
p_0_in55_in => p_0_in55_in,
p_0_in57_in => p_0_in57_in,
p_0_in59_in => p_0_in59_in,
p_0_in5_in => p_0_in5_in,
p_0_in64_in => p_0_in64_in,
p_0_in74_in => p_0_in74_in,
p_0_in85_in => p_0_in85_in,
p_0_in8_in => p_0_in8_in,
p_0_in96_in => p_0_in96_in,
p_17_in => p_17_in,
p_1_in => p_1_in,
p_1_in21_in => p_1_in21_in,
p_1_in23_in => p_1_in23_in,
p_1_in25_in => p_1_in25_in,
p_1_in27_in => p_1_in27_in,
p_1_in29_in => p_1_in29_in,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(6 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(6 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => s_axi_bresp(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => s_axi_rresp(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0_axi_intc is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
intr : in STD_LOGIC_VECTOR ( 6 downto 0 );
processor_clk : in STD_LOGIC;
processor_rst : in STD_LOGIC;
irq : out STD_LOGIC;
processor_ack : in STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt_address : out STD_LOGIC_VECTOR ( 31 downto 0 );
irq_in : in STD_LOGIC;
interrupt_address_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
processor_ack_out : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute C_ASYNC_INTR : integer;
attribute C_ASYNC_INTR of system_microblaze_0_axi_intc_0_axi_intc : entity is -62;
attribute C_CASCADE_MASTER : integer;
attribute C_CASCADE_MASTER of system_microblaze_0_axi_intc_0_axi_intc : entity is 0;
attribute C_DISABLE_SYNCHRONIZERS : integer;
attribute C_DISABLE_SYNCHRONIZERS of system_microblaze_0_axi_intc_0_axi_intc : entity is 0;
attribute C_ENABLE_ASYNC : integer;
attribute C_ENABLE_ASYNC of system_microblaze_0_axi_intc_0_axi_intc : entity is 0;
attribute C_EN_CASCADE_MODE : integer;
attribute C_EN_CASCADE_MODE of system_microblaze_0_axi_intc_0_axi_intc : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_microblaze_0_axi_intc_0_axi_intc : entity is "artix7";
attribute C_HAS_CIE : integer;
attribute C_HAS_CIE of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_HAS_FAST : integer;
attribute C_HAS_FAST of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_HAS_ILR : integer;
attribute C_HAS_ILR of system_microblaze_0_axi_intc_0_axi_intc : entity is 0;
attribute C_HAS_IPR : integer;
attribute C_HAS_IPR of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_HAS_IVR : integer;
attribute C_HAS_IVR of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_HAS_SIE : integer;
attribute C_HAS_SIE of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_INSTANCE : string;
attribute C_INSTANCE of system_microblaze_0_axi_intc_0_axi_intc : entity is "system_microblaze_0_axi_intc_0";
attribute C_IRQ_ACTIVE : string;
attribute C_IRQ_ACTIVE of system_microblaze_0_axi_intc_0_axi_intc : entity is "1'b1";
attribute C_IRQ_IS_LEVEL : integer;
attribute C_IRQ_IS_LEVEL of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_IVAR_RESET_VALUE : integer;
attribute C_IVAR_RESET_VALUE of system_microblaze_0_axi_intc_0_axi_intc : entity is 16;
attribute C_KIND_OF_EDGE : integer;
attribute C_KIND_OF_EDGE of system_microblaze_0_axi_intc_0_axi_intc : entity is -1;
attribute C_KIND_OF_INTR : integer;
attribute C_KIND_OF_INTR of system_microblaze_0_axi_intc_0_axi_intc : entity is -78;
attribute C_KIND_OF_LVL : integer;
attribute C_KIND_OF_LVL of system_microblaze_0_axi_intc_0_axi_intc : entity is -1;
attribute C_MB_CLK_NOT_CONNECTED : integer;
attribute C_MB_CLK_NOT_CONNECTED of system_microblaze_0_axi_intc_0_axi_intc : entity is 1;
attribute C_NUM_INTR_INPUTS : integer;
attribute C_NUM_INTR_INPUTS of system_microblaze_0_axi_intc_0_axi_intc : entity is 7;
attribute C_NUM_SW_INTR : integer;
attribute C_NUM_SW_INTR of system_microblaze_0_axi_intc_0_axi_intc : entity is 0;
attribute C_NUM_SYNC_FF : integer;
attribute C_NUM_SYNC_FF of system_microblaze_0_axi_intc_0_axi_intc : entity is 2;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_microblaze_0_axi_intc_0_axi_intc : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_microblaze_0_axi_intc_0_axi_intc : entity is 32;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_microblaze_0_axi_intc_0_axi_intc : entity is "axi_intc";
attribute hdl : string;
attribute hdl of system_microblaze_0_axi_intc_0_axi_intc : entity is "VHDL";
attribute imp_netlist : string;
attribute imp_netlist of system_microblaze_0_axi_intc_0_axi_intc : entity is "TRUE";
attribute ip_group : string;
attribute ip_group of system_microblaze_0_axi_intc_0_axi_intc : entity is "LOGICORE";
attribute iptype : string;
attribute iptype of system_microblaze_0_axi_intc_0_axi_intc : entity is "PERIPHERAL";
attribute run_ngcbuild : string;
attribute run_ngcbuild of system_microblaze_0_axi_intc_0_axi_intc : entity is "TRUE";
attribute style : string;
attribute style of system_microblaze_0_axi_intc_0_axi_intc : entity is "HDL";
end system_microblaze_0_axi_intc_0_axi_intc;
architecture STRUCTURE of system_microblaze_0_axi_intc_0_axi_intc is
signal \<const0>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_10 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_26 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_27 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_28 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_29 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_30 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_31 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_32 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_33 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_34 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_35 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_36 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_37 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_38 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_39 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_40 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_41 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_8 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_9 : STD_LOGIC;
signal Douta : STD_LOGIC_VECTOR ( 31 downto 0 );
signal INTC_CORE_I_n_0 : STD_LOGIC;
signal INTC_CORE_I_n_16 : STD_LOGIC;
signal INTC_CORE_I_n_23 : STD_LOGIC;
signal INTC_CORE_I_n_30 : STD_LOGIC;
signal INTC_CORE_I_n_32 : STD_LOGIC;
signal INTC_CORE_I_n_39 : STD_LOGIC;
signal INTC_CORE_I_n_40 : STD_LOGIC;
signal INTC_CORE_I_n_41 : STD_LOGIC;
signal INTC_CORE_I_n_42 : STD_LOGIC;
signal INTC_CORE_I_n_7 : STD_LOGIC;
signal INTC_CORE_I_n_8 : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/p_17_in\ : STD_LOGIC;
signal Or128_vec2stdlogic : STD_LOGIC;
signal Or128_vec2stdlogic19_out : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 5 downto 2 );
signal bus2ip_wrce : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \bus2ip_wrce__0\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal ip2bus_rdack : STD_LOGIC;
signal ip2bus_rdack_int_d1 : STD_LOGIC;
signal ip2bus_rdack_prev2 : STD_LOGIC;
signal ip2bus_wrack : STD_LOGIC;
signal ip2bus_wrack_int_d1 : STD_LOGIC;
signal ip2bus_wrack_prev2 : STD_LOGIC;
signal ipr : STD_LOGIC_VECTOR ( 6 downto 0 );
signal p_0_in : STD_LOGIC;
signal p_0_in107_in : STD_LOGIC;
signal p_0_in118_in : STD_LOGIC;
signal p_0_in11_in : STD_LOGIC;
signal p_0_in14_in : STD_LOGIC;
signal p_0_in19_in : STD_LOGIC;
signal p_0_in20_in : STD_LOGIC;
signal p_0_in22_in : STD_LOGIC;
signal p_0_in24_in : STD_LOGIC;
signal p_0_in26_in : STD_LOGIC;
signal p_0_in28_in : STD_LOGIC;
signal p_0_in2_in : STD_LOGIC;
signal p_0_in49_in : STD_LOGIC;
signal p_0_in51_in : STD_LOGIC;
signal p_0_in53_in : STD_LOGIC;
signal p_0_in55_in : STD_LOGIC;
signal p_0_in57_in : STD_LOGIC;
signal p_0_in59_in : STD_LOGIC;
signal p_0_in5_in : STD_LOGIC;
signal p_0_in64_in : STD_LOGIC;
signal p_0_in74_in : STD_LOGIC;
signal p_0_in85_in : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
signal p_0_in96_in : STD_LOGIC;
signal p_0_in_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_1_in21_in : STD_LOGIC;
signal p_1_in23_in : STD_LOGIC;
signal p_1_in25_in : STD_LOGIC;
signal p_1_in27_in : STD_LOGIC;
signal p_1_in29_in : STD_LOGIC;
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_rresp\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
processor_ack_out(1) <= \<const0>\;
processor_ack_out(0) <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \^s_axi_bresp\(1);
s_axi_bresp(0) <= \<const0>\;
s_axi_rresp(1) <= \^s_axi_rresp\(1);
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.system_microblaze_0_axi_intc_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]\ => AXI_LITE_IPIF_I_n_33,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ => INTC_CORE_I_n_23,
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]\ => AXI_LITE_IPIF_I_n_34,
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]\ => AXI_LITE_IPIF_I_n_35,
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]\ => AXI_LITE_IPIF_I_n_36,
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]\ => AXI_LITE_IPIF_I_n_37,
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]\ => AXI_LITE_IPIF_I_n_38,
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]\ => AXI_LITE_IPIF_I_n_39,
\Douta_reg[31]\(31 downto 0) => Douta(31 downto 0),
\IPR_GEN.ipr_reg[6]\(6 downto 0) => ipr(6 downto 0),
\IVR_GEN.ivr_reg[0]\ => INTC_CORE_I_n_39,
\IVR_GEN.ivr_reg[0]_0\(0) => INTC_CORE_I_n_40,
\IVR_GEN.ivr_reg[1]\ => INTC_CORE_I_n_41,
\IVR_GEN.ivr_reg[2]\ => INTC_CORE_I_n_42,
Or128_vec2stdlogic => Or128_vec2stdlogic,
Or128_vec2stdlogic19_out => Or128_vec2stdlogic19_out,
Q(3 downto 0) => bus2ip_addr(5 downto 2),
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]\ => AXI_LITE_IPIF_I_n_14,
\REG_GEN[0].IMR_FAST_MODE_GEN.imr_reg[0]\ => INTC_CORE_I_n_0,
\REG_GEN[0].ier_reg[0]\ => INTC_CORE_I_n_8,
\REG_GEN[0].isr_reg[0]\ => INTC_CORE_I_n_32,
\REG_GEN[1].IAR_FAST_MODE_GEN.iar_reg[1]\ => AXI_LITE_IPIF_I_n_13,
\REG_GEN[2].IAR_FAST_MODE_GEN.iar_reg[2]\ => AXI_LITE_IPIF_I_n_12,
\REG_GEN[3].IAR_FAST_MODE_GEN.iar_reg[3]\ => AXI_LITE_IPIF_I_n_11,
\REG_GEN[4].IAR_FAST_MODE_GEN.iar_reg[4]\ => AXI_LITE_IPIF_I_n_10,
\REG_GEN[5].IAR_FAST_MODE_GEN.iar_reg[5]\ => AXI_LITE_IPIF_I_n_9,
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]\ => AXI_LITE_IPIF_I_n_8,
\REG_GEN[6].IMR_FAST_MODE_GEN.imr_reg[6]\ => INTC_CORE_I_n_7,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]\ => AXI_LITE_IPIF_I_n_26,
\SIE_GEN.SIE_BIT_GEN[0].sie_reg[0]_0\ => INTC_CORE_I_n_16,
\SIE_GEN.SIE_BIT_GEN[1].sie_reg[1]\ => AXI_LITE_IPIF_I_n_27,
\SIE_GEN.SIE_BIT_GEN[2].sie_reg[2]\ => AXI_LITE_IPIF_I_n_28,
\SIE_GEN.SIE_BIT_GEN[3].sie_reg[3]\ => AXI_LITE_IPIF_I_n_29,
\SIE_GEN.SIE_BIT_GEN[4].sie_reg[4]\ => AXI_LITE_IPIF_I_n_30,
\SIE_GEN.SIE_BIT_GEN[5].sie_reg[5]\ => AXI_LITE_IPIF_I_n_31,
\SIE_GEN.SIE_BIT_GEN[6].sie_reg[6]\ => AXI_LITE_IPIF_I_n_32,
SS(0) => p_0_in,
bus2ip_wrce(1) => bus2ip_wrce(8),
bus2ip_wrce(0) => bus2ip_wrce(0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(14),
ip2bus_rdack => ip2bus_rdack,
ip2bus_rdack_int_d1 => ip2bus_rdack_int_d1,
ip2bus_rdack_prev2 => ip2bus_rdack_prev2,
ip2bus_wrack => ip2bus_wrack,
ip2bus_wrack_int_d1 => ip2bus_wrack_int_d1,
ip2bus_wrack_prev2 => ip2bus_wrack_prev2,
\mer_int_reg[0]\ => AXI_LITE_IPIF_I_n_40,
\mer_int_reg[0]_0\ => INTC_CORE_I_n_30,
\mer_int_reg[1]\ => AXI_LITE_IPIF_I_n_41,
p_0_in => p_0_in_0,
p_0_in107_in => p_0_in107_in,
p_0_in118_in => p_0_in118_in,
p_0_in11_in => p_0_in11_in,
p_0_in14_in => p_0_in14_in,
p_0_in19_in => p_0_in19_in,
p_0_in20_in => p_0_in20_in,
p_0_in22_in => p_0_in22_in,
p_0_in24_in => p_0_in24_in,
p_0_in26_in => p_0_in26_in,
p_0_in28_in => p_0_in28_in,
p_0_in2_in => p_0_in2_in,
p_0_in49_in => p_0_in49_in,
p_0_in51_in => p_0_in51_in,
p_0_in53_in => p_0_in53_in,
p_0_in55_in => p_0_in55_in,
p_0_in57_in => p_0_in57_in,
p_0_in59_in => p_0_in59_in,
p_0_in5_in => p_0_in5_in,
p_0_in64_in => p_0_in64_in,
p_0_in74_in => p_0_in74_in,
p_0_in85_in => p_0_in85_in,
p_0_in8_in => p_0_in8_in,
p_0_in96_in => p_0_in96_in,
p_17_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_17_in\,
p_1_in => p_1_in,
p_1_in21_in => p_1_in21_in,
p_1_in23_in => p_1_in23_in,
p_1_in25_in => p_1_in25_in,
p_1_in27_in => p_1_in27_in,
p_1_in29_in => p_1_in29_in,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(6 downto 0) => s_axi_araddr(8 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(6 downto 0) => s_axi_awaddr(8 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(0) => \^s_axi_bresp\(1),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(0) => \^s_axi_rresp\(1),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
INTC_CORE_I: entity work.system_microblaze_0_axi_intc_0_intc_core
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => AXI_LITE_IPIF_I_n_26,
Bus_RNW_reg_reg_0 => AXI_LITE_IPIF_I_n_27,
Bus_RNW_reg_reg_1 => AXI_LITE_IPIF_I_n_28,
Bus_RNW_reg_reg_10 => AXI_LITE_IPIF_I_n_11,
Bus_RNW_reg_reg_11 => AXI_LITE_IPIF_I_n_10,
Bus_RNW_reg_reg_12 => AXI_LITE_IPIF_I_n_9,
Bus_RNW_reg_reg_13 => AXI_LITE_IPIF_I_n_8,
Bus_RNW_reg_reg_2 => AXI_LITE_IPIF_I_n_29,
Bus_RNW_reg_reg_3 => AXI_LITE_IPIF_I_n_30,
Bus_RNW_reg_reg_4 => AXI_LITE_IPIF_I_n_31,
Bus_RNW_reg_reg_5 => AXI_LITE_IPIF_I_n_32,
Bus_RNW_reg_reg_6 => AXI_LITE_IPIF_I_n_41,
Bus_RNW_reg_reg_7 => AXI_LITE_IPIF_I_n_14,
Bus_RNW_reg_reg_8 => AXI_LITE_IPIF_I_n_13,
Bus_RNW_reg_reg_9 => AXI_LITE_IPIF_I_n_12,
\CIE_GEN.CIE_BIT_GEN[0].cie_reg[0]_0\ => AXI_LITE_IPIF_I_n_33,
\CIE_GEN.CIE_BIT_GEN[1].cie_reg[1]_0\ => AXI_LITE_IPIF_I_n_34,
\CIE_GEN.CIE_BIT_GEN[2].cie_reg[2]_0\ => AXI_LITE_IPIF_I_n_35,
\CIE_GEN.CIE_BIT_GEN[3].cie_reg[3]_0\ => AXI_LITE_IPIF_I_n_36,
\CIE_GEN.CIE_BIT_GEN[4].cie_reg[4]_0\ => AXI_LITE_IPIF_I_n_37,
\CIE_GEN.CIE_BIT_GEN[5].cie_reg[5]_0\ => AXI_LITE_IPIF_I_n_38,
\CIE_GEN.CIE_BIT_GEN[6].cie_reg[6]_0\ => AXI_LITE_IPIF_I_n_39,
Douta(31 downto 0) => Douta(31 downto 0),
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\ => AXI_LITE_IPIF_I_n_40,
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[1]_0\ => INTC_CORE_I_n_41,
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_0\ => INTC_CORE_I_n_30,
\IVAR_INDEX_SYNC_ON_AXI_CLK_GEN.ivar_index_axi_clk_reg[2]_1\ => INTC_CORE_I_n_42,
\IVR_GEN.ivr_reg[1]_0\ => INTC_CORE_I_n_8,
\IVR_GEN.ivr_reg[1]_1\ => INTC_CORE_I_n_32,
Q(0) => INTC_CORE_I_n_40,
\REG_GEN[0].IAR_FAST_MODE_GEN.iar_reg[0]_0\ => INTC_CORE_I_n_0,
\REG_GEN[0].ier_reg[0]_0\ => INTC_CORE_I_n_16,
\REG_GEN[0].ier_reg[0]_1\ => INTC_CORE_I_n_23,
\REG_GEN[6].IAR_FAST_MODE_GEN.iar_reg[6]_0\ => INTC_CORE_I_n_7,
SS(0) => p_0_in,
\bus2ip_addr_i_reg[5]\(3 downto 0) => bus2ip_addr(5 downto 2),
bus2ip_wrce(1) => bus2ip_wrce(8),
bus2ip_wrce(0) => bus2ip_wrce(0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(14),
interrupt_address(31 downto 0) => interrupt_address(31 downto 0),
intr(6 downto 0) => intr(6 downto 0),
irq => irq,
p_0_in => p_0_in_0,
p_0_in107_in => p_0_in107_in,
p_0_in118_in => p_0_in118_in,
p_0_in11_in => p_0_in11_in,
p_0_in14_in => p_0_in14_in,
p_0_in19_in => p_0_in19_in,
p_0_in20_in => p_0_in20_in,
p_0_in22_in => p_0_in22_in,
p_0_in24_in => p_0_in24_in,
p_0_in26_in => p_0_in26_in,
p_0_in28_in => p_0_in28_in,
p_0_in2_in => p_0_in2_in,
p_0_in49_in => p_0_in49_in,
p_0_in51_in => p_0_in51_in,
p_0_in53_in => p_0_in53_in,
p_0_in55_in => p_0_in55_in,
p_0_in57_in => p_0_in57_in,
p_0_in59_in => p_0_in59_in,
p_0_in5_in => p_0_in5_in,
p_0_in64_in => p_0_in64_in,
p_0_in74_in => p_0_in74_in,
p_0_in85_in => p_0_in85_in,
p_0_in8_in => p_0_in8_in,
p_0_in96_in => p_0_in96_in,
p_17_in => \I_SLAVE_ATTACHMENT/I_DECODER/p_17_in\,
p_1_in => p_1_in,
p_1_in21_in => p_1_in21_in,
p_1_in23_in => p_1_in23_in,
p_1_in25_in => p_1_in25_in,
p_1_in27_in => p_1_in27_in,
p_1_in29_in => p_1_in29_in,
processor_ack(1 downto 0) => processor_ack(1 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata_i_reg[3]\ => INTC_CORE_I_n_39,
\s_axi_rdata_i_reg[6]\(6 downto 0) => ipr(6 downto 0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0)
);
ip2bus_rdack_int_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Or128_vec2stdlogic19_out,
Q => ip2bus_rdack_int_d1,
R => p_0_in
);
ip2bus_rdack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_prev2,
Q => ip2bus_rdack,
R => p_0_in
);
ip2bus_wrack_int_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Or128_vec2stdlogic,
Q => ip2bus_wrack_int_d1,
R => p_0_in
);
ip2bus_wrack_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_wrack_prev2,
Q => ip2bus_wrack,
R => p_0_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_microblaze_0_axi_intc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
intr : in STD_LOGIC_VECTOR ( 6 downto 0 );
processor_clk : in STD_LOGIC;
processor_rst : in STD_LOGIC;
irq : out STD_LOGIC;
processor_ack : in STD_LOGIC_VECTOR ( 1 downto 0 );
interrupt_address : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_microblaze_0_axi_intc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_microblaze_0_axi_intc_0 : entity is "system_microblaze_0_axi_intc_0,axi_intc,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_microblaze_0_axi_intc_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_microblaze_0_axi_intc_0 : entity is "axi_intc,Vivado 2016.4";
end system_microblaze_0_axi_intc_0;
architecture STRUCTURE of system_microblaze_0_axi_intc_0 is
signal NLW_U0_processor_ack_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ASYNC_INTR : integer;
attribute C_ASYNC_INTR of U0 : label is -62;
attribute C_CASCADE_MASTER : integer;
attribute C_CASCADE_MASTER of U0 : label is 0;
attribute C_DISABLE_SYNCHRONIZERS : integer;
attribute C_DISABLE_SYNCHRONIZERS of U0 : label is 0;
attribute C_ENABLE_ASYNC : integer;
attribute C_ENABLE_ASYNC of U0 : label is 0;
attribute C_EN_CASCADE_MODE : integer;
attribute C_EN_CASCADE_MODE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_CIE : integer;
attribute C_HAS_CIE of U0 : label is 1;
attribute C_HAS_FAST : integer;
attribute C_HAS_FAST of U0 : label is 1;
attribute C_HAS_ILR : integer;
attribute C_HAS_ILR of U0 : label is 0;
attribute C_HAS_IPR : integer;
attribute C_HAS_IPR of U0 : label is 1;
attribute C_HAS_IVR : integer;
attribute C_HAS_IVR of U0 : label is 1;
attribute C_HAS_SIE : integer;
attribute C_HAS_SIE of U0 : label is 1;
attribute C_INSTANCE : string;
attribute C_INSTANCE of U0 : label is "system_microblaze_0_axi_intc_0";
attribute C_IRQ_ACTIVE : string;
attribute C_IRQ_ACTIVE of U0 : label is "1'b1";
attribute C_IRQ_IS_LEVEL : integer;
attribute C_IRQ_IS_LEVEL of U0 : label is 1;
attribute C_IVAR_RESET_VALUE : integer;
attribute C_IVAR_RESET_VALUE of U0 : label is 16;
attribute C_KIND_OF_EDGE : integer;
attribute C_KIND_OF_EDGE of U0 : label is -1;
attribute C_KIND_OF_INTR : integer;
attribute C_KIND_OF_INTR of U0 : label is -78;
attribute C_KIND_OF_LVL : integer;
attribute C_KIND_OF_LVL of U0 : label is -1;
attribute C_MB_CLK_NOT_CONNECTED : integer;
attribute C_MB_CLK_NOT_CONNECTED of U0 : label is 1;
attribute C_NUM_INTR_INPUTS : integer;
attribute C_NUM_INTR_INPUTS of U0 : label is 7;
attribute C_NUM_SW_INTR : integer;
attribute C_NUM_SW_INTR of U0 : label is 0;
attribute C_NUM_SYNC_FF : integer;
attribute C_NUM_SYNC_FF of U0 : label is 2;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute hdl : string;
attribute hdl of U0 : label is "VHDL";
attribute imp_netlist : string;
attribute imp_netlist of U0 : label is "TRUE";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
attribute iptype : string;
attribute iptype of U0 : label is "PERIPHERAL";
attribute run_ngcbuild : string;
attribute run_ngcbuild of U0 : label is "TRUE";
attribute style : string;
attribute style of U0 : label is "HDL";
begin
U0: entity work.system_microblaze_0_axi_intc_0_axi_intc
port map (
interrupt_address(31 downto 0) => interrupt_address(31 downto 0),
interrupt_address_in(31 downto 0) => B"00000000000000000000000000000000",
intr(6 downto 0) => intr(6 downto 0),
irq => irq,
irq_in => '0',
processor_ack(1 downto 0) => processor_ack(1 downto 0),
processor_ack_out(1 downto 0) => NLW_U0_processor_ack_out_UNCONNECTED(1 downto 0),
processor_clk => processor_clk,
processor_rst => processor_rst,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
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