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------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_cache
-- File: mmu_cache.vhd
-- Author: Jiri Gaisler
-- Description: Cache controllers and AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libleon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu_cache is
generic (
hindex : integer := 0;
memtech : integer range 0 to NTECH := 0;
dsu : integer range 0 to 1 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_ulogic;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of mmu_cache is
signal icol : icache_out_type;
signal dcol : dcache_out_type;
signal mcii : memory_ic_in_type;
signal mcio : memory_ic_out_type;
signal mcdi : memory_dc_in_type;
signal mcdo : memory_dc_out_type;
signal mcmmi : memory_mm_in_type;
signal mcmmo : memory_mm_out_type;
signal mmudci : mmudc_in_type;
signal mmudco : mmudc_out_type;
signal mmuici : mmuic_in_type;
signal mmuico : mmuic_out_type;
signal ahbsi2 : ahb_slv_in_type;
signal ahbi2 : ahb_mst_in_type;
signal ahbo2 : ahb_mst_out_type;
signal gndv: std_logic_vector(1 downto 0);
begin
gndv <= (others => '0');
icache0 : mmu_icache
generic map (memtech, icen, irepl, isets, ilinesize, isetsize, isetlock, ilram,
ilramsize, ilramstart,
mmuen)
port map (rst, clk, ici, icol, dci, dcol, mcii, mcio,
crami.icramin, cramo.icramo, fpuholdn, mmudci, mmuici, mmuico);
dcache0 : mmu_dcache
generic map (dsu, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop,
dlram, dlramsize, dlramstart, ilram, ilramstart,
itlbnum, dtlbnum, tlb_type,
memtech, cached, mmupgsz, smp, mmuen)
port map (rst, clk, dci, dcol, icol, mcdi, mcdo, ahbsi2,
crami.dcramin, cramo.dcramo, fpuholdn, mmudci, mmudco, sclk, ahbso);
-- AMBA AHB interface
a0 : mmu_acache
generic map (hindex, ilinesize, cached, clk2x, scantest
)
port map (rst, sclk, mcii, mcio, mcdi, mcdo, mcmmi, mcmmo, ahbi2, ahbo2, ahbso, hclken);
-- MMU
mmugen : if mmuen = 1 generate
m0 : mmu
generic map (memtech, itlbnum, dtlbnum, tlb_type, tlb_rep, mmupgsz, memtest_vlen)
port map (rst, clk, mmudci, mmudco, mmuici, mmuico, mcmmo, mcmmi, ahbi.testin
);
end generate;
nommu : if mmuen = 0 generate
mcmmi <= mci_zero; mmudco <= mmudco_zero; mmuico <= mmuico_zero;
end generate;
ico <= icol;
dco <= dcol;
clk2xgen: if clk2x /= 0 generate
sync0 : clk2xsync generic map (hindex, clk2x)
port map (rst, hclk, clk, ahbi, ahbi2, ahbo2, ahbo, ahbsi, ahbsi2,
mcii, mcdi, mcdo, mcmmi.req, mcmmo.grant, hclken);
end generate;
noclk2x : if clk2x = 0 generate
ahbsi2 <= ahbsi;
ahbi2 <= ahbi;
ahbo <= ahbo2;
end generate;
end;
|
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Testbench for synchronous register of a given width with a load signal.
library ieee;
use ieee.std_logic_1164.all;
entity reg_tb is
end reg_tb;
architecture TB of reg_tb is
signal rst, clk, load : std_logic;
signal input, output : std_logic_vector(0 downto 0);
constant clk_period : time := 20 ns; -- for a 50MHz clock
begin
-- Instantiate the Unit Under Test (UUT)
UUT : entity work.reg
generic map (
WIDTH => 1
)
port map (
rst => rst,
clk => clk,
load => load,
input => input,
output => output
);
-- Clock process
process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
process
begin
-- Hold reset state
rst <= '1';
load <= '0';
input(0) <= '0';
wait for clk_period;
-- Release reset
rst <= '0';
-- Perform the simulation
input(0) <= '1';
wait for clk_period;
input(0) <= '0';
load <= '1';
wait for clk_period;
input(0) <= '1';
wait for clk_period;
input(0) <= '0';
wait;
end process;
end TB;
|
--------------------------------------------------------------------------------
--! @file topmetal_analog_scan.vhd
--! @brief Generate appropriate signals for driving the analog scan of Topmetal array.
--! @author Yuan Mei
--!
--! The bram_sdp_w32r4 must have read latency of 1 (select no register on output).
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY topmetal_analog_scan IS
GENERIC (
ROWS : positive := 45; -- number of ROWS in the array
COLS : positive := 216; -- number of COLS in the ARRAY
CLK_DIV_WIDTH : positive := 16;
CLK_DIV_WLOG2 : positive := 4;
CONFIG_WIDTH : positive := 16
);
PORT (
CLK : IN std_logic; -- clock, TM_CLK_S is derived from this one
RESET : IN std_logic; -- reset
-- data input for writing to in-chip SRAM
MEM_CLK : IN std_logic; -- connect to control_interface
MEM_WE : IN std_logic;
MEM_ADDR : IN std_logic_vector(31 DOWNTO 0);
MEM_DIN : IN std_logic_vector(31 DOWNTO 0);
SRAM_WR_START : IN std_logic; -- 1 MEM_CLK wide pulse to initiate in-chip SRAM write
-- configuration
CLK_DIV : IN std_logic_vector(CLK_DIV_WLOG2-1 DOWNTO 0); -- log2(CLK_DIV_WIDTH), CLK/(2**CLK_DIV)
WR_CLK_DIV : IN std_logic_vector(CLK_DIV_WLOG2-1 DOWNTO 0);
STOP_ADDR : IN std_logic_vector(CONFIG_WIDTH-1 DOWNTO 0); --MSB enables
TRIGGER_RATE : IN std_logic_vector(CONFIG_WIDTH-1 DOWNTO 0); --trigger every () frames
TRIGGER_DELAY : IN std_logic_vector(CONFIG_WIDTH-1 DOWNTO 0);
STOP_CLK_S : IN std_logic; -- 1: stop TM_CLK_S, 0: run TM_CLK_S
KEEP_WE : IN std_logic; -- 1: SRAM_WE keep high in writing mode, 0: SRAM_WE runs in writing mode
-- input
MARKER_A : IN std_logic;
-- output
TRIGGER_OUT :OUT std_logic;
--
SRAM_D :OUT std_logic_vector(3 DOWNTO 0);
SRAM_WE :OUT std_logic;
TM_RST :OUT std_logic; -- digital reset
TM_CLK_S :OUT std_logic;
TM_RST_S :OUT std_logic;
TM_START_S :OUT std_logic;
TM_SPEAK_S :OUT std_logic
);
END topmetal_analog_scan;
ARCHITECTURE Behavioral OF topmetal_analog_scan IS
COMPONENT bram_sdp_w32r4
PORT (
CLKA : IN std_logic;
WEA : IN std_logic_vector(0 DOWNTO 0);
ADDRA : IN std_logic_vector(10 DOWNTO 0);
DINA : IN std_logic_vector(31 DOWNTO 0);
CLKB : IN std_logic;
ADDRB : IN std_logic_vector(13 DOWNTO 0);
DOUTB : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT pulse2pulse
PORT (
IN_CLK : IN std_logic;
OUT_CLK : IN std_logic;
RST : IN std_logic;
PULSEIN : IN std_logic;
INBUSY : OUT std_logic;
PULSEOUT : OUT std_logic
);
END COMPONENT;
SIGNAL clk_cnt : unsigned(CLK_DIV_WIDTH-1 DOWNTO 0);
SIGNAL we_clk_cnt : unsigned(CLK_DIV_WIDTH-1 DOWNTO 0);
SIGNAL we_clk_cnt_p0 : unsigned(CLK_DIV_WIDTH-1 DOWNTO 0);
SIGNAL TM_CLK_buf : std_logic;
SIGNAL TM_RST_S_buf : std_logic;
SIGNAL TM_RST_S_buf1 : std_logic;
SIGNAL TM_START_S_buf : std_logic;
SIGNAL TM_START_S_buf1 : std_logic;
SIGNAL TM_SPEAK_S_buf : std_logic;
SIGNAL TM_SPEAK_S_buf1 : std_logic;
SIGNAL sram_wr_startp : std_logic;
SIGNAL sram_wr_clk : std_logic;
SIGNAL sram_we_clk : std_logic;
SIGNAL sram_writing : std_logic;
SIGNAL sram_we_buf : std_logic;
SIGNAL sram_we_keep : std_logic;
--
SIGNAL bram_wea : std_logic_vector(0 DOWNTO 0);
SIGNAL bram_outb : std_logic_vector(3 DOWNTO 0);
SIGNAL bram_addrb : std_logic_vector(13 DOWNTO 0);
SIGNAL bram_addrb_cnt : unsigned(bram_addrb'length-1 DOWNTO 0);
--
SIGNAL pxladdr : unsigned(bram_addrb'length-1 DOWNTO 0);
SIGNAL trigger_cnt : unsigned(TRIGGER_RATE'length-1 DOWNTO 0);
SIGNAL trigger_buf : std_logic;
--
TYPE driveState_t IS (S0, S1, S2, S3, S4, S5, S6, S7,S8);
SIGNAL driveState : driveState_t;
SIGNAL driveState1 : driveState_t;
SIGNAL driveState2 : driveState_t;
SIGNAL driveState3 : driveState_t;
BEGIN
bram_inst : bram_sdp_w32r4
PORT MAP (
CLKA => MEM_CLK,
WEA => bram_wea,
ADDRA => MEM_ADDR(10 DOWNTO 0),
DINA => MEM_DIN,
CLKB => sram_wr_clk,
ADDRB => bram_addrb(13 DOWNTO 0),
DOUTB => bram_outb
);
bram_wea <= (OTHERS => MEM_WE);
pulse2pulse_inst : pulse2pulse
PORT MAP (
IN_CLK => MEM_CLK,
OUT_CLK => sram_wr_clk,
RST => RESET,
PULSEIN => SRAM_WR_START,
INBUSY => OPEN,
PULSEOUT => sram_wr_startp
);
clk_proc: PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
clk_cnt <= to_unsigned(0, clk_cnt'length);
ELSIF rising_edge(CLK) THEN
clk_cnt <= clk_cnt + 1;
END IF;
END PROCESS clk_proc;
PROCESS (WR_CLK_DIV)
BEGIN
we_clk_cnt_p0 <= ( others => '0');
we_clk_cnt_p0((to_integer(unsigned(WR_CLK_DIV)))-2) <= '1';
END PROCESS;
TM_CLK_buf <= CLK WHEN to_integer(unsigned(CLK_DIV)) = 0 ELSE
clk_cnt(to_integer(unsigned(CLK_DIV))-1);
sram_wr_clk <= CLK WHEN to_integer(unsigned(WR_CLK_DIV)) = 0 ELSE
clk_cnt(to_integer(unsigned(WR_CLK_DIV))-1);
we_clk_cnt <= to_unsigned(0, clk_cnt'length) WHEN clk_cnt = 0 ELSE
clk_cnt - we_clk_cnt_p0;
-- we_clk_cnt <= clk_cnt - we_clk_cnt_p0;
sram_we_clk <= we_clk_cnt(to_integer(unsigned(WR_CLK_DIV))-2);
tm_proc : PROCESS (TM_CLK_buf, RESET)
VARIABLE stopped : std_logic;
BEGIN
IF RESET = '1' OR sram_writing = '1' THEN
TM_RST_S_buf <= '0';
TM_START_S_buf <= '0';
TM_SPEAK_S_buf <= '0';
trigger_buf <= '0';
pxladdr <= (OTHERS => '0');
trigger_cnt <= (OTHERS => '0');
stopped := '0';
driveState <= S0;
ELSIF falling_edge(TM_CLK_buf) THEN
TM_RST_S_buf <= '0';
TM_START_S_buf <= '0';
TM_SPEAK_S_buf <= '0';
trigger_buf <= '0';
CASE driveState IS
WHEN S0 => -- wait a clk cycle
driveState <= S1;
WHEN S1 =>
TM_RST_S_buf <= '1';
driveState <= S2;
WHEN S2 => -- wait a clk cycle then start
driveState <= S3;
WHEN S3 =>
TM_START_S_buf <= '1';
pxladdr <= (OTHERS => '1');
driveState <= S4;
WHEN S4 =>
IF STOP_ADDR(STOP_ADDR'length-1) = '0' THEN
TM_SPEAK_S_buf <= '1';
ELSIF stopped = '1' THEN
TM_SPEAK_S_buf <= '0';
ELSE
TM_SPEAK_S_buf <= '1';
IF pxladdr = unsigned(STOP_ADDR(pxladdr'length-1 DOWNTO 0)) - 1 THEN
TM_SPEAK_S_buf <= '0';
stopped := '1';
END IF;
END IF;
IF trigger_cnt = unsigned(TRIGGER_RATE) AND
(pxladdr = unsigned(TRIGGER_DELAY(pxladdr'length-1 DOWNTO 0))-1 OR
(pxladdr = to_unsigned(ROWS*COLS-1, pxladdr'length) AND
unsigned(TRIGGER_DELAY(pxladdr'length-1 DOWNTO 0)) = 0)) THEN
trigger_buf <= '1';
END IF;
IF pxladdr >= to_unsigned(ROWS*COLS-1, pxladdr'length) THEN
pxladdr <= (OTHERS => '0');
IF trigger_cnt >= unsigned(TRIGGER_RATE) THEN
trigger_cnt <= (OTHERS => '0');
ELSE
trigger_cnt <= trigger_cnt + 1;
END IF;
ELSE
pxladdr <= pxladdr + 1;
END IF;
driveState <= S4;
WHEN OTHERS =>
driveState <= S0;
END CASE;
END IF;
END PROCESS;
sram_write_proc : PROCESS (sram_wr_clk, RESET) --falling edge controls TM_RST, TM_START, TM_SPEAK
BEGIN
IF RESET = '1' THEN
bram_addrb_cnt <= to_unsigned(0, bram_addrb_cnt'length);
sram_writing <= '0';
TM_RST_S_buf1 <= '0';
TM_START_S_buf1 <= '0';
TM_SPEAK_S_buf1 <= '0';
sram_we_keep <= '0';
driveState1 <= S0;
ELSIF falling_edge(sram_wr_clk) THEN
TM_RST_S_buf1 <= '0';
TM_START_S_buf1 <= '0';
TM_SPEAK_S_buf1 <= '0';
sram_we_keep <= '0';
bram_addrb_cnt <= to_unsigned(0, bram_addrb_cnt'length);
CASE driveState1 IS
WHEN S0 =>
IF sram_wr_startp = '1' THEN
sram_writing <= '1';
driveState1 <= S1;
END IF;
WHEN S1 =>
TM_RST_S_buf1 <= '1';
driveState1 <= S2;
WHEN S2 =>
TM_RST_S_buf1 <= '0';
driveState1 <= S3; -- wait a clk cycle then start
WHEN S3 =>
TM_START_S_buf1 <= '1';
driveState1 <= S4;
WHEN S4 => -- wait a clk cycle then speak
TM_START_S_buf1 <= '0';
TM_SPEAK_S_buf1 <= '1';
sram_we_keep <= '1';
driveState1 <= S5;
WHEN S5 =>
TM_SPEAK_S_buf1 <= '1';
sram_we_keep <= '1';
bram_addrb_cnt <= bram_addrb_cnt + 1;
IF bram_addrb_cnt = to_unsigned(ROWS*COLS-2, bram_addrb_cnt'length) THEN
driveState1 <= S6;
END IF;
WHEN S6 =>
TM_SPEAK_S_buf1 <= '0';
sram_we_keep <= '0';
sram_writing <= '0';
driveState1 <= S0;
WHEN OTHERS =>
TM_SPEAK_S_buf1 <= '0';
sram_we_keep <= '0';
sram_writing <= '0';
driveState1 <= S0;
END CASE;
END IF;
END PROCESS;
write_en_pros : PROCESS(sram_we_clk, RESET)
BEGIN
IF RESET = '1' THEN
sram_we_buf <= '0';
driveState2 <= S0;
ELSIF falling_edge(sram_we_clk) THEN
sram_we_buf <= '0';
CASE driveState2 IS
WHEN S0 =>
IF sram_writing = '1' AND TM_START_S_buf1 = '1' THEN
driveState2 <= S3 ;
END IF;
WHEN S3 =>
driveState2 <= S1;
WHEN S1 =>
IF sram_writing = '1' THEN
driveState2 <= S2;
ELSE
driveState2 <= S0;
END IF;
WHEN S2 =>
sram_we_buf <= '1';
IF bram_addrb_cnt = to_unsigned(ROWS*COLS-1, bram_addrb_cnt'length) THEN
driveState2 <= S0;
ELSE
driveState2 <= S1 ;
END IF;
WHEN OTHERS =>
driveState2 <= S0;
END CASE;
END IF;
END PROCESS;
bram_addrb <= std_logic_vector(bram_addrb_cnt);
-- output
TM_RST <= RESET;
TM_CLK_S <= '1' WHEN STOP_CLK_S = '1' ELSE
sram_wr_clk WHEN sram_writing = '1' ELSE TM_CLK_buf;
TM_RST_S <= TM_RST_S_buf1 WHEN sram_writing = '1' ELSE TM_RST_S_buf;
TM_START_S <= TM_START_S_buf1 WHEN sram_writing = '1' ELSE TM_START_S_buf;
TM_SPEAK_S <= TM_SPEAK_S_buf1 WHEN sram_writing = '1' ELSE TM_SPEAK_S_buf;
TRIGGER_OUT <= trigger_buf;
SRAM_WE <= sram_we_keep WHEN KEEP_WE = '1' ELSE sram_we_buf;
--
SRAM_D <= bram_outb(SRAM_D'length-1 DOWNTO 0);
END Behavioral;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package transaction_pkg is
--===============================================================================================
-- t_operation
-- - Bitvis defined BFM operations
--===============================================================================================
type t_operation is (
-- UVVM common
NO_OPERATION,
AWAIT_COMPLETION,
AWAIT_ANY_COMPLETION,
ENABLE_LOG_MSG,
DISABLE_LOG_MSG,
FLUSH_COMMAND_QUEUE,
FETCH_RESULT,
INSERT_DELAY,
TERMINATE_CURRENT_COMMAND,
-- VVC local
MASTER_TRANSMIT_AND_RECEIVE, MASTER_TRANSMIT_AND_CHECK, MASTER_TRANSMIT_ONLY, MASTER_RECEIVE_ONLY, MASTER_CHECK_ONLY,
SLAVE_TRANSMIT_AND_RECEIVE, SLAVE_TRANSMIT_AND_CHECK, SLAVE_TRANSMIT_ONLY, SLAVE_RECEIVE_ONLY, SLAVE_CHECK_ONLY);
constant C_VVC_CMD_STRING_MAX_LENGTH : natural := 300;
constant C_VVC_CMD_DATA_MAX_LENGTH : natural := 32;
constant C_VVC_CMD_MAX_WORDS : natural := C_SPI_VVC_DATA_ARRAY_WIDTH;
--==========================================================================================
--
-- Transaction info types, constants and global signal
--
--==========================================================================================
-- Transaction status
type t_transaction_status is (INACTIVE, IN_PROGRESS, FAILED, SUCCEEDED);
constant C_TRANSACTION_STATUS_DEFAULT : t_transaction_status := INACTIVE;
-- VVC Meta
type t_vvc_meta is record
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
cmd_idx : integer;
end record;
constant C_VVC_META_DEFAULT : t_vvc_meta := (
msg => (others => ' '),
cmd_idx => -1
);
-- Base transaction
type t_base_transaction is record
operation : t_operation;
data : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
data_exp : t_slv_array(C_VVC_CMD_MAX_WORDS-1 downto 0)(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
num_words : natural;
word_length : natural;
when_to_start_transfer : t_when_to_start_transfer;
action_when_transfer_is_done : t_action_when_transfer_is_done;
action_between_words : t_action_between_words;
vvc_meta : t_vvc_meta;
transaction_status : t_transaction_status;
end record;
constant C_BASE_TRANSACTION_SET_DEFAULT : t_base_transaction := (
operation => NO_OPERATION,
data => (others => (others => '0')),
data_exp => (others => (others => '0')),
num_words => 0,
word_length => 0,
when_to_start_transfer => START_TRANSFER_IMMEDIATE,
action_when_transfer_is_done => RELEASE_LINE_AFTER_TRANSFER,
action_between_words => HOLD_LINE_BETWEEN_WORDS,
vvc_meta => C_VVC_META_DEFAULT,
transaction_status => C_TRANSACTION_STATUS_DEFAULT
);
-- Transaction group
type t_transaction_group is record
bt : t_base_transaction;
end record;
constant C_TRANSACTION_GROUP_DEFAULT : t_transaction_group := (
bt => C_BASE_TRANSACTION_SET_DEFAULT
);
-- Global transaction info trigger signal
type t_spi_transaction_trigger_array is array (natural range <>) of std_logic;
signal global_spi_vvc_transaction_trigger : t_spi_transaction_trigger_array(0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => '0');
-- Type is defined as array to coincide with channel based VVCs
type t_spi_transaction_group_array is array (natural range <>) of t_transaction_group;
-- Shared transaction info variable
shared variable shared_spi_vvc_transaction_info : t_spi_transaction_group_array(0 to C_MAX_VVC_INSTANCE_NUM-1) :=
(others => C_TRANSACTION_GROUP_DEFAULT);
end package transaction_pkg; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:00:40 10/08/2011
-- Design Name:
-- Module Name: ArithmeticModule - ArithmeticArchitecture
-- Project Name: DLP Proyecto Codename Calculadora
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity ArithmeticModule is
Port ( A : in STD_LOGIC_VECTOR(7 downto 0);--Primer operando(valor binario)
B : in STD_LOGIC_VECTOR(7 downto 0);--Segundo operando(valor binario)
Op : in STD_LOGIC_VECTOR(1 downto 0);--Operador
Res : out STD_LOGIC_VECTOR(15 downto 0));--Resultado de la operacion(valor binario)
end ArithmeticModule;
architecture ArithmeticArchitecture of ArithmeticModule is
begin
PROCESS(A, B, Op)
BEGIN
CASE Op IS
WHEN "00" => --Suma
Res(7 downto 0) <= A+B;
Res(15 downto 8) <= "00000000";
WHEN "01" => --Resta
Res(7 downto 0) <= A-B;
Res(15 downto 8) <= "00000000";
WHEN "10" =>--Multiplicacion
Res <= A*B;
WHEN "11" =>--Division NO IMPLEMENTADA TODAVIA
Res <= "1111111111111111";
when others =>
Res <= "1111111111111111";
END CASE;
END PROCESS;
end ArithmeticArchitecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity assert2 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end assert2;
architecture behav of assert2 is
signal val : unsigned (3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity one_hot is
port(
si : in std_logic_vector (6 downto 0);
so : out std_logic_vector (2 downto 0)
);
end entity;
architecture behav of one_hot is
signal si_1 : std_logic_vector(6 downto 0);
begin
si_1 <= si;
so(0) <= si_1(0) or si_1(2) or si_1(4) or si_1(6);
so(1) <= si_1(1) or si_1(2) or si_1(5) or si_1(6);
so(2) <= si_1(3) or si_1(4) or si_1(5) or si_1(6);
--C LSB
--so(0) = (nso_1(2) and nso_1(1) and so_1(0)) and (nso_1(2) and so_1(1) and so_1(0)) and (so_1(2) and nso_1(1) and so_1(0)) and (so_1(2) and so_1(1) and so_1(0));
--so(1) = (nso_1(2) and so_1(1) and nso_1(0)) and (so_1(2) and so_1(1) and nso_1(0)) and (so_1(2) and so_1(1) and so_1(0));
--so(2) = (nso_1())
end architecture;
|
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Containing RapidIO packet buffering functionallity. Two different entities
-- are implemented, one with transmission window support and one without.
--
-- To Do:
-- -
--
-- Author(s):
-- - Magnus Rosenius, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- RioPacketBuffer
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for RioPacketBuffer.
--
-- Generic variables
-- -----------------
-- SIZE_ADDRESS_WIDTH - The number of frames in powers of two.
-- CONTENT_ADDRESS_WIDTH - The total number of entries in the memory that can
-- be used to store packet data.
-- CONTENT_WIDTH - The width of the data to store as packet content in the memory.
-- MAX_PACKET_SIZE - The number of entries that must be available for a new
-- complete full sized packet to be received. This option is present to ensure
-- that it is always possible to move a packet to the storage without being
-- surprised that the storage is suddenly empty.
-------------------------------------------------------------------------------
entity RioPacketBuffer is
generic(
SIZE_ADDRESS_WIDTH : natural := 6;
CONTENT_ADDRESS_WIDTH : natural := 8;
CONTENT_WIDTH : natural := 32;
MAX_PACKET_SIZE : natural := 69);
port(
clk : in std_logic;
areset_n : in std_logic;
inboundWriteFrameFull_o : out std_logic;
inboundWriteFrame_i : in std_logic;
inboundWriteFrameAbort_i : in std_logic;
inboundWriteContent_i : in std_logic;
inboundWriteContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
inboundReadFrameEmpty_o : out std_logic;
inboundReadFrame_i : in std_logic;
inboundReadFrameRestart_i : in std_logic;
inboundReadFrameAborted_o : out std_logic;
inboundReadFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
inboundReadContentEmpty_o : out std_logic;
inboundReadContent_i : in std_logic;
inboundReadContentEnd_o : out std_logic;
inboundReadContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0);
outboundWriteFrameFull_o : out std_logic;
outboundWriteFrame_i : in std_logic;
outboundWriteFrameAbort_i : in std_logic;
outboundWriteContent_i : in std_logic;
outboundWriteContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
outboundReadFrameEmpty_o : out std_logic;
outboundReadFrame_i : in std_logic;
outboundReadFrameRestart_i : in std_logic;
outboundReadFrameAborted_o : out std_logic;
outboundReadFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
outboundReadContentEmpty_o : out std_logic;
outboundReadContent_i : in std_logic;
outboundReadContentEnd_o : out std_logic;
outboundReadContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for RioPacketBuffer.
-------------------------------------------------------------------------------
architecture RioPacketBufferImpl of RioPacketBuffer is
component PacketBufferContinous is
generic(
SIZE_ADDRESS_WIDTH : natural;
CONTENT_ADDRESS_WIDTH : natural;
CONTENT_WIDTH : natural;
MAX_PACKET_SIZE : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end component;
begin
-----------------------------------------------------------------------------
-- Outbound frame buffers.
-----------------------------------------------------------------------------
OutboundPacketBuffer: PacketBufferContinous
generic map(
SIZE_ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH,
CONTENT_ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH,
CONTENT_WIDTH=>CONTENT_WIDTH,
MAX_PACKET_SIZE=>MAX_PACKET_SIZE)
port map(
clk=>clk,
areset_n=>areset_n,
writeFrameFull_o=>outboundWriteFrameFull_o,
writeFrame_i=>outboundWriteFrame_i, writeFrameAbort_i=>outboundWriteFrameAbort_i,
writeContent_i=>outboundWriteContent_i, writeContentData_i=>outboundWriteContentData_i,
readFrameEmpty_o=>outboundReadFrameEmpty_o,
readFrame_i=>outboundReadFrame_i, readFrameRestart_i=>outboundReadFrameRestart_i,
readFrameAborted_o=>outboundReadFrameAborted_o,
readFrameSize_o=>outboundReadFrameSize_o,
readContentEmpty_o=>outboundReadContentEmpty_o,
readContent_i=>outboundReadContent_i, readContentEnd_o=>outboundReadContentEnd_o,
readContentData_o=>outboundReadContentData_o);
-----------------------------------------------------------------------------
-- Inbound frame buffers.
-----------------------------------------------------------------------------
InboundPacketBuffer: PacketBufferContinous
generic map(
SIZE_ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH,
CONTENT_ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH,
CONTENT_WIDTH=>CONTENT_WIDTH,
MAX_PACKET_SIZE=>MAX_PACKET_SIZE)
port map(
clk=>clk,
areset_n=>areset_n,
writeFrameFull_o=>inboundWriteFrameFull_o,
writeFrame_i=>inboundWriteFrame_i, writeFrameAbort_i=>inboundWriteFrameAbort_i,
writeContent_i=>inboundWriteContent_i, writeContentData_i=>inboundWriteContentData_i,
readFrameEmpty_o=>inboundReadFrameEmpty_o,
readFrame_i=>inboundReadFrame_i, readFrameRestart_i=>inboundReadFrameRestart_i,
readFrameAborted_o=>inboundReadFrameAborted_o,
readFrameSize_o=>inboundReadFrameSize_o,
readContentEmpty_o=>inboundReadContentEmpty_o,
readContent_i=>inboundReadContent_i, readContentEnd_o=>inboundReadContentEnd_o,
readContentData_o=>inboundReadContentData_o);
end architecture;
-------------------------------------------------------------------------------
-- RioPacketBufferWindow
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for RioPacketBufferWindow.
-------------------------------------------------------------------------------
entity RioPacketBufferWindow is
generic(
SIZE_ADDRESS_WIDTH : natural := 6;
CONTENT_ADDRESS_WIDTH : natural := 8;
CONTENT_WIDTH : natural := 32;
MAX_PACKET_SIZE : natural := 69);
port(
clk : in std_logic;
areset_n : in std_logic;
inboundWriteFrameFull_o : out std_logic;
inboundWriteFrame_i : in std_logic;
inboundWriteFrameAbort_i : in std_logic;
inboundWriteContent_i : in std_logic;
inboundWriteContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
inboundReadFrameEmpty_o : out std_logic;
inboundReadFrame_i : in std_logic;
inboundReadFrameRestart_i : in std_logic;
inboundReadFrameAborted_o : out std_logic;
inboundReadContentEmpty_o : out std_logic;
inboundReadContent_i : in std_logic;
inboundReadContentEnd_o : out std_logic;
inboundReadContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0);
outboundWriteFrameFull_o : out std_logic;
outboundWriteFrame_i : in std_logic;
outboundWriteFrameAbort_i : in std_logic;
outboundWriteContent_i : in std_logic;
outboundWriteContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
outboundReadFrameEmpty_o : out std_logic;
outboundReadFrame_i : in std_logic;
outboundReadFrameRestart_i : in std_logic;
outboundReadFrameAborted_o : out std_logic;
outboundReadWindowEmpty_o : out std_logic;
outboundReadWindowReset_i : in std_logic;
outboundReadWindowNext_i : in std_logic;
outboundReadContentEmpty_o : out std_logic;
outboundReadContent_i : in std_logic;
outboundReadContentEnd_o : out std_logic;
outboundReadContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for RioPacketBufferWindow.
-------------------------------------------------------------------------------
architecture RioPacketBufferWindowImpl of RioPacketBufferWindow is
component PacketBufferContinous is
generic(
SIZE_ADDRESS_WIDTH : natural;
CONTENT_ADDRESS_WIDTH : natural;
CONTENT_WIDTH : natural;
MAX_PACKET_SIZE : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end component;
component PacketBufferContinousWindow is
generic(
SIZE_ADDRESS_WIDTH : natural;
CONTENT_ADDRESS_WIDTH : natural;
CONTENT_WIDTH : natural;
MAX_PACKET_SIZE : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readWindowEmpty_o : out std_logic;
readWindowReset_i : in std_logic;
readWindowNext_i : in std_logic;
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end component;
begin
-----------------------------------------------------------------------------
-- Outbound frame buffers.
-----------------------------------------------------------------------------
OutboundPacketBuffer: PacketBufferContinousWindow
generic map(
SIZE_ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH,
CONTENT_ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH,
CONTENT_WIDTH=>CONTENT_WIDTH,
MAX_PACKET_SIZE=>MAX_PACKET_SIZE)
port map(
clk=>clk,
areset_n=>areset_n,
writeFrameFull_o=>outboundWriteFrameFull_o,
writeFrame_i=>outboundWriteFrame_i, writeFrameAbort_i=>outboundWriteFrameAbort_i,
writeContent_i=>outboundWriteContent_i, writeContentData_i=>outboundWriteContentData_i,
readFrameEmpty_o=>outboundReadFrameEmpty_o,
readFrame_i=>outboundReadFrame_i, readFrameRestart_i=>outboundReadFrameRestart_i,
readFrameAborted_o=>outboundReadFrameAborted_o,
readWindowEmpty_o=>outboundReadWindowEmpty_o,
readWindowReset_i=>outboundReadWindowReset_i,
readWindowNext_i=>outboundReadWindowNext_i,
readContentEmpty_o=>outboundReadContentEmpty_o,
readContent_i=>outboundReadContent_i, readContentEnd_o=>outboundReadContentEnd_o,
readContentData_o=>outboundReadContentData_o);
-----------------------------------------------------------------------------
-- Inbound frame buffers.
-----------------------------------------------------------------------------
InboundPacketBuffer: PacketBufferContinous
generic map(
SIZE_ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH,
CONTENT_ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH,
CONTENT_WIDTH=>CONTENT_WIDTH,
MAX_PACKET_SIZE=>MAX_PACKET_SIZE)
port map(
clk=>clk,
areset_n=>areset_n,
writeFrameFull_o=>inboundWriteFrameFull_o,
writeFrame_i=>inboundWriteFrame_i, writeFrameAbort_i=>inboundWriteFrameAbort_i,
writeContent_i=>inboundWriteContent_i, writeContentData_i=>inboundWriteContentData_i,
readFrameEmpty_o=>inboundReadFrameEmpty_o,
readFrame_i=>inboundReadFrame_i, readFrameRestart_i=>inboundReadFrameRestart_i,
readFrameAborted_o=>inboundReadFrameAborted_o,
readFrameSize_o=>open,
readContentEmpty_o=>inboundReadContentEmpty_o,
readContent_i=>inboundReadContent_i, readContentEnd_o=>inboundReadContentEnd_o,
readContentData_o=>inboundReadContentData_o);
end architecture;
-------------------------------------------------------------------------------
-- PacketBufferContinous
-- This component stores data in chuncks and stores the size of them. The full
-- memory can be used, except for one word, or a specified (using generic)
-- maximum number of frames.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Entity for PacketBufferContinous.
-------------------------------------------------------------------------------
entity PacketBufferContinous is
generic(
SIZE_ADDRESS_WIDTH : natural;
CONTENT_ADDRESS_WIDTH : natural;
CONTENT_WIDTH : natural;
MAX_PACKET_SIZE : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for PacketBufferContinous.
-------------------------------------------------------------------------------
architecture PacketBufferContinousImpl of PacketBufferContinous is
component MemorySimpleDualPortAsync is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
component MemorySimpleDualPort is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
clkB_i : in std_logic;
enableB_i : in std_logic;
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
-- The number of available word positions left in the memory.
signal available : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The position to place new frames.
signal backIndex, backIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The position to remove old frames.
signal frontIndex, frontIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The size of the current frame.
signal readFrameEnd_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The start of unread content.
signal memoryStart_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The current reading position.
signal memoryRead_p, memoryReadNext_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The end of unread content.
signal memoryEnd_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The current writing position.
signal memoryWrite_p, memoryWriteNext_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- Memory output signal containing the position of a frame.
signal framePositionReadData : std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
begin
-----------------------------------------------------------------------------
-- Internal signal assignments.
-----------------------------------------------------------------------------
available <= not (memoryEnd_p - memoryStart_p);
backIndexNext <= backIndex + 1;
frontIndexNext <= frontIndex + 1;
memoryWriteNext_p <= memoryWrite_p + 1;
memoryReadNext_p <= memoryRead_p + 1;
-----------------------------------------------------------------------------
-- Writer logic.
-----------------------------------------------------------------------------
writeFrameFull_o <= '1' when ((backIndexNext = frontIndex) or
(available < MAX_PACKET_SIZE)) else '0';
Writer: process(clk, areset_n)
begin
if (areset_n = '0') then
backIndex <= (others=>'0');
memoryEnd_p <= (others=>'0');
memoryWrite_p <= (others=>'0');
elsif (clk'event and clk = '1') then
if (writeFrameAbort_i = '1') then
memoryWrite_p <= memoryEnd_p;
elsif (writeContent_i = '1') then
memoryWrite_p <= memoryWriteNext_p;
end if;
if(writeFrame_i = '1') then
memoryEnd_p <= memoryWrite_p;
backIndex <= backIndexNext;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Frame cancellation logic.
-----------------------------------------------------------------------------
process(clk, areset_n)
begin
if (areset_n = '0') then
readFrameAborted_o <= '0';
elsif (clk'event and clk = '1') then
if ((frontIndex = backIndex) and
((writeFrameAbort_i = '1') and (readFrameRestart_i = '0'))) then
readFrameAborted_o <= '1';
elsif ((writeFrameAbort_i = '0') and (readFrameRestart_i = '1')) then
readFrameAborted_o <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Reader logic.
-----------------------------------------------------------------------------
readFrameEmpty_o <= '1' when (frontIndex = backIndex) else '0';
readContentEmpty_o <= '1' when ((frontIndex = backIndex) and
(memoryWrite_p = memoryRead_p)) else '0';
readFrameSize_o <= std_logic_vector(readFrameEnd_p - memoryStart_p);
Reader: process(clk, areset_n)
begin
if (areset_n = '0') then
frontIndex <= (others=>'0');
memoryStart_p <= (others=>'0');
memoryRead_p <= (others=>'0');
readContentEnd_o <= '0';
elsif (clk'event and clk = '1') then
-- REMARK: Break apart into registers to avoid priority ladder???
if(readFrameRestart_i = '1') then
memoryRead_p <= memoryStart_p;
elsif(readContent_i = '1') then
if(memoryRead_p = readFrameEnd_p) then
readContentEnd_o <= '1';
else
readContentEnd_o <= '0';
memoryRead_p <= memoryReadNext_p;
end if;
elsif(readFrame_i = '1') then
memoryStart_p <= readFrameEnd_p;
frontIndex <= frontIndexNext;
memoryRead_p <= readFrameEnd_p;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Frame positioning memory signals.
-----------------------------------------------------------------------------
readFrameEnd_p <= unsigned(framePositionReadData);
-- Memory to keep frame starting/ending positions in.
FramePosition: MemorySimpleDualPortAsync
generic map(ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH, DATA_WIDTH=>CONTENT_ADDRESS_WIDTH)
port map(
clkA_i=>clk, enableA_i=>writeFrame_i,
addressA_i=>std_logic_vector(backIndex), dataA_i=>std_logic_vector(memoryWrite_p),
addressB_i=>std_logic_vector(frontIndex), dataB_o=>framePositionReadData);
-----------------------------------------------------------------------------
-- Frame content memory signals.
-----------------------------------------------------------------------------
-- Memory to keep frame content in.
-- REMARK: Use paritybits here as well to make sure the frame data does not
-- become corrupt???
FrameContent: MemorySimpleDualPort
generic map(ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH, DATA_WIDTH=>CONTENT_WIDTH)
port map(
clkA_i=>clk, enableA_i=>writeContent_i,
addressA_i=>std_logic_vector(memoryWrite_p), dataA_i=>writeContentData_i,
clkB_i=>clk, enableB_i=>readContent_i,
addressB_i=>std_logic_vector(memoryRead_p), dataB_o=>readContentData_o);
end architecture;
-------------------------------------------------------------------------------
-- PacketBufferContinousWindow
-- This component stores data in chuncks and stores the size of them. The full
-- memory can be used, except for one word, or a specified (using generic)
-- maximum number of frames.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- Entity for PacketBufferContinousWindow.
-------------------------------------------------------------------------------
entity PacketBufferContinousWindow is
generic(
SIZE_ADDRESS_WIDTH : natural;
CONTENT_ADDRESS_WIDTH : natural;
CONTENT_WIDTH : natural;
MAX_PACKET_SIZE : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readWindowEmpty_o : out std_logic;
readWindowReset_i : in std_logic;
readWindowNext_i : in std_logic;
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
end entity;
-------------------------------------------------------------------------------
-- Architecture for PacketBufferContinousWindow.
-------------------------------------------------------------------------------
architecture PacketBufferContinousWindowImpl of PacketBufferContinousWindow is
component MemorySimpleDualPortAsync is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
component MemorySimpleDualPort is
generic(
ADDRESS_WIDTH : natural := 1;
DATA_WIDTH : natural := 1);
port(
clkA_i : in std_logic;
enableA_i : in std_logic;
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
clkB_i : in std_logic;
enableB_i : in std_logic;
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
-- The number of available word positions left in the memory.
signal available : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
signal backIndex, backIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
signal frontIndex, frontIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
signal windowIndex, windowIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The size of the current frame.
signal readFrameEnd_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The start of unread content.
signal memoryStart_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The start of unread window content.
signal memoryStartWindow_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The current reading position.
signal memoryRead_p, memoryReadNext_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The end of unread content.
signal memoryEnd_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
-- The current writing position.
signal memoryWrite_p, memoryWriteNext_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
signal framePositionReadAddress : std_logic_vector(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
signal framePositionReadData : std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
begin
-----------------------------------------------------------------------------
-- Internal signal assignments.
-----------------------------------------------------------------------------
available <= not (memoryEnd_p - memoryStart_p);
backIndexNext <= backIndex + 1;
frontIndexNext <= frontIndex + 1;
windowIndexNext <= windowIndex + 1;
memoryWriteNext_p <= memoryWrite_p + 1;
memoryReadNext_p <= memoryRead_p + 1;
-----------------------------------------------------------------------------
-- Writer logic.
-----------------------------------------------------------------------------
writeFrameFull_o <= '1' when ((backIndexNext = frontIndex) or
(available < MAX_PACKET_SIZE)) else '0';
Writer: process(clk, areset_n)
begin
if (areset_n = '0') then
backIndex <= (others=>'0');
memoryEnd_p <= (others=>'0');
memoryWrite_p <= (others=>'0');
elsif (clk'event and clk = '1') then
if (writeFrameAbort_i = '1') then
memoryWrite_p <= memoryEnd_p;
elsif (writeContent_i = '1') then
memoryWrite_p <= memoryWriteNext_p;
end if;
if(writeFrame_i = '1') then
memoryEnd_p <= memoryWrite_p;
backIndex <= backIndexNext;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Frame cancellation logic.
-----------------------------------------------------------------------------
process(clk, areset_n)
begin
if (areset_n = '0') then
readFrameAborted_o <= '0';
elsif (clk'event and clk = '1') then
if ((windowIndex = backIndex) and
((writeFrameAbort_i = '1') and (readFrameRestart_i = '0'))) then
readFrameAborted_o <= '1';
elsif ((writeFrameAbort_i = '0') and (readFrameRestart_i = '1')) then
readFrameAborted_o <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Reader logic.
-----------------------------------------------------------------------------
readFrameEmpty_o <= '1' when (frontIndex = backIndex) else '0';
readWindowEmpty_o <= '1' when (windowIndex = backIndex) else '0';
readContentEmpty_o <= '1' when ((windowIndex = backIndex) and
(memoryWrite_p = memoryRead_p)) else '0';
Reader: process(clk, areset_n)
begin
if (areset_n = '0') then
frontIndex <= (others=>'0');
windowIndex <= (others=>'0');
memoryStart_p <= (others=>'0');
memoryStartWindow_p <= (others=>'0');
memoryRead_p <= (others=>'0');
readContentEnd_o <= '0';
elsif (clk'event and clk = '1') then
-- REMARK: Break apart into registers to avoid priority ladder???
if(readFrameRestart_i = '1') then
memoryRead_p <= memoryStartWindow_p;
elsif(readContent_i = '1') then
if(memoryRead_p = readFrameEnd_p) then
readContentEnd_o <= '1';
else
readContentEnd_o <= '0';
memoryRead_p <= memoryReadNext_p;
end if;
elsif(readFrame_i = '1') then
memoryStart_p <= readFrameEnd_p;
frontIndex <= frontIndexNext;
elsif(readWindowReset_i = '1') then
memoryStartWindow_p <= memoryStart_p;
windowIndex <= frontIndex;
memoryRead_p <= memoryStart_p;
elsif(readWindowNext_i = '1') then
memoryStartWindow_p <= readFrameEnd_p;
windowIndex <= windowIndexNext;
memoryRead_p <= readFrameEnd_p;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Frame positioning memory signals.
-----------------------------------------------------------------------------
-- Assign the address from both frontIndex and windowIndex to be able to
-- share the memory between the two different types of accesses. This assumes
-- that the window is not accessed at the same time as the other signal.
framePositionReadAddress <= std_logic_vector(frontIndex) when (readFrame_i = '1') else
std_logic_vector(windowIndex);
readFrameEnd_p <= unsigned(framePositionReadData);
-- Memory to keep frame starting/ending positions in.
FramePosition: MemorySimpleDualPortAsync
generic map(ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH, DATA_WIDTH=>CONTENT_ADDRESS_WIDTH)
port map(
clkA_i=>clk, enableA_i=>writeFrame_i,
addressA_i=>std_logic_vector(backIndex), dataA_i=>std_logic_vector(memoryWrite_p),
addressB_i=>framePositionReadAddress, dataB_o=>framePositionReadData);
-----------------------------------------------------------------------------
-- Frame content memory signals.
-----------------------------------------------------------------------------
-- Memory to keep frame content in.
-- REMARK: Use paritybits here as well to make sure the frame data does not
-- become corrupt???
FrameContent: MemorySimpleDualPort
generic map(ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH, DATA_WIDTH=>CONTENT_WIDTH)
port map(
clkA_i=>clk, enableA_i=>writeContent_i,
addressA_i=>std_logic_vector(memoryWrite_p), dataA_i=>writeContentData_i,
clkB_i=>clk, enableB_i=>readContent_i,
addressB_i=>std_logic_vector(memoryRead_p), dataB_o=>readContentData_o);
end architecture;
|
-- Added these lines on rev. 42 in order to remove the commit message saying that
-- there is a bug in the implementation, since the bug has been fixed in the same rev.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity node_port_readdec is
Port ( I_clk : in STD_LOGIC;
I_portID : in STD_LOGIC_VECTOR (2 downto 0);
I_readEnable : in STD_LOGIC;
O_readEnableUp : out STD_LOGIC;
O_readEnableDown : out STD_LOGIC;
O_readEnableLeft : out STD_LOGIC;
O_readEnableRight : out STD_LOGIC);
end node_port_readdec;
-- NOTE: The architecture below doesn't support ANY or LAST ports.
architecture Behavioral of node_port_readdec is
begin
O_readEnableUp <= I_readEnable when I_portID = "000" else '0';
O_readEnableDown <= I_readEnable when I_portID = "001" else '0';
O_readEnableLeft <= I_readEnable when I_portID = "010" else '0';
O_readEnableRight <= I_readEnable when I_portID = "011" else '0';
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: charrom
-- File: charrom.vhd
-- Author: Marcus Hellqvist
-- Description: Character ROM for video controller
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity charrom is
port(
clk : in std_ulogic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of charrom is
signal romdata : std_logic_vector(7 downto 0);
signal romaddr : std_logic_vector(11 downto 0);
begin
data <= romdata;
p0: process(clk)
begin
if rising_edge(clk) then
romaddr <= addr;
end if;
end process;
p1: process(romaddr)
begin
case conv_integer(romaddr) is
when 16#000# => romdata <= X"00"; --
when 16#100# => romdata <= X"00"; --
when 16#200# => romdata <= X"00"; --
when 16#300# => romdata <= X"00"; --
when 16#400# => romdata <= X"00"; --
when 16#500# => romdata <= X"00"; --
when 16#600# => romdata <= X"00"; --
when 16#700# => romdata <= X"00"; --
when 16#800# => romdata <= X"00"; --
when 16#900# => romdata <= X"00"; --
when 16#a00# => romdata <= X"00"; --
when 16#b00# => romdata <= X"00"; --
when 16#c00# => romdata <= X"00"; --
when 16#020# => romdata <= X"00"; --
when 16#120# => romdata <= X"00"; --
when 16#220# => romdata <= X"00"; --
when 16#320# => romdata <= X"00"; --
when 16#420# => romdata <= X"00"; --
when 16#520# => romdata <= X"00"; --
when 16#620# => romdata <= X"00"; --
when 16#720# => romdata <= X"00"; --
when 16#820# => romdata <= X"00"; --
when 16#920# => romdata <= X"00"; --
when 16#a20# => romdata <= X"00"; --
when 16#b20# => romdata <= X"00"; --
when 16#c20# => romdata <= X"00"; --
when 16#021# => romdata <= X"00"; -- !
when 16#121# => romdata <= X"00"; -- !
when 16#221# => romdata <= X"10"; -- !
when 16#321# => romdata <= X"10"; -- !
when 16#421# => romdata <= X"10"; -- !
when 16#521# => romdata <= X"10"; -- !
when 16#621# => romdata <= X"10"; -- !
when 16#721# => romdata <= X"10"; -- !
when 16#821# => romdata <= X"10"; -- !
when 16#921# => romdata <= X"00"; -- !
when 16#a21# => romdata <= X"10"; -- !
when 16#b21# => romdata <= X"00"; -- !
when 16#c21# => romdata <= X"00"; -- !
when 16#022# => romdata <= X"00"; -- "
when 16#122# => romdata <= X"00"; -- "
when 16#222# => romdata <= X"24"; -- "
when 16#322# => romdata <= X"24"; -- "
when 16#422# => romdata <= X"24"; -- "
when 16#522# => romdata <= X"00"; -- "
when 16#622# => romdata <= X"00"; -- "
when 16#722# => romdata <= X"00"; -- "
when 16#822# => romdata <= X"00"; -- "
when 16#922# => romdata <= X"00"; -- "
when 16#a22# => romdata <= X"00"; -- "
when 16#b22# => romdata <= X"00"; -- "
when 16#c22# => romdata <= X"00"; -- "
when 16#023# => romdata <= X"00"; -- #
when 16#123# => romdata <= X"00"; -- #
when 16#223# => romdata <= X"00"; -- #
when 16#323# => romdata <= X"24"; -- #
when 16#423# => romdata <= X"24"; -- #
when 16#523# => romdata <= X"7e"; -- #
when 16#623# => romdata <= X"24"; -- #
when 16#723# => romdata <= X"7e"; -- #
when 16#823# => romdata <= X"24"; -- #
when 16#923# => romdata <= X"24"; -- #
when 16#a23# => romdata <= X"00"; -- #
when 16#b23# => romdata <= X"00"; -- #
when 16#c23# => romdata <= X"00"; -- #
when 16#024# => romdata <= X"00"; -- $
when 16#124# => romdata <= X"00"; -- $
when 16#224# => romdata <= X"10"; -- $
when 16#324# => romdata <= X"3c"; -- $
when 16#424# => romdata <= X"50"; -- $
when 16#524# => romdata <= X"50"; -- $
when 16#624# => romdata <= X"38"; -- $
when 16#724# => romdata <= X"14"; -- $
when 16#824# => romdata <= X"14"; -- $
when 16#924# => romdata <= X"78"; -- $
when 16#a24# => romdata <= X"10"; -- $
when 16#b24# => romdata <= X"00"; -- $
when 16#c24# => romdata <= X"00"; -- $
when 16#025# => romdata <= X"00"; -- %
when 16#125# => romdata <= X"00"; -- %
when 16#225# => romdata <= X"22"; -- %
when 16#325# => romdata <= X"52"; -- %
when 16#425# => romdata <= X"24"; -- %
when 16#525# => romdata <= X"08"; -- %
when 16#625# => romdata <= X"08"; -- %
when 16#725# => romdata <= X"10"; -- %
when 16#825# => romdata <= X"24"; -- %
when 16#925# => romdata <= X"2a"; -- %
when 16#a25# => romdata <= X"44"; -- %
when 16#b25# => romdata <= X"00"; -- %
when 16#c25# => romdata <= X"00"; -- %
when 16#026# => romdata <= X"00"; -- &
when 16#126# => romdata <= X"00"; -- &
when 16#226# => romdata <= X"00"; -- &
when 16#326# => romdata <= X"00"; -- &
when 16#426# => romdata <= X"30"; -- &
when 16#526# => romdata <= X"48"; -- &
when 16#626# => romdata <= X"48"; -- &
when 16#726# => romdata <= X"30"; -- &
when 16#826# => romdata <= X"4a"; -- &
when 16#926# => romdata <= X"44"; -- &
when 16#a26# => romdata <= X"3a"; -- &
when 16#b26# => romdata <= X"00"; -- &
when 16#c26# => romdata <= X"00"; -- &
when 16#027# => romdata <= X"00"; -- '
when 16#127# => romdata <= X"00"; -- '
when 16#227# => romdata <= X"10"; -- '
when 16#327# => romdata <= X"10"; -- '
when 16#427# => romdata <= X"10"; -- '
when 16#527# => romdata <= X"00"; -- '
when 16#627# => romdata <= X"00"; -- '
when 16#727# => romdata <= X"00"; -- '
when 16#827# => romdata <= X"00"; -- '
when 16#927# => romdata <= X"00"; -- '
when 16#a27# => romdata <= X"00"; -- '
when 16#b27# => romdata <= X"00"; -- '
when 16#c27# => romdata <= X"00"; -- '
when 16#028# => romdata <= X"00"; -- (
when 16#128# => romdata <= X"00"; -- (
when 16#228# => romdata <= X"04"; -- (
when 16#328# => romdata <= X"08"; -- (
when 16#428# => romdata <= X"08"; -- (
when 16#528# => romdata <= X"10"; -- (
when 16#628# => romdata <= X"10"; -- (
when 16#728# => romdata <= X"10"; -- (
when 16#828# => romdata <= X"08"; -- (
when 16#928# => romdata <= X"08"; -- (
when 16#a28# => romdata <= X"04"; -- (
when 16#b28# => romdata <= X"00"; -- (
when 16#c28# => romdata <= X"00"; -- (
when 16#029# => romdata <= X"00"; -- )
when 16#129# => romdata <= X"00"; -- )
when 16#229# => romdata <= X"20"; -- )
when 16#329# => romdata <= X"10"; -- )
when 16#429# => romdata <= X"10"; -- )
when 16#529# => romdata <= X"08"; -- )
when 16#629# => romdata <= X"08"; -- )
when 16#729# => romdata <= X"08"; -- )
when 16#829# => romdata <= X"10"; -- )
when 16#929# => romdata <= X"10"; -- )
when 16#a29# => romdata <= X"20"; -- )
when 16#b29# => romdata <= X"00"; -- )
when 16#c29# => romdata <= X"00"; -- )
when 16#02a# => romdata <= X"00"; -- *
when 16#12a# => romdata <= X"00"; -- *
when 16#22a# => romdata <= X"24"; -- *
when 16#32a# => romdata <= X"18"; -- *
when 16#42a# => romdata <= X"7e"; -- *
when 16#52a# => romdata <= X"18"; -- *
when 16#62a# => romdata <= X"24"; -- *
when 16#72a# => romdata <= X"00"; -- *
when 16#82a# => romdata <= X"00"; -- *
when 16#92a# => romdata <= X"00"; -- *
when 16#a2a# => romdata <= X"00"; -- *
when 16#b2a# => romdata <= X"00"; -- *
when 16#c2a# => romdata <= X"00"; -- *
when 16#02b# => romdata <= X"00"; -- +
when 16#12b# => romdata <= X"00"; -- +
when 16#22b# => romdata <= X"00"; -- +
when 16#32b# => romdata <= X"00"; -- +
when 16#42b# => romdata <= X"10"; -- +
when 16#52b# => romdata <= X"10"; -- +
when 16#62b# => romdata <= X"7c"; -- +
when 16#72b# => romdata <= X"10"; -- +
when 16#82b# => romdata <= X"10"; -- +
when 16#92b# => romdata <= X"00"; -- +
when 16#a2b# => romdata <= X"00"; -- +
when 16#b2b# => romdata <= X"00"; -- +
when 16#c2b# => romdata <= X"00"; -- +
when 16#02c# => romdata <= X"00"; -- ,
when 16#12c# => romdata <= X"00"; -- ,
when 16#22c# => romdata <= X"00"; -- ,
when 16#32c# => romdata <= X"00"; -- ,
when 16#42c# => romdata <= X"00"; -- ,
when 16#52c# => romdata <= X"00"; -- ,
when 16#62c# => romdata <= X"00"; -- ,
when 16#72c# => romdata <= X"00"; -- ,
when 16#82c# => romdata <= X"00"; -- ,
when 16#92c# => romdata <= X"38"; -- ,
when 16#a2c# => romdata <= X"30"; -- ,
when 16#b2c# => romdata <= X"40"; -- ,
when 16#c2c# => romdata <= X"00"; -- ,
when 16#02d# => romdata <= X"00"; -- -
when 16#12d# => romdata <= X"00"; -- -
when 16#22d# => romdata <= X"00"; -- -
when 16#32d# => romdata <= X"00"; -- -
when 16#42d# => romdata <= X"00"; -- -
when 16#52d# => romdata <= X"00"; -- -
when 16#62d# => romdata <= X"7c"; -- -
when 16#72d# => romdata <= X"00"; -- -
when 16#82d# => romdata <= X"00"; -- -
when 16#92d# => romdata <= X"00"; -- -
when 16#a2d# => romdata <= X"00"; -- -
when 16#b2d# => romdata <= X"00"; -- -
when 16#c2d# => romdata <= X"00"; -- -
when 16#02e# => romdata <= X"00"; -- .
when 16#12e# => romdata <= X"00"; -- .
when 16#22e# => romdata <= X"00"; -- .
when 16#32e# => romdata <= X"00"; -- .
when 16#42e# => romdata <= X"00"; -- .
when 16#52e# => romdata <= X"00"; -- .
when 16#62e# => romdata <= X"00"; -- .
when 16#72e# => romdata <= X"00"; -- .
when 16#82e# => romdata <= X"00"; -- .
when 16#92e# => romdata <= X"10"; -- .
when 16#a2e# => romdata <= X"38"; -- .
when 16#b2e# => romdata <= X"10"; -- .
when 16#c2e# => romdata <= X"00"; -- .
when 16#02f# => romdata <= X"00"; -- /
when 16#12f# => romdata <= X"00"; -- /
when 16#22f# => romdata <= X"02"; -- /
when 16#32f# => romdata <= X"02"; -- /
when 16#42f# => romdata <= X"04"; -- /
when 16#52f# => romdata <= X"08"; -- /
when 16#62f# => romdata <= X"10"; -- /
when 16#72f# => romdata <= X"20"; -- /
when 16#82f# => romdata <= X"40"; -- /
when 16#92f# => romdata <= X"80"; -- /
when 16#a2f# => romdata <= X"80"; -- /
when 16#b2f# => romdata <= X"00"; -- /
when 16#c2f# => romdata <= X"00"; -- /
when 16#030# => romdata <= X"00"; -- 0
when 16#130# => romdata <= X"00"; -- 0
when 16#230# => romdata <= X"18"; -- 0
when 16#330# => romdata <= X"24"; -- 0
when 16#430# => romdata <= X"42"; -- 0
when 16#530# => romdata <= X"42"; -- 0
when 16#630# => romdata <= X"42"; -- 0
when 16#730# => romdata <= X"42"; -- 0
when 16#830# => romdata <= X"42"; -- 0
when 16#930# => romdata <= X"24"; -- 0
when 16#a30# => romdata <= X"18"; -- 0
when 16#b30# => romdata <= X"00"; -- 0
when 16#c30# => romdata <= X"00"; -- 0
when 16#031# => romdata <= X"00"; -- 1
when 16#131# => romdata <= X"00"; -- 1
when 16#231# => romdata <= X"10"; -- 1
when 16#331# => romdata <= X"30"; -- 1
when 16#431# => romdata <= X"50"; -- 1
when 16#531# => romdata <= X"10"; -- 1
when 16#631# => romdata <= X"10"; -- 1
when 16#731# => romdata <= X"10"; -- 1
when 16#831# => romdata <= X"10"; -- 1
when 16#931# => romdata <= X"10"; -- 1
when 16#a31# => romdata <= X"7c"; -- 1
when 16#b31# => romdata <= X"00"; -- 1
when 16#c31# => romdata <= X"00"; -- 1
when 16#032# => romdata <= X"00"; -- 2
when 16#132# => romdata <= X"00"; -- 2
when 16#232# => romdata <= X"3c"; -- 2
when 16#332# => romdata <= X"42"; -- 2
when 16#432# => romdata <= X"42"; -- 2
when 16#532# => romdata <= X"02"; -- 2
when 16#632# => romdata <= X"04"; -- 2
when 16#732# => romdata <= X"18"; -- 2
when 16#832# => romdata <= X"20"; -- 2
when 16#932# => romdata <= X"40"; -- 2
when 16#a32# => romdata <= X"7e"; -- 2
when 16#b32# => romdata <= X"00"; -- 2
when 16#c32# => romdata <= X"00"; -- 2
when 16#033# => romdata <= X"00"; -- 3
when 16#133# => romdata <= X"00"; -- 3
when 16#233# => romdata <= X"7e"; -- 3
when 16#333# => romdata <= X"02"; -- 3
when 16#433# => romdata <= X"04"; -- 3
when 16#533# => romdata <= X"08"; -- 3
when 16#633# => romdata <= X"1c"; -- 3
when 16#733# => romdata <= X"02"; -- 3
when 16#833# => romdata <= X"02"; -- 3
when 16#933# => romdata <= X"42"; -- 3
when 16#a33# => romdata <= X"3c"; -- 3
when 16#b33# => romdata <= X"00"; -- 3
when 16#c33# => romdata <= X"00"; -- 3
when 16#034# => romdata <= X"00"; -- 4
when 16#134# => romdata <= X"00"; -- 4
when 16#234# => romdata <= X"04"; -- 4
when 16#334# => romdata <= X"0c"; -- 4
when 16#434# => romdata <= X"14"; -- 4
when 16#534# => romdata <= X"24"; -- 4
when 16#634# => romdata <= X"44"; -- 4
when 16#734# => romdata <= X"44"; -- 4
when 16#834# => romdata <= X"7e"; -- 4
when 16#934# => romdata <= X"04"; -- 4
when 16#a34# => romdata <= X"04"; -- 4
when 16#b34# => romdata <= X"00"; -- 4
when 16#c34# => romdata <= X"00"; -- 4
when 16#035# => romdata <= X"00"; -- 5
when 16#135# => romdata <= X"00"; -- 5
when 16#235# => romdata <= X"7e"; -- 5
when 16#335# => romdata <= X"40"; -- 5
when 16#435# => romdata <= X"40"; -- 5
when 16#535# => romdata <= X"5c"; -- 5
when 16#635# => romdata <= X"62"; -- 5
when 16#735# => romdata <= X"02"; -- 5
when 16#835# => romdata <= X"02"; -- 5
when 16#935# => romdata <= X"42"; -- 5
when 16#a35# => romdata <= X"3c"; -- 5
when 16#b35# => romdata <= X"00"; -- 5
when 16#c35# => romdata <= X"00"; -- 5
when 16#036# => romdata <= X"00"; -- 6
when 16#136# => romdata <= X"00"; -- 6
when 16#236# => romdata <= X"1c"; -- 6
when 16#336# => romdata <= X"20"; -- 6
when 16#436# => romdata <= X"40"; -- 6
when 16#536# => romdata <= X"40"; -- 6
when 16#636# => romdata <= X"5c"; -- 6
when 16#736# => romdata <= X"62"; -- 6
when 16#836# => romdata <= X"42"; -- 6
when 16#936# => romdata <= X"42"; -- 6
when 16#a36# => romdata <= X"3c"; -- 6
when 16#b36# => romdata <= X"00"; -- 6
when 16#c36# => romdata <= X"00"; -- 6
when 16#037# => romdata <= X"00"; -- 7
when 16#137# => romdata <= X"00"; -- 7
when 16#237# => romdata <= X"7e"; -- 7
when 16#337# => romdata <= X"02"; -- 7
when 16#437# => romdata <= X"04"; -- 7
when 16#537# => romdata <= X"08"; -- 7
when 16#637# => romdata <= X"08"; -- 7
when 16#737# => romdata <= X"10"; -- 7
when 16#837# => romdata <= X"10"; -- 7
when 16#937# => romdata <= X"20"; -- 7
when 16#a37# => romdata <= X"20"; -- 7
when 16#b37# => romdata <= X"00"; -- 7
when 16#c37# => romdata <= X"00"; -- 7
when 16#038# => romdata <= X"00"; -- 8
when 16#138# => romdata <= X"00"; -- 8
when 16#238# => romdata <= X"3c"; -- 8
when 16#338# => romdata <= X"42"; -- 8
when 16#438# => romdata <= X"42"; -- 8
when 16#538# => romdata <= X"42"; -- 8
when 16#638# => romdata <= X"3c"; -- 8
when 16#738# => romdata <= X"42"; -- 8
when 16#838# => romdata <= X"42"; -- 8
when 16#938# => romdata <= X"42"; -- 8
when 16#a38# => romdata <= X"3c"; -- 8
when 16#b38# => romdata <= X"00"; -- 8
when 16#c38# => romdata <= X"00"; -- 8
when 16#039# => romdata <= X"00"; -- 9
when 16#139# => romdata <= X"00"; -- 9
when 16#239# => romdata <= X"3c"; -- 9
when 16#339# => romdata <= X"42"; -- 9
when 16#439# => romdata <= X"42"; -- 9
when 16#539# => romdata <= X"46"; -- 9
when 16#639# => romdata <= X"3a"; -- 9
when 16#739# => romdata <= X"02"; -- 9
when 16#839# => romdata <= X"02"; -- 9
when 16#939# => romdata <= X"04"; -- 9
when 16#a39# => romdata <= X"38"; -- 9
when 16#b39# => romdata <= X"00"; -- 9
when 16#c39# => romdata <= X"00"; -- 9
when 16#03a# => romdata <= X"00"; -- :
when 16#13a# => romdata <= X"00"; -- :
when 16#23a# => romdata <= X"00"; -- :
when 16#33a# => romdata <= X"00"; -- :
when 16#43a# => romdata <= X"10"; -- :
when 16#53a# => romdata <= X"38"; -- :
when 16#63a# => romdata <= X"10"; -- :
when 16#73a# => romdata <= X"00"; -- :
when 16#83a# => romdata <= X"00"; -- :
when 16#93a# => romdata <= X"10"; -- :
when 16#a3a# => romdata <= X"38"; -- :
when 16#b3a# => romdata <= X"10"; -- :
when 16#c3a# => romdata <= X"00"; -- :
when 16#03b# => romdata <= X"00"; -- ;
when 16#13b# => romdata <= X"00"; -- ;
when 16#23b# => romdata <= X"00"; -- ;
when 16#33b# => romdata <= X"00"; -- ;
when 16#43b# => romdata <= X"10"; -- ;
when 16#53b# => romdata <= X"38"; -- ;
when 16#63b# => romdata <= X"10"; -- ;
when 16#73b# => romdata <= X"00"; -- ;
when 16#83b# => romdata <= X"00"; -- ;
when 16#93b# => romdata <= X"38"; -- ;
when 16#a3b# => romdata <= X"30"; -- ;
when 16#b3b# => romdata <= X"40"; -- ;
when 16#c3b# => romdata <= X"00"; -- ;
when 16#03c# => romdata <= X"00"; -- <
when 16#13c# => romdata <= X"00"; -- <
when 16#23c# => romdata <= X"02"; -- <
when 16#33c# => romdata <= X"04"; -- <
when 16#43c# => romdata <= X"08"; -- <
when 16#53c# => romdata <= X"10"; -- <
when 16#63c# => romdata <= X"20"; -- <
when 16#73c# => romdata <= X"10"; -- <
when 16#83c# => romdata <= X"08"; -- <
when 16#93c# => romdata <= X"04"; -- <
when 16#a3c# => romdata <= X"02"; -- <
when 16#b3c# => romdata <= X"00"; -- <
when 16#c3c# => romdata <= X"00"; -- <
when 16#03d# => romdata <= X"00"; -- =
when 16#13d# => romdata <= X"00"; -- =
when 16#23d# => romdata <= X"00"; -- =
when 16#33d# => romdata <= X"00"; -- =
when 16#43d# => romdata <= X"00"; -- =
when 16#53d# => romdata <= X"7e"; -- =
when 16#63d# => romdata <= X"00"; -- =
when 16#73d# => romdata <= X"00"; -- =
when 16#83d# => romdata <= X"7e"; -- =
when 16#93d# => romdata <= X"00"; -- =
when 16#a3d# => romdata <= X"00"; -- =
when 16#b3d# => romdata <= X"00"; -- =
when 16#c3d# => romdata <= X"00"; -- =
when 16#03e# => romdata <= X"00"; -- >
when 16#13e# => romdata <= X"00"; -- >
when 16#23e# => romdata <= X"40"; -- >
when 16#33e# => romdata <= X"20"; -- >
when 16#43e# => romdata <= X"10"; -- >
when 16#53e# => romdata <= X"08"; -- >
when 16#63e# => romdata <= X"04"; -- >
when 16#73e# => romdata <= X"08"; -- >
when 16#83e# => romdata <= X"10"; -- >
when 16#93e# => romdata <= X"20"; -- >
when 16#a3e# => romdata <= X"40"; -- >
when 16#b3e# => romdata <= X"00"; -- >
when 16#c3e# => romdata <= X"00"; -- >
when 16#03f# => romdata <= X"00"; -- ?
when 16#13f# => romdata <= X"00"; -- ?
when 16#23f# => romdata <= X"3c"; -- ?
when 16#33f# => romdata <= X"42"; -- ?
when 16#43f# => romdata <= X"42"; -- ?
when 16#53f# => romdata <= X"02"; -- ?
when 16#63f# => romdata <= X"04"; -- ?
when 16#73f# => romdata <= X"08"; -- ?
when 16#83f# => romdata <= X"08"; -- ?
when 16#93f# => romdata <= X"00"; -- ?
when 16#a3f# => romdata <= X"08"; -- ?
when 16#b3f# => romdata <= X"00"; -- ?
when 16#c3f# => romdata <= X"00"; -- ?
when 16#040# => romdata <= X"00"; -- @
when 16#140# => romdata <= X"00"; -- @
when 16#240# => romdata <= X"3c"; -- @
when 16#340# => romdata <= X"42"; -- @
when 16#440# => romdata <= X"42"; -- @
when 16#540# => romdata <= X"4e"; -- @
when 16#640# => romdata <= X"52"; -- @
when 16#740# => romdata <= X"56"; -- @
when 16#840# => romdata <= X"4a"; -- @
when 16#940# => romdata <= X"40"; -- @
when 16#a40# => romdata <= X"3c"; -- @
when 16#b40# => romdata <= X"00"; -- @
when 16#c40# => romdata <= X"00"; -- @
when 16#041# => romdata <= X"00"; -- A
when 16#141# => romdata <= X"00"; -- A
when 16#241# => romdata <= X"18"; -- A
when 16#341# => romdata <= X"24"; -- A
when 16#441# => romdata <= X"42"; -- A
when 16#541# => romdata <= X"42"; -- A
when 16#641# => romdata <= X"42"; -- A
when 16#741# => romdata <= X"7e"; -- A
when 16#841# => romdata <= X"42"; -- A
when 16#941# => romdata <= X"42"; -- A
when 16#a41# => romdata <= X"42"; -- A
when 16#b41# => romdata <= X"00"; -- A
when 16#c41# => romdata <= X"00"; -- A
when 16#042# => romdata <= X"00"; -- B
when 16#142# => romdata <= X"00"; -- B
when 16#242# => romdata <= X"78"; -- B
when 16#342# => romdata <= X"44"; -- B
when 16#442# => romdata <= X"42"; -- B
when 16#542# => romdata <= X"44"; -- B
when 16#642# => romdata <= X"78"; -- B
when 16#742# => romdata <= X"44"; -- B
when 16#842# => romdata <= X"42"; -- B
when 16#942# => romdata <= X"44"; -- B
when 16#a42# => romdata <= X"78"; -- B
when 16#b42# => romdata <= X"00"; -- B
when 16#c42# => romdata <= X"00"; -- B
when 16#043# => romdata <= X"00"; -- C
when 16#143# => romdata <= X"00"; -- C
when 16#243# => romdata <= X"3c"; -- C
when 16#343# => romdata <= X"42"; -- C
when 16#443# => romdata <= X"40"; -- C
when 16#543# => romdata <= X"40"; -- C
when 16#643# => romdata <= X"40"; -- C
when 16#743# => romdata <= X"40"; -- C
when 16#843# => romdata <= X"40"; -- C
when 16#943# => romdata <= X"42"; -- C
when 16#a43# => romdata <= X"3c"; -- C
when 16#b43# => romdata <= X"00"; -- C
when 16#c43# => romdata <= X"00"; -- C
when 16#044# => romdata <= X"00"; -- D
when 16#144# => romdata <= X"00"; -- D
when 16#244# => romdata <= X"78"; -- D
when 16#344# => romdata <= X"44"; -- D
when 16#444# => romdata <= X"42"; -- D
when 16#544# => romdata <= X"42"; -- D
when 16#644# => romdata <= X"42"; -- D
when 16#744# => romdata <= X"42"; -- D
when 16#844# => romdata <= X"42"; -- D
when 16#944# => romdata <= X"44"; -- D
when 16#a44# => romdata <= X"78"; -- D
when 16#b44# => romdata <= X"00"; -- D
when 16#c44# => romdata <= X"00"; -- D
when 16#045# => romdata <= X"00"; -- E
when 16#145# => romdata <= X"00"; -- E
when 16#245# => romdata <= X"7e"; -- E
when 16#345# => romdata <= X"40"; -- E
when 16#445# => romdata <= X"40"; -- E
when 16#545# => romdata <= X"40"; -- E
when 16#645# => romdata <= X"78"; -- E
when 16#745# => romdata <= X"40"; -- E
when 16#845# => romdata <= X"40"; -- E
when 16#945# => romdata <= X"40"; -- E
when 16#a45# => romdata <= X"7e"; -- E
when 16#b45# => romdata <= X"00"; -- E
when 16#c45# => romdata <= X"00"; -- E
when 16#046# => romdata <= X"00"; -- F
when 16#146# => romdata <= X"00"; -- F
when 16#246# => romdata <= X"7e"; -- F
when 16#346# => romdata <= X"40"; -- F
when 16#446# => romdata <= X"40"; -- F
when 16#546# => romdata <= X"40"; -- F
when 16#646# => romdata <= X"78"; -- F
when 16#746# => romdata <= X"40"; -- F
when 16#846# => romdata <= X"40"; -- F
when 16#946# => romdata <= X"40"; -- F
when 16#a46# => romdata <= X"40"; -- F
when 16#b46# => romdata <= X"00"; -- F
when 16#c46# => romdata <= X"00"; -- F
when 16#047# => romdata <= X"00"; -- G
when 16#147# => romdata <= X"00"; -- G
when 16#247# => romdata <= X"3c"; -- G
when 16#347# => romdata <= X"42"; -- G
when 16#447# => romdata <= X"40"; -- G
when 16#547# => romdata <= X"40"; -- G
when 16#647# => romdata <= X"40"; -- G
when 16#747# => romdata <= X"4e"; -- G
when 16#847# => romdata <= X"42"; -- G
when 16#947# => romdata <= X"46"; -- G
when 16#a47# => romdata <= X"3a"; -- G
when 16#b47# => romdata <= X"00"; -- G
when 16#c47# => romdata <= X"00"; -- G
when 16#048# => romdata <= X"00"; -- H
when 16#148# => romdata <= X"00"; -- H
when 16#248# => romdata <= X"42"; -- H
when 16#348# => romdata <= X"42"; -- H
when 16#448# => romdata <= X"42"; -- H
when 16#548# => romdata <= X"42"; -- H
when 16#648# => romdata <= X"7e"; -- H
when 16#748# => romdata <= X"42"; -- H
when 16#848# => romdata <= X"42"; -- H
when 16#948# => romdata <= X"42"; -- H
when 16#a48# => romdata <= X"42"; -- H
when 16#b48# => romdata <= X"00"; -- H
when 16#c48# => romdata <= X"00"; -- H
when 16#049# => romdata <= X"00"; -- I
when 16#149# => romdata <= X"00"; -- I
when 16#249# => romdata <= X"7c"; -- I
when 16#349# => romdata <= X"10"; -- I
when 16#449# => romdata <= X"10"; -- I
when 16#549# => romdata <= X"10"; -- I
when 16#649# => romdata <= X"10"; -- I
when 16#749# => romdata <= X"10"; -- I
when 16#849# => romdata <= X"10"; -- I
when 16#949# => romdata <= X"10"; -- I
when 16#a49# => romdata <= X"7c"; -- I
when 16#b49# => romdata <= X"00"; -- I
when 16#c49# => romdata <= X"00"; -- I
when 16#04a# => romdata <= X"00"; -- J
when 16#14a# => romdata <= X"00"; -- J
when 16#24a# => romdata <= X"1f"; -- J
when 16#34a# => romdata <= X"04"; -- J
when 16#44a# => romdata <= X"04"; -- J
when 16#54a# => romdata <= X"04"; -- J
when 16#64a# => romdata <= X"04"; -- J
when 16#74a# => romdata <= X"04"; -- J
when 16#84a# => romdata <= X"04"; -- J
when 16#94a# => romdata <= X"44"; -- J
when 16#a4a# => romdata <= X"38"; -- J
when 16#b4a# => romdata <= X"00"; -- J
when 16#c4a# => romdata <= X"00"; -- J
when 16#04b# => romdata <= X"00"; -- K
when 16#14b# => romdata <= X"00"; -- K
when 16#24b# => romdata <= X"42"; -- K
when 16#34b# => romdata <= X"44"; -- K
when 16#44b# => romdata <= X"48"; -- K
when 16#54b# => romdata <= X"50"; -- K
when 16#64b# => romdata <= X"60"; -- K
when 16#74b# => romdata <= X"50"; -- K
when 16#84b# => romdata <= X"48"; -- K
when 16#94b# => romdata <= X"44"; -- K
when 16#a4b# => romdata <= X"42"; -- K
when 16#b4b# => romdata <= X"00"; -- K
when 16#c4b# => romdata <= X"00"; -- K
when 16#04c# => romdata <= X"00"; -- L
when 16#14c# => romdata <= X"00"; -- L
when 16#24c# => romdata <= X"40"; -- L
when 16#34c# => romdata <= X"40"; -- L
when 16#44c# => romdata <= X"40"; -- L
when 16#54c# => romdata <= X"40"; -- L
when 16#64c# => romdata <= X"40"; -- L
when 16#74c# => romdata <= X"40"; -- L
when 16#84c# => romdata <= X"40"; -- L
when 16#94c# => romdata <= X"40"; -- L
when 16#a4c# => romdata <= X"7e"; -- L
when 16#b4c# => romdata <= X"00"; -- L
when 16#c4c# => romdata <= X"00"; -- L
when 16#04d# => romdata <= X"00"; -- M
when 16#14d# => romdata <= X"00"; -- M
when 16#24d# => romdata <= X"82"; -- M
when 16#34d# => romdata <= X"82"; -- M
when 16#44d# => romdata <= X"c6"; -- M
when 16#54d# => romdata <= X"aa"; -- M
when 16#64d# => romdata <= X"92"; -- M
when 16#74d# => romdata <= X"92"; -- M
when 16#84d# => romdata <= X"82"; -- M
when 16#94d# => romdata <= X"82"; -- M
when 16#a4d# => romdata <= X"82"; -- M
when 16#b4d# => romdata <= X"00"; -- M
when 16#c4d# => romdata <= X"00"; -- M
when 16#04e# => romdata <= X"00"; -- N
when 16#14e# => romdata <= X"00"; -- N
when 16#24e# => romdata <= X"42"; -- N
when 16#34e# => romdata <= X"42"; -- N
when 16#44e# => romdata <= X"62"; -- N
when 16#54e# => romdata <= X"52"; -- N
when 16#64e# => romdata <= X"4a"; -- N
when 16#74e# => romdata <= X"46"; -- N
when 16#84e# => romdata <= X"42"; -- N
when 16#94e# => romdata <= X"42"; -- N
when 16#a4e# => romdata <= X"42"; -- N
when 16#b4e# => romdata <= X"00"; -- N
when 16#c4e# => romdata <= X"00"; -- N
when 16#04f# => romdata <= X"00"; -- O
when 16#14f# => romdata <= X"00"; -- O
when 16#24f# => romdata <= X"3c"; -- O
when 16#34f# => romdata <= X"42"; -- O
when 16#44f# => romdata <= X"42"; -- O
when 16#54f# => romdata <= X"42"; -- O
when 16#64f# => romdata <= X"42"; -- O
when 16#74f# => romdata <= X"42"; -- O
when 16#84f# => romdata <= X"42"; -- O
when 16#94f# => romdata <= X"42"; -- O
when 16#a4f# => romdata <= X"3c"; -- O
when 16#b4f# => romdata <= X"00"; -- O
when 16#c4f# => romdata <= X"00"; -- O
when 16#050# => romdata <= X"00"; -- P
when 16#150# => romdata <= X"00"; -- P
when 16#250# => romdata <= X"7c"; -- P
when 16#350# => romdata <= X"42"; -- P
when 16#450# => romdata <= X"42"; -- P
when 16#550# => romdata <= X"42"; -- P
when 16#650# => romdata <= X"7c"; -- P
when 16#750# => romdata <= X"40"; -- P
when 16#850# => romdata <= X"40"; -- P
when 16#950# => romdata <= X"40"; -- P
when 16#a50# => romdata <= X"40"; -- P
when 16#b50# => romdata <= X"00"; -- P
when 16#c50# => romdata <= X"00"; -- P
when 16#051# => romdata <= X"00"; -- Q
when 16#151# => romdata <= X"00"; -- Q
when 16#251# => romdata <= X"3c"; -- Q
when 16#351# => romdata <= X"42"; -- Q
when 16#451# => romdata <= X"42"; -- Q
when 16#551# => romdata <= X"42"; -- Q
when 16#651# => romdata <= X"42"; -- Q
when 16#751# => romdata <= X"42"; -- Q
when 16#851# => romdata <= X"52"; -- Q
when 16#951# => romdata <= X"4a"; -- Q
when 16#a51# => romdata <= X"3c"; -- Q
when 16#b51# => romdata <= X"02"; -- Q
when 16#c51# => romdata <= X"00"; -- Q
when 16#052# => romdata <= X"00"; -- R
when 16#152# => romdata <= X"00"; -- R
when 16#252# => romdata <= X"7c"; -- R
when 16#352# => romdata <= X"42"; -- R
when 16#452# => romdata <= X"42"; -- R
when 16#552# => romdata <= X"42"; -- R
when 16#652# => romdata <= X"7c"; -- R
when 16#752# => romdata <= X"50"; -- R
when 16#852# => romdata <= X"48"; -- R
when 16#952# => romdata <= X"44"; -- R
when 16#a52# => romdata <= X"42"; -- R
when 16#b52# => romdata <= X"00"; -- R
when 16#c52# => romdata <= X"00"; -- R
when 16#053# => romdata <= X"00"; -- S
when 16#153# => romdata <= X"00"; -- S
when 16#253# => romdata <= X"3c"; -- S
when 16#353# => romdata <= X"42"; -- S
when 16#453# => romdata <= X"40"; -- S
when 16#553# => romdata <= X"40"; -- S
when 16#653# => romdata <= X"3c"; -- S
when 16#753# => romdata <= X"02"; -- S
when 16#853# => romdata <= X"02"; -- S
when 16#953# => romdata <= X"42"; -- S
when 16#a53# => romdata <= X"3c"; -- S
when 16#b53# => romdata <= X"00"; -- S
when 16#c53# => romdata <= X"00"; -- S
when 16#054# => romdata <= X"00"; -- T
when 16#154# => romdata <= X"00"; -- T
when 16#254# => romdata <= X"fe"; -- T
when 16#354# => romdata <= X"10"; -- T
when 16#454# => romdata <= X"10"; -- T
when 16#554# => romdata <= X"10"; -- T
when 16#654# => romdata <= X"10"; -- T
when 16#754# => romdata <= X"10"; -- T
when 16#854# => romdata <= X"10"; -- T
when 16#954# => romdata <= X"10"; -- T
when 16#a54# => romdata <= X"10"; -- T
when 16#b54# => romdata <= X"00"; -- T
when 16#c54# => romdata <= X"00"; -- T
when 16#055# => romdata <= X"00"; -- U
when 16#155# => romdata <= X"00"; -- U
when 16#255# => romdata <= X"42"; -- U
when 16#355# => romdata <= X"42"; -- U
when 16#455# => romdata <= X"42"; -- U
when 16#555# => romdata <= X"42"; -- U
when 16#655# => romdata <= X"42"; -- U
when 16#755# => romdata <= X"42"; -- U
when 16#855# => romdata <= X"42"; -- U
when 16#955# => romdata <= X"42"; -- U
when 16#a55# => romdata <= X"3c"; -- U
when 16#b55# => romdata <= X"00"; -- U
when 16#c55# => romdata <= X"00"; -- U
when 16#056# => romdata <= X"00"; -- V
when 16#156# => romdata <= X"00"; -- V
when 16#256# => romdata <= X"82"; -- V
when 16#356# => romdata <= X"82"; -- V
when 16#456# => romdata <= X"44"; -- V
when 16#556# => romdata <= X"44"; -- V
when 16#656# => romdata <= X"44"; -- V
when 16#756# => romdata <= X"28"; -- V
when 16#856# => romdata <= X"28"; -- V
when 16#956# => romdata <= X"28"; -- V
when 16#a56# => romdata <= X"10"; -- V
when 16#b56# => romdata <= X"00"; -- V
when 16#c56# => romdata <= X"00"; -- V
when 16#057# => romdata <= X"00"; -- W
when 16#157# => romdata <= X"00"; -- W
when 16#257# => romdata <= X"82"; -- W
when 16#357# => romdata <= X"82"; -- W
when 16#457# => romdata <= X"82"; -- W
when 16#557# => romdata <= X"82"; -- W
when 16#657# => romdata <= X"92"; -- W
when 16#757# => romdata <= X"92"; -- W
when 16#857# => romdata <= X"92"; -- W
when 16#957# => romdata <= X"aa"; -- W
when 16#a57# => romdata <= X"44"; -- W
when 16#b57# => romdata <= X"00"; -- W
when 16#c57# => romdata <= X"00"; -- W
when 16#058# => romdata <= X"00"; -- X
when 16#158# => romdata <= X"00"; -- X
when 16#258# => romdata <= X"82"; -- X
when 16#358# => romdata <= X"82"; -- X
when 16#458# => romdata <= X"44"; -- X
when 16#558# => romdata <= X"28"; -- X
when 16#658# => romdata <= X"10"; -- X
when 16#758# => romdata <= X"28"; -- X
when 16#858# => romdata <= X"44"; -- X
when 16#958# => romdata <= X"82"; -- X
when 16#a58# => romdata <= X"82"; -- X
when 16#b58# => romdata <= X"00"; -- X
when 16#c58# => romdata <= X"00"; -- X
when 16#059# => romdata <= X"00"; -- Y
when 16#159# => romdata <= X"00"; -- Y
when 16#259# => romdata <= X"82"; -- Y
when 16#359# => romdata <= X"82"; -- Y
when 16#459# => romdata <= X"44"; -- Y
when 16#559# => romdata <= X"28"; -- Y
when 16#659# => romdata <= X"10"; -- Y
when 16#759# => romdata <= X"10"; -- Y
when 16#859# => romdata <= X"10"; -- Y
when 16#959# => romdata <= X"10"; -- Y
when 16#a59# => romdata <= X"10"; -- Y
when 16#b59# => romdata <= X"00"; -- Y
when 16#c59# => romdata <= X"00"; -- Y
when 16#05a# => romdata <= X"00"; -- Z
when 16#15a# => romdata <= X"00"; -- Z
when 16#25a# => romdata <= X"7e"; -- Z
when 16#35a# => romdata <= X"02"; -- Z
when 16#45a# => romdata <= X"04"; -- Z
when 16#55a# => romdata <= X"08"; -- Z
when 16#65a# => romdata <= X"10"; -- Z
when 16#75a# => romdata <= X"20"; -- Z
when 16#85a# => romdata <= X"40"; -- Z
when 16#95a# => romdata <= X"40"; -- Z
when 16#a5a# => romdata <= X"7e"; -- Z
when 16#b5a# => romdata <= X"00"; -- Z
when 16#c5a# => romdata <= X"00"; -- Z
when 16#05b# => romdata <= X"00"; -- [
when 16#15b# => romdata <= X"00"; -- [
when 16#25b# => romdata <= X"3c"; -- [
when 16#35b# => romdata <= X"20"; -- [
when 16#45b# => romdata <= X"20"; -- [
when 16#55b# => romdata <= X"20"; -- [
when 16#65b# => romdata <= X"20"; -- [
when 16#75b# => romdata <= X"20"; -- [
when 16#85b# => romdata <= X"20"; -- [
when 16#95b# => romdata <= X"20"; -- [
when 16#a5b# => romdata <= X"3c"; -- [
when 16#b5b# => romdata <= X"00"; -- [
when 16#c5b# => romdata <= X"00"; -- [
when 16#05c# => romdata <= X"00"; -- \
when 16#15c# => romdata <= X"00"; -- \
when 16#25c# => romdata <= X"80"; -- \
when 16#35c# => romdata <= X"80"; -- \
when 16#45c# => romdata <= X"40"; -- \
when 16#55c# => romdata <= X"20"; -- \
when 16#65c# => romdata <= X"10"; -- \
when 16#75c# => romdata <= X"08"; -- \
when 16#85c# => romdata <= X"04"; -- \
when 16#95c# => romdata <= X"02"; -- \
when 16#a5c# => romdata <= X"02"; -- \
when 16#b5c# => romdata <= X"00"; -- \
when 16#c5c# => romdata <= X"00"; -- \
when 16#05d# => romdata <= X"00"; -- ]
when 16#15d# => romdata <= X"00"; -- ]
when 16#25d# => romdata <= X"78"; -- ]
when 16#35d# => romdata <= X"08"; -- ]
when 16#45d# => romdata <= X"08"; -- ]
when 16#55d# => romdata <= X"08"; -- ]
when 16#65d# => romdata <= X"08"; -- ]
when 16#75d# => romdata <= X"08"; -- ]
when 16#85d# => romdata <= X"08"; -- ]
when 16#95d# => romdata <= X"08"; -- ]
when 16#a5d# => romdata <= X"78"; -- ]
when 16#b5d# => romdata <= X"00"; -- ]
when 16#c5d# => romdata <= X"00"; -- ]
when 16#05e# => romdata <= X"00"; -- ^
when 16#15e# => romdata <= X"00"; -- ^
when 16#25e# => romdata <= X"10"; -- ^
when 16#35e# => romdata <= X"28"; -- ^
when 16#45e# => romdata <= X"44"; -- ^
when 16#55e# => romdata <= X"00"; -- ^
when 16#65e# => romdata <= X"00"; -- ^
when 16#75e# => romdata <= X"00"; -- ^
when 16#85e# => romdata <= X"00"; -- ^
when 16#95e# => romdata <= X"00"; -- ^
when 16#a5e# => romdata <= X"00"; -- ^
when 16#b5e# => romdata <= X"00"; -- ^
when 16#c5e# => romdata <= X"00"; -- ^
when 16#05f# => romdata <= X"00"; -- _
when 16#15f# => romdata <= X"00"; -- _
when 16#25f# => romdata <= X"00"; -- _
when 16#35f# => romdata <= X"00"; -- _
when 16#45f# => romdata <= X"00"; -- _
when 16#55f# => romdata <= X"00"; -- _
when 16#65f# => romdata <= X"00"; -- _
when 16#75f# => romdata <= X"00"; -- _
when 16#85f# => romdata <= X"00"; -- _
when 16#95f# => romdata <= X"00"; -- _
when 16#a5f# => romdata <= X"00"; -- _
when 16#b5f# => romdata <= X"fe"; -- _
when 16#c5f# => romdata <= X"00"; -- _
when 16#060# => romdata <= X"00"; -- `
when 16#160# => romdata <= X"10"; -- `
when 16#260# => romdata <= X"08"; -- `
when 16#360# => romdata <= X"00"; -- `
when 16#460# => romdata <= X"00"; -- `
when 16#560# => romdata <= X"00"; -- `
when 16#660# => romdata <= X"00"; -- `
when 16#760# => romdata <= X"00"; -- `
when 16#860# => romdata <= X"00"; -- `
when 16#960# => romdata <= X"00"; -- `
when 16#a60# => romdata <= X"00"; -- `
when 16#b60# => romdata <= X"00"; -- `
when 16#c60# => romdata <= X"00"; -- `
when 16#061# => romdata <= X"00"; -- a
when 16#161# => romdata <= X"00"; -- a
when 16#261# => romdata <= X"00"; -- a
when 16#361# => romdata <= X"00"; -- a
when 16#461# => romdata <= X"00"; -- a
when 16#561# => romdata <= X"3c"; -- a
when 16#661# => romdata <= X"02"; -- a
when 16#761# => romdata <= X"3e"; -- a
when 16#861# => romdata <= X"42"; -- a
when 16#961# => romdata <= X"46"; -- a
when 16#a61# => romdata <= X"3a"; -- a
when 16#b61# => romdata <= X"00"; -- a
when 16#c61# => romdata <= X"00"; -- a
when 16#062# => romdata <= X"00"; -- b
when 16#162# => romdata <= X"00"; -- b
when 16#262# => romdata <= X"40"; -- b
when 16#362# => romdata <= X"40"; -- b
when 16#462# => romdata <= X"40"; -- b
when 16#562# => romdata <= X"5c"; -- b
when 16#662# => romdata <= X"62"; -- b
when 16#762# => romdata <= X"42"; -- b
when 16#862# => romdata <= X"42"; -- b
when 16#962# => romdata <= X"62"; -- b
when 16#a62# => romdata <= X"5c"; -- b
when 16#b62# => romdata <= X"00"; -- b
when 16#c62# => romdata <= X"00"; -- b
when 16#063# => romdata <= X"00"; -- c
when 16#163# => romdata <= X"00"; -- c
when 16#263# => romdata <= X"00"; -- c
when 16#363# => romdata <= X"00"; -- c
when 16#463# => romdata <= X"00"; -- c
when 16#563# => romdata <= X"3c"; -- c
when 16#663# => romdata <= X"42"; -- c
when 16#763# => romdata <= X"40"; -- c
when 16#863# => romdata <= X"40"; -- c
when 16#963# => romdata <= X"42"; -- c
when 16#a63# => romdata <= X"3c"; -- c
when 16#b63# => romdata <= X"00"; -- c
when 16#c63# => romdata <= X"00"; -- c
when 16#064# => romdata <= X"00"; -- d
when 16#164# => romdata <= X"00"; -- d
when 16#264# => romdata <= X"02"; -- d
when 16#364# => romdata <= X"02"; -- d
when 16#464# => romdata <= X"02"; -- d
when 16#564# => romdata <= X"3a"; -- d
when 16#664# => romdata <= X"46"; -- d
when 16#764# => romdata <= X"42"; -- d
when 16#864# => romdata <= X"42"; -- d
when 16#964# => romdata <= X"46"; -- d
when 16#a64# => romdata <= X"3a"; -- d
when 16#b64# => romdata <= X"00"; -- d
when 16#c64# => romdata <= X"00"; -- d
when 16#065# => romdata <= X"00"; -- e
when 16#165# => romdata <= X"00"; -- e
when 16#265# => romdata <= X"00"; -- e
when 16#365# => romdata <= X"00"; -- e
when 16#465# => romdata <= X"00"; -- e
when 16#565# => romdata <= X"3c"; -- e
when 16#665# => romdata <= X"42"; -- e
when 16#765# => romdata <= X"7e"; -- e
when 16#865# => romdata <= X"40"; -- e
when 16#965# => romdata <= X"42"; -- e
when 16#a65# => romdata <= X"3c"; -- e
when 16#b65# => romdata <= X"00"; -- e
when 16#c65# => romdata <= X"00"; -- e
when 16#066# => romdata <= X"00"; -- f
when 16#166# => romdata <= X"00"; -- f
when 16#266# => romdata <= X"1c"; -- f
when 16#366# => romdata <= X"22"; -- f
when 16#466# => romdata <= X"20"; -- f
when 16#566# => romdata <= X"20"; -- f
when 16#666# => romdata <= X"7c"; -- f
when 16#766# => romdata <= X"20"; -- f
when 16#866# => romdata <= X"20"; -- f
when 16#966# => romdata <= X"20"; -- f
when 16#a66# => romdata <= X"20"; -- f
when 16#b66# => romdata <= X"00"; -- f
when 16#c66# => romdata <= X"00"; -- f
when 16#067# => romdata <= X"00"; -- g
when 16#167# => romdata <= X"00"; -- g
when 16#267# => romdata <= X"00"; -- g
when 16#367# => romdata <= X"00"; -- g
when 16#467# => romdata <= X"00"; -- g
when 16#567# => romdata <= X"3a"; -- g
when 16#667# => romdata <= X"44"; -- g
when 16#767# => romdata <= X"44"; -- g
when 16#867# => romdata <= X"38"; -- g
when 16#967# => romdata <= X"40"; -- g
when 16#a67# => romdata <= X"3c"; -- g
when 16#b67# => romdata <= X"42"; -- g
when 16#c67# => romdata <= X"3c"; -- g
when 16#068# => romdata <= X"00"; -- h
when 16#168# => romdata <= X"00"; -- h
when 16#268# => romdata <= X"40"; -- h
when 16#368# => romdata <= X"40"; -- h
when 16#468# => romdata <= X"40"; -- h
when 16#568# => romdata <= X"5c"; -- h
when 16#668# => romdata <= X"62"; -- h
when 16#768# => romdata <= X"42"; -- h
when 16#868# => romdata <= X"42"; -- h
when 16#968# => romdata <= X"42"; -- h
when 16#a68# => romdata <= X"42"; -- h
when 16#b68# => romdata <= X"00"; -- h
when 16#c68# => romdata <= X"00"; -- h
when 16#069# => romdata <= X"00"; -- i
when 16#169# => romdata <= X"00"; -- i
when 16#269# => romdata <= X"00"; -- i
when 16#369# => romdata <= X"10"; -- i
when 16#469# => romdata <= X"00"; -- i
when 16#569# => romdata <= X"30"; -- i
when 16#669# => romdata <= X"10"; -- i
when 16#769# => romdata <= X"10"; -- i
when 16#869# => romdata <= X"10"; -- i
when 16#969# => romdata <= X"10"; -- i
when 16#a69# => romdata <= X"7c"; -- i
when 16#b69# => romdata <= X"00"; -- i
when 16#c69# => romdata <= X"00"; -- i
when 16#06a# => romdata <= X"00"; -- j
when 16#16a# => romdata <= X"00"; -- j
when 16#26a# => romdata <= X"00"; -- j
when 16#36a# => romdata <= X"04"; -- j
when 16#46a# => romdata <= X"00"; -- j
when 16#56a# => romdata <= X"0c"; -- j
when 16#66a# => romdata <= X"04"; -- j
when 16#76a# => romdata <= X"04"; -- j
when 16#86a# => romdata <= X"04"; -- j
when 16#96a# => romdata <= X"04"; -- j
when 16#a6a# => romdata <= X"44"; -- j
when 16#b6a# => romdata <= X"44"; -- j
when 16#c6a# => romdata <= X"38"; -- j
when 16#06b# => romdata <= X"00"; -- k
when 16#16b# => romdata <= X"00"; -- k
when 16#26b# => romdata <= X"40"; -- k
when 16#36b# => romdata <= X"40"; -- k
when 16#46b# => romdata <= X"40"; -- k
when 16#56b# => romdata <= X"44"; -- k
when 16#66b# => romdata <= X"48"; -- k
when 16#76b# => romdata <= X"70"; -- k
when 16#86b# => romdata <= X"48"; -- k
when 16#96b# => romdata <= X"44"; -- k
when 16#a6b# => romdata <= X"42"; -- k
when 16#b6b# => romdata <= X"00"; -- k
when 16#c6b# => romdata <= X"00"; -- k
when 16#06c# => romdata <= X"00"; -- l
when 16#16c# => romdata <= X"00"; -- l
when 16#26c# => romdata <= X"30"; -- l
when 16#36c# => romdata <= X"10"; -- l
when 16#46c# => romdata <= X"10"; -- l
when 16#56c# => romdata <= X"10"; -- l
when 16#66c# => romdata <= X"10"; -- l
when 16#76c# => romdata <= X"10"; -- l
when 16#86c# => romdata <= X"10"; -- l
when 16#96c# => romdata <= X"10"; -- l
when 16#a6c# => romdata <= X"7c"; -- l
when 16#b6c# => romdata <= X"00"; -- l
when 16#c6c# => romdata <= X"00"; -- l
when 16#06d# => romdata <= X"00"; -- m
when 16#16d# => romdata <= X"00"; -- m
when 16#26d# => romdata <= X"00"; -- m
when 16#36d# => romdata <= X"00"; -- m
when 16#46d# => romdata <= X"00"; -- m
when 16#56d# => romdata <= X"ec"; -- m
when 16#66d# => romdata <= X"92"; -- m
when 16#76d# => romdata <= X"92"; -- m
when 16#86d# => romdata <= X"92"; -- m
when 16#96d# => romdata <= X"92"; -- m
when 16#a6d# => romdata <= X"82"; -- m
when 16#b6d# => romdata <= X"00"; -- m
when 16#c6d# => romdata <= X"00"; -- m
when 16#06e# => romdata <= X"00"; -- n
when 16#16e# => romdata <= X"00"; -- n
when 16#26e# => romdata <= X"00"; -- n
when 16#36e# => romdata <= X"00"; -- n
when 16#46e# => romdata <= X"00"; -- n
when 16#56e# => romdata <= X"5c"; -- n
when 16#66e# => romdata <= X"62"; -- n
when 16#76e# => romdata <= X"42"; -- n
when 16#86e# => romdata <= X"42"; -- n
when 16#96e# => romdata <= X"42"; -- n
when 16#a6e# => romdata <= X"42"; -- n
when 16#b6e# => romdata <= X"00"; -- n
when 16#c6e# => romdata <= X"00"; -- n
when 16#06f# => romdata <= X"00"; -- o
when 16#16f# => romdata <= X"00"; -- o
when 16#26f# => romdata <= X"00"; -- o
when 16#36f# => romdata <= X"00"; -- o
when 16#46f# => romdata <= X"00"; -- o
when 16#56f# => romdata <= X"3c"; -- o
when 16#66f# => romdata <= X"42"; -- o
when 16#76f# => romdata <= X"42"; -- o
when 16#86f# => romdata <= X"42"; -- o
when 16#96f# => romdata <= X"42"; -- o
when 16#a6f# => romdata <= X"3c"; -- o
when 16#b6f# => romdata <= X"00"; -- o
when 16#c6f# => romdata <= X"00"; -- o
when 16#070# => romdata <= X"00"; -- p
when 16#170# => romdata <= X"00"; -- p
when 16#270# => romdata <= X"00"; -- p
when 16#370# => romdata <= X"00"; -- p
when 16#470# => romdata <= X"00"; -- p
when 16#570# => romdata <= X"5c"; -- p
when 16#670# => romdata <= X"62"; -- p
when 16#770# => romdata <= X"42"; -- p
when 16#870# => romdata <= X"62"; -- p
when 16#970# => romdata <= X"5c"; -- p
when 16#a70# => romdata <= X"40"; -- p
when 16#b70# => romdata <= X"40"; -- p
when 16#c70# => romdata <= X"40"; -- p
when 16#071# => romdata <= X"00"; -- q
when 16#171# => romdata <= X"00"; -- q
when 16#271# => romdata <= X"00"; -- q
when 16#371# => romdata <= X"00"; -- q
when 16#471# => romdata <= X"00"; -- q
when 16#571# => romdata <= X"3a"; -- q
when 16#671# => romdata <= X"46"; -- q
when 16#771# => romdata <= X"42"; -- q
when 16#871# => romdata <= X"46"; -- q
when 16#971# => romdata <= X"3a"; -- q
when 16#a71# => romdata <= X"02"; -- q
when 16#b71# => romdata <= X"02"; -- q
when 16#c71# => romdata <= X"02"; -- q
when 16#072# => romdata <= X"00"; -- r
when 16#172# => romdata <= X"00"; -- r
when 16#272# => romdata <= X"00"; -- r
when 16#372# => romdata <= X"00"; -- r
when 16#472# => romdata <= X"00"; -- r
when 16#572# => romdata <= X"5c"; -- r
when 16#672# => romdata <= X"22"; -- r
when 16#772# => romdata <= X"20"; -- r
when 16#872# => romdata <= X"20"; -- r
when 16#972# => romdata <= X"20"; -- r
when 16#a72# => romdata <= X"20"; -- r
when 16#b72# => romdata <= X"00"; -- r
when 16#c72# => romdata <= X"00"; -- r
when 16#073# => romdata <= X"00"; -- s
when 16#173# => romdata <= X"00"; -- s
when 16#273# => romdata <= X"00"; -- s
when 16#373# => romdata <= X"00"; -- s
when 16#473# => romdata <= X"00"; -- s
when 16#573# => romdata <= X"3c"; -- s
when 16#673# => romdata <= X"42"; -- s
when 16#773# => romdata <= X"30"; -- s
when 16#873# => romdata <= X"0c"; -- s
when 16#973# => romdata <= X"42"; -- s
when 16#a73# => romdata <= X"3c"; -- s
when 16#b73# => romdata <= X"00"; -- s
when 16#c73# => romdata <= X"00"; -- s
when 16#074# => romdata <= X"00"; -- t
when 16#174# => romdata <= X"00"; -- t
when 16#274# => romdata <= X"00"; -- t
when 16#374# => romdata <= X"20"; -- t
when 16#474# => romdata <= X"20"; -- t
when 16#574# => romdata <= X"7c"; -- t
when 16#674# => romdata <= X"20"; -- t
when 16#774# => romdata <= X"20"; -- t
when 16#874# => romdata <= X"20"; -- t
when 16#974# => romdata <= X"22"; -- t
when 16#a74# => romdata <= X"1c"; -- t
when 16#b74# => romdata <= X"00"; -- t
when 16#c74# => romdata <= X"00"; -- t
when 16#075# => romdata <= X"00"; -- u
when 16#175# => romdata <= X"00"; -- u
when 16#275# => romdata <= X"00"; -- u
when 16#375# => romdata <= X"00"; -- u
when 16#475# => romdata <= X"00"; -- u
when 16#575# => romdata <= X"44"; -- u
when 16#675# => romdata <= X"44"; -- u
when 16#775# => romdata <= X"44"; -- u
when 16#875# => romdata <= X"44"; -- u
when 16#975# => romdata <= X"44"; -- u
when 16#a75# => romdata <= X"3a"; -- u
when 16#b75# => romdata <= X"00"; -- u
when 16#c75# => romdata <= X"00"; -- u
when 16#076# => romdata <= X"00"; -- v
when 16#176# => romdata <= X"00"; -- v
when 16#276# => romdata <= X"00"; -- v
when 16#376# => romdata <= X"00"; -- v
when 16#476# => romdata <= X"00"; -- v
when 16#576# => romdata <= X"44"; -- v
when 16#676# => romdata <= X"44"; -- v
when 16#776# => romdata <= X"44"; -- v
when 16#876# => romdata <= X"28"; -- v
when 16#976# => romdata <= X"28"; -- v
when 16#a76# => romdata <= X"10"; -- v
when 16#b76# => romdata <= X"00"; -- v
when 16#c76# => romdata <= X"00"; -- v
when 16#077# => romdata <= X"00"; -- w
when 16#177# => romdata <= X"00"; -- w
when 16#277# => romdata <= X"00"; -- w
when 16#377# => romdata <= X"00"; -- w
when 16#477# => romdata <= X"00"; -- w
when 16#577# => romdata <= X"82"; -- w
when 16#677# => romdata <= X"82"; -- w
when 16#777# => romdata <= X"92"; -- w
when 16#877# => romdata <= X"92"; -- w
when 16#977# => romdata <= X"aa"; -- w
when 16#a77# => romdata <= X"44"; -- w
when 16#b77# => romdata <= X"00"; -- w
when 16#c77# => romdata <= X"00"; -- w
when 16#078# => romdata <= X"00"; -- x
when 16#178# => romdata <= X"00"; -- x
when 16#278# => romdata <= X"00"; -- x
when 16#378# => romdata <= X"00"; -- x
when 16#478# => romdata <= X"00"; -- x
when 16#578# => romdata <= X"42"; -- x
when 16#678# => romdata <= X"24"; -- x
when 16#778# => romdata <= X"18"; -- x
when 16#878# => romdata <= X"18"; -- x
when 16#978# => romdata <= X"24"; -- x
when 16#a78# => romdata <= X"42"; -- x
when 16#b78# => romdata <= X"00"; -- x
when 16#c78# => romdata <= X"00"; -- x
when 16#079# => romdata <= X"00"; -- y
when 16#179# => romdata <= X"00"; -- y
when 16#279# => romdata <= X"00"; -- y
when 16#379# => romdata <= X"00"; -- y
when 16#479# => romdata <= X"00"; -- y
when 16#579# => romdata <= X"42"; -- y
when 16#679# => romdata <= X"42"; -- y
when 16#779# => romdata <= X"42"; -- y
when 16#879# => romdata <= X"46"; -- y
when 16#979# => romdata <= X"3a"; -- y
when 16#a79# => romdata <= X"02"; -- y
when 16#b79# => romdata <= X"42"; -- y
when 16#c79# => romdata <= X"3c"; -- y
when 16#07a# => romdata <= X"00"; -- z
when 16#17a# => romdata <= X"00"; -- z
when 16#27a# => romdata <= X"00"; -- z
when 16#37a# => romdata <= X"00"; -- z
when 16#47a# => romdata <= X"00"; -- z
when 16#57a# => romdata <= X"7e"; -- z
when 16#67a# => romdata <= X"04"; -- z
when 16#77a# => romdata <= X"08"; -- z
when 16#87a# => romdata <= X"10"; -- z
when 16#97a# => romdata <= X"20"; -- z
when 16#a7a# => romdata <= X"7e"; -- z
when 16#b7a# => romdata <= X"00"; -- z
when 16#c7a# => romdata <= X"00"; -- z
when 16#07b# => romdata <= X"00"; -- {
when 16#17b# => romdata <= X"00"; -- {
when 16#27b# => romdata <= X"0e"; -- {
when 16#37b# => romdata <= X"10"; -- {
when 16#47b# => romdata <= X"10"; -- {
when 16#57b# => romdata <= X"08"; -- {
when 16#67b# => romdata <= X"30"; -- {
when 16#77b# => romdata <= X"08"; -- {
when 16#87b# => romdata <= X"10"; -- {
when 16#97b# => romdata <= X"10"; -- {
when 16#a7b# => romdata <= X"0e"; -- {
when 16#b7b# => romdata <= X"00"; -- {
when 16#c7b# => romdata <= X"00"; -- {
when 16#07c# => romdata <= X"00"; -- |
when 16#17c# => romdata <= X"00"; -- |
when 16#27c# => romdata <= X"10"; -- |
when 16#37c# => romdata <= X"10"; -- |
when 16#47c# => romdata <= X"10"; -- |
when 16#57c# => romdata <= X"10"; -- |
when 16#67c# => romdata <= X"10"; -- |
when 16#77c# => romdata <= X"10"; -- |
when 16#87c# => romdata <= X"10"; -- |
when 16#97c# => romdata <= X"10"; -- |
when 16#a7c# => romdata <= X"10"; -- |
when 16#b7c# => romdata <= X"00"; -- |
when 16#c7c# => romdata <= X"00"; -- |
when 16#07d# => romdata <= X"00"; -- }
when 16#17d# => romdata <= X"00"; -- }
when 16#27d# => romdata <= X"70"; -- }
when 16#37d# => romdata <= X"08"; -- }
when 16#47d# => romdata <= X"08"; -- }
when 16#57d# => romdata <= X"10"; -- }
when 16#67d# => romdata <= X"0c"; -- }
when 16#77d# => romdata <= X"10"; -- }
when 16#87d# => romdata <= X"08"; -- }
when 16#97d# => romdata <= X"08"; -- }
when 16#a7d# => romdata <= X"70"; -- }
when 16#b7d# => romdata <= X"00"; -- }
when 16#c7d# => romdata <= X"00"; -- }
when 16#07e# => romdata <= X"00"; -- ~
when 16#17e# => romdata <= X"00"; -- ~
when 16#27e# => romdata <= X"24"; -- ~
when 16#37e# => romdata <= X"54"; -- ~
when 16#47e# => romdata <= X"48"; -- ~
when 16#57e# => romdata <= X"00"; -- ~
when 16#67e# => romdata <= X"00"; -- ~
when 16#77e# => romdata <= X"00"; -- ~
when 16#87e# => romdata <= X"00"; -- ~
when 16#97e# => romdata <= X"00"; -- ~
when 16#a7e# => romdata <= X"00"; -- ~
when 16#b7e# => romdata <= X"00"; -- ~
when 16#c7e# => romdata <= X"00"; -- ~
when 16#0a0# => romdata <= X"00"; --
when 16#1a0# => romdata <= X"00"; --
when 16#2a0# => romdata <= X"00"; --
when 16#3a0# => romdata <= X"00"; --
when 16#4a0# => romdata <= X"00"; --
when 16#5a0# => romdata <= X"00"; --
when 16#6a0# => romdata <= X"00"; --
when 16#7a0# => romdata <= X"00"; --
when 16#8a0# => romdata <= X"00"; --
when 16#9a0# => romdata <= X"00"; --
when 16#aa0# => romdata <= X"00"; --
when 16#ba0# => romdata <= X"00"; --
when 16#ca0# => romdata <= X"00"; --
when 16#0a1# => romdata <= X"00"; -- ¡
when 16#1a1# => romdata <= X"00"; -- ¡
when 16#2a1# => romdata <= X"10"; -- ¡
when 16#3a1# => romdata <= X"00"; -- ¡
when 16#4a1# => romdata <= X"10"; -- ¡
when 16#5a1# => romdata <= X"10"; -- ¡
when 16#6a1# => romdata <= X"10"; -- ¡
when 16#7a1# => romdata <= X"10"; -- ¡
when 16#8a1# => romdata <= X"10"; -- ¡
when 16#9a1# => romdata <= X"10"; -- ¡
when 16#aa1# => romdata <= X"10"; -- ¡
when 16#ba1# => romdata <= X"00"; -- ¡
when 16#ca1# => romdata <= X"00"; -- ¡
when 16#0a2# => romdata <= X"00"; -- ¢
when 16#1a2# => romdata <= X"00"; -- ¢
when 16#2a2# => romdata <= X"10"; -- ¢
when 16#3a2# => romdata <= X"38"; -- ¢
when 16#4a2# => romdata <= X"54"; -- ¢
when 16#5a2# => romdata <= X"50"; -- ¢
when 16#6a2# => romdata <= X"50"; -- ¢
when 16#7a2# => romdata <= X"54"; -- ¢
when 16#8a2# => romdata <= X"38"; -- ¢
when 16#9a2# => romdata <= X"10"; -- ¢
when 16#aa2# => romdata <= X"00"; -- ¢
when 16#ba2# => romdata <= X"00"; -- ¢
when 16#ca2# => romdata <= X"00"; -- ¢
when 16#0a3# => romdata <= X"00"; -- £
when 16#1a3# => romdata <= X"00"; -- £
when 16#2a3# => romdata <= X"1c"; -- £
when 16#3a3# => romdata <= X"22"; -- £
when 16#4a3# => romdata <= X"20"; -- £
when 16#5a3# => romdata <= X"70"; -- £
when 16#6a3# => romdata <= X"20"; -- £
when 16#7a3# => romdata <= X"20"; -- £
when 16#8a3# => romdata <= X"20"; -- £
when 16#9a3# => romdata <= X"62"; -- £
when 16#aa3# => romdata <= X"dc"; -- £
when 16#ba3# => romdata <= X"00"; -- £
when 16#ca3# => romdata <= X"00"; -- £
when 16#0a4# => romdata <= X"00"; -- ¤
when 16#1a4# => romdata <= X"00"; -- ¤
when 16#2a4# => romdata <= X"00"; -- ¤
when 16#3a4# => romdata <= X"00"; -- ¤
when 16#4a4# => romdata <= X"42"; -- ¤
when 16#5a4# => romdata <= X"3c"; -- ¤
when 16#6a4# => romdata <= X"24"; -- ¤
when 16#7a4# => romdata <= X"24"; -- ¤
when 16#8a4# => romdata <= X"3c"; -- ¤
when 16#9a4# => romdata <= X"42"; -- ¤
when 16#aa4# => romdata <= X"00"; -- ¤
when 16#ba4# => romdata <= X"00"; -- ¤
when 16#ca4# => romdata <= X"00"; -- ¤
when 16#0a5# => romdata <= X"00"; -- ¥
when 16#1a5# => romdata <= X"00"; -- ¥
when 16#2a5# => romdata <= X"82"; -- ¥
when 16#3a5# => romdata <= X"82"; -- ¥
when 16#4a5# => romdata <= X"44"; -- ¥
when 16#5a5# => romdata <= X"28"; -- ¥
when 16#6a5# => romdata <= X"7c"; -- ¥
when 16#7a5# => romdata <= X"10"; -- ¥
when 16#8a5# => romdata <= X"7c"; -- ¥
when 16#9a5# => romdata <= X"10"; -- ¥
when 16#aa5# => romdata <= X"10"; -- ¥
when 16#ba5# => romdata <= X"00"; -- ¥
when 16#ca5# => romdata <= X"00"; -- ¥
when 16#0a6# => romdata <= X"00"; -- ¦
when 16#1a6# => romdata <= X"00"; -- ¦
when 16#2a6# => romdata <= X"10"; -- ¦
when 16#3a6# => romdata <= X"10"; -- ¦
when 16#4a6# => romdata <= X"10"; -- ¦
when 16#5a6# => romdata <= X"10"; -- ¦
when 16#6a6# => romdata <= X"00"; -- ¦
when 16#7a6# => romdata <= X"10"; -- ¦
when 16#8a6# => romdata <= X"10"; -- ¦
when 16#9a6# => romdata <= X"10"; -- ¦
when 16#aa6# => romdata <= X"10"; -- ¦
when 16#ba6# => romdata <= X"00"; -- ¦
when 16#ca6# => romdata <= X"00"; -- ¦
when 16#0a7# => romdata <= X"00"; -- §
when 16#1a7# => romdata <= X"18"; -- §
when 16#2a7# => romdata <= X"24"; -- §
when 16#3a7# => romdata <= X"20"; -- §
when 16#4a7# => romdata <= X"18"; -- §
when 16#5a7# => romdata <= X"24"; -- §
when 16#6a7# => romdata <= X"24"; -- §
when 16#7a7# => romdata <= X"18"; -- §
when 16#8a7# => romdata <= X"04"; -- §
when 16#9a7# => romdata <= X"24"; -- §
when 16#aa7# => romdata <= X"18"; -- §
when 16#ba7# => romdata <= X"00"; -- §
when 16#ca7# => romdata <= X"00"; -- §
when 16#0a8# => romdata <= X"00"; -- ¨
when 16#1a8# => romdata <= X"24"; -- ¨
when 16#2a8# => romdata <= X"24"; -- ¨
when 16#3a8# => romdata <= X"00"; -- ¨
when 16#4a8# => romdata <= X"00"; -- ¨
when 16#5a8# => romdata <= X"00"; -- ¨
when 16#6a8# => romdata <= X"00"; -- ¨
when 16#7a8# => romdata <= X"00"; -- ¨
when 16#8a8# => romdata <= X"00"; -- ¨
when 16#9a8# => romdata <= X"00"; -- ¨
when 16#aa8# => romdata <= X"00"; -- ¨
when 16#ba8# => romdata <= X"00"; -- ¨
when 16#ca8# => romdata <= X"00"; -- ¨
when 16#0a9# => romdata <= X"00"; -- ©
when 16#1a9# => romdata <= X"38"; -- ©
when 16#2a9# => romdata <= X"44"; -- ©
when 16#3a9# => romdata <= X"92"; -- ©
when 16#4a9# => romdata <= X"aa"; -- ©
when 16#5a9# => romdata <= X"a2"; -- ©
when 16#6a9# => romdata <= X"aa"; -- ©
when 16#7a9# => romdata <= X"92"; -- ©
when 16#8a9# => romdata <= X"44"; -- ©
when 16#9a9# => romdata <= X"38"; -- ©
when 16#aa9# => romdata <= X"00"; -- ©
when 16#ba9# => romdata <= X"00"; -- ©
when 16#ca9# => romdata <= X"00"; -- ©
when 16#0aa# => romdata <= X"00"; -- ª
when 16#1aa# => romdata <= X"00"; -- ª
when 16#2aa# => romdata <= X"38"; -- ª
when 16#3aa# => romdata <= X"04"; -- ª
when 16#4aa# => romdata <= X"3c"; -- ª
when 16#5aa# => romdata <= X"44"; -- ª
when 16#6aa# => romdata <= X"3c"; -- ª
when 16#7aa# => romdata <= X"00"; -- ª
when 16#8aa# => romdata <= X"7c"; -- ª
when 16#9aa# => romdata <= X"00"; -- ª
when 16#aaa# => romdata <= X"00"; -- ª
when 16#baa# => romdata <= X"00"; -- ª
when 16#caa# => romdata <= X"00"; -- ª
when 16#0ab# => romdata <= X"00"; -- «
when 16#1ab# => romdata <= X"00"; -- «
when 16#2ab# => romdata <= X"00"; -- «
when 16#3ab# => romdata <= X"12"; -- «
when 16#4ab# => romdata <= X"24"; -- «
when 16#5ab# => romdata <= X"48"; -- «
when 16#6ab# => romdata <= X"90"; -- «
when 16#7ab# => romdata <= X"48"; -- «
when 16#8ab# => romdata <= X"24"; -- «
when 16#9ab# => romdata <= X"12"; -- «
when 16#aab# => romdata <= X"00"; -- «
when 16#bab# => romdata <= X"00"; -- «
when 16#cab# => romdata <= X"00"; -- «
when 16#0ac# => romdata <= X"00"; -- ¬
when 16#1ac# => romdata <= X"00"; -- ¬
when 16#2ac# => romdata <= X"00"; -- ¬
when 16#3ac# => romdata <= X"00"; -- ¬
when 16#4ac# => romdata <= X"00"; -- ¬
when 16#5ac# => romdata <= X"00"; -- ¬
when 16#6ac# => romdata <= X"7e"; -- ¬
when 16#7ac# => romdata <= X"02"; -- ¬
when 16#8ac# => romdata <= X"02"; -- ¬
when 16#9ac# => romdata <= X"02"; -- ¬
when 16#aac# => romdata <= X"00"; -- ¬
when 16#bac# => romdata <= X"00"; -- ¬
when 16#cac# => romdata <= X"00"; -- ¬
when 16#0ad# => romdata <= X"00"; --
when 16#1ad# => romdata <= X"00"; --
when 16#2ad# => romdata <= X"00"; --
when 16#3ad# => romdata <= X"00"; --
when 16#4ad# => romdata <= X"00"; --
when 16#5ad# => romdata <= X"00"; --
when 16#6ad# => romdata <= X"3c"; --
when 16#7ad# => romdata <= X"00"; --
when 16#8ad# => romdata <= X"00"; --
when 16#9ad# => romdata <= X"00"; --
when 16#aad# => romdata <= X"00"; --
when 16#bad# => romdata <= X"00"; --
when 16#cad# => romdata <= X"00"; --
when 16#0ae# => romdata <= X"00"; -- ®
when 16#1ae# => romdata <= X"38"; -- ®
when 16#2ae# => romdata <= X"44"; -- ®
when 16#3ae# => romdata <= X"92"; -- ®
when 16#4ae# => romdata <= X"aa"; -- ®
when 16#5ae# => romdata <= X"aa"; -- ®
when 16#6ae# => romdata <= X"b2"; -- ®
when 16#7ae# => romdata <= X"aa"; -- ®
when 16#8ae# => romdata <= X"44"; -- ®
when 16#9ae# => romdata <= X"38"; -- ®
when 16#aae# => romdata <= X"00"; -- ®
when 16#bae# => romdata <= X"00"; -- ®
when 16#cae# => romdata <= X"00"; -- ®
when 16#0af# => romdata <= X"00"; -- ¯
when 16#1af# => romdata <= X"00"; -- ¯
when 16#2af# => romdata <= X"7e"; -- ¯
when 16#3af# => romdata <= X"00"; -- ¯
when 16#4af# => romdata <= X"00"; -- ¯
when 16#5af# => romdata <= X"00"; -- ¯
when 16#6af# => romdata <= X"00"; -- ¯
when 16#7af# => romdata <= X"00"; -- ¯
when 16#8af# => romdata <= X"00"; -- ¯
when 16#9af# => romdata <= X"00"; -- ¯
when 16#aaf# => romdata <= X"00"; -- ¯
when 16#baf# => romdata <= X"00"; -- ¯
when 16#caf# => romdata <= X"00"; -- ¯
when 16#0b0# => romdata <= X"00"; -- °
when 16#1b0# => romdata <= X"00"; -- °
when 16#2b0# => romdata <= X"18"; -- °
when 16#3b0# => romdata <= X"24"; -- °
when 16#4b0# => romdata <= X"24"; -- °
when 16#5b0# => romdata <= X"18"; -- °
when 16#6b0# => romdata <= X"00"; -- °
when 16#7b0# => romdata <= X"00"; -- °
when 16#8b0# => romdata <= X"00"; -- °
when 16#9b0# => romdata <= X"00"; -- °
when 16#ab0# => romdata <= X"00"; -- °
when 16#bb0# => romdata <= X"00"; -- °
when 16#cb0# => romdata <= X"00"; -- °
when 16#0b1# => romdata <= X"00"; -- ±
when 16#1b1# => romdata <= X"00"; -- ±
when 16#2b1# => romdata <= X"00"; -- ±
when 16#3b1# => romdata <= X"10"; -- ±
when 16#4b1# => romdata <= X"10"; -- ±
when 16#5b1# => romdata <= X"7c"; -- ±
when 16#6b1# => romdata <= X"10"; -- ±
when 16#7b1# => romdata <= X"10"; -- ±
when 16#8b1# => romdata <= X"00"; -- ±
when 16#9b1# => romdata <= X"7c"; -- ±
when 16#ab1# => romdata <= X"00"; -- ±
when 16#bb1# => romdata <= X"00"; -- ±
when 16#cb1# => romdata <= X"00"; -- ±
when 16#0b2# => romdata <= X"00"; -- ²
when 16#1b2# => romdata <= X"30"; -- ²
when 16#2b2# => romdata <= X"48"; -- ²
when 16#3b2# => romdata <= X"08"; -- ²
when 16#4b2# => romdata <= X"30"; -- ²
when 16#5b2# => romdata <= X"40"; -- ²
when 16#6b2# => romdata <= X"78"; -- ²
when 16#7b2# => romdata <= X"00"; -- ²
when 16#8b2# => romdata <= X"00"; -- ²
when 16#9b2# => romdata <= X"00"; -- ²
when 16#ab2# => romdata <= X"00"; -- ²
when 16#bb2# => romdata <= X"00"; -- ²
when 16#cb2# => romdata <= X"00"; -- ²
when 16#0b3# => romdata <= X"00"; -- ³
when 16#1b3# => romdata <= X"30"; -- ³
when 16#2b3# => romdata <= X"48"; -- ³
when 16#3b3# => romdata <= X"10"; -- ³
when 16#4b3# => romdata <= X"08"; -- ³
when 16#5b3# => romdata <= X"48"; -- ³
when 16#6b3# => romdata <= X"30"; -- ³
when 16#7b3# => romdata <= X"00"; -- ³
when 16#8b3# => romdata <= X"00"; -- ³
when 16#9b3# => romdata <= X"00"; -- ³
when 16#ab3# => romdata <= X"00"; -- ³
when 16#bb3# => romdata <= X"00"; -- ³
when 16#cb3# => romdata <= X"00"; -- ³
when 16#0b4# => romdata <= X"00"; -- ´
when 16#1b4# => romdata <= X"08"; -- ´
when 16#2b4# => romdata <= X"10"; -- ´
when 16#3b4# => romdata <= X"00"; -- ´
when 16#4b4# => romdata <= X"00"; -- ´
when 16#5b4# => romdata <= X"00"; -- ´
when 16#6b4# => romdata <= X"00"; -- ´
when 16#7b4# => romdata <= X"00"; -- ´
when 16#8b4# => romdata <= X"00"; -- ´
when 16#9b4# => romdata <= X"00"; -- ´
when 16#ab4# => romdata <= X"00"; -- ´
when 16#bb4# => romdata <= X"00"; -- ´
when 16#cb4# => romdata <= X"00"; -- ´
when 16#0b5# => romdata <= X"00"; -- µ
when 16#1b5# => romdata <= X"00"; -- µ
when 16#2b5# => romdata <= X"00"; -- µ
when 16#3b5# => romdata <= X"00"; -- µ
when 16#4b5# => romdata <= X"00"; -- µ
when 16#5b5# => romdata <= X"42"; -- µ
when 16#6b5# => romdata <= X"42"; -- µ
when 16#7b5# => romdata <= X"42"; -- µ
when 16#8b5# => romdata <= X"42"; -- µ
when 16#9b5# => romdata <= X"66"; -- µ
when 16#ab5# => romdata <= X"5a"; -- µ
when 16#bb5# => romdata <= X"40"; -- µ
when 16#cb5# => romdata <= X"00"; -- µ
when 16#0b6# => romdata <= X"00"; -- ¶
when 16#1b6# => romdata <= X"00"; -- ¶
when 16#2b6# => romdata <= X"3e"; -- ¶
when 16#3b6# => romdata <= X"74"; -- ¶
when 16#4b6# => romdata <= X"74"; -- ¶
when 16#5b6# => romdata <= X"74"; -- ¶
when 16#6b6# => romdata <= X"34"; -- ¶
when 16#7b6# => romdata <= X"14"; -- ¶
when 16#8b6# => romdata <= X"14"; -- ¶
when 16#9b6# => romdata <= X"14"; -- ¶
when 16#ab6# => romdata <= X"14"; -- ¶
when 16#bb6# => romdata <= X"00"; -- ¶
when 16#cb6# => romdata <= X"00"; -- ¶
when 16#0b7# => romdata <= X"00"; -- ·
when 16#1b7# => romdata <= X"00"; -- ·
when 16#2b7# => romdata <= X"00"; -- ·
when 16#3b7# => romdata <= X"00"; -- ·
when 16#4b7# => romdata <= X"00"; -- ·
when 16#5b7# => romdata <= X"00"; -- ·
when 16#6b7# => romdata <= X"18"; -- ·
when 16#7b7# => romdata <= X"00"; -- ·
when 16#8b7# => romdata <= X"00"; -- ·
when 16#9b7# => romdata <= X"00"; -- ·
when 16#ab7# => romdata <= X"00"; -- ·
when 16#bb7# => romdata <= X"00"; -- ·
when 16#cb7# => romdata <= X"00"; -- ·
when 16#0b8# => romdata <= X"00"; -- ¸
when 16#1b8# => romdata <= X"00"; -- ¸
when 16#2b8# => romdata <= X"00"; -- ¸
when 16#3b8# => romdata <= X"00"; -- ¸
when 16#4b8# => romdata <= X"00"; -- ¸
when 16#5b8# => romdata <= X"00"; -- ¸
when 16#6b8# => romdata <= X"00"; -- ¸
when 16#7b8# => romdata <= X"00"; -- ¸
when 16#8b8# => romdata <= X"00"; -- ¸
when 16#9b8# => romdata <= X"00"; -- ¸
when 16#ab8# => romdata <= X"00"; -- ¸
when 16#bb8# => romdata <= X"08"; -- ¸
when 16#cb8# => romdata <= X"18"; -- ¸
when 16#0b9# => romdata <= X"00"; -- ¹
when 16#1b9# => romdata <= X"20"; -- ¹
when 16#2b9# => romdata <= X"60"; -- ¹
when 16#3b9# => romdata <= X"20"; -- ¹
when 16#4b9# => romdata <= X"20"; -- ¹
when 16#5b9# => romdata <= X"20"; -- ¹
when 16#6b9# => romdata <= X"70"; -- ¹
when 16#7b9# => romdata <= X"00"; -- ¹
when 16#8b9# => romdata <= X"00"; -- ¹
when 16#9b9# => romdata <= X"00"; -- ¹
when 16#ab9# => romdata <= X"00"; -- ¹
when 16#bb9# => romdata <= X"00"; -- ¹
when 16#cb9# => romdata <= X"00"; -- ¹
when 16#0ba# => romdata <= X"00"; -- º
when 16#1ba# => romdata <= X"00"; -- º
when 16#2ba# => romdata <= X"30"; -- º
when 16#3ba# => romdata <= X"48"; -- º
when 16#4ba# => romdata <= X"48"; -- º
when 16#5ba# => romdata <= X"30"; -- º
when 16#6ba# => romdata <= X"00"; -- º
when 16#7ba# => romdata <= X"78"; -- º
when 16#8ba# => romdata <= X"00"; -- º
when 16#9ba# => romdata <= X"00"; -- º
when 16#aba# => romdata <= X"00"; -- º
when 16#bba# => romdata <= X"00"; -- º
when 16#cba# => romdata <= X"00"; -- º
when 16#0bb# => romdata <= X"00"; -- »
when 16#1bb# => romdata <= X"00"; -- »
when 16#2bb# => romdata <= X"00"; -- »
when 16#3bb# => romdata <= X"90"; -- »
when 16#4bb# => romdata <= X"48"; -- »
when 16#5bb# => romdata <= X"24"; -- »
when 16#6bb# => romdata <= X"12"; -- »
when 16#7bb# => romdata <= X"24"; -- »
when 16#8bb# => romdata <= X"48"; -- »
when 16#9bb# => romdata <= X"90"; -- »
when 16#abb# => romdata <= X"00"; -- »
when 16#bbb# => romdata <= X"00"; -- »
when 16#cbb# => romdata <= X"00"; -- »
when 16#0bc# => romdata <= X"00"; -- ¼
when 16#1bc# => romdata <= X"40"; -- ¼
when 16#2bc# => romdata <= X"c0"; -- ¼
when 16#3bc# => romdata <= X"40"; -- ¼
when 16#4bc# => romdata <= X"40"; -- ¼
when 16#5bc# => romdata <= X"42"; -- ¼
when 16#6bc# => romdata <= X"e6"; -- ¼
when 16#7bc# => romdata <= X"0a"; -- ¼
when 16#8bc# => romdata <= X"12"; -- ¼
when 16#9bc# => romdata <= X"1a"; -- ¼
when 16#abc# => romdata <= X"06"; -- ¼
when 16#bbc# => romdata <= X"00"; -- ¼
when 16#cbc# => romdata <= X"00"; -- ¼
when 16#0bd# => romdata <= X"00"; -- ½
when 16#1bd# => romdata <= X"40"; -- ½
when 16#2bd# => romdata <= X"c0"; -- ½
when 16#3bd# => romdata <= X"40"; -- ½
when 16#4bd# => romdata <= X"40"; -- ½
when 16#5bd# => romdata <= X"4c"; -- ½
when 16#6bd# => romdata <= X"f2"; -- ½
when 16#7bd# => romdata <= X"02"; -- ½
when 16#8bd# => romdata <= X"0c"; -- ½
when 16#9bd# => romdata <= X"10"; -- ½
when 16#abd# => romdata <= X"1e"; -- ½
when 16#bbd# => romdata <= X"00"; -- ½
when 16#cbd# => romdata <= X"00"; -- ½
when 16#0be# => romdata <= X"00"; -- ¾
when 16#1be# => romdata <= X"60"; -- ¾
when 16#2be# => romdata <= X"90"; -- ¾
when 16#3be# => romdata <= X"20"; -- ¾
when 16#4be# => romdata <= X"10"; -- ¾
when 16#5be# => romdata <= X"92"; -- ¾
when 16#6be# => romdata <= X"66"; -- ¾
when 16#7be# => romdata <= X"0a"; -- ¾
when 16#8be# => romdata <= X"12"; -- ¾
when 16#9be# => romdata <= X"1a"; -- ¾
when 16#abe# => romdata <= X"06"; -- ¾
when 16#bbe# => romdata <= X"00"; -- ¾
when 16#cbe# => romdata <= X"00"; -- ¾
when 16#0bf# => romdata <= X"00"; -- ¿
when 16#1bf# => romdata <= X"00"; -- ¿
when 16#2bf# => romdata <= X"10"; -- ¿
when 16#3bf# => romdata <= X"00"; -- ¿
when 16#4bf# => romdata <= X"10"; -- ¿
when 16#5bf# => romdata <= X"10"; -- ¿
when 16#6bf# => romdata <= X"20"; -- ¿
when 16#7bf# => romdata <= X"40"; -- ¿
when 16#8bf# => romdata <= X"42"; -- ¿
when 16#9bf# => romdata <= X"42"; -- ¿
when 16#abf# => romdata <= X"3c"; -- ¿
when 16#bbf# => romdata <= X"00"; -- ¿
when 16#cbf# => romdata <= X"00"; -- ¿
when 16#0c0# => romdata <= X"00"; -- À
when 16#1c0# => romdata <= X"10"; -- À
when 16#2c0# => romdata <= X"08"; -- À
when 16#3c0# => romdata <= X"00"; -- À
when 16#4c0# => romdata <= X"18"; -- À
when 16#5c0# => romdata <= X"24"; -- À
when 16#6c0# => romdata <= X"42"; -- À
when 16#7c0# => romdata <= X"42"; -- À
when 16#8c0# => romdata <= X"7e"; -- À
when 16#9c0# => romdata <= X"42"; -- À
when 16#ac0# => romdata <= X"42"; -- À
when 16#bc0# => romdata <= X"00"; -- À
when 16#cc0# => romdata <= X"00"; -- À
when 16#0c1# => romdata <= X"00"; -- Á
when 16#1c1# => romdata <= X"08"; -- Á
when 16#2c1# => romdata <= X"10"; -- Á
when 16#3c1# => romdata <= X"00"; -- Á
when 16#4c1# => romdata <= X"18"; -- Á
when 16#5c1# => romdata <= X"24"; -- Á
when 16#6c1# => romdata <= X"42"; -- Á
when 16#7c1# => romdata <= X"42"; -- Á
when 16#8c1# => romdata <= X"7e"; -- Á
when 16#9c1# => romdata <= X"42"; -- Á
when 16#ac1# => romdata <= X"42"; -- Á
when 16#bc1# => romdata <= X"00"; -- Á
when 16#cc1# => romdata <= X"00"; -- Á
when 16#0c2# => romdata <= X"00"; -- Â
when 16#1c2# => romdata <= X"18"; -- Â
when 16#2c2# => romdata <= X"24"; -- Â
when 16#3c2# => romdata <= X"00"; -- Â
when 16#4c2# => romdata <= X"18"; -- Â
when 16#5c2# => romdata <= X"24"; -- Â
when 16#6c2# => romdata <= X"42"; -- Â
when 16#7c2# => romdata <= X"42"; -- Â
when 16#8c2# => romdata <= X"7e"; -- Â
when 16#9c2# => romdata <= X"42"; -- Â
when 16#ac2# => romdata <= X"42"; -- Â
when 16#bc2# => romdata <= X"00"; -- Â
when 16#cc2# => romdata <= X"00"; -- Â
when 16#0c3# => romdata <= X"00"; -- Ã
when 16#1c3# => romdata <= X"32"; -- Ã
when 16#2c3# => romdata <= X"4c"; -- Ã
when 16#3c3# => romdata <= X"00"; -- Ã
when 16#4c3# => romdata <= X"18"; -- Ã
when 16#5c3# => romdata <= X"24"; -- Ã
when 16#6c3# => romdata <= X"42"; -- Ã
when 16#7c3# => romdata <= X"42"; -- Ã
when 16#8c3# => romdata <= X"7e"; -- Ã
when 16#9c3# => romdata <= X"42"; -- Ã
when 16#ac3# => romdata <= X"42"; -- Ã
when 16#bc3# => romdata <= X"00"; -- Ã
when 16#cc3# => romdata <= X"00"; -- Ã
when 16#0c4# => romdata <= X"00"; -- Ä
when 16#1c4# => romdata <= X"24"; -- Ä
when 16#2c4# => romdata <= X"24"; -- Ä
when 16#3c4# => romdata <= X"00"; -- Ä
when 16#4c4# => romdata <= X"18"; -- Ä
when 16#5c4# => romdata <= X"24"; -- Ä
when 16#6c4# => romdata <= X"42"; -- Ä
when 16#7c4# => romdata <= X"42"; -- Ä
when 16#8c4# => romdata <= X"7e"; -- Ä
when 16#9c4# => romdata <= X"42"; -- Ä
when 16#ac4# => romdata <= X"42"; -- Ä
when 16#bc4# => romdata <= X"00"; -- Ä
when 16#cc4# => romdata <= X"00"; -- Ä
when 16#0c5# => romdata <= X"00"; -- Å
when 16#1c5# => romdata <= X"18"; -- Å
when 16#2c5# => romdata <= X"24"; -- Å
when 16#3c5# => romdata <= X"18"; -- Å
when 16#4c5# => romdata <= X"18"; -- Å
when 16#5c5# => romdata <= X"24"; -- Å
when 16#6c5# => romdata <= X"42"; -- Å
when 16#7c5# => romdata <= X"42"; -- Å
when 16#8c5# => romdata <= X"7e"; -- Å
when 16#9c5# => romdata <= X"42"; -- Å
when 16#ac5# => romdata <= X"42"; -- Å
when 16#bc5# => romdata <= X"00"; -- Å
when 16#cc5# => romdata <= X"00"; -- Å
when 16#0c6# => romdata <= X"00"; -- Æ
when 16#1c6# => romdata <= X"00"; -- Æ
when 16#2c6# => romdata <= X"6e"; -- Æ
when 16#3c6# => romdata <= X"90"; -- Æ
when 16#4c6# => romdata <= X"90"; -- Æ
when 16#5c6# => romdata <= X"90"; -- Æ
when 16#6c6# => romdata <= X"9c"; -- Æ
when 16#7c6# => romdata <= X"f0"; -- Æ
when 16#8c6# => romdata <= X"90"; -- Æ
when 16#9c6# => romdata <= X"90"; -- Æ
when 16#ac6# => romdata <= X"9e"; -- Æ
when 16#bc6# => romdata <= X"00"; -- Æ
when 16#cc6# => romdata <= X"00"; -- Æ
when 16#0c7# => romdata <= X"00"; -- Ç
when 16#1c7# => romdata <= X"00"; -- Ç
when 16#2c7# => romdata <= X"3c"; -- Ç
when 16#3c7# => romdata <= X"42"; -- Ç
when 16#4c7# => romdata <= X"40"; -- Ç
when 16#5c7# => romdata <= X"40"; -- Ç
when 16#6c7# => romdata <= X"40"; -- Ç
when 16#7c7# => romdata <= X"40"; -- Ç
when 16#8c7# => romdata <= X"40"; -- Ç
when 16#9c7# => romdata <= X"42"; -- Ç
when 16#ac7# => romdata <= X"3c"; -- Ç
when 16#bc7# => romdata <= X"08"; -- Ç
when 16#cc7# => romdata <= X"10"; -- Ç
when 16#0c8# => romdata <= X"00"; -- È
when 16#1c8# => romdata <= X"10"; -- È
when 16#2c8# => romdata <= X"08"; -- È
when 16#3c8# => romdata <= X"00"; -- È
when 16#4c8# => romdata <= X"7e"; -- È
when 16#5c8# => romdata <= X"40"; -- È
when 16#6c8# => romdata <= X"40"; -- È
when 16#7c8# => romdata <= X"78"; -- È
when 16#8c8# => romdata <= X"40"; -- È
when 16#9c8# => romdata <= X"40"; -- È
when 16#ac8# => romdata <= X"7e"; -- È
when 16#bc8# => romdata <= X"00"; -- È
when 16#cc8# => romdata <= X"00"; -- È
when 16#0c9# => romdata <= X"00"; -- É
when 16#1c9# => romdata <= X"08"; -- É
when 16#2c9# => romdata <= X"10"; -- É
when 16#3c9# => romdata <= X"00"; -- É
when 16#4c9# => romdata <= X"7e"; -- É
when 16#5c9# => romdata <= X"40"; -- É
when 16#6c9# => romdata <= X"40"; -- É
when 16#7c9# => romdata <= X"78"; -- É
when 16#8c9# => romdata <= X"40"; -- É
when 16#9c9# => romdata <= X"40"; -- É
when 16#ac9# => romdata <= X"7e"; -- É
when 16#bc9# => romdata <= X"00"; -- É
when 16#cc9# => romdata <= X"00"; -- É
when 16#0ca# => romdata <= X"00"; -- Ê
when 16#1ca# => romdata <= X"18"; -- Ê
when 16#2ca# => romdata <= X"24"; -- Ê
when 16#3ca# => romdata <= X"00"; -- Ê
when 16#4ca# => romdata <= X"7e"; -- Ê
when 16#5ca# => romdata <= X"40"; -- Ê
when 16#6ca# => romdata <= X"40"; -- Ê
when 16#7ca# => romdata <= X"78"; -- Ê
when 16#8ca# => romdata <= X"40"; -- Ê
when 16#9ca# => romdata <= X"40"; -- Ê
when 16#aca# => romdata <= X"7e"; -- Ê
when 16#bca# => romdata <= X"00"; -- Ê
when 16#cca# => romdata <= X"00"; -- Ê
when 16#0cb# => romdata <= X"00"; -- Ë
when 16#1cb# => romdata <= X"24"; -- Ë
when 16#2cb# => romdata <= X"24"; -- Ë
when 16#3cb# => romdata <= X"00"; -- Ë
when 16#4cb# => romdata <= X"7e"; -- Ë
when 16#5cb# => romdata <= X"40"; -- Ë
when 16#6cb# => romdata <= X"40"; -- Ë
when 16#7cb# => romdata <= X"78"; -- Ë
when 16#8cb# => romdata <= X"40"; -- Ë
when 16#9cb# => romdata <= X"40"; -- Ë
when 16#acb# => romdata <= X"7e"; -- Ë
when 16#bcb# => romdata <= X"00"; -- Ë
when 16#ccb# => romdata <= X"00"; -- Ë
when 16#0cc# => romdata <= X"00"; -- Ì
when 16#1cc# => romdata <= X"20"; -- Ì
when 16#2cc# => romdata <= X"10"; -- Ì
when 16#3cc# => romdata <= X"00"; -- Ì
when 16#4cc# => romdata <= X"7c"; -- Ì
when 16#5cc# => romdata <= X"10"; -- Ì
when 16#6cc# => romdata <= X"10"; -- Ì
when 16#7cc# => romdata <= X"10"; -- Ì
when 16#8cc# => romdata <= X"10"; -- Ì
when 16#9cc# => romdata <= X"10"; -- Ì
when 16#acc# => romdata <= X"7c"; -- Ì
when 16#bcc# => romdata <= X"00"; -- Ì
when 16#ccc# => romdata <= X"00"; -- Ì
when 16#0cd# => romdata <= X"00"; -- Í
when 16#1cd# => romdata <= X"08"; -- Í
when 16#2cd# => romdata <= X"10"; -- Í
when 16#3cd# => romdata <= X"00"; -- Í
when 16#4cd# => romdata <= X"7c"; -- Í
when 16#5cd# => romdata <= X"10"; -- Í
when 16#6cd# => romdata <= X"10"; -- Í
when 16#7cd# => romdata <= X"10"; -- Í
when 16#8cd# => romdata <= X"10"; -- Í
when 16#9cd# => romdata <= X"10"; -- Í
when 16#acd# => romdata <= X"7c"; -- Í
when 16#bcd# => romdata <= X"00"; -- Í
when 16#ccd# => romdata <= X"00"; -- Í
when 16#0ce# => romdata <= X"00"; -- Î
when 16#1ce# => romdata <= X"18"; -- Î
when 16#2ce# => romdata <= X"24"; -- Î
when 16#3ce# => romdata <= X"00"; -- Î
when 16#4ce# => romdata <= X"7c"; -- Î
when 16#5ce# => romdata <= X"10"; -- Î
when 16#6ce# => romdata <= X"10"; -- Î
when 16#7ce# => romdata <= X"10"; -- Î
when 16#8ce# => romdata <= X"10"; -- Î
when 16#9ce# => romdata <= X"10"; -- Î
when 16#ace# => romdata <= X"7c"; -- Î
when 16#bce# => romdata <= X"00"; -- Î
when 16#cce# => romdata <= X"00"; -- Î
when 16#0cf# => romdata <= X"00"; -- Ï
when 16#1cf# => romdata <= X"44"; -- Ï
when 16#2cf# => romdata <= X"44"; -- Ï
when 16#3cf# => romdata <= X"00"; -- Ï
when 16#4cf# => romdata <= X"7c"; -- Ï
when 16#5cf# => romdata <= X"10"; -- Ï
when 16#6cf# => romdata <= X"10"; -- Ï
when 16#7cf# => romdata <= X"10"; -- Ï
when 16#8cf# => romdata <= X"10"; -- Ï
when 16#9cf# => romdata <= X"10"; -- Ï
when 16#acf# => romdata <= X"7c"; -- Ï
when 16#bcf# => romdata <= X"00"; -- Ï
when 16#ccf# => romdata <= X"00"; -- Ï
when 16#0d0# => romdata <= X"00"; -- Ð
when 16#1d0# => romdata <= X"00"; -- Ð
when 16#2d0# => romdata <= X"78"; -- Ð
when 16#3d0# => romdata <= X"44"; -- Ð
when 16#4d0# => romdata <= X"42"; -- Ð
when 16#5d0# => romdata <= X"42"; -- Ð
when 16#6d0# => romdata <= X"e2"; -- Ð
when 16#7d0# => romdata <= X"42"; -- Ð
when 16#8d0# => romdata <= X"42"; -- Ð
when 16#9d0# => romdata <= X"44"; -- Ð
when 16#ad0# => romdata <= X"78"; -- Ð
when 16#bd0# => romdata <= X"00"; -- Ð
when 16#cd0# => romdata <= X"00"; -- Ð
when 16#0d1# => romdata <= X"00"; -- Ñ
when 16#1d1# => romdata <= X"64"; -- Ñ
when 16#2d1# => romdata <= X"98"; -- Ñ
when 16#3d1# => romdata <= X"00"; -- Ñ
when 16#4d1# => romdata <= X"82"; -- Ñ
when 16#5d1# => romdata <= X"c2"; -- Ñ
when 16#6d1# => romdata <= X"a2"; -- Ñ
when 16#7d1# => romdata <= X"92"; -- Ñ
when 16#8d1# => romdata <= X"8a"; -- Ñ
when 16#9d1# => romdata <= X"86"; -- Ñ
when 16#ad1# => romdata <= X"82"; -- Ñ
when 16#bd1# => romdata <= X"00"; -- Ñ
when 16#cd1# => romdata <= X"00"; -- Ñ
when 16#0d2# => romdata <= X"00"; -- Ò
when 16#1d2# => romdata <= X"20"; -- Ò
when 16#2d2# => romdata <= X"10"; -- Ò
when 16#3d2# => romdata <= X"00"; -- Ò
when 16#4d2# => romdata <= X"7c"; -- Ò
when 16#5d2# => romdata <= X"82"; -- Ò
when 16#6d2# => romdata <= X"82"; -- Ò
when 16#7d2# => romdata <= X"82"; -- Ò
when 16#8d2# => romdata <= X"82"; -- Ò
when 16#9d2# => romdata <= X"82"; -- Ò
when 16#ad2# => romdata <= X"7c"; -- Ò
when 16#bd2# => romdata <= X"00"; -- Ò
when 16#cd2# => romdata <= X"00"; -- Ò
when 16#0d3# => romdata <= X"00"; -- Ó
when 16#1d3# => romdata <= X"08"; -- Ó
when 16#2d3# => romdata <= X"10"; -- Ó
when 16#3d3# => romdata <= X"00"; -- Ó
when 16#4d3# => romdata <= X"7c"; -- Ó
when 16#5d3# => romdata <= X"82"; -- Ó
when 16#6d3# => romdata <= X"82"; -- Ó
when 16#7d3# => romdata <= X"82"; -- Ó
when 16#8d3# => romdata <= X"82"; -- Ó
when 16#9d3# => romdata <= X"82"; -- Ó
when 16#ad3# => romdata <= X"7c"; -- Ó
when 16#bd3# => romdata <= X"00"; -- Ó
when 16#cd3# => romdata <= X"00"; -- Ó
when 16#0d4# => romdata <= X"00"; -- Ô
when 16#1d4# => romdata <= X"18"; -- Ô
when 16#2d4# => romdata <= X"24"; -- Ô
when 16#3d4# => romdata <= X"00"; -- Ô
when 16#4d4# => romdata <= X"7c"; -- Ô
when 16#5d4# => romdata <= X"82"; -- Ô
when 16#6d4# => romdata <= X"82"; -- Ô
when 16#7d4# => romdata <= X"82"; -- Ô
when 16#8d4# => romdata <= X"82"; -- Ô
when 16#9d4# => romdata <= X"82"; -- Ô
when 16#ad4# => romdata <= X"7c"; -- Ô
when 16#bd4# => romdata <= X"00"; -- Ô
when 16#cd4# => romdata <= X"00"; -- Ô
when 16#0d5# => romdata <= X"00"; -- Õ
when 16#1d5# => romdata <= X"64"; -- Õ
when 16#2d5# => romdata <= X"98"; -- Õ
when 16#3d5# => romdata <= X"00"; -- Õ
when 16#4d5# => romdata <= X"7c"; -- Õ
when 16#5d5# => romdata <= X"82"; -- Õ
when 16#6d5# => romdata <= X"82"; -- Õ
when 16#7d5# => romdata <= X"82"; -- Õ
when 16#8d5# => romdata <= X"82"; -- Õ
when 16#9d5# => romdata <= X"82"; -- Õ
when 16#ad5# => romdata <= X"7c"; -- Õ
when 16#bd5# => romdata <= X"00"; -- Õ
when 16#cd5# => romdata <= X"00"; -- Õ
when 16#0d6# => romdata <= X"00"; -- Ö
when 16#1d6# => romdata <= X"44"; -- Ö
when 16#2d6# => romdata <= X"44"; -- Ö
when 16#3d6# => romdata <= X"00"; -- Ö
when 16#4d6# => romdata <= X"7c"; -- Ö
when 16#5d6# => romdata <= X"82"; -- Ö
when 16#6d6# => romdata <= X"82"; -- Ö
when 16#7d6# => romdata <= X"82"; -- Ö
when 16#8d6# => romdata <= X"82"; -- Ö
when 16#9d6# => romdata <= X"82"; -- Ö
when 16#ad6# => romdata <= X"7c"; -- Ö
when 16#bd6# => romdata <= X"00"; -- Ö
when 16#cd6# => romdata <= X"00"; -- Ö
when 16#0d7# => romdata <= X"00"; -- ×
when 16#1d7# => romdata <= X"00"; -- ×
when 16#2d7# => romdata <= X"00"; -- ×
when 16#3d7# => romdata <= X"00"; -- ×
when 16#4d7# => romdata <= X"42"; -- ×
when 16#5d7# => romdata <= X"24"; -- ×
when 16#6d7# => romdata <= X"18"; -- ×
when 16#7d7# => romdata <= X"18"; -- ×
when 16#8d7# => romdata <= X"24"; -- ×
when 16#9d7# => romdata <= X"42"; -- ×
when 16#ad7# => romdata <= X"00"; -- ×
when 16#bd7# => romdata <= X"00"; -- ×
when 16#cd7# => romdata <= X"00"; -- ×
when 16#0d8# => romdata <= X"00"; -- Ø
when 16#1d8# => romdata <= X"02"; -- Ø
when 16#2d8# => romdata <= X"3c"; -- Ø
when 16#3d8# => romdata <= X"46"; -- Ø
when 16#4d8# => romdata <= X"4a"; -- Ø
when 16#5d8# => romdata <= X"4a"; -- Ø
when 16#6d8# => romdata <= X"52"; -- Ø
when 16#7d8# => romdata <= X"52"; -- Ø
when 16#8d8# => romdata <= X"52"; -- Ø
when 16#9d8# => romdata <= X"62"; -- Ø
when 16#ad8# => romdata <= X"3c"; -- Ø
when 16#bd8# => romdata <= X"40"; -- Ø
when 16#cd8# => romdata <= X"00"; -- Ø
when 16#0d9# => romdata <= X"00"; -- Ù
when 16#1d9# => romdata <= X"20"; -- Ù
when 16#2d9# => romdata <= X"10"; -- Ù
when 16#3d9# => romdata <= X"00"; -- Ù
when 16#4d9# => romdata <= X"42"; -- Ù
when 16#5d9# => romdata <= X"42"; -- Ù
when 16#6d9# => romdata <= X"42"; -- Ù
when 16#7d9# => romdata <= X"42"; -- Ù
when 16#8d9# => romdata <= X"42"; -- Ù
when 16#9d9# => romdata <= X"42"; -- Ù
when 16#ad9# => romdata <= X"3c"; -- Ù
when 16#bd9# => romdata <= X"00"; -- Ù
when 16#cd9# => romdata <= X"00"; -- Ù
when 16#0da# => romdata <= X"00"; -- Ú
when 16#1da# => romdata <= X"08"; -- Ú
when 16#2da# => romdata <= X"10"; -- Ú
when 16#3da# => romdata <= X"00"; -- Ú
when 16#4da# => romdata <= X"42"; -- Ú
when 16#5da# => romdata <= X"42"; -- Ú
when 16#6da# => romdata <= X"42"; -- Ú
when 16#7da# => romdata <= X"42"; -- Ú
when 16#8da# => romdata <= X"42"; -- Ú
when 16#9da# => romdata <= X"42"; -- Ú
when 16#ada# => romdata <= X"3c"; -- Ú
when 16#bda# => romdata <= X"00"; -- Ú
when 16#cda# => romdata <= X"00"; -- Ú
when 16#0db# => romdata <= X"00"; -- Û
when 16#1db# => romdata <= X"18"; -- Û
when 16#2db# => romdata <= X"24"; -- Û
when 16#3db# => romdata <= X"00"; -- Û
when 16#4db# => romdata <= X"42"; -- Û
when 16#5db# => romdata <= X"42"; -- Û
when 16#6db# => romdata <= X"42"; -- Û
when 16#7db# => romdata <= X"42"; -- Û
when 16#8db# => romdata <= X"42"; -- Û
when 16#9db# => romdata <= X"42"; -- Û
when 16#adb# => romdata <= X"3c"; -- Û
when 16#bdb# => romdata <= X"00"; -- Û
when 16#cdb# => romdata <= X"00"; -- Û
when 16#0dc# => romdata <= X"00"; -- Ü
when 16#1dc# => romdata <= X"24"; -- Ü
when 16#2dc# => romdata <= X"24"; -- Ü
when 16#3dc# => romdata <= X"00"; -- Ü
when 16#4dc# => romdata <= X"42"; -- Ü
when 16#5dc# => romdata <= X"42"; -- Ü
when 16#6dc# => romdata <= X"42"; -- Ü
when 16#7dc# => romdata <= X"42"; -- Ü
when 16#8dc# => romdata <= X"42"; -- Ü
when 16#9dc# => romdata <= X"42"; -- Ü
when 16#adc# => romdata <= X"3c"; -- Ü
when 16#bdc# => romdata <= X"00"; -- Ü
when 16#cdc# => romdata <= X"00"; -- Ü
when 16#0dd# => romdata <= X"00"; -- Ý
when 16#1dd# => romdata <= X"08"; -- Ý
when 16#2dd# => romdata <= X"10"; -- Ý
when 16#3dd# => romdata <= X"00"; -- Ý
when 16#4dd# => romdata <= X"44"; -- Ý
when 16#5dd# => romdata <= X"44"; -- Ý
when 16#6dd# => romdata <= X"28"; -- Ý
when 16#7dd# => romdata <= X"10"; -- Ý
when 16#8dd# => romdata <= X"10"; -- Ý
when 16#9dd# => romdata <= X"10"; -- Ý
when 16#add# => romdata <= X"10"; -- Ý
when 16#bdd# => romdata <= X"00"; -- Ý
when 16#cdd# => romdata <= X"00"; -- Ý
when 16#0de# => romdata <= X"00"; -- Þ
when 16#1de# => romdata <= X"00"; -- Þ
when 16#2de# => romdata <= X"40"; -- Þ
when 16#3de# => romdata <= X"7c"; -- Þ
when 16#4de# => romdata <= X"42"; -- Þ
when 16#5de# => romdata <= X"42"; -- Þ
when 16#6de# => romdata <= X"42"; -- Þ
when 16#7de# => romdata <= X"7c"; -- Þ
when 16#8de# => romdata <= X"40"; -- Þ
when 16#9de# => romdata <= X"40"; -- Þ
when 16#ade# => romdata <= X"40"; -- Þ
when 16#bde# => romdata <= X"00"; -- Þ
when 16#cde# => romdata <= X"00"; -- Þ
when 16#0df# => romdata <= X"00"; -- ß
when 16#1df# => romdata <= X"00"; -- ß
when 16#2df# => romdata <= X"38"; -- ß
when 16#3df# => romdata <= X"44"; -- ß
when 16#4df# => romdata <= X"44"; -- ß
when 16#5df# => romdata <= X"48"; -- ß
when 16#6df# => romdata <= X"50"; -- ß
when 16#7df# => romdata <= X"4c"; -- ß
when 16#8df# => romdata <= X"42"; -- ß
when 16#9df# => romdata <= X"42"; -- ß
when 16#adf# => romdata <= X"5c"; -- ß
when 16#bdf# => romdata <= X"00"; -- ß
when 16#cdf# => romdata <= X"00"; -- ß
when 16#0e0# => romdata <= X"00"; -- à
when 16#1e0# => romdata <= X"00"; -- à
when 16#2e0# => romdata <= X"10"; -- à
when 16#3e0# => romdata <= X"08"; -- à
when 16#4e0# => romdata <= X"00"; -- à
when 16#5e0# => romdata <= X"3c"; -- à
when 16#6e0# => romdata <= X"02"; -- à
when 16#7e0# => romdata <= X"3e"; -- à
when 16#8e0# => romdata <= X"42"; -- à
when 16#9e0# => romdata <= X"46"; -- à
when 16#ae0# => romdata <= X"3a"; -- à
when 16#be0# => romdata <= X"00"; -- à
when 16#ce0# => romdata <= X"00"; -- à
when 16#0e1# => romdata <= X"00"; -- á
when 16#1e1# => romdata <= X"00"; -- á
when 16#2e1# => romdata <= X"04"; -- á
when 16#3e1# => romdata <= X"08"; -- á
when 16#4e1# => romdata <= X"00"; -- á
when 16#5e1# => romdata <= X"3c"; -- á
when 16#6e1# => romdata <= X"02"; -- á
when 16#7e1# => romdata <= X"3e"; -- á
when 16#8e1# => romdata <= X"42"; -- á
when 16#9e1# => romdata <= X"46"; -- á
when 16#ae1# => romdata <= X"3a"; -- á
when 16#be1# => romdata <= X"00"; -- á
when 16#ce1# => romdata <= X"00"; -- á
when 16#0e2# => romdata <= X"00"; -- â
when 16#1e2# => romdata <= X"00"; -- â
when 16#2e2# => romdata <= X"18"; -- â
when 16#3e2# => romdata <= X"24"; -- â
when 16#4e2# => romdata <= X"00"; -- â
when 16#5e2# => romdata <= X"3c"; -- â
when 16#6e2# => romdata <= X"02"; -- â
when 16#7e2# => romdata <= X"3e"; -- â
when 16#8e2# => romdata <= X"42"; -- â
when 16#9e2# => romdata <= X"46"; -- â
when 16#ae2# => romdata <= X"3a"; -- â
when 16#be2# => romdata <= X"00"; -- â
when 16#ce2# => romdata <= X"00"; -- â
when 16#0e3# => romdata <= X"00"; -- ã
when 16#1e3# => romdata <= X"00"; -- ã
when 16#2e3# => romdata <= X"32"; -- ã
when 16#3e3# => romdata <= X"4c"; -- ã
when 16#4e3# => romdata <= X"00"; -- ã
when 16#5e3# => romdata <= X"3c"; -- ã
when 16#6e3# => romdata <= X"02"; -- ã
when 16#7e3# => romdata <= X"3e"; -- ã
when 16#8e3# => romdata <= X"42"; -- ã
when 16#9e3# => romdata <= X"46"; -- ã
when 16#ae3# => romdata <= X"3a"; -- ã
when 16#be3# => romdata <= X"00"; -- ã
when 16#ce3# => romdata <= X"00"; -- ã
when 16#0e4# => romdata <= X"00"; -- ä
when 16#1e4# => romdata <= X"00"; -- ä
when 16#2e4# => romdata <= X"24"; -- ä
when 16#3e4# => romdata <= X"24"; -- ä
when 16#4e4# => romdata <= X"00"; -- ä
when 16#5e4# => romdata <= X"3c"; -- ä
when 16#6e4# => romdata <= X"02"; -- ä
when 16#7e4# => romdata <= X"3e"; -- ä
when 16#8e4# => romdata <= X"42"; -- ä
when 16#9e4# => romdata <= X"46"; -- ä
when 16#ae4# => romdata <= X"3a"; -- ä
when 16#be4# => romdata <= X"00"; -- ä
when 16#ce4# => romdata <= X"00"; -- ä
when 16#0e5# => romdata <= X"00"; -- å
when 16#1e5# => romdata <= X"18"; -- å
when 16#2e5# => romdata <= X"24"; -- å
when 16#3e5# => romdata <= X"18"; -- å
when 16#4e5# => romdata <= X"00"; -- å
when 16#5e5# => romdata <= X"3c"; -- å
when 16#6e5# => romdata <= X"02"; -- å
when 16#7e5# => romdata <= X"3e"; -- å
when 16#8e5# => romdata <= X"42"; -- å
when 16#9e5# => romdata <= X"46"; -- å
when 16#ae5# => romdata <= X"3a"; -- å
when 16#be5# => romdata <= X"00"; -- å
when 16#ce5# => romdata <= X"00"; -- å
when 16#0e6# => romdata <= X"00"; -- æ
when 16#1e6# => romdata <= X"00"; -- æ
when 16#2e6# => romdata <= X"00"; -- æ
when 16#3e6# => romdata <= X"00"; -- æ
when 16#4e6# => romdata <= X"00"; -- æ
when 16#5e6# => romdata <= X"6c"; -- æ
when 16#6e6# => romdata <= X"12"; -- æ
when 16#7e6# => romdata <= X"7c"; -- æ
when 16#8e6# => romdata <= X"90"; -- æ
when 16#9e6# => romdata <= X"92"; -- æ
when 16#ae6# => romdata <= X"6c"; -- æ
when 16#be6# => romdata <= X"00"; -- æ
when 16#ce6# => romdata <= X"00"; -- æ
when 16#0e7# => romdata <= X"00"; -- ç
when 16#1e7# => romdata <= X"00"; -- ç
when 16#2e7# => romdata <= X"00"; -- ç
when 16#3e7# => romdata <= X"00"; -- ç
when 16#4e7# => romdata <= X"00"; -- ç
when 16#5e7# => romdata <= X"3c"; -- ç
when 16#6e7# => romdata <= X"42"; -- ç
when 16#7e7# => romdata <= X"40"; -- ç
when 16#8e7# => romdata <= X"40"; -- ç
when 16#9e7# => romdata <= X"42"; -- ç
when 16#ae7# => romdata <= X"3c"; -- ç
when 16#be7# => romdata <= X"08"; -- ç
when 16#ce7# => romdata <= X"10"; -- ç
when 16#0e8# => romdata <= X"00"; -- è
when 16#1e8# => romdata <= X"00"; -- è
when 16#2e8# => romdata <= X"10"; -- è
when 16#3e8# => romdata <= X"08"; -- è
when 16#4e8# => romdata <= X"00"; -- è
when 16#5e8# => romdata <= X"3c"; -- è
when 16#6e8# => romdata <= X"42"; -- è
when 16#7e8# => romdata <= X"7e"; -- è
when 16#8e8# => romdata <= X"40"; -- è
when 16#9e8# => romdata <= X"42"; -- è
when 16#ae8# => romdata <= X"3c"; -- è
when 16#be8# => romdata <= X"00"; -- è
when 16#ce8# => romdata <= X"00"; -- è
when 16#0e9# => romdata <= X"00"; -- é
when 16#1e9# => romdata <= X"00"; -- é
when 16#2e9# => romdata <= X"08"; -- é
when 16#3e9# => romdata <= X"10"; -- é
when 16#4e9# => romdata <= X"00"; -- é
when 16#5e9# => romdata <= X"3c"; -- é
when 16#6e9# => romdata <= X"42"; -- é
when 16#7e9# => romdata <= X"7e"; -- é
when 16#8e9# => romdata <= X"40"; -- é
when 16#9e9# => romdata <= X"42"; -- é
when 16#ae9# => romdata <= X"3c"; -- é
when 16#be9# => romdata <= X"00"; -- é
when 16#ce9# => romdata <= X"00"; -- é
when 16#0ea# => romdata <= X"00"; -- ê
when 16#1ea# => romdata <= X"00"; -- ê
when 16#2ea# => romdata <= X"18"; -- ê
when 16#3ea# => romdata <= X"24"; -- ê
when 16#4ea# => romdata <= X"00"; -- ê
when 16#5ea# => romdata <= X"3c"; -- ê
when 16#6ea# => romdata <= X"42"; -- ê
when 16#7ea# => romdata <= X"7e"; -- ê
when 16#8ea# => romdata <= X"40"; -- ê
when 16#9ea# => romdata <= X"42"; -- ê
when 16#aea# => romdata <= X"3c"; -- ê
when 16#bea# => romdata <= X"00"; -- ê
when 16#cea# => romdata <= X"00"; -- ê
when 16#0eb# => romdata <= X"00"; -- ë
when 16#1eb# => romdata <= X"00"; -- ë
when 16#2eb# => romdata <= X"24"; -- ë
when 16#3eb# => romdata <= X"24"; -- ë
when 16#4eb# => romdata <= X"00"; -- ë
when 16#5eb# => romdata <= X"3c"; -- ë
when 16#6eb# => romdata <= X"42"; -- ë
when 16#7eb# => romdata <= X"7e"; -- ë
when 16#8eb# => romdata <= X"40"; -- ë
when 16#9eb# => romdata <= X"42"; -- ë
when 16#aeb# => romdata <= X"3c"; -- ë
when 16#beb# => romdata <= X"00"; -- ë
when 16#ceb# => romdata <= X"00"; -- ë
when 16#0ec# => romdata <= X"00"; -- ì
when 16#1ec# => romdata <= X"00"; -- ì
when 16#2ec# => romdata <= X"20"; -- ì
when 16#3ec# => romdata <= X"10"; -- ì
when 16#4ec# => romdata <= X"00"; -- ì
when 16#5ec# => romdata <= X"30"; -- ì
when 16#6ec# => romdata <= X"10"; -- ì
when 16#7ec# => romdata <= X"10"; -- ì
when 16#8ec# => romdata <= X"10"; -- ì
when 16#9ec# => romdata <= X"10"; -- ì
when 16#aec# => romdata <= X"7c"; -- ì
when 16#bec# => romdata <= X"00"; -- ì
when 16#cec# => romdata <= X"00"; -- ì
when 16#0ed# => romdata <= X"00"; -- í
when 16#1ed# => romdata <= X"00"; -- í
when 16#2ed# => romdata <= X"10"; -- í
when 16#3ed# => romdata <= X"20"; -- í
when 16#4ed# => romdata <= X"00"; -- í
when 16#5ed# => romdata <= X"30"; -- í
when 16#6ed# => romdata <= X"10"; -- í
when 16#7ed# => romdata <= X"10"; -- í
when 16#8ed# => romdata <= X"10"; -- í
when 16#9ed# => romdata <= X"10"; -- í
when 16#aed# => romdata <= X"7c"; -- í
when 16#bed# => romdata <= X"00"; -- í
when 16#ced# => romdata <= X"00"; -- í
when 16#0ee# => romdata <= X"00"; -- î
when 16#1ee# => romdata <= X"00"; -- î
when 16#2ee# => romdata <= X"30"; -- î
when 16#3ee# => romdata <= X"48"; -- î
when 16#4ee# => romdata <= X"00"; -- î
when 16#5ee# => romdata <= X"30"; -- î
when 16#6ee# => romdata <= X"10"; -- î
when 16#7ee# => romdata <= X"10"; -- î
when 16#8ee# => romdata <= X"10"; -- î
when 16#9ee# => romdata <= X"10"; -- î
when 16#aee# => romdata <= X"7c"; -- î
when 16#bee# => romdata <= X"00"; -- î
when 16#cee# => romdata <= X"00"; -- î
when 16#0ef# => romdata <= X"00"; -- ï
when 16#1ef# => romdata <= X"00"; -- ï
when 16#2ef# => romdata <= X"48"; -- ï
when 16#3ef# => romdata <= X"48"; -- ï
when 16#4ef# => romdata <= X"00"; -- ï
when 16#5ef# => romdata <= X"30"; -- ï
when 16#6ef# => romdata <= X"10"; -- ï
when 16#7ef# => romdata <= X"10"; -- ï
when 16#8ef# => romdata <= X"10"; -- ï
when 16#9ef# => romdata <= X"10"; -- ï
when 16#aef# => romdata <= X"7c"; -- ï
when 16#bef# => romdata <= X"00"; -- ï
when 16#cef# => romdata <= X"00"; -- ï
when 16#0f0# => romdata <= X"00"; -- ð
when 16#1f0# => romdata <= X"24"; -- ð
when 16#2f0# => romdata <= X"18"; -- ð
when 16#3f0# => romdata <= X"28"; -- ð
when 16#4f0# => romdata <= X"04"; -- ð
when 16#5f0# => romdata <= X"3c"; -- ð
when 16#6f0# => romdata <= X"42"; -- ð
when 16#7f0# => romdata <= X"42"; -- ð
when 16#8f0# => romdata <= X"42"; -- ð
when 16#9f0# => romdata <= X"42"; -- ð
when 16#af0# => romdata <= X"3c"; -- ð
when 16#bf0# => romdata <= X"00"; -- ð
when 16#cf0# => romdata <= X"00"; -- ð
when 16#0f1# => romdata <= X"00"; -- ñ
when 16#1f1# => romdata <= X"00"; -- ñ
when 16#2f1# => romdata <= X"32"; -- ñ
when 16#3f1# => romdata <= X"4c"; -- ñ
when 16#4f1# => romdata <= X"00"; -- ñ
when 16#5f1# => romdata <= X"5c"; -- ñ
when 16#6f1# => romdata <= X"62"; -- ñ
when 16#7f1# => romdata <= X"42"; -- ñ
when 16#8f1# => romdata <= X"42"; -- ñ
when 16#9f1# => romdata <= X"42"; -- ñ
when 16#af1# => romdata <= X"42"; -- ñ
when 16#bf1# => romdata <= X"00"; -- ñ
when 16#cf1# => romdata <= X"00"; -- ñ
when 16#0f2# => romdata <= X"00"; -- ò
when 16#1f2# => romdata <= X"00"; -- ò
when 16#2f2# => romdata <= X"20"; -- ò
when 16#3f2# => romdata <= X"10"; -- ò
when 16#4f2# => romdata <= X"00"; -- ò
when 16#5f2# => romdata <= X"3c"; -- ò
when 16#6f2# => romdata <= X"42"; -- ò
when 16#7f2# => romdata <= X"42"; -- ò
when 16#8f2# => romdata <= X"42"; -- ò
when 16#9f2# => romdata <= X"42"; -- ò
when 16#af2# => romdata <= X"3c"; -- ò
when 16#bf2# => romdata <= X"00"; -- ò
when 16#cf2# => romdata <= X"00"; -- ò
when 16#0f3# => romdata <= X"00"; -- ó
when 16#1f3# => romdata <= X"00"; -- ó
when 16#2f3# => romdata <= X"08"; -- ó
when 16#3f3# => romdata <= X"10"; -- ó
when 16#4f3# => romdata <= X"00"; -- ó
when 16#5f3# => romdata <= X"3c"; -- ó
when 16#6f3# => romdata <= X"42"; -- ó
when 16#7f3# => romdata <= X"42"; -- ó
when 16#8f3# => romdata <= X"42"; -- ó
when 16#9f3# => romdata <= X"42"; -- ó
when 16#af3# => romdata <= X"3c"; -- ó
when 16#bf3# => romdata <= X"00"; -- ó
when 16#cf3# => romdata <= X"00"; -- ó
when 16#0f4# => romdata <= X"00"; -- ô
when 16#1f4# => romdata <= X"00"; -- ô
when 16#2f4# => romdata <= X"18"; -- ô
when 16#3f4# => romdata <= X"24"; -- ô
when 16#4f4# => romdata <= X"00"; -- ô
when 16#5f4# => romdata <= X"3c"; -- ô
when 16#6f4# => romdata <= X"42"; -- ô
when 16#7f4# => romdata <= X"42"; -- ô
when 16#8f4# => romdata <= X"42"; -- ô
when 16#9f4# => romdata <= X"42"; -- ô
when 16#af4# => romdata <= X"3c"; -- ô
when 16#bf4# => romdata <= X"00"; -- ô
when 16#cf4# => romdata <= X"00"; -- ô
when 16#0f5# => romdata <= X"00"; -- õ
when 16#1f5# => romdata <= X"00"; -- õ
when 16#2f5# => romdata <= X"32"; -- õ
when 16#3f5# => romdata <= X"4c"; -- õ
when 16#4f5# => romdata <= X"00"; -- õ
when 16#5f5# => romdata <= X"3c"; -- õ
when 16#6f5# => romdata <= X"42"; -- õ
when 16#7f5# => romdata <= X"42"; -- õ
when 16#8f5# => romdata <= X"42"; -- õ
when 16#9f5# => romdata <= X"42"; -- õ
when 16#af5# => romdata <= X"3c"; -- õ
when 16#bf5# => romdata <= X"00"; -- õ
when 16#cf5# => romdata <= X"00"; -- õ
when 16#0f6# => romdata <= X"00"; -- ö
when 16#1f6# => romdata <= X"00"; -- ö
when 16#2f6# => romdata <= X"24"; -- ö
when 16#3f6# => romdata <= X"24"; -- ö
when 16#4f6# => romdata <= X"00"; -- ö
when 16#5f6# => romdata <= X"3c"; -- ö
when 16#6f6# => romdata <= X"42"; -- ö
when 16#7f6# => romdata <= X"42"; -- ö
when 16#8f6# => romdata <= X"42"; -- ö
when 16#9f6# => romdata <= X"42"; -- ö
when 16#af6# => romdata <= X"3c"; -- ö
when 16#bf6# => romdata <= X"00"; -- ö
when 16#cf6# => romdata <= X"00"; -- ö
when 16#0f7# => romdata <= X"00"; -- ÷
when 16#1f7# => romdata <= X"00"; -- ÷
when 16#2f7# => romdata <= X"00"; -- ÷
when 16#3f7# => romdata <= X"10"; -- ÷
when 16#4f7# => romdata <= X"10"; -- ÷
when 16#5f7# => romdata <= X"00"; -- ÷
when 16#6f7# => romdata <= X"7c"; -- ÷
when 16#7f7# => romdata <= X"00"; -- ÷
when 16#8f7# => romdata <= X"10"; -- ÷
when 16#9f7# => romdata <= X"10"; -- ÷
when 16#af7# => romdata <= X"00"; -- ÷
when 16#bf7# => romdata <= X"00"; -- ÷
when 16#cf7# => romdata <= X"00"; -- ÷
when 16#0f8# => romdata <= X"00"; -- ø
when 16#1f8# => romdata <= X"00"; -- ø
when 16#2f8# => romdata <= X"00"; -- ø
when 16#3f8# => romdata <= X"00"; -- ø
when 16#4f8# => romdata <= X"02"; -- ø
when 16#5f8# => romdata <= X"3c"; -- ø
when 16#6f8# => romdata <= X"46"; -- ø
when 16#7f8# => romdata <= X"4a"; -- ø
when 16#8f8# => romdata <= X"52"; -- ø
when 16#9f8# => romdata <= X"62"; -- ø
when 16#af8# => romdata <= X"3c"; -- ø
when 16#bf8# => romdata <= X"40"; -- ø
when 16#cf8# => romdata <= X"00"; -- ø
when 16#0f9# => romdata <= X"00"; -- ù
when 16#1f9# => romdata <= X"00"; -- ù
when 16#2f9# => romdata <= X"20"; -- ù
when 16#3f9# => romdata <= X"10"; -- ù
when 16#4f9# => romdata <= X"00"; -- ù
when 16#5f9# => romdata <= X"44"; -- ù
when 16#6f9# => romdata <= X"44"; -- ù
when 16#7f9# => romdata <= X"44"; -- ù
when 16#8f9# => romdata <= X"44"; -- ù
when 16#9f9# => romdata <= X"44"; -- ù
when 16#af9# => romdata <= X"3a"; -- ù
when 16#bf9# => romdata <= X"00"; -- ù
when 16#cf9# => romdata <= X"00"; -- ù
when 16#0fa# => romdata <= X"00"; -- ú
when 16#1fa# => romdata <= X"00"; -- ú
when 16#2fa# => romdata <= X"08"; -- ú
when 16#3fa# => romdata <= X"10"; -- ú
when 16#4fa# => romdata <= X"00"; -- ú
when 16#5fa# => romdata <= X"44"; -- ú
when 16#6fa# => romdata <= X"44"; -- ú
when 16#7fa# => romdata <= X"44"; -- ú
when 16#8fa# => romdata <= X"44"; -- ú
when 16#9fa# => romdata <= X"44"; -- ú
when 16#afa# => romdata <= X"3a"; -- ú
when 16#bfa# => romdata <= X"00"; -- ú
when 16#cfa# => romdata <= X"00"; -- ú
when 16#0fb# => romdata <= X"00"; -- û
when 16#1fb# => romdata <= X"00"; -- û
when 16#2fb# => romdata <= X"18"; -- û
when 16#3fb# => romdata <= X"24"; -- û
when 16#4fb# => romdata <= X"00"; -- û
when 16#5fb# => romdata <= X"44"; -- û
when 16#6fb# => romdata <= X"44"; -- û
when 16#7fb# => romdata <= X"44"; -- û
when 16#8fb# => romdata <= X"44"; -- û
when 16#9fb# => romdata <= X"44"; -- û
when 16#afb# => romdata <= X"3a"; -- û
when 16#bfb# => romdata <= X"00"; -- û
when 16#cfb# => romdata <= X"00"; -- û
when 16#0fc# => romdata <= X"00"; -- ü
when 16#1fc# => romdata <= X"00"; -- ü
when 16#2fc# => romdata <= X"28"; -- ü
when 16#3fc# => romdata <= X"28"; -- ü
when 16#4fc# => romdata <= X"00"; -- ü
when 16#5fc# => romdata <= X"44"; -- ü
when 16#6fc# => romdata <= X"44"; -- ü
when 16#7fc# => romdata <= X"44"; -- ü
when 16#8fc# => romdata <= X"44"; -- ü
when 16#9fc# => romdata <= X"44"; -- ü
when 16#afc# => romdata <= X"3a"; -- ü
when 16#bfc# => romdata <= X"00"; -- ü
when 16#cfc# => romdata <= X"00"; -- ü
when 16#0fd# => romdata <= X"00"; -- ý
when 16#1fd# => romdata <= X"00"; -- ý
when 16#2fd# => romdata <= X"08"; -- ý
when 16#3fd# => romdata <= X"10"; -- ý
when 16#4fd# => romdata <= X"00"; -- ý
when 16#5fd# => romdata <= X"42"; -- ý
when 16#6fd# => romdata <= X"42"; -- ý
when 16#7fd# => romdata <= X"42"; -- ý
when 16#8fd# => romdata <= X"46"; -- ý
when 16#9fd# => romdata <= X"3a"; -- ý
when 16#afd# => romdata <= X"02"; -- ý
when 16#bfd# => romdata <= X"42"; -- ý
when 16#cfd# => romdata <= X"3c"; -- ý
when 16#0fe# => romdata <= X"00"; -- þ
when 16#1fe# => romdata <= X"00"; -- þ
when 16#2fe# => romdata <= X"00"; -- þ
when 16#3fe# => romdata <= X"40"; -- þ
when 16#4fe# => romdata <= X"40"; -- þ
when 16#5fe# => romdata <= X"5c"; -- þ
when 16#6fe# => romdata <= X"62"; -- þ
when 16#7fe# => romdata <= X"42"; -- þ
when 16#8fe# => romdata <= X"42"; -- þ
when 16#9fe# => romdata <= X"62"; -- þ
when 16#afe# => romdata <= X"5c"; -- þ
when 16#bfe# => romdata <= X"40"; -- þ
when 16#cfe# => romdata <= X"40"; -- þ
when 16#0ff# => romdata <= X"00"; -- ÿ
when 16#1ff# => romdata <= X"00"; -- ÿ
when 16#2ff# => romdata <= X"24"; -- ÿ
when 16#3ff# => romdata <= X"24"; -- ÿ
when 16#4ff# => romdata <= X"00"; -- ÿ
when 16#5ff# => romdata <= X"42"; -- ÿ
when 16#6ff# => romdata <= X"42"; -- ÿ
when 16#7ff# => romdata <= X"42"; -- ÿ
when 16#8ff# => romdata <= X"46"; -- ÿ
when 16#9ff# => romdata <= X"3a"; -- ÿ
when 16#aff# => romdata <= X"02"; -- ÿ
when 16#bff# => romdata <= X"42"; -- ÿ
when 16#cff# => romdata <= X"3c"; -- ÿ
when others => romdata <= (others => '0');
end case;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--! @file onewire_idtemp_pkg.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright LGPL v2.1
--! @brief Constants for the 1-wire ID and temperature sensor interface.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--! @brief Package declaration of onewire_idtemp_pkg
package onewire_idtemp_pkg is
-----------------------------------------------------------------------------
-- Types and Constants
-----------------------------------------------------------------------------
--! DS18B20 ID and temperature sensor family code
constant code_ds18b20_c : std_ulogic_vector(7 downto 0) := x"28";
--! DS2401 ID family code
constant code_ds2401_c : std_ulogic_vector(7 downto 0) := x"01";
--! Search command
constant cmd_search_c : std_ulogic_vector(7 downto 0) := x"F0";
--! Match ROM command
constant cmd_match_c : std_ulogic_vector(7 downto 0) := x"55";
--! Skip ROM command
constant cmd_skip_c : std_ulogic_vector(7 downto 0) := x"CC";
--! Convert command
constant cmd_convert_c : std_ulogic_vector(7 downto 0) := x"44";
--! Read scratchpad
constant cmd_read_sp_c : std_ulogic_vector(7 downto 0) := x"BE";
end package onewire_idtemp_pkg;
|
entity arrayop1 is
end entity;
architecture test of arrayop1 is
begin
process is
variable x : bit_vector(1 to 3);
begin
assert x < "000";
wait;
end process;
end architecture;
|
entity arrayop1 is
end entity;
architecture test of arrayop1 is
begin
process is
variable x : bit_vector(1 to 3);
begin
assert x < "000";
wait;
end process;
end architecture;
|
entity arrayop1 is
end entity;
architecture test of arrayop1 is
begin
process is
variable x : bit_vector(1 to 3);
begin
assert x < "000";
wait;
end process;
end architecture;
|
entity arrayop1 is
end entity;
architecture test of arrayop1 is
begin
process is
variable x : bit_vector(1 to 3);
begin
assert x < "000";
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: genclkbuf
-- File: genclkbuf.vhd
-- Author: Jiri Gaisler, Marko Isomaki - Gaisler Research
-- Description: Hard buffers with tech wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity techbuf is
generic(
buftype : integer range 0 to 6 := 0;
tech : integer range 0 to NTECH := inferred);
port( i : in std_ulogic; o : out std_ulogic);
end entity;
architecture rtl of techbuf is
component clkbuf_fusion is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_apa3 is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_apa3e is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_apa3l is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_actel is generic( buftype : integer range 0 to 6 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_xilinx is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_ut025crh is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_ut130hbd is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_nextreme is generic( buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
component clkbuf_n2x is generic(buftype : integer range 0 to 3 := 0);
port( i : in std_ulogic; o : out std_ulogic);
end component;
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
gen : if has_techbuf(tech) = 0 generate
o <= i;
end generate;
fus : if (tech = actfus) generate
fus0 : clkbuf_fusion generic map (buftype => buftype) port map(i => i, o => o);
end generate;
pa3 : if (tech = apa3) generate
pa30 : clkbuf_apa3 generic map (buftype => buftype) port map(i => i, o => o);
end generate;
pa3e : if (tech = apa3e) generate
pae30 : clkbuf_apa3e generic map (buftype => buftype) port map(i => i, o => o);
end generate;
pa3l : if (tech = apa3l) generate
pa3l0 : clkbuf_apa3l generic map (buftype => buftype) port map(i => i, o => o);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
axc0 : clkbuf_actel generic map (buftype => buftype) port map(i => i, o => o);
end generate;
xil : if (is_unisim(tech) = 1) generate
xil0 : clkbuf_xilinx generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut : if (tech = ut25) generate
ut0 : clkbuf_ut025crh generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut13 : if (tech = ut130) generate
ut0 : clkbuf_ut130hbd generic map (buftype => buftype) port map(i => i, o => o);
end generate;
ut09 : if (tech = ut90) generate
ut0 : clkand_ut90nhbd port map(i => i, en => vcc, o => o, tsten => gnd);
end generate;
easic: if tech = easic90 generate
eas : clkbuf_nextreme generic map (buftype => buftype) port map(i => i, o => o);
end generate easic;
n2x : if tech = easic45 generate
n2x0 : clkbuf_n2x generic map (buftype => buftype) port map(i => i, o => o);
end generate;
end architecture;
|
library ieee, base;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use base.base.all;
entity RightShiftTests is
end entity RightShiftTests;
architecture TB of RightShiftTests is
component RightShift
port(c_in : in unsigned(3 downto 0) := "0001";
c_out : out unsigned(3 downto 0);
data_in : in unsigned(3 downto 0);
data_out : out unsigned(3 downto 0));
end component RightShift;
for uut : RightShift use entity work.RightShift(Behavioural);
signal c_in : unsigned(3 downto 0) := "0000";
signal c_out : unsigned(3 downto 0) := "0000";
signal data_in : unsigned(3 downto 0) := "0000";
signal data_out : unsigned(3 downto 0) := "0000";
begin
-- Unit under test
uut : RightShift
port map(c_in => c_in,
c_out => c_out,
data_in => data_in,
data_out => data_out);
test : process
begin
wait_for_sim_setup;
c_in <= "0011";
wait for 10 ns;
assert_equal(c_out, "0011");
c_in <= "0001";
data_in <= "0001";
wait for 10 ns;
assert_equal(data_out, "0000");
c_in <= "0001";
data_in <= "0010";
wait for 10 ns;
assert_equal(data_out, "0001");
c_in <= "0100";
data_in <= "0010";
wait for 10 ns;
assert_equal(data_out, "0010");
report "Test complete";
wait;
end process;
end architecture TB; |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ec_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ec_e-e.vhd,v 1.1 2004/04/06 10:50:27 wig Exp $
-- $Date: 2004/04/06 10:50:27 $
-- $Log: inst_ec_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:27 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ec_e
--
entity inst_ec_e is
-- Generics:
-- No Generated Generics for Entity inst_ec_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ec_e
p_mix_nreset_gi : in std_ulogic;
p_mix_nreset_s_gi : in std_ulogic;
p_mix_v_select_5_0_gi : in std_ulogic_vector(5 downto 0);
tpm_scani : in std_ulogic_vector(12 downto 0);
tpm_scano : out std_ulogic_vector(12 downto 0)
-- End of Generated Port for Entity inst_ec_e
);
end inst_ec_e;
--
-- End of Generated Entity inst_ec_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: avnet:zedboard:zed_hdmi_out:2.0
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.zed_hdmi_out;
ENTITY tutorial_zed_hdmi_out_0_0 IS
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
audio_spdif : IN STD_LOGIC;
video_vsync : IN STD_LOGIC;
video_hsync : IN STD_LOGIC;
video_de : IN STD_LOGIC;
video_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_spdif : OUT STD_LOGIC;
io_hdmio_video : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_vsync : OUT STD_LOGIC;
io_hdmio_hsync : OUT STD_LOGIC;
io_hdmio_de : OUT STD_LOGIC;
io_hdmio_clk : OUT STD_LOGIC
);
END tutorial_zed_hdmi_out_0_0;
ARCHITECTURE tutorial_zed_hdmi_out_0_0_arch OF tutorial_zed_hdmi_out_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_zed_hdmi_out_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_hdmi_out IS
GENERIC (
C_DATA_WIDTH : INTEGER; -- Video Data Width
C_FAMILY : STRING
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
audio_spdif : IN STD_LOGIC;
video_vsync : IN STD_LOGIC;
video_hsync : IN STD_LOGIC;
video_de : IN STD_LOGIC;
video_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_spdif : OUT STD_LOGIC;
io_hdmio_video : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
io_hdmio_vsync : OUT STD_LOGIC;
io_hdmio_hsync : OUT STD_LOGIC;
io_hdmio_de : OUT STD_LOGIC;
io_hdmio_clk : OUT STD_LOGIC
);
END COMPONENT zed_hdmi_out;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF video_vsync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF video_hsync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF video_de: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF video_data: SIGNAL IS "xilinx.com:interface:vid_io:1.0 VID_IO_IN DATA";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_spdif: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO SPDIF";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_video: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO DATA";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_vsync: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_hsync: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_de: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO DE";
ATTRIBUTE X_INTERFACE_INFO OF io_hdmio_clk: SIGNAL IS "avnet.com:interface:avnet_hdmi:1.0 IO_HDMIO CLK";
BEGIN
U0 : zed_hdmi_out
GENERIC MAP (
C_DATA_WIDTH => 16,
C_FAMILY => "zynq"
)
PORT MAP (
clk => clk,
reset => reset,
audio_spdif => audio_spdif,
video_vsync => video_vsync,
video_hsync => video_hsync,
video_de => video_de,
video_data => video_data,
io_hdmio_spdif => io_hdmio_spdif,
io_hdmio_video => io_hdmio_video,
io_hdmio_vsync => io_hdmio_vsync,
io_hdmio_hsync => io_hdmio_hsync,
io_hdmio_de => io_hdmio_de,
io_hdmio_clk => io_hdmio_clk
);
END tutorial_zed_hdmi_out_0_0_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "10.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll1: label is CLKIN_PERIOD_ST;
attribute CLKIN_PERIOD of dll2: label is CLKIN_PERIOD_ST;
signal clk_l, clk_m, clk_n, clk_o : std_logic;
signal dll0lock, dll1lock, dll2lock : std_logic;
signal dllrst : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk_fb)
begin -- process
if rising_edge(vgaclk_fb) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25_fb when clksel(1) = '0' else lclk40_65;
lclk40_65 <= lclk40 when clksel(0) = '0' else lclk65;
bufg01 : BUFG port map (I => clk40_fb, O => lclk40);
bufg02 : BUFG port map (I => clk65_fb, O => lclk65);
dllrst <= not rstn;
-- Generate clocks
clkdiv : process(clk_m, rstn)
begin
if (rstn and dll1lock) = '0' then clkval <= "00";
elsif rising_edge(clk_m) then
clkval <= clkval + 1;
end if;
end process;
clk25 <= clkval(1);
dll0lock <= '1';
bufg03 : BUFG port map (I => clk_l, O => clk_m);
dll1 : DCM
generic map (CLKFX_MULTIPLY => 4, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_m, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_l,
CLKFX => clk40, LOCKED => dll1lock);
bufg04 : BUFG port map (I => clk_n, O => clk_o);
dll2 : DCM
generic map (CLKFX_MULTIPLY => 13, CLKFX_DIVIDE => 20,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_o, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_n,
CLKFX => clk65, LOCKED => dll2lock);
locked <= dll0lock and dll1lock and dll2lock;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "10.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll1: label is CLKIN_PERIOD_ST;
attribute CLKIN_PERIOD of dll2: label is CLKIN_PERIOD_ST;
signal clk_l, clk_m, clk_n, clk_o : std_logic;
signal dll0lock, dll1lock, dll2lock : std_logic;
signal dllrst : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk_fb)
begin -- process
if rising_edge(vgaclk_fb) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25_fb when clksel(1) = '0' else lclk40_65;
lclk40_65 <= lclk40 when clksel(0) = '0' else lclk65;
bufg01 : BUFG port map (I => clk40_fb, O => lclk40);
bufg02 : BUFG port map (I => clk65_fb, O => lclk65);
dllrst <= not rstn;
-- Generate clocks
clkdiv : process(clk_m, rstn)
begin
if (rstn and dll1lock) = '0' then clkval <= "00";
elsif rising_edge(clk_m) then
clkval <= clkval + 1;
end if;
end process;
clk25 <= clkval(1);
dll0lock <= '1';
bufg03 : BUFG port map (I => clk_l, O => clk_m);
dll1 : DCM
generic map (CLKFX_MULTIPLY => 4, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_m, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_l,
CLKFX => clk40, LOCKED => dll1lock);
bufg04 : BUFG port map (I => clk_n, O => clk_o);
dll2 : DCM
generic map (CLKFX_MULTIPLY => 13, CLKFX_DIVIDE => 20,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_o, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_n,
CLKFX => clk65, LOCKED => dll2lock);
locked <= dll0lock and dll1lock and dll2lock;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
constant VERSION : integer := 1;
constant CLKIN_PERIOD_ST : string := "10.0";
attribute CLKIN_PERIOD : string;
attribute CLKIN_PERIOD of dll1: label is CLKIN_PERIOD_ST;
attribute CLKIN_PERIOD of dll2: label is CLKIN_PERIOD_ST;
signal clk_l, clk_m, clk_n, clk_o : std_logic;
signal dll0lock, dll1lock, dll2lock : std_logic;
signal dllrst : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk_fb)
begin -- process
if rising_edge(vgaclk_fb) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk_fb, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25_fb when clksel(1) = '0' else lclk40_65;
lclk40_65 <= lclk40 when clksel(0) = '0' else lclk65;
bufg01 : BUFG port map (I => clk40_fb, O => lclk40);
bufg02 : BUFG port map (I => clk65_fb, O => lclk65);
dllrst <= not rstn;
-- Generate clocks
clkdiv : process(clk_m, rstn)
begin
if (rstn and dll1lock) = '0' then clkval <= "00";
elsif rising_edge(clk_m) then
clkval <= clkval + 1;
end if;
end process;
clk25 <= clkval(1);
dll0lock <= '1';
bufg03 : BUFG port map (I => clk_l, O => clk_m);
dll1 : DCM
generic map (CLKFX_MULTIPLY => 4, CLKFX_DIVIDE => 10,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_m, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_l,
CLKFX => clk40, LOCKED => dll1lock);
bufg04 : BUFG port map (I => clk_n, O => clk_o);
dll2 : DCM
generic map (CLKFX_MULTIPLY => 13, CLKFX_DIVIDE => 20,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map ( CLKIN => clk, CLKFB => clk_o, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst, CLK0 => clk_n,
CLKFX => clk65, LOCKED => dll2lock);
locked <= dll0lock and dll1lock and dll2lock;
end rtl;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: tb_elem-minimal-c.vhd,v 1.1 2005-02-08 21:09:20 arniml Exp $
--
-------------------------------------------------------------------------------
configuration tb_elem_behav_minimal of tb_elem is
for behav
for dut_b : chip
use configuration work.chip_minimal_c0;
end for;
for card_b : card
use configuration work.card_behav_c0;
end for;
end for;
end tb_elem_behav_minimal;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1695.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01695ent IS
END c09s02b00x00p03n01i01695ent;
ARCHITECTURE c09s02b00x00p03n01i01695arch OF c09s02b00x00p03n01i01695ent IS
BEGIN
TEST_PROCESS: process
-- Illegal Disconnection specification. ERROR:
disconnect all : BIT after 0 ns;
begin
end process TEST_PROCESS;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01695 - Disconnection specifications may not be declared inside a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01695arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1695.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01695ent IS
END c09s02b00x00p03n01i01695ent;
ARCHITECTURE c09s02b00x00p03n01i01695arch OF c09s02b00x00p03n01i01695ent IS
BEGIN
TEST_PROCESS: process
-- Illegal Disconnection specification. ERROR:
disconnect all : BIT after 0 ns;
begin
end process TEST_PROCESS;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01695 - Disconnection specifications may not be declared inside a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01695arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1695.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01695ent IS
END c09s02b00x00p03n01i01695ent;
ARCHITECTURE c09s02b00x00p03n01i01695arch OF c09s02b00x00p03n01i01695ent IS
BEGIN
TEST_PROCESS: process
-- Illegal Disconnection specification. ERROR:
disconnect all : BIT after 0 ns;
begin
end process TEST_PROCESS;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01695 - Disconnection specifications may not be declared inside a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01695arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc127.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x01p04n01i00127ent IS
generic ( signal c1 : in integer ) ; -- Failure_here
-- signal declaration
-- not allowed
END c04s03b02x01p04n01i00127ent;
ARCHITECTURE c04s03b02x01p04n01i00127arch OF c04s03b02x01p04n01i00127ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x01p04n01i00127 - Only constant declarations allowed in generic interface list."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x01p04n01i00127arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc127.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x01p04n01i00127ent IS
generic ( signal c1 : in integer ) ; -- Failure_here
-- signal declaration
-- not allowed
END c04s03b02x01p04n01i00127ent;
ARCHITECTURE c04s03b02x01p04n01i00127arch OF c04s03b02x01p04n01i00127ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x01p04n01i00127 - Only constant declarations allowed in generic interface list."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x01p04n01i00127arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc127.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x01p04n01i00127ent IS
generic ( signal c1 : in integer ) ; -- Failure_here
-- signal declaration
-- not allowed
END c04s03b02x01p04n01i00127ent;
ARCHITECTURE c04s03b02x01p04n01i00127arch OF c04s03b02x01p04n01i00127ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x01p04n01i00127 - Only constant declarations allowed in generic interface list."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x01p04n01i00127arch;
|
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes.
use work.std_logic_1164_for_tst.all;
entity ENT00010_Test_Bench is
end ENT00010_Test_Bench;
architecture ARCH00010_Test_Bench of ENT00010_Test_Bench is
type std_array_array is array (0 to 3, 1 to 4) of std_ulogic;
signal I_saa : std_array_array := (others => x"B");
subtype byte is bit_vector(7 downto 0);
subtype byte2 is bit_vector(0 to 7);
signal b1 : byte := x"00";
signal b2 : byte2 := x"00";
type bit_array_array is array (0 to 3, 4 downto 1) of bit;
signal I_baa : bit_array_array := (others => x"A");
type NatArray is array (natural range <>) of natural;
type std_array is array (0 to 7) of std_logic;
signal I_sa : std_array := "10101010";
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type enum_array is array (integer range <>) of enum;
type rec is record
f1 : integer;
f2 : boolean;
f3 : bit;
f4 : enum;
f5 : enum_array(0 to 3);
f6 : NatArray(7 downto 0);
f7 : bit_vector(7 downto 0);
end record;
type rec_array is array (integer range <>) of rec;
signal e : enum := a_v;
signal ea : enum_array(0 to 3) := (others => a_v);
signal r : rec := (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
);
signal ra : rec_array(0 to 3) := (others => (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
)
);
signal bv : bit_vector(15 downto 0) := x"CCCC";
signal clk : std_ulogic := '0';
signal clk2 : std_ulogic := '0';
type BoolVector is array (integer range <>) of boolean;
signal bool : BoolVector(1 to 60);
begin
bool(1) <= bv'Stable(20 ns);
bool(2) <= ra'Stable(20 ns);
bool(3) <= r'Stable(20 ns);
bool(4) <= ea'Stable(20 ns);
bool(5) <= e'Stable(20 ns);
bool(6) <= I_sa'Stable(20 ns);
bool(7) <= I_baa'Stable(20 ns);
bool(8) <= I_saa'Stable(20 ns);
bool(9) <= b1'Stable(20 ns);
bool(10) <= b2'Stable(20 ns);
bool(11) <= clk'Stable(20 ns);
bool(12) <= clk2'Stable(20 ns);
clk <= not clk after 1 us;
clk2 <= not clk2 after 3 us;
process (clk)
begin
if clk'event and clk = '1' then
b1 <= b1(6 downto 0) & not b1(7);
case e is
when a_v => e <= b_v;
when b_v => e <= c_v;
when c_v => e <= d_v;
when d_v => e <= e_v;
when e_v => e <= f_v;
when f_v => e <= a_v;
end case;
ea(0) <= e;
ea_loop: for i in 1 to ea'length-1 loop
ea(i) <= ea(i-1);
end loop ea_loop;
elsif falling_edge(clk) then
bv <= bv(bv'left-1 downto bv'low) & bv(bv'high);
r.f1 <= r.f1 + 1;
r.f2 <= not r.f2;
r.f3 <= not r.f3;
r.f4 <= e;
r.f5 <= ea;
r_f6_loop: for i in r.f6'low to r.f6'high loop
r.f6(i) <= r.f6(i) + 1;
end loop r_f6_loop;
r.f7 <= r.f7(6 downto 0) & r.f7(7);
ra(ra'high) <= r;
ra_loop: for i in ra'high-1 downto 0 loop
ra(i) <= ra(i+1);
end loop;
end if;
end process;
process (clk2)
begin
if rising_edge(clk2) then
I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2);
elsif clk2'event and clk2 = '0' then
I_saa_loop_1: for i in 0 to 3 loop
I_saa_loop_2: for j in 1 to 4 loop
I_saa(i,j) <= I_sa(i+j);
end loop I_saa_loop_2;
end loop I_saa_loop_1;
I_baa_loop_1: for i in 0 to 3 loop
I_baa_loop_2: for j in 1 to 4 loop
I_baa(i,j) <= bv(i*j);
end loop I_baa_loop_2;
end loop I_baa_loop_1;
end if;
end process;
end ARCH00010_Test_Bench ; |
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF2_4_block6.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block6
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block6 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_15 : IN std_logic; -- ufix1
dout_14_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_15_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_15_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_16_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block6;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block6 IS
-- Signals
SIGNAL dout_14_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_14_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_16_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_16_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_15_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_15_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_16_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_16_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
dout_14_re_signed <= signed(dout_14_re);
dout_14_im_signed <= signed(dout_14_im);
dout_16_re_signed <= signed(dout_16_re);
dout_16_im_signed <= signed(dout_16_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_14_re_signed, dout_14_im_signed,
dout_16_re_signed, dout_16_im_signed, dout_1_vld, rotate_15)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE add_cast_3 : signed(16 DOWNTO 0);
VARIABLE add_cast_4 : signed(16 DOWNTO 0);
VARIABLE add_cast_5 : signed(16 DOWNTO 0);
VARIABLE add_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_3 : signed(16 DOWNTO 0);
VARIABLE sub_cast_4 : signed(16 DOWNTO 0);
VARIABLE sub_cast_5 : signed(16 DOWNTO 0);
VARIABLE sub_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_15 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(dout_14_re_signed, 17);
add_cast_2 := resize(dout_16_im_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(dout_14_re_signed, 17);
sub_cast_2 := resize(dout_16_im_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(dout_14_im_signed, 17);
add_cast_6 := resize(dout_16_re_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(dout_14_im_signed, 17);
sub_cast_6 := resize(dout_16_re_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(dout_14_re_signed, 17);
add_cast_0 := resize(dout_16_re_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(dout_14_re_signed, 17);
sub_cast_0 := resize(dout_16_re_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(dout_14_im_signed, 17);
add_cast_4 := resize(dout_16_im_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(dout_14_im_signed, 17);
sub_cast_4 := resize(dout_16_im_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_15_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_15_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_16_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_16_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_15_re <= std_logic_vector(dout_15_re_tmp);
dout_15_im <= std_logic_vector(dout_15_im_tmp);
dout_16_re_1 <= std_logic_vector(dout_16_re_tmp);
dout_16_im_1 <= std_logic_vector(dout_16_im_tmp);
END rtl;
|
-------------------------------------------------------------------------------
-- Title : HDLC async Encoder
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Decode 8-Bit HDLC Async framing int 8-Bit Data + Frame Delimiter
--
-- Frame-seperator is encoded as 0x100.
--
-- 0x00 to 0x7C -> 0x000 to 0x007C
-- 0x7f to 0xff -> 0x07f to 0x0ff
-- 0x7e -> 0x1XX
-- 0x7D, 0x5E -> 0x07E
-- 0x7D, 0x5D -> 0x07D
--
-- Input port can't take in data while it outputs an escape sequence!
-- TODO add a busy signal for the input.
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.hdlc_pkg.all;
-------------------------------------------------------------------------------
entity hdlc_dec is
port (
din_p : in hdlc_dec_in_type;
dout_p : out hdlc_dec_out_type;
clk : in std_logic);
end hdlc_dec;
-------------------------------------------------------------------------------
architecture behavioural of hdlc_dec is
type hdlc_dec_state_type is (
NOM, -- previous char was nominal
ESC -- previous char was an escape
);
type hdlc_dec_type is record
state : hdlc_dec_state_type;
strobe : std_logic;
dout : std_logic_vector(8 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : hdlc_dec_type := (state => NOM, strobe => '0', dout => (others => '0'));
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
dout_p.data <= r.dout;
dout_p.enable <= r.strobe;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(din_p, r)
variable v : hdlc_dec_type;
begin
v := r;
v.strobe := '0';
case r.state is
when NOM =>
if din_p.enable = '1' then
if din_p.data = x"7e" then
v.dout := "1" & x"00";
v.strobe := '1';
elsif din_p.data = x"7d" then
v.state := ESC;
else
v.dout := "0" & din_p.data;
v.strobe := '1';
end if;
end if;
when ESC =>
if din_p.enable = '1' then
v.dout := "0" & din_p.data(7 downto 6) & not din_p.data(5) & din_p.data(4 downto 0);
v.strobe := '1';
v.state := NOM;
end if;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
|
-------------------------------------------------------------------------------
-- Title : HDLC async Encoder
-------------------------------------------------------------------------------
-- Author : Carl Treudler ([email protected])
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Decode 8-Bit HDLC Async framing int 8-Bit Data + Frame Delimiter
--
-- Frame-seperator is encoded as 0x100.
--
-- 0x00 to 0x7C -> 0x000 to 0x007C
-- 0x7f to 0xff -> 0x07f to 0x0ff
-- 0x7e -> 0x1XX
-- 0x7D, 0x5E -> 0x07E
-- 0x7D, 0x5D -> 0x07D
--
-- Input port can't take in data while it outputs an escape sequence!
-- TODO add a busy signal for the input.
-------------------------------------------------------------------------------
-- Copyright (c) 2013, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.hdlc_pkg.all;
-------------------------------------------------------------------------------
entity hdlc_dec is
port (
din_p : in hdlc_dec_in_type;
dout_p : out hdlc_dec_out_type;
clk : in std_logic);
end hdlc_dec;
-------------------------------------------------------------------------------
architecture behavioural of hdlc_dec is
type hdlc_dec_state_type is (
NOM, -- previous char was nominal
ESC -- previous char was an escape
);
type hdlc_dec_type is record
state : hdlc_dec_state_type;
strobe : std_logic;
dout : std_logic_vector(8 downto 0);
end record;
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal r, rin : hdlc_dec_type := (state => NOM, strobe => '0', dout => (others => '0'));
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-- None here. If any: in package
begin -- architecture behavourial
----------------------------------------------------------------------------
-- Connections between ports and signals
----------------------------------------------------------------------------
dout_p.data <= r.dout;
dout_p.enable <= r.strobe;
----------------------------------------------------------------------------
-- Sequential part of finite state machine (FSM)
----------------------------------------------------------------------------
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
----------------------------------------------------------------------------
-- Combinatorial part of FSM
----------------------------------------------------------------------------
comb_proc : process(din_p, r)
variable v : hdlc_dec_type;
begin
v := r;
v.strobe := '0';
case r.state is
when NOM =>
if din_p.enable = '1' then
if din_p.data = x"7e" then
v.dout := "1" & x"00";
v.strobe := '1';
elsif din_p.data = x"7d" then
v.state := ESC;
else
v.dout := "0" & din_p.data;
v.strobe := '1';
end if;
end if;
when ESC =>
if din_p.enable = '1' then
v.dout := "0" & din_p.data(7 downto 6) & not din_p.data(5) & din_p.data(4 downto 0);
v.strobe := '1';
v.state := NOM;
end if;
end case;
rin <= v;
end process comb_proc;
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
-- None.
end behavioural;
|
library ieee;
use ieee.std_logic_1164.all;
entity targ02 is
port (o0, o1, o2 : out std_logic);
end targ02;
architecture behav of targ02 is
begin
(o2, o1, o0) <= std_logic_vector'("001");
end behav;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:52:57 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_to_uint_0_1/affine_block_ieee754_fp_to_uint_0_1_stub.vhdl
-- Design : affine_block_ieee754_fp_to_uint_0_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity affine_block_ieee754_fp_to_uint_0_1 is
Port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end affine_block_ieee754_fp_to_uint_0_1;
architecture stub of affine_block_ieee754_fp_to_uint_0_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "x[31:0],y[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ieee754_fp_to_uint,Vivado 2016.4";
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2369.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b01x00p06n02i02369ent IS
END c07s03b01x00p06n02i02369ent;
ARCHITECTURE c07s03b01x00p06n02i02369arch OF c07s03b01x00p06n02i02369ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( bit_vector'(O"4777") = B"100_111_111_111" )
report "***PASSED TEST: c07s03b01x00p06n02i02369"
severity NOTE;
assert ( bit_vector'(O"4777") = B"100_111_111_111" )
report "***FAILED TEST: c07s03b01x00p06n02i02369 - The type of the literal is determinable from the context in which it appears."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b01x00p06n02i02369arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2369.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b01x00p06n02i02369ent IS
END c07s03b01x00p06n02i02369ent;
ARCHITECTURE c07s03b01x00p06n02i02369arch OF c07s03b01x00p06n02i02369ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( bit_vector'(O"4777") = B"100_111_111_111" )
report "***PASSED TEST: c07s03b01x00p06n02i02369"
severity NOTE;
assert ( bit_vector'(O"4777") = B"100_111_111_111" )
report "***FAILED TEST: c07s03b01x00p06n02i02369 - The type of the literal is determinable from the context in which it appears."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b01x00p06n02i02369arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2369.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b01x00p06n02i02369ent IS
END c07s03b01x00p06n02i02369ent;
ARCHITECTURE c07s03b01x00p06n02i02369arch OF c07s03b01x00p06n02i02369ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( bit_vector'(O"4777") = B"100_111_111_111" )
report "***PASSED TEST: c07s03b01x00p06n02i02369"
severity NOTE;
assert ( bit_vector'(O"4777") = B"100_111_111_111" )
report "***FAILED TEST: c07s03b01x00p06n02i02369 - The type of the literal is determinable from the context in which it appears."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b01x00p06n02i02369arch;
|
-------------------------------------------------------------------------------
-- $Id: or_bits.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Or_bits
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_bits.vhd
--
-- Description: This file is used to OR together consecutive bits within
-- sections of a bus.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/06/01 -- First version
--
-- ALS 05/18/01
-- ^^^^^^
-- Added use of carry chain muxes if number of bits is > 4
-- ~~~~~~
-- BLT 05/23/01
-- ^^^^^^
-- Removed pad_4 function, replaced with arithmetic expression
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
-- C_START_BIT -- starting bit location of bits to OR
-- C_BUS_SIZE -- total size of the bus
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- input Sig -- another signal not in the bus to be ORd with the
-- -- bus section
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
entity or_bits is
generic (
C_NUM_BITS : integer := 8;
C_START_BIT : integer := 0;
C_BUS_SIZE : integer := 8);
port (
In_bus : in std_logic_vector(0 to C_BUS_SIZE-1);
Sig : in std_logic;
Or_out : out std_logic
);
end or_bits;
architecture implementation of or_bits is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- define output of OR chain
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
begin
-- If the number of bits to OR is 4 or less (including Sig), a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 4 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= Sig or In_bus(C_START_BIT);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(C_START_BIT + i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more (including Sig), then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 4 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(C_START_BIT to C_START_BIT+C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
--CI => '0' , --[in]
CI => Sig , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.12.2015 15:39:44
-- Design Name:
-- Module Name: topmodule - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity topmodule is
Port (
clk : IN STD_LOGIC;
SCL1 : INOUT STD_LOGIC;
SDA1 : INOUT STD_LOGIC;
SCL2 : INOUT STD_LOGIC;
SDA2 : INOUT STD_LOGIC;
SCL3 : INOUT STD_LOGIC;
SDA3 : INOUT STD_LOGIC;
SCL4 : INOUT STD_LOGIC;
SDA4 : INOUT STD_LOGIC;
SCL5 : INOUT STD_LOGIC;
SDA5 : INOUT STD_LOGIC;
SCL6 : INOUT STD_LOGIC;
SDA6 : INOUT STD_LOGIC;
SCL7 : INOUT STD_LOGIC;
SDA7 : INOUT STD_LOGIC;
SCL8 : INOUT STD_LOGIC;
SDA8 : INOUT STD_LOGIC;
SCL9 : INOUT STD_LOGIC;
SDA9 : INOUT STD_LOGIC;
SCL10 : INOUT STD_LOGIC;
SDA10 : INOUT STD_LOGIC;
--RsRx : IN STD_LOGIC;
RsTx : OUT STD_LOGIC;
--RsCts :
--RsRts :
btnCpuReset : IN STD_LOGIC
);
end topmodule;
architecture Behavioral of topmodule is
-- internal reset
signal resetin, reset, reset_n: std_logic;
-- serial to serialLoader signals
signal txd, ready, send: std_logic;
signal serialData: std_logic_vector (7 downto 0);
-- FIFO Signals serial loader to FIFO signals
signal Serial_FIFO_Empty, Serial_FIFO_Full, Serial_FIFO_ReadEn, Serial_FIFO_WriteEn: std_logic;
signal Serial_FIFO_DataOut, Serial_FIFO_DataIn: std_logic_vector (7 downto 0);
--SENSORS:
-- Global stuff
constant I2C_RW : std_logic := '1'; -- we will always be reading so we can set this constant
constant I2C_DELIMETER : std_logic_vector (7 downto 0):= "00000000"; -- the byte that will be between each reading.
constant I2C_ADDR : std_logic_vector (6 downto 0):= "0101000"; -- the address of the
--SENSOR1:
constant I2C1_Id : std_Logic_vector (7 downto 0) := "00000001"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C1_FIFO_Empty, I2C1_FIFO_Full, I2C1_FIFO_ReadEn, I2C1_FIFO_WriteEn: std_logic;
signal I2C1_FIFO_DataOut, I2C1_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C1_ENA,I2C1_RW,I2C1_BUSY,I2C1_ACK_ERROR : std_logic;
signal I2C1_DATA_RD : std_logic_vector (7 downto 0);
signal I2C1_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR2:
constant I2C2_Id : std_Logic_vector (7 downto 0) := "00000010"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C2_FIFO_Empty, I2C2_FIFO_Full, I2C2_FIFO_ReadEn, I2C2_FIFO_WriteEn: std_logic;
signal I2C2_FIFO_DataOut, I2C2_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C2_ENA,I2C2_RW,I2C2_BUSY,I2C2_ACK_ERROR : std_logic;
signal I2C2_DATA_RD : std_logic_vector (7 downto 0);
signal I2C2_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR3:
constant I2C3_Id : std_Logic_vector (7 downto 0) := "00000011"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C3_FIFO_Empty, I2C3_FIFO_Full, I2C3_FIFO_ReadEn, I2C3_FIFO_WriteEn: std_logic;
signal I2C3_FIFO_DataOut, I2C3_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C3_ENA,I2C3_RW,I2C3_BUSY,I2C3_ACK_ERROR : std_logic;
signal I2C3_DATA_RD : std_logic_vector (7 downto 0);
signal I2C3_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR4:
constant I2C4_Id : std_Logic_vector (7 downto 0) := "00000100"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C4_FIFO_Empty, I2C4_FIFO_Full, I2C4_FIFO_ReadEn, I2C4_FIFO_WriteEn: std_logic;
signal I2C4_FIFO_DataOut, I2C4_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C4_ENA,I2C4_RW,I2C4_BUSY,I2C4_ACK_ERROR : std_logic;
signal I2C4_DATA_RD : std_logic_vector (7 downto 0);
signal I2C4_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR5:
constant I2C5_Id : std_Logic_vector (7 downto 0) := "00000101"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C5_FIFO_Empty, I2C5_FIFO_Full, I2C5_FIFO_ReadEn, I2C5_FIFO_WriteEn: std_logic;
signal I2C5_FIFO_DataOut, I2C5_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C5_ENA,I2C5_RW,I2C5_BUSY,I2C5_ACK_ERROR : std_logic;
signal I2C5_DATA_RD : std_logic_vector (7 downto 0);
signal I2C5_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR6:
constant I2C6_Id : std_Logic_vector (7 downto 0) := "00000110"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C6_FIFO_Empty, I2C6_FIFO_Full, I2C6_FIFO_ReadEn, I2C6_FIFO_WriteEn: std_logic;
signal I2C6_FIFO_DataOut, I2C6_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C6_ENA,I2C6_RW,I2C6_BUSY,I2C6_ACK_ERROR : std_logic;
signal I2C6_DATA_RD : std_logic_vector (7 downto 0);
signal I2C6_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR7:
constant I2C7_Id : std_Logic_vector (7 downto 0) := "00000111"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C7_FIFO_Empty, I2C7_FIFO_Full, I2C7_FIFO_ReadEn, I2C7_FIFO_WriteEn: std_logic;
signal I2C7_FIFO_DataOut, I2C7_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C7_ENA,I2C7_RW,I2C7_BUSY,I2C7_ACK_ERROR : std_logic;
signal I2C7_DATA_RD : std_logic_vector (7 downto 0);
signal I2C7_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR8:
constant I2C8_Id : std_Logic_vector (7 downto 0) := "00001000"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C8_FIFO_Empty, I2C8_FIFO_Full, I2C8_FIFO_ReadEn, I2C8_FIFO_WriteEn: std_logic;
signal I2C8_FIFO_DataOut, I2C8_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C8_ENA,I2C8_RW,I2C8_BUSY,I2C8_ACK_ERROR : std_logic;
signal I2C8_DATA_RD : std_logic_vector (7 downto 0);
signal I2C8_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR9:
constant I2C9_Id : std_Logic_vector (7 downto 0) := "00001001"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C9_FIFO_Empty, I2C9_FIFO_Full, I2C9_FIFO_ReadEn, I2C9_FIFO_WriteEn: std_logic;
signal I2C9_FIFO_DataOut, I2C9_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C9_ENA,I2C9_RW,I2C9_BUSY,I2C9_ACK_ERROR : std_logic;
signal I2C9_DATA_RD : std_logic_vector (7 downto 0);
signal I2C9_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
--SENSOR10:
constant I2C10_Id : std_Logic_vector (7 downto 0) := "00001010"; -- id for this sensor
-- I2C Signals I2C loader to FIFO signals
signal I2C10_FIFO_Empty, I2C10_FIFO_Full, I2C10_FIFO_ReadEn, I2C10_FIFO_WriteEn: std_logic;
signal I2C10_FIFO_DataOut, I2C10_FIFO_DataIn: std_logic_vector (7 downto 0);
-- I2C control signals
signal I2C10_ENA,I2C10_RW,I2C10_BUSY,I2C10_ACK_ERROR : std_logic;
signal I2C10_DATA_RD : std_logic_vector (7 downto 0);
signal I2C10_DATA_WR : std_logic_vector (7 downto 0):= "00000000";
begin
--wire up the global reset
resetDebounce_unit: entity work.debouncer(Behavioral)
port map(
resetin => resetin,
resetout => reset,
resetout_n => reset_n
);
resetin <= btnCpuReset;
serial_unit: entity work.UART_TX_CTRL(Behavioral)
port map(
SEND => send,
DATA => serialData,
CLK => clk,
READY => ready,
UART_TX => txd
);
RsTx <= txd;
serialLoader_unit: entity work.serialLoader(Behavioral)
port map (
-- global clock
clk => clk,
reset => reset,
--serial control signals
S_Send => send,
S_DataOut => serialData,
S_Ready => ready,
--FIFO DATA
FIFO_Empty => Serial_FIFO_Empty,
FIFO_Data => Serial_FIFO_DataOut,
FIFO_ReadEn => Serial_FIFO_ReadEn
);
serialFIFObuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => Serial_FIFO_WriteEn,
DataIn => Serial_FIFO_DataIn,
ReadEn => Serial_FIFO_ReadEn,
DataOut => Serial_FIFO_DataOut,
Empty => Serial_FIFO_Empty,
Full => Serial_FIFO_Full
);
DataSequencer_unit: entity work.DataSequencer(Behavioral)
port map (
clk => clk,
reset => reset,
S_FIFO_WriteEn => Serial_FIFO_WriteEn,
S_FIFO_DataIn => Serial_FIFO_DataIn,
S_FIFO_Full => Serial_FIFO_Full,
I2C1_FIFO_ReadEn => I2C1_FIFO_ReadEn,
I2C1_FIFO_DataOut => I2C1_FIFO_DataOut,
I2C1_FIFO_Empty => I2C1_FIFO_Empty,
I2C2_FIFO_ReadEn => I2C2_FIFO_ReadEn,
I2C2_FIFO_DataOut => I2C2_FIFO_DataOut,
I2C2_FIFO_Empty => I2C2_FIFO_Empty,
I2C3_FIFO_ReadEn => I2C3_FIFO_ReadEn,
I2C3_FIFO_DataOut => I2C3_FIFO_DataOut,
I2C3_FIFO_Empty => I2C3_FIFO_Empty,
I2C4_FIFO_ReadEn => I2C4_FIFO_ReadEn,
I2C4_FIFO_DataOut => I2C4_FIFO_DataOut,
I2C4_FIFO_Empty => I2C4_FIFO_Empty,
I2C5_FIFO_ReadEn => I2C5_FIFO_ReadEn,
I2C5_FIFO_DataOut => I2C5_FIFO_DataOut,
I2C5_FIFO_Empty => I2C5_FIFO_Empty,
I2C6_FIFO_ReadEn => I2C6_FIFO_ReadEn,
I2C6_FIFO_DataOut => I2C6_FIFO_DataOut,
I2C6_FIFO_Empty => I2C6_FIFO_Empty,
I2C7_FIFO_ReadEn => I2C7_FIFO_ReadEn,
I2C7_FIFO_DataOut => I2C7_FIFO_DataOut,
I2C7_FIFO_Empty => I2C7_FIFO_Empty,
I2C8_FIFO_ReadEn => I2C8_FIFO_ReadEn,
I2C8_FIFO_DataOut => I2C8_FIFO_DataOut,
I2C8_FIFO_Empty => I2C8_FIFO_Empty,
I2C9_FIFO_ReadEn => I2C9_FIFO_ReadEn,
I2C9_FIFO_DataOut => I2C9_FIFO_DataOut,
I2C9_FIFO_Empty => I2C9_FIFO_Empty,
I2C10_FIFO_ReadEn => I2C10_FIFO_ReadEn,
I2C10_FIFO_DataOut => I2C10_FIFO_DataOut,
I2C10_FIFO_Empty => I2C10_FIFO_Empty
);
-- LOGIC FOR SENSORS:
--SENSOR1:
I2C1_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C1_FIFO_WriteEn,
DataIn => I2C1_FIFO_DataIn,
ReadEn => I2C1_FIFO_ReadEn,
DataOut => I2C1_FIFO_DataOut,
Empty => I2C1_FIFO_Empty,
Full => I2C1_FIFO_Full
);
I2C1_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C1_FIFO_WriteEn,
FIFO_DataIn => I2C1_FIFO_DataIn,
FIFO_Full => I2C1_FIFO_Full,
ena => I2C1_ENA,
busy => I2C1_BUSY,
data_rd => I2C1_DATA_RD,
ack_error => I2C1_ACK_ERROR,
sensorId => I2C1_Id,
delimeter => I2C_DELIMETER
);
I2C1_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C1_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C1_DATA_WR,
busy => I2C1_BUSY,
data_rd => I2C1_DATA_RD,
ack_error => I2C1_ACK_ERROR,
sda => SDA1,-- sda,
scl => SCL1 --scl
);
--SENSOR2:
I2C2_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C2_FIFO_WriteEn,
DataIn => I2C2_FIFO_DataIn,
ReadEn => I2C2_FIFO_ReadEn,
DataOut => I2C2_FIFO_DataOut,
Empty => I2C2_FIFO_Empty,
Full => I2C2_FIFO_Full
);
I2C2_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C2_FIFO_WriteEn,
FIFO_DataIn => I2C2_FIFO_DataIn,
FIFO_Full => I2C2_FIFO_Full,
ena => I2C2_ENA,
busy => I2C2_BUSY,
data_rd => I2C2_DATA_RD,
ack_error => I2C2_ACK_ERROR,
sensorId => I2C2_Id,
delimeter => I2C_DELIMETER
);
I2C2_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C2_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C2_DATA_WR,
busy => I2C2_BUSY,
data_rd => I2C2_DATA_RD,
ack_error => I2C2_ACK_ERROR,
sda => SDA2,-- sda,
scl => SCL2 --scl
);
--SENSOR3:
I2C3_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C3_FIFO_WriteEn,
DataIn => I2C3_FIFO_DataIn,
ReadEn => I2C3_FIFO_ReadEn,
DataOut => I2C3_FIFO_DataOut,
Empty => I2C3_FIFO_Empty,
Full => I2C3_FIFO_Full
);
I2C3_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C3_FIFO_WriteEn,
FIFO_DataIn => I2C3_FIFO_DataIn,
FIFO_Full => I2C3_FIFO_Full,
ena => I2C3_ENA,
busy => I2C3_BUSY,
data_rd => I2C3_DATA_RD,
ack_error => I2C3_ACK_ERROR,
sensorId => I2C3_Id,
delimeter => I2C_DELIMETER
);
I2C3_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C3_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C3_DATA_WR,
busy => I2C3_BUSY,
data_rd => I2C3_DATA_RD,
ack_error => I2C3_ACK_ERROR,
sda => SDA3,-- sda,
scl => SCL3 --scl
);
--SENSOR4:
I2C4_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C4_FIFO_WriteEn,
DataIn => I2C4_FIFO_DataIn,
ReadEn => I2C4_FIFO_ReadEn,
DataOut => I2C4_FIFO_DataOut,
Empty => I2C4_FIFO_Empty,
Full => I2C4_FIFO_Full
);
I2C4_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C4_FIFO_WriteEn,
FIFO_DataIn => I2C4_FIFO_DataIn,
FIFO_Full => I2C4_FIFO_Full,
ena => I2C4_ENA,
busy => I2C4_BUSY,
data_rd => I2C4_DATA_RD,
ack_error => I2C4_ACK_ERROR,
sensorId => I2C4_Id,
delimeter => I2C_DELIMETER
);
I2C4_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C4_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C4_DATA_WR,
busy => I2C4_BUSY,
data_rd => I2C4_DATA_RD,
ack_error => I2C4_ACK_ERROR,
sda => SDA4,-- sda,
scl => SCL4 --scl
);
--SENSOR5:
I2C5_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C5_FIFO_WriteEn,
DataIn => I2C5_FIFO_DataIn,
ReadEn => I2C5_FIFO_ReadEn,
DataOut => I2C5_FIFO_DataOut,
Empty => I2C5_FIFO_Empty,
Full => I2C5_FIFO_Full
);
I2C5_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C5_FIFO_WriteEn,
FIFO_DataIn => I2C5_FIFO_DataIn,
FIFO_Full => I2C5_FIFO_Full,
ena => I2C5_ENA,
busy => I2C5_BUSY,
data_rd => I2C5_DATA_RD,
ack_error => I2C5_ACK_ERROR,
sensorId => I2C5_Id,
delimeter => I2C_DELIMETER
);
I2C5_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C5_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C5_DATA_WR,
busy => I2C5_BUSY,
data_rd => I2C5_DATA_RD,
ack_error => I2C5_ACK_ERROR,
sda => SDA5,-- sda,
scl => SCL5 --scl
);
--SENSOR6:
I2C6_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C6_FIFO_WriteEn,
DataIn => I2C6_FIFO_DataIn,
ReadEn => I2C6_FIFO_ReadEn,
DataOut => I2C6_FIFO_DataOut,
Empty => I2C6_FIFO_Empty,
Full => I2C6_FIFO_Full
);
I2C6_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C6_FIFO_WriteEn,
FIFO_DataIn => I2C6_FIFO_DataIn,
FIFO_Full => I2C6_FIFO_Full,
ena => I2C6_ENA,
busy => I2C6_BUSY,
data_rd => I2C6_DATA_RD,
ack_error => I2C6_ACK_ERROR,
sensorId => I2C6_Id,
delimeter => I2C_DELIMETER
);
I2C6_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C6_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C6_DATA_WR,
busy => I2C6_BUSY,
data_rd => I2C6_DATA_RD,
ack_error => I2C6_ACK_ERROR,
sda => SDA6,-- sda,
scl => SCL6 --scl
);
--SENSOR7:
I2C7_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C7_FIFO_WriteEn,
DataIn => I2C7_FIFO_DataIn,
ReadEn => I2C7_FIFO_ReadEn,
DataOut => I2C7_FIFO_DataOut,
Empty => I2C7_FIFO_Empty,
Full => I2C7_FIFO_Full
);
I2C7_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C7_FIFO_WriteEn,
FIFO_DataIn => I2C7_FIFO_DataIn,
FIFO_Full => I2C7_FIFO_Full,
ena => I2C7_ENA,
busy => I2C7_BUSY,
data_rd => I2C7_DATA_RD,
ack_error => I2C7_ACK_ERROR,
sensorId => I2C7_Id,
delimeter => I2C_DELIMETER
);
I2C7_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C7_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C7_DATA_WR,
busy => I2C7_BUSY,
data_rd => I2C7_DATA_RD,
ack_error => I2C7_ACK_ERROR,
sda => SDA7,-- sda,
scl => SCL7 --scl
);
--SENSOR8:
I2C8_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C8_FIFO_WriteEn,
DataIn => I2C8_FIFO_DataIn,
ReadEn => I2C8_FIFO_ReadEn,
DataOut => I2C8_FIFO_DataOut,
Empty => I2C8_FIFO_Empty,
Full => I2C8_FIFO_Full
);
I2C8_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C8_FIFO_WriteEn,
FIFO_DataIn => I2C8_FIFO_DataIn,
FIFO_Full => I2C8_FIFO_Full,
ena => I2C8_ENA,
busy => I2C8_BUSY,
data_rd => I2C8_DATA_RD,
ack_error => I2C8_ACK_ERROR,
sensorId => I2C8_Id,
delimeter => I2C_DELIMETER
);
I2C8_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C8_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C8_DATA_WR,
busy => I2C8_BUSY,
data_rd => I2C8_DATA_RD,
ack_error => I2C8_ACK_ERROR,
sda => SDA8,-- sda,
scl => SCL8 --scl
);
--SENSOR9:
I2C9_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C9_FIFO_WriteEn,
DataIn => I2C9_FIFO_DataIn,
ReadEn => I2C9_FIFO_ReadEn,
DataOut => I2C9_FIFO_DataOut,
Empty => I2C9_FIFO_Empty,
Full => I2C9_FIFO_Full
);
I2C9_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C9_FIFO_WriteEn,
FIFO_DataIn => I2C9_FIFO_DataIn,
FIFO_Full => I2C9_FIFO_Full,
ena => I2C9_ENA,
busy => I2C9_BUSY,
data_rd => I2C9_DATA_RD,
ack_error => I2C9_ACK_ERROR,
sensorId => I2C9_Id,
delimeter => I2C_DELIMETER
);
I2C9_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C9_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C9_DATA_WR,
busy => I2C9_BUSY,
data_rd => I2C9_DATA_RD,
ack_error => I2C9_ACK_ERROR,
sda => SDA9,-- sda,
scl => SCL9 --scl
);
--SENSOR10:
I2C10_FIFOBuffer_unit: entity work.STD_FIFO(Behavioral)
port map (
CLK => clk,
RST => reset,
WriteEn => I2C10_FIFO_WriteEn,
DataIn => I2C10_FIFO_DataIn,
ReadEn => I2C10_FIFO_ReadEn,
DataOut => I2C10_FIFO_DataOut,
Empty => I2C10_FIFO_Empty,
Full => I2C10_FIFO_Full
);
I2C10_Control_unit: entity work.i2c_controller(Behavioral)
port map (
clk => clk,
reset_n => reset_n,
FIFO_WriteEn => I2C10_FIFO_WriteEn,
FIFO_DataIn => I2C10_FIFO_DataIn,
FIFO_Full => I2C10_FIFO_Full,
ena => I2C10_ENA,
busy => I2C10_BUSY,
data_rd => I2C10_DATA_RD,
ack_error => I2C10_ACK_ERROR,
sensorId => I2C10_Id,
delimeter => I2C_DELIMETER
);
I2C10_Comms_unit: entity work.i2c_master(logic)
port map (
clk => clk,
reset_n => reset_n,
ena => I2C10_ENA,
addr => I2C_ADDR,
rw => I2C_RW,
data_wr => I2C10_DATA_WR,
busy => I2C10_BUSY,
data_rd => I2C10_DATA_RD,
ack_error => I2C10_ACK_ERROR,
sda => SDA10,-- sda,
scl => SCL10 --scl
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_rx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle receipt of arp pkt
-- ignores other types of pkt
--
-- When it receives an ARP pkt that is either addressed to our IP or is a global request,
-- it outputs for a single clock cycle either recv_who_has or recv_I_have along
-- with associated mac or arp entry data.
--
-- Note that if recv who_has and we have it, then we also assert I_have so that we can cache the rev lookup
-- on the expectation that we will want to reply to this host.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created - refactored from arp v0.02 module
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arp_rx is
port (
-- MAC layer RX signals
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- ARP output signals
recv_who_has : out std_logic; -- pulse will be latched
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to)
recv_I_have : out std_logic; -- pulse will be latched
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg
-- control and status signals
req_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
-- system signals
our_ip_address : in std_logic_vector (31 downto 0);
rx_clk : in std_logic;
reset : in std_logic
);
end arp_rx;
architecture Behavioral of arp_rx is
type rx_state_t is (IDLE, PARSE, PROCESS_ARP, WAIT_END);
type rx_event_t is (NO_EVENT, DATA);
type count_mode_t is (RST, INCR, HOLD);
type arp_oper_t is (NOP, REQUEST, REPLY);
type tx_state_type is (IDLE, WAIT_MAC, SEND);
-- state variables
signal send_request_needed : std_logic;
signal tx_mac_chn_reqd : std_logic;
signal rx_state : rx_state_t;
signal rx_count : unsigned (7 downto 0);
signal arp_operation : arp_oper_t;
signal arp_req_count : unsigned (7 downto 0);
signal new_arp_entry : arp_entry_t;
-- FIXME - remove these debug state signals
signal arp_err_data : std_logic_vector (7 downto 0);
signal set_err_data : std_logic;
attribute keep : string;
attribute keep of arp_err_data : signal is "true";
-- rx control signals
signal next_rx_state : rx_state_t;
signal set_rx_state : std_logic;
signal rx_event : rx_event_t;
signal rx_count_mode : count_mode_t;
signal set_arp_oper : std_logic;
signal arp_oper_set_val : arp_oper_t;
signal dataval : std_logic_vector (7 downto 0);
signal count_arp_rcvd : std_logic;
signal set_mac5 : std_logic;
signal set_mac4 : std_logic;
signal set_mac3 : std_logic;
signal set_mac2 : std_logic;
signal set_mac1 : std_logic;
signal set_mac0 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
-- function to determine whether the rx pkt is an arp pkt and whether we want to process it
-- Returns 1 if we should discard
-- The following will make us ignore the frame (all values hexadecimal):
-- PDU type /= 0806
-- Protocol Type /= 0800
-- Hardware Type /= 1
-- Hardware Length /= 6
-- Protocol Length /= 4
-- Operation /= 1 or 2
-- Target IP /= our IP (i.er. message is not meant for us)
--
function not_our_arp(data : std_logic_vector; count : unsigned; our_ip : std_logic_vector) return std_logic is
begin
if
(count = 12 and data /= x"08") or -- PDU type 0806 : ARP
(count = 13 and data /= x"06") or
(count = 14 and data /= x"00") or -- HW type 1 : eth
(count = 15 and data /= x"01") or
(count = 16 and data /= x"08") or -- Protocol 0800 : IP
(count = 17 and data /= x"00") or
(count = 18 and data /= x"06") or -- HW Length 6
(count = 19 and data /= x"04") or -- protocol length 4
(count = 20 and data /= x"00") or -- operation 1 or 2 (req or reply)
(count = 21 and data /= x"01" and data /= x"02") or
(count = 38 and data /= our_ip(31 downto 24)) or -- target IP is ours
(count = 39 and data /= our_ip(23 downto 16)) or
(count = 40 and data /= our_ip(15 downto 8)) or
(count = 41 and data /= our_ip(7 downto 0))
then
return '1';
else
return '0';
end if;
end function not_our_arp;
begin
rx_combinatorial : process (
-- input signals
data_in, data_in_valid, data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, arp_operation, arp_req_count, arp_err_data, new_arp_entry,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, set_arp_oper, arp_oper_set_val,
dataval, set_mac5, set_mac4, set_mac3, set_mac2, set_mac1, set_mac0, set_ip3, set_ip2, set_ip1, set_ip0, set_err_data,
count_arp_rcvd
)
begin
-- set output followers
req_count <= std_logic_vector(arp_req_count);
-- set defaults for combinatorial outputs
recv_who_has <= '0';
arp_entry_for_who_has.ip <= (others => '0');
arp_entry_for_who_has.mac <= (others => '0');
recv_I_have <= '0';
arp_entry_for_I_have.ip <= (others => '0');
arp_entry_for_I_have.mac <= (others => '0');
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_arp_oper <= '0';
arp_oper_set_val <= NOP;
dataval <= (others => '0');
set_mac5 <= '0';
set_mac4 <= '0';
set_mac3 <= '0';
set_mac2 <= '0';
set_mac1 <= '0';
set_mac0 <= '0';
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
count_arp_rcvd <= '0';
set_err_data <= '0';
-- determine event (if any)
if data_in_valid = '1' then
rx_event <= DATA;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
next_rx_state <= PARSE;
set_rx_state <= '1';
rx_count_mode <= INCR;
end case;
when PARSE =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
-- handle early frame termination
if data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
--else
end if;
-- check for end of frame. Also, detect and discard if not our frame
if rx_count = 41 then -- TB 2013-01-14 15:09:45 was 42
next_rx_state <= PROCESS_ARP;
set_rx_state <= '1';
elsif not_our_arp(data_in, rx_count, our_ip_address) = '1' then
dataval <= data_in;
set_err_data <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
elsif rx_count = 21 then
-- capture ARP operation
case data_in is
when x"01" =>
arp_oper_set_val <= REQUEST;
set_arp_oper <= '1';
when x"02" =>
arp_oper_set_val <= REPLY;
set_arp_oper <= '1';
when others => -- ignore other values
end case;
-- capture source mac addr
elsif rx_count = 22 then
set_mac5 <= '1';
dataval <= data_in;
elsif rx_count = 23 then
set_mac4 <= '1';
dataval <= data_in;
elsif rx_count = 24 then
set_mac3 <= '1';
dataval <= data_in;
elsif rx_count = 25 then
set_mac2 <= '1';
dataval <= data_in;
elsif rx_count = 26 then
set_mac1 <= '1';
dataval <= data_in;
elsif rx_count = 27 then
set_mac0 <= '1';
dataval <= data_in;
-- capture source ip addr
elsif rx_count = 28 then
set_ip3 <= '1';
dataval <= data_in;
elsif rx_count = 29 then
set_ip2 <= '1';
dataval <= data_in;
elsif rx_count = 30 then
set_ip1 <= '1';
dataval <= data_in;
elsif rx_count = 31 then
set_ip0 <= '1';
dataval <= data_in;
end if;
-- end if;
end case;
when PROCESS_ARP =>
next_rx_state <= WAIT_END;
set_rx_state <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
case arp_operation is
when NOP => -- (nothing to do)
when REQUEST =>
count_arp_rcvd <= '1';
recv_who_has <= '1';
arp_entry_for_who_has <= new_arp_entry;
-- setting I_Have as well allows us to cache the remote node's entry immediately
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
when REPLY =>
count_arp_rcvd <= '1';
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
end case;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
rx_sequential : process (rx_clk)
begin
if rising_edge(rx_clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"00";
arp_operation <= NOP;
arp_req_count <= x"00";
arp_err_data <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST =>
rx_count <= x"00";
when INCR =>
rx_count <= rx_count + 1;
when HOLD =>
rx_count <= rx_count;
end case;
-- err data
if set_err_data = '1' then
arp_err_data <= data_in;
else
arp_err_data <= arp_err_data;
end if;
-- arp operation processing
if set_arp_oper = '1' then
arp_operation <= arp_oper_set_val;
else
arp_operation <= arp_operation;
end if;
-- source mac capture
if (set_mac5 = '1') then new_arp_entry.mac(47 downto 40) <= dataval; end if;
if (set_mac4 = '1') then new_arp_entry.mac(39 downto 32) <= dataval; end if;
if (set_mac3 = '1') then new_arp_entry.mac(31 downto 24) <= dataval; end if;
if (set_mac2 = '1') then new_arp_entry.mac(23 downto 16) <= dataval; end if;
if (set_mac1 = '1') then new_arp_entry.mac(15 downto 8) <= dataval; end if;
if (set_mac0 = '1') then new_arp_entry.mac(7 downto 0) <= dataval; end if;
-- source ip capture
if (set_ip3 = '1') then new_arp_entry.ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then new_arp_entry.ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if;
-- set arp entry request
if count_arp_rcvd = '1' then
-- count another ARP pkt received
arp_req_count <= arp_req_count + 1;
else
arp_req_count <= arp_req_count;
end if;
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 12:00:04 05/31/2011
-- Design Name:
-- Module Name: arp_rx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle receipt of arp pkt
-- ignores other types of pkt
--
-- When it receives an ARP pkt that is either addressed to our IP or is a global request,
-- it outputs for a single clock cycle either recv_who_has or recv_I_have along
-- with associated mac or arp entry data.
--
-- Note that if recv who_has and we have it, then we also assert I_have so that we can cache the rev lookup
-- on the expectation that we will want to reply to this host.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created - refactored from arp v0.02 module
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.arp_types.all;
entity arp_rx is
port (
-- MAC layer RX signals
data_in : in std_logic_vector (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
data_in_valid : in std_logic; -- indicates data_in valid on clock
data_in_last : in std_logic; -- indicates last data in frame
-- ARP output signals
recv_who_has : out std_logic; -- pulse will be latched
arp_entry_for_who_has : out arp_entry_t; -- target for who_has msg (Iie, who to reply to)
recv_I_have : out std_logic; -- pulse will be latched
arp_entry_for_I_have : out arp_entry_t; -- arp target for I_have msg
-- control and status signals
req_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
-- system signals
our_ip_address : in std_logic_vector (31 downto 0);
rx_clk : in std_logic;
reset : in std_logic
);
end arp_rx;
architecture Behavioral of arp_rx is
type rx_state_t is (IDLE, PARSE, PROCESS_ARP, WAIT_END);
type rx_event_t is (NO_EVENT, DATA);
type count_mode_t is (RST, INCR, HOLD);
type arp_oper_t is (NOP, REQUEST, REPLY);
type tx_state_type is (IDLE, WAIT_MAC, SEND);
-- state variables
signal send_request_needed : std_logic;
signal tx_mac_chn_reqd : std_logic;
signal rx_state : rx_state_t;
signal rx_count : unsigned (7 downto 0);
signal arp_operation : arp_oper_t;
signal arp_req_count : unsigned (7 downto 0);
signal new_arp_entry : arp_entry_t;
-- FIXME - remove these debug state signals
signal arp_err_data : std_logic_vector (7 downto 0);
signal set_err_data : std_logic;
attribute keep : string;
attribute keep of arp_err_data : signal is "true";
-- rx control signals
signal next_rx_state : rx_state_t;
signal set_rx_state : std_logic;
signal rx_event : rx_event_t;
signal rx_count_mode : count_mode_t;
signal set_arp_oper : std_logic;
signal arp_oper_set_val : arp_oper_t;
signal dataval : std_logic_vector (7 downto 0);
signal count_arp_rcvd : std_logic;
signal set_mac5 : std_logic;
signal set_mac4 : std_logic;
signal set_mac3 : std_logic;
signal set_mac2 : std_logic;
signal set_mac1 : std_logic;
signal set_mac0 : std_logic;
signal set_ip3 : std_logic;
signal set_ip2 : std_logic;
signal set_ip1 : std_logic;
signal set_ip0 : std_logic;
-- function to determine whether the rx pkt is an arp pkt and whether we want to process it
-- Returns 1 if we should discard
-- The following will make us ignore the frame (all values hexadecimal):
-- PDU type /= 0806
-- Protocol Type /= 0800
-- Hardware Type /= 1
-- Hardware Length /= 6
-- Protocol Length /= 4
-- Operation /= 1 or 2
-- Target IP /= our IP (i.er. message is not meant for us)
--
function not_our_arp(data : std_logic_vector; count : unsigned; our_ip : std_logic_vector) return std_logic is
begin
if
(count = 12 and data /= x"08") or -- PDU type 0806 : ARP
(count = 13 and data /= x"06") or
(count = 14 and data /= x"00") or -- HW type 1 : eth
(count = 15 and data /= x"01") or
(count = 16 and data /= x"08") or -- Protocol 0800 : IP
(count = 17 and data /= x"00") or
(count = 18 and data /= x"06") or -- HW Length 6
(count = 19 and data /= x"04") or -- protocol length 4
(count = 20 and data /= x"00") or -- operation 1 or 2 (req or reply)
(count = 21 and data /= x"01" and data /= x"02") or
(count = 38 and data /= our_ip(31 downto 24)) or -- target IP is ours
(count = 39 and data /= our_ip(23 downto 16)) or
(count = 40 and data /= our_ip(15 downto 8)) or
(count = 41 and data /= our_ip(7 downto 0))
then
return '1';
else
return '0';
end if;
end function not_our_arp;
begin
rx_combinatorial : process (
-- input signals
data_in, data_in_valid, data_in_last, our_ip_address,
-- state variables
rx_state, rx_count, arp_operation, arp_req_count, arp_err_data, new_arp_entry,
-- control signals
next_rx_state, set_rx_state, rx_event, rx_count_mode, set_arp_oper, arp_oper_set_val,
dataval, set_mac5, set_mac4, set_mac3, set_mac2, set_mac1, set_mac0, set_ip3, set_ip2, set_ip1, set_ip0, set_err_data,
count_arp_rcvd
)
begin
-- set output followers
req_count <= std_logic_vector(arp_req_count);
-- set defaults for combinatorial outputs
recv_who_has <= '0';
arp_entry_for_who_has.ip <= (others => '0');
arp_entry_for_who_has.mac <= (others => '0');
recv_I_have <= '0';
arp_entry_for_I_have.ip <= (others => '0');
arp_entry_for_I_have.mac <= (others => '0');
-- set signal defaults
next_rx_state <= IDLE;
set_rx_state <= '0';
rx_event <= NO_EVENT;
rx_count_mode <= HOLD;
set_arp_oper <= '0';
arp_oper_set_val <= NOP;
dataval <= (others => '0');
set_mac5 <= '0';
set_mac4 <= '0';
set_mac3 <= '0';
set_mac2 <= '0';
set_mac1 <= '0';
set_mac0 <= '0';
set_ip3 <= '0';
set_ip2 <= '0';
set_ip1 <= '0';
set_ip0 <= '0';
count_arp_rcvd <= '0';
set_err_data <= '0';
-- determine event (if any)
if data_in_valid = '1' then
rx_event <= DATA;
end if;
-- RX FSM
case rx_state is
when IDLE =>
rx_count_mode <= RST;
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
next_rx_state <= PARSE;
set_rx_state <= '1';
rx_count_mode <= INCR;
end case;
when PARSE =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
rx_count_mode <= INCR;
-- handle early frame termination
if data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
--else
end if;
-- check for end of frame. Also, detect and discard if not our frame
if rx_count = 41 then -- TB 2013-01-14 15:09:45 was 42
next_rx_state <= PROCESS_ARP;
set_rx_state <= '1';
elsif not_our_arp(data_in, rx_count, our_ip_address) = '1' then
dataval <= data_in;
set_err_data <= '1';
next_rx_state <= WAIT_END;
set_rx_state <= '1';
elsif rx_count = 21 then
-- capture ARP operation
case data_in is
when x"01" =>
arp_oper_set_val <= REQUEST;
set_arp_oper <= '1';
when x"02" =>
arp_oper_set_val <= REPLY;
set_arp_oper <= '1';
when others => -- ignore other values
end case;
-- capture source mac addr
elsif rx_count = 22 then
set_mac5 <= '1';
dataval <= data_in;
elsif rx_count = 23 then
set_mac4 <= '1';
dataval <= data_in;
elsif rx_count = 24 then
set_mac3 <= '1';
dataval <= data_in;
elsif rx_count = 25 then
set_mac2 <= '1';
dataval <= data_in;
elsif rx_count = 26 then
set_mac1 <= '1';
dataval <= data_in;
elsif rx_count = 27 then
set_mac0 <= '1';
dataval <= data_in;
-- capture source ip addr
elsif rx_count = 28 then
set_ip3 <= '1';
dataval <= data_in;
elsif rx_count = 29 then
set_ip2 <= '1';
dataval <= data_in;
elsif rx_count = 30 then
set_ip1 <= '1';
dataval <= data_in;
elsif rx_count = 31 then
set_ip0 <= '1';
dataval <= data_in;
end if;
-- end if;
end case;
when PROCESS_ARP =>
next_rx_state <= WAIT_END;
set_rx_state <= '1';
arp_oper_set_val <= NOP;
set_arp_oper <= '1';
case arp_operation is
when NOP => -- (nothing to do)
when REQUEST =>
count_arp_rcvd <= '1';
recv_who_has <= '1';
arp_entry_for_who_has <= new_arp_entry;
-- setting I_Have as well allows us to cache the remote node's entry immediately
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
when REPLY =>
count_arp_rcvd <= '1';
recv_I_have <= '1';
arp_entry_for_I_have <= new_arp_entry;
end case;
when WAIT_END =>
case rx_event is
when NO_EVENT => -- (nothing to do)
when DATA =>
if data_in_last = '1' then
next_rx_state <= IDLE;
rx_count_mode <= RST;
set_rx_state <= '1';
end if;
end case;
end case;
end process;
rx_sequential : process (rx_clk)
begin
if rising_edge(rx_clk) then
if reset = '1' then
-- reset state variables
rx_state <= IDLE;
rx_count <= x"00";
arp_operation <= NOP;
arp_req_count <= x"00";
arp_err_data <= (others => '0');
else
-- Next rx_state processing
if set_rx_state = '1' then
rx_state <= next_rx_state;
else
rx_state <= rx_state;
end if;
-- rx_count processing
case rx_count_mode is
when RST =>
rx_count <= x"00";
when INCR =>
rx_count <= rx_count + 1;
when HOLD =>
rx_count <= rx_count;
end case;
-- err data
if set_err_data = '1' then
arp_err_data <= data_in;
else
arp_err_data <= arp_err_data;
end if;
-- arp operation processing
if set_arp_oper = '1' then
arp_operation <= arp_oper_set_val;
else
arp_operation <= arp_operation;
end if;
-- source mac capture
if (set_mac5 = '1') then new_arp_entry.mac(47 downto 40) <= dataval; end if;
if (set_mac4 = '1') then new_arp_entry.mac(39 downto 32) <= dataval; end if;
if (set_mac3 = '1') then new_arp_entry.mac(31 downto 24) <= dataval; end if;
if (set_mac2 = '1') then new_arp_entry.mac(23 downto 16) <= dataval; end if;
if (set_mac1 = '1') then new_arp_entry.mac(15 downto 8) <= dataval; end if;
if (set_mac0 = '1') then new_arp_entry.mac(7 downto 0) <= dataval; end if;
-- source ip capture
if (set_ip3 = '1') then new_arp_entry.ip(31 downto 24) <= dataval; end if;
if (set_ip2 = '1') then new_arp_entry.ip(23 downto 16) <= dataval; end if;
if (set_ip1 = '1') then new_arp_entry.ip(15 downto 8) <= dataval; end if;
if (set_ip0 = '1') then new_arp_entry.ip(7 downto 0) <= dataval; end if;
-- set arp entry request
if count_arp_rcvd = '1' then
-- count another ARP pkt received
arp_req_count <= arp_req_count + 1;
else
arp_req_count <= arp_req_count;
end if;
end if;
end if;
end process;
end Behavioral;
|
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 246352)
`protect data_block
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`protect end_protected
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Ram_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY Ram_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE Ram_synth_ARCH OF Ram_synth IS
COMPONENT Ram_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 32,
READ_WIDTH => 32 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: Ram_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port (
a : in std_logic;
b : in std_logic;
ci : in std_logic;
s : out std_logic;
co : out std_logic);
end;
architecture behavioral of full_adder is
begin
s <= a xor b xor ci;
co <= (a and b) or ((a xor b) and ci);
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port (
a : in std_logic;
b : in std_logic;
ci : in std_logic;
s : out std_logic;
co : out std_logic);
end;
architecture behavioral of full_adder is
begin
s <= a xor b xor ci;
co <= (a and b) or ((a xor b) and ci);
end;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_189 is
port (
lt : out std_logic;
sign : in std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_189;
architecture augh of sub_189 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
lt <= not(tmp_ge);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_189 is
port (
lt : out std_logic;
sign : in std_logic;
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_189;
architecture augh of sub_189 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= carry_inA(32) & carry_inB(32) & carry_res(32);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" or msb_abr = "111" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "011") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011") else
'0';
lt <= not(tmp_ge);
end architecture;
|
------------------------------------------------------------------------------
-- {WRAPPERNAME}.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: {WRAPPERNAME}.vhd
-- Version: {VERSION}
-- Description: Top level design, instantiates library components and user logic.
-- Date: {DATE} (by PSHDL)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
library {DIRNAME};
use {DIRNAME}.{NAME};
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity {WRAPPERNAME} is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
{GENERICS}
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex5"
{MEM_GENERICS}
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
{PORTS}
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity {WRAPPERNAME};
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of {WRAPPERNAME} is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
{MEM_ARRAY}
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := {REGCOUNT};
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
{MEM_CES}
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity {DIRNAME}.{NAME}
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
{GENERICSMAP}
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
{PORTMAP}
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
{MEM_PORTMAP}
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6640)
`protect data_block
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1sePzFTPPgejhXUMJyN02CYtKVrBMetC0ws5JNHnMOkZWP5ZmuvBMG6OHsudUZKGuWSZwdPUSYor
bpceBc+hl+I6mFHtZ+O8x3icH5ES+H7xxzZZ5O1AV1DvaRB0qJlGk/dutcCcm5wKe5NmPWY14X+S
IlhAMINj6ag6O9Y6/Z/p7YbhPxqZR/7KYq8VarHLEHSRu0LqJHSYFA7s13hvDwcorEInrRb4cQOF
3iL0fr6mY75JMLiQRWHMqNi49Y5blYxrs3uR0WVeGLhNqmuGv7xbzH32rQNzQHb1kybkFpgswEvX
+HNftxR4mSLaQvCmvrv8MPU82RPfjPUXLdVhLtmix9Q4mYLxowPjCFgLjYAKm8it+BAlvuIZd9Vp
z8UFZW842k2NcKlaEIHsf2J6hB9s0P0bzqHfrv3rWg04iH3Uohca6Z9vHOLWen0stGYjK+6lNe4B
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UrPlL2nE1K2lNA6GzKzTIR5DZkJ+CwMyt1lSkGwYmtMNT0tB1ullknOd5O2rnL4TnO9BXZJhzmI5
ovQvRXyvX+7zOU3MygjK42hfUKl4txw/rRzghVsyXYT+uxtoL86zCFj9wLSBV+bCMbVAB+hcumdK
CjdakurRHOzI+aaukZYQhXqgZIoxH2LZ9mJzkg==
`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2785.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity BUFFER is
end BUFFER;
ENTITY c13s09b00x00p99n01i02785ent IS
END c13s09b00x00p99n01i02785ent;
ARCHITECTURE c13s09b00x00p99n01i02785arch OF c13s09b00x00p99n01i02785ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02785 - Reserved word BUFFER can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02785arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2785.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity BUFFER is
end BUFFER;
ENTITY c13s09b00x00p99n01i02785ent IS
END c13s09b00x00p99n01i02785ent;
ARCHITECTURE c13s09b00x00p99n01i02785arch OF c13s09b00x00p99n01i02785ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02785 - Reserved word BUFFER can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02785arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2785.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity BUFFER is
end BUFFER;
ENTITY c13s09b00x00p99n01i02785ent IS
END c13s09b00x00p99n01i02785ent;
ARCHITECTURE c13s09b00x00p99n01i02785arch OF c13s09b00x00p99n01i02785ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02785 - Reserved word BUFFER can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02785arch;
|
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Modified by : Champaka Ramachandran
--
-- Modified on : Sept 16, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran 16 Sept,92 ZYCAD
-- Functionality yes Champaka Ramachandran 16 Sept,92 ZYCAD
--------------------------------------------------------------------------------
use work.types.all;
use work.MVL7_functions.all; --some binary functions
use work.synthesis_types.all; --hints for synthesis
entity testbench is
end;
architecture A of testbench is
component AM2901
port (
I : in MVL7_vector(8 downto 0);
Aadd, Badd : in integer range 0 to 15;
D : in MVL7_vector(3 downto 0);
Y : out MVL7_vector(3 downto 0);
RAM0, RAM3, Q0, Q3 : in MVL7;
RAM0out, RAM3out, Q0out, Q3out : out MVL7;
CLK : in clock;
C0 : in MVL7;
OEbar : in MVL7;
C4, Gbar, Pbar, OVR, F3, F30 : out MVL7
);
end component;
signal I : MVL7_vector(8 downto 0);
signal Aadd, Badd : integer range 0 to 15;
signal D : MVL7_vector(3 downto 0);
signal Y : MVL7_vector(3 downto 0);
signal RAM0, RAM3, Q0, Q3 : MVL7;
signal RAM0out, RAM3out, Q0out, Q3out : MVL7;
signal CLK : clock;
signal C0 : MVL7;
signal OEbar : MVL7;
signal C4, Gbar, Pbar, OVR, F3, F30 : MVL7;
for all : AM2901 use entity work.a2901(a2901);
begin
AM1 : AM2901 port map(
I,
Aadd, Badd,
D,
Y,
RAM0, RAM3, Q0, Q3,
RAM0out, RAM3out, Q0out, Q3out,
CLK,
C0,
OEbar,
C4, Gbar, Pbar, OVR, F3, F30
);
process
begin
-- ************************
-- * *
-- * TEST VECTORS FOR ALU *
-- * *
-- ************************
-- ******** ADDITION R + S ********
--------------------------
clk <= '1'; -- Cycle No: 0
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 1
wait for 1 ns;
I <= "001000110";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 0 : < Y /= 0000 >" -- Vector No: 0
severity warning;
assert (C4 = '0')
report
"Assert 1 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 2 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '1')
report
"Assert 3 : < Pbar /= 1 >"
severity warning;
assert (OVR = '0')
report
"Assert 4 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 5 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 6 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 2
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 3
wait for 1 ns;
I <= "001000110";
D <= "0000";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0001")
report
"Assert 7 : < Y /= 0001 >" -- Vector No: 1
severity warning;
assert (C4 = '0')
report
"Assert 8 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 9 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '1')
report
"Assert 10 : < Pbar /= 1 >"
severity warning;
assert (OVR = '0')
report
"Assert 11 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 12 : < F3 /= 0 >"
severity warning;
assert (F30 = '0')
report
"Assert 13 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 4
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 5
wait for 1 ns;
I <= "001000110";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 14 : < Y /= 1111 >" -- Vector No: 2
severity warning;
assert (C4 = '0')
report
"Assert 15 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 16 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '0')
report
"Assert 17 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 18 : < OVR /= 0 >"
severity warning;
assert (F3 = '1')
report
"Assert 19 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 20 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 6
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 7
wait for 1 ns;
I <= "001000110";
D <= "0000";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 21 : < Y /= 0000 >" -- Vector No: 3
severity warning;
assert (C4 = '1')
report
"Assert 22 : < C4 /= 1 >"
severity warning;
assert (Gbar = '1')
report
"Assert 23 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '0')
report
"Assert 24 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 25 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 26 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 27 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 8
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 9
wait for 1 ns;
I <= "001000110";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1110")
report
"Assert 28 : < Y /= 1110 >" -- Vector No: 4
severity warning;
assert (C4 = '1')
report
"Assert 29 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 30 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '0')
report
"Assert 31 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 32 : < OVR /= 0 >"
severity warning;
assert (F3 = '1')
report
"Assert 33 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 34 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 10
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 11
wait for 1 ns;
I <= "001000110";
D <= "1111";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 35 : < Y /= 1111 >" -- Vector No: 5
severity warning;
assert (C4 = '1')
report
"Assert 36 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 37 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '0')
report
"Assert 38 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 39 : < OVR /= 0 >"
severity warning;
assert (F3 = '1')
report
"Assert 40 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 41 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 12
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 13
wait for 1 ns;
I <= "001000110";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 42 : < Y /= 1111 >" -- Vector No: 6
severity warning;
assert (C4 = '0')
report
"Assert 43 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 44 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '0')
report
"Assert 45 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 46 : < OVR /= 0 >"
severity warning;
assert (F3 = '1')
report
"Assert 47 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 48 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 14
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 15
wait for 1 ns;
I <= "001000110";
D <= "1111";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 49 : < Y /= 0000 >" -- Vector No: 7
severity warning;
assert (C4 = '1')
report
"Assert 50 : < C4 /= 1 >"
severity warning;
assert (Gbar = '1')
report
"Assert 51 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '0')
report
"Assert 52 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 53 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 54 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 55 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 16
wait for 1 ns;
I <= "000000111";
D <= "0001";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 17
wait for 1 ns;
I <= "000000110";
D <= "0001";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0010")
report
"Assert 56 : < Y /= 0010 >" -- Vector No: 8
severity warning;
assert (C4 = '0')
report
"Assert 57 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 58 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '1')
report
"Assert 59 : < Pbar /= 1 >"
severity warning;
assert (OVR = '0')
report
"Assert 60 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 61 : < F3 /= 0 >"
severity warning;
assert (F30 = '0')
report
"Assert 62 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 18
wait for 1 ns;
I <= "000000111";
D <= "0010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 19
wait for 1 ns;
I <= "001000110";
D <= "0010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0100")
report
"Assert 63 : < Y /= 0100 >" -- Vector No: 9
severity warning;
assert (C4 = '0')
report
"Assert 64 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 65 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '1')
report
"Assert 66 : < Pbar /= 1 >"
severity warning;
assert (OVR = '0')
report
"Assert 67 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 68 : < F3 /= 0 >"
severity warning;
assert (F30 = '0')
report
"Assert 69 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 20
wait for 1 ns;
I <= "000000111";
D <= "0100";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 21
wait for 1 ns;
I <= "001000110";
D <= "0100";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1000")
report
"Assert 70 : < Y /= 1000 >" -- Vector No: 10
severity warning;
assert (C4 = '0')
report
"Assert 71 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 72 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '1')
report
"Assert 73 : < Pbar /= 1 >"
severity warning;
assert (OVR = '1')
report
"Assert 74 : < OVR /= 1 >"
severity warning;
assert (F3 = '1')
report
"Assert 75 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 76 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 22
wait for 1 ns;
I <= "000000111";
D <= "1000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 23
wait for 1 ns;
I <= "001000110";
D <= "1000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 77 : < Y /= 0000 >" -- Vector No: 11
severity warning;
assert (C4 = '1')
report
"Assert 78 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 79 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '1')
report
"Assert 80 : < Pbar /= 1 >"
severity warning;
assert (OVR = '1')
report
"Assert 81 : < OVR /= 1 >"
severity warning;
assert (F3 = '0')
report
"Assert 82 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 83 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** SUBTRACTION S - R ********
--------------------------
clk <= '1'; -- Cycle No: 24
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 25
wait for 1 ns;
I <= "001001110";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 84 : < Y /= 1111 >" -- Vector No: 12
severity warning;
assert (C4 = '0')
report
"Assert 85 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 86 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '0')
report
"Assert 87 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 88 : < OVR /= 0 >"
severity warning;
assert (F3 = '1')
report
"Assert 89 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 90 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 26
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 27
wait for 1 ns;
I <= "001001110";
D <= "0000";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 91 : < Y /= 0000 >" -- Vector No: 13
severity warning;
assert (C4 = '1')
report
"Assert 92 : < C4 /= 1 >"
severity warning;
assert (Gbar = '1')
report
"Assert 93 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '0')
report
"Assert 94 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 95 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 96 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 97 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 28
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 29
wait for 1 ns;
I <= "001001110";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 98 : < Y /= 0000 >" -- Vector No: 14
severity warning;
assert (C4 = '0')
report
"Assert 99 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 100 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '1')
report
"Assert 101 : < Pbar /= 1 >"
severity warning;
assert (OVR = '0')
report
"Assert 102 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 103 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 104 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 30
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 31
wait for 1 ns;
I <= "001001110";
D <= "1111";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0001")
report
"Assert 105 : < Y /= 0001 >" -- Vector No: 15
severity warning;
assert (C4 = '0')
report
"Assert 106 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 107 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '1')
report
"Assert 108 : < Pbar /= 1 >"
severity warning;
assert (OVR = '0')
report
"Assert 109 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 110 : < F3 /= 0 >"
severity warning;
assert (F30 = '0')
report
"Assert 111 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 32
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 33
wait for 1 ns;
I <= "001001110";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 112 : < Y /= 1111 >" -- Vector No: 16
severity warning;
assert (C4 = '0')
report
"Assert 113 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 114 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '0')
report
"Assert 115 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 116 : < OVR /= 0 >"
severity warning;
assert (F3 = '1')
report
"Assert 117 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 118 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 34
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 35
wait for 1 ns;
I <= "001001110";
D <= "1111";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 119 : < Y /= 0000 >" -- Vector No: 17
severity warning;
assert (C4 = '1')
report
"Assert 120 : < C4 /= 1 >"
severity warning;
assert (Gbar = '1')
report
"Assert 121 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '0')
report
"Assert 122 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 123 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 124 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 125 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 36
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 37
wait for 1 ns;
I <= "001001110";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1110")
report
"Assert 126 : < Y /= 1110 >" -- Vector No: 18
severity warning;
assert (C4 = '1')
report
"Assert 127 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 128 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '0')
report
"Assert 129 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 130 : < OVR /= 0 >"
severity warning;
assert (F3 = '1')
report
"Assert 131 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 132 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 38
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 39
wait for 1 ns;
I <= "001001110";
D <= "0000";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 133 : < Y /= 1111 >" -- Vector No: 19
severity warning;
assert (C4 = '1')
report
"Assert 134 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 135 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '0')
report
"Assert 136 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 137 : < OVR /= 0 >"
severity warning;
assert (F3 = '1')
report
"Assert 138 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 139 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 40
wait for 1 ns;
I <= "000000111";
D <= "0001";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 41
wait for 1 ns;
I <= "001001110";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 140 : < Y /= 0000 >" -- Vector No: 20
severity warning;
assert (C4 = '1')
report
"Assert 141 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 142 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '0')
report
"Assert 143 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 144 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 145 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 146 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 42
wait for 1 ns;
I <= "000000111";
D <= "0010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 43
wait for 1 ns;
I <= "001001110";
D <= "0001";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0001")
report
"Assert 147 : < Y /= 0001 >" -- Vector No: 21
severity warning;
assert (C4 = '1')
report
"Assert 148 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 149 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '1')
report
"Assert 150 : < Pbar /= 1 >"
severity warning;
assert (OVR = '0')
report
"Assert 151 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 152 : < F3 /= 0 >"
severity warning;
assert (F30 = '0')
report
"Assert 153 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 44
wait for 1 ns;
I <= "000000111";
D <= "0100";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 45
wait for 1 ns;
I <= "001001110";
D <= "0010";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0010")
report
"Assert 154 : < Y /= 0010 >" -- Vector No: 22
severity warning;
assert (C4 = '1')
report
"Assert 155 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 156 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '1')
report
"Assert 157 : < Pbar /= 1 >"
severity warning;
assert (OVR = '0')
report
"Assert 158 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 159 : < F3 /= 0 >"
severity warning;
assert (F30 = '0')
report
"Assert 160 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 46
wait for 1 ns;
I <= "000000111";
D <= "1000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 47
wait for 1 ns;
I <= "001001110";
D <= "0100";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0100")
report
"Assert 161 : < Y /= 0100 >" -- Vector No: 23
severity warning;
assert (C4 = '1')
report
"Assert 162 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 163 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '1')
report
"Assert 164 : < Pbar /= 1 >"
severity warning;
assert (OVR = '1')
report
"Assert 165 : < OVR /= 1 >"
severity warning;
assert (F3 = '0')
report
"Assert 166 : < F3 /= 0 >"
severity warning;
assert (F30 = '0')
report
"Assert 167 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** SUBTRACTION R - S ********
--------------------------
clk <= '1'; -- Cycle No: 48
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 49
wait for 1 ns;
I <= "001010110";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 168 : < Y /= 1111 >" -- Vector No: 24
severity warning;
assert (C4 = '0')
report
"Assert 169 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 170 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '0')
report
"Assert 171 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 172 : < OVR /= 0 >"
severity warning;
assert (F3 = '1')
report
"Assert 173 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 174 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 50
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 51
wait for 1 ns;
I <= "001010110";
D <= "0000";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 175 : < Y /= 0000 >" -- Vector No: 25
severity warning;
assert (C4 = '1')
report
"Assert 176 : < C4 /= 1 >"
severity warning;
assert (Gbar = '1')
report
"Assert 177 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '0')
report
"Assert 178 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 179 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 180 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 181 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 52
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 53
wait for 1 ns;
I <= "001010110";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 182 : < Y /= 0000 >" -- Vector No: 26
severity warning;
assert (C4 = '0')
report
"Assert 183 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 184 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '1')
report
"Assert 185 : < Pbar /= 1 >"
severity warning;
assert (OVR = '0')
report
"Assert 186 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 187 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 188 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 54
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 55
wait for 1 ns;
I <= "001010110";
D <= "0000";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0001")
report
"Assert 189 : < Y /= 0001 >" -- Vector No: 27
severity warning;
assert (C4 = '0')
report
"Assert 190 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 191 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '1')
report
"Assert 192 : < Pbar /= 1 >"
severity warning;
assert (OVR = '0')
report
"Assert 193 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 194 : < F3 /= 0 >"
severity warning;
assert (F30 = '0')
report
"Assert 195 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 56
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 57
wait for 1 ns;
I <= "001010110";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 196 : < Y /= 1111 >" -- Vector No: 28
severity warning;
assert (C4 = '0')
report
"Assert 197 : < C4 /= 0 >"
severity warning;
assert (Gbar = '1')
report
"Assert 198 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '0')
report
"Assert 199 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 200 : < OVR /= 0 >"
severity warning;
assert (F3 = '1')
report
"Assert 201 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 202 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 58
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 59
wait for 1 ns;
I <= "001010110";
D <= "1111";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 203 : < Y /= 0000 >" -- Vector No: 29
severity warning;
assert (C4 = '1')
report
"Assert 204 : < C4 /= 1 >"
severity warning;
assert (Gbar = '1')
report
"Assert 205 : < Gbar /= 1 >"
severity warning;
assert (Pbar = '0')
report
"Assert 206 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 207 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 208 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 209 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 60
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 61
wait for 1 ns;
I <= "001010110";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1110")
report
"Assert 210 : < Y /= 1110 >" -- Vector No: 30
severity warning;
assert (C4 = '1')
report
"Assert 211 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 212 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '0')
report
"Assert 213 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 214 : < OVR /= 0 >"
severity warning;
assert (F3 = '1')
report
"Assert 215 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 216 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 62
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 63
wait for 1 ns;
I <= "001010110";
D <= "1111";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 217 : < Y /= 1111 >" -- Vector No: 31
severity warning;
assert (C4 = '1')
report
"Assert 218 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 219 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '0')
report
"Assert 220 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 221 : < OVR /= 0 >"
severity warning;
assert (F3 = '1')
report
"Assert 222 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 223 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 64
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 65
wait for 1 ns;
I <= "001010110";
D <= "0001";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 224 : < Y /= 0000 >" -- Vector No: 32
severity warning;
assert (C4 = '1')
report
"Assert 225 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 226 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '0')
report
"Assert 227 : < Pbar /= 0 >"
severity warning;
assert (OVR = '0')
report
"Assert 228 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 229 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 230 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 66
wait for 1 ns;
I <= "000000111";
D <= "0001";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 67
wait for 1 ns;
I <= "001010110";
D <= "0010";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0001")
report
"Assert 231 : < Y /= 0001 >" -- Vector No: 33
severity warning;
assert (C4 = '1')
report
"Assert 232 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 233 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '1')
report
"Assert 234 : < Pbar /= 1 >"
severity warning;
assert (OVR = '0')
report
"Assert 235 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 236 : < F3 /= 0 >"
severity warning;
assert (F30 = '0')
report
"Assert 237 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 68
wait for 1 ns;
I <= "000000111";
D <= "0010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 69
wait for 1 ns;
I <= "001010110";
D <= "0100";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0010")
report
"Assert 238 : < Y /= 0010 >" -- Vector No: 34
severity warning;
assert (C4 = '1')
report
"Assert 239 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 240 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '1')
report
"Assert 241 : < Pbar /= 1 >"
severity warning;
assert (OVR = '0')
report
"Assert 242 : < OVR /= 0 >"
severity warning;
assert (F3 = '0')
report
"Assert 243 : < F3 /= 0 >"
severity warning;
assert (F30 = '0')
report
"Assert 244 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 70
wait for 1 ns;
I <= "000000111";
D <= "0100";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 71
wait for 1 ns;
I <= "001010110";
D <= "1000";
C0 <= '1';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0100")
report
"Assert 245 : < Y /= 0100 >" -- Vector No: 35
severity warning;
assert (C4 = '1')
report
"Assert 246 : < C4 /= 1 >"
severity warning;
assert (Gbar = '0')
report
"Assert 247 : < Gbar /= 0 >"
severity warning;
assert (Pbar = '1')
report
"Assert 248 : < Pbar /= 1 >"
severity warning;
assert (OVR = '1')
report
"Assert 249 : < OVR /= 1 >"
severity warning;
assert (F3 = '0')
report
"Assert 250 : < F3 /= 0 >"
severity warning;
assert (F30 = '0')
report
"Assert 251 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** OR (R or S) ********
--------------------------
clk <= '1'; -- Cycle No: 72
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 73
wait for 1 ns;
I <= "001011110";
D <= "0000";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 252 : < Y /= 0000 >" -- Vector No: 36
severity warning;
assert (F3 = '0')
report
"Assert 253 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 254 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 74
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 75
wait for 1 ns;
I <= "001011110";
D <= "0000";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 255 : < Y /= 1111 >" -- Vector No: 37
severity warning;
assert (F3 = '1')
report
"Assert 256 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 257 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 76
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 77
wait for 1 ns;
I <= "001011110";
D <= "1111";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 258 : < Y /= 1111 >" -- Vector No: 38
severity warning;
assert (F3 = '1')
report
"Assert 259 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 260 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 78
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 79
wait for 1 ns;
I <= "001011110";
D <= "1111";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 261 : < Y /= 1111 >" -- Vector No: 39
severity warning;
assert (F3 = '1')
report
"Assert 262 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 263 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** AND (R and S) ********
--------------------------
clk <= '1'; -- Cycle No: 80
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 81
wait for 1 ns;
I <= "001100110";
D <= "0000";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 264 : < Y /= 0000 >" -- Vector No: 40
severity warning;
assert (F3 = '0')
report
"Assert 265 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 266 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 82
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 83
wait for 1 ns;
I <= "001100110";
D <= "0000";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 267 : < Y /= 0000 >" -- Vector No: 41
severity warning;
assert (F3 = '0')
report
"Assert 268 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 269 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 84
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 85
wait for 1 ns;
I <= "001100110";
D <= "1111";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 270 : < Y /= 1111 >" -- Vector No: 42
severity warning;
assert (F3 = '1')
report
"Assert 271 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 272 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 86
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 87
wait for 1 ns;
I <= "001100110";
D <= "1111";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 273 : < Y /= 0000 >" -- Vector No: 43
severity warning;
assert (F3 = '0')
report
"Assert 274 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 275 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** AND (not(R) and S) ********
--------------------------
clk <= '1'; -- Cycle No: 88
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 89
wait for 1 ns;
I <= "001101110";
D <= "0000";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 276 : < Y /= 0000 >" -- Vector No: 44
severity warning;
assert (F3 = '0')
report
"Assert 277 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 278 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 90
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 91
wait for 1 ns;
I <= "001101110";
D <= "0000";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 279 : < Y /= 1111 >" -- Vector No: 45
severity warning;
assert (F3 = '1')
report
"Assert 280 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 281 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 92
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 93
wait for 1 ns;
I <= "001101110";
D <= "1111";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 282 : < Y /= 0000 >" -- Vector No: 46
severity warning;
assert (F3 = '0')
report
"Assert 283 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 284 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 94
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 95
wait for 1 ns;
I <= "001101110";
D <= "1111";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 285 : < Y /= 0000 >" -- Vector No: 47
severity warning;
assert (F3 = '0')
report
"Assert 286 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 287 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** XOR (R xor S) ********
--------------------------
clk <= '1'; -- Cycle No: 96
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 97
wait for 1 ns;
I <= "001110110";
D <= "0000";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 288 : < Y /= 0000 >" -- Vector No: 48
severity warning;
assert (F3 = '0')
report
"Assert 289 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 290 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 98
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 99
wait for 1 ns;
I <= "001110110";
D <= "0000";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 291 : < Y /= 1111 >" -- Vector No: 49
severity warning;
assert (F3 = '1')
report
"Assert 292 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 293 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 100
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 101
wait for 1 ns;
I <= "001110110";
D <= "1111";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 294 : < Y /= 0000 >" -- Vector No: 50
severity warning;
assert (F3 = '0')
report
"Assert 295 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 296 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 102
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 103
wait for 1 ns;
I <= "001110110";
D <= "1111";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 297 : < Y /= 1111 >" -- Vector No: 51
severity warning;
assert (F3 = '1')
report
"Assert 298 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 299 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** XNOR (R xnor S) ********
--------------------------
clk <= '1'; -- Cycle No: 104
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 105
wait for 1 ns;
I <= "001111110";
D <= "0000";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 300 : < Y /= 1111 >" -- Vector No: 52
severity warning;
assert (F3 = '1')
report
"Assert 301 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 302 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 106
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 107
wait for 1 ns;
I <= "001111110";
D <= "0000";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 303 : < Y /= 0000 >" -- Vector No: 53
severity warning;
assert (F3 = '0')
report
"Assert 304 : < F3 /= 0 >"
severity warning;
assert (F30 = '1')
report
"Assert 305 : < F30 /= 1 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 108
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 109
wait for 1 ns;
I <= "001111110";
D <= "1111";
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 306 : < Y /= 1111 >" -- Vector No: 54
severity warning;
assert (F3 = '1')
report
"Assert 307 : < F3 /= 1 >"
severity warning;
assert (F30 = '0')
report
"Assert 308 : < F30 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
-- ************************
-- * *
-- * TEST VECTORS FOR RAM *
-- * *
-- ************************
-- ******** WRITING 0's AND 1's IN RAM LOCATIONS ********
--------------------------
clk <= '1'; -- Cycle No: 110
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 111
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 309 : < Y /= 0000 >" -- Vector No: 55
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 112
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 113
wait for 1 ns;
I <= "001000100";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 310 : < Y /= 0000 >" -- Vector No: 56
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 114
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 115
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 311 : < Y /= 1111 >" -- Vector No: 57
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 116
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 117
wait for 1 ns;
I <= "001000100";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 312 : < Y /= 1111 >" -- Vector No: 58
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 118
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 119
wait for 1 ns;
I <= "001000100";
Aadd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 313 : < Y /= 0000 >" -- Vector No: 59
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 120
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 121
wait for 1 ns;
I <= "001000100";
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 314 : < Y /= 0000 >" -- Vector No: 60
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 122
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 123
wait for 1 ns;
I <= "001000100";
Aadd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 315 : < Y /= 1111 >" -- Vector No: 61
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 124
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 125
wait for 1 ns;
I <= "001000100";
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 316 : < Y /= 1111 >" -- Vector No: 62
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 126
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 2 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 127
wait for 1 ns;
I <= "001000100";
Aadd <= 2 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 317 : < Y /= 0000 >" -- Vector No: 63
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 128
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 2 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 129
wait for 1 ns;
I <= "001000100";
Badd <= 2 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 318 : < Y /= 0000 >" -- Vector No: 64
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 130
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 2 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 131
wait for 1 ns;
I <= "001000100";
Aadd <= 2 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 319 : < Y /= 1111 >" -- Vector No: 65
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 132
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 2 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 133
wait for 1 ns;
I <= "001000100";
Badd <= 2 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 320 : < Y /= 1111 >" -- Vector No: 66
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 134
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 3 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 135
wait for 1 ns;
I <= "001000100";
Aadd <= 3 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 321 : < Y /= 0000 >" -- Vector No: 67
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 136
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 3 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 137
wait for 1 ns;
I <= "001000100";
Badd <= 3 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 322 : < Y /= 0000 >" -- Vector No: 68
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 138
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 3 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 139
wait for 1 ns;
I <= "001000100";
Aadd <= 3 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 323 : < Y /= 1111 >" -- Vector No: 69
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 140
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 3 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 141
wait for 1 ns;
I <= "001000100";
Badd <= 3 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 324 : < Y /= 1111 >" -- Vector No: 70
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 142
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 4 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 143
wait for 1 ns;
I <= "001000100";
Aadd <= 4 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 325 : < Y /= 0000 >" -- Vector No: 71
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 144
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 4 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 145
wait for 1 ns;
I <= "001000100";
Badd <= 4 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 326 : < Y /= 0000 >" -- Vector No: 72
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 146
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 4 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 147
wait for 1 ns;
I <= "001000100";
Aadd <= 4 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 327 : < Y /= 1111 >" -- Vector No: 73
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 148
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 4 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 149
wait for 1 ns;
I <= "001000100";
Badd <= 4 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 328 : < Y /= 1111 >" -- Vector No: 74
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 150
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 5 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 151
wait for 1 ns;
I <= "001000100";
Aadd <= 5 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 329 : < Y /= 0000 >" -- Vector No: 75
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 152
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 5 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 153
wait for 1 ns;
I <= "001000100";
Badd <= 5 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 330 : < Y /= 0000 >" -- Vector No: 76
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 154
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 5 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 155
wait for 1 ns;
I <= "001000100";
Aadd <= 5 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 331 : < Y /= 1111 >" -- Vector No: 77
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 156
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 5 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 157
wait for 1 ns;
I <= "001000100";
Badd <= 5 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 332 : < Y /= 1111 >" -- Vector No: 78
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 158
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 6 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 159
wait for 1 ns;
I <= "001000100";
Aadd <= 6 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 333 : < Y /= 0000 >" -- Vector No: 79
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 160
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 6 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 161
wait for 1 ns;
I <= "001000100";
Badd <= 6 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 334 : < Y /= 0000 >" -- Vector No: 80
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 162
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 6 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 163
wait for 1 ns;
I <= "001000100";
Aadd <= 6 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 335 : < Y /= 1111 >" -- Vector No: 81
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 164
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 6 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 165
wait for 1 ns;
I <= "001000100";
Badd <= 6 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 336 : < Y /= 1111 >" -- Vector No: 82
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 166
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 7 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 167
wait for 1 ns;
I <= "001000100";
Aadd <= 7 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 337 : < Y /= 0000 >" -- Vector No: 83
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 168
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 7 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 169
wait for 1 ns;
I <= "001000100";
Badd <= 7 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 338 : < Y /= 0000 >" -- Vector No: 84
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 170
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 7 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 171
wait for 1 ns;
I <= "001000100";
Aadd <= 7 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 339 : < Y /= 1111 >" -- Vector No: 85
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 172
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 7 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 173
wait for 1 ns;
I <= "001000100";
Badd <= 7 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 340 : < Y /= 1111 >" -- Vector No: 86
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 174
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 8 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 175
wait for 1 ns;
I <= "001000100";
Aadd <= 8 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 341 : < Y /= 0000 >" -- Vector No: 87
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 176
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 8 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 177
wait for 1 ns;
I <= "001000100";
Badd <= 8 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 342 : < Y /= 0000 >" -- Vector No: 88
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 178
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 8 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 179
wait for 1 ns;
I <= "001000100";
Aadd <= 8 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 343 : < Y /= 1111 >" -- Vector No: 89
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 180
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 8 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 181
wait for 1 ns;
I <= "001000100";
Badd <= 8 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 344 : < Y /= 1111 >" -- Vector No: 90
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 182
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 9 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 183
wait for 1 ns;
I <= "001000100";
Aadd <= 9 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 345 : < Y /= 0000 >" -- Vector No: 91
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 184
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 9 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 185
wait for 1 ns;
I <= "001000100";
Badd <= 9 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 346 : < Y /= 0000 >" -- Vector No: 92
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 186
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 9 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 187
wait for 1 ns;
I <= "001000100";
Aadd <= 9 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 347 : < Y /= 1111 >" -- Vector No: 93
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 188
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 9 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 189
wait for 1 ns;
I <= "001000100";
Badd <= 9 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 348 : < Y /= 1111 >" -- Vector No: 94
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 190
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 10 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 191
wait for 1 ns;
I <= "001000100";
Aadd <= 10 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 349 : < Y /= 0000 >" -- Vector No: 95
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 192
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 10 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 193
wait for 1 ns;
I <= "001000100";
Badd <= 10 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 350 : < Y /= 0000 >" -- Vector No: 96
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 194
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 10 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 195
wait for 1 ns;
I <= "001000100";
Aadd <= 10 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 351 : < Y /= 1111 >" -- Vector No: 97
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 196
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 10 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 197
wait for 1 ns;
I <= "001000100";
Badd <= 10 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 352 : < Y /= 1111 >" -- Vector No: 98
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 198
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 11 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 199
wait for 1 ns;
I <= "001000100";
Aadd <= 11 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 353 : < Y /= 0000 >" -- Vector No: 99
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 200
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 11 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 201
wait for 1 ns;
I <= "001000100";
Badd <= 11 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 354 : < Y /= 0000 >" -- Vector No: 100
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 202
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 11 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 203
wait for 1 ns;
I <= "001000100";
Aadd <= 11 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 355 : < Y /= 1111 >" -- Vector No: 101
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 204
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 11 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 205
wait for 1 ns;
I <= "001000100";
Badd <= 11 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 356 : < Y /= 1111 >" -- Vector No: 102
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 206
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 12 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 207
wait for 1 ns;
I <= "001000100";
Aadd <= 12 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 357 : < Y /= 0000 >" -- Vector No: 103
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 208
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 12 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 209
wait for 1 ns;
I <= "001000100";
Badd <= 12 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 358 : < Y /= 0000 >" -- Vector No: 104
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 210
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 12 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 211
wait for 1 ns;
I <= "001000100";
Aadd <= 12 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 359 : < Y /= 1111 >" -- Vector No: 105
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 212
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 12 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 213
wait for 1 ns;
I <= "001000100";
Badd <= 12 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 360 : < Y /= 1111 >" -- Vector No: 106
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 214
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 13 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 215
wait for 1 ns;
I <= "001000100";
Aadd <= 13 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 361 : < Y /= 0000 >" -- Vector No: 107
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 216
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 13 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 217
wait for 1 ns;
I <= "001000100";
Badd <= 13 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 362 : < Y /= 0000 >" -- Vector No: 108
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 218
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 13 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 219
wait for 1 ns;
I <= "001000100";
Aadd <= 13 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 363 : < Y /= 1111 >" -- Vector No: 109
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 220
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 13 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 221
wait for 1 ns;
I <= "001000100";
Badd <= 13 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 364 : < Y /= 1111 >" -- Vector No: 110
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 222
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 14 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 223
wait for 1 ns;
I <= "001000100";
Aadd <= 14 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 365 : < Y /= 0000 >" -- Vector No: 111
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 224
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 14 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 225
wait for 1 ns;
I <= "001000100";
Badd <= 14 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 366 : < Y /= 0000 >" -- Vector No: 112
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 226
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 14 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 227
wait for 1 ns;
I <= "001000100";
Aadd <= 14 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 367 : < Y /= 1111 >" -- Vector No: 113
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 228
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 14 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 229
wait for 1 ns;
I <= "001000100";
Badd <= 14 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 368 : < Y /= 1111 >" -- Vector No: 114
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 230
wait for 1 ns;
I <= "010000111";
D <= "0000";
Badd <= 15 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 231
wait for 1 ns;
I <= "001000100";
Aadd <= 15 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 369 : < Y /= 0000 >" -- Vector No: 115
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 232
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 15 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 233
wait for 1 ns;
I <= "001000100";
Badd <= 15 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 370 : < Y /= 0000 >" -- Vector No: 116
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 234
wait for 1 ns;
I <= "010000111";
D <= "1111";
Badd <= 15 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 235
wait for 1 ns;
I <= "001000100";
Aadd <= 15 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 371 : < Y /= 1111 >" -- Vector No: 117
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 236
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 15 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 237
wait for 1 ns;
I <= "001000100";
Badd <= 15 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 372 : < Y /= 1111 >" -- Vector No: 118
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING RAM SHIFTERS ********
--------------------------
clk <= '1'; -- Cycle No: 238
wait for 1 ns;
I <= "100000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
RAM0 <= 'Z';
RAM3 <= '1';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (RAM0out = '0')
report
"Assert 373 : < RAM0 /= 0 >" -- Vector No: 119
severity warning;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 239
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1000")
report
"Assert 374 : < Y /= 1000 >" -- Vector No: 120
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 240
wait for 1 ns;
I <= "100000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
RAM0 <= 'Z';
RAM3 <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (RAM0out = '1')
report
"Assert 375 : < RAM0 /= 1 >" -- Vector No: 121
severity warning;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 241
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0111")
report
"Assert 376 : < Y /= 0111 >" -- Vector No: 122
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 242
wait for 1 ns;
I <= "101000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
RAM0 <= 'Z';
RAM3 <= '1';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (RAM0out = '0')
report
"Assert 377 : < RAM0 /= 0 >" -- Vector No: 123
severity warning;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 243
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1000")
report
"Assert 378 : < Y /= 1000 >" -- Vector No: 124
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 244
wait for 1 ns;
I <= "101000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
RAM0 <= 'Z';
RAM3 <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (RAM0out = '1')
report
"Assert 379 : < RAM0 /= 1 >" -- Vector No: 125
severity warning;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 245
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0111")
report
"Assert 380 : < Y /= 0111 >" -- Vector No: 126
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 246
wait for 1 ns;
I <= "110000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
RAM0 <= '1';
RAM3 <= 'Z';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (RAM3out = '0')
report
"Assert 381 : < RAM3 /= 0 >" -- Vector No: 127
severity warning;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 247
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0001")
report
"Assert 382 : < Y /= 0001 >" -- Vector No: 128
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 248
wait for 1 ns;
I <= "110000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
RAM0 <= '0';
RAM3 <= 'Z';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (RAM3out = '1')
report
"Assert 383 : < RAM3 /= 1 >" -- Vector No: 129
severity warning;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 249
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1110")
report
"Assert 384 : < Y /= 1110 >" -- Vector No: 130
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 250
wait for 1 ns;
I <= "111000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
RAM0 <= '1';
RAM3 <= 'Z';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (RAM3out = '0')
report
"Assert 385 : < RAM3 /= 0 >" -- Vector No: 131
severity warning;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 251
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0001")
report
"Assert 386 : < Y /= 0001 >" -- Vector No: 132
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 252
wait for 1 ns;
I <= "111000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
RAM0 <= '0';
RAM3 <= 'Z';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (RAM3out = '1')
report
"Assert 387 : < RAM3 /= 1 >" -- Vector No: 133
severity warning;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 253
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1110")
report
"Assert 388 : < Y /= 1110 >" -- Vector No: 134
severity warning;
wait for 1 ns;
-- ************************
-- *******************************
-- * *
-- * TEST VECTORS FOR Q-REGISTER *
-- * *
-- *******************************
-- ******** WRITING 0's AND 1's ********
--------------------------
clk <= '1'; -- Cycle No: 254
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 255
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 389 : < Y /= 1111 >" -- Vector No: 135
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 256
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 257
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 390 : < Y /= 0000 >" -- Vector No: 136
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING Q-REGISTER SHIFTERS ********
--------------------------
clk <= '1'; -- Cycle No: 258
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 259
wait for 1 ns;
I <= "100000111";
C0 <= '0';
OEbar <= '0';
Q0 <= 'Z';
Q3 <= '1';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Q0out = '0')
report
"Assert 391 : < Q0 /= 0 >" -- Vector No: 137
severity warning;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 260
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1000")
report
"Assert 392 : < Y /= 1000 >" -- Vector No: 138
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 261
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 262
wait for 1 ns;
I <= "100000111";
C0 <= '0';
OEbar <= '0';
Q0 <= 'Z';
Q3 <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Q0out = '1')
report
"Assert 393 : < Q0 /= 1 >" -- Vector No: 139
severity warning;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 263
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0111")
report
"Assert 394 : < Y /= 0111 >" -- Vector No: 140
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 264
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 265
wait for 1 ns;
I <= "110000111";
C0 <= '0';
OEbar <= '0';
Q0 <= '1';
Q3 <= 'Z';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Q3out = '0')
report
"Assert 395 : < Q3 /= 0 >" -- Vector No: 141
severity warning;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 266
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0001")
report
"Assert 396 : < Y /= 0001 >" -- Vector No: 142
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 267
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 268
wait for 1 ns;
I <= "110000111";
C0 <= '0';
OEbar <= '0';
Q0 <= '0';
Q3 <= 'Z';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Q3out = '1')
report
"Assert 397 : < Q3 /= 1 >" -- Vector No: 143
severity warning;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 269
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1110")
report
"Assert 398 : < Y /= 1110 >" -- Vector No: 144
severity warning;
wait for 1 ns;
-- ************************
-- ****************************************
-- * *
-- * TEST VECTORS FOR ALU SOURCE-SELECTOR *
-- * *
-- ****************************************
-- ******** TESTING FOR ALU SOURCE-SELECT ( R = A, S = Q) ********
--------------------------
clk <= '1'; -- Cycle No: 270
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 271
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 272
wait for 1 ns;
I <= "001000000";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 399 : < Y /= 1111 >" -- Vector No: 145
severity warning;
assert (C4 = '0')
report
"Assert 400 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 273
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 274
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 275
wait for 1 ns;
I <= "001000000";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 401 : < Y /= 1111 >" -- Vector No: 146
severity warning;
assert (C4 = '0')
report
"Assert 402 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING FOR ALU SOURCE-SELECT ( R = A, S = B) ********
--------------------------
clk <= '1'; -- Cycle No: 276
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 277
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 278
wait for 1 ns;
I <= "001000001";
Aadd <= 0 ;
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 403 : < Y /= 1111 >" -- Vector No: 147
severity warning;
assert (C4 = '0')
report
"Assert 404 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 279
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 280
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 281
wait for 1 ns;
I <= "001000001";
Aadd <= 0 ;
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 405 : < Y /= 1111 >" -- Vector No: 148
severity warning;
assert (C4 = '0')
report
"Assert 406 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING FOR ALU SOURCE-SELECT ( R = 0, S = Q) ********
--------------------------
clk <= '1'; -- Cycle No: 282
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 283
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 407 : < Y /= 0000 >" -- Vector No: 149
severity warning;
assert (C4 = '0')
report
"Assert 408 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 284
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 285
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 409 : < Y /= 1111 >" -- Vector No: 150
severity warning;
assert (C4 = '0')
report
"Assert 410 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING FOR ALU SOURCE-SELECT ( R = 0, S = B) ********
--------------------------
clk <= '1'; -- Cycle No: 286
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 287
wait for 1 ns;
I <= "001000011";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 411 : < Y /= 0000 >" -- Vector No: 151
severity warning;
assert (C4 = '0')
report
"Assert 412 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 288
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 289
wait for 1 ns;
I <= "001000011";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 413 : < Y /= 1111 >" -- Vector No: 152
severity warning;
assert (C4 = '0')
report
"Assert 414 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING FOR ALU SOURCE-SELECT ( R = 0, S = A) ********
--------------------------
clk <= '1'; -- Cycle No: 290
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 291
wait for 1 ns;
I <= "001000100";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 415 : < Y /= 0000 >" -- Vector No: 153
severity warning;
assert (C4 = '0')
report
"Assert 416 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 292
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 293
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 417 : < Y /= 1111 >" -- Vector No: 154
severity warning;
assert (C4 = '0')
report
"Assert 418 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING FOR ALU SOURCE-SELECT ( R = D, S = A) ********
--------------------------
clk <= '1'; -- Cycle No: 294
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 295
wait for 1 ns;
I <= "001000101";
D <= "1111";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 419 : < Y /= 1111 >" -- Vector No: 155
severity warning;
assert (C4 = '0')
report
"Assert 420 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 296
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 297
wait for 1 ns;
I <= "001000101";
D <= "0000";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 421 : < Y /= 1111 >" -- Vector No: 156
severity warning;
assert (C4 = '0')
report
"Assert 422 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING FOR ALU SOURCE-SELECT ( R = D, S = Q) ********
--------------------------
clk <= '1'; -- Cycle No: 298
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 299
wait for 1 ns;
I <= "001000110";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 423 : < Y /= 1111 >" -- Vector No: 157
severity warning;
assert (C4 = '0')
report
"Assert 424 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 300
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 301
wait for 1 ns;
I <= "001000110";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 425 : < Y /= 1111 >" -- Vector No: 158
severity warning;
assert (C4 = '0')
report
"Assert 426 : < C4 /= 0 >"
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING FOR ALU SOURCE-SELECT ( R = D, S = 0) ********
--------------------------
clk <= '1'; -- Cycle No: 302
wait for 1 ns;
I <= "001000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 427 : < Y /= 0000 >" -- Vector No: 159
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 303
wait for 1 ns;
I <= "001000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 428 : < Y /= 1111 >" -- Vector No: 160
severity warning;
wait for 1 ns;
-- ************************
-- ************************************
-- * *
-- * TEST VECTORS FOR OUTPUT-SELECTOR *
-- * *
-- ************************************
-- ******** TESTING OUTPUT FOR (I8 I7 I6 = 000) ********
--------------------------
clk <= '1'; -- Cycle No: 304
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 429 : < Y /= 0000 >" -- Vector No: 161
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 305
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 430 : < Y /= 1111 >" -- Vector No: 162
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 306
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '1';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "ZZZZ")
report
"Assert 431 : < Y /= ZZZZ >" -- Vector No: 163
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING OUTPUT FOR (I8 I7 I6 = 001) ********
--------------------------
clk <= '1'; -- Cycle No: 307
wait for 1 ns;
I <= "001000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 432 : < Y /= 0000 >" -- Vector No: 164
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 308
wait for 1 ns;
I <= "001000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 433 : < Y /= 1111 >" -- Vector No: 165
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 309
wait for 1 ns;
I <= "001000111";
D <= "1111";
C0 <= '0';
OEbar <= '1';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "ZZZZ")
report
"Assert 434 : < Y /= ZZZZ >" -- Vector No: 166
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING OUTPUT FOR (I8 I7 I6 = 010) ********
--------------------------
clk <= '1'; -- Cycle No: 310
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 311
wait for 1 ns;
I <= "010000111";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 435 : < Y /= 0000 >" -- Vector No: 167
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 312
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 313
wait for 1 ns;
I <= "010000111";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 436 : < Y /= 1111 >" -- Vector No: 168
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 314
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 315
wait for 1 ns;
I <= "010000111";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '1';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "ZZZZ")
report
"Assert 437 : < Y /= ZZZZ >" -- Vector No: 169
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING OUTPUT FOR (I8 I7 I6 = 011) ********
--------------------------
clk <= '1'; -- Cycle No: 316
wait for 1 ns;
I <= "011000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 438 : < Y /= 0000 >" -- Vector No: 170
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 317
wait for 1 ns;
I <= "011000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 439 : < Y /= 1111 >" -- Vector No: 171
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 318
wait for 1 ns;
I <= "011000111";
D <= "1111";
C0 <= '0';
OEbar <= '1';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "ZZZZ")
report
"Assert 440 : < Y /= ZZZZ >" -- Vector No: 172
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING OUTPUT FOR (I8 I7 I6 = 100) ********
--------------------------
clk <= '1'; -- Cycle No: 319
wait for 1 ns;
I <= "100000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 441 : < Y /= 0000 >" -- Vector No: 173
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 320
wait for 1 ns;
I <= "100000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 442 : < Y /= 1111 >" -- Vector No: 174
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 321
wait for 1 ns;
I <= "100000111";
D <= "1111";
C0 <= '0';
OEbar <= '1';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "ZZZZ")
report
"Assert 443 : < Y /= ZZZZ >" -- Vector No: 175
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING OUTPUT FOR (I8 I7 I6 = 101) ********
--------------------------
clk <= '1'; -- Cycle No: 322
wait for 1 ns;
I <= "101000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 444 : < Y /= 0000 >" -- Vector No: 176
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 323
wait for 1 ns;
I <= "101000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 445 : < Y /= 1111 >" -- Vector No: 177
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 324
wait for 1 ns;
I <= "101000111";
D <= "1111";
C0 <= '0';
OEbar <= '1';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "ZZZZ")
report
"Assert 446 : < Y /= ZZZZ >" -- Vector No: 178
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING OUTPUT FOR (I8 I7 I6 = 110) ********
--------------------------
clk <= '1'; -- Cycle No: 325
wait for 1 ns;
I <= "110000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 447 : < Y /= 0000 >" -- Vector No: 179
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 326
wait for 1 ns;
I <= "110000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 448 : < Y /= 1111 >" -- Vector No: 180
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 327
wait for 1 ns;
I <= "110000111";
D <= "1111";
C0 <= '0';
OEbar <= '1';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "ZZZZ")
report
"Assert 449 : < Y /= ZZZZ >" -- Vector No: 181
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING OUTPUT FOR (I8 I7 I6 = 111) ********
--------------------------
clk <= '1'; -- Cycle No: 328
wait for 1 ns;
I <= "111000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 450 : < Y /= 0000 >" -- Vector No: 182
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 329
wait for 1 ns;
I <= "111000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 451 : < Y /= 1111 >" -- Vector No: 183
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 330
wait for 1 ns;
I <= "111000111";
D <= "1111";
C0 <= '0';
OEbar <= '1';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "ZZZZ")
report
"Assert 452 : < Y /= ZZZZ >" -- Vector No: 184
severity warning;
wait for 1 ns;
-- ************************
-- **************************
-- * *
-- * TEST VECTORS FOR PATHS *
-- * *
-- **************************
-- ******** TESTING PATHS ( "ALU-SOURCES" --> F --> Q ) ********
-- * * * * PATH TEST WITH ALU-SOURCE ( R = A , S = Q ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 331
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 332
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 333
wait for 1 ns;
I <= "000011000";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 334
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 453 : < Y /= 0000 >" -- Vector No: 185
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 335
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 336
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 337
wait for 1 ns;
I <= "000100000";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 338
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 454 : < Y /= 1111 >" -- Vector No: 186
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = A , S = B ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 339
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 340
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 341
wait for 1 ns;
I <= "000011001";
Aadd <= 0 ;
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 342
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 455 : < Y /= 0000 >" -- Vector No: 187
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 343
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 344
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 345
wait for 1 ns;
I <= "000100001";
Aadd <= 0 ;
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 346
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 456 : < Y /= 1111 >" -- Vector No: 188
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = 0 , S = Q ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 347
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 348
wait for 1 ns;
I <= "000011010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 349
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 457 : < Y /= 0000 >" -- Vector No: 189
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 350
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 351
wait for 1 ns;
I <= "000011010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 352
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 458 : < Y /= 1111 >" -- Vector No: 190
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = 0 , S = B ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 353
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 354
wait for 1 ns;
I <= "000011011";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 355
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 459 : < Y /= 0000 >" -- Vector No: 191
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 356
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 357
wait for 1 ns;
I <= "000011011";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 358
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 460 : < Y /= 1111 >" -- Vector No: 192
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = 0 , S = A ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 359
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 360
wait for 1 ns;
I <= "000011100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 361
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 461 : < Y /= 0000 >" -- Vector No: 193
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 362
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 363
wait for 1 ns;
I <= "000011100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 364
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 462 : < Y /= 1111 >" -- Vector No: 194
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = A ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 365
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 366
wait for 1 ns;
I <= "000011101";
D <= "0000";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 367
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 463 : < Y /= 0000 >" -- Vector No: 195
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 368
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 369
wait for 1 ns;
I <= "000100101";
D <= "1111";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 370
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 464 : < Y /= 1111 >" -- Vector No: 196
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = Q ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 371
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 372
wait for 1 ns;
I <= "000011110";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 373
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 465 : < Y /= 0000 >" -- Vector No: 197
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 374
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 375
wait for 1 ns;
I <= "000100110";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 376
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 466 : < Y /= 1111 >" -- Vector No: 198
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = 0 ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 377
wait for 1 ns;
I <= "000011111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 378
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 467 : < Y /= 0000 >" -- Vector No: 199
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = 0 ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 379
wait for 1 ns;
I <= "000011111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 380
wait for 1 ns;
I <= "001000010";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 468 : < Y /= 1111 >" -- Vector No: 200
severity warning;
wait for 1 ns;
-- ************************
-- ******** TESTING PATHS ( "ALU-SOURCES" --> F --> B ) ********
-- * * * * PATH TEST WITH ALU-SOURCE ( R = A , S = Q ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 381
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 382
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 383
wait for 1 ns;
I <= "011011000";
Aadd <= 0 ;
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 384
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 469 : < Y /= 0000 >" -- Vector No: 201
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 385
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 386
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 387
wait for 1 ns;
I <= "011100000";
Aadd <= 0 ;
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 388
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 470 : < Y /= 1111 >" -- Vector No: 202
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = A , S = B ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 389
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 390
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 391
wait for 1 ns;
I <= "011011001";
Aadd <= 1 ;
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 392
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 471 : < Y /= 0000 >" -- Vector No: 203
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 393
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 394
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 1 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 395
wait for 1 ns;
I <= "011100001";
Aadd <= 1 ;
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 396
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 472 : < Y /= 1111 >" -- Vector No: 204
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = 0 , S = Q ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 397
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 398
wait for 1 ns;
I <= "011011010";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 399
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 473 : < Y /= 0000 >" -- Vector No: 205
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 400
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 401
wait for 1 ns;
I <= "011011010";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 402
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 474 : < Y /= 1111 >" -- Vector No: 206
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = 0 , S = B ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 403
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 404
wait for 1 ns;
I <= "011011011";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 405
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 475 : < Y /= 0000 >" -- Vector No: 207
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 406
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 407
wait for 1 ns;
I <= "011011011";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 408
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 476 : < Y /= 1111 >" -- Vector No: 208
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = 0 , S = A ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 409
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 410
wait for 1 ns;
I <= "011011100";
Aadd <= 0 ;
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 411
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 477 : < Y /= 0000 >" -- Vector No: 209
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 412
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 413
wait for 1 ns;
I <= "011011100";
Aadd <= 0 ;
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 414
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 478 : < Y /= 1111 >" -- Vector No: 210
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = A ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 415
wait for 1 ns;
I <= "011000111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 416
wait for 1 ns;
I <= "011011101";
D <= "0000";
Aadd <= 0 ;
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 417
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 479 : < Y /= 0000 >" -- Vector No: 211
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 418
wait for 1 ns;
I <= "011000111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 419
wait for 1 ns;
I <= "011100101";
D <= "1111";
Aadd <= 0 ;
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 420
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 480 : < Y /= 1111 >" -- Vector No: 212
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = Q ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 421
wait for 1 ns;
I <= "000000111";
D <= "0000";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 422
wait for 1 ns;
I <= "011011110";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 423
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 481 : < Y /= 0000 >" -- Vector No: 213
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 424
wait for 1 ns;
I <= "000000111";
D <= "1111";
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 425
wait for 1 ns;
I <= "011100110";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 426
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 482 : < Y /= 1111 >" -- Vector No: 214
severity warning;
wait for 1 ns;
-- ************************
-- * * * * PATH TEST WITH ALU-SOURCE ( R = D , S = 0 ) * * * *
--------------------------
clk <= '1'; -- Cycle No: 427
wait for 1 ns;
I <= "011011111";
D <= "0000";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 428
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "0000")
report
"Assert 483 : < Y /= 0000 >" -- Vector No: 215
severity warning;
wait for 1 ns;
-- ************************
--------------------------
clk <= '1'; -- Cycle No: 429
wait for 1 ns;
I <= "011011111";
D <= "1111";
Badd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
wait for 1 ns;
--------------------------
clk <= '1'; -- Cycle No: 430
wait for 1 ns;
I <= "001000100";
Aadd <= 0 ;
C0 <= '0';
OEbar <= '0';
wait for 4 ns;
clk <= '0';
wait for 4 ns;
assert (Y = "1111")
report
"Assert 484 : < Y /= 1111 >" -- Vector No: 216
severity warning;
wait for 1 ns;
-- ************************
--------------------------
report "Test PASS";
wait;
end process;
end A;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- This simulation model contains highly confidential and
-- proprietary information of Altera and is being provided
-- in accordance with and subject to the protections of the
-- applicable Altera Program License Subscription Agreement
-- which governs its use and disclosure. Your use of Altera
-- Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions,
-- and any output files any of the foregoing (including device
-- programming or simulation files), and any associated
-- documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of simulating designs for
-- use exclusively in logic devices manufactured by Altera and sold
-- by Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details. Altera products and
-- services are protected under numerous U.S. and foreign patents,
-- maskwork rights, copyrights and other intellectual property laws.
-- Altera assumes no responsibility or liability arising out of the
-- application or use of this simulation model.
-- Quartus II 11.0 Build 157 04/27/2011
library IEEE;
use IEEE.std_logic_1164.all;
entity stratixv_hssi_gen3_pcie_hip is
generic (
func_mode : string := "disable";
in_cvp_mode : string := "not_cvp_mode";
bonding_mode : string := "bond_disable";
prot_mode : string := "disabled_prot_mode";
pcie_spec_1p0_compliance : string := "spec_1p1";
vc_enable : string := "single_vc";
enable_slot_register : string := "false";
pcie_mode : string := "shared_mode";
bypass_cdc : string := "false";
enable_rx_reordering : string := "true";
enable_rx_buffer_checking : string := "false";
single_rx_detect_data : bit_vector := B"0000";
single_rx_detect : string := "single_rx_detect";
use_crc_forwarding : string := "false";
bypass_tl : string := "false";
gen123_lane_rate_mode : string := "gen1";
lane_mask : string := "x4";
disable_link_x2_support : string := "false";
national_inst_thru_enhance : string := "true";
hip_hard_reset : string := "enable";
dis_paritychk : string := "enable";
wrong_device_id : string := "disable";
data_pack_rx : string := "disable";
ast_width : string := "rx_tx_64";
rx_sop_ctrl : string := "boundary_64";
rx_ast_parity : string := "disable";
tx_ast_parity : string := "disable";
ltssm_1ms_timeout : string := "disable";
ltssm_freqlocked_check : string := "disable";
deskew_comma : string := "skp_eieos_deskw";
dl_tx_check_parity_edb : string := "disable";
tl_tx_check_parity_msg : string := "disable";
port_link_number_data : bit_vector := B"00000001";
port_link_number : string := "port_link_number";
device_number_data : bit_vector := B"00000";
device_number : string := "device_number";
bypass_clk_switch : string := "false";
core_clk_out_sel : string := "div_1";
core_clk_divider : string := "div_1";
core_clk_source : string := "pll_fixed_clk";
core_clk_sel : string := "pld_clk";
enable_ch0_pclk_out : string := "true";
enable_ch01_pclk_out : string := "pclk_ch0";
pipex1_debug_sel : string := "disable";
pclk_out_sel : string := "pclk";
vendor_id_data : bit_vector := B"1000101110010";
vendor_id : string := "vendor_id";
device_id_data : bit_vector := B"0000000000000001";
device_id : string := "device_id";
revision_id_data : bit_vector := B"00000001";
revision_id : string := "revision_id";
class_code_data : bit_vector := B"111111110000000000000000";
class_code : string := "class_code";
subsystem_vendor_id_data : bit_vector := B"0001000101110010";
subsystem_vendor_id : string := "subsystem_vendor_id";
subsystem_device_id_data : bit_vector := B"0000000000000001";
subsystem_device_id : string := "subsystem_device_id";
no_soft_reset : string := "false";
maximum_current_data : bit_vector := B"000";
maximum_current : string := "maximum_current";
d1_support : string := "false";
d2_support : string := "false";
d0_pme : string := "false";
d1_pme : string := "false";
d2_pme : string := "false";
d3_hot_pme : string := "false";
d3_cold_pme : string := "false";
use_aer : string := "false";
low_priority_vc : string := "single_vc";
vc_arbitration : string := "single_vc";
disable_snoop_packet : string := "false";
max_payload_size : string := "payload_512";
surprise_down_error_support : string := "false";
dll_active_report_support : string := "false";
extend_tag_field : string := "false";
endpoint_l0_latency_data : bit_vector := B"000";
endpoint_l0_latency : string := "endpoint_l0_latency";
endpoint_l1_latency_data : bit_vector := B"000";
endpoint_l1_latency : string := "endpoint_l1_latency";
indicator_data : bit_vector := B"111";
indicator : string := "indicator";
role_based_error_reporting : string := "false";
slot_power_scale_data : bit_vector := B"00";
slot_power_scale : string := "slot_power_scale";
max_link_width : string := "x4";
enable_l1_aspm : string := "false";
enable_l0s_aspm : string := "false";
l1_exit_latency_sameclock_data : bit_vector := B"000";
l1_exit_latency_sameclock : string := "l1_exit_latency_sameclock";
l1_exit_latency_diffclock_data : bit_vector := B"000";
l1_exit_latency_diffclock : string := "l1_exit_latency_diffclock";
hot_plug_support_data : bit_vector := B"0000000";
hot_plug_support : string := "hot_plug_support";
slot_power_limit_data : bit_vector := B"00000000";
slot_power_limit : string := "slot_power_limit";
slot_number_data : bit_vector := B"0000000000000";
slot_number : string := "slot_number";
diffclock_nfts_count_data : bit_vector := B"00000000";
diffclock_nfts_count : string := "diffclock_nfts_count";
sameclock_nfts_count_data : bit_vector := B"00000000";
sameclock_nfts_count : string := "sameclock_nfts_count";
completion_timeout : string := "abcd";
enable_completion_timeout_disable : string := "true";
extended_tag_reset : string := "false";
ecrc_check_capable : string := "true";
ecrc_gen_capable : string := "true";
no_command_completed : string := "true";
msi_multi_message_capable : string := "count_4";
msi_64bit_addressing_capable : string := "true";
msi_masking_capable : string := "false";
msi_support : string := "true";
interrupt_pin : string := "inta";
ena_ido_req : string := "false";
ena_ido_cpl : string := "false";
enable_function_msix_support : string := "true";
msix_table_size_data : bit_vector := B"00000000000";
msix_table_size : string := "msix_table_size";
msix_table_bir_data : bit_vector := B"000";
msix_table_bir : string := "msix_table_bir";
msix_table_offset_data : bit_vector := B"00000000000000000000000000000";
msix_table_offset : string := "msix_table_offset";
msix_pba_bir_data : bit_vector := B"000";
msix_pba_bir : string := "msix_pba_bir";
msix_pba_offset_data : bit_vector := B"00000000000000000000000000000";
msix_pba_offset : string := "msix_pba_offset";
bridge_port_vga_enable : string := "false";
bridge_port_ssid_support : string := "false";
ssvid_data : bit_vector := B"0000000000000000";
ssvid : string := "ssvid";
ssid_data : bit_vector := B"0000000000000000";
ssid : string := "ssid";
eie_before_nfts_count_data : bit_vector := B"0100";
eie_before_nfts_count : string := "eie_before_nfts_count";
gen2_diffclock_nfts_count_data : bit_vector := B"11111111";
gen2_diffclock_nfts_count : string := "gen2_diffclock_nfts_count";
gen2_sameclock_nfts_count_data : bit_vector := B"11111111";
gen2_sameclock_nfts_count : string := "gen2_sameclock_nfts_count";
deemphasis_enable : string := "false";
pcie_spec_version : string := "v2";
l0_exit_latency_sameclock_data : bit_vector := B"110";
l0_exit_latency_sameclock : string := "l0_exit_latency_sameclock";
l0_exit_latency_diffclock_data : bit_vector := B"110";
l0_exit_latency_diffclock : string := "l0_exit_latency_diffclock";
rx_ei_l0s : string := "disable";
l2_async_logic : string := "enable";
aspm_config_management : string := "true";
atomic_op_routing : string := "false";
atomic_op_completer_32bit : string := "false";
atomic_op_completer_64bit : string := "false";
cas_completer_128bit : string := "false";
ltr_mechanism : string := "false";
tph_completer : string := "false";
extended_format_field : string := "true";
atomic_malformed : string := "false";
flr_capability : string := "true";
enable_adapter_half_rate_mode : string := "false";
vc0_clk_enable : string := "true";
vc1_clk_enable : string := "false";
register_pipe_signals : string := "false";
bar0_io_space : string := "false";
bar0_64bit_mem_space : string := "true";
bar0_prefetchable : string := "true";
bar0_size_mask_data : bit_vector := B"1111111111111111111111111111";
bar0_size_mask : string := "bar0_size_mask";
bar1_io_space : string := "false";
bar1_64bit_mem_space : string := "false";
bar1_prefetchable : string := "false";
bar1_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar1_size_mask : string := "bar1_size_mask";
bar2_io_space : string := "false";
bar2_64bit_mem_space : string := "false";
bar2_prefetchable : string := "false";
bar2_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar2_size_mask : string := "bar2_size_mask";
bar3_io_space : string := "false";
bar3_64bit_mem_space : string := "false";
bar3_prefetchable : string := "false";
bar3_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar3_size_mask : string := "bar3_size_mask";
bar4_io_space : string := "false";
bar4_64bit_mem_space : string := "false";
bar4_prefetchable : string := "false";
bar4_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar4_size_mask : string := "bar4_size_mask";
bar5_io_space : string := "false";
bar5_64bit_mem_space : string := "false";
bar5_prefetchable : string := "false";
bar5_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar5_size_mask : string := "bar5_size_mask";
expansion_base_address_register_data : bit_vector := B"00000000000000000000000000000000";
expansion_base_address_register : string := "expansion_base_address_register";
io_window_addr_width : string := "window_32_bit";
prefetchable_mem_window_addr_width : string := "prefetch_32";
skp_os_gen3_count_data : bit_vector := B"00000000000";
skp_os_gen3_count : string := "skp_os_gen3_count";
rx_cdc_almost_empty_data : bit_vector := B"0000";
rx_cdc_almost_empty : string := "rx_cdc_almost_empty";
tx_cdc_almost_empty_data : bit_vector := B"0000";
tx_cdc_almost_empty : string := "tx_cdc_almost_empty";
rx_cdc_almost_full_data : bit_vector := B"0000";
rx_cdc_almost_full : string := "rx_cdc_almost_full";
tx_cdc_almost_full_data : bit_vector := B"0000";
tx_cdc_almost_full : string := "tx_cdc_almost_full";
rx_l0s_count_idl_data : bit_vector := B"00000000";
rx_l0s_count_idl : string := "rx_l0s_count_idl";
cdc_dummy_insert_limit_data : bit_vector := B"0000";
cdc_dummy_insert_limit : string := "cdc_dummy_insert_limit";
ei_delay_powerdown_count_data : bit_vector := B"00001010";
ei_delay_powerdown_count : string := "ei_delay_powerdown_count";
millisecond_cycle_count_data : bit_vector := B"00000000000000000000";
millisecond_cycle_count : string := "millisecond_cycle_count";
skp_os_schedule_count_data : bit_vector := B"00000000000";
skp_os_schedule_count : string := "skp_os_schedule_count";
fc_init_timer_data : bit_vector := B"10000000000";
fc_init_timer : string := "fc_init_timer";
l01_entry_latency_data : bit_vector := B"11111";
l01_entry_latency : string := "l01_entry_latency";
flow_control_update_count_data : bit_vector := B"11110";
flow_control_update_count : string := "flow_control_update_count";
flow_control_timeout_count_data : bit_vector := B"11001000";
flow_control_timeout_count : string := "flow_control_timeout_count";
vc0_rx_flow_ctrl_posted_header_data : bit_vector := B"00110010";
vc0_rx_flow_ctrl_posted_header : string := "vc0_rx_flow_ctrl_posted_header";
vc0_rx_flow_ctrl_posted_data_data : bit_vector := B"000101101000";
vc0_rx_flow_ctrl_posted_data : string := "vc0_rx_flow_ctrl_posted_data";
vc0_rx_flow_ctrl_nonposted_header_data : bit_vector := B"00110110";
vc0_rx_flow_ctrl_nonposted_header : string := "vc0_rx_flow_ctrl_nonposted_header";
vc0_rx_flow_ctrl_nonposted_data_data : bit_vector := B"00000000";
vc0_rx_flow_ctrl_nonposted_data : string := "vc0_rx_flow_ctrl_nonposted_data";
vc0_rx_flow_ctrl_compl_header_data : bit_vector := B"01110000";
vc0_rx_flow_ctrl_compl_header : string := "vc0_rx_flow_ctrl_compl_header";
vc0_rx_flow_ctrl_compl_data_data : bit_vector := B"000111000000";
vc0_rx_flow_ctrl_compl_data : string := "vc0_rx_flow_ctrl_compl_data";
rx_ptr0_posted_dpram_min_data : bit_vector := B"00000000000";
rx_ptr0_posted_dpram_min : string := "rx_ptr0_posted_dpram_min";
rx_ptr0_posted_dpram_max_data : bit_vector := B"00000000000";
rx_ptr0_posted_dpram_max : string := "rx_ptr0_posted_dpram_max";
rx_ptr0_nonposted_dpram_min_data : bit_vector := B"00000000000";
rx_ptr0_nonposted_dpram_min : string := "rx_ptr0_nonposted_dpram_min";
rx_ptr0_nonposted_dpram_max_data : bit_vector := B"00000000000";
rx_ptr0_nonposted_dpram_max : string := "rx_ptr0_nonposted_dpram_max";
retry_buffer_last_active_address_data : bit_vector := B"1111111111";
retry_buffer_last_active_address : string := "retry_buffer_last_active_address";
retry_buffer_memory_settings_data : bit_vector := B"000000000000000000000000000000";
retry_buffer_memory_settings : string := "retry_buffer_memory_settings";
vc0_rx_buffer_memory_settings_data : bit_vector := B"000000000000000000000000000000";
vc0_rx_buffer_memory_settings : string := "vc0_rx_buffer_memory_settings";
bist_memory_settings_data : bit_vector := B"000000000000000000000000000000000000000000000000000000000000000000000000000";
bist_memory_settings : string := "bist_memory_settings";
credit_buffer_allocation_aux : string := "balanced";
iei_enable_settings : string := "gen2_infei_infsd_gen1_infei_sd";
vsec_id_data : bit_vector := B"0001000101110010";
vsec_id : string := "vsec_id";
cvp_rate_sel : string := "full_rate";
hard_reset_bypass : string := "false";
cvp_data_compressed : string := "false";
cvp_data_encrypted : string := "false";
cvp_mode_reset : string := "false";
cvp_clk_reset : string := "false";
vsec_cap_data : bit_vector := B"0000";
vsec_cap : string := "vsec_cap";
jtag_id_data : bit_vector := B"00000000000000000000000000000000";
jtag_id : string := "jtag_id";
user_id_data : bit_vector := B"0000000000000000";
user_id : string := "user_id";
cseb_extend_pci : string := "false";
cseb_extend_pcie : string := "false";
cseb_cpl_status_during_cvp : string := "config_retry_status";
cseb_route_to_avl_rx_st : string := "cseb";
cseb_config_bypass : string := "disable";
cseb_cpl_tag_checking : string := "enable";
cseb_bar_match_checking : string := "enable";
cseb_min_error_checking : string := "false";
cseb_temp_busy_crs : string := "completer_abort";
cseb_disable_auto_crs : string := "false";
gen3_diffclock_nfts_count_data : bit_vector := B"10000000";
gen3_diffclock_nfts_count : string := "g3_diffclock_nfts_count";
gen3_sameclock_nfts_count_data : bit_vector := B"10000000";
gen3_sameclock_nfts_count : string := "g3_sameclock_nfts_count";
gen3_coeff_errchk : string := "enable";
gen3_paritychk : string := "enable";
gen3_coeff_delay_count_data : bit_vector := B"1111101";
gen3_coeff_delay_count : string := "g3_coeff_dly_count";
gen3_coeff_1_data : bit_vector := B"000000000000000000";
gen3_coeff_1 : string := "g3_coeff_1";
gen3_coeff_1_sel : string := "coeff_1";
gen3_coeff_1_preset_hint_data : bit_vector := B"000";
gen3_coeff_1_preset_hint : string := "g3_coeff_1_prst_hint";
gen3_coeff_1_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_1_nxtber_more : string := "g3_coeff_1_nxtber_more";
gen3_coeff_1_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_1_nxtber_less : string := "g3_coeff_1_nxtber_less";
gen3_coeff_1_reqber_data : bit_vector := B"00000";
gen3_coeff_1_reqber : string := "g3_coeff_1_reqber";
gen3_coeff_1_ber_meas_data : bit_vector := B"000000";
gen3_coeff_1_ber_meas : string := "g3_coeff_1_ber_meas";
gen3_coeff_2_data : bit_vector := B"000000000000000000";
gen3_coeff_2 : string := "g3_coeff_2";
gen3_coeff_2_sel : string := "coeff_2";
gen3_coeff_2_preset_hint_data : bit_vector := B"000";
gen3_coeff_2_preset_hint : string := "g3_coeff_2_prst_hint";
gen3_coeff_2_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_2_nxtber_more : string := "g3_coeff_2_nxtber_more";
gen3_coeff_2_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_2_nxtber_less : string := "g3_coeff_2_nxtber_less";
gen3_coeff_2_reqber_data : bit_vector := B"00000";
gen3_coeff_2_reqber : string := "g3_coeff_2_reqber";
gen3_coeff_2_ber_meas_data : bit_vector := B"000000";
gen3_coeff_2_ber_meas : string := "g3_coeff_1_ber_meas";
gen3_coeff_3_data : bit_vector := B"000000000000000000";
gen3_coeff_3 : string := "g3_coeff_3";
gen3_coeff_3_sel : string := "coeff_3";
gen3_coeff_3_preset_hint_data : bit_vector := B"000";
gen3_coeff_3_preset_hint : string := "g3_coeff_3_prst_hint";
gen3_coeff_3_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_3_nxtber_more : string := "g3_coeff_3_nxtber_more";
gen3_coeff_3_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_3_nxtber_less : string := "g3_coeff_3_nxtber_less";
gen3_coeff_3_reqber_data : bit_vector := B"00000";
gen3_coeff_3_reqber : string := "g3_coeff_3_reqber";
gen3_coeff_3_ber_meas_data : bit_vector := B"000000";
gen3_coeff_3_ber_meas : string := "g3_coeff_3_ber_meas";
gen3_coeff_4_data : bit_vector := B"000000000000000000";
gen3_coeff_4 : string := "g3_coeff_4";
gen3_coeff_4_sel : string := "coeff_4";
gen3_coeff_4_preset_hint_data : bit_vector := B"000";
gen3_coeff_4_preset_hint : string := "g3_coeff_4_prst_hint";
gen3_coeff_4_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_4_nxtber_more : string := "g3_coeff_4_nxtber_more";
gen3_coeff_4_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_4_nxtber_less : string := "g3_coeff_4_nxtber_less";
gen3_coeff_4_reqber_data : bit_vector := B"00000";
gen3_coeff_4_reqber : string := "g3_coeff_4_reqber";
gen3_coeff_4_ber_meas_data : bit_vector := B"000000";
gen3_coeff_4_ber_meas : string := "g3_coeff_4_ber_meas";
gen3_coeff_5_data : bit_vector := B"000000000000000000";
gen3_coeff_5 : string := "g3_coeff_5";
gen3_coeff_5_sel : string := "coeff_5";
gen3_coeff_5_preset_hint_data : bit_vector := B"000";
gen3_coeff_5_preset_hint : string := "g3_coeff_5_prst_hint";
gen3_coeff_5_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_5_nxtber_more : string := "g3_coeff_5_nxtber_more";
gen3_coeff_5_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_5_nxtber_less : string := "g3_coeff_5_nxtber_less";
gen3_coeff_5_reqber_data : bit_vector := B"00000";
gen3_coeff_5_reqber : string := "g3_coeff_5_reqber";
gen3_coeff_5_ber_meas_data : bit_vector := B"000000";
gen3_coeff_5_ber_meas : string := "g3_coeff_5_ber_meas";
gen3_coeff_6_data : bit_vector := B"000000000000000000";
gen3_coeff_6 : string := "g3_coeff_6";
gen3_coeff_6_sel : string := "coeff_6";
gen3_coeff_6_preset_hint_data : bit_vector := B"000";
gen3_coeff_6_preset_hint : string := "g3_coeff_6_prst_hint";
gen3_coeff_6_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_6_nxtber_more : string := "g3_coeff_6_nxtber_more";
gen3_coeff_6_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_6_nxtber_less : string := "g3_coeff_6_nxtber_less";
gen3_coeff_6_reqber_data : bit_vector := B"00000";
gen3_coeff_6_reqber : string := "g3_coeff_6_reqber";
gen3_coeff_6_ber_meas_data : bit_vector := B"000000";
gen3_coeff_6_ber_meas : string := "g3_coeff_6_ber_meas";
gen3_coeff_7_data : bit_vector := B"000000000000000000";
gen3_coeff_7 : string := "g3_coeff_7";
gen3_coeff_7_sel : string := "coeff_7";
gen3_coeff_7_preset_hint_data : bit_vector := B"000";
gen3_coeff_7_preset_hint : string := "g3_coeff_7_prst_hint";
gen3_coeff_7_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_7_nxtber_more : string := "g3_coeff_7_nxtber_more";
gen3_coeff_7_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_7_nxtber_less : string := "g3_coeff_7_nxtber_less";
gen3_coeff_7_reqber_data : bit_vector := B"00000";
gen3_coeff_7_reqber : string := "g3_coeff_7_reqber";
gen3_coeff_7_ber_meas_data : bit_vector := B"000000";
gen3_coeff_7_ber_meas : string := "g3_coeff_7_ber_meas";
gen3_coeff_8_data : bit_vector := B"000000000000000000";
gen3_coeff_8 : string := "g3_coeff_8";
gen3_coeff_8_sel : string := "coeff_8";
gen3_coeff_8_preset_hint_data : bit_vector := B"000";
gen3_coeff_8_preset_hint : string := "g3_coeff_8_prst_hint";
gen3_coeff_8_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_8_nxtber_more : string := "g3_coeff_8_nxtber_more";
gen3_coeff_8_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_8_nxtber_less : string := "g3_coeff_8_nxtber_less";
gen3_coeff_8_reqber_data : bit_vector := B"00000";
gen3_coeff_8_reqber : string := "g3_coeff_8_reqber";
gen3_coeff_8_ber_meas_data : bit_vector := B"000000";
gen3_coeff_8_ber_meas : string := "g3_coeff_8_ber_meas";
gen3_coeff_9_data : bit_vector := B"000000000000000000";
gen3_coeff_9 : string := "g3_coeff_9";
gen3_coeff_9_sel : string := "coeff_9";
gen3_coeff_9_preset_hint_data : bit_vector := B"000";
gen3_coeff_9_preset_hint : string := "g3_coeff_9_prst_hint";
gen3_coeff_9_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_9_nxtber_more : string := "g3_coeff_9_nxtber_more";
gen3_coeff_9_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_9_nxtber_less : string := "g3_coeff_9_nxtber_less";
gen3_coeff_9_reqber_data : bit_vector := B"00000";
gen3_coeff_9_reqber : string := "g3_coeff_9_reqber";
gen3_coeff_9_ber_meas_data : bit_vector := B"000000";
gen3_coeff_9_ber_meas : string := "g3_coeff_9_ber_meas";
gen3_coeff_10_data : bit_vector := B"000000000000000000";
gen3_coeff_10 : string := "g3_coeff_10";
gen3_coeff_10_sel : string := "coeff_10";
gen3_coeff_10_preset_hint_data : bit_vector := B"000";
gen3_coeff_10_preset_hint : string := "g3_coeff_10_prst_hint";
gen3_coeff_10_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_10_nxtber_more : string := "g3_coeff_10_nxtber_more";
gen3_coeff_10_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_10_nxtber_less : string := "g3_coeff_10_nxtber_less";
gen3_coeff_10_reqber_data : bit_vector := B"00000";
gen3_coeff_10_reqber : string := "g3_coeff_10_reqber";
gen3_coeff_10_ber_meas_data : bit_vector := B"000000";
gen3_coeff_10_ber_meas : string := "g3_coeff_10_ber_meas";
gen3_coeff_11_data : bit_vector := B"000000000000000000";
gen3_coeff_11 : string := "g3_coeff_11";
gen3_coeff_11_sel : string := "coeff_11";
gen3_coeff_11_preset_hint_data : bit_vector := B"000";
gen3_coeff_11_preset_hint : string := "g3_coeff_11_prst_hint";
gen3_coeff_11_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_11_nxtber_more : string := "g3_coeff_11_nxtber_more";
gen3_coeff_11_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_11_nxtber_less : string := "g3_coeff_11_nxtber_less";
gen3_coeff_11_reqber_data : bit_vector := B"00000";
gen3_coeff_11_reqber : string := "g3_coeff_11_reqber";
gen3_coeff_11_ber_meas_data : bit_vector := B"000000";
gen3_coeff_11_ber_meas : string := "g3_coeff_11_ber_meas";
gen3_coeff_12_data : bit_vector := B"000000000000000000";
gen3_coeff_12 : string := "g3_coeff_12";
gen3_coeff_12_sel : string := "coeff_12";
gen3_coeff_12_preset_hint_data : bit_vector := B"000";
gen3_coeff_12_preset_hint : string := "g3_coeff_12_prst_hint";
gen3_coeff_12_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_12_nxtber_more : string := "g3_coeff_12_nxtber_more";
gen3_coeff_12_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_12_nxtber_less : string := "g3_coeff_12_nxtber_less";
gen3_coeff_12_reqber_data : bit_vector := B"00000";
gen3_coeff_12_reqber : string := "g3_coeff_12_reqber";
gen3_coeff_12_ber_meas_data : bit_vector := B"000000";
gen3_coeff_12_ber_meas : string := "g3_coeff_12_ber_meas";
gen3_coeff_13_data : bit_vector := B"000000000000000000";
gen3_coeff_13 : string := "g3_coeff_13";
gen3_coeff_13_sel : string := "coeff_13";
gen3_coeff_13_preset_hint_data : bit_vector := B"000";
gen3_coeff_13_preset_hint : string := "g3_coeff_13_prst_hint";
gen3_coeff_13_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_13_nxtber_more : string := "g3_coeff_13_nxtber_more";
gen3_coeff_13_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_13_nxtber_less : string := "g3_coeff_13_nxtber_less";
gen3_coeff_13_reqber_data : bit_vector := B"00000";
gen3_coeff_13_reqber : string := "g3_coeff_13_reqber";
gen3_coeff_13_ber_meas_data : bit_vector := B"000000";
gen3_coeff_13_ber_meas : string := "g3_coeff_13_ber_meas";
gen3_coeff_14_data : bit_vector := B"000000000000000000";
gen3_coeff_14 : string := "g3_coeff_14";
gen3_coeff_14_sel : string := "coeff_14";
gen3_coeff_14_preset_hint_data : bit_vector := B"000";
gen3_coeff_14_preset_hint : string := "g3_coeff_14_prst_hint";
gen3_coeff_14_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_14_nxtber_more : string := "g3_coeff_14_nxtber_more";
gen3_coeff_14_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_14_nxtber_less : string := "g3_coeff_14_nxtber_less";
gen3_coeff_14_reqber_data : bit_vector := B"00000";
gen3_coeff_14_reqber : string := "g3_coeff_14_reqber";
gen3_coeff_14_ber_meas_data : bit_vector := B"000000";
gen3_coeff_14_ber_meas : string := "g3_coeff_14_ber_meas";
gen3_coeff_15_data : bit_vector := B"000000000000000000";
gen3_coeff_15 : string := "g3_coeff_15";
gen3_coeff_15_sel : string := "coeff_15";
gen3_coeff_15_preset_hint_data : bit_vector := B"000";
gen3_coeff_15_preset_hint : string := "g3_coeff_15_prst_hint";
gen3_coeff_15_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_15_nxtber_more : string := "g3_coeff_15_nxtber_more";
gen3_coeff_15_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_15_nxtber_less : string := "g3_coeff_15_nxtber_less";
gen3_coeff_15_reqber_data : bit_vector := B"00000";
gen3_coeff_15_reqber : string := "g3_coeff_15_reqber";
gen3_coeff_15_ber_meas_data : bit_vector := B"000000";
gen3_coeff_15_ber_meas : string := "g3_coeff_15_ber_meas";
gen3_coeff_16_data : bit_vector := B"000000000000000000";
gen3_coeff_16 : string := "g3_coeff_16";
gen3_coeff_16_sel : string := "coeff_16";
gen3_coeff_16_preset_hint_data : bit_vector := B"000";
gen3_coeff_16_preset_hint : string := "g3_coeff_16_prst_hint";
gen3_coeff_16_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_16_nxtber_more : string := "g3_coeff_16_nxtber_more";
gen3_coeff_16_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_16_nxtber_less : string := "g3_coeff_16_nxtber_less";
gen3_coeff_16_reqber_data : bit_vector := B"00000";
gen3_coeff_16_reqber : string := "g3_coeff_16_reqber";
gen3_coeff_16_ber_meas_data : bit_vector := B"000000";
gen3_coeff_16_ber_meas : string := "g3_coeff_16_ber_meas";
gen3_preset_coeff_1_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_1 : string := "g3_prst_coeff_1";
gen3_preset_coeff_2_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_2 : string := "g3_prst_coeff_2";
gen3_preset_coeff_3_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_3 : string := "g3_prst_coeff_3";
gen3_preset_coeff_4_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_4 : string := "g3_prst_coeff_4";
gen3_preset_coeff_5_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_5 : string := "g3_prst_coeff_5";
gen3_preset_coeff_6_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_6 : string := "g3_prst_coeff_6";
gen3_preset_coeff_7_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_7 : string := "g3_prst_coeff_7";
gen3_preset_coeff_8_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_8 : string := "g3_prst_coeff_8";
gen3_preset_coeff_9_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_9 : string := "g3_prst_coeff_9";
gen3_preset_coeff_10_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_10 : string := "g3_prst_coeff_10";
gen3_rxfreqlock_counter_data : bit_vector := "00000000000000000000";
gen3_rxfreqlock_counter : string := "g3_rxfreqlock_count";
rstctrl_pld_clr : string := "false";-- "false", "true".
rstctrl_debug_en : string := "false";-- "false", "true".
rstctrl_force_inactive_rst : string := "false";-- "false", "true".
rstctrl_perst_enable : string := "level";-- "level", "neg_edge", "not_used".
hrdrstctrl_en : string := "hrdrstctrl_dis";--"hrdrstctrl_dis", "hrdrstctrl_en".
rstctrl_hip_ep : string := "hip_ep"; --"hip_ep", "hip_not_ep".
rstctrl_hard_block_enable : string := "hard_rst_ctl";--"hard_rst_ctl", "pld_rst_ctl".
rstctrl_rx_pma_rstb_inv : string := "false";--"false", "true".
rstctrl_tx_pma_rstb_inv : string := "false";--"false", "true".
rstctrl_rx_pcs_rst_n_inv : string := "false";--"false", "true".
rstctrl_tx_pcs_rst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_crst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_srst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_rst_n_inv : string := "false";--"false", "true".
rstctrl_tx_pma_syncp_inv : string := "false";--"false", "true".
rstctrl_1us_count_fref_clk : string := "rstctrl_1us_cnt";--
rstctrl_1us_count_fref_clk_value : bit_vector := B"00000000000000111111";--
rstctrl_1ms_count_fref_clk : string := "rstctrl_1ms_cnt";--
rstctrl_1ms_count_fref_clk_value : bit_vector := B"00001111010000100100";--
rstctrl_off_cal_done_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
rstctrl_rx_pma_rstb_cmu_select : string := "not_active";-- "ch1cmu_sel", "ch4cmu_sel", "ch4_10cmu_sel", "not_active".
rstctrl_rx_pll_freq_lock_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active", "ch0_phs_sel", "ch01_phs_sel", "ch0123_phs_sel", "ch0123_5678_phs_sel".
rstctrl_mask_tx_pll_lock_select : string := "not_active";-- "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
rstctrl_rx_pll_lock_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
rstctrl_perstn_select : string := "perstn_pin";-- "perstn_pin", "perstn_pld".
rstctrl_tx_lc_pll_rstb_select : string := "not_active";-- "ch1_out", "ch7_out", "not_active".
rstctrl_fref_clk_select : string := "ch0_sel";-- "ch0_sel", "ch1_sel", "ch2_sel", "ch3_sel", "ch4_sel", "ch5_sel", "ch6_sel", "ch7_sel", "ch8_sel", "ch9_sel", "ch10_sel", "ch11_sel".
rstctrl_off_cal_en_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch0123_5678_out", "not_active".
rstctrl_tx_pma_syncp_select : string := "not_active";-- "ch1_out", "ch4_out", "ch4_10_out", "not_active".
rstctrl_rx_pcs_rst_n_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
rstctrl_tx_cmu_pll_lock_select : string := "not_active";-- "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
rstctrl_tx_pcs_rst_n_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
rstctrl_tx_lc_pll_lock_select : string := "not_active";-- "ch1_sel", "ch7_sel", "not_active".
rstctrl_timer_a : string := "rstctrl_timer_a";
rstctrl_timer_a_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_a_value : bit_vector := B"00000001" ;
rstctrl_timer_b : string := "rstctrl_timer_b";
rstctrl_timer_b_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_b_value : bit_vector := B"00000001";
rstctrl_timer_c : string := "rstctrl_timer_c";
rstctrl_timer_c_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_c_value : bit_vector := B"00000001";
rstctrl_timer_d : string := "rstctrl_timer_d";
rstctrl_timer_d_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_d_value : bit_vector := B"00000001";
rstctrl_timer_e : string := "rstctrl_timer_e";
rstctrl_timer_e_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_e_value : bit_vector := B"00000001";
rstctrl_timer_f : string := "rstctrl_timer_f";
rstctrl_timer_f_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_f_value : bit_vector := B"00000001";
rstctrl_timer_g : string := "rstctrl_timer_g";
rstctrl_timer_g_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_g_value : bit_vector := B"00000001";
rstctrl_timer_h : string := "rstctrl_timer_h";
rstctrl_timer_h_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_h_value : bit_vector := B"00000001";
rstctrl_timer_i : string := "rstctrl_timer_i";
rstctrl_timer_i_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_i_value : bit_vector := B"00000001";
rstctrl_timer_j : string := "rstctrl_timer_j";
rstctrl_timer_j_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_j_value : bit_vector := B"00000001"
);
port (
dpriostatus : out std_logic_vector(15 downto 0);
lmidout : out std_logic_vector(31 downto 0);
lmiack : out std_logic_vector(0 downto 0);
lmirden : in std_logic_vector(0 downto 0);
lmiwren : in std_logic_vector(0 downto 0);
lmiaddr : in std_logic_vector(11 downto 0);
lmidin : in std_logic_vector(31 downto 0);
flrreset : in std_logic_vector(0 downto 0);
flrsts : out std_logic_vector(0 downto 0);
resetstatus : out std_logic_vector(0 downto 0);
l2exit : out std_logic_vector(0 downto 0);
hotrstexit : out std_logic_vector(0 downto 0);
hiphardreset : in std_logic_vector(0 downto 0);
dlupexit : out std_logic_vector(0 downto 0);
coreclkout : out std_logic_vector(0 downto 0);
pldclk : in std_logic_vector(0 downto 0);
pldsrst : in std_logic_vector(0 downto 0);
pldrst : in std_logic_vector(0 downto 0);
pclkch0 : in std_logic_vector(0 downto 0);
pclkch1 : in std_logic_vector(0 downto 0);
pclkcentral : in std_logic_vector(0 downto 0);
pllfixedclkch0 : in std_logic_vector(0 downto 0);
pllfixedclkch1 : in std_logic_vector(0 downto 0);
pllfixedclkcentral : in std_logic_vector(0 downto 0);
phyrst : in std_logic_vector(0 downto 0);
physrst : in std_logic_vector(0 downto 0);
coreclkin : in std_logic_vector(0 downto 0);
corerst : in std_logic_vector(0 downto 0);
corepor : in std_logic_vector(0 downto 0);
corecrst : in std_logic_vector(0 downto 0);
coresrst : in std_logic_vector(0 downto 0);
swdnout : out std_logic_vector(6 downto 0);
swupout : out std_logic_vector(2 downto 0);
swdnin : in std_logic_vector(2 downto 0);
swupin : in std_logic_vector(6 downto 0);
swctmod : in std_logic_vector(1 downto 0);
rxstdata : out std_logic_vector(255 downto 0);
rxstparity : out std_logic_vector(31 downto 0);
rxstbe : out std_logic_vector(31 downto 0);
rxsterr : out std_logic_vector(3 downto 0);
rxstsop : out std_logic_vector(3 downto 0);
rxsteop : out std_logic_vector(3 downto 0);
rxstempty : out std_logic_vector(1 downto 0);
rxstvalid : out std_logic_vector(3 downto 0);
rxstbardec1 : out std_logic_vector(7 downto 0);
rxstbardec2 : out std_logic_vector(7 downto 0);
rxstmask : in std_logic_vector(0 downto 0);
rxstready : in std_logic_vector(0 downto 0);
txstready : out std_logic_vector(0 downto 0);
txcredfchipcons : out std_logic_vector(5 downto 0);
txcredfcinfinite : out std_logic_vector(5 downto 0);
txcredhdrfcp : out std_logic_vector(7 downto 0);
txcreddatafcp : out std_logic_vector(11 downto 0);
txcredhdrfcnp : out std_logic_vector(7 downto 0);
txcreddatafcnp : out std_logic_vector(11 downto 0);
txcredhdrfccp : out std_logic_vector(7 downto 0);
txcreddatafccp : out std_logic_vector(11 downto 0);
txstdata : in std_logic_vector(255 downto 0);
txstparity : in std_logic_vector(31 downto 0);
txsterr : in std_logic_vector(3 downto 0);
txstsop : in std_logic_vector(3 downto 0);
txsteop : in std_logic_vector(3 downto 0);
txstempty : in std_logic_vector(1 downto 0);
txstvalid : in std_logic_vector(0 downto 0);
r2cuncecc : out std_logic_vector(0 downto 0);
rxcorrecc : out std_logic_vector(0 downto 0);
retryuncecc : out std_logic_vector(0 downto 0);
retrycorrecc : out std_logic_vector(0 downto 0);
rxparerr : out std_logic_vector(0 downto 0);
txparerr : out std_logic_vector(1 downto 0);
r2cparerr : out std_logic_vector(0 downto 0);
pmetosr : out std_logic_vector(0 downto 0);
pmetocr : in std_logic_vector(0 downto 0);
pmevent : in std_logic_vector(0 downto 0);
pmdata : in std_logic_vector(9 downto 0);
pmauxpwr : in std_logic_vector(0 downto 0);
tlcfgsts : out std_logic_vector(52 downto 0);
tlcfgctl : out std_logic_vector(31 downto 0);
tlcfgadd : out std_logic_vector(3 downto 0);
appintaack : out std_logic_vector(0 downto 0);
appintasts : in std_logic_vector(0 downto 0);
intstatus : out std_logic_vector(3 downto 0);
appmsiack : out std_logic_vector(0 downto 0);
appmsireq : in std_logic_vector(0 downto 0);
appmsitc : in std_logic_vector(2 downto 0);
appmsinum : in std_logic_vector(4 downto 0);
aermsinum : in std_logic_vector(4 downto 0);
pexmsinum : in std_logic_vector(4 downto 0);
hpgctrler : in std_logic_vector(4 downto 0);
cfglink2csrpld : in std_logic_vector(12 downto 0);
cfgprmbuspld : in std_logic_vector(7 downto 0);
csebisshadow : out std_logic_vector(0 downto 0);
csebwrdata : out std_logic_vector(31 downto 0);
csebwrdataparity : out std_logic_vector(3 downto 0);
csebbe : out std_logic_vector(3 downto 0);
csebaddr : out std_logic_vector(32 downto 0);
csebaddrparity : out std_logic_vector(4 downto 0);
csebwren : out std_logic_vector(0 downto 0);
csebrden : out std_logic_vector(0 downto 0);
csebwrrespreq : out std_logic_vector(0 downto 0);
csebrddata : in std_logic_vector(31 downto 0);
csebrddataparity : in std_logic_vector(3 downto 0);
csebwaitrequest : in std_logic_vector(0 downto 0);
csebwrrespvalid : in std_logic_vector(0 downto 0);
csebwrresponse : in std_logic_vector(4 downto 0);
csebrdresponse : in std_logic_vector(4 downto 0);
dlup : out std_logic_vector(0 downto 0);
testouthip : out std_logic_vector(255 downto 0);
testout1hip : out std_logic_vector(63 downto 0);
ev1us : out std_logic_vector(0 downto 0);
ev128ns : out std_logic_vector(0 downto 0);
wakeoen : out std_logic_vector(0 downto 0);
serrout : out std_logic_vector(0 downto 0);
ltssmstate : out std_logic_vector(4 downto 0);
laneact : out std_logic_vector(3 downto 0);
currentspeed : out std_logic_vector(1 downto 0);
slotclkcfg : in std_logic_vector(0 downto 0);
mode : in std_logic_vector(1 downto 0);
testinhip : in std_logic_vector(31 downto 0);
testin1hip : in std_logic_vector(31 downto 0);
cplpending : in std_logic_vector(0 downto 0);
cplerr : in std_logic_vector(6 downto 0);
appinterr : in std_logic_vector(1 downto 0);
egressblkerr : in std_logic_vector(0 downto 0);
pmexitd0ack : in std_logic_vector(0 downto 0);
pmexitd0req : out std_logic_vector(0 downto 0);
currentcoeff0 : out std_logic_vector(17 downto 0);
currentcoeff1 : out std_logic_vector(17 downto 0);
currentcoeff2 : out std_logic_vector(17 downto 0);
currentcoeff3 : out std_logic_vector(17 downto 0);
currentcoeff4 : out std_logic_vector(17 downto 0);
currentcoeff5 : out std_logic_vector(17 downto 0);
currentcoeff6 : out std_logic_vector(17 downto 0);
currentcoeff7 : out std_logic_vector(17 downto 0);
currentrxpreset0 : out std_logic_vector(2 downto 0);
currentrxpreset1 : out std_logic_vector(2 downto 0);
currentrxpreset2 : out std_logic_vector(2 downto 0);
currentrxpreset3 : out std_logic_vector(2 downto 0);
currentrxpreset4 : out std_logic_vector(2 downto 0);
currentrxpreset5 : out std_logic_vector(2 downto 0);
currentrxpreset6 : out std_logic_vector(2 downto 0);
currentrxpreset7 : out std_logic_vector(2 downto 0);
rate0 : out std_logic_vector(1 downto 0);
rate1 : out std_logic_vector(1 downto 0);
rate2 : out std_logic_vector(1 downto 0);
rate3 : out std_logic_vector(1 downto 0);
rate4 : out std_logic_vector(1 downto 0);
rate5 : out std_logic_vector(1 downto 0);
rate6 : out std_logic_vector(1 downto 0);
rate7 : out std_logic_vector(1 downto 0);
ratectrl : out std_logic_vector(1 downto 0);
ratetiedtognd : out std_logic_vector(0 downto 0);
eidleinfersel0 : out std_logic_vector(2 downto 0);
eidleinfersel1 : out std_logic_vector(2 downto 0);
eidleinfersel2 : out std_logic_vector(2 downto 0);
eidleinfersel3 : out std_logic_vector(2 downto 0);
eidleinfersel4 : out std_logic_vector(2 downto 0);
eidleinfersel5 : out std_logic_vector(2 downto 0);
eidleinfersel6 : out std_logic_vector(2 downto 0);
eidleinfersel7 : out std_logic_vector(2 downto 0);
txdata0 : out std_logic_vector(31 downto 0);
txdatak0 : out std_logic_vector(3 downto 0);
txdetectrx0 : out std_logic_vector(0 downto 0);
txelecidle0 : out std_logic_vector(0 downto 0);
txcompl0 : out std_logic_vector(0 downto 0);
rxpolarity0 : out std_logic_vector(0 downto 0);
powerdown0 : out std_logic_vector(1 downto 0);
txdataskip0 : out std_logic_vector(0 downto 0);
txblkst0 : out std_logic_vector(0 downto 0);
txsynchd0 : out std_logic_vector(1 downto 0);
txdeemph0 : out std_logic_vector(0 downto 0);
txmargin0 : out std_logic_vector(2 downto 0);
rxdata0 : in std_logic_vector(31 downto 0);
rxdatak0 : in std_logic_vector(3 downto 0);
rxvalid0 : in std_logic_vector(0 downto 0);
phystatus0 : in std_logic_vector(0 downto 0);
rxelecidle0 : in std_logic_vector(0 downto 0);
rxstatus0 : in std_logic_vector(2 downto 0);
rxdataskip0 : in std_logic_vector(0 downto 0);
rxblkst0 : in std_logic_vector(0 downto 0);
rxsynchd0 : in std_logic_vector(1 downto 0);
rxfreqlocked0 : in std_logic_vector(0 downto 0);
txdata1 : out std_logic_vector(31 downto 0);
txdatak1 : out std_logic_vector(3 downto 0);
txdetectrx1 : out std_logic_vector(0 downto 0);
txelecidle1 : out std_logic_vector(0 downto 0);
txcompl1 : out std_logic_vector(0 downto 0);
rxpolarity1 : out std_logic_vector(0 downto 0);
powerdown1 : out std_logic_vector(1 downto 0);
txdataskip1 : out std_logic_vector(0 downto 0);
txblkst1 : out std_logic_vector(0 downto 0);
txsynchd1 : out std_logic_vector(1 downto 0);
txdeemph1 : out std_logic_vector(0 downto 0);
txmargin1 : out std_logic_vector(2 downto 0);
rxdata1 : in std_logic_vector(31 downto 0);
rxdatak1 : in std_logic_vector(3 downto 0);
rxvalid1 : in std_logic_vector(0 downto 0);
phystatus1 : in std_logic_vector(0 downto 0);
rxelecidle1 : in std_logic_vector(0 downto 0);
rxstatus1 : in std_logic_vector(2 downto 0);
rxdataskip1 : in std_logic_vector(0 downto 0);
rxblkst1 : in std_logic_vector(0 downto 0);
rxsynchd1 : in std_logic_vector(1 downto 0);
rxfreqlocked1 : in std_logic_vector(0 downto 0);
txdata2 : out std_logic_vector(31 downto 0);
txdatak2 : out std_logic_vector(3 downto 0);
txdetectrx2 : out std_logic_vector(0 downto 0);
txelecidle2 : out std_logic_vector(0 downto 0);
txcompl2 : out std_logic_vector(0 downto 0);
rxpolarity2 : out std_logic_vector(0 downto 0);
powerdown2 : out std_logic_vector(1 downto 0);
txdataskip2 : out std_logic_vector(0 downto 0);
txblkst2 : out std_logic_vector(0 downto 0);
txsynchd2 : out std_logic_vector(1 downto 0);
txdeemph2 : out std_logic_vector(0 downto 0);
txmargin2 : out std_logic_vector(2 downto 0);
rxdata2 : in std_logic_vector(31 downto 0);
rxdatak2 : in std_logic_vector(3 downto 0);
rxvalid2 : in std_logic_vector(0 downto 0);
phystatus2 : in std_logic_vector(0 downto 0);
rxelecidle2 : in std_logic_vector(0 downto 0);
rxstatus2 : in std_logic_vector(2 downto 0);
rxdataskip2 : in std_logic_vector(0 downto 0);
rxblkst2 : in std_logic_vector(0 downto 0);
rxsynchd2 : in std_logic_vector(1 downto 0);
rxfreqlocked2 : in std_logic_vector(0 downto 0);
txdata3 : out std_logic_vector(31 downto 0);
txdatak3 : out std_logic_vector(3 downto 0);
txdetectrx3 : out std_logic_vector(0 downto 0);
txelecidle3 : out std_logic_vector(0 downto 0);
txcompl3 : out std_logic_vector(0 downto 0);
rxpolarity3 : out std_logic_vector(0 downto 0);
powerdown3 : out std_logic_vector(1 downto 0);
txdataskip3 : out std_logic_vector(0 downto 0);
txblkst3 : out std_logic_vector(0 downto 0);
txsynchd3 : out std_logic_vector(1 downto 0);
txdeemph3 : out std_logic_vector(0 downto 0);
txmargin3 : out std_logic_vector(2 downto 0);
rxdata3 : in std_logic_vector(31 downto 0);
rxdatak3 : in std_logic_vector(3 downto 0);
rxvalid3 : in std_logic_vector(0 downto 0);
phystatus3 : in std_logic_vector(0 downto 0);
rxelecidle3 : in std_logic_vector(0 downto 0);
rxstatus3 : in std_logic_vector(2 downto 0);
rxdataskip3 : in std_logic_vector(0 downto 0);
rxblkst3 : in std_logic_vector(0 downto 0);
rxsynchd3 : in std_logic_vector(1 downto 0);
rxfreqlocked3 : in std_logic_vector(0 downto 0);
txdata4 : out std_logic_vector(31 downto 0);
txdatak4 : out std_logic_vector(3 downto 0);
txdetectrx4 : out std_logic_vector(0 downto 0);
txelecidle4 : out std_logic_vector(0 downto 0);
txcompl4 : out std_logic_vector(0 downto 0);
rxpolarity4 : out std_logic_vector(0 downto 0);
powerdown4 : out std_logic_vector(1 downto 0);
txdataskip4 : out std_logic_vector(0 downto 0);
txblkst4 : out std_logic_vector(0 downto 0);
txsynchd4 : out std_logic_vector(1 downto 0);
txdeemph4 : out std_logic_vector(0 downto 0);
txmargin4 : out std_logic_vector(2 downto 0);
rxdata4 : in std_logic_vector(31 downto 0);
rxdatak4 : in std_logic_vector(3 downto 0);
rxvalid4 : in std_logic_vector(0 downto 0);
phystatus4 : in std_logic_vector(0 downto 0);
rxelecidle4 : in std_logic_vector(0 downto 0);
rxstatus4 : in std_logic_vector(2 downto 0);
rxdataskip4 : in std_logic_vector(0 downto 0);
rxblkst4 : in std_logic_vector(0 downto 0);
rxsynchd4 : in std_logic_vector(1 downto 0);
rxfreqlocked4 : in std_logic_vector(0 downto 0);
txdata5 : out std_logic_vector(31 downto 0);
txdatak5 : out std_logic_vector(3 downto 0);
txdetectrx5 : out std_logic_vector(0 downto 0);
txelecidle5 : out std_logic_vector(0 downto 0);
txcompl5 : out std_logic_vector(0 downto 0);
rxpolarity5 : out std_logic_vector(0 downto 0);
powerdown5 : out std_logic_vector(1 downto 0);
txdataskip5 : out std_logic_vector(0 downto 0);
txblkst5 : out std_logic_vector(0 downto 0);
txsynchd5 : out std_logic_vector(1 downto 0);
txdeemph5 : out std_logic_vector(0 downto 0);
txmargin5 : out std_logic_vector(2 downto 0);
rxdata5 : in std_logic_vector(31 downto 0);
rxdatak5 : in std_logic_vector(3 downto 0);
rxvalid5 : in std_logic_vector(0 downto 0);
phystatus5 : in std_logic_vector(0 downto 0);
rxelecidle5 : in std_logic_vector(0 downto 0);
rxstatus5 : in std_logic_vector(2 downto 0);
rxdataskip5 : in std_logic_vector(0 downto 0);
rxblkst5 : in std_logic_vector(0 downto 0);
rxsynchd5 : in std_logic_vector(1 downto 0);
rxfreqlocked5 : in std_logic_vector(0 downto 0);
txdata6 : out std_logic_vector(31 downto 0);
txdatak6 : out std_logic_vector(3 downto 0);
txdetectrx6 : out std_logic_vector(0 downto 0);
txelecidle6 : out std_logic_vector(0 downto 0);
txcompl6 : out std_logic_vector(0 downto 0);
rxpolarity6 : out std_logic_vector(0 downto 0);
powerdown6 : out std_logic_vector(1 downto 0);
txdataskip6 : out std_logic_vector(0 downto 0);
txblkst6 : out std_logic_vector(0 downto 0);
txsynchd6 : out std_logic_vector(1 downto 0);
txdeemph6 : out std_logic_vector(0 downto 0);
txmargin6 : out std_logic_vector(2 downto 0);
rxdata6 : in std_logic_vector(31 downto 0);
rxdatak6 : in std_logic_vector(3 downto 0);
rxvalid6 : in std_logic_vector(0 downto 0);
phystatus6 : in std_logic_vector(0 downto 0);
rxelecidle6 : in std_logic_vector(0 downto 0);
rxstatus6 : in std_logic_vector(2 downto 0);
rxdataskip6 : in std_logic_vector(0 downto 0);
rxblkst6 : in std_logic_vector(0 downto 0);
rxsynchd6 : in std_logic_vector(1 downto 0);
rxfreqlocked6 : in std_logic_vector(0 downto 0);
txdata7 : out std_logic_vector(31 downto 0);
txdatak7 : out std_logic_vector(3 downto 0);
txdetectrx7 : out std_logic_vector(0 downto 0);
txelecidle7 : out std_logic_vector(0 downto 0);
txcompl7 : out std_logic_vector(0 downto 0);
rxpolarity7 : out std_logic_vector(0 downto 0);
powerdown7 : out std_logic_vector(1 downto 0);
txdataskip7 : out std_logic_vector(0 downto 0);
txblkst7 : out std_logic_vector(0 downto 0);
txsynchd7 : out std_logic_vector(1 downto 0);
txdeemph7 : out std_logic_vector(0 downto 0);
txmargin7 : out std_logic_vector(2 downto 0);
rxdata7 : in std_logic_vector(31 downto 0);
rxdatak7 : in std_logic_vector(3 downto 0);
rxvalid7 : in std_logic_vector(0 downto 0);
phystatus7 : in std_logic_vector(0 downto 0);
rxelecidle7 : in std_logic_vector(0 downto 0);
rxstatus7 : in std_logic_vector(2 downto 0);
rxdataskip7 : in std_logic_vector(0 downto 0);
rxblkst7 : in std_logic_vector(0 downto 0);
rxsynchd7 : in std_logic_vector(1 downto 0);
rxfreqlocked7 : in std_logic_vector(0 downto 0);
dbgpipex1rx : in std_logic_vector(43 downto 0);
memredsclk : in std_logic_vector(0 downto 0);
memredenscan : in std_logic_vector(0 downto 0);
memredscen : in std_logic_vector(0 downto 0);
memredscin : in std_logic_vector(0 downto 0);
memredscsel : in std_logic_vector(0 downto 0);
memredscrst : in std_logic_vector(0 downto 0);
memredscout : out std_logic_vector(0 downto 0);
memregscanen : in std_logic_vector(0 downto 0);
memregscanin : in std_logic_vector(0 downto 0);
memhiptestenable : in std_logic_vector(0 downto 0);
memregscanout : out std_logic_vector(0 downto 0);
bisttesten : in std_logic_vector(0 downto 0);
bistenrpl : in std_logic_vector(0 downto 0);
bistscanin : in std_logic_vector(0 downto 0);
bistscanen : in std_logic_vector(0 downto 0);
bistenrcv : in std_logic_vector(0 downto 0);
bistscanoutrpl : out std_logic_vector(0 downto 0);
bistdonearpl : out std_logic_vector(0 downto 0);
bistdonebrpl : out std_logic_vector(0 downto 0);
bistpassrpl : out std_logic_vector(0 downto 0);
derrrpl : out std_logic_vector(0 downto 0);
derrcorextrpl : out std_logic_vector(0 downto 0);
bistscanoutrcv : out std_logic_vector(0 downto 0);
bistdonearcv : out std_logic_vector(0 downto 0);
bistdonebrcv : out std_logic_vector(0 downto 0);
bistpassrcv : out std_logic_vector(0 downto 0);
derrcorextrcv : out std_logic_vector(0 downto 0);
bistscanoutrcv1 : out std_logic_vector(0 downto 0);
bistdonearcv1 : out std_logic_vector(0 downto 0);
bistdonebrcv1 : out std_logic_vector(0 downto 0);
bistpassrcv1 : out std_logic_vector(0 downto 0);
derrcorextrcv1 : out std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
nfrzdrv : in std_logic_vector(0 downto 0);
frzreg : in std_logic_vector(0 downto 0);
frzlogic : in std_logic_vector(0 downto 0);
idrpl : in std_logic_vector(7 downto 0);
idrcv : in std_logic_vector(7 downto 0);
plniotri : in std_logic_vector(0 downto 0);
entest : in std_logic_vector(0 downto 0);
npor : in std_logic_vector(0 downto 0);
usermode : in std_logic_vector(0 downto 0);
cvpclk : out std_logic_vector(0 downto 0);
cvpdata : out std_logic_vector(31 downto 0);
cvpstartxfer : out std_logic_vector(0 downto 0);
cvpconfig : out std_logic_vector(0 downto 0);
cvpfullconfig : out std_logic_vector(0 downto 0);
cvpconfigready : in std_logic_vector(0 downto 0);
cvpen : in std_logic_vector(0 downto 0);
cvpconfigerror : in std_logic_vector(0 downto 0);
cvpconfigdone : in std_logic_vector(0 downto 0);
pinperstn : in std_logic_vector(0 downto 0);
pldperstn : in std_logic_vector(0 downto 0);
iocsrrdydly : in std_logic_vector(0 downto 0);
softaltpe3rstn : in std_logic_vector(0 downto 0);
softaltpe3srstn : in std_logic_vector(0 downto 0);
softaltpe3crstn : in std_logic_vector(0 downto 0);
pldclrpmapcshipn : in std_logic_vector(0 downto 0);
pldclrpcshipn : in std_logic_vector(0 downto 0);
pldclrhipn : in std_logic_vector(0 downto 0);
s0ch0emsiptieoff : out std_logic_vector(100 downto 0);
s0ch1emsiptieoff : out std_logic_vector(100 downto 0);
s0ch2emsiptieoff : out std_logic_vector(100 downto 0);
s1ch0emsiptieoff : out std_logic_vector(100 downto 0);
s1ch1emsiptieoff : out std_logic_vector(188 downto 0);
s1ch2emsiptieoff : out std_logic_vector(100 downto 0);
s2ch0emsiptieoff : out std_logic_vector(100 downto 0);
s2ch1emsiptieoff : out std_logic_vector(100 downto 0);
s2ch2emsiptieoff : out std_logic_vector(100 downto 0);
s3ch0emsiptieoff : out std_logic_vector(188 downto 0);
s3ch1emsiptieoff : out std_logic_vector(188 downto 0);
s3ch2emsiptieoff : out std_logic_vector(188 downto 0);
emsiptieofftop : out std_logic_vector(299 downto 0);
emsiptieoffbot : out std_logic_vector(299 downto 0);
txpcsrstn0 : out std_logic_vector(0 downto 0);
rxpcsrstn0 : out std_logic_vector(0 downto 0);
g3txpcsrstn0 : out std_logic_vector(0 downto 0);
g3rxpcsrstn0 : out std_logic_vector(0 downto 0);
txpmasyncp0 : out std_logic_vector(0 downto 0);
rxpmarstb0 : out std_logic_vector(0 downto 0);
txlcpllrstb0 : out std_logic_vector(0 downto 0);
offcalen0 : out std_logic_vector(0 downto 0);
frefclk0 : in std_logic_vector(0 downto 0);
offcaldone0 : in std_logic_vector(0 downto 0);
txlcplllock0 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock0 : in std_logic_vector(0 downto 0);
rxpllphaselock0 : in std_logic_vector(0 downto 0);
masktxplllock0 : in std_logic_vector(0 downto 0);
txpcsrstn1 : out std_logic_vector(0 downto 0);
rxpcsrstn1 : out std_logic_vector(0 downto 0);
g3txpcsrstn1 : out std_logic_vector(0 downto 0);
g3rxpcsrstn1 : out std_logic_vector(0 downto 0);
txpmasyncp1 : out std_logic_vector(0 downto 0);
rxpmarstb1 : out std_logic_vector(0 downto 0);
txlcpllrstb1 : out std_logic_vector(0 downto 0);
offcalen1 : out std_logic_vector(0 downto 0);
frefclk1 : in std_logic_vector(0 downto 0);
offcaldone1 : in std_logic_vector(0 downto 0);
txlcplllock1 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock1 : in std_logic_vector(0 downto 0);
rxpllphaselock1 : in std_logic_vector(0 downto 0);
masktxplllock1 : in std_logic_vector(0 downto 0);
txpcsrstn2 : out std_logic_vector(0 downto 0);
rxpcsrstn2 : out std_logic_vector(0 downto 0);
g3txpcsrstn2 : out std_logic_vector(0 downto 0);
g3rxpcsrstn2 : out std_logic_vector(0 downto 0);
txpmasyncp2 : out std_logic_vector(0 downto 0);
rxpmarstb2 : out std_logic_vector(0 downto 0);
txlcpllrstb2 : out std_logic_vector(0 downto 0);
offcalen2 : out std_logic_vector(0 downto 0);
frefclk2 : in std_logic_vector(0 downto 0);
offcaldone2 : in std_logic_vector(0 downto 0);
txlcplllock2 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock2 : in std_logic_vector(0 downto 0);
rxpllphaselock2 : in std_logic_vector(0 downto 0);
masktxplllock2 : in std_logic_vector(0 downto 0);
txpcsrstn3 : out std_logic_vector(0 downto 0);
rxpcsrstn3 : out std_logic_vector(0 downto 0);
g3txpcsrstn3 : out std_logic_vector(0 downto 0);
g3rxpcsrstn3 : out std_logic_vector(0 downto 0);
txpmasyncp3 : out std_logic_vector(0 downto 0);
rxpmarstb3 : out std_logic_vector(0 downto 0);
txlcpllrstb3 : out std_logic_vector(0 downto 0);
offcalen3 : out std_logic_vector(0 downto 0);
frefclk3 : in std_logic_vector(0 downto 0);
offcaldone3 : in std_logic_vector(0 downto 0);
txlcplllock3 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock3 : in std_logic_vector(0 downto 0);
rxpllphaselock3 : in std_logic_vector(0 downto 0);
masktxplllock3 : in std_logic_vector(0 downto 0);
txpcsrstn4 : out std_logic_vector(0 downto 0);
rxpcsrstn4 : out std_logic_vector(0 downto 0);
g3txpcsrstn4 : out std_logic_vector(0 downto 0);
g3rxpcsrstn4 : out std_logic_vector(0 downto 0);
txpmasyncp4 : out std_logic_vector(0 downto 0);
rxpmarstb4 : out std_logic_vector(0 downto 0);
txlcpllrstb4 : out std_logic_vector(0 downto 0);
offcalen4 : out std_logic_vector(0 downto 0);
frefclk4 : in std_logic_vector(0 downto 0);
offcaldone4 : in std_logic_vector(0 downto 0);
txlcplllock4 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock4 : in std_logic_vector(0 downto 0);
rxpllphaselock4 : in std_logic_vector(0 downto 0);
masktxplllock4 : in std_logic_vector(0 downto 0);
txpcsrstn5 : out std_logic_vector(0 downto 0);
rxpcsrstn5 : out std_logic_vector(0 downto 0);
g3txpcsrstn5 : out std_logic_vector(0 downto 0);
g3rxpcsrstn5 : out std_logic_vector(0 downto 0);
txpmasyncp5 : out std_logic_vector(0 downto 0);
rxpmarstb5 : out std_logic_vector(0 downto 0);
txlcpllrstb5 : out std_logic_vector(0 downto 0);
offcalen5 : out std_logic_vector(0 downto 0);
frefclk5 : in std_logic_vector(0 downto 0);
offcaldone5 : in std_logic_vector(0 downto 0);
txlcplllock5 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock5 : in std_logic_vector(0 downto 0);
rxpllphaselock5 : in std_logic_vector(0 downto 0);
masktxplllock5 : in std_logic_vector(0 downto 0);
txpcsrstn6 : out std_logic_vector(0 downto 0);
rxpcsrstn6 : out std_logic_vector(0 downto 0);
g3txpcsrstn6 : out std_logic_vector(0 downto 0);
g3rxpcsrstn6 : out std_logic_vector(0 downto 0);
txpmasyncp6 : out std_logic_vector(0 downto 0);
rxpmarstb6 : out std_logic_vector(0 downto 0);
txlcpllrstb6 : out std_logic_vector(0 downto 0);
offcalen6 : out std_logic_vector(0 downto 0);
frefclk6 : in std_logic_vector(0 downto 0);
offcaldone6 : in std_logic_vector(0 downto 0);
txlcplllock6 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock6 : in std_logic_vector(0 downto 0);
rxpllphaselock6 : in std_logic_vector(0 downto 0);
masktxplllock6 : in std_logic_vector(0 downto 0);
txpcsrstn7 : out std_logic_vector(0 downto 0);
rxpcsrstn7 : out std_logic_vector(0 downto 0);
g3txpcsrstn7 : out std_logic_vector(0 downto 0);
g3rxpcsrstn7 : out std_logic_vector(0 downto 0);
txpmasyncp7 : out std_logic_vector(0 downto 0);
rxpmarstb7 : out std_logic_vector(0 downto 0);
txlcpllrstb7 : out std_logic_vector(0 downto 0);
offcalen7 : out std_logic_vector(0 downto 0);
frefclk7 : in std_logic_vector(0 downto 0);
offcaldone7 : in std_logic_vector(0 downto 0);
txlcplllock7 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock7 : in std_logic_vector(0 downto 0);
rxpllphaselock7 : in std_logic_vector(0 downto 0);
masktxplllock7 : in std_logic_vector(0 downto 0);
txpcsrstn8 : out std_logic_vector(0 downto 0);
rxpcsrstn8 : out std_logic_vector(0 downto 0);
g3txpcsrstn8 : out std_logic_vector(0 downto 0);
g3rxpcsrstn8 : out std_logic_vector(0 downto 0);
txpmasyncp8 : out std_logic_vector(0 downto 0);
rxpmarstb8 : out std_logic_vector(0 downto 0);
txlcpllrstb8 : out std_logic_vector(0 downto 0);
offcalen8 : out std_logic_vector(0 downto 0);
frefclk8 : in std_logic_vector(0 downto 0);
offcaldone8 : in std_logic_vector(0 downto 0);
txlcplllock8 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock8 : in std_logic_vector(0 downto 0);
rxpllphaselock8 : in std_logic_vector(0 downto 0);
masktxplllock8 : in std_logic_vector(0 downto 0);
txpcsrstn9 : out std_logic_vector(0 downto 0);
rxpcsrstn9 : out std_logic_vector(0 downto 0);
g3txpcsrstn9 : out std_logic_vector(0 downto 0);
g3rxpcsrstn9 : out std_logic_vector(0 downto 0);
txpmasyncp9 : out std_logic_vector(0 downto 0);
rxpmarstb9 : out std_logic_vector(0 downto 0);
txlcpllrstb9 : out std_logic_vector(0 downto 0);
offcalen9 : out std_logic_vector(0 downto 0);
frefclk9 : in std_logic_vector(0 downto 0);
offcaldone9 : in std_logic_vector(0 downto 0);
txlcplllock9 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock9 : in std_logic_vector(0 downto 0);
rxpllphaselock9 : in std_logic_vector(0 downto 0);
masktxplllock9 : in std_logic_vector(0 downto 0);
txpcsrstn10 : out std_logic_vector(0 downto 0);
rxpcsrstn10 : out std_logic_vector(0 downto 0);
g3txpcsrstn10 : out std_logic_vector(0 downto 0);
g3rxpcsrstn10 : out std_logic_vector(0 downto 0);
txpmasyncp10 : out std_logic_vector(0 downto 0);
rxpmarstb10 : out std_logic_vector(0 downto 0);
txlcpllrstb10 : out std_logic_vector(0 downto 0);
offcalen10 : out std_logic_vector(0 downto 0);
frefclk10 : in std_logic_vector(0 downto 0);
offcaldone10 : in std_logic_vector(0 downto 0);
txlcplllock10 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock10 : in std_logic_vector(0 downto 0);
rxpllphaselock10 : in std_logic_vector(0 downto 0);
masktxplllock10 : in std_logic_vector(0 downto 0);
txpcsrstn11 : out std_logic_vector(0 downto 0);
rxpcsrstn11 : out std_logic_vector(0 downto 0);
g3txpcsrstn11 : out std_logic_vector(0 downto 0);
g3rxpcsrstn11 : out std_logic_vector(0 downto 0);
txpmasyncp11 : out std_logic_vector(0 downto 0);
rxpmarstb11 : out std_logic_vector(0 downto 0);
txlcpllrstb11 : out std_logic_vector(0 downto 0);
offcalen11 : out std_logic_vector(0 downto 0);
frefclk11 : in std_logic_vector(0 downto 0);
offcaldone11 : in std_logic_vector(0 downto 0);
txlcplllock11 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock11 : in std_logic_vector(0 downto 0);
rxpllphaselock11 : in std_logic_vector(0 downto 0);
masktxplllock11 : in std_logic_vector(0 downto 0);
reservedin : in std_logic_vector(31 downto 0);
reservedclkin : in std_logic_vector(0 downto 0);
reservedout : out std_logic_vector(31 downto 0);
reservedclkout : out std_logic_vector(0 downto 0)
);
end stratixv_hssi_gen3_pcie_hip;
architecture behavior of stratixv_hssi_gen3_pcie_hip is
component stratixv_hssi_gen3_pcie_hip_encrypted
generic (
func_mode : string := "disable";
in_cvp_mode : string := "not_cvp_mode";
bonding_mode : string := "bond_disable";
prot_mode : string := "disabled_prot_mode";
pcie_spec_1p0_compliance : string := "spec_1p1";
vc_enable : string := "single_vc";
enable_slot_register : string := "false";
pcie_mode : string := "shared_mode";
bypass_cdc : string := "false";
enable_rx_reordering : string := "true";
enable_rx_buffer_checking : string := "false";
single_rx_detect_data : bit_vector := B"0000";
single_rx_detect : string := "single_rx_detect";
use_crc_forwarding : string := "false";
bypass_tl : string := "false";
gen123_lane_rate_mode : string := "gen1";
lane_mask : string := "x4";
disable_link_x2_support : string := "false";
national_inst_thru_enhance : string := "true";
hip_hard_reset : string := "enable";
dis_paritychk : string := "enable";
wrong_device_id : string := "disable";
data_pack_rx : string := "disable";
ast_width : string := "rx_tx_64";
rx_sop_ctrl : string := "boundary_64";
rx_ast_parity : string := "disable";
tx_ast_parity : string := "disable";
ltssm_1ms_timeout : string := "disable";
ltssm_freqlocked_check : string := "disable";
deskew_comma : string := "skp_eieos_deskw";
dl_tx_check_parity_edb : string := "disable";
tl_tx_check_parity_msg : string := "disable";
port_link_number_data : bit_vector := B"00000001";
port_link_number : string := "port_link_number";
device_number_data : bit_vector := B"00000";
device_number : string := "device_number";
bypass_clk_switch : string := "false";
core_clk_out_sel : string := "div_1";
core_clk_divider : string := "div_1";
core_clk_source : string := "pll_fixed_clk";
core_clk_sel : string := "pld_clk";
enable_ch0_pclk_out : string := "true";
enable_ch01_pclk_out : string := "pclk_ch0";
pipex1_debug_sel : string := "disable";
pclk_out_sel : string := "pclk";
vendor_id_data : bit_vector := B"1000101110010";
vendor_id : string := "vendor_id";
device_id_data : bit_vector := B"0000000000000001";
device_id : string := "device_id";
revision_id_data : bit_vector := B"00000001";
revision_id : string := "revision_id";
class_code_data : bit_vector := B"111111110000000000000000";
class_code : string := "class_code";
subsystem_vendor_id_data : bit_vector := B"0001000101110010";
subsystem_vendor_id : string := "subsystem_vendor_id";
subsystem_device_id_data : bit_vector := B"0000000000000001";
subsystem_device_id : string := "subsystem_device_id";
no_soft_reset : string := "false";
maximum_current_data : bit_vector := B"000";
maximum_current : string := "maximum_current";
d1_support : string := "false";
d2_support : string := "false";
d0_pme : string := "false";
d1_pme : string := "false";
d2_pme : string := "false";
d3_hot_pme : string := "false";
d3_cold_pme : string := "false";
use_aer : string := "false";
low_priority_vc : string := "single_vc";
vc_arbitration : string := "single_vc";
disable_snoop_packet : string := "false";
max_payload_size : string := "payload_512";
surprise_down_error_support : string := "false";
dll_active_report_support : string := "false";
extend_tag_field : string := "false";
endpoint_l0_latency_data : bit_vector := B"000";
endpoint_l0_latency : string := "endpoint_l0_latency";
endpoint_l1_latency_data : bit_vector := B"000";
endpoint_l1_latency : string := "endpoint_l1_latency";
indicator_data : bit_vector := B"111";
indicator : string := "indicator";
role_based_error_reporting : string := "false";
slot_power_scale_data : bit_vector := B"00";
slot_power_scale : string := "slot_power_scale";
max_link_width : string := "x4";
enable_l1_aspm : string := "false";
enable_l0s_aspm : string := "false";
l1_exit_latency_sameclock_data : bit_vector := B"000";
l1_exit_latency_sameclock : string := "l1_exit_latency_sameclock";
l1_exit_latency_diffclock_data : bit_vector := B"000";
l1_exit_latency_diffclock : string := "l1_exit_latency_diffclock";
hot_plug_support_data : bit_vector := B"0000000";
hot_plug_support : string := "hot_plug_support";
slot_power_limit_data : bit_vector := B"00000000";
slot_power_limit : string := "slot_power_limit";
slot_number_data : bit_vector := B"0000000000000";
slot_number : string := "slot_number";
diffclock_nfts_count_data : bit_vector := B"00000000";
diffclock_nfts_count : string := "diffclock_nfts_count";
sameclock_nfts_count_data : bit_vector := B"00000000";
sameclock_nfts_count : string := "sameclock_nfts_count";
completion_timeout : string := "abcd";
enable_completion_timeout_disable : string := "true";
extended_tag_reset : string := "false";
ecrc_check_capable : string := "true";
ecrc_gen_capable : string := "true";
no_command_completed : string := "true";
msi_multi_message_capable : string := "count_4";
msi_64bit_addressing_capable : string := "true";
msi_masking_capable : string := "false";
msi_support : string := "true";
interrupt_pin : string := "inta";
ena_ido_req : string := "false";
ena_ido_cpl : string := "false";
enable_function_msix_support : string := "true";
msix_table_size_data : bit_vector := B"00000000000";
msix_table_size : string := "msix_table_size";
msix_table_bir_data : bit_vector := B"000";
msix_table_bir : string := "msix_table_bir";
msix_table_offset_data : bit_vector := B"00000000000000000000000000000";
msix_table_offset : string := "msix_table_offset";
msix_pba_bir_data : bit_vector := B"000";
msix_pba_bir : string := "msix_pba_bir";
msix_pba_offset_data : bit_vector := B"00000000000000000000000000000";
msix_pba_offset : string := "msix_pba_offset";
bridge_port_vga_enable : string := "false";
bridge_port_ssid_support : string := "false";
ssvid_data : bit_vector := B"0000000000000000";
ssvid : string := "ssvid";
ssid_data : bit_vector := B"0000000000000000";
ssid : string := "ssid";
eie_before_nfts_count_data : bit_vector := B"0100";
eie_before_nfts_count : string := "eie_before_nfts_count";
gen2_diffclock_nfts_count_data : bit_vector := B"11111111";
gen2_diffclock_nfts_count : string := "gen2_diffclock_nfts_count";
gen2_sameclock_nfts_count_data : bit_vector := B"11111111";
gen2_sameclock_nfts_count : string := "gen2_sameclock_nfts_count";
deemphasis_enable : string := "false";
pcie_spec_version : string := "v2";
l0_exit_latency_sameclock_data : bit_vector := B"110";
l0_exit_latency_sameclock : string := "l0_exit_latency_sameclock";
l0_exit_latency_diffclock_data : bit_vector := B"110";
l0_exit_latency_diffclock : string := "l0_exit_latency_diffclock";
rx_ei_l0s : string := "disable";
l2_async_logic : string := "enable";
aspm_config_management : string := "true";
atomic_op_routing : string := "false";
atomic_op_completer_32bit : string := "false";
atomic_op_completer_64bit : string := "false";
cas_completer_128bit : string := "false";
ltr_mechanism : string := "false";
tph_completer : string := "false";
extended_format_field : string := "true";
atomic_malformed : string := "false";
flr_capability : string := "true";
enable_adapter_half_rate_mode : string := "false";
vc0_clk_enable : string := "true";
vc1_clk_enable : string := "false";
register_pipe_signals : string := "false";
bar0_io_space : string := "false";
bar0_64bit_mem_space : string := "true";
bar0_prefetchable : string := "true";
bar0_size_mask_data : bit_vector := B"1111111111111111111111111111";
bar0_size_mask : string := "bar0_size_mask";
bar1_io_space : string := "false";
bar1_64bit_mem_space : string := "false";
bar1_prefetchable : string := "false";
bar1_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar1_size_mask : string := "bar1_size_mask";
bar2_io_space : string := "false";
bar2_64bit_mem_space : string := "false";
bar2_prefetchable : string := "false";
bar2_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar2_size_mask : string := "bar2_size_mask";
bar3_io_space : string := "false";
bar3_64bit_mem_space : string := "false";
bar3_prefetchable : string := "false";
bar3_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar3_size_mask : string := "bar3_size_mask";
bar4_io_space : string := "false";
bar4_64bit_mem_space : string := "false";
bar4_prefetchable : string := "false";
bar4_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar4_size_mask : string := "bar4_size_mask";
bar5_io_space : string := "false";
bar5_64bit_mem_space : string := "false";
bar5_prefetchable : string := "false";
bar5_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar5_size_mask : string := "bar5_size_mask";
expansion_base_address_register_data : bit_vector := B"00000000000000000000000000000000";
expansion_base_address_register : string := "expansion_base_address_register";
io_window_addr_width : string := "window_32_bit";
prefetchable_mem_window_addr_width : string := "prefetch_32";
skp_os_gen3_count_data : bit_vector := B"00000000000";
skp_os_gen3_count : string := "skp_os_gen3_count";
rx_cdc_almost_empty_data : bit_vector := B"0000";
rx_cdc_almost_empty : string := "rx_cdc_almost_empty";
tx_cdc_almost_empty_data : bit_vector := B"0000";
tx_cdc_almost_empty : string := "tx_cdc_almost_empty";
rx_cdc_almost_full_data : bit_vector := B"0000";
rx_cdc_almost_full : string := "rx_cdc_almost_full";
tx_cdc_almost_full_data : bit_vector := B"0000";
tx_cdc_almost_full : string := "tx_cdc_almost_full";
rx_l0s_count_idl_data : bit_vector := B"00000000";
rx_l0s_count_idl : string := "rx_l0s_count_idl";
cdc_dummy_insert_limit_data : bit_vector := B"0000";
cdc_dummy_insert_limit : string := "cdc_dummy_insert_limit";
ei_delay_powerdown_count_data : bit_vector := B"00001010";
ei_delay_powerdown_count : string := "ei_delay_powerdown_count";
millisecond_cycle_count_data : bit_vector := B"00000000000000000000";
millisecond_cycle_count : string := "millisecond_cycle_count";
skp_os_schedule_count_data : bit_vector := B"00000000000";
skp_os_schedule_count : string := "skp_os_schedule_count";
fc_init_timer_data : bit_vector := B"10000000000";
fc_init_timer : string := "fc_init_timer";
l01_entry_latency_data : bit_vector := B"11111";
l01_entry_latency : string := "l01_entry_latency";
flow_control_update_count_data : bit_vector := B"11110";
flow_control_update_count : string := "flow_control_update_count";
flow_control_timeout_count_data : bit_vector := B"11001000";
flow_control_timeout_count : string := "flow_control_timeout_count";
vc0_rx_flow_ctrl_posted_header_data : bit_vector := B"00110010";
vc0_rx_flow_ctrl_posted_header : string := "vc0_rx_flow_ctrl_posted_header";
vc0_rx_flow_ctrl_posted_data_data : bit_vector := B"000101101000";
vc0_rx_flow_ctrl_posted_data : string := "vc0_rx_flow_ctrl_posted_data";
vc0_rx_flow_ctrl_nonposted_header_data : bit_vector := B"00110110";
vc0_rx_flow_ctrl_nonposted_header : string := "vc0_rx_flow_ctrl_nonposted_header";
vc0_rx_flow_ctrl_nonposted_data_data : bit_vector := B"00000000";
vc0_rx_flow_ctrl_nonposted_data : string := "vc0_rx_flow_ctrl_nonposted_data";
vc0_rx_flow_ctrl_compl_header_data : bit_vector := B"01110000";
vc0_rx_flow_ctrl_compl_header : string := "vc0_rx_flow_ctrl_compl_header";
vc0_rx_flow_ctrl_compl_data_data : bit_vector := B"000111000000";
vc0_rx_flow_ctrl_compl_data : string := "vc0_rx_flow_ctrl_compl_data";
rx_ptr0_posted_dpram_min_data : bit_vector := B"00000000000";
rx_ptr0_posted_dpram_min : string := "rx_ptr0_posted_dpram_min";
rx_ptr0_posted_dpram_max_data : bit_vector := B"00000000000";
rx_ptr0_posted_dpram_max : string := "rx_ptr0_posted_dpram_max";
rx_ptr0_nonposted_dpram_min_data : bit_vector := B"00000000000";
rx_ptr0_nonposted_dpram_min : string := "rx_ptr0_nonposted_dpram_min";
rx_ptr0_nonposted_dpram_max_data : bit_vector := B"00000000000";
rx_ptr0_nonposted_dpram_max : string := "rx_ptr0_nonposted_dpram_max";
retry_buffer_last_active_address_data : bit_vector := B"1111111111";
retry_buffer_last_active_address : string := "retry_buffer_last_active_address";
retry_buffer_memory_settings_data : bit_vector := B"000000000000000000000000000000";
retry_buffer_memory_settings : string := "retry_buffer_memory_settings";
vc0_rx_buffer_memory_settings_data : bit_vector := B"000000000000000000000000000000";
vc0_rx_buffer_memory_settings : string := "vc0_rx_buffer_memory_settings";
bist_memory_settings_data : bit_vector := B"000000000000000000000000000000000000000000000000000000000000000000000000000";
bist_memory_settings : string := "bist_memory_settings";
credit_buffer_allocation_aux : string := "balanced";
iei_enable_settings : string := "gen2_infei_infsd_gen1_infei_sd";
vsec_id_data : bit_vector := B"0001000101110010";
vsec_id : string := "vsec_id";
cvp_rate_sel : string := "full_rate";
hard_reset_bypass : string := "false";
cvp_data_compressed : string := "false";
cvp_data_encrypted : string := "false";
cvp_mode_reset : string := "false";
cvp_clk_reset : string := "false";
vsec_cap_data : bit_vector := B"0000";
vsec_cap : string := "vsec_cap";
jtag_id_data : bit_vector := B"00000000000000000000000000000000";
jtag_id : string := "jtag_id";
user_id_data : bit_vector := B"0000000000000000";
user_id : string := "user_id";
cseb_extend_pci : string := "false";
cseb_extend_pcie : string := "false";
cseb_cpl_status_during_cvp : string := "config_retry_status";
cseb_route_to_avl_rx_st : string := "cseb";
cseb_config_bypass : string := "disable";
cseb_cpl_tag_checking : string := "enable";
cseb_bar_match_checking : string := "enable";
cseb_min_error_checking : string := "false";
cseb_temp_busy_crs : string := "completer_abort";
cseb_disable_auto_crs : string := "false";
gen3_diffclock_nfts_count_data : bit_vector := B"10000000";
gen3_diffclock_nfts_count : string := "g3_diffclock_nfts_count";
gen3_sameclock_nfts_count_data : bit_vector := B"10000000";
gen3_sameclock_nfts_count : string := "g3_sameclock_nfts_count";
gen3_coeff_errchk : string := "enable";
gen3_paritychk : string := "enable";
gen3_coeff_delay_count_data : bit_vector := B"1111101";
gen3_coeff_delay_count : string := "g3_coeff_dly_count";
gen3_coeff_1_data : bit_vector := B"000000000000000000";
gen3_coeff_1 : string := "g3_coeff_1";
gen3_coeff_1_sel : string := "coeff_1";
gen3_coeff_1_preset_hint_data : bit_vector := B"000";
gen3_coeff_1_preset_hint : string := "g3_coeff_1_prst_hint";
gen3_coeff_1_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_1_nxtber_more : string := "g3_coeff_1_nxtber_more";
gen3_coeff_1_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_1_nxtber_less : string := "g3_coeff_1_nxtber_less";
gen3_coeff_1_reqber_data : bit_vector := B"00000";
gen3_coeff_1_reqber : string := "g3_coeff_1_reqber";
gen3_coeff_1_ber_meas_data : bit_vector := B"000000";
gen3_coeff_1_ber_meas : string := "g3_coeff_1_ber_meas";
gen3_coeff_2_data : bit_vector := B"000000000000000000";
gen3_coeff_2 : string := "g3_coeff_2";
gen3_coeff_2_sel : string := "coeff_2";
gen3_coeff_2_preset_hint_data : bit_vector := B"000";
gen3_coeff_2_preset_hint : string := "g3_coeff_2_prst_hint";
gen3_coeff_2_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_2_nxtber_more : string := "g3_coeff_2_nxtber_more";
gen3_coeff_2_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_2_nxtber_less : string := "g3_coeff_2_nxtber_less";
gen3_coeff_2_reqber_data : bit_vector := B"00000";
gen3_coeff_2_reqber : string := "g3_coeff_2_reqber";
gen3_coeff_2_ber_meas_data : bit_vector := B"000000";
gen3_coeff_2_ber_meas : string := "g3_coeff_1_ber_meas";
gen3_coeff_3_data : bit_vector := B"000000000000000000";
gen3_coeff_3 : string := "g3_coeff_3";
gen3_coeff_3_sel : string := "coeff_3";
gen3_coeff_3_preset_hint_data : bit_vector := B"000";
gen3_coeff_3_preset_hint : string := "g3_coeff_3_prst_hint";
gen3_coeff_3_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_3_nxtber_more : string := "g3_coeff_3_nxtber_more";
gen3_coeff_3_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_3_nxtber_less : string := "g3_coeff_3_nxtber_less";
gen3_coeff_3_reqber_data : bit_vector := B"00000";
gen3_coeff_3_reqber : string := "g3_coeff_3_reqber";
gen3_coeff_3_ber_meas_data : bit_vector := B"000000";
gen3_coeff_3_ber_meas : string := "g3_coeff_3_ber_meas";
gen3_coeff_4_data : bit_vector := B"000000000000000000";
gen3_coeff_4 : string := "g3_coeff_4";
gen3_coeff_4_sel : string := "coeff_4";
gen3_coeff_4_preset_hint_data : bit_vector := B"000";
gen3_coeff_4_preset_hint : string := "g3_coeff_4_prst_hint";
gen3_coeff_4_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_4_nxtber_more : string := "g3_coeff_4_nxtber_more";
gen3_coeff_4_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_4_nxtber_less : string := "g3_coeff_4_nxtber_less";
gen3_coeff_4_reqber_data : bit_vector := B"00000";
gen3_coeff_4_reqber : string := "g3_coeff_4_reqber";
gen3_coeff_4_ber_meas_data : bit_vector := B"000000";
gen3_coeff_4_ber_meas : string := "g3_coeff_4_ber_meas";
gen3_coeff_5_data : bit_vector := B"000000000000000000";
gen3_coeff_5 : string := "g3_coeff_5";
gen3_coeff_5_sel : string := "coeff_5";
gen3_coeff_5_preset_hint_data : bit_vector := B"000";
gen3_coeff_5_preset_hint : string := "g3_coeff_5_prst_hint";
gen3_coeff_5_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_5_nxtber_more : string := "g3_coeff_5_nxtber_more";
gen3_coeff_5_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_5_nxtber_less : string := "g3_coeff_5_nxtber_less";
gen3_coeff_5_reqber_data : bit_vector := B"00000";
gen3_coeff_5_reqber : string := "g3_coeff_5_reqber";
gen3_coeff_5_ber_meas_data : bit_vector := B"000000";
gen3_coeff_5_ber_meas : string := "g3_coeff_5_ber_meas";
gen3_coeff_6_data : bit_vector := B"000000000000000000";
gen3_coeff_6 : string := "g3_coeff_6";
gen3_coeff_6_sel : string := "coeff_6";
gen3_coeff_6_preset_hint_data : bit_vector := B"000";
gen3_coeff_6_preset_hint : string := "g3_coeff_6_prst_hint";
gen3_coeff_6_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_6_nxtber_more : string := "g3_coeff_6_nxtber_more";
gen3_coeff_6_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_6_nxtber_less : string := "g3_coeff_6_nxtber_less";
gen3_coeff_6_reqber_data : bit_vector := B"00000";
gen3_coeff_6_reqber : string := "g3_coeff_6_reqber";
gen3_coeff_6_ber_meas_data : bit_vector := B"000000";
gen3_coeff_6_ber_meas : string := "g3_coeff_6_ber_meas";
gen3_coeff_7_data : bit_vector := B"000000000000000000";
gen3_coeff_7 : string := "g3_coeff_7";
gen3_coeff_7_sel : string := "coeff_7";
gen3_coeff_7_preset_hint_data : bit_vector := B"000";
gen3_coeff_7_preset_hint : string := "g3_coeff_7_prst_hint";
gen3_coeff_7_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_7_nxtber_more : string := "g3_coeff_7_nxtber_more";
gen3_coeff_7_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_7_nxtber_less : string := "g3_coeff_7_nxtber_less";
gen3_coeff_7_reqber_data : bit_vector := B"00000";
gen3_coeff_7_reqber : string := "g3_coeff_7_reqber";
gen3_coeff_7_ber_meas_data : bit_vector := B"000000";
gen3_coeff_7_ber_meas : string := "g3_coeff_7_ber_meas";
gen3_coeff_8_data : bit_vector := B"000000000000000000";
gen3_coeff_8 : string := "g3_coeff_8";
gen3_coeff_8_sel : string := "coeff_8";
gen3_coeff_8_preset_hint_data : bit_vector := B"000";
gen3_coeff_8_preset_hint : string := "g3_coeff_8_prst_hint";
gen3_coeff_8_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_8_nxtber_more : string := "g3_coeff_8_nxtber_more";
gen3_coeff_8_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_8_nxtber_less : string := "g3_coeff_8_nxtber_less";
gen3_coeff_8_reqber_data : bit_vector := B"00000";
gen3_coeff_8_reqber : string := "g3_coeff_8_reqber";
gen3_coeff_8_ber_meas_data : bit_vector := B"000000";
gen3_coeff_8_ber_meas : string := "g3_coeff_8_ber_meas";
gen3_coeff_9_data : bit_vector := B"000000000000000000";
gen3_coeff_9 : string := "g3_coeff_9";
gen3_coeff_9_sel : string := "coeff_9";
gen3_coeff_9_preset_hint_data : bit_vector := B"000";
gen3_coeff_9_preset_hint : string := "g3_coeff_9_prst_hint";
gen3_coeff_9_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_9_nxtber_more : string := "g3_coeff_9_nxtber_more";
gen3_coeff_9_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_9_nxtber_less : string := "g3_coeff_9_nxtber_less";
gen3_coeff_9_reqber_data : bit_vector := B"00000";
gen3_coeff_9_reqber : string := "g3_coeff_9_reqber";
gen3_coeff_9_ber_meas_data : bit_vector := B"000000";
gen3_coeff_9_ber_meas : string := "g3_coeff_9_ber_meas";
gen3_coeff_10_data : bit_vector := B"000000000000000000";
gen3_coeff_10 : string := "g3_coeff_10";
gen3_coeff_10_sel : string := "coeff_10";
gen3_coeff_10_preset_hint_data : bit_vector := B"000";
gen3_coeff_10_preset_hint : string := "g3_coeff_10_prst_hint";
gen3_coeff_10_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_10_nxtber_more : string := "g3_coeff_10_nxtber_more";
gen3_coeff_10_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_10_nxtber_less : string := "g3_coeff_10_nxtber_less";
gen3_coeff_10_reqber_data : bit_vector := B"00000";
gen3_coeff_10_reqber : string := "g3_coeff_10_reqber";
gen3_coeff_10_ber_meas_data : bit_vector := B"000000";
gen3_coeff_10_ber_meas : string := "g3_coeff_10_ber_meas";
gen3_coeff_11_data : bit_vector := B"000000000000000000";
gen3_coeff_11 : string := "g3_coeff_11";
gen3_coeff_11_sel : string := "coeff_11";
gen3_coeff_11_preset_hint_data : bit_vector := B"000";
gen3_coeff_11_preset_hint : string := "g3_coeff_11_prst_hint";
gen3_coeff_11_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_11_nxtber_more : string := "g3_coeff_11_nxtber_more";
gen3_coeff_11_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_11_nxtber_less : string := "g3_coeff_11_nxtber_less";
gen3_coeff_11_reqber_data : bit_vector := B"00000";
gen3_coeff_11_reqber : string := "g3_coeff_11_reqber";
gen3_coeff_11_ber_meas_data : bit_vector := B"000000";
gen3_coeff_11_ber_meas : string := "g3_coeff_11_ber_meas";
gen3_coeff_12_data : bit_vector := B"000000000000000000";
gen3_coeff_12 : string := "g3_coeff_12";
gen3_coeff_12_sel : string := "coeff_12";
gen3_coeff_12_preset_hint_data : bit_vector := B"000";
gen3_coeff_12_preset_hint : string := "g3_coeff_12_prst_hint";
gen3_coeff_12_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_12_nxtber_more : string := "g3_coeff_12_nxtber_more";
gen3_coeff_12_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_12_nxtber_less : string := "g3_coeff_12_nxtber_less";
gen3_coeff_12_reqber_data : bit_vector := B"00000";
gen3_coeff_12_reqber : string := "g3_coeff_12_reqber";
gen3_coeff_12_ber_meas_data : bit_vector := B"000000";
gen3_coeff_12_ber_meas : string := "g3_coeff_12_ber_meas";
gen3_coeff_13_data : bit_vector := B"000000000000000000";
gen3_coeff_13 : string := "g3_coeff_13";
gen3_coeff_13_sel : string := "coeff_13";
gen3_coeff_13_preset_hint_data : bit_vector := B"000";
gen3_coeff_13_preset_hint : string := "g3_coeff_13_prst_hint";
gen3_coeff_13_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_13_nxtber_more : string := "g3_coeff_13_nxtber_more";
gen3_coeff_13_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_13_nxtber_less : string := "g3_coeff_13_nxtber_less";
gen3_coeff_13_reqber_data : bit_vector := B"00000";
gen3_coeff_13_reqber : string := "g3_coeff_13_reqber";
gen3_coeff_13_ber_meas_data : bit_vector := B"000000";
gen3_coeff_13_ber_meas : string := "g3_coeff_13_ber_meas";
gen3_coeff_14_data : bit_vector := B"000000000000000000";
gen3_coeff_14 : string := "g3_coeff_14";
gen3_coeff_14_sel : string := "coeff_14";
gen3_coeff_14_preset_hint_data : bit_vector := B"000";
gen3_coeff_14_preset_hint : string := "g3_coeff_14_prst_hint";
gen3_coeff_14_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_14_nxtber_more : string := "g3_coeff_14_nxtber_more";
gen3_coeff_14_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_14_nxtber_less : string := "g3_coeff_14_nxtber_less";
gen3_coeff_14_reqber_data : bit_vector := B"00000";
gen3_coeff_14_reqber : string := "g3_coeff_14_reqber";
gen3_coeff_14_ber_meas_data : bit_vector := B"000000";
gen3_coeff_14_ber_meas : string := "g3_coeff_14_ber_meas";
gen3_coeff_15_data : bit_vector := B"000000000000000000";
gen3_coeff_15 : string := "g3_coeff_15";
gen3_coeff_15_sel : string := "coeff_15";
gen3_coeff_15_preset_hint_data : bit_vector := B"000";
gen3_coeff_15_preset_hint : string := "g3_coeff_15_prst_hint";
gen3_coeff_15_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_15_nxtber_more : string := "g3_coeff_15_nxtber_more";
gen3_coeff_15_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_15_nxtber_less : string := "g3_coeff_15_nxtber_less";
gen3_coeff_15_reqber_data : bit_vector := B"00000";
gen3_coeff_15_reqber : string := "g3_coeff_15_reqber";
gen3_coeff_15_ber_meas_data : bit_vector := B"000000";
gen3_coeff_15_ber_meas : string := "g3_coeff_15_ber_meas";
gen3_coeff_16_data : bit_vector := B"000000000000000000";
gen3_coeff_16 : string := "g3_coeff_16";
gen3_coeff_16_sel : string := "coeff_16";
gen3_coeff_16_preset_hint_data : bit_vector := B"000";
gen3_coeff_16_preset_hint : string := "g3_coeff_16_prst_hint";
gen3_coeff_16_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_16_nxtber_more : string := "g3_coeff_16_nxtber_more";
gen3_coeff_16_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_16_nxtber_less : string := "g3_coeff_16_nxtber_less";
gen3_coeff_16_reqber_data : bit_vector := B"00000";
gen3_coeff_16_reqber : string := "g3_coeff_16_reqber";
gen3_coeff_16_ber_meas_data : bit_vector := B"000000";
gen3_coeff_16_ber_meas : string := "g3_coeff_16_ber_meas";
gen3_preset_coeff_1_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_1 : string := "g3_prst_coeff_1";
gen3_preset_coeff_2_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_2 : string := "g3_prst_coeff_2";
gen3_preset_coeff_3_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_3 : string := "g3_prst_coeff_3";
gen3_preset_coeff_4_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_4 : string := "g3_prst_coeff_4";
gen3_preset_coeff_5_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_5 : string := "g3_prst_coeff_5";
gen3_preset_coeff_6_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_6 : string := "g3_prst_coeff_6";
gen3_preset_coeff_7_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_7 : string := "g3_prst_coeff_7";
gen3_preset_coeff_8_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_8 : string := "g3_prst_coeff_8";
gen3_preset_coeff_9_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_9 : string := "g3_prst_coeff_9";
gen3_preset_coeff_10_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_10 : string := "g3_prst_coeff_10";
gen3_rxfreqlock_counter_data : bit_vector := "00000000000000000000";
gen3_rxfreqlock_counter : string := "g3_rxfreqlock_count";
rstctrl_pld_clr : string := "false";-- "false", "true".
rstctrl_debug_en : string := "false";-- "false", "true".
rstctrl_force_inactive_rst : string := "false";-- "false", "true".
rstctrl_perst_enable : string := "level";-- "level", "neg_edge", "not_used".
hrdrstctrl_en : string := "hrdrstctrl_dis";--"hrdrstctrl_dis", "hrdrstctrl_en".
rstctrl_hip_ep : string := "hip_ep"; --"hip_ep", "hip_not_ep".
rstctrl_hard_block_enable : string := "hard_rst_ctl";--"hard_rst_ctl", "pld_rst_ctl".
rstctrl_rx_pma_rstb_inv : string := "false";--"false", "true".
rstctrl_tx_pma_rstb_inv : string := "false";--"false", "true".
rstctrl_rx_pcs_rst_n_inv : string := "false";--"false", "true".
rstctrl_tx_pcs_rst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_crst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_srst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_rst_n_inv : string := "false";--"false", "true".
rstctrl_tx_pma_syncp_inv : string := "false";--"false", "true".
rstctrl_1us_count_fref_clk : string := "rstctrl_1us_cnt";--
rstctrl_1us_count_fref_clk_value : bit_vector := B"00000000000000111111";--
rstctrl_1ms_count_fref_clk : string := "rstctrl_1ms_cnt";--
rstctrl_1ms_count_fref_clk_value : bit_vector := B"00001111010000100100";--
rstctrl_off_cal_done_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
rstctrl_rx_pma_rstb_cmu_select : string := "not_active";-- "ch1cmu_sel", "ch4cmu_sel", "ch4_10cmu_sel", "not_active".
rstctrl_rx_pll_freq_lock_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active", "ch0_phs_sel", "ch01_phs_sel", "ch0123_phs_sel", "ch0123_5678_phs_sel".
rstctrl_mask_tx_pll_lock_select : string := "not_active";-- "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
rstctrl_rx_pll_lock_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
rstctrl_perstn_select : string := "perstn_pin";-- "perstn_pin", "perstn_pld".
rstctrl_tx_lc_pll_rstb_select : string := "not_active";-- "ch1_out", "ch7_out", "not_active".
rstctrl_fref_clk_select : string := "not_active";-- "ch0_sel", "ch1_sel", "ch2_sel", "ch3_sel", "ch4_sel", "ch5_sel", "ch6_sel", "ch7_sel", "ch8_sel", "ch9_sel", "ch10_sel", "ch11_sel".
rstctrl_off_cal_en_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch0123_5678_out", "not_active".
rstctrl_tx_pma_syncp_select : string := "not_active";-- "ch1_out", "ch4_out", "ch4_10_out", "not_active".
rstctrl_rx_pcs_rst_n_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
rstctrl_tx_cmu_pll_lock_select : string := "not_active";-- "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
rstctrl_tx_pcs_rst_n_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
rstctrl_tx_lc_pll_lock_select : string := "not_active";-- "ch1_sel", "ch7_sel", "not_active".
rstctrl_timer_a : string := "rstctrl_timer_a";
rstctrl_timer_a_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_a_value : bit_vector := B"00000001" ;
rstctrl_timer_b : string := "rstctrl_timer_b";
rstctrl_timer_b_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_b_value : bit_vector := B"00000001";
rstctrl_timer_c : string := "rstctrl_timer_c";
rstctrl_timer_c_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_c_value : bit_vector := B"00000001";
rstctrl_timer_d : string := "rstctrl_timer_d";
rstctrl_timer_d_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_d_value : bit_vector := B"00000001";
rstctrl_timer_e : string := "rstctrl_timer_e";
rstctrl_timer_e_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_e_value : bit_vector := B"00000001";
rstctrl_timer_f : string := "rstctrl_timer_f";
rstctrl_timer_f_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_f_value : bit_vector := B"00000001";
rstctrl_timer_g : string := "rstctrl_timer_g";
rstctrl_timer_g_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_g_value : bit_vector := B"00000001";
rstctrl_timer_h : string := "rstctrl_timer_h";
rstctrl_timer_h_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_h_value : bit_vector := B"00000001";
rstctrl_timer_i : string := "rstctrl_timer_i";
rstctrl_timer_i_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_i_value : bit_vector := B"00000001";
rstctrl_timer_j : string := "rstctrl_timer_j";
rstctrl_timer_j_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_j_value : bit_vector := B"00000001"
);
port (
dpriostatus : out std_logic_vector(15 downto 0);
lmidout : out std_logic_vector(31 downto 0);
lmiack : out std_logic_vector(0 downto 0);
lmirden : in std_logic_vector(0 downto 0);
lmiwren : in std_logic_vector(0 downto 0);
lmiaddr : in std_logic_vector(11 downto 0);
lmidin : in std_logic_vector(31 downto 0);
flrreset : in std_logic_vector(0 downto 0);
flrsts : out std_logic_vector(0 downto 0);
resetstatus : out std_logic_vector(0 downto 0);
l2exit : out std_logic_vector(0 downto 0);
hotrstexit : out std_logic_vector(0 downto 0);
hiphardreset : in std_logic_vector(0 downto 0);
dlupexit : out std_logic_vector(0 downto 0);
coreclkout : out std_logic_vector(0 downto 0);
pldclk : in std_logic_vector(0 downto 0);
pldsrst : in std_logic_vector(0 downto 0);
pldrst : in std_logic_vector(0 downto 0);
pclkch0 : in std_logic_vector(0 downto 0);
pclkch1 : in std_logic_vector(0 downto 0);
pclkcentral : in std_logic_vector(0 downto 0);
pllfixedclkch0 : in std_logic_vector(0 downto 0);
pllfixedclkch1 : in std_logic_vector(0 downto 0);
pllfixedclkcentral : in std_logic_vector(0 downto 0);
phyrst : in std_logic_vector(0 downto 0);
physrst : in std_logic_vector(0 downto 0);
coreclkin : in std_logic_vector(0 downto 0);
corerst : in std_logic_vector(0 downto 0);
corepor : in std_logic_vector(0 downto 0);
corecrst : in std_logic_vector(0 downto 0);
coresrst : in std_logic_vector(0 downto 0);
swdnout : out std_logic_vector(6 downto 0);
swupout : out std_logic_vector(2 downto 0);
swdnin : in std_logic_vector(2 downto 0);
swupin : in std_logic_vector(6 downto 0);
swctmod : in std_logic_vector(1 downto 0);
rxstdata : out std_logic_vector(255 downto 0);
rxstparity : out std_logic_vector(31 downto 0);
rxstbe : out std_logic_vector(31 downto 0);
rxsterr : out std_logic_vector(3 downto 0);
rxstsop : out std_logic_vector(3 downto 0);
rxsteop : out std_logic_vector(3 downto 0);
rxstempty : out std_logic_vector(1 downto 0);
rxstvalid : out std_logic_vector(3 downto 0);
rxstbardec1 : out std_logic_vector(7 downto 0);
rxstbardec2 : out std_logic_vector(7 downto 0);
rxstmask : in std_logic_vector(0 downto 0);
rxstready : in std_logic_vector(0 downto 0);
txstready : out std_logic_vector(0 downto 0);
txcredfchipcons : out std_logic_vector(5 downto 0);
txcredfcinfinite : out std_logic_vector(5 downto 0);
txcredhdrfcp : out std_logic_vector(7 downto 0);
txcreddatafcp : out std_logic_vector(11 downto 0);
txcredhdrfcnp : out std_logic_vector(7 downto 0);
txcreddatafcnp : out std_logic_vector(11 downto 0);
txcredhdrfccp : out std_logic_vector(7 downto 0);
txcreddatafccp : out std_logic_vector(11 downto 0);
txstdata : in std_logic_vector(255 downto 0);
txstparity : in std_logic_vector(31 downto 0);
txsterr : in std_logic_vector(3 downto 0);
txstsop : in std_logic_vector(3 downto 0);
txsteop : in std_logic_vector(3 downto 0);
txstempty : in std_logic_vector(1 downto 0);
txstvalid : in std_logic_vector(0 downto 0);
r2cuncecc : out std_logic_vector(0 downto 0);
rxcorrecc : out std_logic_vector(0 downto 0);
retryuncecc : out std_logic_vector(0 downto 0);
retrycorrecc : out std_logic_vector(0 downto 0);
rxparerr : out std_logic_vector(0 downto 0);
txparerr : out std_logic_vector(1 downto 0);
r2cparerr : out std_logic_vector(0 downto 0);
pmetosr : out std_logic_vector(0 downto 0);
pmetocr : in std_logic_vector(0 downto 0);
pmevent : in std_logic_vector(0 downto 0);
pmdata : in std_logic_vector(9 downto 0);
pmauxpwr : in std_logic_vector(0 downto 0);
tlcfgsts : out std_logic_vector(52 downto 0);
tlcfgctl : out std_logic_vector(31 downto 0);
tlcfgadd : out std_logic_vector(3 downto 0);
appintaack : out std_logic_vector(0 downto 0);
appintasts : in std_logic_vector(0 downto 0);
intstatus : out std_logic_vector(3 downto 0);
appmsiack : out std_logic_vector(0 downto 0);
appmsireq : in std_logic_vector(0 downto 0);
appmsitc : in std_logic_vector(2 downto 0);
appmsinum : in std_logic_vector(4 downto 0);
aermsinum : in std_logic_vector(4 downto 0);
pexmsinum : in std_logic_vector(4 downto 0);
hpgctrler : in std_logic_vector(4 downto 0);
cfglink2csrpld : in std_logic_vector(12 downto 0);
cfgprmbuspld : in std_logic_vector(7 downto 0);
csebisshadow : out std_logic_vector(0 downto 0);
csebwrdata : out std_logic_vector(31 downto 0);
csebwrdataparity : out std_logic_vector(3 downto 0);
csebbe : out std_logic_vector(3 downto 0);
csebaddr : out std_logic_vector(32 downto 0);
csebaddrparity : out std_logic_vector(4 downto 0);
csebwren : out std_logic_vector(0 downto 0);
csebrden : out std_logic_vector(0 downto 0);
csebwrrespreq : out std_logic_vector(0 downto 0);
csebrddata : in std_logic_vector(31 downto 0);
csebrddataparity : in std_logic_vector(3 downto 0);
csebwaitrequest : in std_logic_vector(0 downto 0);
csebwrrespvalid : in std_logic_vector(0 downto 0);
csebwrresponse : in std_logic_vector(4 downto 0);
csebrdresponse : in std_logic_vector(4 downto 0);
dlup : out std_logic_vector(0 downto 0);
testouthip : out std_logic_vector(255 downto 0);
testout1hip : out std_logic_vector(63 downto 0);
ev1us : out std_logic_vector(0 downto 0);
ev128ns : out std_logic_vector(0 downto 0);
wakeoen : out std_logic_vector(0 downto 0);
serrout : out std_logic_vector(0 downto 0);
ltssmstate : out std_logic_vector(4 downto 0);
laneact : out std_logic_vector(3 downto 0);
currentspeed : out std_logic_vector(1 downto 0);
slotclkcfg : in std_logic_vector(0 downto 0);
mode : in std_logic_vector(1 downto 0);
testinhip : in std_logic_vector(31 downto 0);
testin1hip : in std_logic_vector(31 downto 0);
cplpending : in std_logic_vector(0 downto 0);
cplerr : in std_logic_vector(6 downto 0);
appinterr : in std_logic_vector(1 downto 0);
egressblkerr : in std_logic_vector(0 downto 0);
pmexitd0ack : in std_logic_vector(0 downto 0);
pmexitd0req : out std_logic_vector(0 downto 0);
currentcoeff0 : out std_logic_vector(17 downto 0);
currentcoeff1 : out std_logic_vector(17 downto 0);
currentcoeff2 : out std_logic_vector(17 downto 0);
currentcoeff3 : out std_logic_vector(17 downto 0);
currentcoeff4 : out std_logic_vector(17 downto 0);
currentcoeff5 : out std_logic_vector(17 downto 0);
currentcoeff6 : out std_logic_vector(17 downto 0);
currentcoeff7 : out std_logic_vector(17 downto 0);
currentrxpreset0 : out std_logic_vector(2 downto 0);
currentrxpreset1 : out std_logic_vector(2 downto 0);
currentrxpreset2 : out std_logic_vector(2 downto 0);
currentrxpreset3 : out std_logic_vector(2 downto 0);
currentrxpreset4 : out std_logic_vector(2 downto 0);
currentrxpreset5 : out std_logic_vector(2 downto 0);
currentrxpreset6 : out std_logic_vector(2 downto 0);
currentrxpreset7 : out std_logic_vector(2 downto 0);
rate0 : out std_logic_vector(1 downto 0);
rate1 : out std_logic_vector(1 downto 0);
rate2 : out std_logic_vector(1 downto 0);
rate3 : out std_logic_vector(1 downto 0);
rate4 : out std_logic_vector(1 downto 0);
rate5 : out std_logic_vector(1 downto 0);
rate6 : out std_logic_vector(1 downto 0);
rate7 : out std_logic_vector(1 downto 0);
ratectrl : out std_logic_vector(1 downto 0);
ratetiedtognd : out std_logic_vector(0 downto 0);
eidleinfersel0 : out std_logic_vector(2 downto 0);
eidleinfersel1 : out std_logic_vector(2 downto 0);
eidleinfersel2 : out std_logic_vector(2 downto 0);
eidleinfersel3 : out std_logic_vector(2 downto 0);
eidleinfersel4 : out std_logic_vector(2 downto 0);
eidleinfersel5 : out std_logic_vector(2 downto 0);
eidleinfersel6 : out std_logic_vector(2 downto 0);
eidleinfersel7 : out std_logic_vector(2 downto 0);
txdata0 : out std_logic_vector(31 downto 0);
txdatak0 : out std_logic_vector(3 downto 0);
txdetectrx0 : out std_logic_vector(0 downto 0);
txelecidle0 : out std_logic_vector(0 downto 0);
txcompl0 : out std_logic_vector(0 downto 0);
rxpolarity0 : out std_logic_vector(0 downto 0);
powerdown0 : out std_logic_vector(1 downto 0);
txdataskip0 : out std_logic_vector(0 downto 0);
txblkst0 : out std_logic_vector(0 downto 0);
txsynchd0 : out std_logic_vector(1 downto 0);
txdeemph0 : out std_logic_vector(0 downto 0);
txmargin0 : out std_logic_vector(2 downto 0);
rxdata0 : in std_logic_vector(31 downto 0);
rxdatak0 : in std_logic_vector(3 downto 0);
rxvalid0 : in std_logic_vector(0 downto 0);
phystatus0 : in std_logic_vector(0 downto 0);
rxelecidle0 : in std_logic_vector(0 downto 0);
rxstatus0 : in std_logic_vector(2 downto 0);
rxdataskip0 : in std_logic_vector(0 downto 0);
rxblkst0 : in std_logic_vector(0 downto 0);
rxsynchd0 : in std_logic_vector(1 downto 0);
rxfreqlocked0 : in std_logic_vector(0 downto 0);
txdata1 : out std_logic_vector(31 downto 0);
txdatak1 : out std_logic_vector(3 downto 0);
txdetectrx1 : out std_logic_vector(0 downto 0);
txelecidle1 : out std_logic_vector(0 downto 0);
txcompl1 : out std_logic_vector(0 downto 0);
rxpolarity1 : out std_logic_vector(0 downto 0);
powerdown1 : out std_logic_vector(1 downto 0);
txdataskip1 : out std_logic_vector(0 downto 0);
txblkst1 : out std_logic_vector(0 downto 0);
txsynchd1 : out std_logic_vector(1 downto 0);
txdeemph1 : out std_logic_vector(0 downto 0);
txmargin1 : out std_logic_vector(2 downto 0);
rxdata1 : in std_logic_vector(31 downto 0);
rxdatak1 : in std_logic_vector(3 downto 0);
rxvalid1 : in std_logic_vector(0 downto 0);
phystatus1 : in std_logic_vector(0 downto 0);
rxelecidle1 : in std_logic_vector(0 downto 0);
rxstatus1 : in std_logic_vector(2 downto 0);
rxdataskip1 : in std_logic_vector(0 downto 0);
rxblkst1 : in std_logic_vector(0 downto 0);
rxsynchd1 : in std_logic_vector(1 downto 0);
rxfreqlocked1 : in std_logic_vector(0 downto 0);
txdata2 : out std_logic_vector(31 downto 0);
txdatak2 : out std_logic_vector(3 downto 0);
txdetectrx2 : out std_logic_vector(0 downto 0);
txelecidle2 : out std_logic_vector(0 downto 0);
txcompl2 : out std_logic_vector(0 downto 0);
rxpolarity2 : out std_logic_vector(0 downto 0);
powerdown2 : out std_logic_vector(1 downto 0);
txdataskip2 : out std_logic_vector(0 downto 0);
txblkst2 : out std_logic_vector(0 downto 0);
txsynchd2 : out std_logic_vector(1 downto 0);
txdeemph2 : out std_logic_vector(0 downto 0);
txmargin2 : out std_logic_vector(2 downto 0);
rxdata2 : in std_logic_vector(31 downto 0);
rxdatak2 : in std_logic_vector(3 downto 0);
rxvalid2 : in std_logic_vector(0 downto 0);
phystatus2 : in std_logic_vector(0 downto 0);
rxelecidle2 : in std_logic_vector(0 downto 0);
rxstatus2 : in std_logic_vector(2 downto 0);
rxdataskip2 : in std_logic_vector(0 downto 0);
rxblkst2 : in std_logic_vector(0 downto 0);
rxsynchd2 : in std_logic_vector(1 downto 0);
rxfreqlocked2 : in std_logic_vector(0 downto 0);
txdata3 : out std_logic_vector(31 downto 0);
txdatak3 : out std_logic_vector(3 downto 0);
txdetectrx3 : out std_logic_vector(0 downto 0);
txelecidle3 : out std_logic_vector(0 downto 0);
txcompl3 : out std_logic_vector(0 downto 0);
rxpolarity3 : out std_logic_vector(0 downto 0);
powerdown3 : out std_logic_vector(1 downto 0);
txdataskip3 : out std_logic_vector(0 downto 0);
txblkst3 : out std_logic_vector(0 downto 0);
txsynchd3 : out std_logic_vector(1 downto 0);
txdeemph3 : out std_logic_vector(0 downto 0);
txmargin3 : out std_logic_vector(2 downto 0);
rxdata3 : in std_logic_vector(31 downto 0);
rxdatak3 : in std_logic_vector(3 downto 0);
rxvalid3 : in std_logic_vector(0 downto 0);
phystatus3 : in std_logic_vector(0 downto 0);
rxelecidle3 : in std_logic_vector(0 downto 0);
rxstatus3 : in std_logic_vector(2 downto 0);
rxdataskip3 : in std_logic_vector(0 downto 0);
rxblkst3 : in std_logic_vector(0 downto 0);
rxsynchd3 : in std_logic_vector(1 downto 0);
rxfreqlocked3 : in std_logic_vector(0 downto 0);
txdata4 : out std_logic_vector(31 downto 0);
txdatak4 : out std_logic_vector(3 downto 0);
txdetectrx4 : out std_logic_vector(0 downto 0);
txelecidle4 : out std_logic_vector(0 downto 0);
txcompl4 : out std_logic_vector(0 downto 0);
rxpolarity4 : out std_logic_vector(0 downto 0);
powerdown4 : out std_logic_vector(1 downto 0);
txdataskip4 : out std_logic_vector(0 downto 0);
txblkst4 : out std_logic_vector(0 downto 0);
txsynchd4 : out std_logic_vector(1 downto 0);
txdeemph4 : out std_logic_vector(0 downto 0);
txmargin4 : out std_logic_vector(2 downto 0);
rxdata4 : in std_logic_vector(31 downto 0);
rxdatak4 : in std_logic_vector(3 downto 0);
rxvalid4 : in std_logic_vector(0 downto 0);
phystatus4 : in std_logic_vector(0 downto 0);
rxelecidle4 : in std_logic_vector(0 downto 0);
rxstatus4 : in std_logic_vector(2 downto 0);
rxdataskip4 : in std_logic_vector(0 downto 0);
rxblkst4 : in std_logic_vector(0 downto 0);
rxsynchd4 : in std_logic_vector(1 downto 0);
rxfreqlocked4 : in std_logic_vector(0 downto 0);
txdata5 : out std_logic_vector(31 downto 0);
txdatak5 : out std_logic_vector(3 downto 0);
txdetectrx5 : out std_logic_vector(0 downto 0);
txelecidle5 : out std_logic_vector(0 downto 0);
txcompl5 : out std_logic_vector(0 downto 0);
rxpolarity5 : out std_logic_vector(0 downto 0);
powerdown5 : out std_logic_vector(1 downto 0);
txdataskip5 : out std_logic_vector(0 downto 0);
txblkst5 : out std_logic_vector(0 downto 0);
txsynchd5 : out std_logic_vector(1 downto 0);
txdeemph5 : out std_logic_vector(0 downto 0);
txmargin5 : out std_logic_vector(2 downto 0);
rxdata5 : in std_logic_vector(31 downto 0);
rxdatak5 : in std_logic_vector(3 downto 0);
rxvalid5 : in std_logic_vector(0 downto 0);
phystatus5 : in std_logic_vector(0 downto 0);
rxelecidle5 : in std_logic_vector(0 downto 0);
rxstatus5 : in std_logic_vector(2 downto 0);
rxdataskip5 : in std_logic_vector(0 downto 0);
rxblkst5 : in std_logic_vector(0 downto 0);
rxsynchd5 : in std_logic_vector(1 downto 0);
rxfreqlocked5 : in std_logic_vector(0 downto 0);
txdata6 : out std_logic_vector(31 downto 0);
txdatak6 : out std_logic_vector(3 downto 0);
txdetectrx6 : out std_logic_vector(0 downto 0);
txelecidle6 : out std_logic_vector(0 downto 0);
txcompl6 : out std_logic_vector(0 downto 0);
rxpolarity6 : out std_logic_vector(0 downto 0);
powerdown6 : out std_logic_vector(1 downto 0);
txdataskip6 : out std_logic_vector(0 downto 0);
txblkst6 : out std_logic_vector(0 downto 0);
txsynchd6 : out std_logic_vector(1 downto 0);
txdeemph6 : out std_logic_vector(0 downto 0);
txmargin6 : out std_logic_vector(2 downto 0);
rxdata6 : in std_logic_vector(31 downto 0);
rxdatak6 : in std_logic_vector(3 downto 0);
rxvalid6 : in std_logic_vector(0 downto 0);
phystatus6 : in std_logic_vector(0 downto 0);
rxelecidle6 : in std_logic_vector(0 downto 0);
rxstatus6 : in std_logic_vector(2 downto 0);
rxdataskip6 : in std_logic_vector(0 downto 0);
rxblkst6 : in std_logic_vector(0 downto 0);
rxsynchd6 : in std_logic_vector(1 downto 0);
rxfreqlocked6 : in std_logic_vector(0 downto 0);
txdata7 : out std_logic_vector(31 downto 0);
txdatak7 : out std_logic_vector(3 downto 0);
txdetectrx7 : out std_logic_vector(0 downto 0);
txelecidle7 : out std_logic_vector(0 downto 0);
txcompl7 : out std_logic_vector(0 downto 0);
rxpolarity7 : out std_logic_vector(0 downto 0);
powerdown7 : out std_logic_vector(1 downto 0);
txdataskip7 : out std_logic_vector(0 downto 0);
txblkst7 : out std_logic_vector(0 downto 0);
txsynchd7 : out std_logic_vector(1 downto 0);
txdeemph7 : out std_logic_vector(0 downto 0);
txmargin7 : out std_logic_vector(2 downto 0);
rxdata7 : in std_logic_vector(31 downto 0);
rxdatak7 : in std_logic_vector(3 downto 0);
rxvalid7 : in std_logic_vector(0 downto 0);
phystatus7 : in std_logic_vector(0 downto 0);
rxelecidle7 : in std_logic_vector(0 downto 0);
rxstatus7 : in std_logic_vector(2 downto 0);
rxdataskip7 : in std_logic_vector(0 downto 0);
rxblkst7 : in std_logic_vector(0 downto 0);
rxsynchd7 : in std_logic_vector(1 downto 0);
rxfreqlocked7 : in std_logic_vector(0 downto 0);
dbgpipex1rx : in std_logic_vector(43 downto 0);
memredsclk : in std_logic_vector(0 downto 0);
memredenscan : in std_logic_vector(0 downto 0);
memredscen : in std_logic_vector(0 downto 0);
memredscin : in std_logic_vector(0 downto 0);
memredscsel : in std_logic_vector(0 downto 0);
memredscrst : in std_logic_vector(0 downto 0);
memredscout : out std_logic_vector(0 downto 0);
memregscanen : in std_logic_vector(0 downto 0);
memregscanin : in std_logic_vector(0 downto 0);
memhiptestenable : in std_logic_vector(0 downto 0);
memregscanout : out std_logic_vector(0 downto 0);
bisttesten : in std_logic_vector(0 downto 0);
bistenrpl : in std_logic_vector(0 downto 0);
bistscanin : in std_logic_vector(0 downto 0);
bistscanen : in std_logic_vector(0 downto 0);
bistenrcv : in std_logic_vector(0 downto 0);
bistscanoutrpl : out std_logic_vector(0 downto 0);
bistdonearpl : out std_logic_vector(0 downto 0);
bistdonebrpl : out std_logic_vector(0 downto 0);
bistpassrpl : out std_logic_vector(0 downto 0);
derrrpl : out std_logic_vector(0 downto 0);
derrcorextrpl : out std_logic_vector(0 downto 0);
bistscanoutrcv : out std_logic_vector(0 downto 0);
bistdonearcv : out std_logic_vector(0 downto 0);
bistdonebrcv : out std_logic_vector(0 downto 0);
bistpassrcv : out std_logic_vector(0 downto 0);
derrcorextrcv : out std_logic_vector(0 downto 0);
bistscanoutrcv1 : out std_logic_vector(0 downto 0);
bistdonearcv1 : out std_logic_vector(0 downto 0);
bistdonebrcv1 : out std_logic_vector(0 downto 0);
bistpassrcv1 : out std_logic_vector(0 downto 0);
derrcorextrcv1 : out std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
nfrzdrv : in std_logic_vector(0 downto 0);
frzreg : in std_logic_vector(0 downto 0);
frzlogic : in std_logic_vector(0 downto 0);
idrpl : in std_logic_vector(7 downto 0);
idrcv : in std_logic_vector(7 downto 0);
plniotri : in std_logic_vector(0 downto 0);
entest : in std_logic_vector(0 downto 0);
npor : in std_logic_vector(0 downto 0);
usermode : in std_logic_vector(0 downto 0);
cvpclk : out std_logic_vector(0 downto 0);
cvpdata : out std_logic_vector(31 downto 0);
cvpstartxfer : out std_logic_vector(0 downto 0);
cvpconfig : out std_logic_vector(0 downto 0);
cvpfullconfig : out std_logic_vector(0 downto 0);
cvpconfigready : in std_logic_vector(0 downto 0);
cvpen : in std_logic_vector(0 downto 0);
cvpconfigerror : in std_logic_vector(0 downto 0);
cvpconfigdone : in std_logic_vector(0 downto 0);
pinperstn : in std_logic_vector(0 downto 0);
pldperstn : in std_logic_vector(0 downto 0);
iocsrrdydly : in std_logic_vector(0 downto 0);
softaltpe3rstn : in std_logic_vector(0 downto 0);
softaltpe3srstn : in std_logic_vector(0 downto 0);
softaltpe3crstn : in std_logic_vector(0 downto 0);
pldclrpmapcshipn : in std_logic_vector(0 downto 0);
pldclrpcshipn : in std_logic_vector(0 downto 0);
pldclrhipn : in std_logic_vector(0 downto 0);
s0ch0emsiptieoff : out std_logic_vector(100 downto 0);
s0ch1emsiptieoff : out std_logic_vector(100 downto 0);
s0ch2emsiptieoff : out std_logic_vector(100 downto 0);
s1ch0emsiptieoff : out std_logic_vector(100 downto 0);
s1ch1emsiptieoff : out std_logic_vector(188 downto 0);
s1ch2emsiptieoff : out std_logic_vector(100 downto 0);
s2ch0emsiptieoff : out std_logic_vector(100 downto 0);
s2ch1emsiptieoff : out std_logic_vector(100 downto 0);
s2ch2emsiptieoff : out std_logic_vector(100 downto 0);
s3ch0emsiptieoff : out std_logic_vector(188 downto 0);
s3ch1emsiptieoff : out std_logic_vector(188 downto 0);
s3ch2emsiptieoff : out std_logic_vector(188 downto 0);
emsiptieofftop : out std_logic_vector(299 downto 0);
emsiptieoffbot : out std_logic_vector(299 downto 0);
txpcsrstn0 : out std_logic_vector(0 downto 0);
rxpcsrstn0 : out std_logic_vector(0 downto 0);
g3txpcsrstn0 : out std_logic_vector(0 downto 0);
g3rxpcsrstn0 : out std_logic_vector(0 downto 0);
txpmasyncp0 : out std_logic_vector(0 downto 0);
rxpmarstb0 : out std_logic_vector(0 downto 0);
txlcpllrstb0 : out std_logic_vector(0 downto 0);
offcalen0 : out std_logic_vector(0 downto 0);
frefclk0 : in std_logic_vector(0 downto 0);
offcaldone0 : in std_logic_vector(0 downto 0);
txlcplllock0 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock0 : in std_logic_vector(0 downto 0);
rxpllphaselock0 : in std_logic_vector(0 downto 0);
masktxplllock0 : in std_logic_vector(0 downto 0);
txpcsrstn1 : out std_logic_vector(0 downto 0);
rxpcsrstn1 : out std_logic_vector(0 downto 0);
g3txpcsrstn1 : out std_logic_vector(0 downto 0);
g3rxpcsrstn1 : out std_logic_vector(0 downto 0);
txpmasyncp1 : out std_logic_vector(0 downto 0);
rxpmarstb1 : out std_logic_vector(0 downto 0);
txlcpllrstb1 : out std_logic_vector(0 downto 0);
offcalen1 : out std_logic_vector(0 downto 0);
frefclk1 : in std_logic_vector(0 downto 0);
offcaldone1 : in std_logic_vector(0 downto 0);
txlcplllock1 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock1 : in std_logic_vector(0 downto 0);
rxpllphaselock1 : in std_logic_vector(0 downto 0);
masktxplllock1 : in std_logic_vector(0 downto 0);
txpcsrstn2 : out std_logic_vector(0 downto 0);
rxpcsrstn2 : out std_logic_vector(0 downto 0);
g3txpcsrstn2 : out std_logic_vector(0 downto 0);
g3rxpcsrstn2 : out std_logic_vector(0 downto 0);
txpmasyncp2 : out std_logic_vector(0 downto 0);
rxpmarstb2 : out std_logic_vector(0 downto 0);
txlcpllrstb2 : out std_logic_vector(0 downto 0);
offcalen2 : out std_logic_vector(0 downto 0);
frefclk2 : in std_logic_vector(0 downto 0);
offcaldone2 : in std_logic_vector(0 downto 0);
txlcplllock2 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock2 : in std_logic_vector(0 downto 0);
rxpllphaselock2 : in std_logic_vector(0 downto 0);
masktxplllock2 : in std_logic_vector(0 downto 0);
txpcsrstn3 : out std_logic_vector(0 downto 0);
rxpcsrstn3 : out std_logic_vector(0 downto 0);
g3txpcsrstn3 : out std_logic_vector(0 downto 0);
g3rxpcsrstn3 : out std_logic_vector(0 downto 0);
txpmasyncp3 : out std_logic_vector(0 downto 0);
rxpmarstb3 : out std_logic_vector(0 downto 0);
txlcpllrstb3 : out std_logic_vector(0 downto 0);
offcalen3 : out std_logic_vector(0 downto 0);
frefclk3 : in std_logic_vector(0 downto 0);
offcaldone3 : in std_logic_vector(0 downto 0);
txlcplllock3 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock3 : in std_logic_vector(0 downto 0);
rxpllphaselock3 : in std_logic_vector(0 downto 0);
masktxplllock3 : in std_logic_vector(0 downto 0);
txpcsrstn4 : out std_logic_vector(0 downto 0);
rxpcsrstn4 : out std_logic_vector(0 downto 0);
g3txpcsrstn4 : out std_logic_vector(0 downto 0);
g3rxpcsrstn4 : out std_logic_vector(0 downto 0);
txpmasyncp4 : out std_logic_vector(0 downto 0);
rxpmarstb4 : out std_logic_vector(0 downto 0);
txlcpllrstb4 : out std_logic_vector(0 downto 0);
offcalen4 : out std_logic_vector(0 downto 0);
frefclk4 : in std_logic_vector(0 downto 0);
offcaldone4 : in std_logic_vector(0 downto 0);
txlcplllock4 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock4 : in std_logic_vector(0 downto 0);
rxpllphaselock4 : in std_logic_vector(0 downto 0);
masktxplllock4 : in std_logic_vector(0 downto 0);
txpcsrstn5 : out std_logic_vector(0 downto 0);
rxpcsrstn5 : out std_logic_vector(0 downto 0);
g3txpcsrstn5 : out std_logic_vector(0 downto 0);
g3rxpcsrstn5 : out std_logic_vector(0 downto 0);
txpmasyncp5 : out std_logic_vector(0 downto 0);
rxpmarstb5 : out std_logic_vector(0 downto 0);
txlcpllrstb5 : out std_logic_vector(0 downto 0);
offcalen5 : out std_logic_vector(0 downto 0);
frefclk5 : in std_logic_vector(0 downto 0);
offcaldone5 : in std_logic_vector(0 downto 0);
txlcplllock5 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock5 : in std_logic_vector(0 downto 0);
rxpllphaselock5 : in std_logic_vector(0 downto 0);
masktxplllock5 : in std_logic_vector(0 downto 0);
txpcsrstn6 : out std_logic_vector(0 downto 0);
rxpcsrstn6 : out std_logic_vector(0 downto 0);
g3txpcsrstn6 : out std_logic_vector(0 downto 0);
g3rxpcsrstn6 : out std_logic_vector(0 downto 0);
txpmasyncp6 : out std_logic_vector(0 downto 0);
rxpmarstb6 : out std_logic_vector(0 downto 0);
txlcpllrstb6 : out std_logic_vector(0 downto 0);
offcalen6 : out std_logic_vector(0 downto 0);
frefclk6 : in std_logic_vector(0 downto 0);
offcaldone6 : in std_logic_vector(0 downto 0);
txlcplllock6 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock6 : in std_logic_vector(0 downto 0);
rxpllphaselock6 : in std_logic_vector(0 downto 0);
masktxplllock6 : in std_logic_vector(0 downto 0);
txpcsrstn7 : out std_logic_vector(0 downto 0);
rxpcsrstn7 : out std_logic_vector(0 downto 0);
g3txpcsrstn7 : out std_logic_vector(0 downto 0);
g3rxpcsrstn7 : out std_logic_vector(0 downto 0);
txpmasyncp7 : out std_logic_vector(0 downto 0);
rxpmarstb7 : out std_logic_vector(0 downto 0);
txlcpllrstb7 : out std_logic_vector(0 downto 0);
offcalen7 : out std_logic_vector(0 downto 0);
frefclk7 : in std_logic_vector(0 downto 0);
offcaldone7 : in std_logic_vector(0 downto 0);
txlcplllock7 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock7 : in std_logic_vector(0 downto 0);
rxpllphaselock7 : in std_logic_vector(0 downto 0);
masktxplllock7 : in std_logic_vector(0 downto 0);
txpcsrstn8 : out std_logic_vector(0 downto 0);
rxpcsrstn8 : out std_logic_vector(0 downto 0);
g3txpcsrstn8 : out std_logic_vector(0 downto 0);
g3rxpcsrstn8 : out std_logic_vector(0 downto 0);
txpmasyncp8 : out std_logic_vector(0 downto 0);
rxpmarstb8 : out std_logic_vector(0 downto 0);
txlcpllrstb8 : out std_logic_vector(0 downto 0);
offcalen8 : out std_logic_vector(0 downto 0);
frefclk8 : in std_logic_vector(0 downto 0);
offcaldone8 : in std_logic_vector(0 downto 0);
txlcplllock8 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock8 : in std_logic_vector(0 downto 0);
rxpllphaselock8 : in std_logic_vector(0 downto 0);
masktxplllock8 : in std_logic_vector(0 downto 0);
txpcsrstn9 : out std_logic_vector(0 downto 0);
rxpcsrstn9 : out std_logic_vector(0 downto 0);
g3txpcsrstn9 : out std_logic_vector(0 downto 0);
g3rxpcsrstn9 : out std_logic_vector(0 downto 0);
txpmasyncp9 : out std_logic_vector(0 downto 0);
rxpmarstb9 : out std_logic_vector(0 downto 0);
txlcpllrstb9 : out std_logic_vector(0 downto 0);
offcalen9 : out std_logic_vector(0 downto 0);
frefclk9 : in std_logic_vector(0 downto 0);
offcaldone9 : in std_logic_vector(0 downto 0);
txlcplllock9 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock9 : in std_logic_vector(0 downto 0);
rxpllphaselock9 : in std_logic_vector(0 downto 0);
masktxplllock9 : in std_logic_vector(0 downto 0);
txpcsrstn10 : out std_logic_vector(0 downto 0);
rxpcsrstn10 : out std_logic_vector(0 downto 0);
g3txpcsrstn10 : out std_logic_vector(0 downto 0);
g3rxpcsrstn10 : out std_logic_vector(0 downto 0);
txpmasyncp10 : out std_logic_vector(0 downto 0);
rxpmarstb10 : out std_logic_vector(0 downto 0);
txlcpllrstb10 : out std_logic_vector(0 downto 0);
offcalen10 : out std_logic_vector(0 downto 0);
frefclk10 : in std_logic_vector(0 downto 0);
offcaldone10 : in std_logic_vector(0 downto 0);
txlcplllock10 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock10 : in std_logic_vector(0 downto 0);
rxpllphaselock10 : in std_logic_vector(0 downto 0);
masktxplllock10 : in std_logic_vector(0 downto 0);
txpcsrstn11 : out std_logic_vector(0 downto 0);
rxpcsrstn11 : out std_logic_vector(0 downto 0);
g3txpcsrstn11 : out std_logic_vector(0 downto 0);
g3rxpcsrstn11 : out std_logic_vector(0 downto 0);
txpmasyncp11 : out std_logic_vector(0 downto 0);
rxpmarstb11 : out std_logic_vector(0 downto 0);
txlcpllrstb11 : out std_logic_vector(0 downto 0);
offcalen11 : out std_logic_vector(0 downto 0);
frefclk11 : in std_logic_vector(0 downto 0);
offcaldone11 : in std_logic_vector(0 downto 0);
txlcplllock11 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock11 : in std_logic_vector(0 downto 0);
rxpllphaselock11 : in std_logic_vector(0 downto 0);
masktxplllock11 : in std_logic_vector(0 downto 0);
reservedin : in std_logic_vector(31 downto 0);
reservedclkin : in std_logic_vector(0 downto 0);
reservedout : out std_logic_vector(31 downto 0);
reservedclkout : out std_logic_vector(0 downto 0)
);
end component;
begin
inst : stratixv_hssi_gen3_pcie_hip_encrypted
generic map (
func_mode => func_mode,
in_cvp_mode => in_cvp_mode,
bonding_mode => bonding_mode,
prot_mode => prot_mode,
pcie_spec_1p0_compliance => pcie_spec_1p0_compliance,
vc_enable => vc_enable,
enable_slot_register => enable_slot_register,
pcie_mode => pcie_mode,
bypass_cdc => bypass_cdc,
enable_rx_reordering => enable_rx_reordering,
enable_rx_buffer_checking => enable_rx_buffer_checking,
single_rx_detect_data => single_rx_detect_data,
single_rx_detect => single_rx_detect,
use_crc_forwarding => use_crc_forwarding,
bypass_tl => bypass_tl,
gen123_lane_rate_mode => gen123_lane_rate_mode,
lane_mask => lane_mask,
disable_link_x2_support => disable_link_x2_support,
national_inst_thru_enhance => national_inst_thru_enhance,
hip_hard_reset => hip_hard_reset,
dis_paritychk => dis_paritychk,
wrong_device_id => wrong_device_id,
data_pack_rx => data_pack_rx,
ast_width => ast_width,
rx_sop_ctrl => rx_sop_ctrl,
rx_ast_parity => rx_ast_parity,
tx_ast_parity => tx_ast_parity,
ltssm_1ms_timeout => ltssm_1ms_timeout,
ltssm_freqlocked_check => ltssm_freqlocked_check,
deskew_comma => deskew_comma,
dl_tx_check_parity_edb => dl_tx_check_parity_edb,
tl_tx_check_parity_msg => tl_tx_check_parity_msg,
port_link_number_data => port_link_number_data,
port_link_number => port_link_number,
device_number_data => device_number_data,
device_number => device_number,
bypass_clk_switch => bypass_clk_switch,
core_clk_out_sel => core_clk_out_sel,
core_clk_divider => core_clk_divider,
core_clk_source => core_clk_source,
core_clk_sel => core_clk_sel,
enable_ch0_pclk_out => enable_ch0_pclk_out,
enable_ch01_pclk_out => enable_ch01_pclk_out,
pipex1_debug_sel => pipex1_debug_sel,
pclk_out_sel => pclk_out_sel,
vendor_id_data => vendor_id_data,
vendor_id => vendor_id,
device_id_data => device_id_data,
device_id => device_id,
revision_id_data => revision_id_data,
revision_id => revision_id,
class_code_data => class_code_data,
class_code => class_code,
subsystem_vendor_id_data => subsystem_vendor_id_data,
subsystem_vendor_id => subsystem_vendor_id,
subsystem_device_id_data => subsystem_device_id_data,
subsystem_device_id => subsystem_device_id,
no_soft_reset => no_soft_reset,
maximum_current_data => maximum_current_data,
maximum_current => maximum_current,
d1_support => d1_support,
d2_support => d2_support,
d0_pme => d0_pme,
d1_pme => d1_pme,
d2_pme => d2_pme,
d3_hot_pme => d3_hot_pme,
d3_cold_pme => d3_cold_pme,
use_aer => use_aer,
low_priority_vc => low_priority_vc,
vc_arbitration => vc_arbitration,
disable_snoop_packet => disable_snoop_packet,
max_payload_size => max_payload_size,
surprise_down_error_support => surprise_down_error_support,
dll_active_report_support => dll_active_report_support,
extend_tag_field => extend_tag_field,
endpoint_l0_latency_data => endpoint_l0_latency_data,
endpoint_l0_latency => endpoint_l0_latency,
endpoint_l1_latency_data => endpoint_l1_latency_data,
endpoint_l1_latency => endpoint_l1_latency,
indicator_data => indicator_data,
indicator => indicator,
role_based_error_reporting => role_based_error_reporting,
slot_power_scale_data => slot_power_scale_data,
slot_power_scale => slot_power_scale,
max_link_width => max_link_width,
enable_l1_aspm => enable_l1_aspm,
enable_l0s_aspm => enable_l0s_aspm,
l1_exit_latency_sameclock_data => l1_exit_latency_sameclock_data,
l1_exit_latency_sameclock => l1_exit_latency_sameclock,
l1_exit_latency_diffclock_data => l1_exit_latency_diffclock_data,
l1_exit_latency_diffclock => l1_exit_latency_diffclock,
hot_plug_support_data => hot_plug_support_data,
hot_plug_support => hot_plug_support,
slot_power_limit_data => slot_power_limit_data,
slot_power_limit => slot_power_limit,
slot_number_data => slot_number_data,
slot_number => slot_number,
diffclock_nfts_count_data => diffclock_nfts_count_data,
diffclock_nfts_count => diffclock_nfts_count,
sameclock_nfts_count_data => sameclock_nfts_count_data,
sameclock_nfts_count => sameclock_nfts_count,
completion_timeout => completion_timeout,
enable_completion_timeout_disable => enable_completion_timeout_disable,
extended_tag_reset => extended_tag_reset,
ecrc_check_capable => ecrc_check_capable,
ecrc_gen_capable => ecrc_gen_capable,
no_command_completed => no_command_completed,
msi_multi_message_capable => msi_multi_message_capable,
msi_64bit_addressing_capable => msi_64bit_addressing_capable,
msi_masking_capable => msi_masking_capable,
msi_support => msi_support,
interrupt_pin => interrupt_pin,
ena_ido_req => ena_ido_req,
ena_ido_cpl => ena_ido_cpl,
enable_function_msix_support => enable_function_msix_support,
msix_table_size_data => msix_table_size_data,
msix_table_size => msix_table_size,
msix_table_bir_data => msix_table_bir_data,
msix_table_bir => msix_table_bir,
msix_table_offset_data => msix_table_offset_data,
msix_table_offset => msix_table_offset,
msix_pba_bir_data => msix_pba_bir_data,
msix_pba_bir => msix_pba_bir,
msix_pba_offset_data => msix_pba_offset_data,
msix_pba_offset => msix_pba_offset,
bridge_port_vga_enable => bridge_port_vga_enable,
bridge_port_ssid_support => bridge_port_ssid_support,
ssvid_data => ssvid_data,
ssvid => ssvid,
ssid_data => ssid_data,
ssid => ssid,
eie_before_nfts_count_data => eie_before_nfts_count_data,
eie_before_nfts_count => eie_before_nfts_count,
gen2_diffclock_nfts_count_data => gen2_diffclock_nfts_count_data,
gen2_diffclock_nfts_count => gen2_diffclock_nfts_count,
gen2_sameclock_nfts_count_data => gen2_sameclock_nfts_count_data,
gen2_sameclock_nfts_count => gen2_sameclock_nfts_count,
deemphasis_enable => deemphasis_enable,
pcie_spec_version => pcie_spec_version,
l0_exit_latency_sameclock_data => l0_exit_latency_sameclock_data,
l0_exit_latency_sameclock => l0_exit_latency_sameclock,
l0_exit_latency_diffclock_data => l0_exit_latency_diffclock_data,
l0_exit_latency_diffclock => l0_exit_latency_diffclock,
rx_ei_l0s => rx_ei_l0s,
l2_async_logic => l2_async_logic,
aspm_config_management => aspm_config_management,
atomic_op_routing => atomic_op_routing,
atomic_op_completer_32bit => atomic_op_completer_32bit,
atomic_op_completer_64bit => atomic_op_completer_64bit,
cas_completer_128bit => cas_completer_128bit,
ltr_mechanism => ltr_mechanism,
tph_completer => tph_completer,
extended_format_field => extended_format_field,
atomic_malformed => atomic_malformed,
flr_capability => flr_capability,
enable_adapter_half_rate_mode => enable_adapter_half_rate_mode,
vc0_clk_enable => vc0_clk_enable,
vc1_clk_enable => vc1_clk_enable,
register_pipe_signals => register_pipe_signals,
bar0_io_space => bar0_io_space,
bar0_64bit_mem_space => bar0_64bit_mem_space,
bar0_prefetchable => bar0_prefetchable,
bar0_size_mask_data => bar0_size_mask_data,
bar0_size_mask => bar0_size_mask,
bar1_io_space => bar1_io_space,
bar1_64bit_mem_space => bar1_64bit_mem_space,
bar1_prefetchable => bar1_prefetchable,
bar1_size_mask_data => bar1_size_mask_data,
bar1_size_mask => bar1_size_mask,
bar2_io_space => bar2_io_space,
bar2_64bit_mem_space => bar2_64bit_mem_space,
bar2_prefetchable => bar2_prefetchable,
bar2_size_mask_data => bar2_size_mask_data,
bar2_size_mask => bar2_size_mask,
bar3_io_space => bar3_io_space,
bar3_64bit_mem_space => bar3_64bit_mem_space,
bar3_prefetchable => bar3_prefetchable,
bar3_size_mask_data => bar3_size_mask_data,
bar3_size_mask => bar3_size_mask,
bar4_io_space => bar4_io_space,
bar4_64bit_mem_space => bar4_64bit_mem_space,
bar4_prefetchable => bar4_prefetchable,
bar4_size_mask_data => bar4_size_mask_data,
bar4_size_mask => bar4_size_mask,
bar5_io_space => bar5_io_space,
bar5_64bit_mem_space => bar5_64bit_mem_space,
bar5_prefetchable => bar5_prefetchable,
bar5_size_mask_data => bar5_size_mask_data,
bar5_size_mask => bar5_size_mask,
expansion_base_address_register_data => expansion_base_address_register_data,
expansion_base_address_register => expansion_base_address_register,
io_window_addr_width => io_window_addr_width,
prefetchable_mem_window_addr_width => prefetchable_mem_window_addr_width,
skp_os_gen3_count_data => skp_os_gen3_count_data,
skp_os_gen3_count => skp_os_gen3_count,
rx_cdc_almost_empty_data => rx_cdc_almost_empty_data,
rx_cdc_almost_empty => rx_cdc_almost_empty,
tx_cdc_almost_empty_data => tx_cdc_almost_empty_data,
tx_cdc_almost_empty => tx_cdc_almost_empty,
rx_cdc_almost_full_data => rx_cdc_almost_full_data,
rx_cdc_almost_full => rx_cdc_almost_full,
tx_cdc_almost_full_data => tx_cdc_almost_full_data,
tx_cdc_almost_full => tx_cdc_almost_full,
rx_l0s_count_idl_data => rx_l0s_count_idl_data,
rx_l0s_count_idl => rx_l0s_count_idl,
cdc_dummy_insert_limit_data => cdc_dummy_insert_limit_data,
cdc_dummy_insert_limit => cdc_dummy_insert_limit,
ei_delay_powerdown_count_data => ei_delay_powerdown_count_data,
ei_delay_powerdown_count => ei_delay_powerdown_count,
millisecond_cycle_count_data => millisecond_cycle_count_data,
millisecond_cycle_count => millisecond_cycle_count,
skp_os_schedule_count_data => skp_os_schedule_count_data,
skp_os_schedule_count => skp_os_schedule_count,
fc_init_timer_data => fc_init_timer_data,
fc_init_timer => fc_init_timer,
l01_entry_latency_data => l01_entry_latency_data,
l01_entry_latency => l01_entry_latency,
flow_control_update_count_data => flow_control_update_count_data,
flow_control_update_count => flow_control_update_count,
flow_control_timeout_count_data => flow_control_timeout_count_data,
flow_control_timeout_count => flow_control_timeout_count,
vc0_rx_flow_ctrl_posted_header_data => vc0_rx_flow_ctrl_posted_header_data,
vc0_rx_flow_ctrl_posted_header => vc0_rx_flow_ctrl_posted_header,
vc0_rx_flow_ctrl_posted_data_data => vc0_rx_flow_ctrl_posted_data_data,
vc0_rx_flow_ctrl_posted_data => vc0_rx_flow_ctrl_posted_data,
vc0_rx_flow_ctrl_nonposted_header_data => vc0_rx_flow_ctrl_nonposted_header_data,
vc0_rx_flow_ctrl_nonposted_header => vc0_rx_flow_ctrl_nonposted_header,
vc0_rx_flow_ctrl_nonposted_data_data => vc0_rx_flow_ctrl_nonposted_data_data,
vc0_rx_flow_ctrl_nonposted_data => vc0_rx_flow_ctrl_nonposted_data,
vc0_rx_flow_ctrl_compl_header_data => vc0_rx_flow_ctrl_compl_header_data,
vc0_rx_flow_ctrl_compl_header => vc0_rx_flow_ctrl_compl_header,
vc0_rx_flow_ctrl_compl_data_data => vc0_rx_flow_ctrl_compl_data_data,
vc0_rx_flow_ctrl_compl_data => vc0_rx_flow_ctrl_compl_data,
rx_ptr0_posted_dpram_min_data => rx_ptr0_posted_dpram_min_data,
rx_ptr0_posted_dpram_min => rx_ptr0_posted_dpram_min,
rx_ptr0_posted_dpram_max_data => rx_ptr0_posted_dpram_max_data,
rx_ptr0_posted_dpram_max => rx_ptr0_posted_dpram_max,
rx_ptr0_nonposted_dpram_min_data => rx_ptr0_nonposted_dpram_min_data,
rx_ptr0_nonposted_dpram_min => rx_ptr0_nonposted_dpram_min,
rx_ptr0_nonposted_dpram_max_data => rx_ptr0_nonposted_dpram_max_data,
rx_ptr0_nonposted_dpram_max => rx_ptr0_nonposted_dpram_max,
retry_buffer_last_active_address_data => retry_buffer_last_active_address_data,
retry_buffer_last_active_address => retry_buffer_last_active_address,
retry_buffer_memory_settings_data => retry_buffer_memory_settings_data,
retry_buffer_memory_settings => retry_buffer_memory_settings,
vc0_rx_buffer_memory_settings_data => vc0_rx_buffer_memory_settings_data,
vc0_rx_buffer_memory_settings => vc0_rx_buffer_memory_settings,
bist_memory_settings_data => bist_memory_settings_data,
bist_memory_settings => bist_memory_settings,
credit_buffer_allocation_aux => credit_buffer_allocation_aux,
iei_enable_settings => iei_enable_settings,
vsec_id_data => vsec_id_data,
vsec_id => vsec_id,
cvp_rate_sel => cvp_rate_sel,
hard_reset_bypass => hard_reset_bypass,
cvp_data_compressed => cvp_data_compressed,
cvp_data_encrypted => cvp_data_encrypted,
cvp_mode_reset => cvp_mode_reset,
cvp_clk_reset => cvp_clk_reset,
vsec_cap_data => vsec_cap_data,
vsec_cap => vsec_cap,
jtag_id_data => jtag_id_data,
jtag_id => jtag_id,
user_id_data => user_id_data,
user_id => user_id,
cseb_extend_pci => cseb_extend_pci,
cseb_extend_pcie => cseb_extend_pcie,
cseb_cpl_status_during_cvp => cseb_cpl_status_during_cvp,
cseb_route_to_avl_rx_st => cseb_route_to_avl_rx_st,
cseb_config_bypass => cseb_config_bypass,
cseb_cpl_tag_checking => cseb_cpl_tag_checking,
cseb_bar_match_checking => cseb_bar_match_checking,
cseb_min_error_checking => cseb_min_error_checking,
cseb_temp_busy_crs => cseb_temp_busy_crs,
cseb_disable_auto_crs => cseb_disable_auto_crs,
gen3_diffclock_nfts_count_data => gen3_diffclock_nfts_count_data,
gen3_diffclock_nfts_count => gen3_diffclock_nfts_count,
gen3_sameclock_nfts_count_data => gen3_sameclock_nfts_count_data,
gen3_sameclock_nfts_count => gen3_sameclock_nfts_count,
gen3_coeff_errchk => gen3_coeff_errchk,
gen3_paritychk => gen3_paritychk,
gen3_coeff_delay_count_data => gen3_coeff_delay_count_data,
gen3_coeff_delay_count => gen3_coeff_delay_count,
gen3_coeff_1_data => gen3_coeff_1_data,
gen3_coeff_1 => gen3_coeff_1,
gen3_coeff_1_sel => gen3_coeff_1_sel,
gen3_coeff_1_preset_hint_data => gen3_coeff_1_preset_hint_data,
gen3_coeff_1_preset_hint => gen3_coeff_1_preset_hint,
gen3_coeff_1_nxtber_more_ptr => gen3_coeff_1_nxtber_more_ptr,
gen3_coeff_1_nxtber_more => gen3_coeff_1_nxtber_more,
gen3_coeff_1_nxtber_less_ptr => gen3_coeff_1_nxtber_less_ptr,
gen3_coeff_1_nxtber_less => gen3_coeff_1_nxtber_less,
gen3_coeff_1_reqber_data => gen3_coeff_1_reqber_data,
gen3_coeff_1_reqber => gen3_coeff_1_reqber,
gen3_coeff_1_ber_meas_data => gen3_coeff_1_ber_meas_data,
gen3_coeff_1_ber_meas => gen3_coeff_1_ber_meas,
gen3_coeff_2_data => gen3_coeff_2_data,
gen3_coeff_2 => gen3_coeff_2,
gen3_coeff_2_sel => gen3_coeff_2_sel,
gen3_coeff_2_preset_hint_data => gen3_coeff_2_preset_hint_data,
gen3_coeff_2_preset_hint => gen3_coeff_2_preset_hint,
gen3_coeff_2_nxtber_more_ptr => gen3_coeff_2_nxtber_more_ptr,
gen3_coeff_2_nxtber_more => gen3_coeff_2_nxtber_more,
gen3_coeff_2_nxtber_less_ptr => gen3_coeff_2_nxtber_less_ptr,
gen3_coeff_2_nxtber_less => gen3_coeff_2_nxtber_less,
gen3_coeff_2_reqber_data => gen3_coeff_2_reqber_data,
gen3_coeff_2_reqber => gen3_coeff_2_reqber,
gen3_coeff_2_ber_meas_data => gen3_coeff_2_ber_meas_data,
gen3_coeff_2_ber_meas => gen3_coeff_2_ber_meas,
gen3_coeff_3_data => gen3_coeff_3_data,
gen3_coeff_3 => gen3_coeff_3,
gen3_coeff_3_sel => gen3_coeff_3_sel,
gen3_coeff_3_preset_hint_data => gen3_coeff_3_preset_hint_data,
gen3_coeff_3_preset_hint => gen3_coeff_3_preset_hint,
gen3_coeff_3_nxtber_more_ptr => gen3_coeff_3_nxtber_more_ptr,
gen3_coeff_3_nxtber_more => gen3_coeff_3_nxtber_more,
gen3_coeff_3_nxtber_less_ptr => gen3_coeff_3_nxtber_less_ptr,
gen3_coeff_3_nxtber_less => gen3_coeff_3_nxtber_less,
gen3_coeff_3_reqber_data => gen3_coeff_3_reqber_data,
gen3_coeff_3_reqber => gen3_coeff_3_reqber,
gen3_coeff_3_ber_meas_data => gen3_coeff_3_ber_meas_data,
gen3_coeff_3_ber_meas => gen3_coeff_3_ber_meas,
gen3_coeff_4_data => gen3_coeff_4_data,
gen3_coeff_4 => gen3_coeff_4,
gen3_coeff_4_sel => gen3_coeff_4_sel,
gen3_coeff_4_preset_hint_data => gen3_coeff_4_preset_hint_data,
gen3_coeff_4_preset_hint => gen3_coeff_4_preset_hint,
gen3_coeff_4_nxtber_more_ptr => gen3_coeff_4_nxtber_more_ptr,
gen3_coeff_4_nxtber_more => gen3_coeff_4_nxtber_more,
gen3_coeff_4_nxtber_less_ptr => gen3_coeff_4_nxtber_less_ptr,
gen3_coeff_4_nxtber_less => gen3_coeff_4_nxtber_less,
gen3_coeff_4_reqber_data => gen3_coeff_4_reqber_data,
gen3_coeff_4_reqber => gen3_coeff_4_reqber,
gen3_coeff_4_ber_meas_data => gen3_coeff_4_ber_meas_data,
gen3_coeff_4_ber_meas => gen3_coeff_4_ber_meas,
gen3_coeff_5_data => gen3_coeff_5_data,
gen3_coeff_5 => gen3_coeff_5,
gen3_coeff_5_sel => gen3_coeff_5_sel,
gen3_coeff_5_preset_hint_data => gen3_coeff_5_preset_hint_data,
gen3_coeff_5_preset_hint => gen3_coeff_5_preset_hint,
gen3_coeff_5_nxtber_more_ptr => gen3_coeff_5_nxtber_more_ptr,
gen3_coeff_5_nxtber_more => gen3_coeff_5_nxtber_more,
gen3_coeff_5_nxtber_less_ptr => gen3_coeff_5_nxtber_less_ptr,
gen3_coeff_5_nxtber_less => gen3_coeff_5_nxtber_less,
gen3_coeff_5_reqber_data => gen3_coeff_5_reqber_data,
gen3_coeff_5_reqber => gen3_coeff_5_reqber,
gen3_coeff_5_ber_meas_data => gen3_coeff_5_ber_meas_data,
gen3_coeff_5_ber_meas => gen3_coeff_5_ber_meas,
gen3_coeff_6_data => gen3_coeff_6_data,
gen3_coeff_6 => gen3_coeff_6,
gen3_coeff_6_sel => gen3_coeff_6_sel,
gen3_coeff_6_preset_hint_data => gen3_coeff_6_preset_hint_data,
gen3_coeff_6_preset_hint => gen3_coeff_6_preset_hint,
gen3_coeff_6_nxtber_more_ptr => gen3_coeff_6_nxtber_more_ptr,
gen3_coeff_6_nxtber_more => gen3_coeff_6_nxtber_more,
gen3_coeff_6_nxtber_less_ptr => gen3_coeff_6_nxtber_less_ptr,
gen3_coeff_6_nxtber_less => gen3_coeff_6_nxtber_less,
gen3_coeff_6_reqber_data => gen3_coeff_6_reqber_data,
gen3_coeff_6_reqber => gen3_coeff_6_reqber,
gen3_coeff_6_ber_meas_data => gen3_coeff_6_ber_meas_data,
gen3_coeff_6_ber_meas => gen3_coeff_6_ber_meas,
gen3_coeff_7_data => gen3_coeff_7_data,
gen3_coeff_7 => gen3_coeff_7,
gen3_coeff_7_sel => gen3_coeff_7_sel,
gen3_coeff_7_preset_hint_data => gen3_coeff_7_preset_hint_data,
gen3_coeff_7_preset_hint => gen3_coeff_7_preset_hint,
gen3_coeff_7_nxtber_more_ptr => gen3_coeff_7_nxtber_more_ptr,
gen3_coeff_7_nxtber_more => gen3_coeff_7_nxtber_more,
gen3_coeff_7_nxtber_less_ptr => gen3_coeff_7_nxtber_less_ptr,
gen3_coeff_7_nxtber_less => gen3_coeff_7_nxtber_less,
gen3_coeff_7_reqber_data => gen3_coeff_7_reqber_data,
gen3_coeff_7_reqber => gen3_coeff_7_reqber,
gen3_coeff_7_ber_meas_data => gen3_coeff_7_ber_meas_data,
gen3_coeff_7_ber_meas => gen3_coeff_7_ber_meas,
gen3_coeff_8_data => gen3_coeff_8_data,
gen3_coeff_8 => gen3_coeff_8,
gen3_coeff_8_sel => gen3_coeff_8_sel,
gen3_coeff_8_preset_hint_data => gen3_coeff_8_preset_hint_data,
gen3_coeff_8_preset_hint => gen3_coeff_8_preset_hint,
gen3_coeff_8_nxtber_more_ptr => gen3_coeff_8_nxtber_more_ptr,
gen3_coeff_8_nxtber_more => gen3_coeff_8_nxtber_more,
gen3_coeff_8_nxtber_less_ptr => gen3_coeff_8_nxtber_less_ptr,
gen3_coeff_8_nxtber_less => gen3_coeff_8_nxtber_less,
gen3_coeff_8_reqber_data => gen3_coeff_8_reqber_data,
gen3_coeff_8_reqber => gen3_coeff_8_reqber,
gen3_coeff_8_ber_meas_data => gen3_coeff_8_ber_meas_data,
gen3_coeff_8_ber_meas => gen3_coeff_8_ber_meas,
gen3_coeff_9_data => gen3_coeff_9_data,
gen3_coeff_9 => gen3_coeff_9,
gen3_coeff_9_sel => gen3_coeff_9_sel,
gen3_coeff_9_preset_hint_data => gen3_coeff_9_preset_hint_data,
gen3_coeff_9_preset_hint => gen3_coeff_9_preset_hint,
gen3_coeff_9_nxtber_more_ptr => gen3_coeff_9_nxtber_more_ptr,
gen3_coeff_9_nxtber_more => gen3_coeff_9_nxtber_more,
gen3_coeff_9_nxtber_less_ptr => gen3_coeff_9_nxtber_less_ptr,
gen3_coeff_9_nxtber_less => gen3_coeff_9_nxtber_less,
gen3_coeff_9_reqber_data => gen3_coeff_9_reqber_data,
gen3_coeff_9_reqber => gen3_coeff_9_reqber,
gen3_coeff_9_ber_meas_data => gen3_coeff_9_ber_meas_data,
gen3_coeff_9_ber_meas => gen3_coeff_9_ber_meas,
gen3_coeff_10_data => gen3_coeff_10_data,
gen3_coeff_10 => gen3_coeff_10,
gen3_coeff_10_sel => gen3_coeff_10_sel,
gen3_coeff_10_preset_hint_data => gen3_coeff_10_preset_hint_data,
gen3_coeff_10_preset_hint => gen3_coeff_10_preset_hint,
gen3_coeff_10_nxtber_more_ptr => gen3_coeff_10_nxtber_more_ptr,
gen3_coeff_10_nxtber_more => gen3_coeff_10_nxtber_more,
gen3_coeff_10_nxtber_less_ptr => gen3_coeff_10_nxtber_less_ptr,
gen3_coeff_10_nxtber_less => gen3_coeff_10_nxtber_less,
gen3_coeff_10_reqber_data => gen3_coeff_10_reqber_data,
gen3_coeff_10_reqber => gen3_coeff_10_reqber,
gen3_coeff_10_ber_meas_data => gen3_coeff_10_ber_meas_data,
gen3_coeff_10_ber_meas => gen3_coeff_10_ber_meas,
gen3_coeff_11_data => gen3_coeff_11_data,
gen3_coeff_11 => gen3_coeff_11,
gen3_coeff_11_sel => gen3_coeff_11_sel,
gen3_coeff_11_preset_hint_data => gen3_coeff_11_preset_hint_data,
gen3_coeff_11_preset_hint => gen3_coeff_11_preset_hint,
gen3_coeff_11_nxtber_more_ptr => gen3_coeff_11_nxtber_more_ptr,
gen3_coeff_11_nxtber_more => gen3_coeff_11_nxtber_more,
gen3_coeff_11_nxtber_less_ptr => gen3_coeff_11_nxtber_less_ptr,
gen3_coeff_11_nxtber_less => gen3_coeff_11_nxtber_less,
gen3_coeff_11_reqber_data => gen3_coeff_11_reqber_data,
gen3_coeff_11_reqber => gen3_coeff_11_reqber,
gen3_coeff_11_ber_meas_data => gen3_coeff_11_ber_meas_data,
gen3_coeff_11_ber_meas => gen3_coeff_11_ber_meas,
gen3_coeff_12_data => gen3_coeff_12_data,
gen3_coeff_12 => gen3_coeff_12,
gen3_coeff_12_sel => gen3_coeff_12_sel,
gen3_coeff_12_preset_hint_data => gen3_coeff_12_preset_hint_data,
gen3_coeff_12_preset_hint => gen3_coeff_12_preset_hint,
gen3_coeff_12_nxtber_more_ptr => gen3_coeff_12_nxtber_more_ptr,
gen3_coeff_12_nxtber_more => gen3_coeff_12_nxtber_more,
gen3_coeff_12_nxtber_less_ptr => gen3_coeff_12_nxtber_less_ptr,
gen3_coeff_12_nxtber_less => gen3_coeff_12_nxtber_less,
gen3_coeff_12_reqber_data => gen3_coeff_12_reqber_data,
gen3_coeff_12_reqber => gen3_coeff_12_reqber,
gen3_coeff_12_ber_meas_data => gen3_coeff_12_ber_meas_data,
gen3_coeff_12_ber_meas => gen3_coeff_12_ber_meas,
gen3_coeff_13_data => gen3_coeff_13_data,
gen3_coeff_13 => gen3_coeff_13,
gen3_coeff_13_sel => gen3_coeff_13_sel,
gen3_coeff_13_preset_hint_data => gen3_coeff_13_preset_hint_data,
gen3_coeff_13_preset_hint => gen3_coeff_13_preset_hint,
gen3_coeff_13_nxtber_more_ptr => gen3_coeff_13_nxtber_more_ptr,
gen3_coeff_13_nxtber_more => gen3_coeff_13_nxtber_more,
gen3_coeff_13_nxtber_less_ptr => gen3_coeff_13_nxtber_less_ptr,
gen3_coeff_13_nxtber_less => gen3_coeff_13_nxtber_less,
gen3_coeff_13_reqber_data => gen3_coeff_13_reqber_data,
gen3_coeff_13_reqber => gen3_coeff_13_reqber,
gen3_coeff_13_ber_meas_data => gen3_coeff_13_ber_meas_data,
gen3_coeff_13_ber_meas => gen3_coeff_13_ber_meas,
gen3_coeff_14_data => gen3_coeff_14_data,
gen3_coeff_14 => gen3_coeff_14,
gen3_coeff_14_sel => gen3_coeff_14_sel,
gen3_coeff_14_preset_hint_data => gen3_coeff_14_preset_hint_data,
gen3_coeff_14_preset_hint => gen3_coeff_14_preset_hint,
gen3_coeff_14_nxtber_more_ptr => gen3_coeff_14_nxtber_more_ptr,
gen3_coeff_14_nxtber_more => gen3_coeff_14_nxtber_more,
gen3_coeff_14_nxtber_less_ptr => gen3_coeff_14_nxtber_less_ptr,
gen3_coeff_14_nxtber_less => gen3_coeff_14_nxtber_less,
gen3_coeff_14_reqber_data => gen3_coeff_14_reqber_data,
gen3_coeff_14_reqber => gen3_coeff_14_reqber,
gen3_coeff_14_ber_meas_data => gen3_coeff_14_ber_meas_data,
gen3_coeff_14_ber_meas => gen3_coeff_14_ber_meas,
gen3_coeff_15_data => gen3_coeff_15_data,
gen3_coeff_15 => gen3_coeff_15,
gen3_coeff_15_sel => gen3_coeff_15_sel,
gen3_coeff_15_preset_hint_data => gen3_coeff_15_preset_hint_data,
gen3_coeff_15_preset_hint => gen3_coeff_15_preset_hint,
gen3_coeff_15_nxtber_more_ptr => gen3_coeff_15_nxtber_more_ptr,
gen3_coeff_15_nxtber_more => gen3_coeff_15_nxtber_more,
gen3_coeff_15_nxtber_less_ptr => gen3_coeff_15_nxtber_less_ptr,
gen3_coeff_15_nxtber_less => gen3_coeff_15_nxtber_less,
gen3_coeff_15_reqber_data => gen3_coeff_15_reqber_data,
gen3_coeff_15_reqber => gen3_coeff_15_reqber,
gen3_coeff_15_ber_meas_data => gen3_coeff_15_ber_meas_data,
gen3_coeff_15_ber_meas => gen3_coeff_15_ber_meas,
gen3_coeff_16_data => gen3_coeff_16_data,
gen3_coeff_16 => gen3_coeff_16,
gen3_coeff_16_sel => gen3_coeff_16_sel,
gen3_coeff_16_preset_hint_data => gen3_coeff_16_preset_hint_data,
gen3_coeff_16_preset_hint => gen3_coeff_16_preset_hint,
gen3_coeff_16_nxtber_more_ptr => gen3_coeff_16_nxtber_more_ptr,
gen3_coeff_16_nxtber_more => gen3_coeff_16_nxtber_more,
gen3_coeff_16_nxtber_less_ptr => gen3_coeff_16_nxtber_less_ptr,
gen3_coeff_16_nxtber_less => gen3_coeff_16_nxtber_less,
gen3_coeff_16_reqber_data => gen3_coeff_16_reqber_data,
gen3_coeff_16_reqber => gen3_coeff_16_reqber,
gen3_coeff_16_ber_meas_data => gen3_coeff_16_ber_meas_data,
gen3_coeff_16_ber_meas => gen3_coeff_16_ber_meas,
gen3_preset_coeff_1_data => gen3_preset_coeff_1_data,
gen3_preset_coeff_1 => gen3_preset_coeff_1,
gen3_preset_coeff_2_data => gen3_preset_coeff_2_data,
gen3_preset_coeff_2 => gen3_preset_coeff_2,
gen3_preset_coeff_3_data => gen3_preset_coeff_3_data,
gen3_preset_coeff_3 => gen3_preset_coeff_3,
gen3_preset_coeff_4_data => gen3_preset_coeff_4_data,
gen3_preset_coeff_4 => gen3_preset_coeff_4,
gen3_preset_coeff_5_data => gen3_preset_coeff_5_data,
gen3_preset_coeff_5 => gen3_preset_coeff_5,
gen3_preset_coeff_6_data => gen3_preset_coeff_6_data,
gen3_preset_coeff_6 => gen3_preset_coeff_6,
gen3_preset_coeff_7_data => gen3_preset_coeff_7_data,
gen3_preset_coeff_7 => gen3_preset_coeff_7,
gen3_preset_coeff_8_data => gen3_preset_coeff_8_data,
gen3_preset_coeff_8 => gen3_preset_coeff_8,
gen3_preset_coeff_9_data => gen3_preset_coeff_9_data,
gen3_preset_coeff_9 => gen3_preset_coeff_9,
gen3_preset_coeff_10_data => gen3_preset_coeff_10_data,
gen3_preset_coeff_10 => gen3_preset_coeff_10,
gen3_rxfreqlock_counter_data => gen3_rxfreqlock_counter_data,
gen3_rxfreqlock_counter => gen3_rxfreqlock_counter,
rstctrl_pld_clr => rstctrl_pld_clr ,
rstctrl_debug_en => rstctrl_debug_en ,
rstctrl_force_inactive_rst => rstctrl_force_inactive_rst ,
rstctrl_perst_enable => rstctrl_perst_enable ,
hrdrstctrl_en => hrdrstctrl_en ,
rstctrl_hip_ep => rstctrl_hip_ep ,
rstctrl_hard_block_enable => rstctrl_hard_block_enable ,
rstctrl_rx_pma_rstb_inv => rstctrl_rx_pma_rstb_inv ,
rstctrl_tx_pma_rstb_inv => rstctrl_tx_pma_rstb_inv ,
rstctrl_rx_pcs_rst_n_inv => rstctrl_rx_pcs_rst_n_inv ,
rstctrl_tx_pcs_rst_n_inv => rstctrl_tx_pcs_rst_n_inv ,
rstctrl_altpe3_crst_n_inv => rstctrl_altpe3_crst_n_inv ,
rstctrl_altpe3_srst_n_inv => rstctrl_altpe3_srst_n_inv ,
rstctrl_altpe3_rst_n_inv => rstctrl_altpe3_rst_n_inv ,
rstctrl_tx_pma_syncp_inv => rstctrl_tx_pma_syncp_inv ,
rstctrl_1us_count_fref_clk => rstctrl_1us_count_fref_clk ,
rstctrl_1us_count_fref_clk_value => rstctrl_1us_count_fref_clk_value ,
rstctrl_1ms_count_fref_clk => rstctrl_1ms_count_fref_clk ,
rstctrl_1ms_count_fref_clk_value => rstctrl_1ms_count_fref_clk_value ,
rstctrl_off_cal_done_select => rstctrl_off_cal_done_select ,
rstctrl_rx_pma_rstb_cmu_select => rstctrl_rx_pma_rstb_cmu_select ,
rstctrl_rx_pll_freq_lock_select => rstctrl_rx_pll_freq_lock_select ,
rstctrl_mask_tx_pll_lock_select => rstctrl_mask_tx_pll_lock_select ,
rstctrl_rx_pll_lock_select => rstctrl_rx_pll_lock_select ,
rstctrl_perstn_select => rstctrl_perstn_select ,
rstctrl_tx_lc_pll_rstb_select => rstctrl_tx_lc_pll_rstb_select ,
rstctrl_fref_clk_select => rstctrl_fref_clk_select ,
rstctrl_off_cal_en_select => rstctrl_off_cal_en_select ,
rstctrl_tx_pma_syncp_select => rstctrl_tx_pma_syncp_select ,
rstctrl_rx_pcs_rst_n_select => rstctrl_rx_pcs_rst_n_select ,
rstctrl_tx_cmu_pll_lock_select => rstctrl_tx_cmu_pll_lock_select ,
rstctrl_tx_pcs_rst_n_select => rstctrl_tx_pcs_rst_n_select ,
rstctrl_tx_lc_pll_lock_select => rstctrl_tx_lc_pll_lock_select ,
rstctrl_timer_a => rstctrl_timer_a ,
rstctrl_timer_a_type => rstctrl_timer_a_type ,
rstctrl_timer_a_value => rstctrl_timer_a_value ,
rstctrl_timer_b => rstctrl_timer_b ,
rstctrl_timer_b_type => rstctrl_timer_b_type ,
rstctrl_timer_b_value => rstctrl_timer_b_value ,
rstctrl_timer_c => rstctrl_timer_c ,
rstctrl_timer_c_type => rstctrl_timer_c_type ,
rstctrl_timer_c_value => rstctrl_timer_c_value ,
rstctrl_timer_d => rstctrl_timer_d ,
rstctrl_timer_d_type => rstctrl_timer_d_type ,
rstctrl_timer_d_value => rstctrl_timer_d_value ,
rstctrl_timer_e => rstctrl_timer_e ,
rstctrl_timer_e_type => rstctrl_timer_e_type ,
rstctrl_timer_e_value => rstctrl_timer_e_value ,
rstctrl_timer_f => rstctrl_timer_f ,
rstctrl_timer_f_type => rstctrl_timer_f_type ,
rstctrl_timer_f_value => rstctrl_timer_f_value ,
rstctrl_timer_g => rstctrl_timer_g ,
rstctrl_timer_g_type => rstctrl_timer_g_type ,
rstctrl_timer_g_value => rstctrl_timer_g_value ,
rstctrl_timer_h => rstctrl_timer_h ,
rstctrl_timer_h_type => rstctrl_timer_h_type ,
rstctrl_timer_h_value => rstctrl_timer_h_value ,
rstctrl_timer_i => rstctrl_timer_i ,
rstctrl_timer_i_type => rstctrl_timer_i_type ,
rstctrl_timer_i_value => rstctrl_timer_i_value ,
rstctrl_timer_j => rstctrl_timer_j ,
rstctrl_timer_j_type => rstctrl_timer_j_type ,
rstctrl_timer_j_value => rstctrl_timer_j_value
)
port map (
dpriostatus => dpriostatus,
lmidout => lmidout,
lmiack => lmiack,
lmirden => lmirden,
lmiwren => lmiwren,
lmiaddr => lmiaddr,
lmidin => lmidin,
flrreset => flrreset,
flrsts => flrsts,
resetstatus => resetstatus,
l2exit => l2exit,
hotrstexit => hotrstexit,
hiphardreset => hiphardreset,
dlupexit => dlupexit,
coreclkout => coreclkout,
pldclk => pldclk,
pldsrst => pldsrst,
pldrst => pldrst,
pclkch0 => pclkch0,
pclkch1 => pclkch1,
pclkcentral => pclkcentral,
pllfixedclkch0 => pllfixedclkch0,
pllfixedclkch1 => pllfixedclkch1,
pllfixedclkcentral => pllfixedclkcentral,
phyrst => phyrst,
physrst => physrst,
coreclkin => coreclkin,
corerst => corerst,
corepor => corepor,
corecrst => corecrst,
coresrst => coresrst,
swdnout => swdnout,
swupout => swupout,
swdnin => swdnin,
swupin => swupin,
swctmod => swctmod,
rxstdata => rxstdata,
rxstparity => rxstparity,
rxstbe => rxstbe,
rxsterr => rxsterr,
rxstsop => rxstsop,
rxsteop => rxsteop,
rxstempty => rxstempty,
rxstvalid => rxstvalid,
rxstbardec1 => rxstbardec1,
rxstbardec2 => rxstbardec2,
rxstmask => rxstmask,
rxstready => rxstready,
txstready => txstready,
txcredfchipcons => txcredfchipcons,
txcredfcinfinite => txcredfcinfinite,
txcredhdrfcp => txcredhdrfcp,
txcreddatafcp => txcreddatafcp,
txcredhdrfcnp => txcredhdrfcnp,
txcreddatafcnp => txcreddatafcnp,
txcredhdrfccp => txcredhdrfccp,
txcreddatafccp => txcreddatafccp,
txstdata => txstdata,
txstparity => txstparity,
txsterr => txsterr,
txstsop => txstsop,
txsteop => txsteop,
txstempty => txstempty,
txstvalid => txstvalid,
r2cuncecc => r2cuncecc,
rxcorrecc => rxcorrecc,
retryuncecc => retryuncecc,
retrycorrecc => retrycorrecc,
rxparerr => rxparerr,
txparerr => txparerr,
r2cparerr => r2cparerr,
pmetosr => pmetosr,
pmetocr => pmetocr,
pmevent => pmevent,
pmdata => pmdata,
pmauxpwr => pmauxpwr,
tlcfgsts => tlcfgsts,
tlcfgctl => tlcfgctl,
tlcfgadd => tlcfgadd,
appintaack => appintaack,
appintasts => appintasts,
intstatus => intstatus,
appmsiack => appmsiack,
appmsireq => appmsireq,
appmsitc => appmsitc,
appmsinum => appmsinum,
aermsinum => aermsinum,
pexmsinum => pexmsinum,
hpgctrler => hpgctrler,
cfglink2csrpld => cfglink2csrpld,
cfgprmbuspld => cfgprmbuspld,
csebisshadow => csebisshadow,
csebwrdata => csebwrdata,
csebwrdataparity => csebwrdataparity,
csebbe => csebbe,
csebaddr => csebaddr,
csebaddrparity => csebaddrparity,
csebwren => csebwren,
csebrden => csebrden,
csebwrrespreq => csebwrrespreq,
csebrddata => csebrddata,
csebrddataparity => csebrddataparity,
csebwaitrequest => csebwaitrequest,
csebwrrespvalid => csebwrrespvalid,
csebwrresponse => csebwrresponse,
csebrdresponse => csebrdresponse,
dlup => dlup,
testouthip => testouthip,
testout1hip => testout1hip,
ev1us => ev1us,
ev128ns => ev128ns,
wakeoen => wakeoen,
serrout => serrout,
ltssmstate => ltssmstate,
laneact => laneact,
currentspeed => currentspeed,
slotclkcfg => slotclkcfg,
mode => mode,
testinhip => testinhip,
testin1hip => testin1hip,
cplpending => cplpending,
cplerr => cplerr,
appinterr => appinterr,
egressblkerr => egressblkerr,
pmexitd0ack => pmexitd0ack,
pmexitd0req => pmexitd0req,
currentcoeff0 => currentcoeff0,
currentcoeff1 => currentcoeff1,
currentcoeff2 => currentcoeff2,
currentcoeff3 => currentcoeff3,
currentcoeff4 => currentcoeff4,
currentcoeff5 => currentcoeff5,
currentcoeff6 => currentcoeff6,
currentcoeff7 => currentcoeff7,
currentrxpreset0 => currentrxpreset0,
currentrxpreset1 => currentrxpreset1,
currentrxpreset2 => currentrxpreset2,
currentrxpreset3 => currentrxpreset3,
currentrxpreset4 => currentrxpreset4,
currentrxpreset5 => currentrxpreset5,
currentrxpreset6 => currentrxpreset6,
currentrxpreset7 => currentrxpreset7,
rate0 => rate0,
rate1 => rate1,
rate2 => rate2,
rate3 => rate3,
rate4 => rate4,
rate5 => rate5,
rate6 => rate6,
rate7 => rate7,
ratectrl => ratectrl,
ratetiedtognd => ratetiedtognd,
eidleinfersel0 => eidleinfersel0,
eidleinfersel1 => eidleinfersel1,
eidleinfersel2 => eidleinfersel2,
eidleinfersel3 => eidleinfersel3,
eidleinfersel4 => eidleinfersel4,
eidleinfersel5 => eidleinfersel5,
eidleinfersel6 => eidleinfersel6,
eidleinfersel7 => eidleinfersel7,
txdata0 => txdata0,
txdatak0 => txdatak0,
txdetectrx0 => txdetectrx0,
txelecidle0 => txelecidle0,
txcompl0 => txcompl0,
rxpolarity0 => rxpolarity0,
powerdown0 => powerdown0,
txdataskip0 => txdataskip0,
txblkst0 => txblkst0,
txsynchd0 => txsynchd0,
txdeemph0 => txdeemph0,
txmargin0 => txmargin0,
rxdata0 => rxdata0,
rxdatak0 => rxdatak0,
rxvalid0 => rxvalid0,
phystatus0 => phystatus0,
rxelecidle0 => rxelecidle0,
rxstatus0 => rxstatus0,
rxdataskip0 => rxdataskip0,
rxblkst0 => rxblkst0,
rxsynchd0 => rxsynchd0,
rxfreqlocked0 => rxfreqlocked0,
txdata1 => txdata1,
txdatak1 => txdatak1,
txdetectrx1 => txdetectrx1,
txelecidle1 => txelecidle1,
txcompl1 => txcompl1,
rxpolarity1 => rxpolarity1,
powerdown1 => powerdown1,
txdataskip1 => txdataskip1,
txblkst1 => txblkst1,
txsynchd1 => txsynchd1,
txdeemph1 => txdeemph1,
txmargin1 => txmargin1,
rxdata1 => rxdata1,
rxdatak1 => rxdatak1,
rxvalid1 => rxvalid1,
phystatus1 => phystatus1,
rxelecidle1 => rxelecidle1,
rxstatus1 => rxstatus1,
rxdataskip1 => rxdataskip1,
rxblkst1 => rxblkst1,
rxsynchd1 => rxsynchd1,
rxfreqlocked1 => rxfreqlocked1,
txdata2 => txdata2,
txdatak2 => txdatak2,
txdetectrx2 => txdetectrx2,
txelecidle2 => txelecidle2,
txcompl2 => txcompl2,
rxpolarity2 => rxpolarity2,
powerdown2 => powerdown2,
txdataskip2 => txdataskip2,
txblkst2 => txblkst2,
txsynchd2 => txsynchd2,
txdeemph2 => txdeemph2,
txmargin2 => txmargin2,
rxdata2 => rxdata2,
rxdatak2 => rxdatak2,
rxvalid2 => rxvalid2,
phystatus2 => phystatus2,
rxelecidle2 => rxelecidle2,
rxstatus2 => rxstatus2,
rxdataskip2 => rxdataskip2,
rxblkst2 => rxblkst2,
rxsynchd2 => rxsynchd2,
rxfreqlocked2 => rxfreqlocked2,
txdata3 => txdata3,
txdatak3 => txdatak3,
txdetectrx3 => txdetectrx3,
txelecidle3 => txelecidle3,
txcompl3 => txcompl3,
rxpolarity3 => rxpolarity3,
powerdown3 => powerdown3,
txdataskip3 => txdataskip3,
txblkst3 => txblkst3,
txsynchd3 => txsynchd3,
txdeemph3 => txdeemph3,
txmargin3 => txmargin3,
rxdata3 => rxdata3,
rxdatak3 => rxdatak3,
rxvalid3 => rxvalid3,
phystatus3 => phystatus3,
rxelecidle3 => rxelecidle3,
rxstatus3 => rxstatus3,
rxdataskip3 => rxdataskip3,
rxblkst3 => rxblkst3,
rxsynchd3 => rxsynchd3,
rxfreqlocked3 => rxfreqlocked3,
txdata4 => txdata4,
txdatak4 => txdatak4,
txdetectrx4 => txdetectrx4,
txelecidle4 => txelecidle4,
txcompl4 => txcompl4,
rxpolarity4 => rxpolarity4,
powerdown4 => powerdown4,
txdataskip4 => txdataskip4,
txblkst4 => txblkst4,
txsynchd4 => txsynchd4,
txdeemph4 => txdeemph4,
txmargin4 => txmargin4,
rxdata4 => rxdata4,
rxdatak4 => rxdatak4,
rxvalid4 => rxvalid4,
phystatus4 => phystatus4,
rxelecidle4 => rxelecidle4,
rxstatus4 => rxstatus4,
rxdataskip4 => rxdataskip4,
rxblkst4 => rxblkst4,
rxsynchd4 => rxsynchd4,
rxfreqlocked4 => rxfreqlocked4,
txdata5 => txdata5,
txdatak5 => txdatak5,
txdetectrx5 => txdetectrx5,
txelecidle5 => txelecidle5,
txcompl5 => txcompl5,
rxpolarity5 => rxpolarity5,
powerdown5 => powerdown5,
txdataskip5 => txdataskip5,
txblkst5 => txblkst5,
txsynchd5 => txsynchd5,
txdeemph5 => txdeemph5,
txmargin5 => txmargin5,
rxdata5 => rxdata5,
rxdatak5 => rxdatak5,
rxvalid5 => rxvalid5,
phystatus5 => phystatus5,
rxelecidle5 => rxelecidle5,
rxstatus5 => rxstatus5,
rxdataskip5 => rxdataskip5,
rxblkst5 => rxblkst5,
rxsynchd5 => rxsynchd5,
rxfreqlocked5 => rxfreqlocked5,
txdata6 => txdata6,
txdatak6 => txdatak6,
txdetectrx6 => txdetectrx6,
txelecidle6 => txelecidle6,
txcompl6 => txcompl6,
rxpolarity6 => rxpolarity6,
powerdown6 => powerdown6,
txdataskip6 => txdataskip6,
txblkst6 => txblkst6,
txsynchd6 => txsynchd6,
txdeemph6 => txdeemph6,
txmargin6 => txmargin6,
rxdata6 => rxdata6,
rxdatak6 => rxdatak6,
rxvalid6 => rxvalid6,
phystatus6 => phystatus6,
rxelecidle6 => rxelecidle6,
rxstatus6 => rxstatus6,
rxdataskip6 => rxdataskip6,
rxblkst6 => rxblkst6,
rxsynchd6 => rxsynchd6,
rxfreqlocked6 => rxfreqlocked6,
txdata7 => txdata7,
txdatak7 => txdatak7,
txdetectrx7 => txdetectrx7,
txelecidle7 => txelecidle7,
txcompl7 => txcompl7,
rxpolarity7 => rxpolarity7,
powerdown7 => powerdown7,
txdataskip7 => txdataskip7,
txblkst7 => txblkst7,
txsynchd7 => txsynchd7,
txdeemph7 => txdeemph7,
txmargin7 => txmargin7,
rxdata7 => rxdata7,
rxdatak7 => rxdatak7,
rxvalid7 => rxvalid7,
phystatus7 => phystatus7,
rxelecidle7 => rxelecidle7,
rxstatus7 => rxstatus7,
rxdataskip7 => rxdataskip7,
rxblkst7 => rxblkst7,
rxsynchd7 => rxsynchd7,
rxfreqlocked7 => rxfreqlocked7,
dbgpipex1rx => dbgpipex1rx,
memredsclk => memredsclk,
memredenscan => memredenscan,
memredscen => memredscen,
memredscin => memredscin,
memredscsel => memredscsel,
memredscrst => memredscrst,
memredscout => memredscout,
memregscanen => memregscanen,
memregscanin => memregscanin,
memhiptestenable => memhiptestenable,
memregscanout => memregscanout,
bisttesten => bisttesten,
bistenrpl => bistenrpl,
bistscanin => bistscanin,
bistscanen => bistscanen,
bistenrcv => bistenrcv,
bistscanoutrpl => bistscanoutrpl,
bistdonearpl => bistdonearpl,
bistdonebrpl => bistdonebrpl,
bistpassrpl => bistpassrpl,
derrrpl => derrrpl,
derrcorextrpl => derrcorextrpl,
bistscanoutrcv => bistscanoutrcv,
bistdonearcv => bistdonearcv,
bistdonebrcv => bistdonebrcv,
bistpassrcv => bistpassrcv,
derrcorextrcv => derrcorextrcv,
bistscanoutrcv1 => bistscanoutrcv1,
bistdonearcv1 => bistdonearcv1,
bistdonebrcv1 => bistdonebrcv1,
bistpassrcv1 => bistpassrcv1,
derrcorextrcv1 => derrcorextrcv1,
scanmoden => scanmoden,
scanshiftn => scanshiftn,
nfrzdrv => nfrzdrv,
frzreg => frzreg,
frzlogic => frzlogic,
idrpl => idrpl,
idrcv => idrcv,
plniotri => plniotri,
entest => entest,
npor => npor,
usermode => usermode,
cvpclk => cvpclk,
cvpdata => cvpdata,
cvpstartxfer => cvpstartxfer,
cvpconfig => cvpconfig,
cvpfullconfig => cvpfullconfig,
cvpconfigready => cvpconfigready,
cvpen => cvpen,
cvpconfigerror => cvpconfigerror,
cvpconfigdone => cvpconfigdone,
pinperstn => pinperstn,
pldperstn => pldperstn,
iocsrrdydly => iocsrrdydly,
softaltpe3rstn => softaltpe3rstn,
softaltpe3srstn => softaltpe3srstn,
softaltpe3crstn => softaltpe3crstn,
pldclrpmapcshipn => pldclrpmapcshipn,
pldclrpcshipn => pldclrpcshipn,
pldclrhipn => pldclrhipn,
s0ch0emsiptieoff => s0ch0emsiptieoff,
s0ch1emsiptieoff => s0ch1emsiptieoff,
s0ch2emsiptieoff => s0ch2emsiptieoff,
s1ch0emsiptieoff => s1ch0emsiptieoff,
s1ch1emsiptieoff => s1ch1emsiptieoff,
s1ch2emsiptieoff => s1ch2emsiptieoff,
s2ch0emsiptieoff => s2ch0emsiptieoff,
s2ch1emsiptieoff => s2ch1emsiptieoff,
s2ch2emsiptieoff => s2ch2emsiptieoff,
s3ch0emsiptieoff => s3ch0emsiptieoff,
s3ch1emsiptieoff => s3ch1emsiptieoff,
s3ch2emsiptieoff => s3ch2emsiptieoff,
emsiptieofftop => emsiptieofftop,
emsiptieoffbot => emsiptieoffbot,
txpcsrstn0 => txpcsrstn0 ,
rxpcsrstn0 => rxpcsrstn0 ,
g3txpcsrstn0 => g3txpcsrstn0 ,
g3rxpcsrstn0 => g3rxpcsrstn0 ,
txpmasyncp0 => txpmasyncp0 ,
rxpmarstb0 => rxpmarstb0 ,
txlcpllrstb0 => txlcpllrstb0 ,
offcalen0 => offcalen0 ,
frefclk0 => frefclk0 ,
offcaldone0 => offcaldone0 ,
txlcplllock0 => txlcplllock0 ,
rxfreqtxcmuplllock0 => rxfreqtxcmuplllock0 ,
rxpllphaselock0 => rxpllphaselock0 ,
masktxplllock0 => masktxplllock0 ,
txpcsrstn1 => txpcsrstn1 ,
rxpcsrstn1 => rxpcsrstn1 ,
g3txpcsrstn1 => g3txpcsrstn1 ,
g3rxpcsrstn1 => g3rxpcsrstn1 ,
txpmasyncp1 => txpmasyncp1 ,
rxpmarstb1 => rxpmarstb1 ,
txlcpllrstb1 => txlcpllrstb1 ,
offcalen1 => offcalen1 ,
frefclk1 => frefclk1 ,
offcaldone1 => offcaldone1 ,
txlcplllock1 => txlcplllock1 ,
rxfreqtxcmuplllock1 => rxfreqtxcmuplllock1 ,
rxpllphaselock1 => rxpllphaselock1 ,
masktxplllock1 => masktxplllock1 ,
txpcsrstn2 => txpcsrstn2 ,
rxpcsrstn2 => rxpcsrstn2 ,
g3txpcsrstn2 => g3txpcsrstn2 ,
g3rxpcsrstn2 => g3rxpcsrstn2 ,
txpmasyncp2 => txpmasyncp2 ,
rxpmarstb2 => rxpmarstb2 ,
txlcpllrstb2 => txlcpllrstb2 ,
offcalen2 => offcalen2 ,
frefclk2 => frefclk2 ,
offcaldone2 => offcaldone2 ,
txlcplllock2 => txlcplllock2 ,
rxfreqtxcmuplllock2 => rxfreqtxcmuplllock2 ,
rxpllphaselock2 => rxpllphaselock2 ,
masktxplllock2 => masktxplllock2 ,
txpcsrstn3 => txpcsrstn3 ,
rxpcsrstn3 => rxpcsrstn3 ,
g3txpcsrstn3 => g3txpcsrstn3 ,
g3rxpcsrstn3 => g3rxpcsrstn3 ,
txpmasyncp3 => txpmasyncp3 ,
rxpmarstb3 => rxpmarstb3 ,
txlcpllrstb3 => txlcpllrstb3 ,
offcalen3 => offcalen3 ,
frefclk3 => frefclk3 ,
offcaldone3 => offcaldone3 ,
txlcplllock3 => txlcplllock3 ,
rxfreqtxcmuplllock3 => rxfreqtxcmuplllock3 ,
rxpllphaselock3 => rxpllphaselock3 ,
masktxplllock3 => masktxplllock3 ,
txpcsrstn4 => txpcsrstn4 ,
rxpcsrstn4 => rxpcsrstn4 ,
g3txpcsrstn4 => g3txpcsrstn4 ,
g3rxpcsrstn4 => g3rxpcsrstn4 ,
txpmasyncp4 => txpmasyncp4 ,
rxpmarstb4 => rxpmarstb4 ,
txlcpllrstb4 => txlcpllrstb4 ,
offcalen4 => offcalen4 ,
frefclk4 => frefclk4 ,
offcaldone4 => offcaldone4 ,
txlcplllock4 => txlcplllock4 ,
rxfreqtxcmuplllock4 => rxfreqtxcmuplllock4 ,
rxpllphaselock4 => rxpllphaselock4 ,
masktxplllock4 => masktxplllock4 ,
txpcsrstn5 => txpcsrstn5 ,
rxpcsrstn5 => rxpcsrstn5 ,
g3txpcsrstn5 => g3txpcsrstn5 ,
g3rxpcsrstn5 => g3rxpcsrstn5 ,
txpmasyncp5 => txpmasyncp5 ,
rxpmarstb5 => rxpmarstb5 ,
txlcpllrstb5 => txlcpllrstb5 ,
offcalen5 => offcalen5 ,
frefclk5 => frefclk5 ,
offcaldone5 => offcaldone5 ,
txlcplllock5 => txlcplllock5 ,
rxfreqtxcmuplllock5 => rxfreqtxcmuplllock5 ,
rxpllphaselock5 => rxpllphaselock5 ,
masktxplllock5 => masktxplllock5 ,
txpcsrstn6 => txpcsrstn6 ,
rxpcsrstn6 => rxpcsrstn6 ,
g3txpcsrstn6 => g3txpcsrstn6 ,
g3rxpcsrstn6 => g3rxpcsrstn6 ,
txpmasyncp6 => txpmasyncp6 ,
rxpmarstb6 => rxpmarstb6 ,
txlcpllrstb6 => txlcpllrstb6 ,
offcalen6 => offcalen6 ,
frefclk6 => frefclk6 ,
offcaldone6 => offcaldone6 ,
txlcplllock6 => txlcplllock6 ,
rxfreqtxcmuplllock6 => rxfreqtxcmuplllock6 ,
rxpllphaselock6 => rxpllphaselock6 ,
masktxplllock6 => masktxplllock6 ,
txpcsrstn7 => txpcsrstn7 ,
rxpcsrstn7 => rxpcsrstn7 ,
g3txpcsrstn7 => g3txpcsrstn7 ,
g3rxpcsrstn7 => g3rxpcsrstn7 ,
txpmasyncp7 => txpmasyncp7 ,
rxpmarstb7 => rxpmarstb7 ,
txlcpllrstb7 => txlcpllrstb7 ,
offcalen7 => offcalen7 ,
frefclk7 => frefclk7 ,
offcaldone7 => offcaldone7 ,
txlcplllock7 => txlcplllock7 ,
rxfreqtxcmuplllock7 => rxfreqtxcmuplllock7 ,
rxpllphaselock7 => rxpllphaselock7 ,
masktxplllock7 => masktxplllock7 ,
txpcsrstn8 => txpcsrstn8 ,
rxpcsrstn8 => rxpcsrstn8 ,
g3txpcsrstn8 => g3txpcsrstn8 ,
g3rxpcsrstn8 => g3rxpcsrstn8 ,
txpmasyncp8 => txpmasyncp8 ,
rxpmarstb8 => rxpmarstb8 ,
txlcpllrstb8 => txlcpllrstb8 ,
offcalen8 => offcalen8 ,
frefclk8 => frefclk8 ,
offcaldone8 => offcaldone8 ,
txlcplllock8 => txlcplllock8 ,
rxfreqtxcmuplllock8 => rxfreqtxcmuplllock8 ,
rxpllphaselock8 => rxpllphaselock8 ,
masktxplllock8 => masktxplllock8 ,
txpcsrstn9 => txpcsrstn9 ,
rxpcsrstn9 => rxpcsrstn9 ,
g3txpcsrstn9 => g3txpcsrstn9 ,
g3rxpcsrstn9 => g3rxpcsrstn9 ,
txpmasyncp9 => txpmasyncp9 ,
rxpmarstb9 => rxpmarstb9 ,
txlcpllrstb9 => txlcpllrstb9 ,
offcalen9 => offcalen9 ,
frefclk9 => frefclk9 ,
offcaldone9 => offcaldone9 ,
txlcplllock9 => txlcplllock9 ,
rxfreqtxcmuplllock9 => rxfreqtxcmuplllock9 ,
rxpllphaselock9 => rxpllphaselock9 ,
masktxplllock9 => masktxplllock9 ,
txpcsrstn10 => txpcsrstn10 ,
rxpcsrstn10 => rxpcsrstn10 ,
g3txpcsrstn10 => g3txpcsrstn10 ,
g3rxpcsrstn10 => g3rxpcsrstn10 ,
txpmasyncp10 => txpmasyncp10 ,
rxpmarstb10 => rxpmarstb10 ,
txlcpllrstb10 => txlcpllrstb10 ,
offcalen10 => offcalen10 ,
frefclk10 => frefclk10 ,
offcaldone10 => offcaldone10 ,
txlcplllock10 => txlcplllock10 ,
rxfreqtxcmuplllock10 => rxfreqtxcmuplllock10 ,
rxpllphaselock10 => rxpllphaselock10 ,
masktxplllock10 => masktxplllock10 ,
txpcsrstn11 => txpcsrstn11 ,
rxpcsrstn11 => rxpcsrstn11 ,
g3txpcsrstn11 => g3txpcsrstn11 ,
g3rxpcsrstn11 => g3rxpcsrstn11 ,
txpmasyncp11 => txpmasyncp11 ,
rxpmarstb11 => rxpmarstb11 ,
txlcpllrstb11 => txlcpllrstb11 ,
offcalen11 => offcalen11 ,
frefclk11 => frefclk11 ,
offcaldone11 => offcaldone11 ,
txlcplllock11 => txlcplllock11 ,
rxfreqtxcmuplllock11 => rxfreqtxcmuplllock11 ,
rxpllphaselock11 => rxpllphaselock11 ,
masktxplllock11 => masktxplllock11 ,
reservedin => reservedin,
reservedclkin => reservedclkin,
reservedout => reservedout,
reservedclkout => reservedclkout
);
end behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
configuration controller_with_timing of controller is
for structural
for state_reg : reg
use entity work.reg(gate_level)
generic map ( t_setup => 200 ps, t_hold => 150 ps, t_pd => 150 ps,
width => width );
end for;
-- . . .
end for;
end configuration controller_with_timing;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
configuration controller_with_timing of controller is
for structural
for state_reg : reg
use entity work.reg(gate_level)
generic map ( t_setup => 200 ps, t_hold => 150 ps, t_pd => 150 ps,
width => width );
end for;
-- . . .
end for;
end configuration controller_with_timing;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_13_fg_13_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
configuration controller_with_timing of controller is
for structural
for state_reg : reg
use entity work.reg(gate_level)
generic map ( t_setup => 200 ps, t_hold => 150 ps, t_pd => 150 ps,
width => width );
end for;
-- . . .
end for;
end configuration controller_with_timing;
|
library IEEE;
use IEEE.std_logic_1164.all;
-- Alunos: Adan Pereira Gomes e Wesley Mayk Gama Luz
entity regNbits is
generic (N: positive := 5);
port (
clock, reset, enable: in std_logic;
data: in std_logic_vector((N - 1) downto 0);
Q: out std_logic_vector((N - 1) downto 0)
);
end entity;
architecture circuito of regNbits is
begin
REG : process (clock, reset)
begin
if reset = '0' then
Q <= (others => '0');
elsif rising_edge(clock) then
if enable = '1' then
Q <= data;
end if;
end if;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ad_e
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:41:45 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../constant.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ad_e-e.vhd,v 1.3 2004/08/18 10:47:03 wig Exp $
-- $Date: 2004/08/18 10:47:03 $
-- $Log: inst_ad_e-e.vhd,v $
-- Revision 1.3 2004/08/18 10:47:03 wig
-- reworked some testcases
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ad_e
--
entity inst_ad_e is
-- Generics:
-- No Generated Generics for Entity inst_ad_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_ad_e
end inst_ad_e;
--
-- End of Generated Entity inst_ad_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY cpu_rst_M_AXI_GP1_ACLK_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END cpu_rst_M_AXI_GP1_ACLK_100M_0;
ARCHITECTURE cpu_rst_M_AXI_GP1_ACLK_100M_0_arch OF cpu_rst_M_AXI_GP1_ACLK_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_rst_M_AXI_GP1_ACLK_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END cpu_rst_M_AXI_GP1_ACLK_100M_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity foo is
end entity;
architecture fum of foo is
constant A: std_logic_vector (7 downto 0) := X"04";
function slv_image(inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end;
begin
SOME_LABEL:
process
begin
wait for 1 ns;
if A <= "00001011" then -- if A <= std_logic_vector'("00001011") then
report "A = " & slv_image(A) ;
end if;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity foo is
end entity;
architecture fum of foo is
constant A: std_logic_vector (7 downto 0) := X"04";
function slv_image(inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end;
begin
SOME_LABEL:
process
begin
wait for 1 ns;
if A <= "00001011" then -- if A <= std_logic_vector'("00001011") then
report "A = " & slv_image(A) ;
end if;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity foo is
end entity;
architecture fum of foo is
constant A: std_logic_vector (7 downto 0) := X"04";
function slv_image(inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end;
begin
SOME_LABEL:
process
begin
wait for 1 ns;
if A <= "00001011" then -- if A <= std_logic_vector'("00001011") then
report "A = " & slv_image(A) ;
end if;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.vga_lib.all;
entity VGA_sync_gen is
port
(
clk,rst : in std_logic;
Hcount,Vcount : out std_logic_vector(COUNT_WIDTH-1 downto 0);
Horiz_Sync,Vert_Sync,Video_on : out std_logic
);
end VGA_sync_gen;
architecture bhv of VGA_sync_gen is
signal Hcount_temp, Vcount_temp : unsigned(COUNT_WIDTH-1 downto 0);
begin
Hcount <= std_logic_vector(Hcount_temp);
Vcount <= std_logic_vector(Vcount_temp);
process(clk,rst)
begin
if(rst = '1') then
Hcount_temp <= (others => '0');
Vcount_temp <= (others => '0');
elsif(rising_edge(clk)) then
if(Hcount_temp = H_MAX) then
Hcount_temp <= (others => '0');
else
Hcount_temp <= Hcount_temp + 1;
end if;
if(Vcount_temp = V_MAX) then
Vcount_temp <= (others => '0');
elsif(Hcount_temp = H_VERT_INC) then
Vcount_temp <= Vcount_temp + 1;
end if;
end if;
end process;
process(Hcount_temp,Vcount_temp)
begin
if(Hcount_temp >= HSYNC_BEGIN and Hcount_temp <= HSYNC_END) then
Horiz_Sync <= '0'; --active low
else
Horiz_Sync <= '1';
end if;
if(Vcount_temp >= VSYNC_BEGIN and Vcount_temp <= VSYNC_END) then
Vert_Sync <= '0';
else
Vert_Sync <= '1';
end if;
if((Hcount_temp >= 0 and Hcount_temp <= H_DISPLAY_END) and (Vcount_temp >= 0 and Vcount_temp <= V_DISPLAY_END)) then
Video_on <= '1'; --this one is active high
else
Video_on <= '0';
end if;
end process;
end bhv; |
-------------------------------------------------------------------
-- System Generator version 11.1.00 VHDL source file.
--
-- Copyright(C) 2008 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2007 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity plbaddrpref is
generic (
C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF";
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_NATIVE_DWIDTH : integer range 32 to 32 := 32
);
port (
addrpref : out std_logic_vector(20-1 downto 0);
sl_rddbus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
plb_wrdbus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
sgsl_rddbus : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
sgplb_wrdbus : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
);
end plbaddrpref;
architecture behavior of plbaddrpref is
signal sl_rddbus_i : std_logic_vector(0 to C_SPLB_DWIDTH-1);
begin
addrpref <= C_BASEADDR(32-1 downto 12);
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb
-------------------------------------------------------------------------------
GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate
begin
-----------------------------------------------------------------------
-- Map lower rd data to each quarter of the plb slave read bus
-----------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(64 to 95) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(96 to 127) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_128_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb
-------------------------------------------------------------------------------
GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Map lower rd data to upper and lower halves of plb slave read bus
---------------------------------------------------------------------------
sl_rddbus_i(0 to 31) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
sl_rddbus_i(32 to 63) <= sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end generate GEN_64_TO_32_SLAVE;
-------------------------------------------------------------------------------
-- IPIF DWidth = PLB DWidth
-- If IPIF Slave Data width is equal to the PLB Bus Data Width
-- Then BE and Read Data Bus map directly to eachother.
-------------------------------------------------------------------------------
GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate
sl_rddbus_i <= sgsl_rddbus;
end generate GEN_FOR_EQUAL_SLAVE;
sl_rddbus <= sl_rddbus_i;
sgplb_wrdbus <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity sg_xsvi_fanout_plbw is
generic (
C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000";
C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF";
C_SPLB_AWIDTH: integer := 0;
C_SPLB_DWIDTH: integer := 0;
C_SPLB_MID_WIDTH: integer := 0;
C_SPLB_NATIVE_DWIDTH: integer := 0;
C_SPLB_NUM_MASTERS: integer := 0;
C_SPLB_SUPPORT_BURSTS: integer := 0
);
port (
active_video_i: in std_logic;
hblank_i: in std_logic;
hsync_i: in std_logic;
plb_abus: in std_logic_vector(0 to 31);
plb_pavalid: in std_logic;
plb_rnw: in std_logic;
plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1);
splb_clk: in std_logic;
splb_rst: in std_logic;
sysgen_clk: in std_logic;
vblank_i: in std_logic;
video_data_i: in std_logic_vector(0 to 23);
vsync_i: in std_logic;
active_video_o: out std_logic;
hblank_o: out std_logic;
hsync_o: out std_logic;
sl_addrack: out std_logic;
sl_rdcomp: out std_logic;
sl_rddack: out std_logic;
sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1);
sl_wait: out std_logic;
sl_wrcomp: out std_logic;
sl_wrdack: out std_logic;
vblank_o: out std_logic;
video_data_o: out std_logic_vector(0 to 23);
vsync_o: out std_logic
);
end sg_xsvi_fanout_plbw;
architecture structural of sg_xsvi_fanout_plbw is
signal active_video_i_x0: std_logic;
signal active_video_o_x0: std_logic;
signal clk: std_logic;
signal hblank_i_x0: std_logic;
signal hblank_o_x0: std_logic;
signal hsync_i_x0: std_logic;
signal hsync_o_x0: std_logic;
signal plb_abus_x0: std_logic_vector(31 downto 0);
signal plb_pavalid_x0: std_logic;
signal plb_rnw_x0: std_logic;
signal plbaddrpref_addrpref_net: std_logic_vector(19 downto 0);
signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0);
signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
signal sl_addrack_x0: std_logic;
signal sl_rdcomp_x0: std_logic;
signal sl_rddack_x0: std_logic;
signal sl_wait_x0: std_logic;
signal sl_wrcomp_x0: std_logic;
signal sl_wrdack_x0: std_logic;
signal splb_rst_x0: std_logic;
signal vblank_i_x0: std_logic;
signal vblank_o_x0: std_logic;
signal video_data_i_x0: std_logic_vector(23 downto 0);
signal video_data_o_x0: std_logic_vector(23 downto 0);
signal vsync_i_x0: std_logic;
signal vsync_o_x0: std_logic;
signal xps_clk: std_logic;
begin
active_video_i_x0 <= active_video_i;
hblank_i_x0 <= hblank_i;
hsync_i_x0 <= hsync_i;
plb_abus_x0 <= plb_abus;
plb_pavalid_x0 <= plb_pavalid;
plb_rnw_x0 <= plb_rnw;
plbaddrpref_plb_wrdbus_net <= plb_wrdbus;
xps_clk <= splb_clk;
splb_rst_x0 <= splb_rst;
clk <= sysgen_clk;
vblank_i_x0 <= vblank_i;
video_data_i_x0 <= video_data_i;
vsync_i_x0 <= vsync_i;
active_video_o <= active_video_o_x0;
hblank_o <= hblank_o_x0;
hsync_o <= hsync_o_x0;
sl_addrack <= sl_addrack_x0;
sl_rdcomp <= sl_rdcomp_x0;
sl_rddack <= sl_rddack_x0;
sl_rddbus <= plbaddrpref_sl_rddbus_net;
sl_wait <= sl_wait_x0;
sl_wrcomp <= sl_wrcomp_x0;
sl_wrdack <= sl_wrdack_x0;
vblank_o <= vblank_o_x0;
video_data_o <= video_data_o_x0;
vsync_o <= vsync_o_x0;
plbaddrpref_x0: entity work.plbaddrpref
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
)
port map (
plb_wrdbus => plbaddrpref_plb_wrdbus_net,
sgsl_rddbus => plbaddrpref_sgsl_rddbus_net,
addrpref => plbaddrpref_addrpref_net,
sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sl_rddbus => plbaddrpref_sl_rddbus_net
);
sysgen_dut: entity work.sg_xsvi_fanout_cw
port map (
active_video_i => active_video_i_x0,
clk => clk,
hblank_i => hblank_i_x0,
hsync_i => hsync_i_x0,
plb_abus => plb_abus_x0,
plb_pavalid => plb_pavalid_x0,
plb_rnw => plb_rnw_x0,
plb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
sg_plb_addrpref => plbaddrpref_addrpref_net,
splb_rst => splb_rst_x0,
vblank_i => vblank_i_x0,
video_data_i => video_data_i_x0,
vsync_i => vsync_i_x0,
xps_clk => xps_clk,
active_video_o => active_video_o_x0,
hblank_o => hblank_o_x0,
hsync_o => hsync_o_x0,
sl_addrack => sl_addrack_x0,
sl_rdcomp => sl_rdcomp_x0,
sl_rddack => sl_rddack_x0,
sl_rddbus => plbaddrpref_sgsl_rddbus_net,
sl_wait => sl_wait_x0,
sl_wrcomp => sl_wrcomp_x0,
sl_wrdack => sl_wrdack_x0,
vblank_o => vblank_o_x0,
video_data_o => video_data_o_x0,
vsync_o => vsync_o_x0
);
end structural;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Parameter memory
-------------------------------------------------------------------------------
-- File : floppy.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity floppy_param_mem is
port (
clock : in std_logic;
reset : in std_logic;
cpu_write : in std_logic;
cpu_ram_en : in std_logic;
cpu_addr : in std_logic_vector(10 downto 0);
cpu_wdata : in std_logic_vector(7 downto 0);
cpu_rdata : out std_logic_vector(7 downto 0);
track : in std_logic_vector(6 downto 0);
bit_time : out unsigned(8 downto 0);
track_start : out std_logic_vector(25 downto 0);
max_offset : out std_logic_vector(13 downto 0) );
end floppy_param_mem;
architecture gideon of floppy_param_mem is
signal toggle : std_logic;
signal param_addr : std_logic_vector(8 downto 0);
signal param_data : std_logic_vector(31 downto 0);
begin
ram: RAMB16_S9_S36
port map (
CLKA => clock,
SSRA => reset,
ENA => cpu_ram_en,
WEA => cpu_write,
ADDRA => cpu_addr,
DIA => cpu_wdata,
DIPA => "0",
DOA => cpu_rdata,
DOPA => open,
CLKB => clock,
SSRB => reset,
ENB => '1',
WEB => '0',
ADDRB => param_addr,
DIB => X"00000000",
DIPB => X"0",
DOB(31 downto 24) => param_data(7 downto 0), -- CPU writes big endian, bram is little endian
DOB(23 downto 16) => param_data(15 downto 8),
DOB(15 downto 8) => param_data(23 downto 16),
DOB(7 downto 0) => param_data(31 downto 24),
DOPB => open );
param_addr <= '0' & track & toggle;
process(clock)
begin
if rising_edge(clock) then
if toggle='1' then -- even addresses (one clock later)
track_start <= param_data(track_start'range);
else
max_offset <= param_data(max_offset'range);
bit_time <= unsigned(param_data(bit_time'high+16 downto 16));
end if;
if reset='1' then
toggle <= '0';
else
toggle <= not toggle;
end if;
end if;
end process;
end gideon;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.07.2017 16:36:50
-- Design Name:
-- Module Name: fsm_dds_wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fsm_dds_wrapper is
Port ( clock : in STD_LOGIC;
reset_n : in STD_LOGIC;
valid_in : in STD_LOGIC;
count_hit : in STD_LOGIC;
valid_in_out : out STD_LOGIC;
reset_n_all : out STD_LOGIC;
done : out STD_LOGIC);
end fsm_dds_wrapper;
architecture Behavioral of fsm_dds_wrapper is
type state is (idle, reset_dds, waiting_for_count_hit, op_done);
signal current_state, next_state : state := idle;
begin
registro_stato : process(clock, reset_n, next_state)
begin
if(reset_n = '0') then
current_state <= idle;
elsif(rising_edge(clock)) then
current_state <= next_state;
end if;
end process;
fsm_next_state : process(current_state, reset_n, valid_in, count_hit)
begin
case current_state is
when idle =>
if(valid_in = '1') then
next_state <= reset_dds;
else
next_state <= idle;
end if;
when reset_dds =>
next_state <= waiting_for_count_hit;
when waiting_for_count_hit =>
if(count_hit = '1') then
next_state <= op_done;
else
next_state <= waiting_for_count_hit;
end if;
when op_done =>
if(valid_in = '1') then
next_state <= reset_dds;
else
next_state <= op_done;
end if;
end case;
end process;
fsm_output : process(current_state)
begin
valid_in_out <= '0';
reset_n_all <= '1';
done <= '0';
case current_state is
when idle =>
reset_n_all <= '0';
when reset_dds =>
valid_in_out <= '1';
reset_n_all <= '0';
when waiting_for_count_hit =>
when op_done =>
reset_n_all <= '0';
done <= '1';
end case;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
-- based on work by Alan Daly. Copyright(c) 2009. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomFpga_Core
-- /___/ /\ Timestamp : 02/03/2013 06:17:50
-- \ \ / \
-- \___\/\___\
--
--Design Name: Atomic_top.vhf
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity AtomFpga_Core is
generic (
CImplCpu65c02 : boolean := false;
CImplDebugger : boolean := false;
CImplSDDOS : boolean;
CImplAtoMMC2 : boolean;
CImplGraphicsExt : boolean;
CImplSoftChar : boolean;
CImplSID : boolean;
CImplVGA80x40 : boolean;
CImplHWScrolling : boolean;
CImplMouse : boolean;
CImplUart : boolean;
CImplDoubleVideo : boolean;
CImplRamRomNone : boolean;
CImplRamRomPhill : boolean;
CImplRamRomAtom2015 : boolean;
CImplRamRomSchakelKaart : boolean;
CImplVIA : boolean := true;
CImplProfilingCounters : boolean := false;
MainClockSpeed : integer;
DefaultBaud : integer
);
port (
-- Clocking
clk_vga : in std_logic; -- nominally 25.175MHz VGA clock
clk_main : in std_logic; -- clock for the main system
clk_avr : in std_logic; -- clock for the AtoMMC AVR
clk_avr_debug : in std_logic; -- clock for the Debugger AVR
clk_dac : in std_logic; -- fast clock for the 1-bit DAC
clk_32M00 : in std_logic; -- fixed clock, used for SID and casette
-- Keyboard/mouse
kbd_pa : out std_logic_vector(3 downto 0);
kbd_pb : in std_logic_vector(7 downto 0) := (others => '1');
kbd_pc : in std_logic_vector(6 downto 6) := (others => '1');
ps2_clk : in std_logic;
ps2_data : in std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
-- Resets
powerup_reset_n : in std_logic := '1'; -- power up reset only (optional)
ext_reset_n : in std_logic := '1'; -- external bus reset (optional)
int_reset_n : out std_logic; -- internal bus reset (e.g. PS/2 break)
-- Video
red : out std_logic_vector (2 downto 0);
green : out std_logic_vector (2 downto 0);
blue : out std_logic_vector (2 downto 0);
vsync : out std_logic;
hsync : out std_logic;
blank : out std_logic;
-- External 6502 bus interface
phi2 : out std_logic;
sync : out std_logic;
rnw : out std_logic;
addr : out std_logic_vector(15 downto 0);
rdy : in std_logic := '1';
so : in std_logic := '1';
irq_n : in std_logic := '1';
nmi_n : in std_logic := '1';
-- External Bus/Ram/Rom interface
ExternBus : out std_logic;
ExternCE : out std_logic;
ExternWE : out std_logic;
ExternA : out std_logic_vector (18 downto 0);
ExternDin : out std_logic_vector (7 downto 0);
ExternDout : in std_logic_vector (7 downto 0);
-- Audio
sid_audio_d : out std_logic_vector (17 downto 0);
sid_audio : out std_logic;
atom_audio : out std_logic;
-- SD Card
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
-- Serial
uart_RxD : in std_logic;
uart_TxD : out std_logic;
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Cassette
cas_in : in std_logic := '0';
cas_out : out std_logic;
-- Misc
LED1 : out std_logic;
LED2 : out std_logic;
charSet : in std_logic;
Joystick1 : in std_logic_vector (7 downto 0) := (others => '1');
Joystick2 : in std_logic_vector (7 downto 0) := (others => '1')
);
end AtomFpga_Core;
architecture BEHAVIORAL of AtomFpga_Core is
function InitBFFE_Atom2015 return std_logic_vector is
begin
if CImplAtoMMC2 then
-- Use OS ROM Bank 0 (contains AVR AtoMMC)
return x"00";
else
-- Use OS ROM Bank 1 (contains PIC AtoMMC)
return x"08";
end if;
end function;
-------------------------------------------------
-- Clocks and enables
-------------------------------------------------
signal clk_counter : std_logic_vector(4 downto 0);
signal cpu_cycle : std_logic;
signal cpu_clken : std_logic;
signal pia_clken : std_logic;
signal sample_data : std_logic;
-------------------------------------------------
-- CPU signals
-------------------------------------------------
signal powerup_reset_n_sync : std_logic;
signal ext_reset_n_sync : std_logic;
signal RSTn : std_logic;
signal cpu_R_W_n : std_logic;
signal not_cpu_R_W_n : std_logic;
signal cpu_addr : std_logic_vector (15 downto 0);
signal cpu_din : std_logic_vector (7 downto 0);
signal cpu_dout : std_logic_vector (7 downto 0);
signal cpu_IRQ_n : std_logic;
signal cpu_NMI_n : std_logic;
signal ExternDin1 : std_logic_vector (7 downto 0);
signal ExternDout1 : std_logic_vector (7 downto 0);
---------------------------------------------------
-- VDG signals
---------------------------------------------------
signal vdg_fs_n : std_logic;
signal vdg_an_g : std_logic;
signal vdg_gm : std_logic_vector(2 downto 0);
signal vdg_css : std_logic;
signal vdg_red : std_logic;
signal vdg_green1 : std_logic;
signal vdg_green0 : std_logic;
signal vdg_blue : std_logic;
signal vdg_hsync : std_logic;
signal vdg_vsync : std_logic;
signal vdg_blank : std_logic;
----------------------------------------------------
-- Device enables
----------------------------------------------------
signal mc6522_enable : std_logic;
signal i8255_enable : std_logic;
signal ext_ramrom_enable : std_logic;
signal ext_bus_enable : std_logic;
signal video_ram_enable : std_logic;
signal reg_enable : std_logic;
signal sid_enable : std_logic;
signal uart_enable : std_logic;
signal counter_enable : std_logic;
signal gated_we : std_logic;
signal video_ram_we : std_logic;
signal reg_we : std_logic;
signal sid_we : std_logic;
signal uart_we : std_logic;
----------------------------------------------------
-- External data
----------------------------------------------------
signal extern_data : std_logic_vector(7 downto 0);
signal godil_data : std_logic_vector(7 downto 0);
----------------------------------------------------
-- 6522 signals
----------------------------------------------------
signal via4_clken : std_logic;
signal via1_clken : std_logic;
signal mc6522_data : std_logic_vector(7 downto 0);
signal mc6522_irq : std_logic;
signal mc6522_ca1 : std_logic;
signal mc6522_ca2 : std_logic;
signal mc6522_cb1 : std_logic;
signal mc6522_cb2 : std_logic;
signal mc6522_porta : std_logic_vector(7 downto 0);
signal mc6522_portb : std_logic_vector(7 downto 0);
----------------------------------------------------
-- 8255 signals
----------------------------------------------------
signal i8255_pa_data : std_logic_vector(7 downto 0);
signal i8255_pb_idata : std_logic_vector(7 downto 0);
signal i8255_pc_data : std_logic_vector(7 downto 0);
signal i8255_pc_idata : std_logic_vector(7 downto 0);
signal i8255_data : std_logic_vector(7 downto 0);
signal i8255_rd : std_logic;
signal ps2dataout : std_logic_vector(5 downto 0);
signal key_shift : std_logic;
signal key_ctrl : std_logic;
signal key_repeat : std_logic;
signal key_break : std_logic;
signal key_escape : std_logic;
signal key_turbo : std_logic_vector(1 downto 0);
signal cas_divider : std_logic_vector(15 downto 0);
signal cas_tone : std_logic;
signal turbo : std_logic_vector(1 downto 0);
signal turbo_synced : std_logic_vector(1 downto 0);
----------------------------------------------------
-- AtoMMC signals
----------------------------------------------------
signal pl8_enable : std_logic;
signal pl8_data : std_logic_vector (7 downto 0);
signal uart_escape : std_logic;
signal uart_break : std_logic;
signal nARD : std_logic;
signal nAWR : std_logic;
signal AVRA0 : std_logic;
signal AVRInt : std_logic;
signal AVRDataIn : std_logic_vector (7 downto 0);
signal AVRDataOut : std_logic_vector (7 downto 0);
signal ioport : std_logic_vector (7 downto 0);
signal LED1n : std_logic;
signal LED2n : std_logic;
signal avr_TxD_debugger : std_logic;
signal avr_TxD_atommc : std_logic;
----------------------------------------------------
-- Profiling Counter Signals
----------------------------------------------------
signal p_counter_ctrl : std_logic_vector (7 downto 0);
signal p_counter_data : std_logic_vector (7 downto 0);
signal p_divider_latch : std_logic_vector (31 downto 0);
signal p_divider_counter : std_logic_vector (31 downto 0);
signal p_profile_counter : std_logic_vector (31 downto 0);
signal p_reset : std_logic;
signal p_pause : std_logic;
signal p_reset_last : std_logic;
--------------------------------------------------------------------
-- here it begin :)
--------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- 6502 CPU (using a wrapper module
---------------------------------------------------------------------
cpu : entity work.CpuWrapper
generic map (
CImplDebugger => CImplDebugger,
CImplCpu65c02 => CImplCpu65c02
)
port map (
clk_main => clk_main,
clk_avr => clk_avr_debug,
cpu_clken => cpu_clken,
IRQ_n => cpu_IRQ_n,
NMI_n => nmi_n,
RST_n => RSTn,
PRST_n => powerup_reset_n,
SO => So,
RDY => Rdy,
Din => cpu_din,
Dout => cpu_dout,
R_W_n => cpu_R_W_n,
Sync => Sync,
Addr => cpu_addr,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD_debugger
);
not_cpu_R_W_n <= not cpu_R_W_n;
cpu_IRQ_n <= irq_n and mc6522_irq when CImplVIA else
irq_n;
cpu_NMI_n <= nmi_n;
avr_TxD <= avr_TxD_debugger and avr_TxD_atommc;
-- reset logic
process(clk_main)
begin
if rising_edge(clk_main) then
powerup_reset_n_sync <= powerup_reset_n;
ext_reset_n_sync <= ext_reset_n;
RSTn <= key_break and powerup_reset_n_sync and ext_reset_n_sync;
int_reset_n <= key_break;
end if;
end process;
-- write enables
gated_we <= not_cpu_R_W_n;
uart_we <= gated_we;
video_ram_we <= gated_we and video_ram_enable;
reg_we <= gated_we;
sid_we <= gated_we;
-- external bus
rnw <= cpu_R_W_n;
addr <= cpu_addr;
---------------------------------------------------------------------
-- Atom GODIL Video adapter
---------------------------------------------------------------------
Inst_AtomGodilVideo : entity work.AtomGodilVideo
generic map (
CImplGraphicsExt => CImplGraphicsExt,
CImplSoftChar => CImplSoftChar,
CImplSID => CImplSID,
CImplVGA80x40 => CImplVGA80x40,
CImplHWScrolling => CImplHWScrolling,
CImplMouse => CImplMouse,
CImplUart => CImplUart,
CImplDoubleVideo => CImplDoubleVideo,
MainClockSpeed => MainClockSpeed,
DefaultBaud => DefaultBaud
)
port map (
clock_vga => clk_vga,
clock_main => clk_main,
clock_sid_32Mhz => clk_32M00,
clock_sid_dac => clk_dac,
reset => not RSTn,
reset_vid => '0',
din => cpu_dout,
dout => godil_data,
addr => cpu_addr(12 downto 0),
CSS => vdg_css,
AG => vdg_an_g,
GM => vdg_gm,
nFS => vdg_fs_n,
ram_we => video_ram_we,
reg_cs => reg_enable,
reg_we => reg_we,
sid_cs => sid_enable,
sid_we => sid_we,
sid_audio => sid_audio,
sid_audio_d => sid_audio_d,
PS2_CLK => ps2_mouse_clk,
PS2_DATA => ps2_mouse_data,
uart_cs => uart_enable,
uart_we => uart_we,
uart_RxD => uart_RxD,
uart_TxD => uart_TxD,
uart_escape => uart_escape,
uart_break => uart_break,
final_red => vdg_red,
final_green1 => vdg_green1,
final_green0 => vdg_green0,
final_blue => vdg_blue,
final_vsync => vdg_vsync,
final_hsync => vdg_hsync,
final_blank => vdg_blank,
charSet => charSet
);
-- external ouputs
red(2 downto 0) <= vdg_red & vdg_red & vdg_red;
green(2 downto 0) <= vdg_green1 & vdg_green0 & vdg_green0;
blue(2 downto 0) <= vdg_blue & vdg_blue & vdg_blue;
vsync <= vdg_vsync;
hsync <= vdg_hsync;
blank <= vdg_blank;
---------------------------------------------------------------------
-- 8255 PIA
---------------------------------------------------------------------
pia : entity work.I82C55 port map(
I_ADDR => cpu_addr(1 downto 0), -- A1-A0
I_DATA => cpu_dout, -- D7-D0
O_DATA => i8255_data,
CS_H => i8255_enable,
WR_L => cpu_R_W_n,
O_PA => i8255_pa_data,
I_PB => i8255_pb_idata,
I_PC => i8255_pc_idata(7 downto 4),
O_PC => i8255_pc_data(3 downto 0),
RESET => RSTn,
ENA => pia_clken,
CLK => clk_main);
-- Port A
-- bits 7..4 (output) determine the 6847 graphics mode
-- bits 3..0 (output) drive the keyboard matrix
vdg_gm <= i8255_pa_data(7 downto 5) when RSTn='1' else "000";
vdg_an_g <= i8255_pa_data(4) when RSTn='1' else '0';
kbd_pa <= i8255_pa_data(3 downto 0);
-- Port B
-- bits 7..0 (input) read the keyboard matrix
i8255_pb_idata <= (key_shift & key_ctrl & ps2dataout) and (kbd_pb);
-- Port C
-- bit 7 (input) FS from the 6847
-- bit 6 (input) Repeat from the keyboard matrix
-- bit 5 (input) Cassette input
-- bit 4 (input) 2.4KHz tone input
-- bit 3 (output) CSS to the 6847
-- bit 2 (output) Audio
-- bit 1 (output) Enable 2.4KHz tone to casette output
-- bit 0 (output) Cassette output
vdg_css <= i8255_pc_data(3) when RSTn='1' else '0';
atom_audio <= i8255_pc_data(2);
i8255_pc_idata <= vdg_fs_n & (key_repeat and kbd_pc(6)) & cas_in & cas_tone & i8255_pc_data (3 downto 0);
-- Cassette divider
-- 32 MHz / 2 / 13 / 16 / 16 = 4807 Hz
process(clk_32M00)
begin
if rising_edge(clk_32M00) then
if cas_divider = 0 then
cas_divider <= x"19FF";
cas_tone <= not cas_tone;
else
cas_divider <= cas_divider - 1;
end if;
end if;
end process;
-- this is a direct translation of the logic in the atom
-- (two NAND gates and an inverter)
cas_out <= not(not((not cas_tone) and i8255_pc_data(1)) and i8255_pc_data(0));
---------------------------------------------------------------------
-- PS/2 Keyboard Emulation
---------------------------------------------------------------------
input : entity work.keyboard port map(
CLOCK => clk_main,
nRESET => powerup_reset_n_sync,
CLKEN_1MHZ => cpu_clken,
PS2_CLK => ps2_clk,
PS2_DATA => ps2_data,
KEYOUT => ps2dataout,
ROW => i8255_pa_data(3 downto 0),
ESC_IN => uart_escape,
BREAK_IN => uart_break,
SHIFT_OUT => key_shift,
CTRL_OUT => key_ctrl,
REPEAT_OUT => key_repeat,
BREAK_OUT => key_break,
TURBO => key_turbo,
ESC_OUT => key_escape,
Joystick1 => Joystick1,
Joystick2 => Joystick2
);
---------------------------------------------------------------------
-- 6522 VIA
---------------------------------------------------------------------
Inst_via: if (CImplVIA) generate
via : entity work.M6522 port map(
I_RS => cpu_addr(3 downto 0),
I_DATA => cpu_dout,
O_DATA => mc6522_data(7 downto 0),
I_RW_L => cpu_R_W_n,
I_CS1 => mc6522_enable,
I_CS2_L => '0',
O_IRQ_L => mc6522_irq,
I_CA1 => mc6522_ca1,
I_CA2 => mc6522_ca2,
O_CA2 => mc6522_ca2,
I_PA => mc6522_porta(7 downto 0),
O_PA => mc6522_porta(7 downto 0),
I_CB1 => mc6522_cb1,
O_CB1 => mc6522_cb1,
I_CB2 => mc6522_cb2,
O_CB2 => mc6522_cb2,
I_PB => mc6522_portb(7 downto 0),
O_PB => mc6522_portb(7 downto 0),
RESET_L => RSTn,
I_P2_H => via1_clken,
ENA_4 => via4_clken,
CLK => clk_main);
mc6522_ca1 <= '1';
end generate;
--------------------------------------------------------
-- SDDOS
--------------------------------------------------------
Inst_spi: if (CImplSDDOS) generate
Inst_spi_comp : entity work.SPI_Port
port map (
nRST => RSTn,
clk => clk_main,
enable => pl8_enable,
nwe => cpu_R_W_n,
address => cpu_addr(2 downto 0),
datain => cpu_dout,
dataout => pl8_data,
MISO => SDMISO,
MOSI => SDMOSI,
NSS => SDSS,
SPICLK => SDCLK
);
LED1 <= '0';
LED2 <= '0';
end generate;
--------------------------------------------------------
-- AtomMMC
--------------------------------------------------------
Inst_atommc2: if (CImplAtoMMC2) generate
Inst_AVR8: entity work.AVR8
generic map(
CDATAMEMSIZE => 4096,
CPROGMEMSIZE => 9216,
FILENAME => "avr_progmem_atommc2.data",
CImplPORTA => TRUE,
CImplPORTB => TRUE,
CImplPORTD => TRUE,
CImplPORTE => TRUE,
CImplUART => TRUE,
CImplSPI => TRUE,
CImplExtIRQ => TRUE
)
port map(
clk16M => clk_avr,
nrst => RSTn,
portain => AVRDataOut,
portaout => AVRDataIn,
portbin(0) => '0',
portbin(1) => '0',
portbin(2) => '0',
portbin(3) => '0',
portbin(4) => AVRInt,
portbin(5) => '0',
portbin(6) => '0',
portbin(7) => '0',
portbout(0) => nARD,
portbout(1) => nAWR,
portbout(2) => open,
portbout(3) => AVRA0,
portbout(4) => open,
portbout(5) => open,
portbout(6) => LED1n,
portbout(7) => LED2n,
portdin => (others => '0'),
portdout(0) => open,
portdout(1) => open,
portdout(2) => open,
portdout(3) => open,
portdout(4) => SDSS,
portdout(5) => open,
portdout(6) => open,
portdout(7) => open,
-- FUDLR
portein => ioport,
porteout => open,
spi_mosio => SDMOSI,
spi_scko => SDCLK,
spi_misoi => SDMISO,
rxd => avr_RxD,
txd => avr_TxD_atommc
);
ioport <= "111" & Joystick1(5) & Joystick1(0) & Joystick1(1) & Joystick1(2) & Joystick1(3);
Inst_AtomPL8: entity work.AtomPL8 port map(
clk => clk_main,
enable => pl8_enable,
nRST => RSTn,
RW => cpu_R_W_n,
Addr => cpu_addr(2 downto 0),
DataIn => cpu_dout,
DataOut => pl8_data,
AVRDataIn => AVRDataIn,
AVRDataOut => AVRDataOut,
nARD => nARD,
nAWR => nAWR,
AVRA0 => AVRA0,
AVRINTOut => AVRInt,
AtomIORDOut => open,
AtomIOWROut => open
);
LED1 <= not LED1n;
LED2 <= not LED2n;
end generate;
Inst_not_atommc2: if not CImplAtoMMC2 generate
avr_TxD_atommc <= '1';
end generate;
---------------------------------------------------------------------
-- No SD Filesystem
---------------------------------------------------------------------
Inst_no_atommc2: if ((not CImplSDDOS) and (not CImplAtoMMC2)) generate
SDCLK <= '1';
SDSS <= '1';
SDMOSI <= '1';
LED1 <= '0';
LED2 <= '0';
end generate;
---------------------------------------------------------------------
-- Ram Rom board functionality
---------------------------------------------------------------------
process(clk_main)
begin
if rising_edge(clk_main) then
if sample_data = '1' then
ExternDout1 <= ExternDout;
end if;
end if;
end process;
Inst_RamRomNone: if (CImplRamRomNone) generate
Inst_RamRomNone_comp: entity work.RamRom_None
port map(
clock => clk_main,
reset_n => RSTn,
-- signals from/to 6502
cpu_addr => cpu_addr,
cpu_we => not_cpu_R_W_n,
cpu_dout => cpu_dout,
cpu_din => extern_data,
-- signals from/to external memory system
ExternCE => ExternCE,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin1,
ExternDout => ExternDout1
);
turbo <= key_turbo;
end generate;
Inst_RamRomPhill: if (CImplRamRomPhill) generate
Inst_RamRomPhill_comp: entity work.RamRom_Phill
port map(
clock => clk_main,
reset_n => RSTn,
-- signals from/to 6502
cpu_addr => cpu_addr,
cpu_we => not_cpu_R_W_n,
cpu_dout => cpu_dout,
cpu_din => extern_data,
-- signals from/to external memory system
ExternCE => ExternCE,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin1,
ExternDout => ExternDout1
);
turbo <= key_turbo;
end generate;
Inst_RamRomAtom2015: if (CImplRamRomAtom2015) generate
Inst_RamRomAtom2015_comp: entity work.RamRom_Atom2015
generic map(
InitBFFE => InitBFFE_Atom2015,
InitBFFF => x"00"
)
port map(
clock => clk_main,
reset_n => RSTn,
-- signals from/to 6502
cpu_addr => cpu_addr,
cpu_we => not_cpu_R_W_n,
cpu_dout => cpu_dout,
cpu_din => extern_data,
-- signals from/to external memory system
ExternCE => ExternCE,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin1,
ExternDout => ExternDout1,
-- turbo mode control
turbo_in => key_turbo,
turbo_out => turbo
);
end generate;
Inst_RamRomSchakelKaart: if (CImplRamRomSchakelKaart) generate
Inst_RamRomSchakelKaart_comp: entity work.RamRom_SchakelKaart
port map(
clock => clk_main,
reset_n => RSTn,
-- signals from/to 6502
cpu_addr => cpu_addr,
cpu_we => not_cpu_R_W_n,
cpu_dout => cpu_dout,
cpu_din => extern_data,
-- signals from/to external memory system
ExternCE => ExternCE,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin1,
ExternDout => ExternDout1
);
turbo <= key_turbo;
end generate;
ExternDin <= ExternDin1 when cpu_R_W_n = '0' else cpu_din;
---------------------------------------------------------------------
-- Profiling Counters
---------------------------------------------------------------------
Inst_ProfilingCounters: if (CImplProfilingCounters) generate
p_reset <= p_counter_ctrl(0);
p_pause <= p_counter_ctrl(1);
process(clk_main)
begin
if rising_edge(clk_main) then
-- Detect falling edge of reset
p_reset_last <= p_reset;
if (p_reset_last = '1' and p_reset = '0') or (p_pause = '0' and p_divider_counter = 0) then
-- Reload the divider on falling edge of reset, or when it reaches 0
p_divider_counter <= p_divider_latch - 1;
elsif p_pause = '0' then
-- Otherwise decrent divider if not paused
p_divider_counter <= p_divider_counter - 1;
end if;
-- Clock main counter when divider reaches 0
if p_divider_counter = 0 and p_reset = '0' and p_pause = '0' then
p_profile_counter <= p_profile_counter + 1;
end if;
-- CPU Writes to Counter Registers
if cpu_clken = '1' and counter_enable = '1' and cpu_R_W_n = '0' then
case cpu_addr(3 downto 0) is
when x"0" => p_counter_ctrl <= cpu_dout;
when x"4" => p_divider_latch(7 downto 0) <= cpu_dout;
when x"5" => p_divider_latch(15 downto 8) <= cpu_dout;
when x"6" => p_divider_latch(23 downto 16) <= cpu_dout;
when x"7" => p_divider_latch(31 downto 24) <= cpu_dout;
when x"8" => p_profile_counter(7 downto 0) <= cpu_dout;
when x"9" => p_profile_counter(15 downto 8) <= cpu_dout;
when x"A" => p_profile_counter(23 downto 16) <= cpu_dout;
when x"B" => p_profile_counter(31 downto 24) <= cpu_dout;
when others => null;
end case;
end if;
-- CPU Reads from Counter Registers
case cpu_addr(3 downto 0) is
when x"0" => p_counter_data <= p_counter_ctrl;
when x"4" => p_counter_data <= p_divider_latch(7 downto 0);
when x"5" => p_counter_data <= p_divider_latch(15 downto 8);
when x"6" => p_counter_data <= p_divider_latch(23 downto 16);
when x"7" => p_counter_data <= p_divider_latch(31 downto 24);
when x"8" => p_counter_data <= p_profile_counter(7 downto 0);
when x"9" => p_counter_data <= p_profile_counter(15 downto 8);
when x"A" => p_counter_data <= p_profile_counter(23 downto 16);
when x"B" => p_counter_data <= p_profile_counter(31 downto 24);
when others => p_counter_data <= x"00";
end case;
end if;
end process;
end generate;
---------------------------------------------------------------------
-- Device enables
---------------------------------------------------------------------
process(cpu_addr)
begin
-- All regions normally de-selected
mc6522_enable <= '0';
i8255_enable <= '0';
video_ram_enable <= '0';
sid_enable <= '0';
pl8_enable <= '0';
reg_enable <= '0';
uart_enable <= '0';
counter_enable <= '0';
ext_ramrom_enable <= '0';
ext_bus_enable <= '0';
case cpu_addr(15 downto 12) is
when x"0" => ext_ramrom_enable <= '1'; -- 0x0000 -- 0x03ff is RAM
when x"1" => ext_ramrom_enable <= '1';
when x"2" => ext_ramrom_enable <= '1';
when x"3" => ext_ramrom_enable <= '1';
when x"4" => ext_ramrom_enable <= '1';
when x"5" => ext_ramrom_enable <= '1';
when x"6" => ext_ramrom_enable <= '1';
when x"7" => ext_ramrom_enable <= '1';
when x"8" => video_ram_enable <= '1'; -- 0x8000 -- 0x9fff is RAM
when x"9" => video_ram_enable <= '1';
when x"A" => ext_ramrom_enable <= '1';
when x"B" =>
if cpu_addr(11 downto 4) = x"00" then -- 0xB00x 8255 PIA
i8255_enable <= '1';
elsif cpu_addr(11 downto 4) = x"40" then -- 0xB40x AtoMMC/SPI
if CImplSDDOS or CImplAtoMMC2 then
pl8_enable <= '1';
else
ext_bus_enable <= '1';
end if;
elsif cpu_addr(11 downto 4) = x"80" then -- 0xB80x 6522 VIA
if CImplVIA then
mc6522_enable <= '1';
else
ext_bus_enable <= '1';
end if;
elsif cpu_addr(11 downto 4) = x"DA" then -- 0xBDAx Profiling Counters
if CImplProfilingCounters then
counter_enable <= '1';
else
ext_bus_enable <= '1';
end if;
elsif cpu_addr(11 downto 4) = x"DB" then -- 0xBDBx UART
if CImplUart then
uart_enable <= '1';
else
ext_bus_enable <= '1';
end if;
elsif cpu_addr(11 downto 5) & '0' = x"DC" then -- 0xBDCx, 0xBDDx SID
if CImplSID then
sid_enable <= '1';
else
ext_bus_enable <= '1';
end if;
elsif cpu_addr(11 downto 5) & '0' = x"DE" then -- 0xBDEx, 0xBDFx GODIL Registers
reg_enable <= '1';
elsif cpu_addr(11 downto 2) & "00"= x"FFC" then -- 0xBFFC-BFFF RomLatch
ext_ramrom_enable <= '1';
elsif cpu_addr(11 downto 7) /= "11011" then -- any non-mapped 0xBxxx address is deemed external
ext_bus_enable <= '1'; -- apart from 0xBD80-0xBDFF which are deemed reserved
end if;
when x"C" => ext_ramrom_enable <= '1';
when x"D" => ext_ramrom_enable <= '1';
when x"E" => ext_ramrom_enable <= '1';
when x"F" => ext_ramrom_enable <= '1';
when others => null;
end case;
end process;
-- External bus enable
ExternBus <= ext_bus_enable;
---------------------------------------------------------------------
-- CPU data input multiplexor
---------------------------------------------------------------------
cpu_din <=
godil_data when video_ram_enable = '1' else
i8255_data when i8255_enable = '1' else
mc6522_data when mc6522_enable = '1' else
godil_data when sid_enable = '1' and CImplSID else
godil_data when uart_enable = '1' and CImplUart else
godil_data when reg_enable = '1' else -- TODO add CImpl constraint
pl8_data when pl8_enable = '1' and CImplSDDOS else
pl8_data when pl8_enable = '1' and CImplAtoMMC2 else
extern_data when ext_ramrom_enable = '1' else
extern_data when ext_bus_enable = '1' else
p_counter_data when counter_enable = '1' and CImplProfilingCounters else
x"f1"; -- un-decoded locations
--------------------------------------------------------
-- Clock enable generator
--------------------------------------------------------
process(clk_main)
variable mask4 : std_logic_vector(4 downto 0);
variable limit : integer;
variable phi2l : integer;
variable phi2h : integer;
variable sampl : integer;
begin
-- Don't include reset here, so 6502 continues to be clocked during reset
if rising_edge(clk_main) then
-- Counter:
-- main_clock = 32MHz
-- 1MHz 0..31
-- 2MHz 0..15
-- 4MHz 0..7
-- 8MHz 0..3
-- main_clock = 16MHz
-- 1MHz 0..15
-- 2MHz 0..7
-- 4MHz 0..3
-- 8MHz not supported
-- Work out optimal timing
-- mask4 - mask to give a 4x speed clock
-- limit - maximum value of clk_counter so it wraps at 1MHz
-- phi2l - when phi2 should go low
-- phi2h - when phi2 should go high
-- sample - when sample_data should asserted
-- none of the variables are stateful
if (MainClockSpeed = 32000000) then
-- 32MHz
case (turbo_synced) is
when "11" => mask4 := "00000"; limit := 3; phi2l := 3; phi2h := 1; sampl := 2; -- 8MHz
when "10" => mask4 := "00001"; limit := 7; phi2l := 7; phi2h := 3; sampl := 6; -- 4MHz
when "01" => mask4 := "00011"; limit := 15; phi2l := 15; phi2h := 7; sampl := 14; -- 2MHz
when others => mask4 := "00111"; limit := 31; phi2l := 31; phi2h := 15; sampl := 30; -- 1MHz
end case;
else
-- 16MHz
case (turbo_synced) is
when "10" => mask4 := "00000"; limit := 3; phi2l := 3; phi2h := 1; sampl := 2; -- 4MHz
when "01" => mask4 := "00001"; limit := 7; phi2l := 7; phi2h := 3; sampl := 6; -- 2MHz
when others => mask4 := "00011"; limit := 15; phi2l := 15; phi2h := 7; sampl := 14; -- 1MHz
end case;
end if;
if clk_counter = limit then
turbo_synced <= turbo; -- only change the timing at the end of the cycle
clk_counter <= (others => '0');
else
clk_counter <= clk_counter + 1;
end if;
-- Assert cpu_clken in cycle 0
if clk_counter = limit then
cpu_clken <= '1';
else
cpu_clken <= '0';
end if;
-- Assert pia_clken in anti-phase with cpu_clken
if clk_counter = phi2h then
pia_clken <= '1';
else
pia_clken <= '0';
end if;
-- Assert via1_clken in cycle 0
if clk_counter = limit then
via1_clken <= '1';
else
via1_clken <= '0';
end if;
-- Assert via4 at 4x the rate of via1
if (clk_counter and mask4) = (std_logic_vector(to_unsigned(limit,5)) and mask4) then
via4_clken <= '1';
else
via4_clken <= '0';
end if;
-- Assert phi2 at the specified times
if clk_counter = phi2h then
phi2 <= '1';
elsif clk_counter = phi2l then
phi2 <= '0';
end if;
-- Assert sample_data at the specified time
if clk_counter = sampl then
sample_data <= '1';
else
sample_data <= '0';
end if;
end if;
end process;
end BEHAVIORAL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:23:52 10/22/2015
-- Design Name:
-- Module Name: control_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity control_unit is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
hlt : in STD_LOGIC;
exe : out STD_LOGIC;
pc_en : out STD_LOGIC;
op_en : out STD_LOGIC;
mem_en : out STD_LOGIC);
end control_unit;
architecture Behavioral of control_unit is
-- Intermediate Signals --
signal cycle_counter : std_logic_vector( 2 downto 0 );
signal received_hlt : std_logic;
begin
process( clk )
begin
if reset = '1' then
cycle_counter <= "001";
exe <= '0';
op_en <= '1';
mem_en <= '0';
pc_en <= '1';
received_hlt <= '0';
elsif received_hlt = '0' then
if hlt = '1' then
cycle_counter <= "000";
exe <= '0';
op_en <= '0';
mem_en <= '0';
pc_en <= '0';
received_hlt <= '1';
elsif rising_edge(clk) then
-- Cycle 1 --
-- OP code --
if cycle_counter = "000" then
exe <= '0';
op_en <= '1';
mem_en <= '0';
pc_en <= '1';
-- Cycle 2, 3, 4 --
-- Address Writing --
elsif cycle_counter = "001" or cycle_counter = "010" or cycle_counter = "011" then
exe <= '0';
op_en <= '0';
mem_en <= '1';
pc_en <= '1';
-- Cycles 5 --
-- Execute --
elsif cycle_counter = "100" then
exe <= '0';
op_en <= '0';
mem_en <= '1';
pc_en <= '1';
-- Cycles 6 --
-- Execute --
elsif cycle_counter = "101" then
exe <= '1';
op_en <= '0';
mem_en <= '0';
pc_en <= '0';
end if;
if cycle_counter = "101" then
cycle_counter <= "000";
else
cycle_counter <= cycle_counter + '1';
end if;
else
end if;
else
cycle_counter <= "000";
exe <= '0';
op_en <= '0';
mem_en <= '0';
pc_en <= '0';
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Generic_Equalizer_Debugger is
port(clk : in std_logic;
reset : in std_logic;
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end Generic_Equalizer_Debugger;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Generic_Equalizer_Debugger is
begin
Generic_Equalizer : entity work.Generic_Equalizer
generic map(NO_SECTIONS => 9,
INPUT_WIDTH => 16,
INPUT_FRACT => 14,
OUTPUT_WIDTH => 16,
OUTPUT_FRACT => 14,
SCALE_WIDTH => 16,
SCALE_FRACT => (14,14,14,14,14,14,14,14,14,14),
INTERNAL_WIDTH => 16,
INTERNAL_FRACT => 14,
COEFF_WIDTH_B => 16,
COEFF_FRACT_B => (14,14,14,14,14,14,14,14,14),
COEFF_WIDTH_A => 16,
COEFF_FRACT_A => (14,14,14,14,14,14,14,14,14))
port map(clk => clk,
reset => reset,
x => input,
scale => (x"4000"
& x"4001"
& x"4002"
& x"4003"
& x"4004"
& x"4005"
& x"4006"
& x"4007"
& x"4008"
& x"4009"),
b0 => (x"4010"
& x"4011"
& x"4012"
& x"4013"
& x"4014"
& x"4015"
& x"4016"
& x"4017"
& x"4018"),
b1 => (x"4020"
& x"0021"
& x"0022"
& x"0023"
& x"0024"
& x"0025"
& x"0026"
& x"0027"
& x"0028"),
b2 => (x"4030"
& x"0031"
& x"0032"
& x"0033"
& x"0034"
& x"0035"
& x"0036"
& x"0037"
& x"0038"),
a1 => (x"4040"
& x"0041"
& x"0042"
& x"0043"
& x"0044"
& x"0045"
& x"0046"
& x"0047"
& x"0048"),
a2 => (x"4050"
& x"0051"
& x"0052"
& x"0053"
& x"0054"
& x"0055"
& x"0056"
& x"0057"
& x"0058"),
y => output);
end architecture; |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT pcie_data_rec_fifo_top IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(11-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
ALMOST_FULL : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
entity for1 is
end;
architecture behav of for1 is
begin
process
begin
for i in 1 to 10 loop
report "hello";
wait for 1 ns;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
|
entity for1 is
end;
architecture behav of for1 is
begin
process
begin
for i in 1 to 10 loop
report "hello";
wait for 1 ns;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 99168)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Justin Nguyen, Quinn Mikelson
--
-- Create Date: 18:59:22 01/11/2012
-- Design Name:
-- Module Name: F:/repos/cpe-233-test-benches/lab-4-arc/RegisterFileTestBench.vhd
-- Project Name: RAT CPU
-- Target Device: xc7a50tcsg324-1
-- Tool versions:
-- Description: Testbench for Scratch RAM component of RAT CPU.
--
-- VHDL Test Bench Created by ISE for module: RegisterFile
--
-- Dependencies: ScratchRAM
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- Runtime must be set to 700ns for proper execution
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ScratchRamTestBench IS
END ScratchRamTestBench;
ARCHITECTURE behavior OF ScratchRamTestBench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ScratchRam
PORT(
DATA_IN : IN std_logic_vector(9 downto 0);
DATA_OUT : OUT std_logic_vector(9 downto 0);
ADDR : IN std_logic_vector(7 downto 0);
WE : IN std_logic;
CLK : IN std_logic
);
END COMPONENT;
-- test signals
signal data_x_exp : std_logic_vector(9 downto 0) := "0000000000";
signal data_y_exp : std_logic_vector(9 downto 0) := "0000000000";
--Inputs
signal D_IN_tb : std_logic_vector(9 downto 0) := (others => '0');
signal ADRX_tb : std_logic_vector(7 downto 0) := (others => '0');
signal ADRY_tb : std_logic_vector(7 downto 0) := (others => '0');
signal DX_OE_tb : std_logic := '0';
signal WE_tb : std_logic := '0';
signal CLK_tb : std_logic := '0';
--Outputs
signal DX_OUT_tb : std_logic_vector(9 downto 0);
signal DY_OUT_tb : std_logic_vector(9 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ScratchRam PORT MAP (
DATA_IN => D_IN_tb,
DATA_OUT => DX_OUT_tb,
ADDR => ADRX_tb,
WE => WE_tb,
CLK => CLK_tb
);
-- Clock process definitions
CLK_process :process
begin
CLK_tb <= '0';
wait for CLK_period/2;
CLK_tb <= '1';
wait for CLK_period/2;
end process;
-- verify memory
VERIFY_process :process
variable I : integer range 0 to 32 := 0;
begin
--Write to RegisterFile
ADRX_tb<="00000000";
D_IN_tb<="0000000000";
wait for 4ns;
WE_tb <= '1'; --togle high before rising edge
wait for 1ns;
while( I < 32) loop
wait for 1ns;
WE_tb <= '0'; --drop after rising edge
wait for 1ns;
ADRX_tb <= ADRX_tb + 1; --prepare next address and data
wait for 1ns;
D_IN_tb <= D_IN_tb +2;
wait for 6ns;
I := I+1;
if(I <32) then
WE_tb <= '1';
end if;
wait for 1ns;
end loop;
WE_tb <= '0';
DX_OE_tb <= '1';
wait for 75ns; --no reason, just like to start at a nice number such as 400ns...
-- Read from RegisterFile
I := 0;
-- set initial values
data_x_exp <= "0000000000";
data_y_exp <= "0000000010";
ADRX_tb <= "00000000";
ADRY_tb <= "00000001";
-- loop through all memory locations. NOTE: can read two at once
while ( I < 16) loop
WE_tb <= '0';
wait for 1ns;
if not(DX_OUT_tb = data_x_exp) then
report "error with data X at t= " & time'image(now)
severity failure;
else
report "data X at t= " & time'image(now) & " is good"
severity note;
end if;
if not(DY_OUT_tb = data_y_exp) then
report "error with data Y at t= " & time'image(now)
severity failure;
else
report "data Y at t= " & time'image(now) & " is good"
severity note;
end if;
wait for 1ns;
--get new values
data_x_exp <= data_x_exp + 4 ; --add 4 because each location increases by 2, and you're increasing by 2 memory locations
data_y_exp <= data_y_exp + 4 ;
ADRX_tb <= ADRX_tb + 2;
ADRY_tb <= ADRY_tb + 2;
wait for 8ns;
I := I + 1;
end loop;
wait for 40ns; -- again, just lining up for a nice start time of 600ns.
end process;
END; |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 20
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:06:01 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_c_addsub_0_0/system_c_addsub_0_0_sim_netlist.vhdl
-- Design : system_c_addsub_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
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oMSb+/kVbFoEDx1wFTpo9U4c2NoGCLVXMAlxH6rhh8o5X/nHgtqmrMeP+Ak0sCt0xdrLkjadlasF
vvEA+nHPOqWRC+mxVp37oHtZVxgdcjzmb3E76wRPHRWUFCA0mt3j/l4iCmf0JwesFinjmwDtZJOx
Q4+DsdN5ra/VUPh9Fb8XEswKcPui8Qw5XpqBIOMHuPU6mHlgoh67NfVVsO0dAz0jxVgyq68A8qrt
J5Bm1qyQ977pfB4TiVwWdGmaZftfY3YQndEO0lCSt5ct0JL5vs4c6iziYQ==
`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_c_addsub_0_0_c_addsub_v12_0_10 is
port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
CLK : in STD_LOGIC;
ADD : in STD_LOGIC;
C_IN : in STD_LOGIC;
CE : in STD_LOGIC;
BYPASS : in STD_LOGIC;
SCLR : in STD_LOGIC;
SSET : in STD_LOGIC;
SINIT : in STD_LOGIC;
C_OUT : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute C_ADD_MODE : integer;
attribute C_ADD_MODE of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_AINIT_VAL : string;
attribute C_AINIT_VAL of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is "0";
attribute C_A_TYPE : integer;
attribute C_A_TYPE of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_A_WIDTH : integer;
attribute C_A_WIDTH of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 10;
attribute C_BORROW_LOW : integer;
attribute C_BORROW_LOW of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 1;
attribute C_BYPASS_LOW : integer;
attribute C_BYPASS_LOW of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_B_CONSTANT : integer;
attribute C_B_CONSTANT of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_B_TYPE : integer;
attribute C_B_TYPE of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_B_VALUE : string;
attribute C_B_VALUE of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is "0000000000";
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 10;
attribute C_CE_OVERRIDES_BYPASS : integer;
attribute C_CE_OVERRIDES_BYPASS of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 1;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_BYPASS : integer;
attribute C_HAS_BYPASS of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_CE : integer;
attribute C_HAS_CE of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_C_IN : integer;
attribute C_HAS_C_IN of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_C_OUT : integer;
attribute C_HAS_C_OUT of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_SCLR : integer;
attribute C_HAS_SCLR of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_SINIT : integer;
attribute C_HAS_SINIT of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_HAS_SSET : integer;
attribute C_HAS_SSET of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_IMPLEMENTATION : integer;
attribute C_IMPLEMENTATION of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_OUT_WIDTH : integer;
attribute C_OUT_WIDTH of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 10;
attribute C_SCLR_OVERRIDES_SSET : integer;
attribute C_SCLR_OVERRIDES_SSET of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 1;
attribute C_SINIT_VAL : string;
attribute C_SINIT_VAL of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is "0";
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is "c_addsub_v12_0_10";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_c_addsub_0_0_c_addsub_v12_0_10 : entity is "yes";
end system_c_addsub_0_0_c_addsub_v12_0_10;
architecture STRUCTURE of system_c_addsub_0_0_c_addsub_v12_0_10 is
signal \<const0>\ : STD_LOGIC;
signal NLW_xst_addsub_C_OUT_UNCONNECTED : STD_LOGIC;
attribute C_BORROW_LOW of xst_addsub : label is 1;
attribute C_CE_OVERRIDES_BYPASS of xst_addsub : label is 1;
attribute C_CE_OVERRIDES_SCLR of xst_addsub : label is 0;
attribute C_IMPLEMENTATION of xst_addsub : label is 0;
attribute C_SCLR_OVERRIDES_SSET of xst_addsub : label is 1;
attribute C_VERBOSITY of xst_addsub : label is 0;
attribute C_XDEVICEFAMILY of xst_addsub : label is "zynq";
attribute c_a_type of xst_addsub : label is 0;
attribute c_a_width of xst_addsub : label is 10;
attribute c_add_mode of xst_addsub : label is 0;
attribute c_ainit_val of xst_addsub : label is "0";
attribute c_b_constant of xst_addsub : label is 0;
attribute c_b_type of xst_addsub : label is 0;
attribute c_b_value of xst_addsub : label is "0000000000";
attribute c_b_width of xst_addsub : label is 10;
attribute c_bypass_low of xst_addsub : label is 0;
attribute c_has_bypass of xst_addsub : label is 0;
attribute c_has_c_in of xst_addsub : label is 0;
attribute c_has_c_out of xst_addsub : label is 0;
attribute c_has_ce of xst_addsub : label is 0;
attribute c_has_sclr of xst_addsub : label is 0;
attribute c_has_sinit of xst_addsub : label is 0;
attribute c_has_sset of xst_addsub : label is 0;
attribute c_latency of xst_addsub : label is 0;
attribute c_out_width of xst_addsub : label is 10;
attribute c_sinit_val of xst_addsub : label is "0";
attribute downgradeipidentifiedwarnings of xst_addsub : label is "yes";
begin
C_OUT <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
xst_addsub: entity work.system_c_addsub_0_0_c_addsub_v12_0_10_viv
port map (
A(9 downto 0) => A(9 downto 0),
ADD => '0',
B(9 downto 0) => B(9 downto 0),
BYPASS => '0',
CE => '0',
CLK => '0',
C_IN => '0',
C_OUT => NLW_xst_addsub_C_OUT_UNCONNECTED,
S(9 downto 0) => S(9 downto 0),
SCLR => '0',
SINIT => '0',
SSET => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_c_addsub_0_0 is
port (
A : in STD_LOGIC_VECTOR ( 9 downto 0 );
B : in STD_LOGIC_VECTOR ( 9 downto 0 );
S : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_c_addsub_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_c_addsub_0_0 : entity is "system_c_addsub_0_0,c_addsub_v12_0_10,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_c_addsub_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_c_addsub_0_0 : entity is "c_addsub_v12_0_10,Vivado 2016.4";
end system_c_addsub_0_0;
architecture STRUCTURE of system_c_addsub_0_0 is
signal NLW_U0_C_OUT_UNCONNECTED : STD_LOGIC;
attribute C_BORROW_LOW : integer;
attribute C_BORROW_LOW of U0 : label is 1;
attribute C_CE_OVERRIDES_BYPASS : integer;
attribute C_CE_OVERRIDES_BYPASS of U0 : label is 1;
attribute C_CE_OVERRIDES_SCLR : integer;
attribute C_CE_OVERRIDES_SCLR of U0 : label is 0;
attribute C_IMPLEMENTATION : integer;
attribute C_IMPLEMENTATION of U0 : label is 0;
attribute C_SCLR_OVERRIDES_SSET : integer;
attribute C_SCLR_OVERRIDES_SSET of U0 : label is 1;
attribute C_VERBOSITY : integer;
attribute C_VERBOSITY of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute c_a_type : integer;
attribute c_a_type of U0 : label is 0;
attribute c_a_width : integer;
attribute c_a_width of U0 : label is 10;
attribute c_add_mode : integer;
attribute c_add_mode of U0 : label is 0;
attribute c_ainit_val : string;
attribute c_ainit_val of U0 : label is "0";
attribute c_b_constant : integer;
attribute c_b_constant of U0 : label is 0;
attribute c_b_type : integer;
attribute c_b_type of U0 : label is 0;
attribute c_b_value : string;
attribute c_b_value of U0 : label is "0000000000";
attribute c_b_width : integer;
attribute c_b_width of U0 : label is 10;
attribute c_bypass_low : integer;
attribute c_bypass_low of U0 : label is 0;
attribute c_has_bypass : integer;
attribute c_has_bypass of U0 : label is 0;
attribute c_has_c_in : integer;
attribute c_has_c_in of U0 : label is 0;
attribute c_has_c_out : integer;
attribute c_has_c_out of U0 : label is 0;
attribute c_has_ce : integer;
attribute c_has_ce of U0 : label is 0;
attribute c_has_sclr : integer;
attribute c_has_sclr of U0 : label is 0;
attribute c_has_sinit : integer;
attribute c_has_sinit of U0 : label is 0;
attribute c_has_sset : integer;
attribute c_has_sset of U0 : label is 0;
attribute c_latency : integer;
attribute c_latency of U0 : label is 0;
attribute c_out_width : integer;
attribute c_out_width of U0 : label is 10;
attribute c_sinit_val : string;
attribute c_sinit_val of U0 : label is "0";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.system_c_addsub_0_0_c_addsub_v12_0_10
port map (
A(9 downto 0) => A(9 downto 0),
ADD => '1',
B(9 downto 0) => B(9 downto 0),
BYPASS => '0',
CE => '1',
CLK => '0',
C_IN => '0',
C_OUT => NLW_U0_C_OUT_UNCONNECTED,
S(9 downto 0) => S(9 downto 0),
SCLR => '0',
SINIT => '0',
SSET => '0'
);
end STRUCTURE;
|
library IEEE;
use ieee.std_logic_1164.all;
entity A is
port(
input : in std_logic_vector(31 downto 0);
clk, rst, pre, ce : in std_logic;
output : out std_logic_vector(31 downto 0)
);
end A;
architecture behav of A is
begin
PASA : entity work.thirty_two_bit_register(behav) port map(input, clk, rst, pre, ce, output);
end behav;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
-------------------------------------------------------------------------------
-- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: pselect_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
|
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