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// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_buffer_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Wraps a FIFO for saving channel data and provides a
// registered read output. Retains unread words from reads that are a length
// which is not a multiple of the data bus width (C_FIFO_DATA_WIDTH). Data is
// available 5 cycles after RD_EN is asserted (not 1, like a traditional FIFO).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_buffer_128 #(
parameter C_FIFO_DATA_WIDTH = 9'd128,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_RD_EN_HIST = 2,
parameter C_FIFO_RD_EN_HIST = 2,
parameter C_CONSUME_HIST = 3,
parameter C_COUNT_HIST = 3,
parameter C_LEN_LAST_HIST = 1
)
(
input RST,
input CLK,
input LEN_VALID, // Transfer length is valid
input [1:0] LEN_LSB, // LSBs of transfer length
input LEN_LAST, // Last transfer in transaction
input [C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
input WR_EN, // Input data write enable
output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Input data write count
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // Output data
input RD_EN // Output data read enable
);
`include "functions.vh"
reg [1:0] rRdPtr=0, _rRdPtr=0;
reg [1:0] rWrPtr=0, _rWrPtr=0;
reg [3:0] rLenLSB0=0, _rLenLSB0=0;
reg [3:0] rLenLSB1=0, _rLenLSB1=0;
reg [3:0] rLenLast=0, _rLenLast=0;
reg rLenValid=0, _rLenValid=0;
reg rRen=0, _rRen=0;
reg [2:0] rCount=0, _rCount=0;
reg [(C_COUNT_HIST*3)-1:0] rCountHist={C_COUNT_HIST{3'd0}}, _rCountHist={C_COUNT_HIST{3'd0}};
reg [C_LEN_LAST_HIST-1:0] rLenLastHist={C_LEN_LAST_HIST{1'd0}}, _rLenLastHist={C_LEN_LAST_HIST{1'd0}};
reg [C_RD_EN_HIST-1:0] rRdEnHist={C_RD_EN_HIST{1'd0}}, _rRdEnHist={C_RD_EN_HIST{1'd0}};
reg rFifoRdEn=0, _rFifoRdEn=0;
reg [C_FIFO_RD_EN_HIST-1:0] rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}}, _rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}};
reg [(C_CONSUME_HIST*3)-1:0] rConsumedHist={C_CONSUME_HIST{3'd0}}, _rConsumedHist={C_CONSUME_HIST{3'd0}};
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
reg [223:0] rData=224'd0, _rData=224'd0;
wire [C_FIFO_DATA_WIDTH-1:0] wFifoData;
assign RD_DATA = rData[0 +:C_FIFO_DATA_WIDTH];
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rLenValid <= #1 (RST ? 1'd0 : _rLenValid);
rRen <= #1 (RST ? 1'd0 : _rRen);
end
always @ (*) begin
_rLenValid = LEN_VALID;
_rRen = RD_EN;
end
// FIFO for storing data from the channel.
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
.CLK(CLK),
.RST(RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.FULL(),
.COUNT(WR_COUNT),
.RD_EN(rFifoRdEn),
.RD_DATA(wFifoData),
.EMPTY()
);
// Manage shifting of data in from the FIFO and shifting of data out once
// it is consumed. We'll keep 7 words of output registers to hold an input
// packet with up to 3 extra words of unread data.
wire [1:0] wLenLSB = {rLenLSB1[rRdPtr], rLenLSB0[rRdPtr]};
wire wLenLast = rLenLast[rRdPtr];
wire wAfterEnd = (!rRen & rRdEnHist[0]);
// consumed = 4 if RD+2
// consumed = remainder if EOP on RD+1 (~rRen & rRdEnHist[0])
// consumed = 4 if EOP on RD+3 and LAST on RD+3
wire [2:0] wConsumed = ({(rRdEnHist[0] | (!rRdEnHist[0] & rRdEnHist[1] & rLenLastHist[0])),2'd0}) - ({2{wAfterEnd}} & wLenLSB);
always @ (posedge CLK) begin
rCount <= #1 (RST ? 2'd0 : _rCount);
rCountHist <= #1 _rCountHist;
rRdEnHist <= #1 (RST ? {C_RD_EN_HIST{1'd0}} : _rRdEnHist);
rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
rFifoRdEnHist <= #1 (RST ? {C_FIFO_RD_EN_HIST{1'd0}} : _rFifoRdEnHist);
rConsumedHist <= #1 _rConsumedHist;
rLenLastHist <= #1 (RST ? {C_LEN_LAST_HIST{1'd0}} : _rLenLastHist);
rFifoData <= #1 _rFifoData;
rData <= #1 _rData;
end
always @ (*) begin
// Keep track of words in our buffer. Subtract 4 when we reach 4 on RD_EN.
// Add wLenLSB when we finish a sequence of RD_EN that read 1, 2, or 3 words.
// rCount + remainder
_rCount = rCount + ({2{(wAfterEnd & !wLenLast)}} & wLenLSB) - ({(rRen & rCount[2]), 2'd0}) - ({3{(wAfterEnd & wLenLast)}} & rCount);
_rCountHist = ((rCountHist<<3) | rCount);
// Track read enables in the pipeline.
_rRdEnHist = ((rRdEnHist<<1) | rRen);
_rFifoRdEnHist = ((rFifoRdEnHist<<1) | rFifoRdEn);
// Track delayed length last value
_rLenLastHist = ((rLenLastHist<<1) | wLenLast);
// Calculate the amount to shift out each RD_EN. This is always 4 unless it's
// the last RD_EN in the sequence and the read words length is 1, 2, or 3.
_rConsumedHist = ((rConsumedHist<<3) | wConsumed);
// Read from the FIFO unless we have 4 words cached.
_rFifoRdEn = (!rCount[2] & rRen);
// Buffer the FIFO data.
_rFifoData = wFifoData;
// Shift the buffered FIFO data into and the consumed data out of the output register.
if (rFifoRdEnHist[1])
_rData = ((rData>>({rConsumedHist[8:6], 5'd0})) | (rFifoData<<({rCountHist[7:6], 5'd0})));
else
_rData = (rData>>({rConsumedHist[8:6], 5'd0}));
end
// Buffer up to 4 length LSB values for use to detect unread data that was
// part of a consumed packet. Should only need 2. This is basically a FIFO.
always @ (posedge CLK) begin
rRdPtr <= #1 (RST ? 2'd0 : _rRdPtr);
rWrPtr <= #1 (RST ? 2'd0 : _rWrPtr);
rLenLSB0 <= #1 _rLenLSB0;
rLenLSB1 <= #1 _rLenLSB1;
rLenLast <= #1 _rLenLast;
end
always @ (*) begin
_rRdPtr = (wAfterEnd ? rRdPtr + 1'd1 : rRdPtr);
_rWrPtr = (rLenValid ? rWrPtr + 1'd1 : rWrPtr);
_rLenLSB0 = rLenLSB0;
_rLenLSB1 = rLenLSB1;
if(rLenValid)
{_rLenLSB1[rWrPtr], _rLenLSB0[rWrPtr]} = (~LEN_LSB + 1);
_rLenLast = rLenLast;
if(rLenValid)
_rLenLast[rWrPtr] = LEN_LAST;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_buffer_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Wraps a FIFO for saving channel data and provides a
// registered read output. Retains unread words from reads that are a length
// which is not a multiple of the data bus width (C_FIFO_DATA_WIDTH). Data is
// available 5 cycles after RD_EN is asserted (not 1, like a traditional FIFO).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_buffer_128 #(
parameter C_FIFO_DATA_WIDTH = 9'd128,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_RD_EN_HIST = 2,
parameter C_FIFO_RD_EN_HIST = 2,
parameter C_CONSUME_HIST = 3,
parameter C_COUNT_HIST = 3,
parameter C_LEN_LAST_HIST = 1
)
(
input RST,
input CLK,
input LEN_VALID, // Transfer length is valid
input [1:0] LEN_LSB, // LSBs of transfer length
input LEN_LAST, // Last transfer in transaction
input [C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
input WR_EN, // Input data write enable
output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Input data write count
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // Output data
input RD_EN // Output data read enable
);
`include "functions.vh"
reg [1:0] rRdPtr=0, _rRdPtr=0;
reg [1:0] rWrPtr=0, _rWrPtr=0;
reg [3:0] rLenLSB0=0, _rLenLSB0=0;
reg [3:0] rLenLSB1=0, _rLenLSB1=0;
reg [3:0] rLenLast=0, _rLenLast=0;
reg rLenValid=0, _rLenValid=0;
reg rRen=0, _rRen=0;
reg [2:0] rCount=0, _rCount=0;
reg [(C_COUNT_HIST*3)-1:0] rCountHist={C_COUNT_HIST{3'd0}}, _rCountHist={C_COUNT_HIST{3'd0}};
reg [C_LEN_LAST_HIST-1:0] rLenLastHist={C_LEN_LAST_HIST{1'd0}}, _rLenLastHist={C_LEN_LAST_HIST{1'd0}};
reg [C_RD_EN_HIST-1:0] rRdEnHist={C_RD_EN_HIST{1'd0}}, _rRdEnHist={C_RD_EN_HIST{1'd0}};
reg rFifoRdEn=0, _rFifoRdEn=0;
reg [C_FIFO_RD_EN_HIST-1:0] rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}}, _rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}};
reg [(C_CONSUME_HIST*3)-1:0] rConsumedHist={C_CONSUME_HIST{3'd0}}, _rConsumedHist={C_CONSUME_HIST{3'd0}};
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
reg [223:0] rData=224'd0, _rData=224'd0;
wire [C_FIFO_DATA_WIDTH-1:0] wFifoData;
assign RD_DATA = rData[0 +:C_FIFO_DATA_WIDTH];
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rLenValid <= #1 (RST ? 1'd0 : _rLenValid);
rRen <= #1 (RST ? 1'd0 : _rRen);
end
always @ (*) begin
_rLenValid = LEN_VALID;
_rRen = RD_EN;
end
// FIFO for storing data from the channel.
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
.CLK(CLK),
.RST(RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.FULL(),
.COUNT(WR_COUNT),
.RD_EN(rFifoRdEn),
.RD_DATA(wFifoData),
.EMPTY()
);
// Manage shifting of data in from the FIFO and shifting of data out once
// it is consumed. We'll keep 7 words of output registers to hold an input
// packet with up to 3 extra words of unread data.
wire [1:0] wLenLSB = {rLenLSB1[rRdPtr], rLenLSB0[rRdPtr]};
wire wLenLast = rLenLast[rRdPtr];
wire wAfterEnd = (!rRen & rRdEnHist[0]);
// consumed = 4 if RD+2
// consumed = remainder if EOP on RD+1 (~rRen & rRdEnHist[0])
// consumed = 4 if EOP on RD+3 and LAST on RD+3
wire [2:0] wConsumed = ({(rRdEnHist[0] | (!rRdEnHist[0] & rRdEnHist[1] & rLenLastHist[0])),2'd0}) - ({2{wAfterEnd}} & wLenLSB);
always @ (posedge CLK) begin
rCount <= #1 (RST ? 2'd0 : _rCount);
rCountHist <= #1 _rCountHist;
rRdEnHist <= #1 (RST ? {C_RD_EN_HIST{1'd0}} : _rRdEnHist);
rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
rFifoRdEnHist <= #1 (RST ? {C_FIFO_RD_EN_HIST{1'd0}} : _rFifoRdEnHist);
rConsumedHist <= #1 _rConsumedHist;
rLenLastHist <= #1 (RST ? {C_LEN_LAST_HIST{1'd0}} : _rLenLastHist);
rFifoData <= #1 _rFifoData;
rData <= #1 _rData;
end
always @ (*) begin
// Keep track of words in our buffer. Subtract 4 when we reach 4 on RD_EN.
// Add wLenLSB when we finish a sequence of RD_EN that read 1, 2, or 3 words.
// rCount + remainder
_rCount = rCount + ({2{(wAfterEnd & !wLenLast)}} & wLenLSB) - ({(rRen & rCount[2]), 2'd0}) - ({3{(wAfterEnd & wLenLast)}} & rCount);
_rCountHist = ((rCountHist<<3) | rCount);
// Track read enables in the pipeline.
_rRdEnHist = ((rRdEnHist<<1) | rRen);
_rFifoRdEnHist = ((rFifoRdEnHist<<1) | rFifoRdEn);
// Track delayed length last value
_rLenLastHist = ((rLenLastHist<<1) | wLenLast);
// Calculate the amount to shift out each RD_EN. This is always 4 unless it's
// the last RD_EN in the sequence and the read words length is 1, 2, or 3.
_rConsumedHist = ((rConsumedHist<<3) | wConsumed);
// Read from the FIFO unless we have 4 words cached.
_rFifoRdEn = (!rCount[2] & rRen);
// Buffer the FIFO data.
_rFifoData = wFifoData;
// Shift the buffered FIFO data into and the consumed data out of the output register.
if (rFifoRdEnHist[1])
_rData = ((rData>>({rConsumedHist[8:6], 5'd0})) | (rFifoData<<({rCountHist[7:6], 5'd0})));
else
_rData = (rData>>({rConsumedHist[8:6], 5'd0}));
end
// Buffer up to 4 length LSB values for use to detect unread data that was
// part of a consumed packet. Should only need 2. This is basically a FIFO.
always @ (posedge CLK) begin
rRdPtr <= #1 (RST ? 2'd0 : _rRdPtr);
rWrPtr <= #1 (RST ? 2'd0 : _rWrPtr);
rLenLSB0 <= #1 _rLenLSB0;
rLenLSB1 <= #1 _rLenLSB1;
rLenLast <= #1 _rLenLast;
end
always @ (*) begin
_rRdPtr = (wAfterEnd ? rRdPtr + 1'd1 : rRdPtr);
_rWrPtr = (rLenValid ? rWrPtr + 1'd1 : rWrPtr);
_rLenLSB0 = rLenLSB0;
_rLenLSB1 = rLenLSB1;
if(rLenValid)
{_rLenLSB1[rWrPtr], _rLenLSB0[rWrPtr]} = (~LEN_LSB + 1);
_rLenLast = rLenLast;
if(rLenValid)
_rLenLast[rWrPtr] = LEN_LAST;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/18/2016 03:28:31 PM
// Design Name:
// Module Name: Round_Sgf_Dec
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dep encies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Round_Sgf_Dec(
input wire [1:0] Data_i,
input wire [1:0] Round_Type_i,
input wire Sign_Result_i,
output reg Round_Flag_o
);
always @*
case ({Sign_Result_i,Round_Type_i,Data_i})
//Round type=00; Towards zero / No round
//Round type=01; Towards - infinity
//Round type=10; Towards + infinity
//Op=0;Round type=00
/*5'b00000: Round_Flag_o <=0;
5'b00001: Round_Flag_o <=0;
5'b00010: Round_Flag_o <=0;
5'b00011: Round_Flag_o <=0;*/
//Op=1;Round type=00
/*5'b10000: Round_Flag_o <=0;
5'b10001: Round_Flag_o <=0;
5'b10010: Round_Flag_o <=0;
5'b10011: Round_Flag_o <=0; */
//Op=0;Round type=01
/*5'b00100: Round_Flag_o <=0;
5'b00101: Round_Flag_o <=0;
5'b00110: Round_Flag_o <=0;
5'b00111: Round_Flag_o <=0; */
//Op=1;Round type=01
//5'b10100: Round_Flag_o <=0;
5'b10101: Round_Flag_o <=1;
5'b10110: Round_Flag_o <=1;
5'b10111: Round_Flag_o <=1;
//Op=0;Round type=10
//5'b01000: Round_Flag_o <=0;
5'b01001: Round_Flag_o <=1;
5'b01010: Round_Flag_o <=1;
5'b01011: Round_Flag_o <=1;
//Op=1;Round type=10
/*5'b11000: Round_Flag_o <=0;
5'b11001: Round_Flag_o <=0;
5'b11010: Round_Flag_o <=0;
5'b11011: Round_Flag_o <=0; */
default: Round_Flag_o <=0;
endcase
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_dqs_found_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling calibration logic
// NOTES:
// 1. Phaser_In DQSFOUND calibration
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
**$Date: 2011/06/02 08:35:08 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_dqs_found_cal_hr #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter nCL = 5, // Read CAS latency
parameter AL = "0",
parameter nCWL = 5, // Write CAS latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RANKS = 1, // # of memory ranks in the system
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
parameter N_CTL_LANES = 3, // Number of control byte lanes
parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
parameter HIGHEST_BANK = 3, // Sum of I/O Banks
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf
)
(
input clk,
input rst,
input dqsfound_retry,
// From phy_init
input pi_dqs_found_start,
input detect_pi_found_dqs,
input prech_done,
// DQSFOUND per Phaser_IN
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
// To phy_init
output [5:0] rd_data_offset_0,
output [5:0] rd_data_offset_1,
output [5:0] rd_data_offset_2,
output pi_dqs_found_rank_done,
output pi_dqs_found_done,
output reg pi_dqs_found_err,
output [6*RANKS-1:0] rd_data_offset_ranks_0,
output [6*RANKS-1:0] rd_data_offset_ranks_1,
output [6*RANKS-1:0] rd_data_offset_ranks_2,
output reg dqsfound_retry_done,
output reg dqs_found_prech_req,
//To MC
output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
input [8:0] po_counter_read_val,
output rd_data_offset_cal_done,
output fine_adjust_done,
output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
output reg ck_po_stg2_f_indec,
output reg ck_po_stg2_f_en,
output [255:0] dbg_dqs_found_cal
);
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Added to reduce simulation time
localparam LATENCY_FACTOR = 13;
localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
localparam FINE_ADJ_IDLE = 4'h0;
localparam RST_POSTWAIT = 4'h1;
localparam RST_POSTWAIT1 = 4'h2;
localparam RST_WAIT = 4'h3;
localparam FINE_ADJ_INIT = 4'h4;
localparam FINE_INC = 4'h5;
localparam FINE_INC_WAIT = 4'h6;
localparam FINE_INC_PREWAIT = 4'h7;
localparam DETECT_PREWAIT = 4'h8;
localparam DETECT_DQSFOUND = 4'h9;
localparam PRECH_WAIT = 4'hA;
localparam FINE_DEC = 4'hB;
localparam FINE_DEC_WAIT = 4'hC;
localparam FINE_DEC_PREWAIT = 4'hD;
localparam FINAL_WAIT = 4'hE;
localparam FINE_ADJ_DONE = 4'hF;
integer k,l,m,n,p,q,r,s;
reg dqs_found_start_r;
reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
reg rank_done_r;
reg rank_done_r1;
reg dqs_found_done_r;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
reg init_dqsfound_done_r;
reg init_dqsfound_done_r1;
reg init_dqsfound_done_r2;
reg init_dqsfound_done_r3;
reg init_dqsfound_done_r4;
reg init_dqsfound_done_r5;
reg [1:0] rnk_cnt_r;
reg [2:0 ] final_do_index[0:RANKS-1];
reg [5:0 ] final_do_max[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
reg [10*HIGHEST_BANK-1:0] retry_cnt;
reg dqsfound_retry_r1;
wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
// CK/Control byte lanes fine adjust stage
reg fine_adjust;
reg [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [3:0] fine_adj_state_r;
reg fine_adjust_done_r;
reg rst_dqs_find;
reg rst_dqs_find_r1;
reg rst_dqs_find_r2;
reg [5:0] init_dec_cnt;
reg [5:0] dec_cnt;
reg [5:0] inc_cnt;
reg final_dec_done;
reg init_dec_done;
reg first_fail_detect;
reg second_fail_detect;
reg [5:0] first_fail_taps;
reg [5:0] second_fail_taps;
reg [5:0] stable_pass_cnt;
reg [3:0] detect_rd_cnt;
//***************************************************************************
// Debug signals
//
//***************************************************************************
assign dbg_dqs_found_cal[5:0] = first_fail_taps;
assign dbg_dqs_found_cal[11:6] = second_fail_taps;
assign dbg_dqs_found_cal[12] = first_fail_detect;
assign dbg_dqs_found_cal[13] = second_fail_detect;
assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
assign pi_dqs_found_rank_done = rank_done_r;
assign pi_dqs_found_done = dqs_found_done_r;
generate
genvar rnk_cnt;
if (HIGHEST_BANK == 3) begin // Three Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
end
end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end else begin // Single Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end
endgenerate
// final_data_offset is used during write calibration and during
// normal operation. One rd_data_offset value per rank for entire
// interface
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
final_data_offset[rnk_cnt_r][12+:6];
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = 'd0;
end else begin
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = 'd0;
assign rd_data_offset_2 = 'd0;
end
endgenerate
assign rd_data_offset_cal_done = init_dqsfound_done_r;
assign fine_adjust_lane_cnt = ctl_lane_cnt;
//**************************************************************************
// DQSFOUND all and any generation
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
// asserted
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
// is asserted
//**************************************************************************
generate
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
end
end else if (pi_dqs_found_start) begin
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
end
end
end
always @(posedge clk) begin
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
end
//*****************************************************************************
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
// per CK/A/C tap value
//*****************************************************************************
always @(posedge clk) begin
if (rst || (detect_rd_cnt == 'd0))
detect_rd_cnt <= #TCQ NUM_READS;
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
end
//**************************************************************************
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
//
//**************************************************************************
assign fine_adjust_done = fine_adjust_done_r;
always @(posedge clk) begin
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
end
always @(posedge clk) begin
if(rst)begin
fine_adjust <= #TCQ 1'b0;
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
fine_adjust_done_r <= #TCQ 1'b0;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b0;
init_dec_cnt <= #TCQ 'd31;
dec_cnt <= #TCQ 'd0;
inc_cnt <= #TCQ 'd0;
init_dec_done <= #TCQ 1'b0;
final_dec_done <= #TCQ 1'b0;
first_fail_detect <= #TCQ 1'b0;
second_fail_detect <= #TCQ 1'b0;
first_fail_taps <= #TCQ 'd0;
second_fail_taps <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
dqs_found_prech_req<= #TCQ 1'b0;
end else begin
case (fine_adj_state_r)
FINE_ADJ_IDLE: begin
if (init_dqsfound_done_r5) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
rst_dqs_find <= #TCQ 1'b0;
end else begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
rst_dqs_find <= #TCQ 1'b1;
end
end
end
RST_WAIT: begin
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
rst_dqs_find <= #TCQ 1'b0;
if (|init_dec_cnt)
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else if (final_dec_done)
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
else
fine_adj_state_r <= #TCQ RST_POSTWAIT;
end
end
RST_POSTWAIT: begin
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
end
RST_POSTWAIT1: begin
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
end
FINE_ADJ_INIT: begin
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
fine_adj_state_r <= #TCQ FINE_INC;
end
FINE_INC: begin
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b1;
ck_po_stg2_f_en <= #TCQ 1'b1;
if (ctl_lane_cnt == N_CTL_LANES-1)
inc_cnt <= #TCQ inc_cnt + 1;
end
FINE_INC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
end
FINE_INC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_INC;
end
DETECT_PREWAIT: begin
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
else
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
DETECT_DQSFOUND: begin
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ 'd0;
if (~first_fail_detect && (inc_cnt == 'd63)) begin
// First failing tap detected at 63 taps
// then decrement to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
// First failing tap detected at greater than 30 taps
// then stop looking for second edge and decrement
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
// First failing tap detected, continue incrementing
// until either second failing tap detected or 63
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
// Consecutive 30 taps of passing region was not found
// continue incrementing
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
if (stable_pass_cnt < 'd30) begin
// Consecutive 30 taps of passing region was not found
// from tap 0 to 63 so decrement back to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else begin
// Consecutive 30 taps of passing region was found
// between first_fail_taps and 63
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end else begin
// Second failing tap detected, decrement to center of
// failing taps
second_fail_detect <= #TCQ 1'b1;
second_fail_taps <= #TCQ inc_cnt;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
fine_adj_state_r <= #TCQ FINE_DEC;
end
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else if (inc_cnt < 'd63) begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end else begin
fine_adj_state_r <= #TCQ FINE_DEC;
if (~first_fail_detect || (first_fail_taps > 'd33))
// No failing taps detected, decrement by 31
dec_cnt <= #TCQ 'd32;
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
// // First failing tap detected between 0 and 34
// // decrement midpoint between 63 and failing tap
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
else
// First failing tap detected
// decrement to midpoint between 63 and failing tap
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end
end
PRECH_WAIT: begin
if (prech_done) begin
dqs_found_prech_req <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
end
FINE_DEC: begin
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b1;
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
init_dec_cnt <= #TCQ init_dec_cnt - 1;
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
dec_cnt <= #TCQ dec_cnt - 1;
end
FINE_DEC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else begin
fine_adj_state_r <= #TCQ FINAL_WAIT;
if ((init_dec_cnt == 'd0) && ~init_dec_done)
init_dec_done <= #TCQ 1'b1;
else
final_dec_done <= #TCQ 1'b1;
end
end
end
FINE_DEC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_DEC;
end
FINAL_WAIT: begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
FINE_ADJ_DONE: begin
if (&pi_dqs_found_all_bank) begin
fine_adjust_done_r <= #TCQ 1'b1;
rst_dqs_find <= #TCQ 1'b0;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
end
end
endcase
end
end
//*****************************************************************************
always@(posedge clk)
dqs_found_start_r <= #TCQ pi_dqs_found_start;
always @(posedge clk) begin
if (rst)
rnk_cnt_r <= #TCQ 2'b00;
else if (init_dqsfound_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r;
else if (rank_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
end
//*****************************************************************
// Read data_offset calibration done signal
//*****************************************************************
always @(posedge clk) begin
if (rst || (|pi_rst_stg1_cal_r))
init_dqsfound_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank) begin
if (rnk_cnt_r == RANKS-1)
init_dqsfound_done_r <= #TCQ 1'b1;
else
init_dqsfound_done_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst ||
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
rank_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
rank_done_r <= #TCQ 1'b1;
else
rank_done_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
rank_done_r1 <= #TCQ rank_done_r;
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
end
always @(posedge clk) begin
if (rst)
dqs_found_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
(fine_adj_state_r == FINE_ADJ_DONE))
dqs_found_done_r <= #TCQ 1'b1;
else
dqs_found_done_r <= #TCQ 1'b0;
end
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[2]) ||
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[20+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[2])
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
else
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
//(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][12+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] + 1;
end
//*****************************************************************************
// Two I/O Bank Interface
//*****************************************************************************
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
//*****************************************************************************
// One I/O Bank Interface
//*****************************************************************************
end else begin // One I/O Bank Interface
// Read data offset value for all DQS in Bank0
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
rd_byte_data_offset[l] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r]
<= #TCQ rd_byte_data_offset[rnk_cnt_r] + 1;
end
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted even with 3 dqfound retries
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk) begin
if (rst)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
else if (rst_dqs_find)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
else
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
end
// Final read data offset value to be used during write calibration and
// normal operation
generate
genvar i;
genvar j;
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
reg [5:0] final_do_cand [RANKS-1:0];
// combinatorially select the candidate offset for the bank
// indexed by final_do_index
if (HIGHEST_BANK == 3) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
default: final_do_cand[i] = 'd0;
endcase
end
end else if (HIGHEST_BANK == 2) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end else begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = 'd0;
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end
always @(posedge clk or posedge rst) begin
if (rst)
final_do_max[i] <= #TCQ 0;
else begin
final_do_max[i] <= #TCQ final_do_max[i]; // default
case (final_do_index[i])
3'b000: if ( | DATA_PRESENT[3:0])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b001: if ( | DATA_PRESENT[7:4])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b010: if ( | DATA_PRESENT[11:8])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
default:
final_do_max[i] <= #TCQ final_do_max[i];
endcase
end
end
always @(posedge clk)
if (rst) begin
final_do_index[i] <= #TCQ 0;
end
else begin
final_do_index[i] <= #TCQ final_do_index[i] + 1;
end
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
always @(posedge clk) begin
if (rst) begin
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
end
else begin
//if (dqsfound_retry[j])
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
//else
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
if (CWL_M % 2) // odd latency CAS slot 1
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
else // even latency CAS slot 0
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
end
end
else if (init_dqsfound_done_r5 ) begin
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
end
end
end
end
end
end
endgenerate
// Error generation in case pi_found_dqs signal from Phaser_IN
// is not asserted when a common rddata_offset value is used
always @(posedge clk) begin
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_dqs_found_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling calibration logic
// NOTES:
// 1. Phaser_In DQSFOUND calibration
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
**$Date: 2011/06/02 08:35:08 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_dqs_found_cal_hr #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter nCL = 5, // Read CAS latency
parameter AL = "0",
parameter nCWL = 5, // Write CAS latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RANKS = 1, // # of memory ranks in the system
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
parameter N_CTL_LANES = 3, // Number of control byte lanes
parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
parameter HIGHEST_BANK = 3, // Sum of I/O Banks
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf
)
(
input clk,
input rst,
input dqsfound_retry,
// From phy_init
input pi_dqs_found_start,
input detect_pi_found_dqs,
input prech_done,
// DQSFOUND per Phaser_IN
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
// To phy_init
output [5:0] rd_data_offset_0,
output [5:0] rd_data_offset_1,
output [5:0] rd_data_offset_2,
output pi_dqs_found_rank_done,
output pi_dqs_found_done,
output reg pi_dqs_found_err,
output [6*RANKS-1:0] rd_data_offset_ranks_0,
output [6*RANKS-1:0] rd_data_offset_ranks_1,
output [6*RANKS-1:0] rd_data_offset_ranks_2,
output reg dqsfound_retry_done,
output reg dqs_found_prech_req,
//To MC
output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
input [8:0] po_counter_read_val,
output rd_data_offset_cal_done,
output fine_adjust_done,
output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
output reg ck_po_stg2_f_indec,
output reg ck_po_stg2_f_en,
output [255:0] dbg_dqs_found_cal
);
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Added to reduce simulation time
localparam LATENCY_FACTOR = 13;
localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
localparam FINE_ADJ_IDLE = 4'h0;
localparam RST_POSTWAIT = 4'h1;
localparam RST_POSTWAIT1 = 4'h2;
localparam RST_WAIT = 4'h3;
localparam FINE_ADJ_INIT = 4'h4;
localparam FINE_INC = 4'h5;
localparam FINE_INC_WAIT = 4'h6;
localparam FINE_INC_PREWAIT = 4'h7;
localparam DETECT_PREWAIT = 4'h8;
localparam DETECT_DQSFOUND = 4'h9;
localparam PRECH_WAIT = 4'hA;
localparam FINE_DEC = 4'hB;
localparam FINE_DEC_WAIT = 4'hC;
localparam FINE_DEC_PREWAIT = 4'hD;
localparam FINAL_WAIT = 4'hE;
localparam FINE_ADJ_DONE = 4'hF;
integer k,l,m,n,p,q,r,s;
reg dqs_found_start_r;
reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
reg rank_done_r;
reg rank_done_r1;
reg dqs_found_done_r;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
reg init_dqsfound_done_r;
reg init_dqsfound_done_r1;
reg init_dqsfound_done_r2;
reg init_dqsfound_done_r3;
reg init_dqsfound_done_r4;
reg init_dqsfound_done_r5;
reg [1:0] rnk_cnt_r;
reg [2:0 ] final_do_index[0:RANKS-1];
reg [5:0 ] final_do_max[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
reg [10*HIGHEST_BANK-1:0] retry_cnt;
reg dqsfound_retry_r1;
wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
// CK/Control byte lanes fine adjust stage
reg fine_adjust;
reg [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [3:0] fine_adj_state_r;
reg fine_adjust_done_r;
reg rst_dqs_find;
reg rst_dqs_find_r1;
reg rst_dqs_find_r2;
reg [5:0] init_dec_cnt;
reg [5:0] dec_cnt;
reg [5:0] inc_cnt;
reg final_dec_done;
reg init_dec_done;
reg first_fail_detect;
reg second_fail_detect;
reg [5:0] first_fail_taps;
reg [5:0] second_fail_taps;
reg [5:0] stable_pass_cnt;
reg [3:0] detect_rd_cnt;
//***************************************************************************
// Debug signals
//
//***************************************************************************
assign dbg_dqs_found_cal[5:0] = first_fail_taps;
assign dbg_dqs_found_cal[11:6] = second_fail_taps;
assign dbg_dqs_found_cal[12] = first_fail_detect;
assign dbg_dqs_found_cal[13] = second_fail_detect;
assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
assign pi_dqs_found_rank_done = rank_done_r;
assign pi_dqs_found_done = dqs_found_done_r;
generate
genvar rnk_cnt;
if (HIGHEST_BANK == 3) begin // Three Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
end
end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end else begin // Single Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end
endgenerate
// final_data_offset is used during write calibration and during
// normal operation. One rd_data_offset value per rank for entire
// interface
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
final_data_offset[rnk_cnt_r][12+:6];
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = 'd0;
end else begin
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = 'd0;
assign rd_data_offset_2 = 'd0;
end
endgenerate
assign rd_data_offset_cal_done = init_dqsfound_done_r;
assign fine_adjust_lane_cnt = ctl_lane_cnt;
//**************************************************************************
// DQSFOUND all and any generation
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
// asserted
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
// is asserted
//**************************************************************************
generate
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
end
end else if (pi_dqs_found_start) begin
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
end
end
end
always @(posedge clk) begin
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
end
//*****************************************************************************
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
// per CK/A/C tap value
//*****************************************************************************
always @(posedge clk) begin
if (rst || (detect_rd_cnt == 'd0))
detect_rd_cnt <= #TCQ NUM_READS;
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
end
//**************************************************************************
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
//
//**************************************************************************
assign fine_adjust_done = fine_adjust_done_r;
always @(posedge clk) begin
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
end
always @(posedge clk) begin
if(rst)begin
fine_adjust <= #TCQ 1'b0;
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
fine_adjust_done_r <= #TCQ 1'b0;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b0;
init_dec_cnt <= #TCQ 'd31;
dec_cnt <= #TCQ 'd0;
inc_cnt <= #TCQ 'd0;
init_dec_done <= #TCQ 1'b0;
final_dec_done <= #TCQ 1'b0;
first_fail_detect <= #TCQ 1'b0;
second_fail_detect <= #TCQ 1'b0;
first_fail_taps <= #TCQ 'd0;
second_fail_taps <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
dqs_found_prech_req<= #TCQ 1'b0;
end else begin
case (fine_adj_state_r)
FINE_ADJ_IDLE: begin
if (init_dqsfound_done_r5) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
rst_dqs_find <= #TCQ 1'b0;
end else begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
rst_dqs_find <= #TCQ 1'b1;
end
end
end
RST_WAIT: begin
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
rst_dqs_find <= #TCQ 1'b0;
if (|init_dec_cnt)
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else if (final_dec_done)
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
else
fine_adj_state_r <= #TCQ RST_POSTWAIT;
end
end
RST_POSTWAIT: begin
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
end
RST_POSTWAIT1: begin
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
end
FINE_ADJ_INIT: begin
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
fine_adj_state_r <= #TCQ FINE_INC;
end
FINE_INC: begin
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b1;
ck_po_stg2_f_en <= #TCQ 1'b1;
if (ctl_lane_cnt == N_CTL_LANES-1)
inc_cnt <= #TCQ inc_cnt + 1;
end
FINE_INC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
end
FINE_INC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_INC;
end
DETECT_PREWAIT: begin
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
else
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
DETECT_DQSFOUND: begin
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ 'd0;
if (~first_fail_detect && (inc_cnt == 'd63)) begin
// First failing tap detected at 63 taps
// then decrement to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
// First failing tap detected at greater than 30 taps
// then stop looking for second edge and decrement
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
// First failing tap detected, continue incrementing
// until either second failing tap detected or 63
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
// Consecutive 30 taps of passing region was not found
// continue incrementing
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
if (stable_pass_cnt < 'd30) begin
// Consecutive 30 taps of passing region was not found
// from tap 0 to 63 so decrement back to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else begin
// Consecutive 30 taps of passing region was found
// between first_fail_taps and 63
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end else begin
// Second failing tap detected, decrement to center of
// failing taps
second_fail_detect <= #TCQ 1'b1;
second_fail_taps <= #TCQ inc_cnt;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
fine_adj_state_r <= #TCQ FINE_DEC;
end
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else if (inc_cnt < 'd63) begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end else begin
fine_adj_state_r <= #TCQ FINE_DEC;
if (~first_fail_detect || (first_fail_taps > 'd33))
// No failing taps detected, decrement by 31
dec_cnt <= #TCQ 'd32;
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
// // First failing tap detected between 0 and 34
// // decrement midpoint between 63 and failing tap
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
else
// First failing tap detected
// decrement to midpoint between 63 and failing tap
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end
end
PRECH_WAIT: begin
if (prech_done) begin
dqs_found_prech_req <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
end
FINE_DEC: begin
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b1;
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
init_dec_cnt <= #TCQ init_dec_cnt - 1;
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
dec_cnt <= #TCQ dec_cnt - 1;
end
FINE_DEC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else begin
fine_adj_state_r <= #TCQ FINAL_WAIT;
if ((init_dec_cnt == 'd0) && ~init_dec_done)
init_dec_done <= #TCQ 1'b1;
else
final_dec_done <= #TCQ 1'b1;
end
end
end
FINE_DEC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_DEC;
end
FINAL_WAIT: begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
FINE_ADJ_DONE: begin
if (&pi_dqs_found_all_bank) begin
fine_adjust_done_r <= #TCQ 1'b1;
rst_dqs_find <= #TCQ 1'b0;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
end
end
endcase
end
end
//*****************************************************************************
always@(posedge clk)
dqs_found_start_r <= #TCQ pi_dqs_found_start;
always @(posedge clk) begin
if (rst)
rnk_cnt_r <= #TCQ 2'b00;
else if (init_dqsfound_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r;
else if (rank_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
end
//*****************************************************************
// Read data_offset calibration done signal
//*****************************************************************
always @(posedge clk) begin
if (rst || (|pi_rst_stg1_cal_r))
init_dqsfound_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank) begin
if (rnk_cnt_r == RANKS-1)
init_dqsfound_done_r <= #TCQ 1'b1;
else
init_dqsfound_done_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst ||
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
rank_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
rank_done_r <= #TCQ 1'b1;
else
rank_done_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
rank_done_r1 <= #TCQ rank_done_r;
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
end
always @(posedge clk) begin
if (rst)
dqs_found_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
(fine_adj_state_r == FINE_ADJ_DONE))
dqs_found_done_r <= #TCQ 1'b1;
else
dqs_found_done_r <= #TCQ 1'b0;
end
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[2]) ||
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[20+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[2])
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
else
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
//(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][12+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] + 1;
end
//*****************************************************************************
// Two I/O Bank Interface
//*****************************************************************************
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
//*****************************************************************************
// One I/O Bank Interface
//*****************************************************************************
end else begin // One I/O Bank Interface
// Read data offset value for all DQS in Bank0
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
rd_byte_data_offset[l] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r]
<= #TCQ rd_byte_data_offset[rnk_cnt_r] + 1;
end
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted even with 3 dqfound retries
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk) begin
if (rst)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
else if (rst_dqs_find)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
else
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
end
// Final read data offset value to be used during write calibration and
// normal operation
generate
genvar i;
genvar j;
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
reg [5:0] final_do_cand [RANKS-1:0];
// combinatorially select the candidate offset for the bank
// indexed by final_do_index
if (HIGHEST_BANK == 3) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
default: final_do_cand[i] = 'd0;
endcase
end
end else if (HIGHEST_BANK == 2) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end else begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = 'd0;
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end
always @(posedge clk or posedge rst) begin
if (rst)
final_do_max[i] <= #TCQ 0;
else begin
final_do_max[i] <= #TCQ final_do_max[i]; // default
case (final_do_index[i])
3'b000: if ( | DATA_PRESENT[3:0])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b001: if ( | DATA_PRESENT[7:4])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b010: if ( | DATA_PRESENT[11:8])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
default:
final_do_max[i] <= #TCQ final_do_max[i];
endcase
end
end
always @(posedge clk)
if (rst) begin
final_do_index[i] <= #TCQ 0;
end
else begin
final_do_index[i] <= #TCQ final_do_index[i] + 1;
end
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
always @(posedge clk) begin
if (rst) begin
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
end
else begin
//if (dqsfound_retry[j])
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
//else
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
if (CWL_M % 2) // odd latency CAS slot 1
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
else // even latency CAS slot 0
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
end
end
else if (init_dqsfound_done_r5 ) begin
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
end
end
end
end
end
end
endgenerate
// Error generation in case pi_found_dqs signal from Phaser_IN
// is not asserted when a common rddata_offset value is used
always @(posedge clk) begin
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_dqs_found_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling calibration logic
// NOTES:
// 1. Phaser_In DQSFOUND calibration
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
**$Date: 2011/06/02 08:35:08 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_dqs_found_cal_hr #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter nCL = 5, // Read CAS latency
parameter AL = "0",
parameter nCWL = 5, // Write CAS latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RANKS = 1, // # of memory ranks in the system
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
parameter N_CTL_LANES = 3, // Number of control byte lanes
parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
parameter HIGHEST_BANK = 3, // Sum of I/O Banks
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf
)
(
input clk,
input rst,
input dqsfound_retry,
// From phy_init
input pi_dqs_found_start,
input detect_pi_found_dqs,
input prech_done,
// DQSFOUND per Phaser_IN
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
// To phy_init
output [5:0] rd_data_offset_0,
output [5:0] rd_data_offset_1,
output [5:0] rd_data_offset_2,
output pi_dqs_found_rank_done,
output pi_dqs_found_done,
output reg pi_dqs_found_err,
output [6*RANKS-1:0] rd_data_offset_ranks_0,
output [6*RANKS-1:0] rd_data_offset_ranks_1,
output [6*RANKS-1:0] rd_data_offset_ranks_2,
output reg dqsfound_retry_done,
output reg dqs_found_prech_req,
//To MC
output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
input [8:0] po_counter_read_val,
output rd_data_offset_cal_done,
output fine_adjust_done,
output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
output reg ck_po_stg2_f_indec,
output reg ck_po_stg2_f_en,
output [255:0] dbg_dqs_found_cal
);
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Added to reduce simulation time
localparam LATENCY_FACTOR = 13;
localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
localparam FINE_ADJ_IDLE = 4'h0;
localparam RST_POSTWAIT = 4'h1;
localparam RST_POSTWAIT1 = 4'h2;
localparam RST_WAIT = 4'h3;
localparam FINE_ADJ_INIT = 4'h4;
localparam FINE_INC = 4'h5;
localparam FINE_INC_WAIT = 4'h6;
localparam FINE_INC_PREWAIT = 4'h7;
localparam DETECT_PREWAIT = 4'h8;
localparam DETECT_DQSFOUND = 4'h9;
localparam PRECH_WAIT = 4'hA;
localparam FINE_DEC = 4'hB;
localparam FINE_DEC_WAIT = 4'hC;
localparam FINE_DEC_PREWAIT = 4'hD;
localparam FINAL_WAIT = 4'hE;
localparam FINE_ADJ_DONE = 4'hF;
integer k,l,m,n,p,q,r,s;
reg dqs_found_start_r;
reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
reg rank_done_r;
reg rank_done_r1;
reg dqs_found_done_r;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
reg init_dqsfound_done_r;
reg init_dqsfound_done_r1;
reg init_dqsfound_done_r2;
reg init_dqsfound_done_r3;
reg init_dqsfound_done_r4;
reg init_dqsfound_done_r5;
reg [1:0] rnk_cnt_r;
reg [2:0 ] final_do_index[0:RANKS-1];
reg [5:0 ] final_do_max[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
reg [10*HIGHEST_BANK-1:0] retry_cnt;
reg dqsfound_retry_r1;
wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
// CK/Control byte lanes fine adjust stage
reg fine_adjust;
reg [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [3:0] fine_adj_state_r;
reg fine_adjust_done_r;
reg rst_dqs_find;
reg rst_dqs_find_r1;
reg rst_dqs_find_r2;
reg [5:0] init_dec_cnt;
reg [5:0] dec_cnt;
reg [5:0] inc_cnt;
reg final_dec_done;
reg init_dec_done;
reg first_fail_detect;
reg second_fail_detect;
reg [5:0] first_fail_taps;
reg [5:0] second_fail_taps;
reg [5:0] stable_pass_cnt;
reg [3:0] detect_rd_cnt;
//***************************************************************************
// Debug signals
//
//***************************************************************************
assign dbg_dqs_found_cal[5:0] = first_fail_taps;
assign dbg_dqs_found_cal[11:6] = second_fail_taps;
assign dbg_dqs_found_cal[12] = first_fail_detect;
assign dbg_dqs_found_cal[13] = second_fail_detect;
assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
assign pi_dqs_found_rank_done = rank_done_r;
assign pi_dqs_found_done = dqs_found_done_r;
generate
genvar rnk_cnt;
if (HIGHEST_BANK == 3) begin // Three Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
end
end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end else begin // Single Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end
endgenerate
// final_data_offset is used during write calibration and during
// normal operation. One rd_data_offset value per rank for entire
// interface
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
final_data_offset[rnk_cnt_r][12+:6];
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = 'd0;
end else begin
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = 'd0;
assign rd_data_offset_2 = 'd0;
end
endgenerate
assign rd_data_offset_cal_done = init_dqsfound_done_r;
assign fine_adjust_lane_cnt = ctl_lane_cnt;
//**************************************************************************
// DQSFOUND all and any generation
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
// asserted
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
// is asserted
//**************************************************************************
generate
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
end
end else if (pi_dqs_found_start) begin
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
end
end
end
always @(posedge clk) begin
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
end
//*****************************************************************************
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
// per CK/A/C tap value
//*****************************************************************************
always @(posedge clk) begin
if (rst || (detect_rd_cnt == 'd0))
detect_rd_cnt <= #TCQ NUM_READS;
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
end
//**************************************************************************
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
//
//**************************************************************************
assign fine_adjust_done = fine_adjust_done_r;
always @(posedge clk) begin
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
end
always @(posedge clk) begin
if(rst)begin
fine_adjust <= #TCQ 1'b0;
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
fine_adjust_done_r <= #TCQ 1'b0;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b0;
init_dec_cnt <= #TCQ 'd31;
dec_cnt <= #TCQ 'd0;
inc_cnt <= #TCQ 'd0;
init_dec_done <= #TCQ 1'b0;
final_dec_done <= #TCQ 1'b0;
first_fail_detect <= #TCQ 1'b0;
second_fail_detect <= #TCQ 1'b0;
first_fail_taps <= #TCQ 'd0;
second_fail_taps <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
dqs_found_prech_req<= #TCQ 1'b0;
end else begin
case (fine_adj_state_r)
FINE_ADJ_IDLE: begin
if (init_dqsfound_done_r5) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
rst_dqs_find <= #TCQ 1'b0;
end else begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
rst_dqs_find <= #TCQ 1'b1;
end
end
end
RST_WAIT: begin
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
rst_dqs_find <= #TCQ 1'b0;
if (|init_dec_cnt)
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else if (final_dec_done)
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
else
fine_adj_state_r <= #TCQ RST_POSTWAIT;
end
end
RST_POSTWAIT: begin
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
end
RST_POSTWAIT1: begin
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
end
FINE_ADJ_INIT: begin
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
fine_adj_state_r <= #TCQ FINE_INC;
end
FINE_INC: begin
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b1;
ck_po_stg2_f_en <= #TCQ 1'b1;
if (ctl_lane_cnt == N_CTL_LANES-1)
inc_cnt <= #TCQ inc_cnt + 1;
end
FINE_INC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
end
FINE_INC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_INC;
end
DETECT_PREWAIT: begin
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
else
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
DETECT_DQSFOUND: begin
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ 'd0;
if (~first_fail_detect && (inc_cnt == 'd63)) begin
// First failing tap detected at 63 taps
// then decrement to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
// First failing tap detected at greater than 30 taps
// then stop looking for second edge and decrement
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
// First failing tap detected, continue incrementing
// until either second failing tap detected or 63
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
// Consecutive 30 taps of passing region was not found
// continue incrementing
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
if (stable_pass_cnt < 'd30) begin
// Consecutive 30 taps of passing region was not found
// from tap 0 to 63 so decrement back to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else begin
// Consecutive 30 taps of passing region was found
// between first_fail_taps and 63
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end else begin
// Second failing tap detected, decrement to center of
// failing taps
second_fail_detect <= #TCQ 1'b1;
second_fail_taps <= #TCQ inc_cnt;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
fine_adj_state_r <= #TCQ FINE_DEC;
end
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else if (inc_cnt < 'd63) begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end else begin
fine_adj_state_r <= #TCQ FINE_DEC;
if (~first_fail_detect || (first_fail_taps > 'd33))
// No failing taps detected, decrement by 31
dec_cnt <= #TCQ 'd32;
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
// // First failing tap detected between 0 and 34
// // decrement midpoint between 63 and failing tap
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
else
// First failing tap detected
// decrement to midpoint between 63 and failing tap
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end
end
PRECH_WAIT: begin
if (prech_done) begin
dqs_found_prech_req <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
end
FINE_DEC: begin
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b1;
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
init_dec_cnt <= #TCQ init_dec_cnt - 1;
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
dec_cnt <= #TCQ dec_cnt - 1;
end
FINE_DEC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else begin
fine_adj_state_r <= #TCQ FINAL_WAIT;
if ((init_dec_cnt == 'd0) && ~init_dec_done)
init_dec_done <= #TCQ 1'b1;
else
final_dec_done <= #TCQ 1'b1;
end
end
end
FINE_DEC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_DEC;
end
FINAL_WAIT: begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
FINE_ADJ_DONE: begin
if (&pi_dqs_found_all_bank) begin
fine_adjust_done_r <= #TCQ 1'b1;
rst_dqs_find <= #TCQ 1'b0;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
end
end
endcase
end
end
//*****************************************************************************
always@(posedge clk)
dqs_found_start_r <= #TCQ pi_dqs_found_start;
always @(posedge clk) begin
if (rst)
rnk_cnt_r <= #TCQ 2'b00;
else if (init_dqsfound_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r;
else if (rank_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
end
//*****************************************************************
// Read data_offset calibration done signal
//*****************************************************************
always @(posedge clk) begin
if (rst || (|pi_rst_stg1_cal_r))
init_dqsfound_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank) begin
if (rnk_cnt_r == RANKS-1)
init_dqsfound_done_r <= #TCQ 1'b1;
else
init_dqsfound_done_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst ||
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
rank_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
rank_done_r <= #TCQ 1'b1;
else
rank_done_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
rank_done_r1 <= #TCQ rank_done_r;
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
end
always @(posedge clk) begin
if (rst)
dqs_found_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
(fine_adj_state_r == FINE_ADJ_DONE))
dqs_found_done_r <= #TCQ 1'b1;
else
dqs_found_done_r <= #TCQ 1'b0;
end
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[2]) ||
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[20+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[2])
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
else
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
//(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][12+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] + 1;
end
//*****************************************************************************
// Two I/O Bank Interface
//*****************************************************************************
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
//*****************************************************************************
// One I/O Bank Interface
//*****************************************************************************
end else begin // One I/O Bank Interface
// Read data offset value for all DQS in Bank0
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
rd_byte_data_offset[l] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r]
<= #TCQ rd_byte_data_offset[rnk_cnt_r] + 1;
end
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted even with 3 dqfound retries
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk) begin
if (rst)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
else if (rst_dqs_find)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
else
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
end
// Final read data offset value to be used during write calibration and
// normal operation
generate
genvar i;
genvar j;
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
reg [5:0] final_do_cand [RANKS-1:0];
// combinatorially select the candidate offset for the bank
// indexed by final_do_index
if (HIGHEST_BANK == 3) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
default: final_do_cand[i] = 'd0;
endcase
end
end else if (HIGHEST_BANK == 2) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end else begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = 'd0;
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end
always @(posedge clk or posedge rst) begin
if (rst)
final_do_max[i] <= #TCQ 0;
else begin
final_do_max[i] <= #TCQ final_do_max[i]; // default
case (final_do_index[i])
3'b000: if ( | DATA_PRESENT[3:0])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b001: if ( | DATA_PRESENT[7:4])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b010: if ( | DATA_PRESENT[11:8])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
default:
final_do_max[i] <= #TCQ final_do_max[i];
endcase
end
end
always @(posedge clk)
if (rst) begin
final_do_index[i] <= #TCQ 0;
end
else begin
final_do_index[i] <= #TCQ final_do_index[i] + 1;
end
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
always @(posedge clk) begin
if (rst) begin
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
end
else begin
//if (dqsfound_retry[j])
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
//else
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
if (CWL_M % 2) // odd latency CAS slot 1
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
else // even latency CAS slot 0
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
end
end
else if (init_dqsfound_done_r5 ) begin
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
end
end
end
end
end
end
endgenerate
// Error generation in case pi_found_dqs signal from Phaser_IN
// is not asserted when a common rddata_offset value is used
always @(posedge clk) begin
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_dqs_found_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling calibration logic
// NOTES:
// 1. Phaser_In DQSFOUND calibration
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
**$Date: 2011/06/02 08:35:08 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_dqs_found_cal_hr #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter nCL = 5, // Read CAS latency
parameter AL = "0",
parameter nCWL = 5, // Write CAS latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RANKS = 1, // # of memory ranks in the system
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
parameter N_CTL_LANES = 3, // Number of control byte lanes
parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
parameter HIGHEST_BANK = 3, // Sum of I/O Banks
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf
)
(
input clk,
input rst,
input dqsfound_retry,
// From phy_init
input pi_dqs_found_start,
input detect_pi_found_dqs,
input prech_done,
// DQSFOUND per Phaser_IN
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
// To phy_init
output [5:0] rd_data_offset_0,
output [5:0] rd_data_offset_1,
output [5:0] rd_data_offset_2,
output pi_dqs_found_rank_done,
output pi_dqs_found_done,
output reg pi_dqs_found_err,
output [6*RANKS-1:0] rd_data_offset_ranks_0,
output [6*RANKS-1:0] rd_data_offset_ranks_1,
output [6*RANKS-1:0] rd_data_offset_ranks_2,
output reg dqsfound_retry_done,
output reg dqs_found_prech_req,
//To MC
output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
input [8:0] po_counter_read_val,
output rd_data_offset_cal_done,
output fine_adjust_done,
output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
output reg ck_po_stg2_f_indec,
output reg ck_po_stg2_f_en,
output [255:0] dbg_dqs_found_cal
);
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Added to reduce simulation time
localparam LATENCY_FACTOR = 13;
localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
localparam FINE_ADJ_IDLE = 4'h0;
localparam RST_POSTWAIT = 4'h1;
localparam RST_POSTWAIT1 = 4'h2;
localparam RST_WAIT = 4'h3;
localparam FINE_ADJ_INIT = 4'h4;
localparam FINE_INC = 4'h5;
localparam FINE_INC_WAIT = 4'h6;
localparam FINE_INC_PREWAIT = 4'h7;
localparam DETECT_PREWAIT = 4'h8;
localparam DETECT_DQSFOUND = 4'h9;
localparam PRECH_WAIT = 4'hA;
localparam FINE_DEC = 4'hB;
localparam FINE_DEC_WAIT = 4'hC;
localparam FINE_DEC_PREWAIT = 4'hD;
localparam FINAL_WAIT = 4'hE;
localparam FINE_ADJ_DONE = 4'hF;
integer k,l,m,n,p,q,r,s;
reg dqs_found_start_r;
reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
reg rank_done_r;
reg rank_done_r1;
reg dqs_found_done_r;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
reg init_dqsfound_done_r;
reg init_dqsfound_done_r1;
reg init_dqsfound_done_r2;
reg init_dqsfound_done_r3;
reg init_dqsfound_done_r4;
reg init_dqsfound_done_r5;
reg [1:0] rnk_cnt_r;
reg [2:0 ] final_do_index[0:RANKS-1];
reg [5:0 ] final_do_max[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
reg [10*HIGHEST_BANK-1:0] retry_cnt;
reg dqsfound_retry_r1;
wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
// CK/Control byte lanes fine adjust stage
reg fine_adjust;
reg [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [3:0] fine_adj_state_r;
reg fine_adjust_done_r;
reg rst_dqs_find;
reg rst_dqs_find_r1;
reg rst_dqs_find_r2;
reg [5:0] init_dec_cnt;
reg [5:0] dec_cnt;
reg [5:0] inc_cnt;
reg final_dec_done;
reg init_dec_done;
reg first_fail_detect;
reg second_fail_detect;
reg [5:0] first_fail_taps;
reg [5:0] second_fail_taps;
reg [5:0] stable_pass_cnt;
reg [3:0] detect_rd_cnt;
//***************************************************************************
// Debug signals
//
//***************************************************************************
assign dbg_dqs_found_cal[5:0] = first_fail_taps;
assign dbg_dqs_found_cal[11:6] = second_fail_taps;
assign dbg_dqs_found_cal[12] = first_fail_detect;
assign dbg_dqs_found_cal[13] = second_fail_detect;
assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
assign pi_dqs_found_rank_done = rank_done_r;
assign pi_dqs_found_done = dqs_found_done_r;
generate
genvar rnk_cnt;
if (HIGHEST_BANK == 3) begin // Three Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
end
end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end else begin // Single Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end
endgenerate
// final_data_offset is used during write calibration and during
// normal operation. One rd_data_offset value per rank for entire
// interface
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
final_data_offset[rnk_cnt_r][12+:6];
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = 'd0;
end else begin
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = 'd0;
assign rd_data_offset_2 = 'd0;
end
endgenerate
assign rd_data_offset_cal_done = init_dqsfound_done_r;
assign fine_adjust_lane_cnt = ctl_lane_cnt;
//**************************************************************************
// DQSFOUND all and any generation
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
// asserted
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
// is asserted
//**************************************************************************
generate
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
end
end else if (pi_dqs_found_start) begin
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
end
end
end
always @(posedge clk) begin
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
end
//*****************************************************************************
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
// per CK/A/C tap value
//*****************************************************************************
always @(posedge clk) begin
if (rst || (detect_rd_cnt == 'd0))
detect_rd_cnt <= #TCQ NUM_READS;
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
end
//**************************************************************************
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
//
//**************************************************************************
assign fine_adjust_done = fine_adjust_done_r;
always @(posedge clk) begin
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
end
always @(posedge clk) begin
if(rst)begin
fine_adjust <= #TCQ 1'b0;
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
fine_adjust_done_r <= #TCQ 1'b0;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b0;
init_dec_cnt <= #TCQ 'd31;
dec_cnt <= #TCQ 'd0;
inc_cnt <= #TCQ 'd0;
init_dec_done <= #TCQ 1'b0;
final_dec_done <= #TCQ 1'b0;
first_fail_detect <= #TCQ 1'b0;
second_fail_detect <= #TCQ 1'b0;
first_fail_taps <= #TCQ 'd0;
second_fail_taps <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
dqs_found_prech_req<= #TCQ 1'b0;
end else begin
case (fine_adj_state_r)
FINE_ADJ_IDLE: begin
if (init_dqsfound_done_r5) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
rst_dqs_find <= #TCQ 1'b0;
end else begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
rst_dqs_find <= #TCQ 1'b1;
end
end
end
RST_WAIT: begin
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
rst_dqs_find <= #TCQ 1'b0;
if (|init_dec_cnt)
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else if (final_dec_done)
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
else
fine_adj_state_r <= #TCQ RST_POSTWAIT;
end
end
RST_POSTWAIT: begin
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
end
RST_POSTWAIT1: begin
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
end
FINE_ADJ_INIT: begin
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
fine_adj_state_r <= #TCQ FINE_INC;
end
FINE_INC: begin
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b1;
ck_po_stg2_f_en <= #TCQ 1'b1;
if (ctl_lane_cnt == N_CTL_LANES-1)
inc_cnt <= #TCQ inc_cnt + 1;
end
FINE_INC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
end
FINE_INC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_INC;
end
DETECT_PREWAIT: begin
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
else
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
DETECT_DQSFOUND: begin
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ 'd0;
if (~first_fail_detect && (inc_cnt == 'd63)) begin
// First failing tap detected at 63 taps
// then decrement to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
// First failing tap detected at greater than 30 taps
// then stop looking for second edge and decrement
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
// First failing tap detected, continue incrementing
// until either second failing tap detected or 63
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
// Consecutive 30 taps of passing region was not found
// continue incrementing
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
if (stable_pass_cnt < 'd30) begin
// Consecutive 30 taps of passing region was not found
// from tap 0 to 63 so decrement back to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else begin
// Consecutive 30 taps of passing region was found
// between first_fail_taps and 63
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end else begin
// Second failing tap detected, decrement to center of
// failing taps
second_fail_detect <= #TCQ 1'b1;
second_fail_taps <= #TCQ inc_cnt;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
fine_adj_state_r <= #TCQ FINE_DEC;
end
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else if (inc_cnt < 'd63) begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end else begin
fine_adj_state_r <= #TCQ FINE_DEC;
if (~first_fail_detect || (first_fail_taps > 'd33))
// No failing taps detected, decrement by 31
dec_cnt <= #TCQ 'd32;
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
// // First failing tap detected between 0 and 34
// // decrement midpoint between 63 and failing tap
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
else
// First failing tap detected
// decrement to midpoint between 63 and failing tap
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end
end
PRECH_WAIT: begin
if (prech_done) begin
dqs_found_prech_req <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
end
FINE_DEC: begin
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b1;
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
init_dec_cnt <= #TCQ init_dec_cnt - 1;
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
dec_cnt <= #TCQ dec_cnt - 1;
end
FINE_DEC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else begin
fine_adj_state_r <= #TCQ FINAL_WAIT;
if ((init_dec_cnt == 'd0) && ~init_dec_done)
init_dec_done <= #TCQ 1'b1;
else
final_dec_done <= #TCQ 1'b1;
end
end
end
FINE_DEC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_DEC;
end
FINAL_WAIT: begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
FINE_ADJ_DONE: begin
if (&pi_dqs_found_all_bank) begin
fine_adjust_done_r <= #TCQ 1'b1;
rst_dqs_find <= #TCQ 1'b0;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
end
end
endcase
end
end
//*****************************************************************************
always@(posedge clk)
dqs_found_start_r <= #TCQ pi_dqs_found_start;
always @(posedge clk) begin
if (rst)
rnk_cnt_r <= #TCQ 2'b00;
else if (init_dqsfound_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r;
else if (rank_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
end
//*****************************************************************
// Read data_offset calibration done signal
//*****************************************************************
always @(posedge clk) begin
if (rst || (|pi_rst_stg1_cal_r))
init_dqsfound_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank) begin
if (rnk_cnt_r == RANKS-1)
init_dqsfound_done_r <= #TCQ 1'b1;
else
init_dqsfound_done_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst ||
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
rank_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
rank_done_r <= #TCQ 1'b1;
else
rank_done_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
rank_done_r1 <= #TCQ rank_done_r;
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
end
always @(posedge clk) begin
if (rst)
dqs_found_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
(fine_adj_state_r == FINE_ADJ_DONE))
dqs_found_done_r <= #TCQ 1'b1;
else
dqs_found_done_r <= #TCQ 1'b0;
end
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[2]) ||
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[20+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[2])
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
else
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
//(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][12+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] + 1;
end
//*****************************************************************************
// Two I/O Bank Interface
//*****************************************************************************
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
//*****************************************************************************
// One I/O Bank Interface
//*****************************************************************************
end else begin // One I/O Bank Interface
// Read data offset value for all DQS in Bank0
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
rd_byte_data_offset[l] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r]
<= #TCQ rd_byte_data_offset[rnk_cnt_r] + 1;
end
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted even with 3 dqfound retries
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk) begin
if (rst)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
else if (rst_dqs_find)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
else
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
end
// Final read data offset value to be used during write calibration and
// normal operation
generate
genvar i;
genvar j;
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
reg [5:0] final_do_cand [RANKS-1:0];
// combinatorially select the candidate offset for the bank
// indexed by final_do_index
if (HIGHEST_BANK == 3) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
default: final_do_cand[i] = 'd0;
endcase
end
end else if (HIGHEST_BANK == 2) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end else begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = 'd0;
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end
always @(posedge clk or posedge rst) begin
if (rst)
final_do_max[i] <= #TCQ 0;
else begin
final_do_max[i] <= #TCQ final_do_max[i]; // default
case (final_do_index[i])
3'b000: if ( | DATA_PRESENT[3:0])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b001: if ( | DATA_PRESENT[7:4])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b010: if ( | DATA_PRESENT[11:8])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
default:
final_do_max[i] <= #TCQ final_do_max[i];
endcase
end
end
always @(posedge clk)
if (rst) begin
final_do_index[i] <= #TCQ 0;
end
else begin
final_do_index[i] <= #TCQ final_do_index[i] + 1;
end
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
always @(posedge clk) begin
if (rst) begin
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
end
else begin
//if (dqsfound_retry[j])
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
//else
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
if (CWL_M % 2) // odd latency CAS slot 1
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
else // even latency CAS slot 0
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
end
end
else if (init_dqsfound_done_r5 ) begin
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
end
end
end
end
end
end
endgenerate
// Error generation in case pi_found_dqs signal from Phaser_IN
// is not asserted when a common rddata_offset value is used
always @(posedge clk) begin
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
end
endmodule
|
/***********************************************************
-- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable wrapper instantiating
// up to 5 memory banks of 4-lane phy primitives. There
// There are always 2 control banks leaving 18 lanes for data.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_mc_phy
#(
// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter RCLK_SELECT_BANK = 0,
parameter RCLK_SELECT_LANE = "B",
parameter RCLK_SELECT_EDGE = 4'b1111,
parameter GENERATE_DDR_CK_MAP = "0B",
parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002,
parameter USE_PRE_POST_FIFO = "TRUE",
parameter SYNTHESIS = "FALSE",
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PI_SEL_CLK_OFFSET = 6,
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio
// common to all i/o banks
parameter PHY_FOUR_WINDOW_CLOCKS = 63,
parameter PHY_EVENTS_DELAY = 18,
parameter PHY_COUNT_EN = "TRUE",
parameter PHY_SYNC_MODE = "TRUE",
parameter PHY_DISABLE_SEQ_MATCH = "FALSE",
parameter MASTER_PHY_CTL = 0,
// common to instance 0
parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff,
parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_0_LANE_REMAP = 16'h3210,
parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_0_IODELAY_GRP = "IODELAY_MIG",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter NUM_DDR_CK = 1,
parameter PHY_0_DATA_CTL = DATA_CTL_B0,
parameter PHY_0_CMD_OFFSET = 0,
parameter PHY_0_RD_CMD_OFFSET_0 = 0,
parameter PHY_0_RD_CMD_OFFSET_1 = 0,
parameter PHY_0_RD_CMD_OFFSET_2 = 0,
parameter PHY_0_RD_CMD_OFFSET_3 = 0,
parameter PHY_0_RD_DURATION_0 = 0,
parameter PHY_0_RD_DURATION_1 = 0,
parameter PHY_0_RD_DURATION_2 = 0,
parameter PHY_0_RD_DURATION_3 = 0,
parameter PHY_0_WR_CMD_OFFSET_0 = 0,
parameter PHY_0_WR_CMD_OFFSET_1 = 0,
parameter PHY_0_WR_CMD_OFFSET_2 = 0,
parameter PHY_0_WR_CMD_OFFSET_3 = 0,
parameter PHY_0_WR_DURATION_0 = 0,
parameter PHY_0_WR_DURATION_1 = 0,
parameter PHY_0_WR_DURATION_2 = 0,
parameter PHY_0_WR_DURATION_3 = 0,
parameter PHY_0_AO_WRLVL_EN = 0,
parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PHY_0_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE",
parameter PHY_0_A_PI_CLKOUT_DIV = 2,
parameter PHY_0_A_PO_CLKOUT_DIV = 2,
parameter PHY_0_A_BURST_MODE = "TRUE",
parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OCLK_DELAY = 25,
parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE",
parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED",
parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED",
parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00,
parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
// common to instance 1
parameter PHY_1_BITLANES = PHY_0_BITLANES,
parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_1_LANE_REMAP = 16'h3210,
parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_1_DATA_CTL = DATA_CTL_B1,
parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_1_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV,
parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE,
parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC ,
parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
// common to instance 2
parameter PHY_2_BITLANES = PHY_0_BITLANES,
parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_2_LANE_REMAP = 16'h3210,
parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_2_DATA_CTL = DATA_CTL_B2,
parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_2_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV ,
parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE ,
parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC,
parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE",
parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter TCK = 2500,
// local computational use, do not pass down
parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3])
+ (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3])
, // must not delete comma for syntax
parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))),
parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B3 = 0,
parameter HIGHEST_LANE_B4 = 0,
parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))),
parameter LP_DDR_CK_WIDTH = 2,
parameter GENERATE_SIGNAL_SPLIT = "FALSE"
,parameter CKE_ODT_AUX = "FALSE"
)
(
input rst,
input ddr_rst_in_n ,
input phy_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input auxout_clk,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [31:0] phy_ctl_wd,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input phy_ctl_wr,
input if_rst,
input if_empty_def,
input cke_in,
input idelay_ce,
input idelay_ld,
input idelay_inc,
input phyGo,
input input_sink,
output if_a_empty,
(* keep = "true", max_fanout = 3 *) output if_empty /* synthesis syn_maxfan = 3 */,
output if_empty_or,
output if_empty_and,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output pre_data_a_full,
output [HIGHEST_LANE*80-1:0] phy_din,
output phy_ctl_a_full,
(* keep = "true", max_fanout = 3 *) output wire [3:0] phy_ctl_full,
output [HIGHEST_LANE*12-1:0] mem_dq_out,
output [HIGHEST_LANE*12-1:0] mem_dq_ts,
input [HIGHEST_LANE*10-1:0] mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
(* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller
output phy_ctl_ready, // to fabric
output reg rst_out, // to memory
output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
// output rclk,
output mcGo,
output ref_dll_lock,
// calibration signals
input phy_write_calib,
input phy_read_calib,
input [5:0] calib_sel,
input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank
input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs
input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane
input calib_in_common,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input po_counter_read_en,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_phase_locked,
output pi_phase_locked_all,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg pi_dqs_out_of_range
);
wire [7:0] calib_zero_inputs_int ;
wire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ;
//Added the temporary variable for concadination operation
wire [2:0] calib_sel_byte0 ;
wire [2:0] calib_sel_byte1 ;
wire [2:0] calib_sel_byte2 ;
wire [4:0] po_coarse_overflow_w;
wire [4:0] po_fine_overflow_w;
wire [8:0] po_counter_read_val_w[4:0];
wire [4:0] pi_fine_overflow_w;
wire [5:0] pi_counter_read_val_w[4:0];
wire [4:0] pi_dqs_found_w;
wire [4:0] pi_dqs_found_all_w;
wire [4:0] pi_dqs_found_any_w;
wire [4:0] pi_dqs_out_of_range_w;
wire [4:0] pi_phase_locked_w;
wire [4:0] pi_phase_locked_all_w;
wire [4:0] rclk_w;
wire [HIGHEST_BANK-1:0] phy_ctl_ready_w;
wire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0];
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_;
wire [3:0] if_q0;
wire [3:0] if_q1;
wire [3:0] if_q2;
wire [3:0] if_q3;
wire [3:0] if_q4;
wire [7:0] if_q5;
wire [7:0] if_q6;
wire [3:0] if_q7;
wire [3:0] if_q8;
wire [3:0] if_q9;
wire [31:0] _phy_ctl_wd;
wire [3:0] aux_in_[4:1];
wire [3:0] rst_out_w;
wire freq_refclk_split;
wire mem_refclk_split;
wire mem_refclk_div4_split;
wire sync_pulse_split;
wire phy_clk_split0;
wire phy_ctl_clk_split0;
wire [31:0] phy_ctl_wd_split0;
wire phy_ctl_wr_split0;
wire phy_ctl_clk_split1;
wire phy_clk_split1;
wire [31:0] phy_ctl_wd_split1;
wire phy_ctl_wr_split1;
wire [5:0] phy_data_offset_1_split1;
wire phy_ctl_clk_split2;
wire phy_clk_split2;
wire [31:0] phy_ctl_wd_split2;
wire phy_ctl_wr_split2;
wire [5:0] phy_data_offset_2_split2;
wire [HIGHEST_LANE*80-1:0] phy_dout_split0;
wire phy_cmd_wr_en_split0;
wire phy_data_wr_en_split0;
wire phy_rd_en_split0;
wire [HIGHEST_LANE*80-1:0] phy_dout_split1;
wire phy_cmd_wr_en_split1;
wire phy_data_wr_en_split1;
wire phy_rd_en_split1;
wire [HIGHEST_LANE*80-1:0] phy_dout_split2;
wire phy_cmd_wr_en_split2;
wire phy_data_wr_en_split2;
wire phy_rd_en_split2;
wire phy_ctl_mstr_empty;
wire [HIGHEST_BANK-1:0] phy_ctl_empty;
wire _phy_ctl_a_full_f;
wire _phy_ctl_a_empty_f;
wire _phy_ctl_full_f;
wire _phy_ctl_empty_f;
wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p;
wire [HIGHEST_BANK-1:0] _phy_ctl_full_p;
wire [HIGHEST_BANK-1:0] of_ctl_a_full_v;
wire [HIGHEST_BANK-1:0] of_ctl_full_v;
wire [HIGHEST_BANK-1:0] of_data_a_full_v;
wire [HIGHEST_BANK-1:0] of_data_full_v;
wire [HIGHEST_BANK-1:0] pre_data_a_full_v;
wire [HIGHEST_BANK-1:0] if_empty_v;
wire [HIGHEST_BANK-1:0] byte_rd_en_v;
wire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks;
wire [HIGHEST_BANK-1:0] if_empty_or_v;
wire [HIGHEST_BANK-1:0] if_empty_and_v;
wire [HIGHEST_BANK-1:0] if_a_empty_v;
localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4";
localparam IF_SYNCHRONOUS_MODE = "FALSE";
localparam IF_SLOW_WR_CLK = "FALSE";
localparam IF_SLOW_RD_CLK = "FALSE";
localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE";
localparam RCLK_NEG_EDGE = 3'b000;
localparam RCLK_POS_EDGE = 3'b111;
localparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF;
localparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF;
localparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF;
// hi, lo positions for data offset field, MIG doesn't allow defines
localparam PC_DATA_OFFSET_RANGE_HI = 22;
localparam PC_DATA_OFFSET_RANGE_LO = 17;
/* Phaser_In Output source coding table
"PHASE_REF" : 4'b0000;
"DELAYED_MEM_REF" : 4'b0101;
"DELAYED_PHASE_REF" : 4'b0011;
"DELAYED_REF" : 4'b0001;
"FREQ_REF" : 4'b1000;
"MEM_REF" : 4'b0010;
*/
localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF";
localparam DDR_TCK = TCK;
localparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
localparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0;
localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line
localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line
localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta
/*
Intrinsic delay of Phaser In Stage 1
@3300ps - 1.939ns - 58.8%
@2500ps - 1.657ns - 66.3%
@1875ps - 1.263ns - 67.4%
@1500ps - 1.021ns - 68.1%
@1250ps - 0.868ns - 69.4%
@1072ps - 0.752ns - 70.1%
@938ps - 0.667ns - 71.1%
*/
// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0
// Fraction of a full DDR_TCK period
localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 :
((DDR_TCK < 1005) ? 0.667 :
(DDR_TCK < 1160) ? 0.752 :
(DDR_TCK < 1375) ? 0.868 :
(DDR_TCK < 1685) ? 1.021 :
(DDR_TCK < 2185) ? 1.263 :
(DDR_TCK < 2900) ? 1.657 :
(DDR_TCK < 3100) ? 1.771 : 1.939)*1000;
/*
Intrinsic delay of Phaser In Stage 2
@3300ps - 0.912ns - 27.6% - single tap - 13ps
@3000ps - 0.848ns - 28.3% - single tap - 11ps
@2500ps - 1.264ns - 50.6% - single tap - 19ps
@1875ps - 1.000ns - 53.3% - single tap - 15ps
@1500ps - 0.848ns - 56.5% - single tap - 11ps
@1250ps - 0.736ns - 58.9% - single tap - 9ps
@1072ps - 0.664ns - 61.9% - single tap - 8ps
@938ps - 0.608ns - 64.8% - single tap - 7ps
*/
// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps)
localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor
/*
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1
@3300ps - 1.294ns - 39.2%
@2500ps - 1.294ns - 51.8%
@1875ps - 1.030ns - 54.9%
@1500ps - 0.878ns - 58.5%
@1250ps - 0.766ns - 61.3%
@1072ps - 0.694ns - 64.7%
@938ps - 0.638ns - 68.0%
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0
@3300ps - 2.084ns - 63.2% - single tap - 20ps
@2500ps - 2.084ns - 81.9% - single tap - 19ps
@1875ps - 1.676ns - 89.4% - single tap - 15ps
@1500ps - 1.444ns - 96.3% - single tap - 11ps
@1250ps - 1.276ns - 102.1% - single tap - 9ps
@1072ps - 1.164ns - 108.6% - single tap - 8ps
@938ps - 1.076ns - 114.7% - single tap - 7ps
*/
// Fraction of a full DDR_TCK period
localparam real PO_STG1_INTRINSIC_DELAY = 0;
localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor
localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor
localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY +
(PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY);
// When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can
// go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this,
// a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments
// to the stage 2 delay can be made after reset is removed.
localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PO_CIRC_BUF_META_ZONE = 200.0;
localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0;
localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK;
// If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold
// If it is not more than the threshold than we must push the delay after the clock period plus a guardband.
//A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated.
localparam integer PO_CIRC_BUF_DELAY = 60;
//localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 :
// (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE :
// (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE;
localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE;
localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY;
localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY;
localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE);
localparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi
// The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path
// of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the
// oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment
// is within the range of the stage 2 delay line in the Phaser_In.
localparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY);
localparam integer PO_DELAY_INT = PO_DELAY;
localparam real PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK);
// if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is
// if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge.
// note that in this case PI_OFFSET is negative so invert before subtracting.
localparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0
? PI_OFFSET
: ((-PI_OFFSET) < DDR_TCK/2) ?
(DDR_TCK/2 - (- PI_OFFSET)) :
(DDR_TCK - (- PI_OFFSET)) ;
localparam real PI_STG2_DELAY =
(PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ?
PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND);
localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE;
localparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE));
localparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
wire _phy_clk;
wire [2:0] mcGo_w;
wire [HIGHEST_BANK-1:0] ref_dll_lock_w;
reg [15:0] mcGo_r;
assign ref_dll_lock = & ref_dll_lock_w;
initial begin
if ( SYNTHESIS == "FALSE" ) begin
$display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1);
$display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1);
$display("%m : HIGHEST_BANK = %d", HIGHEST_BANK);
$display("%m : FREQ_REF_PERIOD = %0.2f ", FREQ_REF_PERIOD);
$display("%m : DDR_TCK = %0d ", DDR_TCK);
$display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE);
$display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY);
$display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET);
$display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE);
$display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY);
$display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY);
$display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY);
$display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY);
$display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY);
$display("%m : PO_DELAY = %0.2f ", PO_DELAY);
$display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY);
$display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY);
$display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY);
$display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY);
$display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY);
$display("%m : PI_MAX_STG2_DELAY = %0.2f ", PI_MAX_STG2_DELAY);
$display("%m : PI_OFFSET = %0.2f ", PI_OFFSET);
if ( PI_OFFSET < 0) $display("%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used.");
$display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY);
$display("%m :PI_STG2_DELAY_CAND = %0.2f ",PI_STG2_DELAY_CAND);
$display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY);
$display("%m : RCLK_SELECT_EDGE = %0b ", LP_RCLK_SELECT_EDGE);
end // SYNTHESIS
if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display("WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY);
end
assign sync_pulse_split = sync_pulse;
assign mem_refclk_split = mem_refclk;
assign freq_refclk_split = freq_refclk;
assign mem_refclk_div4_split = mem_refclk_div4;
assign phy_ctl_clk_split0 = _phy_clk;
assign phy_ctl_wd_split0 = phy_ctl_wd;
assign phy_ctl_wr_split0 = phy_ctl_wr;
assign phy_clk_split0 = phy_clk;
assign phy_cmd_wr_en_split0 = phy_cmd_wr_en;
assign phy_data_wr_en_split0 = phy_data_wr_en;
assign phy_rd_en_split0 = phy_rd_en;
assign phy_dout_split0 = phy_dout;
assign phy_ctl_clk_split1 = phy_clk;
assign phy_ctl_wd_split1 = phy_ctl_wd;
assign phy_data_offset_1_split1 = data_offset_1;
assign phy_ctl_wr_split1 = phy_ctl_wr;
assign phy_clk_split1 = phy_clk;
assign phy_cmd_wr_en_split1 = phy_cmd_wr_en;
assign phy_data_wr_en_split1 = phy_data_wr_en;
assign phy_rd_en_split1 = phy_rd_en;
assign phy_dout_split1 = phy_dout;
assign phy_ctl_clk_split2 = phy_clk;
assign phy_ctl_wd_split2 = phy_ctl_wd;
assign phy_data_offset_2_split2 = data_offset_2;
assign phy_ctl_wr_split2 = phy_ctl_wr;
assign phy_clk_split2 = phy_clk;
assign phy_cmd_wr_en_split2 = phy_cmd_wr_en;
assign phy_data_wr_en_split2 = phy_data_wr_en;
assign phy_rd_en_split2 = phy_rd_en;
assign phy_dout_split2 = phy_dout;
// these wires are needed to coerce correct synthesis
// the synthesizer did not always see the widths of the
// parameters as 4 bits.
wire [3:0] blb0 = BYTE_LANES_B0;
wire [3:0] blb1 = BYTE_LANES_B1;
wire [3:0] blb2 = BYTE_LANES_B2;
wire [3:0] dcb0 = DATA_CTL_B0;
wire [3:0] dcb1 = DATA_CTL_B1;
wire [3:0] dcb2 = DATA_CTL_B2;
assign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0});
assign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0});
assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0];
assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs};
//Added to remove concadination in the instantiation
assign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ;
assign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ;
assign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ;
assign calib_zero_lanes_int = calib_zero_lanes;
assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0];
assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL];
assign of_ctl_a_full = |of_ctl_a_full_v;
assign of_ctl_full = |of_ctl_full_v;
assign of_data_a_full = |of_data_a_full_v;
assign of_data_full = |of_data_full_v;
assign pre_data_a_full= |pre_data_a_full_v;
// if if_empty_def == 1, empty is asserted only if all are empty;
// this allows the user to detect a skewed fifo depth and self-clear
// if desired. It avoids a reset to clear the flags.
assign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v;
assign if_empty_or = |if_empty_or_v;
assign if_empty_and = &if_empty_and_v;
assign if_a_empty = |if_a_empty_v;
generate
genvar i;
for (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen
case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff)
16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
default : initial $display("ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) ", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff ));
endcase
end
endgenerate
//assign rclk = rclk_w[RCLK_SELECT_BANK];
reg rst_auxout;
reg rst_auxout_r;
reg rst_auxout_rr;
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout_r <= #(1) 1'b1;
rst_auxout_rr <= #(1) 1'b1;
end
else begin
rst_auxout_r <= #(1) rst;
rst_auxout_rr <= #(1) rst_auxout_r;
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
else begin
always @(negedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
localparam L_RESET_SELECT_BANK =
(BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK;
always @(*) begin
rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n;
end
always @(posedge phy_clk or posedge rst) begin
if ( rst)
mcGo_r <= #(1) 0;
else
mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w;
end
assign mcGo = mcGo_r[15];
generate
// this is an optional 1 clock delay to add latency to the phy_control programming path
if (PHYCTL_CMD_FIFO == "TRUE") begin : cmd_fifo_soft
reg [31:0] phy_wd_reg = 0;
reg [3:0] aux_in1_reg = 0;
reg [3:0] aux_in2_reg = 0;
reg sfifo_ready = 0;
assign _phy_ctl_wd = phy_wd_reg;
assign aux_in_[1] = aux_in1_reg;
assign aux_in_[2] = aux_in2_reg;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[1] = |_phy_ctl_full_p;
assign phy_ctl_full[2] = |_phy_ctl_full_p;
assign phy_ctl_full[3] = |_phy_ctl_full_p;
assign _phy_clk = phy_clk;
always @(posedge phy_clk) begin
phy_wd_reg <= #1 phy_ctl_wd;
aux_in1_reg <= #1 aux_in_1;
aux_in2_reg <= #1 aux_in_2;
sfifo_ready <= #1 phy_ctl_wr;
end
end
else if (PHYCTL_CMD_FIFO == "FALSE") begin
assign _phy_ctl_wd = phy_ctl_wd;
assign aux_in_[1] = aux_in_1;
assign aux_in_[2] = aux_in_2;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[3:1] = 3'b000;
assign _phy_clk = phy_clk;
end
endgenerate
// instance of four-lane phy
generate
if (HIGHEST_BANK == 3) begin : banks_3
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]};
end
else if (HIGHEST_BANK == 2) begin : banks_2
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1};
end
else begin : banks_1
assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1};
end
if ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */
.DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY),
.BITLANES (PHY_0_BITLANES),
.BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK),
.LAST_BANK (PHY_0_IS_LAST_BANK),
.LANE_REMAP (PHY_0_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_0_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_0_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_0_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_0_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_0_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_0_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_0_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_0_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_0_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split0),
.phy_ctl_clk (phy_ctl_clk_split0),
.phy_ctl_wd (phy_ctl_wd_split0),
.data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]),
.phy_ctl_wr (phy_ctl_wr_split0),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]),
.phy_cmd_wr_en (phy_cmd_wr_en_split0),
.phy_data_wr_en (phy_data_wr_en_split0),
.phy_rd_en (phy_rd_en_split0),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[0]),
.rclk (),
.rst_out (rst_out_w[0]),
.mcGo (mcGo_w[0]),
.ref_dll_lock (ref_dll_lock_w[0]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]),
.if_a_empty (if_a_empty_v[0]),
.if_empty (if_empty_v[0]),
.byte_rd_en (byte_rd_en_v[0]),
.if_empty_or (if_empty_or_v[0]),
.if_empty_and (if_empty_and_v[0]),
.of_ctl_a_full (of_ctl_a_full_v[0]),
.of_data_a_full (of_data_a_full_v[0]),
.of_ctl_full (of_ctl_full_v[0]),
.of_data_full (of_data_full_v[0]),
.pre_data_a_full (pre_data_a_full_v[0]),
.phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]),
.phy_ctl_a_full (_phy_ctl_a_full_p[0]),
.phy_ctl_full (_phy_ctl_full_p[0]),
.phy_ctl_empty (phy_ctl_empty[0]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]),
.aux_out (aux_out_[3:0]),
.phy_ctl_ready (phy_ctl_ready_w[0]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte0),
.calib_zero_ctrl (calib_zero_ctrl[0]),
.calib_zero_lanes (calib_zero_lanes_int[3:0]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[0]),
.po_fine_enable (po_fine_enable[0]),
.po_fine_inc (po_fine_inc[0]),
.po_coarse_inc (po_coarse_inc[0]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[0]),
.po_fine_overflow (po_fine_overflow_w[0]),
.po_counter_read_val (po_counter_read_val_w[0]),
.pi_rst_dqs_find (pi_rst_dqs_find[0]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[0]),
.pi_counter_read_val (pi_counter_read_val_w[0]),
.pi_dqs_found (pi_dqs_found_w[0]),
.pi_dqs_found_all (pi_dqs_found_all_w[0]),
.pi_dqs_found_any (pi_dqs_found_any_w[0]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]),
.pi_phase_locked (pi_phase_locked_w[0]),
.pi_phase_locked_all (pi_phase_locked_all_w[0])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[0] <= #100 0;
aux_out[2] <= #100 0;
end
else begin
aux_out[0] <= #100 aux_out_[0];
aux_out[2] <= #100 aux_out_[2];
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
end
else begin
if ( HIGHEST_BANK > 0) begin
assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0;
assign _phy_ctl_a_full_p[0] = 0;
assign of_ctl_a_full_v[0] = 0;
assign of_ctl_full_v[0] = 0;
assign of_data_a_full_v[0] = 0;
assign of_data_full_v[0] = 0;
assign pre_data_a_full_v[0] = 0;
assign if_empty_v[0] = 0;
assign byte_rd_en_v[0] = 1;
always @(*)
aux_out[3:0] = 0;
end
assign pi_dqs_found_w[0] = 1;
assign pi_dqs_found_all_w[0] = 1;
assign pi_dqs_found_any_w[0] = 0;
assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_out_of_range_w[0] = 0;
assign pi_phase_locked_w[0] = 1;
assign po_fine_overflow_w[0] = 0;
assign po_coarse_overflow_w[0] = 0;
assign po_fine_overflow_w[0] = 0;
assign pi_fine_overflow_w[0] = 0;
assign po_counter_read_val_w[0] = 0;
assign pi_counter_read_val_w[0] = 0;
assign mcGo_w[0] = 1;
if ( RCLK_SELECT_BANK == 0)
always @(*)
aux_out[3:0] = 0;
end
if ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */
.DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY),
.BITLANES (PHY_1_BITLANES),
.BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK),
.LAST_BANK (PHY_1_IS_LAST_BANK ),
.LANE_REMAP (PHY_1_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_1_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_1_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_1_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_1_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_1_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_1_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_1_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_1_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_1_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_1_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_1_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_1_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_1_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split1),
.phy_ctl_clk (phy_ctl_clk_split1),
.phy_ctl_wd (phy_ctl_wd_split1),
.data_offset (phy_data_offset_1_split1),
.phy_ctl_wr (phy_ctl_wr_split1),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]),
.phy_cmd_wr_en (phy_cmd_wr_en_split1),
.phy_data_wr_en (phy_data_wr_en_split1),
.phy_rd_en (phy_rd_en_split1),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[1]),
.rclk (),
.rst_out (rst_out_w[1]),
.mcGo (mcGo_w[1]),
.ref_dll_lock (ref_dll_lock_w[1]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]),
.if_a_empty (if_a_empty_v[1]),
.if_empty (if_empty_v[1]),
.byte_rd_en (byte_rd_en_v[1]),
.if_empty_or (if_empty_or_v[1]),
.if_empty_and (if_empty_and_v[1]),
.of_ctl_a_full (of_ctl_a_full_v[1]),
.of_data_a_full (of_data_a_full_v[1]),
.of_ctl_full (of_ctl_full_v[1]),
.of_data_full (of_data_full_v[1]),
.pre_data_a_full (pre_data_a_full_v[1]),
.phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]),
.phy_ctl_a_full (_phy_ctl_a_full_p[1]),
.phy_ctl_full (_phy_ctl_full_p[1]),
.phy_ctl_empty (phy_ctl_empty[1]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]),
.aux_out (aux_out_[7:4]),
.phy_ctl_ready (phy_ctl_ready_w[1]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte1),
.calib_zero_ctrl (calib_zero_ctrl[1]),
.calib_zero_lanes (calib_zero_lanes_int[7:4]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[1]),
.po_fine_enable (po_fine_enable[1]),
.po_fine_inc (po_fine_inc[1]),
.po_coarse_inc (po_coarse_inc[1]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[1]),
.po_fine_overflow (po_fine_overflow_w[1]),
.po_counter_read_val (po_counter_read_val_w[1]),
.pi_rst_dqs_find (pi_rst_dqs_find[1]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[1]),
.pi_counter_read_val (pi_counter_read_val_w[1]),
.pi_dqs_found (pi_dqs_found_w[1]),
.pi_dqs_found_all (pi_dqs_found_all_w[1]),
.pi_dqs_found_any (pi_dqs_found_any_w[1]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]),
.pi_phase_locked (pi_phase_locked_w[1]),
.pi_phase_locked_all (pi_phase_locked_all_w[1])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[4] <= #100 0;
aux_out[6] <= #100 0;
end
else begin
aux_out[4] <= #100 aux_out_[4];
aux_out[6] <= #100 aux_out_[6];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
end
else begin
if ( HIGHEST_BANK > 1) begin
assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0;
assign _phy_ctl_a_full_p[1] = 0;
assign of_ctl_a_full_v[1] = 0;
assign of_ctl_full_v[1] = 0;
assign of_data_a_full_v[1] = 0;
assign of_data_full_v[1] = 0;
assign pre_data_a_full_v[1] = 0;
assign if_empty_v[1] = 0;
assign byte_rd_en_v[1] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
always @(*)
aux_out[7:4] = 0;
end
assign pi_dqs_found_w[1] = 1;
assign pi_dqs_found_all_w[1] = 1;
assign pi_dqs_found_any_w[1] = 0;
assign pi_dqs_out_of_range_w[1] = 0;
assign pi_phase_locked_w[1] = 1;
assign po_coarse_overflow_w[1] = 0;
assign po_fine_overflow_w[1] = 0;
assign pi_fine_overflow_w[1] = 0;
assign po_counter_read_val_w[1] = 0;
assign pi_counter_read_val_w[1] = 0;
assign mcGo_w[1] = 1;
end
if ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */
.DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY),
.BITLANES (PHY_2_BITLANES),
.BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK),
.LAST_BANK (PHY_2_IS_LAST_BANK ),
.LANE_REMAP (PHY_2_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_2_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_2_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_2_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_2_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_2_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_2_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_2_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_2_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_2_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_2_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_2_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_2_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_2_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split2),
.phy_ctl_clk (phy_ctl_clk_split2),
.phy_ctl_wd (phy_ctl_wd_split2),
.data_offset (phy_data_offset_2_split2),
.phy_ctl_wr (phy_ctl_wr_split2),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]),
.phy_cmd_wr_en (phy_cmd_wr_en_split2),
.phy_data_wr_en (phy_data_wr_en_split2),
.phy_rd_en (phy_rd_en_split2),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[2]),
.rclk (),
.rst_out (rst_out_w[2]),
.mcGo (mcGo_w[2]),
.ref_dll_lock (ref_dll_lock_w[2]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]),
.if_a_empty (if_a_empty_v[2]),
.if_empty (if_empty_v[2]),
.byte_rd_en (byte_rd_en_v[2]),
.if_empty_or (if_empty_or_v[2]),
.if_empty_and (if_empty_and_v[2]),
.of_ctl_a_full (of_ctl_a_full_v[2]),
.of_data_a_full (of_data_a_full_v[2]),
.of_ctl_full (of_ctl_full_v[2]),
.of_data_full (of_data_full_v[2]),
.pre_data_a_full (pre_data_a_full_v[2]),
.phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]),
.phy_ctl_a_full (_phy_ctl_a_full_p[2]),
.phy_ctl_full (_phy_ctl_full_p[2]),
.phy_ctl_empty (phy_ctl_empty[2]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]),
.aux_out (aux_out_[11:8]),
.phy_ctl_ready (phy_ctl_ready_w[2]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte2),
.calib_zero_ctrl (calib_zero_ctrl[2]),
.calib_zero_lanes (calib_zero_lanes_int[11:8]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[2]),
.po_fine_enable (po_fine_enable[2]),
.po_fine_inc (po_fine_inc[2]),
.po_coarse_inc (po_coarse_inc[2]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[2]),
.po_fine_overflow (po_fine_overflow_w[2]),
.po_counter_read_val (po_counter_read_val_w[2]),
.pi_rst_dqs_find (pi_rst_dqs_find[2]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[2]),
.pi_counter_read_val (pi_counter_read_val_w[2]),
.pi_dqs_found (pi_dqs_found_w[2]),
.pi_dqs_found_all (pi_dqs_found_all_w[2]),
.pi_dqs_found_any (pi_dqs_found_any_w[2]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]),
.pi_phase_locked (pi_phase_locked_w[2]),
.pi_phase_locked_all (pi_phase_locked_all_w[2])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[8] <= #100 0;
aux_out[10] <= #100 0;
end
else begin
aux_out[8] <= #100 aux_out_[8];
aux_out[10] <= #100 aux_out_[10];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
end
else begin
if ( HIGHEST_BANK > 2) begin
assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0;
assign _phy_ctl_a_full_p[2] = 0;
assign of_ctl_a_full_v[2] = 0;
assign of_ctl_full_v[2] = 0;
assign of_data_a_full_v[2] = 0;
assign of_data_full_v[2] = 0;
assign pre_data_a_full_v[2] = 0;
assign if_empty_v[2] = 0;
assign byte_rd_en_v[2] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
always @(*)
aux_out[11:8] = 0;
end
assign pi_dqs_found_w[2] = 1;
assign pi_dqs_found_all_w[2] = 1;
assign pi_dqs_found_any_w[2] = 0;
assign pi_dqs_out_of_range_w[2] = 0;
assign pi_phase_locked_w[2] = 1;
assign po_coarse_overflow_w[2] = 0;
assign po_fine_overflow_w[2] = 0;
assign po_counter_read_val_w[2] = 0;
assign pi_counter_read_val_w[2] = 0;
assign mcGo_w[2] = 1;
end
endgenerate
generate
// for single bank , emit an extra phaser_in to generate rclk
// so that auxout can be placed in another region
// if desired
if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0)
begin : phaser_in_rclk
localparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY;
PHASER_IN_PHY #(
.BURST_MODE ( PHY_0_A_BURST_MODE),
.CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV),
.FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.FINE_DELAY ( L_EXTRA_PI_FINE_DELAY),
.OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC)
) phaser_in_rclk (
.DQSFOUND (),
.DQSOUTOFRANGE (),
.FINEOVERFLOW (),
.PHASELOCKED (),
.ISERDESRST (),
.ICLKDIV (),
.ICLK (),
.COUNTERREADVAL (),
.RCLK (),
.WRENABLE (),
.BURSTPENDINGPHY (),
.ENCALIBPHY (),
.FINEENABLE (0),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (0),
.PHASEREFCLK (),
.RSTDQSFIND (0),
.RST (rst),
.FINEINC (),
.COUNTERLOADEN (),
.COUNTERREADEN (),
.COUNTERLOADVAL (),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
end
endgenerate
always @(*) begin
case (calib_sel[5:3])
3'b000: begin
po_coarse_overflow = po_coarse_overflow_w[0];
po_fine_overflow = po_fine_overflow_w[0];
po_counter_read_val = po_counter_read_val_w[0];
pi_fine_overflow = pi_fine_overflow_w[0];
pi_counter_read_val = pi_counter_read_val_w[0];
pi_phase_locked = pi_phase_locked_w[0];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[0];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[0];
end
3'b001: begin
po_coarse_overflow = po_coarse_overflow_w[1];
po_fine_overflow = po_fine_overflow_w[1];
po_counter_read_val = po_counter_read_val_w[1];
pi_fine_overflow = pi_fine_overflow_w[1];
pi_counter_read_val = pi_counter_read_val_w[1];
pi_phase_locked = pi_phase_locked_w[1];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[1];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[1];
end
3'b010: begin
po_coarse_overflow = po_coarse_overflow_w[2];
po_fine_overflow = po_fine_overflow_w[2];
po_counter_read_val = po_counter_read_val_w[2];
pi_fine_overflow = pi_fine_overflow_w[2];
pi_counter_read_val = pi_counter_read_val_w[2];
pi_phase_locked = pi_phase_locked_w[2];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[2];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[2];
end
default: begin
po_coarse_overflow = 0;
po_fine_overflow = 0;
po_counter_read_val = 0;
pi_fine_overflow = 0;
pi_counter_read_val = 0;
pi_phase_locked = 0;
pi_dqs_found = 0;
pi_dqs_out_of_range = 0;
end
endcase
end
endmodule // mc_phy
|
/***********************************************************
-- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable wrapper instantiating
// up to 5 memory banks of 4-lane phy primitives. There
// There are always 2 control banks leaving 18 lanes for data.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_mc_phy
#(
// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter RCLK_SELECT_BANK = 0,
parameter RCLK_SELECT_LANE = "B",
parameter RCLK_SELECT_EDGE = 4'b1111,
parameter GENERATE_DDR_CK_MAP = "0B",
parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002,
parameter USE_PRE_POST_FIFO = "TRUE",
parameter SYNTHESIS = "FALSE",
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PI_SEL_CLK_OFFSET = 6,
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio
// common to all i/o banks
parameter PHY_FOUR_WINDOW_CLOCKS = 63,
parameter PHY_EVENTS_DELAY = 18,
parameter PHY_COUNT_EN = "TRUE",
parameter PHY_SYNC_MODE = "TRUE",
parameter PHY_DISABLE_SEQ_MATCH = "FALSE",
parameter MASTER_PHY_CTL = 0,
// common to instance 0
parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff,
parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_0_LANE_REMAP = 16'h3210,
parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_0_IODELAY_GRP = "IODELAY_MIG",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter NUM_DDR_CK = 1,
parameter PHY_0_DATA_CTL = DATA_CTL_B0,
parameter PHY_0_CMD_OFFSET = 0,
parameter PHY_0_RD_CMD_OFFSET_0 = 0,
parameter PHY_0_RD_CMD_OFFSET_1 = 0,
parameter PHY_0_RD_CMD_OFFSET_2 = 0,
parameter PHY_0_RD_CMD_OFFSET_3 = 0,
parameter PHY_0_RD_DURATION_0 = 0,
parameter PHY_0_RD_DURATION_1 = 0,
parameter PHY_0_RD_DURATION_2 = 0,
parameter PHY_0_RD_DURATION_3 = 0,
parameter PHY_0_WR_CMD_OFFSET_0 = 0,
parameter PHY_0_WR_CMD_OFFSET_1 = 0,
parameter PHY_0_WR_CMD_OFFSET_2 = 0,
parameter PHY_0_WR_CMD_OFFSET_3 = 0,
parameter PHY_0_WR_DURATION_0 = 0,
parameter PHY_0_WR_DURATION_1 = 0,
parameter PHY_0_WR_DURATION_2 = 0,
parameter PHY_0_WR_DURATION_3 = 0,
parameter PHY_0_AO_WRLVL_EN = 0,
parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PHY_0_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE",
parameter PHY_0_A_PI_CLKOUT_DIV = 2,
parameter PHY_0_A_PO_CLKOUT_DIV = 2,
parameter PHY_0_A_BURST_MODE = "TRUE",
parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OCLK_DELAY = 25,
parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE",
parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED",
parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED",
parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00,
parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
// common to instance 1
parameter PHY_1_BITLANES = PHY_0_BITLANES,
parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_1_LANE_REMAP = 16'h3210,
parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_1_DATA_CTL = DATA_CTL_B1,
parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_1_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV,
parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE,
parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC ,
parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
// common to instance 2
parameter PHY_2_BITLANES = PHY_0_BITLANES,
parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_2_LANE_REMAP = 16'h3210,
parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_2_DATA_CTL = DATA_CTL_B2,
parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_2_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV ,
parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE ,
parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC,
parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE",
parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter TCK = 2500,
// local computational use, do not pass down
parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3])
+ (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3])
, // must not delete comma for syntax
parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))),
parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B3 = 0,
parameter HIGHEST_LANE_B4 = 0,
parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))),
parameter LP_DDR_CK_WIDTH = 2,
parameter GENERATE_SIGNAL_SPLIT = "FALSE"
,parameter CKE_ODT_AUX = "FALSE"
)
(
input rst,
input ddr_rst_in_n ,
input phy_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input auxout_clk,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [31:0] phy_ctl_wd,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input phy_ctl_wr,
input if_rst,
input if_empty_def,
input cke_in,
input idelay_ce,
input idelay_ld,
input idelay_inc,
input phyGo,
input input_sink,
output if_a_empty,
(* keep = "true", max_fanout = 3 *) output if_empty /* synthesis syn_maxfan = 3 */,
output if_empty_or,
output if_empty_and,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output pre_data_a_full,
output [HIGHEST_LANE*80-1:0] phy_din,
output phy_ctl_a_full,
(* keep = "true", max_fanout = 3 *) output wire [3:0] phy_ctl_full,
output [HIGHEST_LANE*12-1:0] mem_dq_out,
output [HIGHEST_LANE*12-1:0] mem_dq_ts,
input [HIGHEST_LANE*10-1:0] mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
(* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller
output phy_ctl_ready, // to fabric
output reg rst_out, // to memory
output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
// output rclk,
output mcGo,
output ref_dll_lock,
// calibration signals
input phy_write_calib,
input phy_read_calib,
input [5:0] calib_sel,
input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank
input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs
input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane
input calib_in_common,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input po_counter_read_en,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_phase_locked,
output pi_phase_locked_all,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg pi_dqs_out_of_range
);
wire [7:0] calib_zero_inputs_int ;
wire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ;
//Added the temporary variable for concadination operation
wire [2:0] calib_sel_byte0 ;
wire [2:0] calib_sel_byte1 ;
wire [2:0] calib_sel_byte2 ;
wire [4:0] po_coarse_overflow_w;
wire [4:0] po_fine_overflow_w;
wire [8:0] po_counter_read_val_w[4:0];
wire [4:0] pi_fine_overflow_w;
wire [5:0] pi_counter_read_val_w[4:0];
wire [4:0] pi_dqs_found_w;
wire [4:0] pi_dqs_found_all_w;
wire [4:0] pi_dqs_found_any_w;
wire [4:0] pi_dqs_out_of_range_w;
wire [4:0] pi_phase_locked_w;
wire [4:0] pi_phase_locked_all_w;
wire [4:0] rclk_w;
wire [HIGHEST_BANK-1:0] phy_ctl_ready_w;
wire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0];
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_;
wire [3:0] if_q0;
wire [3:0] if_q1;
wire [3:0] if_q2;
wire [3:0] if_q3;
wire [3:0] if_q4;
wire [7:0] if_q5;
wire [7:0] if_q6;
wire [3:0] if_q7;
wire [3:0] if_q8;
wire [3:0] if_q9;
wire [31:0] _phy_ctl_wd;
wire [3:0] aux_in_[4:1];
wire [3:0] rst_out_w;
wire freq_refclk_split;
wire mem_refclk_split;
wire mem_refclk_div4_split;
wire sync_pulse_split;
wire phy_clk_split0;
wire phy_ctl_clk_split0;
wire [31:0] phy_ctl_wd_split0;
wire phy_ctl_wr_split0;
wire phy_ctl_clk_split1;
wire phy_clk_split1;
wire [31:0] phy_ctl_wd_split1;
wire phy_ctl_wr_split1;
wire [5:0] phy_data_offset_1_split1;
wire phy_ctl_clk_split2;
wire phy_clk_split2;
wire [31:0] phy_ctl_wd_split2;
wire phy_ctl_wr_split2;
wire [5:0] phy_data_offset_2_split2;
wire [HIGHEST_LANE*80-1:0] phy_dout_split0;
wire phy_cmd_wr_en_split0;
wire phy_data_wr_en_split0;
wire phy_rd_en_split0;
wire [HIGHEST_LANE*80-1:0] phy_dout_split1;
wire phy_cmd_wr_en_split1;
wire phy_data_wr_en_split1;
wire phy_rd_en_split1;
wire [HIGHEST_LANE*80-1:0] phy_dout_split2;
wire phy_cmd_wr_en_split2;
wire phy_data_wr_en_split2;
wire phy_rd_en_split2;
wire phy_ctl_mstr_empty;
wire [HIGHEST_BANK-1:0] phy_ctl_empty;
wire _phy_ctl_a_full_f;
wire _phy_ctl_a_empty_f;
wire _phy_ctl_full_f;
wire _phy_ctl_empty_f;
wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p;
wire [HIGHEST_BANK-1:0] _phy_ctl_full_p;
wire [HIGHEST_BANK-1:0] of_ctl_a_full_v;
wire [HIGHEST_BANK-1:0] of_ctl_full_v;
wire [HIGHEST_BANK-1:0] of_data_a_full_v;
wire [HIGHEST_BANK-1:0] of_data_full_v;
wire [HIGHEST_BANK-1:0] pre_data_a_full_v;
wire [HIGHEST_BANK-1:0] if_empty_v;
wire [HIGHEST_BANK-1:0] byte_rd_en_v;
wire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks;
wire [HIGHEST_BANK-1:0] if_empty_or_v;
wire [HIGHEST_BANK-1:0] if_empty_and_v;
wire [HIGHEST_BANK-1:0] if_a_empty_v;
localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4";
localparam IF_SYNCHRONOUS_MODE = "FALSE";
localparam IF_SLOW_WR_CLK = "FALSE";
localparam IF_SLOW_RD_CLK = "FALSE";
localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE";
localparam RCLK_NEG_EDGE = 3'b000;
localparam RCLK_POS_EDGE = 3'b111;
localparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF;
localparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF;
localparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF;
// hi, lo positions for data offset field, MIG doesn't allow defines
localparam PC_DATA_OFFSET_RANGE_HI = 22;
localparam PC_DATA_OFFSET_RANGE_LO = 17;
/* Phaser_In Output source coding table
"PHASE_REF" : 4'b0000;
"DELAYED_MEM_REF" : 4'b0101;
"DELAYED_PHASE_REF" : 4'b0011;
"DELAYED_REF" : 4'b0001;
"FREQ_REF" : 4'b1000;
"MEM_REF" : 4'b0010;
*/
localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF";
localparam DDR_TCK = TCK;
localparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
localparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0;
localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line
localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line
localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta
/*
Intrinsic delay of Phaser In Stage 1
@3300ps - 1.939ns - 58.8%
@2500ps - 1.657ns - 66.3%
@1875ps - 1.263ns - 67.4%
@1500ps - 1.021ns - 68.1%
@1250ps - 0.868ns - 69.4%
@1072ps - 0.752ns - 70.1%
@938ps - 0.667ns - 71.1%
*/
// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0
// Fraction of a full DDR_TCK period
localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 :
((DDR_TCK < 1005) ? 0.667 :
(DDR_TCK < 1160) ? 0.752 :
(DDR_TCK < 1375) ? 0.868 :
(DDR_TCK < 1685) ? 1.021 :
(DDR_TCK < 2185) ? 1.263 :
(DDR_TCK < 2900) ? 1.657 :
(DDR_TCK < 3100) ? 1.771 : 1.939)*1000;
/*
Intrinsic delay of Phaser In Stage 2
@3300ps - 0.912ns - 27.6% - single tap - 13ps
@3000ps - 0.848ns - 28.3% - single tap - 11ps
@2500ps - 1.264ns - 50.6% - single tap - 19ps
@1875ps - 1.000ns - 53.3% - single tap - 15ps
@1500ps - 0.848ns - 56.5% - single tap - 11ps
@1250ps - 0.736ns - 58.9% - single tap - 9ps
@1072ps - 0.664ns - 61.9% - single tap - 8ps
@938ps - 0.608ns - 64.8% - single tap - 7ps
*/
// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps)
localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor
/*
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1
@3300ps - 1.294ns - 39.2%
@2500ps - 1.294ns - 51.8%
@1875ps - 1.030ns - 54.9%
@1500ps - 0.878ns - 58.5%
@1250ps - 0.766ns - 61.3%
@1072ps - 0.694ns - 64.7%
@938ps - 0.638ns - 68.0%
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0
@3300ps - 2.084ns - 63.2% - single tap - 20ps
@2500ps - 2.084ns - 81.9% - single tap - 19ps
@1875ps - 1.676ns - 89.4% - single tap - 15ps
@1500ps - 1.444ns - 96.3% - single tap - 11ps
@1250ps - 1.276ns - 102.1% - single tap - 9ps
@1072ps - 1.164ns - 108.6% - single tap - 8ps
@938ps - 1.076ns - 114.7% - single tap - 7ps
*/
// Fraction of a full DDR_TCK period
localparam real PO_STG1_INTRINSIC_DELAY = 0;
localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor
localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor
localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY +
(PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY);
// When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can
// go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this,
// a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments
// to the stage 2 delay can be made after reset is removed.
localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PO_CIRC_BUF_META_ZONE = 200.0;
localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0;
localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK;
// If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold
// If it is not more than the threshold than we must push the delay after the clock period plus a guardband.
//A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated.
localparam integer PO_CIRC_BUF_DELAY = 60;
//localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 :
// (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE :
// (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE;
localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE;
localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY;
localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY;
localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE);
localparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi
// The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path
// of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the
// oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment
// is within the range of the stage 2 delay line in the Phaser_In.
localparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY);
localparam integer PO_DELAY_INT = PO_DELAY;
localparam real PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK);
// if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is
// if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge.
// note that in this case PI_OFFSET is negative so invert before subtracting.
localparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0
? PI_OFFSET
: ((-PI_OFFSET) < DDR_TCK/2) ?
(DDR_TCK/2 - (- PI_OFFSET)) :
(DDR_TCK - (- PI_OFFSET)) ;
localparam real PI_STG2_DELAY =
(PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ?
PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND);
localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE;
localparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE));
localparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
wire _phy_clk;
wire [2:0] mcGo_w;
wire [HIGHEST_BANK-1:0] ref_dll_lock_w;
reg [15:0] mcGo_r;
assign ref_dll_lock = & ref_dll_lock_w;
initial begin
if ( SYNTHESIS == "FALSE" ) begin
$display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1);
$display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1);
$display("%m : HIGHEST_BANK = %d", HIGHEST_BANK);
$display("%m : FREQ_REF_PERIOD = %0.2f ", FREQ_REF_PERIOD);
$display("%m : DDR_TCK = %0d ", DDR_TCK);
$display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE);
$display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY);
$display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET);
$display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE);
$display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY);
$display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY);
$display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY);
$display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY);
$display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY);
$display("%m : PO_DELAY = %0.2f ", PO_DELAY);
$display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY);
$display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY);
$display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY);
$display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY);
$display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY);
$display("%m : PI_MAX_STG2_DELAY = %0.2f ", PI_MAX_STG2_DELAY);
$display("%m : PI_OFFSET = %0.2f ", PI_OFFSET);
if ( PI_OFFSET < 0) $display("%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used.");
$display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY);
$display("%m :PI_STG2_DELAY_CAND = %0.2f ",PI_STG2_DELAY_CAND);
$display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY);
$display("%m : RCLK_SELECT_EDGE = %0b ", LP_RCLK_SELECT_EDGE);
end // SYNTHESIS
if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display("WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY);
end
assign sync_pulse_split = sync_pulse;
assign mem_refclk_split = mem_refclk;
assign freq_refclk_split = freq_refclk;
assign mem_refclk_div4_split = mem_refclk_div4;
assign phy_ctl_clk_split0 = _phy_clk;
assign phy_ctl_wd_split0 = phy_ctl_wd;
assign phy_ctl_wr_split0 = phy_ctl_wr;
assign phy_clk_split0 = phy_clk;
assign phy_cmd_wr_en_split0 = phy_cmd_wr_en;
assign phy_data_wr_en_split0 = phy_data_wr_en;
assign phy_rd_en_split0 = phy_rd_en;
assign phy_dout_split0 = phy_dout;
assign phy_ctl_clk_split1 = phy_clk;
assign phy_ctl_wd_split1 = phy_ctl_wd;
assign phy_data_offset_1_split1 = data_offset_1;
assign phy_ctl_wr_split1 = phy_ctl_wr;
assign phy_clk_split1 = phy_clk;
assign phy_cmd_wr_en_split1 = phy_cmd_wr_en;
assign phy_data_wr_en_split1 = phy_data_wr_en;
assign phy_rd_en_split1 = phy_rd_en;
assign phy_dout_split1 = phy_dout;
assign phy_ctl_clk_split2 = phy_clk;
assign phy_ctl_wd_split2 = phy_ctl_wd;
assign phy_data_offset_2_split2 = data_offset_2;
assign phy_ctl_wr_split2 = phy_ctl_wr;
assign phy_clk_split2 = phy_clk;
assign phy_cmd_wr_en_split2 = phy_cmd_wr_en;
assign phy_data_wr_en_split2 = phy_data_wr_en;
assign phy_rd_en_split2 = phy_rd_en;
assign phy_dout_split2 = phy_dout;
// these wires are needed to coerce correct synthesis
// the synthesizer did not always see the widths of the
// parameters as 4 bits.
wire [3:0] blb0 = BYTE_LANES_B0;
wire [3:0] blb1 = BYTE_LANES_B1;
wire [3:0] blb2 = BYTE_LANES_B2;
wire [3:0] dcb0 = DATA_CTL_B0;
wire [3:0] dcb1 = DATA_CTL_B1;
wire [3:0] dcb2 = DATA_CTL_B2;
assign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0});
assign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0});
assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0];
assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs};
//Added to remove concadination in the instantiation
assign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ;
assign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ;
assign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ;
assign calib_zero_lanes_int = calib_zero_lanes;
assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0];
assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL];
assign of_ctl_a_full = |of_ctl_a_full_v;
assign of_ctl_full = |of_ctl_full_v;
assign of_data_a_full = |of_data_a_full_v;
assign of_data_full = |of_data_full_v;
assign pre_data_a_full= |pre_data_a_full_v;
// if if_empty_def == 1, empty is asserted only if all are empty;
// this allows the user to detect a skewed fifo depth and self-clear
// if desired. It avoids a reset to clear the flags.
assign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v;
assign if_empty_or = |if_empty_or_v;
assign if_empty_and = &if_empty_and_v;
assign if_a_empty = |if_a_empty_v;
generate
genvar i;
for (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen
case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff)
16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
default : initial $display("ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) ", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff ));
endcase
end
endgenerate
//assign rclk = rclk_w[RCLK_SELECT_BANK];
reg rst_auxout;
reg rst_auxout_r;
reg rst_auxout_rr;
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout_r <= #(1) 1'b1;
rst_auxout_rr <= #(1) 1'b1;
end
else begin
rst_auxout_r <= #(1) rst;
rst_auxout_rr <= #(1) rst_auxout_r;
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
else begin
always @(negedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
localparam L_RESET_SELECT_BANK =
(BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK;
always @(*) begin
rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n;
end
always @(posedge phy_clk or posedge rst) begin
if ( rst)
mcGo_r <= #(1) 0;
else
mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w;
end
assign mcGo = mcGo_r[15];
generate
// this is an optional 1 clock delay to add latency to the phy_control programming path
if (PHYCTL_CMD_FIFO == "TRUE") begin : cmd_fifo_soft
reg [31:0] phy_wd_reg = 0;
reg [3:0] aux_in1_reg = 0;
reg [3:0] aux_in2_reg = 0;
reg sfifo_ready = 0;
assign _phy_ctl_wd = phy_wd_reg;
assign aux_in_[1] = aux_in1_reg;
assign aux_in_[2] = aux_in2_reg;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[1] = |_phy_ctl_full_p;
assign phy_ctl_full[2] = |_phy_ctl_full_p;
assign phy_ctl_full[3] = |_phy_ctl_full_p;
assign _phy_clk = phy_clk;
always @(posedge phy_clk) begin
phy_wd_reg <= #1 phy_ctl_wd;
aux_in1_reg <= #1 aux_in_1;
aux_in2_reg <= #1 aux_in_2;
sfifo_ready <= #1 phy_ctl_wr;
end
end
else if (PHYCTL_CMD_FIFO == "FALSE") begin
assign _phy_ctl_wd = phy_ctl_wd;
assign aux_in_[1] = aux_in_1;
assign aux_in_[2] = aux_in_2;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[3:1] = 3'b000;
assign _phy_clk = phy_clk;
end
endgenerate
// instance of four-lane phy
generate
if (HIGHEST_BANK == 3) begin : banks_3
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]};
end
else if (HIGHEST_BANK == 2) begin : banks_2
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1};
end
else begin : banks_1
assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1};
end
if ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */
.DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY),
.BITLANES (PHY_0_BITLANES),
.BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK),
.LAST_BANK (PHY_0_IS_LAST_BANK),
.LANE_REMAP (PHY_0_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_0_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_0_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_0_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_0_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_0_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_0_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_0_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_0_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_0_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split0),
.phy_ctl_clk (phy_ctl_clk_split0),
.phy_ctl_wd (phy_ctl_wd_split0),
.data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]),
.phy_ctl_wr (phy_ctl_wr_split0),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]),
.phy_cmd_wr_en (phy_cmd_wr_en_split0),
.phy_data_wr_en (phy_data_wr_en_split0),
.phy_rd_en (phy_rd_en_split0),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[0]),
.rclk (),
.rst_out (rst_out_w[0]),
.mcGo (mcGo_w[0]),
.ref_dll_lock (ref_dll_lock_w[0]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]),
.if_a_empty (if_a_empty_v[0]),
.if_empty (if_empty_v[0]),
.byte_rd_en (byte_rd_en_v[0]),
.if_empty_or (if_empty_or_v[0]),
.if_empty_and (if_empty_and_v[0]),
.of_ctl_a_full (of_ctl_a_full_v[0]),
.of_data_a_full (of_data_a_full_v[0]),
.of_ctl_full (of_ctl_full_v[0]),
.of_data_full (of_data_full_v[0]),
.pre_data_a_full (pre_data_a_full_v[0]),
.phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]),
.phy_ctl_a_full (_phy_ctl_a_full_p[0]),
.phy_ctl_full (_phy_ctl_full_p[0]),
.phy_ctl_empty (phy_ctl_empty[0]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]),
.aux_out (aux_out_[3:0]),
.phy_ctl_ready (phy_ctl_ready_w[0]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte0),
.calib_zero_ctrl (calib_zero_ctrl[0]),
.calib_zero_lanes (calib_zero_lanes_int[3:0]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[0]),
.po_fine_enable (po_fine_enable[0]),
.po_fine_inc (po_fine_inc[0]),
.po_coarse_inc (po_coarse_inc[0]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[0]),
.po_fine_overflow (po_fine_overflow_w[0]),
.po_counter_read_val (po_counter_read_val_w[0]),
.pi_rst_dqs_find (pi_rst_dqs_find[0]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[0]),
.pi_counter_read_val (pi_counter_read_val_w[0]),
.pi_dqs_found (pi_dqs_found_w[0]),
.pi_dqs_found_all (pi_dqs_found_all_w[0]),
.pi_dqs_found_any (pi_dqs_found_any_w[0]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]),
.pi_phase_locked (pi_phase_locked_w[0]),
.pi_phase_locked_all (pi_phase_locked_all_w[0])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[0] <= #100 0;
aux_out[2] <= #100 0;
end
else begin
aux_out[0] <= #100 aux_out_[0];
aux_out[2] <= #100 aux_out_[2];
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
end
else begin
if ( HIGHEST_BANK > 0) begin
assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0;
assign _phy_ctl_a_full_p[0] = 0;
assign of_ctl_a_full_v[0] = 0;
assign of_ctl_full_v[0] = 0;
assign of_data_a_full_v[0] = 0;
assign of_data_full_v[0] = 0;
assign pre_data_a_full_v[0] = 0;
assign if_empty_v[0] = 0;
assign byte_rd_en_v[0] = 1;
always @(*)
aux_out[3:0] = 0;
end
assign pi_dqs_found_w[0] = 1;
assign pi_dqs_found_all_w[0] = 1;
assign pi_dqs_found_any_w[0] = 0;
assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_out_of_range_w[0] = 0;
assign pi_phase_locked_w[0] = 1;
assign po_fine_overflow_w[0] = 0;
assign po_coarse_overflow_w[0] = 0;
assign po_fine_overflow_w[0] = 0;
assign pi_fine_overflow_w[0] = 0;
assign po_counter_read_val_w[0] = 0;
assign pi_counter_read_val_w[0] = 0;
assign mcGo_w[0] = 1;
if ( RCLK_SELECT_BANK == 0)
always @(*)
aux_out[3:0] = 0;
end
if ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */
.DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY),
.BITLANES (PHY_1_BITLANES),
.BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK),
.LAST_BANK (PHY_1_IS_LAST_BANK ),
.LANE_REMAP (PHY_1_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_1_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_1_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_1_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_1_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_1_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_1_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_1_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_1_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_1_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_1_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_1_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_1_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_1_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split1),
.phy_ctl_clk (phy_ctl_clk_split1),
.phy_ctl_wd (phy_ctl_wd_split1),
.data_offset (phy_data_offset_1_split1),
.phy_ctl_wr (phy_ctl_wr_split1),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]),
.phy_cmd_wr_en (phy_cmd_wr_en_split1),
.phy_data_wr_en (phy_data_wr_en_split1),
.phy_rd_en (phy_rd_en_split1),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[1]),
.rclk (),
.rst_out (rst_out_w[1]),
.mcGo (mcGo_w[1]),
.ref_dll_lock (ref_dll_lock_w[1]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]),
.if_a_empty (if_a_empty_v[1]),
.if_empty (if_empty_v[1]),
.byte_rd_en (byte_rd_en_v[1]),
.if_empty_or (if_empty_or_v[1]),
.if_empty_and (if_empty_and_v[1]),
.of_ctl_a_full (of_ctl_a_full_v[1]),
.of_data_a_full (of_data_a_full_v[1]),
.of_ctl_full (of_ctl_full_v[1]),
.of_data_full (of_data_full_v[1]),
.pre_data_a_full (pre_data_a_full_v[1]),
.phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]),
.phy_ctl_a_full (_phy_ctl_a_full_p[1]),
.phy_ctl_full (_phy_ctl_full_p[1]),
.phy_ctl_empty (phy_ctl_empty[1]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]),
.aux_out (aux_out_[7:4]),
.phy_ctl_ready (phy_ctl_ready_w[1]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte1),
.calib_zero_ctrl (calib_zero_ctrl[1]),
.calib_zero_lanes (calib_zero_lanes_int[7:4]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[1]),
.po_fine_enable (po_fine_enable[1]),
.po_fine_inc (po_fine_inc[1]),
.po_coarse_inc (po_coarse_inc[1]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[1]),
.po_fine_overflow (po_fine_overflow_w[1]),
.po_counter_read_val (po_counter_read_val_w[1]),
.pi_rst_dqs_find (pi_rst_dqs_find[1]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[1]),
.pi_counter_read_val (pi_counter_read_val_w[1]),
.pi_dqs_found (pi_dqs_found_w[1]),
.pi_dqs_found_all (pi_dqs_found_all_w[1]),
.pi_dqs_found_any (pi_dqs_found_any_w[1]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]),
.pi_phase_locked (pi_phase_locked_w[1]),
.pi_phase_locked_all (pi_phase_locked_all_w[1])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[4] <= #100 0;
aux_out[6] <= #100 0;
end
else begin
aux_out[4] <= #100 aux_out_[4];
aux_out[6] <= #100 aux_out_[6];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
end
else begin
if ( HIGHEST_BANK > 1) begin
assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0;
assign _phy_ctl_a_full_p[1] = 0;
assign of_ctl_a_full_v[1] = 0;
assign of_ctl_full_v[1] = 0;
assign of_data_a_full_v[1] = 0;
assign of_data_full_v[1] = 0;
assign pre_data_a_full_v[1] = 0;
assign if_empty_v[1] = 0;
assign byte_rd_en_v[1] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
always @(*)
aux_out[7:4] = 0;
end
assign pi_dqs_found_w[1] = 1;
assign pi_dqs_found_all_w[1] = 1;
assign pi_dqs_found_any_w[1] = 0;
assign pi_dqs_out_of_range_w[1] = 0;
assign pi_phase_locked_w[1] = 1;
assign po_coarse_overflow_w[1] = 0;
assign po_fine_overflow_w[1] = 0;
assign pi_fine_overflow_w[1] = 0;
assign po_counter_read_val_w[1] = 0;
assign pi_counter_read_val_w[1] = 0;
assign mcGo_w[1] = 1;
end
if ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */
.DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY),
.BITLANES (PHY_2_BITLANES),
.BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK),
.LAST_BANK (PHY_2_IS_LAST_BANK ),
.LANE_REMAP (PHY_2_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_2_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_2_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_2_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_2_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_2_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_2_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_2_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_2_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_2_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_2_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_2_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_2_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_2_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split2),
.phy_ctl_clk (phy_ctl_clk_split2),
.phy_ctl_wd (phy_ctl_wd_split2),
.data_offset (phy_data_offset_2_split2),
.phy_ctl_wr (phy_ctl_wr_split2),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]),
.phy_cmd_wr_en (phy_cmd_wr_en_split2),
.phy_data_wr_en (phy_data_wr_en_split2),
.phy_rd_en (phy_rd_en_split2),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[2]),
.rclk (),
.rst_out (rst_out_w[2]),
.mcGo (mcGo_w[2]),
.ref_dll_lock (ref_dll_lock_w[2]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]),
.if_a_empty (if_a_empty_v[2]),
.if_empty (if_empty_v[2]),
.byte_rd_en (byte_rd_en_v[2]),
.if_empty_or (if_empty_or_v[2]),
.if_empty_and (if_empty_and_v[2]),
.of_ctl_a_full (of_ctl_a_full_v[2]),
.of_data_a_full (of_data_a_full_v[2]),
.of_ctl_full (of_ctl_full_v[2]),
.of_data_full (of_data_full_v[2]),
.pre_data_a_full (pre_data_a_full_v[2]),
.phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]),
.phy_ctl_a_full (_phy_ctl_a_full_p[2]),
.phy_ctl_full (_phy_ctl_full_p[2]),
.phy_ctl_empty (phy_ctl_empty[2]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]),
.aux_out (aux_out_[11:8]),
.phy_ctl_ready (phy_ctl_ready_w[2]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte2),
.calib_zero_ctrl (calib_zero_ctrl[2]),
.calib_zero_lanes (calib_zero_lanes_int[11:8]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[2]),
.po_fine_enable (po_fine_enable[2]),
.po_fine_inc (po_fine_inc[2]),
.po_coarse_inc (po_coarse_inc[2]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[2]),
.po_fine_overflow (po_fine_overflow_w[2]),
.po_counter_read_val (po_counter_read_val_w[2]),
.pi_rst_dqs_find (pi_rst_dqs_find[2]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[2]),
.pi_counter_read_val (pi_counter_read_val_w[2]),
.pi_dqs_found (pi_dqs_found_w[2]),
.pi_dqs_found_all (pi_dqs_found_all_w[2]),
.pi_dqs_found_any (pi_dqs_found_any_w[2]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]),
.pi_phase_locked (pi_phase_locked_w[2]),
.pi_phase_locked_all (pi_phase_locked_all_w[2])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[8] <= #100 0;
aux_out[10] <= #100 0;
end
else begin
aux_out[8] <= #100 aux_out_[8];
aux_out[10] <= #100 aux_out_[10];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
end
else begin
if ( HIGHEST_BANK > 2) begin
assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0;
assign _phy_ctl_a_full_p[2] = 0;
assign of_ctl_a_full_v[2] = 0;
assign of_ctl_full_v[2] = 0;
assign of_data_a_full_v[2] = 0;
assign of_data_full_v[2] = 0;
assign pre_data_a_full_v[2] = 0;
assign if_empty_v[2] = 0;
assign byte_rd_en_v[2] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
always @(*)
aux_out[11:8] = 0;
end
assign pi_dqs_found_w[2] = 1;
assign pi_dqs_found_all_w[2] = 1;
assign pi_dqs_found_any_w[2] = 0;
assign pi_dqs_out_of_range_w[2] = 0;
assign pi_phase_locked_w[2] = 1;
assign po_coarse_overflow_w[2] = 0;
assign po_fine_overflow_w[2] = 0;
assign po_counter_read_val_w[2] = 0;
assign pi_counter_read_val_w[2] = 0;
assign mcGo_w[2] = 1;
end
endgenerate
generate
// for single bank , emit an extra phaser_in to generate rclk
// so that auxout can be placed in another region
// if desired
if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0)
begin : phaser_in_rclk
localparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY;
PHASER_IN_PHY #(
.BURST_MODE ( PHY_0_A_BURST_MODE),
.CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV),
.FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.FINE_DELAY ( L_EXTRA_PI_FINE_DELAY),
.OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC)
) phaser_in_rclk (
.DQSFOUND (),
.DQSOUTOFRANGE (),
.FINEOVERFLOW (),
.PHASELOCKED (),
.ISERDESRST (),
.ICLKDIV (),
.ICLK (),
.COUNTERREADVAL (),
.RCLK (),
.WRENABLE (),
.BURSTPENDINGPHY (),
.ENCALIBPHY (),
.FINEENABLE (0),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (0),
.PHASEREFCLK (),
.RSTDQSFIND (0),
.RST (rst),
.FINEINC (),
.COUNTERLOADEN (),
.COUNTERREADEN (),
.COUNTERLOADVAL (),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
end
endgenerate
always @(*) begin
case (calib_sel[5:3])
3'b000: begin
po_coarse_overflow = po_coarse_overflow_w[0];
po_fine_overflow = po_fine_overflow_w[0];
po_counter_read_val = po_counter_read_val_w[0];
pi_fine_overflow = pi_fine_overflow_w[0];
pi_counter_read_val = pi_counter_read_val_w[0];
pi_phase_locked = pi_phase_locked_w[0];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[0];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[0];
end
3'b001: begin
po_coarse_overflow = po_coarse_overflow_w[1];
po_fine_overflow = po_fine_overflow_w[1];
po_counter_read_val = po_counter_read_val_w[1];
pi_fine_overflow = pi_fine_overflow_w[1];
pi_counter_read_val = pi_counter_read_val_w[1];
pi_phase_locked = pi_phase_locked_w[1];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[1];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[1];
end
3'b010: begin
po_coarse_overflow = po_coarse_overflow_w[2];
po_fine_overflow = po_fine_overflow_w[2];
po_counter_read_val = po_counter_read_val_w[2];
pi_fine_overflow = pi_fine_overflow_w[2];
pi_counter_read_val = pi_counter_read_val_w[2];
pi_phase_locked = pi_phase_locked_w[2];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[2];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[2];
end
default: begin
po_coarse_overflow = 0;
po_fine_overflow = 0;
po_counter_read_val = 0;
pi_fine_overflow = 0;
pi_counter_read_val = 0;
pi_phase_locked = 0;
pi_dqs_found = 0;
pi_dqs_out_of_range = 0;
end
endcase
end
endmodule // mc_phy
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Properties of decidable propositions *)
Definition decidable (P:Prop) := P \/ ~ P.
Theorem dec_not_not : forall P:Prop, decidable P -> (~ P -> False) -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_True : decidable True.
Proof.
unfold decidable; auto.
Qed.
Theorem dec_False : decidable False.
Proof.
unfold decidable, not; auto.
Qed.
Theorem dec_or :
forall A B:Prop, decidable A -> decidable B -> decidable (A \/ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_and :
forall A B:Prop, decidable A -> decidable B -> decidable (A /\ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_not : forall A:Prop, decidable A -> decidable (~ A).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_imp :
forall A B:Prop, decidable A -> decidable B -> decidable (A -> B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_iff :
forall A B:Prop, decidable A -> decidable B -> decidable (A<->B).
Proof.
unfold decidable; tauto.
Qed.
Theorem not_not : forall P:Prop, decidable P -> ~ ~ P -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_or : forall A B:Prop, ~ (A \/ B) -> ~ A /\ ~ B.
Proof.
tauto.
Qed.
Theorem not_and : forall A B:Prop, decidable A -> ~ (A /\ B) -> ~ A \/ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_imp : forall A B:Prop, decidable A -> ~ (A -> B) -> A /\ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem imp_simp : forall A B:Prop, decidable A -> (A -> B) -> ~ A \/ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_iff :
forall A B:Prop, decidable A -> decidable B ->
~ (A <-> B) -> (A /\ ~ B) \/ (~ A /\ B).
Proof.
unfold decidable; tauto.
Qed.
(** Results formulated with iff, used in FSetDecide.
Negation are expanded since it is unclear whether setoid rewrite
will always perform conversion. *)
(** We begin with lemmas that, when read from left to right,
can be understood as ways to eliminate uses of [not]. *)
Theorem not_true_iff : (True -> False) <-> False.
Proof.
tauto.
Qed.
Theorem not_false_iff : (False -> False) <-> True.
Proof.
tauto.
Qed.
Theorem not_not_iff : forall A:Prop, decidable A ->
(((A -> False) -> False) <-> A).
Proof.
unfold decidable; tauto.
Qed.
Theorem contrapositive : forall A B:Prop, decidable A ->
(((A -> False) -> (B -> False)) <-> (B -> A)).
Proof.
unfold decidable; tauto.
Qed.
Lemma or_not_l_iff_1 : forall A B: Prop, decidable A ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_l_iff_2 : forall A B: Prop, decidable B ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_1 : forall A B: Prop, decidable A ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_2 : forall A B: Prop, decidable B ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma imp_not_l : forall A B: Prop, decidable A ->
(((A -> False) -> B) <-> (A \/ B)).
Proof.
unfold decidable. tauto.
Qed.
(** Moving Negations Around:
We have four lemmas that, when read from left to right,
describe how to push negations toward the leaves of a
proposition and, when read from right to left, describe
how to pull negations toward the top of a proposition. *)
Theorem not_or_iff : forall A B:Prop,
(A \/ B -> False) <-> (A -> False) /\ (B -> False).
Proof.
tauto.
Qed.
Lemma not_and_iff : forall A B:Prop,
(A /\ B -> False) <-> (A -> B -> False).
Proof.
tauto.
Qed.
Lemma not_imp_iff : forall A B:Prop, decidable A ->
(((A -> B) -> False) <-> A /\ (B -> False)).
Proof.
unfold decidable. tauto.
Qed.
Lemma not_imp_rev_iff : forall A B : Prop, decidable A ->
(((A -> B) -> False) <-> (B -> False) /\ A).
Proof.
unfold decidable. tauto.
Qed.
(* Functional relations on decidable co-domains are decidable *)
Theorem dec_functional_relation :
forall (X Y : Type) (A:X->Y->Prop), (forall y y' : Y, decidable (y=y')) ->
(forall x, exists! y, A x y) -> forall x y, decidable (A x y).
Proof.
intros X Y A Hdec H x y.
destruct (H x) as (y',(Hex,Huniq)).
destruct (Hdec y y') as [->|Hnot]; firstorder.
Qed.
(** With the following hint database, we can leverage [auto] to check
decidability of propositions. *)
Hint Resolve dec_True dec_False dec_or dec_and dec_imp dec_not dec_iff
: decidable_prop.
(** [solve_decidable using lib] will solve goals about the
decidability of a proposition, assisted by an auxiliary
database of lemmas. The database is intended to contain
lemmas stating the decidability of base propositions,
(e.g., the decidability of equality on a particular
inductive type). *)
Tactic Notation "solve_decidable" "using" ident(db) :=
match goal with
| |- decidable _ =>
solve [ auto 100 with decidable_prop db ]
end.
Tactic Notation "solve_decidable" :=
solve_decidable using core.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test case for parameterized module.
//
// When a module is instantiatied with parameter, there will be two modules in
// the tree and eventually one will be removed after param and deadifyModules.
//
// This test is to check that the removal of dead module will not cause
// compilation error. Possible error was/is seen as:
//
// pure virtual method called
// terminate called without an active exception
// %Error: Verilator aborted. Consider trying --debug --gdbbt
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jie Xu.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [71:0] ctrl;
wire [7:0] cl; // this line is added
memory #(.words(72)) i_memory (.clk (clk));
assign ctrl = i_memory.mem[0];
assign cl = i_memory.mem[0][7:0]; // and this line
endmodule
// memory module, which is used with parameter
module memory (clk);
input clk;
parameter words = 16384, bits = 72;
reg [bits-1 :0] mem[words-1 : 0];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test case for parameterized module.
//
// When a module is instantiatied with parameter, there will be two modules in
// the tree and eventually one will be removed after param and deadifyModules.
//
// This test is to check that the removal of dead module will not cause
// compilation error. Possible error was/is seen as:
//
// pure virtual method called
// terminate called without an active exception
// %Error: Verilator aborted. Consider trying --debug --gdbbt
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jie Xu.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [71:0] ctrl;
wire [7:0] cl; // this line is added
memory #(.words(72)) i_memory (.clk (clk));
assign ctrl = i_memory.mem[0];
assign cl = i_memory.mem[0][7:0]; // and this line
endmodule
// memory module, which is used with parameter
module memory (clk);
input clk;
parameter words = 16384, bits = 72;
reg [bits-1 :0] mem[words-1 : 0];
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_common.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Block for logic common to all rank machines. Contains
// a clock prescaler, and arbiters for refresh and periodic
// read functions.
`timescale 1 ps / 1 ps
module mig_7series_v1_9_rank_common #
(
parameter TCQ = 100,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCKESR = 4,
parameter nCK_PER_CLK = 2,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
maint_prescaler_tick_r, refresh_tick, maint_zq_r, maint_sre_r, maint_srx_r,
maint_req_r, maint_rank_r, clear_periodic_rd_request, periodic_rd_r,
periodic_rd_rank_r, app_ref_ack, app_zq_ack, app_sr_active, maint_ref_zq_wip,
// Inputs
clk, rst, init_calib_complete, app_ref_req, app_zq_req, app_sr_req,
insert_maint_r1, refresh_request, maint_wip_r, slot_0_present, slot_1_present,
periodic_rd_request, periodic_rd_ack_r
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input clk;
input rst;
// Maintenance and periodic read prescaler. Nominally 200 nS.
localparam ONE = 1;
localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1);
input init_calib_complete;
reg maint_prescaler_tick_r_lcl;
generate
begin : maint_prescaler
reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r;
reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns;
wire maint_prescaler_tick_ns =
(maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]);
always @(/*AS*/init_calib_complete or maint_prescaler_r
or maint_prescaler_tick_ns) begin
maint_prescaler_ns = maint_prescaler_r;
if (~init_calib_complete || maint_prescaler_tick_ns)
maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0];
else if (|maint_prescaler_r)
maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0];
end
always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns;
always @(posedge clk) maint_prescaler_tick_r_lcl <=
#TCQ maint_prescaler_tick_ns;
end
endgenerate
output wire maint_prescaler_tick_r;
assign maint_prescaler_tick_r = maint_prescaler_tick_r_lcl;
// Refresh timebase. Nominically 7800 nS.
localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER_DIV + /*idle*/ 1);
wire refresh_tick_lcl;
generate
begin : refresh_timer
reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_r;
reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl
or refresh_tick_lcl or refresh_timer_r) begin
refresh_timer_ns = refresh_timer_r;
if (~init_calib_complete || refresh_tick_lcl)
refresh_timer_ns = REFRESH_TIMER_DIV[REFRESH_TIMER_WIDTH-1:0];
else if (|refresh_timer_r && maint_prescaler_tick_r_lcl)
refresh_timer_ns =
refresh_timer_r - ONE[REFRESH_TIMER_WIDTH-1:0];
end
always @(posedge clk) refresh_timer_r <= #TCQ refresh_timer_ns;
assign refresh_tick_lcl = (refresh_timer_r ==
ONE[REFRESH_TIMER_WIDTH-1:0]) && maint_prescaler_tick_r_lcl;
end
endgenerate
output wire refresh_tick;
assign refresh_tick = refresh_tick_lcl;
// ZQ timebase. Nominally 128 mS
localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1);
input app_zq_req;
input insert_maint_r1;
reg maint_zq_r_lcl;
reg zq_request = 1'b0;
generate
if (DRAM_TYPE == "DDR3") begin : zq_cntrl
reg zq_tick = 1'b0;
if (ZQ_TIMER_DIV !=0) begin : zq_timer
reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r;
reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl
or zq_tick or zq_timer_r) begin
zq_timer_ns = zq_timer_r;
if (~init_calib_complete || zq_tick)
zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0];
else if (|zq_timer_r && maint_prescaler_tick_r_lcl)
zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0];
end
always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns;
always @(/*AS*/maint_prescaler_tick_r_lcl or zq_timer_r)
zq_tick = (zq_timer_r ==
ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick_r_lcl);
end // zq_timer
// ZQ request. Set request with timer tick, and when exiting PHY init. Never
// request if ZQ_TIMER_DIV == 0.
begin : zq_request_logic
wire zq_clears_zq_request = insert_maint_r1 && maint_zq_r_lcl;
reg zq_request_r;
wire zq_request_ns = ~rst && (DRAM_TYPE == "DDR3") &&
((~init_calib_complete && (ZQ_TIMER_DIV != 0)) ||
(zq_request_r && ~zq_clears_zq_request) ||
zq_tick ||
(app_zq_req && init_calib_complete));
always @(posedge clk) zq_request_r <= #TCQ zq_request_ns;
always @(/*AS*/init_calib_complete or zq_request_r)
zq_request = init_calib_complete && zq_request_r;
end // zq_request_logic
end
endgenerate
// Self-refresh control
localparam nCKESR_CLKS = (nCKESR / nCK_PER_CLK) + (nCKESR % nCK_PER_CLK ? 1 : 0);
localparam CKESR_TIMER_WIDTH = clogb2(nCKESR_CLKS + 1);
input app_sr_req;
reg maint_sre_r_lcl;
reg maint_srx_r_lcl;
reg sre_request = 1'b0;
wire inhbt_srx;
generate begin : sr_cntrl
// SRE request. Set request with user request.
begin : sre_request_logic
reg sre_request_r;
wire sre_clears_sre_request = insert_maint_r1 && maint_sre_r_lcl;
wire sre_request_ns = ~rst && ((sre_request_r && ~sre_clears_sre_request)
|| (app_sr_req && init_calib_complete && ~maint_sre_r_lcl));
always @(posedge clk) sre_request_r <= #TCQ sre_request_ns;
always @(init_calib_complete or sre_request_r)
sre_request = init_calib_complete && sre_request_r;
end // sre_request_logic
// CKESR timer: Self-Refresh must be maintained for a minimum of tCKESR
begin : ckesr_timer
reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_r = {CKESR_TIMER_WIDTH{1'b0}};
reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_ns = {CKESR_TIMER_WIDTH{1'b0}};
always @(insert_maint_r1 or ckesr_timer_r or maint_sre_r_lcl) begin
ckesr_timer_ns = ckesr_timer_r;
if (insert_maint_r1 && maint_sre_r_lcl)
ckesr_timer_ns = nCKESR_CLKS[CKESR_TIMER_WIDTH-1:0];
else if(|ckesr_timer_r)
ckesr_timer_ns = ckesr_timer_r - ONE[CKESR_TIMER_WIDTH-1:0];
end
always @(posedge clk) ckesr_timer_r <= #TCQ ckesr_timer_ns;
assign inhbt_srx = |ckesr_timer_r;
end // ckesr_timer
end
endgenerate
// DRAM maintenance operations of refresh and ZQ calibration, and self-refresh
// DRAM maintenance operations and self-refresh have their own channel in the
// queue. There is also a single, very simple bank machine
// dedicated to these operations. Its assumed that the
// maintenance operations can be completed quickly enough
// to avoid any queuing.
//
// ZQ, refresh and self-refresh requests share a channel into controller.
// Self-refresh is appended to the uppermost bit of the request bus and ZQ is
// appended just below that.
input[RANKS-1:0] refresh_request;
input maint_wip_r;
reg maint_req_r_lcl;
reg [RANK_WIDTH-1:0] maint_rank_r_lcl;
input [7:0] slot_0_present;
input [7:0] slot_1_present;
generate
begin : maintenance_request
// Maintenance request pipeline.
reg upd_last_master_r;
reg new_maint_rank_r;
wire maint_busy = upd_last_master_r || new_maint_rank_r ||
maint_req_r_lcl || maint_wip_r;
wire [RANKS+1:0] maint_request = {sre_request, zq_request, refresh_request[RANKS-1:0]};
wire upd_last_master_ns = |maint_request && ~maint_busy;
always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns;
always @(posedge clk) new_maint_rank_r <= #TCQ upd_last_master_r;
always @(posedge clk) maint_req_r_lcl <= #TCQ new_maint_rank_r;
// Arbitrate maintenance requests.
wire [RANKS+1:0] maint_grant_ns;
wire [RANKS+1:0] maint_grant_r;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (RANKS+2))
maint_arb0
(.grant_ns (maint_grant_ns),
.grant_r (maint_grant_r),
.upd_last_master (upd_last_master_r),
.current_master (maint_grant_r),
.req (maint_request),
.disable_grant (1'b0),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
// Look at arbitration results. Decide if ZQ, refresh or self-refresh.
// If refresh select the maintenance rank from the winning rank controller.
// If ZQ or self-refresh, generate a sequence of rank numbers corresponding to
// slots populated maint_rank_r is not used for comparisons in the queue for ZQ
// or self-refresh requests. The bank machine will enable CS for the number of
// states equal to the the number of occupied slots. This will produce a
// command to every occupied slot, but not in any particular order.
wire [7:0] present = slot_0_present | slot_1_present;
integer i;
reg [RANK_WIDTH-1:0] maint_rank_ns;
wire maint_zq_ns = ~rst && (upd_last_master_r
? maint_grant_r[RANKS]
: maint_zq_r_lcl);
wire maint_srx_ns = ~rst && (maint_sre_r_lcl
? ~app_sr_req & ~inhbt_srx
: maint_srx_r_lcl && upd_last_master_r
? maint_grant_r[RANKS+1]
: maint_srx_r_lcl);
wire maint_sre_ns = ~rst && (upd_last_master_r
? maint_grant_r[RANKS+1]
: maint_sre_r_lcl && ~maint_srx_ns);
always @(/*AS*/maint_grant_r or maint_rank_r_lcl or maint_zq_ns
or maint_sre_ns or maint_srx_ns or present or rst
or upd_last_master_r) begin
if (rst) maint_rank_ns = {RANK_WIDTH{1'b0}};
else begin
maint_rank_ns = maint_rank_r_lcl;
if (maint_zq_ns || maint_sre_ns || maint_srx_ns) begin
maint_rank_ns = maint_rank_r_lcl + ONE[RANK_WIDTH-1:0];
for (i=0; i<8; i=i+1)
if (~present[maint_rank_ns])
maint_rank_ns = maint_rank_ns + ONE[RANK_WIDTH-1:0];
end
else
if (upd_last_master_r)
for (i=0; i<RANKS; i=i+1)
if (maint_grant_r[i]) maint_rank_ns = i[RANK_WIDTH-1:0];
end
end
always @(posedge clk) maint_rank_r_lcl <= #TCQ maint_rank_ns;
always @(posedge clk) maint_zq_r_lcl <= #TCQ maint_zq_ns;
always @(posedge clk) maint_sre_r_lcl <= #TCQ maint_sre_ns;
always @(posedge clk) maint_srx_r_lcl <= #TCQ maint_srx_ns;
end // block: maintenance_request
endgenerate
output wire maint_zq_r;
assign maint_zq_r = maint_zq_r_lcl;
output wire maint_sre_r;
assign maint_sre_r = maint_sre_r_lcl;
output wire maint_srx_r;
assign maint_srx_r = maint_srx_r_lcl;
output wire maint_req_r;
assign maint_req_r = maint_req_r_lcl;
output wire [RANK_WIDTH-1:0] maint_rank_r;
assign maint_rank_r = maint_rank_r_lcl;
// Indicate whether self-refresh is active or not.
output app_sr_active;
reg app_sr_active_r;
wire app_sr_active_ns =
insert_maint_r1 ? maint_sre_r && ~maint_srx_r : app_sr_active_r;
always @(posedge clk) app_sr_active_r <= #TCQ app_sr_active_ns;
assign app_sr_active = app_sr_active_r;
// Acknowledge user REF and ZQ Requests
input app_ref_req;
output app_ref_ack;
wire app_ref_ack_ns;
wire app_ref_ns;
reg app_ref_ack_r = 1'b0;
reg app_ref_r = 1'b0;
assign app_ref_ns = init_calib_complete && (app_ref_req || app_ref_r && |refresh_request);
assign app_ref_ack_ns = app_ref_r && ~|refresh_request;
always @(posedge clk) app_ref_r <= #TCQ app_ref_ns;
always @(posedge clk) app_ref_ack_r <= #TCQ app_ref_ack_ns;
assign app_ref_ack = app_ref_ack_r;
output app_zq_ack;
wire app_zq_ack_ns;
wire app_zq_ns;
reg app_zq_ack_r = 1'b0;
reg app_zq_r = 1'b0;
assign app_zq_ns = init_calib_complete && (app_zq_req || app_zq_r && zq_request);
assign app_zq_ack_ns = app_zq_r && ~zq_request;
always @(posedge clk) app_zq_r <= #TCQ app_zq_ns;
always @(posedge clk) app_zq_ack_r <= #TCQ app_zq_ack_ns;
assign app_zq_ack = app_zq_ack_r;
// Periodic reads to maintain PHY alignment.
// Demand insertion of periodic read as soon as
// possible. Since the is a single rank, bank compare mechanism
// must be used, periodic reads must be forced in at the
// expense of not accepting a normal request.
input [RANKS-1:0] periodic_rd_request;
reg periodic_rd_r_lcl;
reg [RANK_WIDTH-1:0] periodic_rd_rank_r_lcl;
input periodic_rd_ack_r;
output wire [RANKS-1:0] clear_periodic_rd_request;
output wire periodic_rd_r;
output wire [RANK_WIDTH-1:0] periodic_rd_rank_r;
generate
// This is not needed in 7-Series and should remain disabled
if ( PERIODIC_RD_TIMER_DIV != 0 ) begin : periodic_read_request
// Maintenance request pipeline.
reg periodic_rd_r_cnt;
wire int_periodic_rd_ack_r = (periodic_rd_ack_r && periodic_rd_r_cnt);
reg upd_last_master_r;
wire periodic_rd_busy = upd_last_master_r || periodic_rd_r_lcl;
wire upd_last_master_ns =
init_calib_complete && (|periodic_rd_request && ~periodic_rd_busy);
always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns;
wire periodic_rd_ns = init_calib_complete &&
(upd_last_master_r || (periodic_rd_r_lcl && ~int_periodic_rd_ack_r));
always @(posedge clk) periodic_rd_r_lcl <= #TCQ periodic_rd_ns;
always @(posedge clk) begin
if (rst) periodic_rd_r_cnt <= #TCQ 1'b0;
else if (periodic_rd_r_lcl && periodic_rd_ack_r)
periodic_rd_r_cnt <= ~periodic_rd_r_cnt;
end
// Arbitrate periodic read requests.
wire [RANKS-1:0] periodic_rd_grant_ns;
reg [RANKS-1:0] periodic_rd_grant_r;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (RANKS))
periodic_rd_arb0
(.grant_ns (periodic_rd_grant_ns[RANKS-1:0]),
.grant_r (),
.upd_last_master (upd_last_master_r),
.current_master (periodic_rd_grant_r[RANKS-1:0]),
.req (periodic_rd_request[RANKS-1:0]),
.disable_grant (1'b0),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
always @(posedge clk) periodic_rd_grant_r = upd_last_master_ns
? periodic_rd_grant_ns
: periodic_rd_grant_r;
// Encode and set periodic read rank into periodic_rd_rank_r.
integer i;
reg [RANK_WIDTH-1:0] periodic_rd_rank_ns;
always @(/*AS*/periodic_rd_grant_r or periodic_rd_rank_r_lcl
or upd_last_master_r) begin
periodic_rd_rank_ns = periodic_rd_rank_r_lcl;
if (upd_last_master_r)
for (i=0; i<RANKS; i=i+1)
if (periodic_rd_grant_r[i])
periodic_rd_rank_ns = i[RANK_WIDTH-1:0];
end
always @(posedge clk) periodic_rd_rank_r_lcl <=
#TCQ periodic_rd_rank_ns;
// Once the request is dropped in the queue, it might be a while before it
// emerges. Can't clear the request based on seeing the read issued.
// Need to clear the request as soon as its made it into the queue.
assign clear_periodic_rd_request =
periodic_rd_grant_r & {RANKS{periodic_rd_ack_r}};
assign periodic_rd_r = periodic_rd_r_lcl;
assign periodic_rd_rank_r = periodic_rd_rank_r_lcl;
end else begin
// Disable periodic reads
assign clear_periodic_rd_request = {RANKS{1'b0}};
assign periodic_rd_r = 1'b0;
assign periodic_rd_rank_r = {RANK_WIDTH{1'b0}};
end // block: periodic_read_request
endgenerate
// Indicate that a refresh is in progress. The PHY will use this to schedule
// tap adjustments during idle bus time
reg maint_ref_zq_wip_r = 1'b0;
output maint_ref_zq_wip;
always @(posedge clk)
if(rst)
maint_ref_zq_wip_r <= #TCQ 1'b0;
else if((zq_request || |refresh_request) && insert_maint_r1)
maint_ref_zq_wip_r <= #TCQ 1'b1;
else if(~maint_wip_r)
maint_ref_zq_wip_r <= #TCQ 1'b0;
assign maint_ref_zq_wip = maint_ref_zq_wip_r;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_common.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Block for logic common to all rank machines. Contains
// a clock prescaler, and arbiters for refresh and periodic
// read functions.
`timescale 1 ps / 1 ps
module mig_7series_v1_9_rank_common #
(
parameter TCQ = 100,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCKESR = 4,
parameter nCK_PER_CLK = 2,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
maint_prescaler_tick_r, refresh_tick, maint_zq_r, maint_sre_r, maint_srx_r,
maint_req_r, maint_rank_r, clear_periodic_rd_request, periodic_rd_r,
periodic_rd_rank_r, app_ref_ack, app_zq_ack, app_sr_active, maint_ref_zq_wip,
// Inputs
clk, rst, init_calib_complete, app_ref_req, app_zq_req, app_sr_req,
insert_maint_r1, refresh_request, maint_wip_r, slot_0_present, slot_1_present,
periodic_rd_request, periodic_rd_ack_r
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input clk;
input rst;
// Maintenance and periodic read prescaler. Nominally 200 nS.
localparam ONE = 1;
localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1);
input init_calib_complete;
reg maint_prescaler_tick_r_lcl;
generate
begin : maint_prescaler
reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r;
reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns;
wire maint_prescaler_tick_ns =
(maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]);
always @(/*AS*/init_calib_complete or maint_prescaler_r
or maint_prescaler_tick_ns) begin
maint_prescaler_ns = maint_prescaler_r;
if (~init_calib_complete || maint_prescaler_tick_ns)
maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0];
else if (|maint_prescaler_r)
maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0];
end
always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns;
always @(posedge clk) maint_prescaler_tick_r_lcl <=
#TCQ maint_prescaler_tick_ns;
end
endgenerate
output wire maint_prescaler_tick_r;
assign maint_prescaler_tick_r = maint_prescaler_tick_r_lcl;
// Refresh timebase. Nominically 7800 nS.
localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER_DIV + /*idle*/ 1);
wire refresh_tick_lcl;
generate
begin : refresh_timer
reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_r;
reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl
or refresh_tick_lcl or refresh_timer_r) begin
refresh_timer_ns = refresh_timer_r;
if (~init_calib_complete || refresh_tick_lcl)
refresh_timer_ns = REFRESH_TIMER_DIV[REFRESH_TIMER_WIDTH-1:0];
else if (|refresh_timer_r && maint_prescaler_tick_r_lcl)
refresh_timer_ns =
refresh_timer_r - ONE[REFRESH_TIMER_WIDTH-1:0];
end
always @(posedge clk) refresh_timer_r <= #TCQ refresh_timer_ns;
assign refresh_tick_lcl = (refresh_timer_r ==
ONE[REFRESH_TIMER_WIDTH-1:0]) && maint_prescaler_tick_r_lcl;
end
endgenerate
output wire refresh_tick;
assign refresh_tick = refresh_tick_lcl;
// ZQ timebase. Nominally 128 mS
localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1);
input app_zq_req;
input insert_maint_r1;
reg maint_zq_r_lcl;
reg zq_request = 1'b0;
generate
if (DRAM_TYPE == "DDR3") begin : zq_cntrl
reg zq_tick = 1'b0;
if (ZQ_TIMER_DIV !=0) begin : zq_timer
reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r;
reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl
or zq_tick or zq_timer_r) begin
zq_timer_ns = zq_timer_r;
if (~init_calib_complete || zq_tick)
zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0];
else if (|zq_timer_r && maint_prescaler_tick_r_lcl)
zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0];
end
always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns;
always @(/*AS*/maint_prescaler_tick_r_lcl or zq_timer_r)
zq_tick = (zq_timer_r ==
ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick_r_lcl);
end // zq_timer
// ZQ request. Set request with timer tick, and when exiting PHY init. Never
// request if ZQ_TIMER_DIV == 0.
begin : zq_request_logic
wire zq_clears_zq_request = insert_maint_r1 && maint_zq_r_lcl;
reg zq_request_r;
wire zq_request_ns = ~rst && (DRAM_TYPE == "DDR3") &&
((~init_calib_complete && (ZQ_TIMER_DIV != 0)) ||
(zq_request_r && ~zq_clears_zq_request) ||
zq_tick ||
(app_zq_req && init_calib_complete));
always @(posedge clk) zq_request_r <= #TCQ zq_request_ns;
always @(/*AS*/init_calib_complete or zq_request_r)
zq_request = init_calib_complete && zq_request_r;
end // zq_request_logic
end
endgenerate
// Self-refresh control
localparam nCKESR_CLKS = (nCKESR / nCK_PER_CLK) + (nCKESR % nCK_PER_CLK ? 1 : 0);
localparam CKESR_TIMER_WIDTH = clogb2(nCKESR_CLKS + 1);
input app_sr_req;
reg maint_sre_r_lcl;
reg maint_srx_r_lcl;
reg sre_request = 1'b0;
wire inhbt_srx;
generate begin : sr_cntrl
// SRE request. Set request with user request.
begin : sre_request_logic
reg sre_request_r;
wire sre_clears_sre_request = insert_maint_r1 && maint_sre_r_lcl;
wire sre_request_ns = ~rst && ((sre_request_r && ~sre_clears_sre_request)
|| (app_sr_req && init_calib_complete && ~maint_sre_r_lcl));
always @(posedge clk) sre_request_r <= #TCQ sre_request_ns;
always @(init_calib_complete or sre_request_r)
sre_request = init_calib_complete && sre_request_r;
end // sre_request_logic
// CKESR timer: Self-Refresh must be maintained for a minimum of tCKESR
begin : ckesr_timer
reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_r = {CKESR_TIMER_WIDTH{1'b0}};
reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_ns = {CKESR_TIMER_WIDTH{1'b0}};
always @(insert_maint_r1 or ckesr_timer_r or maint_sre_r_lcl) begin
ckesr_timer_ns = ckesr_timer_r;
if (insert_maint_r1 && maint_sre_r_lcl)
ckesr_timer_ns = nCKESR_CLKS[CKESR_TIMER_WIDTH-1:0];
else if(|ckesr_timer_r)
ckesr_timer_ns = ckesr_timer_r - ONE[CKESR_TIMER_WIDTH-1:0];
end
always @(posedge clk) ckesr_timer_r <= #TCQ ckesr_timer_ns;
assign inhbt_srx = |ckesr_timer_r;
end // ckesr_timer
end
endgenerate
// DRAM maintenance operations of refresh and ZQ calibration, and self-refresh
// DRAM maintenance operations and self-refresh have their own channel in the
// queue. There is also a single, very simple bank machine
// dedicated to these operations. Its assumed that the
// maintenance operations can be completed quickly enough
// to avoid any queuing.
//
// ZQ, refresh and self-refresh requests share a channel into controller.
// Self-refresh is appended to the uppermost bit of the request bus and ZQ is
// appended just below that.
input[RANKS-1:0] refresh_request;
input maint_wip_r;
reg maint_req_r_lcl;
reg [RANK_WIDTH-1:0] maint_rank_r_lcl;
input [7:0] slot_0_present;
input [7:0] slot_1_present;
generate
begin : maintenance_request
// Maintenance request pipeline.
reg upd_last_master_r;
reg new_maint_rank_r;
wire maint_busy = upd_last_master_r || new_maint_rank_r ||
maint_req_r_lcl || maint_wip_r;
wire [RANKS+1:0] maint_request = {sre_request, zq_request, refresh_request[RANKS-1:0]};
wire upd_last_master_ns = |maint_request && ~maint_busy;
always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns;
always @(posedge clk) new_maint_rank_r <= #TCQ upd_last_master_r;
always @(posedge clk) maint_req_r_lcl <= #TCQ new_maint_rank_r;
// Arbitrate maintenance requests.
wire [RANKS+1:0] maint_grant_ns;
wire [RANKS+1:0] maint_grant_r;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (RANKS+2))
maint_arb0
(.grant_ns (maint_grant_ns),
.grant_r (maint_grant_r),
.upd_last_master (upd_last_master_r),
.current_master (maint_grant_r),
.req (maint_request),
.disable_grant (1'b0),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
// Look at arbitration results. Decide if ZQ, refresh or self-refresh.
// If refresh select the maintenance rank from the winning rank controller.
// If ZQ or self-refresh, generate a sequence of rank numbers corresponding to
// slots populated maint_rank_r is not used for comparisons in the queue for ZQ
// or self-refresh requests. The bank machine will enable CS for the number of
// states equal to the the number of occupied slots. This will produce a
// command to every occupied slot, but not in any particular order.
wire [7:0] present = slot_0_present | slot_1_present;
integer i;
reg [RANK_WIDTH-1:0] maint_rank_ns;
wire maint_zq_ns = ~rst && (upd_last_master_r
? maint_grant_r[RANKS]
: maint_zq_r_lcl);
wire maint_srx_ns = ~rst && (maint_sre_r_lcl
? ~app_sr_req & ~inhbt_srx
: maint_srx_r_lcl && upd_last_master_r
? maint_grant_r[RANKS+1]
: maint_srx_r_lcl);
wire maint_sre_ns = ~rst && (upd_last_master_r
? maint_grant_r[RANKS+1]
: maint_sre_r_lcl && ~maint_srx_ns);
always @(/*AS*/maint_grant_r or maint_rank_r_lcl or maint_zq_ns
or maint_sre_ns or maint_srx_ns or present or rst
or upd_last_master_r) begin
if (rst) maint_rank_ns = {RANK_WIDTH{1'b0}};
else begin
maint_rank_ns = maint_rank_r_lcl;
if (maint_zq_ns || maint_sre_ns || maint_srx_ns) begin
maint_rank_ns = maint_rank_r_lcl + ONE[RANK_WIDTH-1:0];
for (i=0; i<8; i=i+1)
if (~present[maint_rank_ns])
maint_rank_ns = maint_rank_ns + ONE[RANK_WIDTH-1:0];
end
else
if (upd_last_master_r)
for (i=0; i<RANKS; i=i+1)
if (maint_grant_r[i]) maint_rank_ns = i[RANK_WIDTH-1:0];
end
end
always @(posedge clk) maint_rank_r_lcl <= #TCQ maint_rank_ns;
always @(posedge clk) maint_zq_r_lcl <= #TCQ maint_zq_ns;
always @(posedge clk) maint_sre_r_lcl <= #TCQ maint_sre_ns;
always @(posedge clk) maint_srx_r_lcl <= #TCQ maint_srx_ns;
end // block: maintenance_request
endgenerate
output wire maint_zq_r;
assign maint_zq_r = maint_zq_r_lcl;
output wire maint_sre_r;
assign maint_sre_r = maint_sre_r_lcl;
output wire maint_srx_r;
assign maint_srx_r = maint_srx_r_lcl;
output wire maint_req_r;
assign maint_req_r = maint_req_r_lcl;
output wire [RANK_WIDTH-1:0] maint_rank_r;
assign maint_rank_r = maint_rank_r_lcl;
// Indicate whether self-refresh is active or not.
output app_sr_active;
reg app_sr_active_r;
wire app_sr_active_ns =
insert_maint_r1 ? maint_sre_r && ~maint_srx_r : app_sr_active_r;
always @(posedge clk) app_sr_active_r <= #TCQ app_sr_active_ns;
assign app_sr_active = app_sr_active_r;
// Acknowledge user REF and ZQ Requests
input app_ref_req;
output app_ref_ack;
wire app_ref_ack_ns;
wire app_ref_ns;
reg app_ref_ack_r = 1'b0;
reg app_ref_r = 1'b0;
assign app_ref_ns = init_calib_complete && (app_ref_req || app_ref_r && |refresh_request);
assign app_ref_ack_ns = app_ref_r && ~|refresh_request;
always @(posedge clk) app_ref_r <= #TCQ app_ref_ns;
always @(posedge clk) app_ref_ack_r <= #TCQ app_ref_ack_ns;
assign app_ref_ack = app_ref_ack_r;
output app_zq_ack;
wire app_zq_ack_ns;
wire app_zq_ns;
reg app_zq_ack_r = 1'b0;
reg app_zq_r = 1'b0;
assign app_zq_ns = init_calib_complete && (app_zq_req || app_zq_r && zq_request);
assign app_zq_ack_ns = app_zq_r && ~zq_request;
always @(posedge clk) app_zq_r <= #TCQ app_zq_ns;
always @(posedge clk) app_zq_ack_r <= #TCQ app_zq_ack_ns;
assign app_zq_ack = app_zq_ack_r;
// Periodic reads to maintain PHY alignment.
// Demand insertion of periodic read as soon as
// possible. Since the is a single rank, bank compare mechanism
// must be used, periodic reads must be forced in at the
// expense of not accepting a normal request.
input [RANKS-1:0] periodic_rd_request;
reg periodic_rd_r_lcl;
reg [RANK_WIDTH-1:0] periodic_rd_rank_r_lcl;
input periodic_rd_ack_r;
output wire [RANKS-1:0] clear_periodic_rd_request;
output wire periodic_rd_r;
output wire [RANK_WIDTH-1:0] periodic_rd_rank_r;
generate
// This is not needed in 7-Series and should remain disabled
if ( PERIODIC_RD_TIMER_DIV != 0 ) begin : periodic_read_request
// Maintenance request pipeline.
reg periodic_rd_r_cnt;
wire int_periodic_rd_ack_r = (periodic_rd_ack_r && periodic_rd_r_cnt);
reg upd_last_master_r;
wire periodic_rd_busy = upd_last_master_r || periodic_rd_r_lcl;
wire upd_last_master_ns =
init_calib_complete && (|periodic_rd_request && ~periodic_rd_busy);
always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns;
wire periodic_rd_ns = init_calib_complete &&
(upd_last_master_r || (periodic_rd_r_lcl && ~int_periodic_rd_ack_r));
always @(posedge clk) periodic_rd_r_lcl <= #TCQ periodic_rd_ns;
always @(posedge clk) begin
if (rst) periodic_rd_r_cnt <= #TCQ 1'b0;
else if (periodic_rd_r_lcl && periodic_rd_ack_r)
periodic_rd_r_cnt <= ~periodic_rd_r_cnt;
end
// Arbitrate periodic read requests.
wire [RANKS-1:0] periodic_rd_grant_ns;
reg [RANKS-1:0] periodic_rd_grant_r;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (RANKS))
periodic_rd_arb0
(.grant_ns (periodic_rd_grant_ns[RANKS-1:0]),
.grant_r (),
.upd_last_master (upd_last_master_r),
.current_master (periodic_rd_grant_r[RANKS-1:0]),
.req (periodic_rd_request[RANKS-1:0]),
.disable_grant (1'b0),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
always @(posedge clk) periodic_rd_grant_r = upd_last_master_ns
? periodic_rd_grant_ns
: periodic_rd_grant_r;
// Encode and set periodic read rank into periodic_rd_rank_r.
integer i;
reg [RANK_WIDTH-1:0] periodic_rd_rank_ns;
always @(/*AS*/periodic_rd_grant_r or periodic_rd_rank_r_lcl
or upd_last_master_r) begin
periodic_rd_rank_ns = periodic_rd_rank_r_lcl;
if (upd_last_master_r)
for (i=0; i<RANKS; i=i+1)
if (periodic_rd_grant_r[i])
periodic_rd_rank_ns = i[RANK_WIDTH-1:0];
end
always @(posedge clk) periodic_rd_rank_r_lcl <=
#TCQ periodic_rd_rank_ns;
// Once the request is dropped in the queue, it might be a while before it
// emerges. Can't clear the request based on seeing the read issued.
// Need to clear the request as soon as its made it into the queue.
assign clear_periodic_rd_request =
periodic_rd_grant_r & {RANKS{periodic_rd_ack_r}};
assign periodic_rd_r = periodic_rd_r_lcl;
assign periodic_rd_rank_r = periodic_rd_rank_r_lcl;
end else begin
// Disable periodic reads
assign clear_periodic_rd_request = {RANKS{1'b0}};
assign periodic_rd_r = 1'b0;
assign periodic_rd_rank_r = {RANK_WIDTH{1'b0}};
end // block: periodic_read_request
endgenerate
// Indicate that a refresh is in progress. The PHY will use this to schedule
// tap adjustments during idle bus time
reg maint_ref_zq_wip_r = 1'b0;
output maint_ref_zq_wip;
always @(posedge clk)
if(rst)
maint_ref_zq_wip_r <= #TCQ 1'b0;
else if((zq_request || |refresh_request) && insert_maint_r1)
maint_ref_zq_wip_r <= #TCQ 1'b1;
else if(~maint_wip_r)
maint_ref_zq_wip_r <= #TCQ 1'b0;
assign maint_ref_zq_wip = maint_ref_zq_wip_r;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_state.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Primary bank state machine. All bank specific timing is generated here.
//
// Conceptually, when a bank machine is assigned a request, conflicts are
// checked. If there is a conflict, then the new request is added
// to the queue for that rank-bank.
//
// Eventually, that request will find itself at the head of the queue for
// its rank-bank. Forthwith, the bank machine will begin arbitration to send an
// activate command to the DRAM. Once arbitration is successful and the
// activate is sent, the row state machine waits the RCD delay. The RAS
// counter is also started when the activate is sent.
//
// Upon completion of the RCD delay, the bank state machine will begin
// arbitration for sending out the column command. Once the column
// command has been sent, the bank state machine waits the RTP latency, and
// if the command is a write, the RAS counter is loaded with the WR latency.
//
// When the RTP counter reaches zero, the pre charge wait state is entered.
// Once the RAS timer reaches zero, arbitration to send a precharge command
// begins.
//
// Upon successful transmission of the precharge command, the bank state
// machine waits the precharge period and then rejoins the idle list.
//
// For an open rank-bank hit, a bank machine passes management of the rank-bank to
// a bank machine that is managing the subsequent request to the same page. A bank
// machine can either be a "passer" or a "passee" in this handoff. There
// are two conditions that have to occur before an open bank can be passed.
// A spatial condition, ie same rank-bank and row address. And a temporal condition,
// ie the passee has completed it work with the bank, but has not issued a precharge.
//
// The spatial condition is signalled by pass_open_bank_ns. The temporal condition
// is when the column command is issued, or when the bank_wait_in_progress
// signal is true. Bank_wait_in_progress is true when the RTP timer is not
// zero, or when the RAS/WR timer is not zero and the state machine is waiting
// to send out a precharge command.
//
// On an open bank pass, the passer transitions from the temporal condition
// noted above and performs the end of request processing and eventually lands
// in the act_wait_r state.
//
// On an open bank pass, the passee lands in the col_wait_r state and waits
// for its chance to send out a column command.
//
// Since there is a single data bus shared by all columns in all ranks, there
// is a single column machine. The column machine is primarily in charge of
// managing the timing on the DQ data bus. It reserves states for data transfer,
// driver turnaround states, and preambles. It also has the ability to add
// additional programmable delay for read to write changeovers. This read to write
// delay is generated in the column machine which inhibits writes via the
// inhbt_wr signal.
//
// There is a rank machine for every rank. The rank machines are responsible
// for enforcing rank specific timing such as FAW, and WTR. RRD is guaranteed
// in the bank machine since it is closely coupled to the operation of the
// bank machine and is timing critical.
//
// Since a bank machine can be working on a request for any rank, all rank machines
// inhibits are input to all bank machines. Based on the rank of the current
// request, each bank machine selects the rank information corresponding
// to the rank of its current request.
//
// Since driver turnaround states and WTR delays are so severe with DDRIII, the
// memory interface has the ability to promote requests that use the same
// driver as the most recent request. There is logic in this block that
// detects when the driver for its request is the same as the driver for
// the most recent request. In such a case, this block will send out special
// "same" request early enough to eliminate dead states when there is no
// driver changeover.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v1_9_bank_state #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 0,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRP = 10,
parameter nRTP = 4,
parameter nRCD = 5,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANKS = 4,
parameter RANK_WIDTH = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
start_rcd, act_wait_r, rd_half_rmw, ras_timer_ns, end_rtp,
bank_wait_in_progress, start_pre_wait, op_exit_req, pre_wait_r,
allow_auto_pre, precharge_bm_end, demand_act_priority, rts_row,
act_this_rank_r, demand_priority, col_rdy_wr, rts_col, wr_this_rank_r,
rd_this_rank_r, rts_pre, rtc,
// Inputs
clk, rst, bm_end, pass_open_bank_r, sending_row, sending_pre, rcv_open_bank,
sending_col, rd_wr_r, req_wr_r, rd_data_addr, req_data_buf_addr_r,
phy_rddata_valid, rd_rmw, ras_timer_ns_in, rb_hit_busies_r, idle_r,
passing_open_bank, low_idle_cnt_r, op_exit_grant, tail_r,
auto_pre_r, pass_open_bank_ns, req_rank_r, req_rank_r_in,
start_rcd_in, inhbt_act_faw_r, wait_for_maint_r, head_r, sent_row,
demand_act_priority_in, order_q_zero, sent_col, q_has_rd,
q_has_priority, req_priority_r, idle_ns, demand_priority_in, inhbt_rd,
inhbt_wr, dq_busy_data, rnk_config_strobe, rnk_config_valid_r, rnk_config,
rnk_config_kill_rts_col, phy_mc_cmd_full, phy_mc_ctl_full, phy_mc_data_full
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input clk;
input rst;
// Activate wait state machine.
input bm_end;
reg bm_end_r1;
always @(posedge clk) bm_end_r1 <= #TCQ bm_end;
reg col_wait_r;
input pass_open_bank_r;
input sending_row;
reg act_wait_r_lcl;
input rcv_open_bank;
wire start_rcd_lcl = act_wait_r_lcl && sending_row;
output wire start_rcd;
assign start_rcd = start_rcd_lcl;
wire act_wait_ns = rst ||
((act_wait_r_lcl && ~start_rcd_lcl && ~rcv_open_bank) ||
bm_end_r1 || (pass_open_bank_r && bm_end));
always @(posedge clk) act_wait_r_lcl <= #TCQ act_wait_ns;
output wire act_wait_r;
assign act_wait_r = act_wait_r_lcl;
// RCD timer
//
// When CWL is even, CAS commands are issued on slot 0 and RAS commands are
// issued on slot 1. This implies that the RCD can never expire in the same
// cycle as the RAS (otherwise the CAS for a given transaction would precede
// the RAS). Similarly, this can also cause premature expiration for longer
// RCD. An offset must be added to RCD before translating it to the FPGA clock
// domain. In this mode, CAS are on the first DRAM clock cycle corresponding to
// a given FPGA cycle. In 2:1 mode add 2 to generate this offset aligned to
// the FPGA cycle. Likewise, add 4 to generate an aligned offset in 4:1 mode.
//
// When CWL is odd, RAS commands are issued on slot 0 and CAS commands are
// issued on slot 1. There is a natural 1 cycle seperation between RAS and CAS
// in the DRAM clock domain so the RCD can expire in the same FPGA cycle as the
// RAS command. In 2:1 mode, there are only 2 slots so direct translation
// correctly places the CAS with respect to the corresponding RAS. In 4:1 mode,
// there are two slots after CAS, so 2 is added to shift the timer into the
// next FPGA cycle for cases that can't expire in the current cycle.
//
// In 2T mode, the offset from ROW to COL commands is fixed at 2. In 2:1 mode,
// It is sufficient to translate to the half-rate domain and add the remainder.
// In 4:1 mode, we must translate to the quarter-rate domain and add an
// additional fabric cycle only if the remainder exceeds the fixed offset of 2
localparam nRCD_CLKS =
nCK_PER_CLK == 1 ?
nRCD :
nCK_PER_CLK == 2 ?
ADDR_CMD_MODE == "2T" ?
(nRCD/2) + (nRCD%2) :
CWL % 2 ?
(nRCD/2) :
(nRCD+2) / 2 :
// (nCK_PER_CLK == 4)
ADDR_CMD_MODE == "2T" ?
(nRCD/4) + (nRCD%4 > 2 ? 1 : 0) :
CWL % 2 ?
(nRCD-2 ? (nRCD-2) / 4 + 1 : 1) :
nRCD/4 + 1;
localparam nRCD_CLKS_M2 = (nRCD_CLKS-2 <0) ? 0 : nRCD_CLKS-2;
localparam RCD_TIMER_WIDTH = clogb2(nRCD_CLKS_M2+1);
localparam ZERO = 0;
localparam ONE = 1;
reg [RCD_TIMER_WIDTH-1:0] rcd_timer_r = {RCD_TIMER_WIDTH{1'b0}};
reg end_rcd;
reg rcd_active_r = 1'b0;
generate
if (nRCD_CLKS <= 2) begin : rcd_timer_leq_2
always @(/*AS*/start_rcd_lcl) end_rcd = start_rcd_lcl;
end
else if (nRCD_CLKS > 2) begin : rcd_timer_gt_2
reg [RCD_TIMER_WIDTH-1:0] rcd_timer_ns;
always @(/*AS*/rcd_timer_r or rst or start_rcd_lcl) begin
if (rst) rcd_timer_ns = ZERO[RCD_TIMER_WIDTH-1:0];
else begin
rcd_timer_ns = rcd_timer_r;
if (start_rcd_lcl) rcd_timer_ns = nRCD_CLKS_M2[RCD_TIMER_WIDTH-1:0];
else if (|rcd_timer_r) rcd_timer_ns =
rcd_timer_r - ONE[RCD_TIMER_WIDTH-1:0];
end
end
always @(posedge clk) rcd_timer_r <= #TCQ rcd_timer_ns;
wire end_rcd_ns = (rcd_timer_ns == ONE[RCD_TIMER_WIDTH-1:0]);
always @(posedge clk) end_rcd = end_rcd_ns;
wire rcd_active_ns = |rcd_timer_ns;
always @(posedge clk) rcd_active_r <= #TCQ rcd_active_ns;
end
endgenerate
// Figure out if the read that's completing is for an RMW for
// this bank machine. Delay by a state if CWL != 8 since the
// data is not ready in the RMW buffer for the early write
// data fetch that happens with ECC and CWL != 8.
// Create a state bit indicating we're waiting for the read
// half of the rmw to complete.
input sending_col;
input rd_wr_r;
input req_wr_r;
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
input phy_rddata_valid;
input rd_rmw;
reg rmw_rd_done = 1'b0;
reg rd_half_rmw_lcl = 1'b0;
output wire rd_half_rmw;
assign rd_half_rmw = rd_half_rmw_lcl;
reg rmw_wait_r = 1'b0;
generate
if (ECC != "OFF") begin : rmw_on
// Delay phy_rddata_valid and rd_rmw by one cycle to align them
// to req_data_buf_addr_r so that rmw_wait_r clears properly
reg phy_rddata_valid_r;
reg rd_rmw_r;
always @(posedge clk) begin
phy_rddata_valid_r <= #TCQ phy_rddata_valid;
rd_rmw_r <= #TCQ rd_rmw;
end
wire my_rmw_rd_ns = phy_rddata_valid_r && rd_rmw_r &&
(rd_data_addr == req_data_buf_addr_r);
if (CWL == 8) always @(my_rmw_rd_ns) rmw_rd_done = my_rmw_rd_ns;
else always @(posedge clk) rmw_rd_done = #TCQ my_rmw_rd_ns;
always @(/*AS*/rd_wr_r or req_wr_r) rd_half_rmw_lcl = req_wr_r && rd_wr_r;
wire rmw_wait_ns = ~rst &&
((rmw_wait_r && ~rmw_rd_done) || (rd_half_rmw_lcl && sending_col));
always @(posedge clk) rmw_wait_r <= #TCQ rmw_wait_ns;
end
endgenerate
// column wait state machine.
wire col_wait_ns = ~rst && ((col_wait_r && ~sending_col) || end_rcd
|| rcv_open_bank || (rmw_rd_done && rmw_wait_r));
always @(posedge clk) col_wait_r <= #TCQ col_wait_ns;
// Set up various RAS timer parameters, wires, etc.
localparam TWO = 2;
output reg [RAS_TIMER_WIDTH-1:0] ras_timer_ns;
reg [RAS_TIMER_WIDTH-1:0] ras_timer_r;
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;
input [(nBANK_MACHS*2)-1:0] rb_hit_busies_r;
// On a bank pass, select the RAS timer from the passing bank machine.
reg [RAS_TIMER_WIDTH-1:0] passed_ras_timer;
integer i;
always @(/*AS*/ras_timer_ns_in or rb_hit_busies_r) begin
passed_ras_timer = {RAS_TIMER_WIDTH{1'b0}};
for (i=ID+1; i<(ID+nBANK_MACHS); i=i+1)
if (rb_hit_busies_r[i])
passed_ras_timer = ras_timer_ns_in[i*RAS_TIMER_WIDTH+:RAS_TIMER_WIDTH];
end
// RAS and (reused for) WTP timer. When an open bank is passed, this
// timer is passed to the new owner. The existing RAS prevents
// an activate from occuring too early.
wire start_wtp_timer = sending_col && ~rd_wr_r;
input idle_r;
always @(/*AS*/bm_end_r1 or ras_timer_r or rst or start_rcd_lcl
or start_wtp_timer) begin
if (bm_end_r1 || rst) ras_timer_ns = ZERO[RAS_TIMER_WIDTH-1:0];
else begin
ras_timer_ns = ras_timer_r;
if (start_rcd_lcl) ras_timer_ns =
nRAS_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0];
if (start_wtp_timer) ras_timer_ns =
// As the timer is being reused, it is essential to compare
// before new value is loaded.
(ras_timer_r <= (nWTP_CLKS-2)) ? nWTP_CLKS[RAS_TIMER_WIDTH-1:0] - TWO[RAS_TIMER_WIDTH-1:0]
: ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];
if (|ras_timer_r && ~start_wtp_timer) ras_timer_ns =
ras_timer_r - ONE[RAS_TIMER_WIDTH-1:0];
end
end // always @ (...
wire [RAS_TIMER_WIDTH-1:0] ras_timer_passed_ns = rcv_open_bank
? passed_ras_timer
: ras_timer_ns;
always @(posedge clk) ras_timer_r <= #TCQ ras_timer_passed_ns;
wire ras_timer_zero_ns = (ras_timer_ns == ZERO[RAS_TIMER_WIDTH-1:0]);
reg ras_timer_zero_r;
always @(posedge clk) ras_timer_zero_r <= #TCQ ras_timer_zero_ns;
// RTP timer. Unless 2T mode, add one for 2:1 mode. This accounts for loss of
// one DRAM CK due to column command to row command fixed offset. In 2T mode,
// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T
// mode, in which case we add 1 if the remainder exceeds the fixed offset.
localparam nRTP_CLKS = (nCK_PER_CLK == 1)
? nRTP :
(nCK_PER_CLK == 2)
? (nRTP/2) + ((ADDR_CMD_MODE == "2T") ? nRTP%2 : 1) :
(nRTP/4) + ((ADDR_CMD_MODE == "2T") ? (nRTP%4 > 2 ? 2 : 1) : 2);
localparam nRTP_CLKS_M1 = ((nRTP_CLKS-1) <= 0) ? 0 : nRTP_CLKS-1;
localparam RTP_TIMER_WIDTH = clogb2(nRTP_CLKS_M1 + 1);
reg [RTP_TIMER_WIDTH-1:0] rtp_timer_ns;
reg [RTP_TIMER_WIDTH-1:0] rtp_timer_r;
wire sending_col_not_rmw_rd = sending_col && ~rd_half_rmw_lcl;
always @(/*AS*/pass_open_bank_r or rst or rtp_timer_r
or sending_col_not_rmw_rd) begin
rtp_timer_ns = rtp_timer_r;
if (rst || pass_open_bank_r)
rtp_timer_ns = ZERO[RTP_TIMER_WIDTH-1:0];
else begin
if (sending_col_not_rmw_rd)
rtp_timer_ns = nRTP_CLKS_M1[RTP_TIMER_WIDTH-1:0];
if (|rtp_timer_r) rtp_timer_ns = rtp_timer_r - ONE[RTP_TIMER_WIDTH-1:0];
end
end
always @(posedge clk) rtp_timer_r <= #TCQ rtp_timer_ns;
wire end_rtp_lcl = ~pass_open_bank_r &&
((rtp_timer_r == ONE[RTP_TIMER_WIDTH-1:0]) ||
((nRTP_CLKS_M1 == 0) && sending_col_not_rmw_rd));
output wire end_rtp;
assign end_rtp = end_rtp_lcl;
// Optionally implement open page mode timer.
localparam OP_WIDTH = clogb2(nOP_WAIT + 1);
output wire bank_wait_in_progress;
output wire start_pre_wait;
input passing_open_bank;
input low_idle_cnt_r;
output wire op_exit_req;
input op_exit_grant;
input tail_r;
output reg pre_wait_r;
generate
if (nOP_WAIT == 0) begin : op_mode_disabled
assign bank_wait_in_progress = sending_col_not_rmw_rd || |rtp_timer_r ||
(pre_wait_r && ~ras_timer_zero_r);
assign start_pre_wait = end_rtp_lcl;
assign op_exit_req = 1'b0;
end
else begin : op_mode_enabled
reg op_wait_r;
assign bank_wait_in_progress = sending_col || |rtp_timer_r ||
(pre_wait_r && ~ras_timer_zero_r) ||
op_wait_r;
wire op_active = ~rst && ~passing_open_bank && ((end_rtp_lcl && tail_r)
|| op_wait_r);
wire op_wait_ns = ~op_exit_grant && op_active;
always @(posedge clk) op_wait_r <= #TCQ op_wait_ns;
assign start_pre_wait = op_exit_grant ||
(end_rtp_lcl && ~tail_r && ~passing_open_bank);
if (nOP_WAIT == -1)
assign op_exit_req = (low_idle_cnt_r && op_active);
else begin : op_cnt
reg [OP_WIDTH-1:0] op_cnt_r;
wire [OP_WIDTH-1:0] op_cnt_ns =
(passing_open_bank || op_exit_grant || rst)
? ZERO[OP_WIDTH-1:0]
: end_rtp_lcl
? nOP_WAIT[OP_WIDTH-1:0]
: |op_cnt_r
? op_cnt_r - ONE[OP_WIDTH-1:0]
: op_cnt_r;
always @(posedge clk) op_cnt_r <= #TCQ op_cnt_ns;
assign op_exit_req = (low_idle_cnt_r && op_active) ||
(op_wait_r && ~|op_cnt_r);
end
end
endgenerate
output allow_auto_pre;
wire allow_auto_pre = act_wait_r_lcl || rcd_active_r ||
(col_wait_r && ~sending_col);
// precharge wait state machine.
input auto_pre_r;
wire start_pre;
input pass_open_bank_ns;
wire pre_wait_ns = ~rst && (~pass_open_bank_ns &&
(start_pre_wait || (pre_wait_r && ~start_pre)));
always @(posedge clk) pre_wait_r <= #TCQ pre_wait_ns;
wire pre_request = pre_wait_r && ras_timer_zero_r && ~auto_pre_r;
// precharge timer.
localparam nRP_CLKS = (nCK_PER_CLK == 1) ? nRP :
(nCK_PER_CLK == 2) ? ((nRP/2) + (nRP%2)) :
/*(nCK_PER_CLK == 4)*/ ((nRP/4) + ((nRP%4) ? 1 : 0));
// Subtract two because there are a minimum of two fabric states from
// end of RP timer until earliest possible arb to send act.
localparam nRP_CLKS_M2 = (nRP_CLKS-2 < 0) ? 0 : nRP_CLKS-2;
localparam RP_TIMER_WIDTH = clogb2(nRP_CLKS_M2 + 1);
input sending_pre;
output rts_pre;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin
assign start_pre = pre_wait_r && ras_timer_zero_r &&
(sending_pre || auto_pre_r);
assign rts_pre = ~sending_pre && pre_request;
end
else begin
assign start_pre = pre_wait_r && ras_timer_zero_r &&
(sending_row || auto_pre_r);
assign rts_pre = 1'b0;
end
endgenerate
reg [RP_TIMER_WIDTH-1:0] rp_timer_r = ZERO[RP_TIMER_WIDTH-1:0];
generate
if (nRP_CLKS_M2 > ZERO) begin : rp_timer
reg [RP_TIMER_WIDTH-1:0] rp_timer_ns;
always @(/*AS*/rp_timer_r or rst or start_pre)
if (rst) rp_timer_ns = ZERO[RP_TIMER_WIDTH-1:0];
else begin
rp_timer_ns = rp_timer_r;
if (start_pre) rp_timer_ns = nRP_CLKS_M2[RP_TIMER_WIDTH-1:0];
else if (|rp_timer_r) rp_timer_ns =
rp_timer_r - ONE[RP_TIMER_WIDTH-1:0];
end
always @(posedge clk) rp_timer_r <= #TCQ rp_timer_ns;
end // block: rp_timer
endgenerate
output wire precharge_bm_end;
assign precharge_bm_end = (rp_timer_r == ONE[RP_TIMER_WIDTH-1:0]) ||
(start_pre && (nRP_CLKS_M2 == ZERO));
// Compute RRD related activate inhibit.
// Compare this bank machine's rank with others, then
// select result based on grant. An alternative is to
// select the just issued rank with the grant and simply
// compare against this bank machine's rank. However, this
// serializes the selection of the rank and the compare processes.
// As implemented below, the compare occurs first, then the
// selection based on grant. This is faster.
input [RANK_WIDTH-1:0] req_rank_r;
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;
reg inhbt_act_rrd;
input [(nBANK_MACHS*2)-1:0] start_rcd_in;
generate
integer j;
if (RANKS == 1)
always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin
inhbt_act_rrd = 1'b0;
for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)
inhbt_act_rrd = inhbt_act_rrd || start_rcd_in[j];
end
else begin
always @(/*AS*/req_rank_r or req_rank_r_in or start_rcd_in) begin
inhbt_act_rrd = 1'b0;
for (j=(ID+1); j<(ID+nBANK_MACHS); j=j+1)
inhbt_act_rrd = inhbt_act_rrd ||
(start_rcd_in[j] &&
(req_rank_r_in[(j*RANK_WIDTH)+:RANK_WIDTH] == req_rank_r));
end
end
endgenerate
// Extract the activate command inhibit for the rank associated
// with this request. FAW and RRD are computed separately so that
// gate level timing can be carefully managed.
input [RANKS-1:0] inhbt_act_faw_r;
wire my_inhbt_act_faw = inhbt_act_faw_r[req_rank_r];
input wait_for_maint_r;
input head_r;
wire act_req = ~idle_r && head_r && act_wait_r && ras_timer_zero_r &&
~wait_for_maint_r;
// Implement simple starvation avoidance for act requests. Precharge
// requests don't need this because they are never gated off by
// timing events such as inhbt_act_rrd. Priority request timeout
// is fixed at a single trip around the round robin arbiter.
input sent_row;
wire rts_act_denied = act_req && sent_row && ~sending_row;
reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_ns;
reg [BM_CNT_WIDTH-1:0] act_starve_limit_cntr_r;
generate
if (BM_CNT_WIDTH > 1) // Number of Bank Machs > 2
begin :BM_MORE_THAN_2
always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)
begin
act_starve_limit_cntr_ns = act_starve_limit_cntr_r;
if (~act_req)
act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};
else
if (rts_act_denied && &act_starve_limit_cntr_r)
act_starve_limit_cntr_ns = act_starve_limit_cntr_r +
{{BM_CNT_WIDTH-1{1'b0}}, 1'b1};
end
end
else // Number of Bank Machs == 2
begin :BM_EQUAL_2
always @(/*AS*/act_req or act_starve_limit_cntr_r or rts_act_denied)
begin
act_starve_limit_cntr_ns = act_starve_limit_cntr_r;
if (~act_req)
act_starve_limit_cntr_ns = {BM_CNT_WIDTH{1'b0}};
else
if (rts_act_denied && &act_starve_limit_cntr_r)
act_starve_limit_cntr_ns = act_starve_limit_cntr_r +
{1'b1};
end
end
endgenerate
always @(posedge clk) act_starve_limit_cntr_r <=
#TCQ act_starve_limit_cntr_ns;
reg demand_act_priority_r;
wire demand_act_priority_ns = act_req &&
(demand_act_priority_r || (rts_act_denied && &act_starve_limit_cntr_r));
always @(posedge clk) demand_act_priority_r <= #TCQ demand_act_priority_ns;
`ifdef MC_SVA
cover_demand_act_priority:
cover property (@(posedge clk) (~rst && demand_act_priority_r));
`endif
output wire demand_act_priority;
assign demand_act_priority = demand_act_priority_r && ~sending_row;
// compute act_demanded from other demand_act_priorities
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;
reg act_demanded = 1'b0;
generate
if (nBANK_MACHS > 1) begin : compute_act_demanded
always @(demand_act_priority_in[`BM_SHARED_BV])
act_demanded = |demand_act_priority_in[`BM_SHARED_BV];
end
endgenerate
wire row_demand_ok = demand_act_priority_r || ~act_demanded;
// Generate the Request To Send row arbitation signal.
output wire rts_row;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T"))
assign rts_row = ~sending_row && row_demand_ok &&
(act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd);
else
assign rts_row = ~sending_row && row_demand_ok &&
((act_req && ~my_inhbt_act_faw && ~inhbt_act_rrd) ||
pre_request);
endgenerate
`ifdef MC_SVA
four_activate_window_wait:
cover property (@(posedge clk)
(~rst && ~sending_row && act_req && my_inhbt_act_faw));
ras_ras_delay_wait:
cover property (@(posedge clk)
(~rst && ~sending_row && act_req && inhbt_act_rrd));
`endif
// Provide rank machines early knowledge that this bank machine is
// going to send an activate to the rank. In this way, the rank
// machines just need to use the sending_row wire to figure out if
// they need to keep track of the activate.
output reg [RANKS-1:0] act_this_rank_r;
reg [RANKS-1:0] act_this_rank_ns;
always @(/*AS*/act_wait_r or req_rank_r) begin
act_this_rank_ns = {RANKS{1'b0}};
for (i = 0; i < RANKS; i = i + 1)
act_this_rank_ns[i] = act_wait_r && (i[RANK_WIDTH-1:0] == req_rank_r);
end
always @(posedge clk) act_this_rank_r <= #TCQ act_this_rank_ns;
// Generate request to send column command signal.
input order_q_zero;
wire req_bank_rdy_ns = order_q_zero && col_wait_r;
reg req_bank_rdy_r;
always @(posedge clk) req_bank_rdy_r <= #TCQ req_bank_rdy_ns;
// Determine is we have been denied a column command request.
input sent_col;
wire rts_col_denied = req_bank_rdy_r && sent_col && ~sending_col;
// Implement a starvation limit counter. Count the number of times a
// request to send a column command has been denied.
localparam STARVE_LIMIT_CNT = STARVE_LIMIT * nBANK_MACHS;
localparam STARVE_LIMIT_WIDTH = clogb2(STARVE_LIMIT_CNT);
reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_r;
reg [STARVE_LIMIT_WIDTH-1:0] starve_limit_cntr_ns;
always @(/*AS*/col_wait_r or rts_col_denied or starve_limit_cntr_r)
if (~col_wait_r)
starve_limit_cntr_ns = {STARVE_LIMIT_WIDTH{1'b0}};
else
if (rts_col_denied && (starve_limit_cntr_r != STARVE_LIMIT_CNT-1))
starve_limit_cntr_ns = starve_limit_cntr_r +
{{STARVE_LIMIT_WIDTH-1{1'b0}}, 1'b1};
else starve_limit_cntr_ns = starve_limit_cntr_r;
always @(posedge clk) starve_limit_cntr_r <= #TCQ starve_limit_cntr_ns;
input q_has_rd;
input q_has_priority;
// Decide if this bank machine should demand priority. Priority is demanded
// when starvation limit counter is reached, or a bit in the request.
wire starved = ((starve_limit_cntr_r == (STARVE_LIMIT_CNT-1)) &&
rts_col_denied);
input req_priority_r;
input idle_ns;
reg demand_priority_r;
wire demand_priority_ns = ~idle_ns && col_wait_ns &&
(demand_priority_r ||
(order_q_zero &&
(req_priority_r || q_has_priority)) ||
(starved && (q_has_rd || ~req_wr_r)));
always @(posedge clk) demand_priority_r <= #TCQ demand_priority_ns;
`ifdef MC_SVA
wire rdy_for_priority = ~rst && ~demand_priority_r && ~idle_ns &&
col_wait_ns;
req_triggers_demand_priority:
cover property (@(posedge clk)
(rdy_for_priority && req_priority_r && ~q_has_priority && ~starved));
q_priority_triggers_demand_priority:
cover property (@(posedge clk)
(rdy_for_priority && ~req_priority_r && q_has_priority && ~starved));
wire not_req_or_q_rdy_for_priority =
rdy_for_priority && ~req_priority_r && ~q_has_priority;
starved_req_triggers_demand_priority:
cover property (@(posedge clk)
(not_req_or_q_rdy_for_priority && starved && ~q_has_rd && ~req_wr_r));
starved_q_triggers_demand_priority:
cover property (@(posedge clk)
(not_req_or_q_rdy_for_priority && starved && q_has_rd && req_wr_r));
`endif
// compute demanded from other demand_priorities
input [(nBANK_MACHS*2)-1:0] demand_priority_in;
reg demanded = 1'b0;
generate
if (nBANK_MACHS > 1) begin : compute_demanded
always @(demand_priority_in[`BM_SHARED_BV]) demanded =
|demand_priority_in[`BM_SHARED_BV];
end
endgenerate
// In order to make sure that there is no starvation amongst a possibly
// unlimited stream of priority requests, add a second stage to the demand
// priority signal. If there are no other requests demanding priority, then
// go ahead and assert demand_priority. If any other requests are asserting
// demand_priority, hold off asserting demand_priority until these clear, then
// assert demand priority. Its possible to get multiple requests asserting
// demand priority simultaneously, but that's OK. Those requests will be
// serviced, demanded will fall, and another group of requests will be
// allowed to assert demand_priority.
reg demanded_prior_r;
wire demanded_prior_ns = demanded &&
(demanded_prior_r || ~demand_priority_r);
always @(posedge clk) demanded_prior_r <= #TCQ demanded_prior_ns;
output wire demand_priority;
assign demand_priority = demand_priority_r && ~demanded_prior_r &&
~sending_col;
`ifdef MC_SVA
demand_priority_gated:
cover property (@(posedge clk) (demand_priority_r && ~demand_priority));
generate
if (nBANK_MACHS >1) multiple_demand_priority:
cover property (@(posedge clk)
($countones(demand_priority_in[`BM_SHARED_BV]) > 1));
endgenerate
`endif
wire demand_ok = demand_priority_r || ~demanded;
// Figure out if the request in this bank machine matches the current rank
// configuration.
input rnk_config_strobe;
input rnk_config_kill_rts_col;
input rnk_config_valid_r;
input [RANK_WIDTH-1:0] rnk_config;
output wire rtc;
wire rnk_config_match = rnk_config_valid_r && (rnk_config == req_rank_r);
assign rtc = ~rnk_config_match && ~rnk_config_kill_rts_col && order_q_zero && col_wait_r && demand_ok;
// Using rank state provided by the rank machines, figure out if
// a read requests should wait for WTR or RTW.
input [RANKS-1:0] inhbt_rd;
wire my_inhbt_rd = inhbt_rd[req_rank_r];
input [RANKS-1:0] inhbt_wr;
wire my_inhbt_wr = inhbt_wr[req_rank_r];
wire allow_rw = ~rd_wr_r ? ~my_inhbt_wr : ~my_inhbt_rd;
// DQ bus timing constraints.
input dq_busy_data;
// Column command is ready to arbitrate, except for databus restrictions.
wire col_rdy = (col_wait_r || ((nRCD_CLKS <= 1) && end_rcd) ||
(rcv_open_bank && nCK_PER_CLK == 2 && DRAM_TYPE=="DDR2" && BURST_MODE == "4") ||
(rcv_open_bank && nCK_PER_CLK == 4 && BURST_MODE == "8")) &&
order_q_zero;
// Column command is ready to arbitrate for sending a write. Used
// to generate early wr_data_addr for ECC mode.
output wire col_rdy_wr;
assign col_rdy_wr = col_rdy && ~rd_wr_r;
// Figure out if we're ready to send a column command based on all timing
// constraints.
// if timing is an issue.
wire col_cmd_rts = col_rdy && ~dq_busy_data && allow_rw && rnk_config_match;
`ifdef MC_SVA
col_wait_for_order_q: cover property
(@(posedge clk)
(~rst && col_wait_r && ~order_q_zero && ~dq_busy_data &&
allow_rw));
col_wait_for_dq_busy: cover property
(@(posedge clk)
(~rst && col_wait_r && order_q_zero && dq_busy_data &&
allow_rw));
col_wait_for_allow_rw: cover property
(@(posedge clk)
(~rst && col_wait_r && order_q_zero && ~dq_busy_data &&
~allow_rw));
`endif
// Implement flow control for the command and control FIFOs and for the data
// FIFO during writes
input phy_mc_ctl_full;
input phy_mc_cmd_full;
input phy_mc_data_full;
// Register ctl_full and cmd_full
reg phy_mc_ctl_full_r = 1'b0;
reg phy_mc_cmd_full_r = 1'b0;
always @(posedge clk)
if(rst) begin
phy_mc_ctl_full_r <= #TCQ 1'b0;
phy_mc_cmd_full_r <= #TCQ 1'b0;
end else begin
phy_mc_ctl_full_r <= #TCQ phy_mc_ctl_full;
phy_mc_cmd_full_r <= #TCQ phy_mc_cmd_full;
end
// register output data pre-fifo almost full condition and fold in WR status
reg ofs_rdy_r = 1'b0;
always @(posedge clk)
if(rst)
ofs_rdy_r <= #TCQ 1'b0;
else
ofs_rdy_r <= #TCQ ~phy_mc_cmd_full_r && ~phy_mc_ctl_full_r && ~(phy_mc_data_full && ~rd_wr_r);
// Disable priority feature for one state after a config to insure
// forward progress on the just installed io config.
reg override_demand_r;
wire override_demand_ns = rnk_config_strobe || rnk_config_kill_rts_col;
always @(posedge clk) override_demand_r <= override_demand_ns;
output wire rts_col;
assign rts_col = ~sending_col && (demand_ok || override_demand_r) &&
col_cmd_rts && ofs_rdy_r;
// As in act_this_rank, wr/rd_this_rank informs rank machines
// that this bank machine is doing a write/rd. Removes logic
// after the grant.
reg [RANKS-1:0] wr_this_rank_ns;
reg [RANKS-1:0] rd_this_rank_ns;
always @(/*AS*/rd_wr_r or req_rank_r) begin
wr_this_rank_ns = {RANKS{1'b0}};
rd_this_rank_ns = {RANKS{1'b0}};
for (i=0; i<RANKS; i=i+1) begin
wr_this_rank_ns[i] = ~rd_wr_r && (i[RANK_WIDTH-1:0] == req_rank_r);
rd_this_rank_ns[i] = rd_wr_r && (i[RANK_WIDTH-1:0] == req_rank_r);
end
end
output reg [RANKS-1:0] wr_this_rank_r;
always @(posedge clk) wr_this_rank_r <= #TCQ wr_this_rank_ns;
output reg [RANKS-1:0] rd_this_rank_r;
always @(posedge clk) rd_this_rank_r <= #TCQ rd_this_rank_ns;
endmodule // bank_state
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_in_deserializer (
// Inputs
clk,
reset,
serial_data_in,
receive_data_en,
// Bidirectionals
// Outputs
fifo_read_available,
received_data_valid,
received_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input serial_data_in;
input receive_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_read_available;
output received_data_valid;
output [DW: 0] received_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_received;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
// Internal Registers
reg receiving_data;
reg [(TDW-1):0] data_in_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_read_available <= 8'h00;
else
fifo_read_available <= {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
receiving_data <= 1'b0;
else if (all_bits_received)
receiving_data <= 1'b0;
else if (serial_data_in == 1'b0)
receiving_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_in_shift_reg <= {TDW{1'b0}};
else if (shift_data_reg_en)
data_in_shift_reg <=
{serial_data_in, data_in_shift_reg[(TDW - 1):1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign received_data_valid = ~fifo_is_empty;
// Input assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_In_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~receiving_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (),
.baud_clock_falling_edge (shift_data_reg_en),
.all_bits_transmitted (all_bits_received)
);
defparam
RS232_In_Counters.CW = CW,
RS232_In_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Counters.TDW = TDW;
altera_up_sync_fifo RS232_In_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (all_bits_received & ~fifo_is_full),
.write_data (data_in_shift_reg[(DW + 1):1]),
.read_en (receive_data_en & ~fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (received_data)
);
defparam
RS232_In_FIFO.DW = DW,
RS232_In_FIFO.DATA_DEPTH = 128,
RS232_In_FIFO.AW = 6;
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_in_deserializer (
// Inputs
clk,
reset,
serial_data_in,
receive_data_en,
// Bidirectionals
// Outputs
fifo_read_available,
received_data_valid,
received_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input serial_data_in;
input receive_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_read_available;
output received_data_valid;
output [DW: 0] received_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_received;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
// Internal Registers
reg receiving_data;
reg [(TDW-1):0] data_in_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_read_available <= 8'h00;
else
fifo_read_available <= {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
receiving_data <= 1'b0;
else if (all_bits_received)
receiving_data <= 1'b0;
else if (serial_data_in == 1'b0)
receiving_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_in_shift_reg <= {TDW{1'b0}};
else if (shift_data_reg_en)
data_in_shift_reg <=
{serial_data_in, data_in_shift_reg[(TDW - 1):1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign received_data_valid = ~fifo_is_empty;
// Input assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_In_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~receiving_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (),
.baud_clock_falling_edge (shift_data_reg_en),
.all_bits_transmitted (all_bits_received)
);
defparam
RS232_In_Counters.CW = CW,
RS232_In_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Counters.TDW = TDW;
altera_up_sync_fifo RS232_In_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (all_bits_received & ~fifo_is_full),
.write_data (data_in_shift_reg[(DW + 1):1]),
.read_en (receive_data_en & ~fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (received_data)
);
defparam
RS232_In_FIFO.DW = DW,
RS232_In_FIFO.DATA_DEPTH = 128,
RS232_In_FIFO.AW = 6;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: syncff.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A back to back FF design to mitigate metastable issues
// when crossing clock domains.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module syncff
(
input CLK,
input IN_ASYNC,
output OUT_SYNC
);
wire wSyncFFQ;
ff
syncFF
(
.CLK(CLK),
.D(IN_ASYNC),
.Q(wSyncFFQ)
);
ff metaFF (
.CLK(CLK),
.D(wSyncFFQ),
.Q(OUT_SYNC)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: syncff.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A back to back FF design to mitigate metastable issues
// when crossing clock domains.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module syncff
(
input CLK,
input IN_ASYNC,
output OUT_SYNC
);
wire wSyncFFQ;
ff
syncFF
(
.CLK(CLK),
.D(IN_ASYNC),
.Q(wSyncFFQ)
);
ff metaFF (
.CLK(CLK),
.D(wSyncFFQ),
.Q(OUT_SYNC)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: syncff.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A back to back FF design to mitigate metastable issues
// when crossing clock domains.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module syncff
(
input CLK,
input IN_ASYNC,
output OUT_SYNC
);
wire wSyncFFQ;
ff
syncFF
(
.CLK(CLK),
.D(IN_ASYNC),
.Q(wSyncFFQ)
);
ff metaFF (
.CLK(CLK),
.D(wSyncFFQ),
.Q(OUT_SYNC)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: syncff.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A back to back FF design to mitigate metastable issues
// when crossing clock domains.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module syncff
(
input CLK,
input IN_ASYNC,
output OUT_SYNC
);
wire wSyncFFQ;
ff
syncFF
(
.CLK(CLK),
.D(IN_ASYNC),
.Q(wSyncFFQ)
);
ff metaFF (
.CLK(CLK),
.D(wSyncFFQ),
.Q(OUT_SYNC)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_compare.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block stores the request for this bank machine.
//
// All possible new requests are compared against the request stored
// here. The compare results are shared with the bank machines and
// is used to determine where to enqueue a new request.
`timescale 1ps/1ps
module mig_7series_v1_9_bank_compare #
(parameter BANK_WIDTH = 3,
parameter TCQ = 100,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter ECC = "OFF",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16)
(/*AUTOARG*/
// Outputs
req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r,
req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r,
rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr,
req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r,
// Inputs
clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd,
sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority,
maint_rank_r, maint_zq_r, maint_sre_r, auto_pre_r, rd_half_rmw, act_wait_r
);
input clk;
input idle_ns;
input idle_r;
input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;
output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns =
idle_r
? data_buf_addr
: req_data_buf_addr_r;
always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns;
input periodic_rd_insert;
reg req_periodic_rd_r_lcl;
wire req_periodic_rd_ns = idle_ns
? periodic_rd_insert
: req_periodic_rd_r_lcl;
always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns;
output wire req_periodic_rd_r;
assign req_periodic_rd_r = req_periodic_rd_r_lcl;
input size;
wire req_size_r_lcl;
generate
if (BURST_MODE == "4") begin : burst_mode_4
assign req_size_r_lcl = 1'b0;
end
else
if (BURST_MODE == "8") begin : burst_mode_8
assign req_size_r_lcl = 1'b1;
end
else
if (BURST_MODE == "OTF") begin : burst_mode_otf
reg req_size;
wire req_size_ns = idle_ns
? (periodic_rd_insert || size)
: req_size;
always @(posedge clk) req_size <= #TCQ req_size_ns;
assign req_size_r_lcl = req_size;
end
endgenerate
output wire req_size_r;
assign req_size_r = req_size_r_lcl;
input [2:0] cmd;
reg [2:0] req_cmd_r;
wire [2:0] req_cmd_ns = idle_ns
? (periodic_rd_insert ? 3'b001 : cmd)
: req_cmd_r;
always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns;
`ifdef MC_SVA
rd_wr_only_wo_ecc: assert property
(@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1]));
`endif
input sending_col;
reg rd_wr_r_lcl;
wire rd_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0])
: ~sending_col && rd_wr_r_lcl;
always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns;
output wire rd_wr_r;
assign rd_wr_r = rd_wr_r_lcl;
input [RANK_WIDTH-1:0] rank;
input [RANK_WIDTH-1:0] periodic_rd_rank_r;
reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}};
reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}};
generate
if (RANKS != 1) begin
always @(/*AS*/idle_ns or periodic_rd_insert
or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns
? periodic_rd_insert
? periodic_rd_rank_r
: rank
: req_rank_r_lcl;
always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns;
end
endgenerate
output wire [RANK_WIDTH-1:0] req_rank_r;
assign req_rank_r = req_rank_r_lcl;
input [BANK_WIDTH-1:0] bank;
reg [BANK_WIDTH-1:0] req_bank_r_lcl;
wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl;
always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns;
output wire[BANK_WIDTH-1:0] req_bank_r;
assign req_bank_r = req_bank_r_lcl;
input [ROW_WIDTH-1:0] row;
reg [ROW_WIDTH-1:0] req_row_r_lcl;
wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl;
always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns;
output wire [ROW_WIDTH-1:0] req_row_r;
assign req_row_r = req_row_r_lcl;
// Make req_col_r as wide as the max row address. This
// makes it easier to deal with indexing different column widths.
input [COL_WIDTH-1:0] col;
reg [15:0] req_col_r = 16'b0;
wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0];
always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns;
reg req_wr_r_lcl;
wire req_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0])
: req_wr_r_lcl;
always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns;
output wire req_wr_r;
assign req_wr_r = req_wr_r_lcl;
input hi_priority;
output reg req_priority_r;
wire req_priority_ns = idle_ns ? hi_priority : req_priority_r;
always @(posedge clk) req_priority_r <= #TCQ req_priority_ns;
wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert
? periodic_rd_rank_r
: rank));
wire bank_hit = (req_bank_r_lcl == bank);
wire rank_bank_hit = rank_hit && bank_hit;
output reg rb_hit_busy_r; // rank-bank hit on non idle row machine
wire rb_hit_busy_ns_lcl;
assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns;
output wire rb_hit_busy_ns;
assign rb_hit_busy_ns = rb_hit_busy_ns_lcl;
wire row_hit_ns = (req_row_r_lcl == row);
output reg row_hit_r;
always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl;
always @(posedge clk) row_hit_r <= #TCQ row_hit_ns;
input [RANK_WIDTH-1:0] maint_rank_r;
input maint_zq_r;
input maint_sre_r;
output wire maint_hit;
assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r || maint_sre_r;
// Assemble column address. Structure to be the same
// width as the row address. This makes it easier
// for the downstream muxing. Depending on the sizes
// of the row and column addresses, fill in as appropriate.
input auto_pre_r;
input rd_half_rmw;
reg [15:0] col_addr_template = 16'b0;
always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r
or req_size_r_lcl) begin
col_addr_template = req_col_r;
col_addr_template[10] = auto_pre_r && ~rd_half_rmw;
col_addr_template[11] = req_col_r[10];
col_addr_template[12] = req_size_r_lcl;
col_addr_template[13] = req_col_r[11];
end
output wire [ROW_WIDTH-1:0] col_addr;
assign col_addr = col_addr_template[ROW_WIDTH-1:0];
output wire req_ras;
output wire req_cas;
output wire row_cmd_wr;
input act_wait_r;
assign req_ras = 1'b0;
assign req_cas = 1'b1;
assign row_cmd_wr = act_wait_r;
output reg [ROW_WIDTH-1:0] row_addr;
always @(/*AS*/act_wait_r or req_row_r_lcl) begin
row_addr = req_row_r_lcl;
// This causes all precharges to be precharge single bank command.
if (~act_wait_r) row_addr[10] = 1'b0;
end
// Indicate which, if any, rank this bank machine is busy with.
// Not registering the result would probably be more accurate, but
// would create timing issues. This is used for refresh banking, perfect
// accuracy is not required.
localparam ONE = 1;
output reg [RANKS-1:0] rank_busy_r;
wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns);
always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns;
endmodule // bank_compare
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: interrupt_controller.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Signals an interrupt on the Xilnx PCIe Endpoint
// interface. Supports single vector MSI or legacy based
// interrupts.
// When INTR is pulsed high, the interrupt will be issued
// as soon as possible. If using legacy interrupts, the
// initial interrupt must be cleared by another request
// (typically a PIO read or write request to the
// endpoint at some predetermined BAR address). Receipt of
// the "clear" acknowledgment should cause INTR_LEGACY_CLR
// input to pulse high. Thus completing the legacy
// interrupt cycle. If using MSI interrupts, no such
// acknowldegment is necessary.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_INTRCTLR_IDLE 3'd0
`define S_INTRCLTR_WORKING 3'd1
`define S_INTRCLTR_COMPLETE 3'd2
`define S_INTRCLTR_CLEAR_LEGACY 3'd3
`define S_INTRCLTR_CLEARING_LEGACY 3'd4
`define S_INTRCLTR_DONE 3'd5
`timescale 1ns/1ns
module interrupt_controller (
input CLK, // System clock
input RST, // Async reset
input INTR, // Pulsed high to request an interrupt
input INTR_LEGACY_CLR, // Pulsed high to ack the legacy interrupt and clear it
output INTR_DONE, // Pulsed high to signal interrupt sent
input CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
output CFG_INTERRUPT_ASSERT, // Legacy interrupt message type
input INTR_MSI_RDY, // High when interrupt is able to be sent
output INTR_MSI_REQUEST // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent
);
reg [2:0] rState=`S_INTRCTLR_IDLE;
reg [2:0] rStateNext=`S_INTRCTLR_IDLE;
reg rIntr=0;
reg rIntrAssert=0;
assign INTR_DONE = (rState == `S_INTRCLTR_DONE);
assign INTR_MSI_REQUEST = rIntr;
assign CFG_INTERRUPT_ASSERT = rIntrAssert;
// Control sending interrupts.
always @(*) begin
case (rState)
`S_INTRCTLR_IDLE : begin
if (INTR) begin
rIntr = 1;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
end
else begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
end
`S_INTRCLTR_WORKING : begin
rIntr = 1;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
end
`S_INTRCLTR_COMPLETE : begin
rIntr = 0;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (CONFIG_INTERRUPT_MSIENABLE ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEAR_LEGACY);
end
`S_INTRCLTR_CLEAR_LEGACY : begin
if (INTR_LEGACY_CLR) begin
rIntr = 1;
rIntrAssert = 0;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
end
else begin
rIntr = 0;
rIntrAssert = 1;
rStateNext = `S_INTRCLTR_CLEAR_LEGACY;
end
end
`S_INTRCLTR_CLEARING_LEGACY : begin
rIntr = 1;
rIntrAssert = 0;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
end
`S_INTRCLTR_DONE : begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
default: begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
endcase
end
// Update the state.
always @(posedge CLK) begin
if (RST)
rState <= #1 `S_INTRCTLR_IDLE;
else
rState <= #1 rStateNext;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: interrupt_controller.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Signals an interrupt on the Xilnx PCIe Endpoint
// interface. Supports single vector MSI or legacy based
// interrupts.
// When INTR is pulsed high, the interrupt will be issued
// as soon as possible. If using legacy interrupts, the
// initial interrupt must be cleared by another request
// (typically a PIO read or write request to the
// endpoint at some predetermined BAR address). Receipt of
// the "clear" acknowledgment should cause INTR_LEGACY_CLR
// input to pulse high. Thus completing the legacy
// interrupt cycle. If using MSI interrupts, no such
// acknowldegment is necessary.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_INTRCTLR_IDLE 3'd0
`define S_INTRCLTR_WORKING 3'd1
`define S_INTRCLTR_COMPLETE 3'd2
`define S_INTRCLTR_CLEAR_LEGACY 3'd3
`define S_INTRCLTR_CLEARING_LEGACY 3'd4
`define S_INTRCLTR_DONE 3'd5
`timescale 1ns/1ns
module interrupt_controller (
input CLK, // System clock
input RST, // Async reset
input INTR, // Pulsed high to request an interrupt
input INTR_LEGACY_CLR, // Pulsed high to ack the legacy interrupt and clear it
output INTR_DONE, // Pulsed high to signal interrupt sent
input CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
output CFG_INTERRUPT_ASSERT, // Legacy interrupt message type
input INTR_MSI_RDY, // High when interrupt is able to be sent
output INTR_MSI_REQUEST // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent
);
reg [2:0] rState=`S_INTRCTLR_IDLE;
reg [2:0] rStateNext=`S_INTRCTLR_IDLE;
reg rIntr=0;
reg rIntrAssert=0;
assign INTR_DONE = (rState == `S_INTRCLTR_DONE);
assign INTR_MSI_REQUEST = rIntr;
assign CFG_INTERRUPT_ASSERT = rIntrAssert;
// Control sending interrupts.
always @(*) begin
case (rState)
`S_INTRCTLR_IDLE : begin
if (INTR) begin
rIntr = 1;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
end
else begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
end
`S_INTRCLTR_WORKING : begin
rIntr = 1;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
end
`S_INTRCLTR_COMPLETE : begin
rIntr = 0;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (CONFIG_INTERRUPT_MSIENABLE ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEAR_LEGACY);
end
`S_INTRCLTR_CLEAR_LEGACY : begin
if (INTR_LEGACY_CLR) begin
rIntr = 1;
rIntrAssert = 0;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
end
else begin
rIntr = 0;
rIntrAssert = 1;
rStateNext = `S_INTRCLTR_CLEAR_LEGACY;
end
end
`S_INTRCLTR_CLEARING_LEGACY : begin
rIntr = 1;
rIntrAssert = 0;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
end
`S_INTRCLTR_DONE : begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
default: begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
endcase
end
// Update the state.
always @(posedge CLK) begin
if (RST)
rState <= #1 `S_INTRCTLR_IDLE;
else
rState <= #1 rStateNext;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: interrupt_controller.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Signals an interrupt on the Xilnx PCIe Endpoint
// interface. Supports single vector MSI or legacy based
// interrupts.
// When INTR is pulsed high, the interrupt will be issued
// as soon as possible. If using legacy interrupts, the
// initial interrupt must be cleared by another request
// (typically a PIO read or write request to the
// endpoint at some predetermined BAR address). Receipt of
// the "clear" acknowledgment should cause INTR_LEGACY_CLR
// input to pulse high. Thus completing the legacy
// interrupt cycle. If using MSI interrupts, no such
// acknowldegment is necessary.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_INTRCTLR_IDLE 3'd0
`define S_INTRCLTR_WORKING 3'd1
`define S_INTRCLTR_COMPLETE 3'd2
`define S_INTRCLTR_CLEAR_LEGACY 3'd3
`define S_INTRCLTR_CLEARING_LEGACY 3'd4
`define S_INTRCLTR_DONE 3'd5
`timescale 1ns/1ns
module interrupt_controller (
input CLK, // System clock
input RST, // Async reset
input INTR, // Pulsed high to request an interrupt
input INTR_LEGACY_CLR, // Pulsed high to ack the legacy interrupt and clear it
output INTR_DONE, // Pulsed high to signal interrupt sent
input CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
output CFG_INTERRUPT_ASSERT, // Legacy interrupt message type
input INTR_MSI_RDY, // High when interrupt is able to be sent
output INTR_MSI_REQUEST // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent
);
reg [2:0] rState=`S_INTRCTLR_IDLE;
reg [2:0] rStateNext=`S_INTRCTLR_IDLE;
reg rIntr=0;
reg rIntrAssert=0;
assign INTR_DONE = (rState == `S_INTRCLTR_DONE);
assign INTR_MSI_REQUEST = rIntr;
assign CFG_INTERRUPT_ASSERT = rIntrAssert;
// Control sending interrupts.
always @(*) begin
case (rState)
`S_INTRCTLR_IDLE : begin
if (INTR) begin
rIntr = 1;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
end
else begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
end
`S_INTRCLTR_WORKING : begin
rIntr = 1;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
end
`S_INTRCLTR_COMPLETE : begin
rIntr = 0;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (CONFIG_INTERRUPT_MSIENABLE ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEAR_LEGACY);
end
`S_INTRCLTR_CLEAR_LEGACY : begin
if (INTR_LEGACY_CLR) begin
rIntr = 1;
rIntrAssert = 0;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
end
else begin
rIntr = 0;
rIntrAssert = 1;
rStateNext = `S_INTRCLTR_CLEAR_LEGACY;
end
end
`S_INTRCLTR_CLEARING_LEGACY : begin
rIntr = 1;
rIntrAssert = 0;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
end
`S_INTRCLTR_DONE : begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
default: begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
endcase
end
// Update the state.
always @(posedge CLK) begin
if (RST)
rState <= #1 `S_INTRCTLR_IDLE;
else
rState <= #1 rStateNext;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_of_pre_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
/******************************************************************************
**$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $
**$Date: 2011/06/02 08:35:07 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $
******************************************************************************/
`timescale 1 ps / 1 ps
module mig_7series_v1_9_ddr_of_pre_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input full_in, // FULL flag from OUT_FIFO
input wr_en_in, // write enable from controller
input [WIDTH-1:0] d_in, // write data from controller
output wr_en_out, // write enable to OUT_FIFO
output [WIDTH-1:0] d_out, // write data to OUT_FIFO
output afull // almost full signal to controller
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
((DEPTH == 3) || (DEPTH == 4)) ? 2 :
(((DEPTH == 5) || (DEPTH == 6) ||
(DEPTH == 7) || (DEPTH == 8)) ? 3 :
DEPTH == 9 ? 4 : 'bx);
// Set watermark. Always give the MC 5 cycles to engage flow control.
localparam ALMOST_FULL_VALUE = DEPTH - 5;
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1] ;
(* keep = "true", max_fanout = 3 *) reg [8:0] my_empty /* synthesis syn_maxfan = 3 */;
(* keep = "true", max_fanout = 3 *) reg [5:0] my_full /* synthesis syn_maxfan = 3 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS:0] entry_cnt;
wire [PTR_BITS-1:0] nxt_rd_ptr;
wire [PTR_BITS-1:0] nxt_wr_ptr;
wire [WIDTH-1:0] mem_out;
wire wr_en;
assign d_out = my_empty[0] ? d_in : mem_out;
assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in);
assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in));
always @ (posedge clk)
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
assign mem_out = mem[rd_ptr];
assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst) begin
rd_ptr <= 'b0;
rd_ptr_timing <= 'b0;
end
else if ((!my_empty[4]) & (!full_in)) begin
rd_ptr <= nxt_rd_ptr;
rd_ptr_timing <= nxt_rd_ptr;
end
end
always @ (posedge clk)
begin
if (rst)
my_empty <= 9'h1ff;
else begin
if (my_empty[2] & !my_full[3] & full_in & wr_en_in)
my_empty[3:0] <= 4'b0000;
else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin
my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing);
end
if (my_empty[8] & !my_full[5] & full_in & wr_en_in)
my_empty[8:4] <= 5'b00000;
else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin
my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing);
end
end
end
assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst) begin
wr_ptr <= 'b0;
wr_ptr_timing <= 'b0;
end
else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin
wr_ptr <= nxt_wr_ptr;
wr_ptr_timing <= nxt_wr_ptr;
end
end
always @ (posedge clk)
begin
if (rst)
my_full <= 6'b000000;
else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in)
my_full <= 6'b000000;
else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin
my_full[0] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[1] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[2] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[3] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[4] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[5] <= (nxt_wr_ptr == rd_ptr_timing);
end
end
always @ (posedge clk)
begin
if (rst)
entry_cnt <= 'b0;
else if (wr_en_in & full_in & !my_full[4])
entry_cnt <= entry_cnt + 1'b1;
else if (!wr_en_in & !full_in & !my_empty[7])
entry_cnt <= entry_cnt - 1'b1;
end
assign afull = (entry_cnt >= ALMOST_FULL_VALUE);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_of_pre_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Extends the depth of a PHASER OUT_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
/******************************************************************************
**$Id: ddr_of_pre_fifo.v,v 1.1 2011/06/02 08:35:07 mishra Exp $
**$Date: 2011/06/02 08:35:07 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_of_pre_fifo.v,v $
******************************************************************************/
`timescale 1 ps / 1 ps
module mig_7series_v1_9_ddr_of_pre_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input full_in, // FULL flag from OUT_FIFO
input wr_en_in, // write enable from controller
input [WIDTH-1:0] d_in, // write data from controller
output wr_en_out, // write enable to OUT_FIFO
output [WIDTH-1:0] d_out, // write data to OUT_FIFO
output afull // almost full signal to controller
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
((DEPTH == 3) || (DEPTH == 4)) ? 2 :
(((DEPTH == 5) || (DEPTH == 6) ||
(DEPTH == 7) || (DEPTH == 8)) ? 3 :
DEPTH == 9 ? 4 : 'bx);
// Set watermark. Always give the MC 5 cycles to engage flow control.
localparam ALMOST_FULL_VALUE = DEPTH - 5;
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1] ;
(* keep = "true", max_fanout = 3 *) reg [8:0] my_empty /* synthesis syn_maxfan = 3 */;
(* keep = "true", max_fanout = 3 *) reg [5:0] my_full /* synthesis syn_maxfan = 3 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */;
(* keep = "true", max_fanout = 10 *) reg [PTR_BITS-1:0] wr_ptr_timing /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS:0] entry_cnt;
wire [PTR_BITS-1:0] nxt_rd_ptr;
wire [PTR_BITS-1:0] nxt_wr_ptr;
wire [WIDTH-1:0] mem_out;
wire wr_en;
assign d_out = my_empty[0] ? d_in : mem_out;
assign wr_en_out = !full_in && (!my_empty[1] || wr_en_in);
assign wr_en = wr_en_in & ((!my_empty[3] & !full_in)|(!my_full[2] & full_in));
always @ (posedge clk)
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
assign mem_out = mem[rd_ptr];
assign nxt_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst) begin
rd_ptr <= 'b0;
rd_ptr_timing <= 'b0;
end
else if ((!my_empty[4]) & (!full_in)) begin
rd_ptr <= nxt_rd_ptr;
rd_ptr_timing <= nxt_rd_ptr;
end
end
always @ (posedge clk)
begin
if (rst)
my_empty <= 9'h1ff;
else begin
if (my_empty[2] & !my_full[3] & full_in & wr_en_in)
my_empty[3:0] <= 4'b0000;
else if (!my_empty[2] & !my_full[3] & !full_in & !wr_en_in) begin
my_empty[0] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[1] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[2] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[3] <= (nxt_rd_ptr == wr_ptr_timing);
end
if (my_empty[8] & !my_full[5] & full_in & wr_en_in)
my_empty[8:4] <= 5'b00000;
else if (!my_empty[8] & !my_full[5] & !full_in & !wr_en_in) begin
my_empty[4] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[5] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[6] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[7] <= (nxt_rd_ptr == wr_ptr_timing);
my_empty[8] <= (nxt_rd_ptr == wr_ptr_timing);
end
end
end
assign nxt_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
always @ (posedge clk)
begin
if (rst) begin
wr_ptr <= 'b0;
wr_ptr_timing <= 'b0;
end
else if ((wr_en_in) & ((!my_empty[5] & !full_in) | (!my_full[1] & full_in))) begin
wr_ptr <= nxt_wr_ptr;
wr_ptr_timing <= nxt_wr_ptr;
end
end
always @ (posedge clk)
begin
if (rst)
my_full <= 6'b000000;
else if (!my_empty[6] & my_full[0] & !full_in & !wr_en_in)
my_full <= 6'b000000;
else if (!my_empty[6] & !my_full[0] & full_in & wr_en_in) begin
my_full[0] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[1] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[2] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[3] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[4] <= (nxt_wr_ptr == rd_ptr_timing);
my_full[5] <= (nxt_wr_ptr == rd_ptr_timing);
end
end
always @ (posedge clk)
begin
if (rst)
entry_cnt <= 'b0;
else if (wr_en_in & full_in & !my_full[4])
entry_cnt <= entry_cnt + 1'b1;
else if (!wr_en_in & !full_in & !my_empty[7])
entry_cnt <= entry_cnt - 1'b1;
end
assign afull = (entry_cnt >= ALMOST_FULL_VALUE);
endmodule
|
module altera_edge_detector #(
parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle
parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge
parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out
) (
input clk,
input rst_n,
input signal_in,
output pulse_out
);
localparam IDLE = 0, ARM = 1, CAPT = 2;
localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0;
localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1;
reg [1:0] state, next_state;
reg pulse_detect;
wire busy_pulsing;
assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0;
assign reset_qual_n = rst_n | busy_pulsing;
generate
if (PULSE_EXT > 1) begin: pulse_extend
integer i;
reg [PULSE_EXT-1:0] extend_pulse;
always @(posedge clk or negedge reset_qual_n) begin
if (!reset_qual_n)
extend_pulse <= {{PULSE_EXT}{1'b0}};
else begin
for (i = 1; i < PULSE_EXT; i = i+1) begin
extend_pulse[i] <= extend_pulse[i-1];
end
extend_pulse[0] <= pulse_detect;
end
end
assign pulse_out = |extend_pulse;
end
else begin: single_pulse
reg pulse_reg;
always @(posedge clk or negedge reset_qual_n) begin
if (!reset_qual_n)
pulse_reg <= 1'b0;
else
pulse_reg <= pulse_detect;
end
assign pulse_out = pulse_reg;
end
endgenerate
always @(posedge clk) begin
if (!rst_n)
state <= IDLE;
else
state <= next_state;
end
// edge detect
always @(*) begin
next_state = state;
pulse_detect = 1'b0;
case (state)
IDLE : begin
pulse_detect = 1'b0;
if (signal_in == SIGNAL_DEASSERT) next_state = ARM;
else next_state = IDLE;
end
ARM : begin
pulse_detect = 1'b0;
if (signal_in == SIGNAL_ASSERT) next_state = CAPT;
else next_state = ARM;
end
CAPT : begin
pulse_detect = 1'b1;
if (signal_in == SIGNAL_DEASSERT) next_state = ARM;
else next_state = IDLE;
end
default : begin
pulse_detect = 1'b0;
next_state = IDLE;
end
endcase
end
endmodule
|
module altera_edge_detector #(
parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle
parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge
parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out
) (
input clk,
input rst_n,
input signal_in,
output pulse_out
);
localparam IDLE = 0, ARM = 1, CAPT = 2;
localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0;
localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1;
reg [1:0] state, next_state;
reg pulse_detect;
wire busy_pulsing;
assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0;
assign reset_qual_n = rst_n | busy_pulsing;
generate
if (PULSE_EXT > 1) begin: pulse_extend
integer i;
reg [PULSE_EXT-1:0] extend_pulse;
always @(posedge clk or negedge reset_qual_n) begin
if (!reset_qual_n)
extend_pulse <= {{PULSE_EXT}{1'b0}};
else begin
for (i = 1; i < PULSE_EXT; i = i+1) begin
extend_pulse[i] <= extend_pulse[i-1];
end
extend_pulse[0] <= pulse_detect;
end
end
assign pulse_out = |extend_pulse;
end
else begin: single_pulse
reg pulse_reg;
always @(posedge clk or negedge reset_qual_n) begin
if (!reset_qual_n)
pulse_reg <= 1'b0;
else
pulse_reg <= pulse_detect;
end
assign pulse_out = pulse_reg;
end
endgenerate
always @(posedge clk) begin
if (!rst_n)
state <= IDLE;
else
state <= next_state;
end
// edge detect
always @(*) begin
next_state = state;
pulse_detect = 1'b0;
case (state)
IDLE : begin
pulse_detect = 1'b0;
if (signal_in == SIGNAL_DEASSERT) next_state = ARM;
else next_state = IDLE;
end
ARM : begin
pulse_detect = 1'b0;
if (signal_in == SIGNAL_ASSERT) next_state = CAPT;
else next_state = ARM;
end
CAPT : begin
pulse_detect = 1'b1;
if (signal_in == SIGNAL_DEASSERT) next_state = ARM;
else next_state = IDLE;
end
default : begin
pulse_detect = 1'b0;
next_state = IDLE;
end
endcase
end
endmodule
|
module altera_edge_detector #(
parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle
parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge
parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out
) (
input clk,
input rst_n,
input signal_in,
output pulse_out
);
localparam IDLE = 0, ARM = 1, CAPT = 2;
localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0;
localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1;
reg [1:0] state, next_state;
reg pulse_detect;
wire busy_pulsing;
assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0;
assign reset_qual_n = rst_n | busy_pulsing;
generate
if (PULSE_EXT > 1) begin: pulse_extend
integer i;
reg [PULSE_EXT-1:0] extend_pulse;
always @(posedge clk or negedge reset_qual_n) begin
if (!reset_qual_n)
extend_pulse <= {{PULSE_EXT}{1'b0}};
else begin
for (i = 1; i < PULSE_EXT; i = i+1) begin
extend_pulse[i] <= extend_pulse[i-1];
end
extend_pulse[0] <= pulse_detect;
end
end
assign pulse_out = |extend_pulse;
end
else begin: single_pulse
reg pulse_reg;
always @(posedge clk or negedge reset_qual_n) begin
if (!reset_qual_n)
pulse_reg <= 1'b0;
else
pulse_reg <= pulse_detect;
end
assign pulse_out = pulse_reg;
end
endgenerate
always @(posedge clk) begin
if (!rst_n)
state <= IDLE;
else
state <= next_state;
end
// edge detect
always @(*) begin
next_state = state;
pulse_detect = 1'b0;
case (state)
IDLE : begin
pulse_detect = 1'b0;
if (signal_in == SIGNAL_DEASSERT) next_state = ARM;
else next_state = IDLE;
end
ARM : begin
pulse_detect = 1'b0;
if (signal_in == SIGNAL_ASSERT) next_state = CAPT;
else next_state = ARM;
end
CAPT : begin
pulse_detect = 1'b1;
if (signal_in == SIGNAL_DEASSERT) next_state = ARM;
else next_state = IDLE;
end
default : begin
pulse_detect = 1'b0;
next_state = IDLE;
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
// verilator lint_off LITENDIAN
reg [5:0] binary_nostart [2:15];
reg [5:0] binary_start [0:15];
reg [175:0] hex [0:15];
// verilator lint_on LITENDIAN
integer i;
initial begin
begin
$readmemb("t/t_sys_readmem_b.mem", binary_nostart);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_nostart[i]);
`endif
if (binary_nostart['h2] != 6'h02) $stop;
if (binary_nostart['h3] != 6'h03) $stop;
if (binary_nostart['h4] != 6'h04) $stop;
if (binary_nostart['h5] != 6'h05) $stop;
if (binary_nostart['h6] != 6'h06) $stop;
if (binary_nostart['h7] != 6'h07) $stop;
if (binary_nostart['h8] != 6'h10) $stop;
if (binary_nostart['hc] != 6'h14) $stop;
if (binary_nostart['hd] != 6'h15) $stop;
end
begin
$readmemb("t/t_sys_readmem_b_8.mem", binary_start, 4, 4+7);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_start[i]);
`endif
if (binary_start['h04] != 6'h10) $stop;
if (binary_start['h05] != 6'h11) $stop;
if (binary_start['h06] != 6'h12) $stop;
if (binary_start['h07] != 6'h13) $stop;
if (binary_start['h08] != 6'h14) $stop;
if (binary_start['h09] != 6'h15) $stop;
if (binary_start['h0a] != 6'h16) $stop;
if (binary_start['h0b] != 6'h17) $stop;
end
begin
$readmemh("t/t_sys_readmem_h.mem", hex, 0);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex[i]);
`endif
if (hex['h04] != 176'h400437654321276543211765432107654321abcdef10) $stop;
if (hex['h0a] != 176'h400a37654321276543211765432107654321abcdef11) $stop;
if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop;
if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: fifo_packer_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Packs 32 bit received data into a 32 bit wide FIFO.
// Assumes the FIFO always has room to accommodate the data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
// Additional Comments:
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module fifo_packer_32 (
input CLK,
input RST,
input [31:0] DATA_IN, // Incoming data
input DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [31:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [31:0] rDataIn=64'd0, _rDataIn=64'd0;
reg rDataInEn=0, _rDataInEn=0;
assign PACKED_DATA = rDataIn;
assign PACKED_WEN = rDataInEn;
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data to ease timing.
always @ (posedge CLK) begin
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 1'd0 : _rDataInEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
_rDataInEn = DATA_IN_EN;
// Track done/error/flush signals.
_rPackedDone = DATA_IN_DONE;
_rPackedErr = DATA_IN_ERR;
_rPackedFlush = DATA_IN_FLUSH;
_rPackedFlushed = rPackedFlush;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: fifo_packer_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Packs 32 bit received data into a 32 bit wide FIFO.
// Assumes the FIFO always has room to accommodate the data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
// Additional Comments:
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module fifo_packer_32 (
input CLK,
input RST,
input [31:0] DATA_IN, // Incoming data
input DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [31:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [31:0] rDataIn=64'd0, _rDataIn=64'd0;
reg rDataInEn=0, _rDataInEn=0;
assign PACKED_DATA = rDataIn;
assign PACKED_WEN = rDataInEn;
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data to ease timing.
always @ (posedge CLK) begin
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 1'd0 : _rDataInEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
_rDataInEn = DATA_IN_EN;
// Track done/error/flush signals.
_rPackedDone = DATA_IN_DONE;
_rPackedErr = DATA_IN_ERR;
_rPackedFlush = DATA_IN_FLUSH;
_rPackedFlushed = rPackedFlush;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: fifo_packer_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Packs 32 bit received data into a 32 bit wide FIFO.
// Assumes the FIFO always has room to accommodate the data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
// Additional Comments:
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module fifo_packer_32 (
input CLK,
input RST,
input [31:0] DATA_IN, // Incoming data
input DATA_IN_EN, // Incoming data enable
input DATA_IN_DONE, // Incoming data packet end
input DATA_IN_ERR, // Incoming data error
input DATA_IN_FLUSH, // End of incoming data
output [31:0] PACKED_DATA, // Outgoing data
output PACKED_WEN, // Outgoing data write enable
output PACKED_DATA_DONE, // End of outgoing data packet
output PACKED_DATA_ERR, // Error in outgoing data
output PACKED_DATA_FLUSHED // End of outgoing data
);
reg rPackedDone=0, _rPackedDone=0;
reg rPackedErr=0, _rPackedErr=0;
reg rPackedFlush=0, _rPackedFlush=0;
reg rPackedFlushed=0, _rPackedFlushed=0;
reg [31:0] rDataIn=64'd0, _rDataIn=64'd0;
reg rDataInEn=0, _rDataInEn=0;
assign PACKED_DATA = rDataIn;
assign PACKED_WEN = rDataInEn;
assign PACKED_DATA_DONE = rPackedDone;
assign PACKED_DATA_ERR = rPackedErr;
assign PACKED_DATA_FLUSHED = rPackedFlushed;
// Buffers input data to ease timing.
always @ (posedge CLK) begin
rPackedDone <= #1 (RST ? 1'd0 : _rPackedDone);
rPackedErr <= #1 (RST ? 1'd0 : _rPackedErr);
rPackedFlush <= #1 (RST ? 1'd0 : _rPackedFlush);
rPackedFlushed <= #1 (RST ? 1'd0 : _rPackedFlushed);
rDataIn <= #1 _rDataIn;
rDataInEn <= #1 (RST ? 1'd0 : _rDataInEn);
end
always @ (*) begin
// Buffer and mask the input data.
_rDataIn = DATA_IN;
_rDataInEn = DATA_IN_EN;
// Track done/error/flush signals.
_rPackedDone = DATA_IN_DONE;
_rPackedErr = DATA_IN_ERR;
_rPackedFlush = DATA_IN_FLUSH;
_rPackedFlushed = rPackedFlush;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sg_list_reader_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Reads data from the scatter gather list buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_SGR128_RD_0 1'b1
`define S_SGR128_RD_WAIT 1'b0
`define S_SGR128_CAP_0 1'b0
`define S_SGR128_CAP_RDY 1'b1
`timescale 1ns/1ns
module sg_list_reader_128 #(
parameter C_DATA_WIDTH = 9'd128
)
(
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output VALID, // Scatter gather element data is valid
output EMPTY, // Scatter gather elements empty
input REN, // Scatter gather element data read enable
output [63:0] ADDR, // Scatter gather element address
output [31:0] LEN // Scatter gather element length (in words)
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg rRdState=`S_SGR128_RD_0, _rRdState=`S_SGR128_RD_0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg rCapState=`S_SGR128_CAP_0, _rCapState=`S_SGR128_CAP_0;
reg [C_DATA_WIDTH-1:0] rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rLen=0, _rLen=0;
reg rFifoValid=0, _rFifoValid=0;
reg rDataValid=0, _rDataValid=0;
assign BUF_DATA_REN = rRdState; // Not S_SGR128_RD_WAIT
assign VALID = rCapState; // S_SGR128_CAP_RDY
assign EMPTY = (BUF_DATA_EMPTY & rRdState); // Not S_SGR128_RD_WAIT
assign ADDR = rAddr;
assign LEN = rLen;
// Capture address and length as it comes out of the FIFO
always @ (posedge CLK) begin
rRdState <= #1 (RST ? `S_SGR128_RD_0 : _rRdState);
rCapState <= #1 (RST ? `S_SGR128_CAP_0 : _rCapState);
rData <= #1 _rData;
rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
end
always @ (*) begin
_rRdState = rRdState;
_rCapState = rCapState;
_rAddr = rAddr;
_rLen = rLen;
_rData = BUF_DATA;
_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
_rDataValid = rFifoValid;
case (rCapState)
`S_SGR128_CAP_0: begin
if (rDataValid) begin
_rAddr = rData[63:0];
_rLen = rData[95:64];
_rCapState = `S_SGR128_CAP_RDY;
end
end
`S_SGR128_CAP_RDY: begin
if (REN)
_rCapState = `S_SGR128_CAP_0;
end
endcase
case (rRdState)
`S_SGR128_RD_0: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR128_RD_WAIT;
end
`S_SGR128_RD_WAIT: begin // Wait for the data to be consumed
if (REN)
_rRdState = `S_SGR128_RD_0;
end
endcase
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sg_list_reader_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Reads data from the scatter gather list buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_SGR128_RD_0 1'b1
`define S_SGR128_RD_WAIT 1'b0
`define S_SGR128_CAP_0 1'b0
`define S_SGR128_CAP_RDY 1'b1
`timescale 1ns/1ns
module sg_list_reader_128 #(
parameter C_DATA_WIDTH = 9'd128
)
(
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output VALID, // Scatter gather element data is valid
output EMPTY, // Scatter gather elements empty
input REN, // Scatter gather element data read enable
output [63:0] ADDR, // Scatter gather element address
output [31:0] LEN // Scatter gather element length (in words)
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg rRdState=`S_SGR128_RD_0, _rRdState=`S_SGR128_RD_0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg rCapState=`S_SGR128_CAP_0, _rCapState=`S_SGR128_CAP_0;
reg [C_DATA_WIDTH-1:0] rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rLen=0, _rLen=0;
reg rFifoValid=0, _rFifoValid=0;
reg rDataValid=0, _rDataValid=0;
assign BUF_DATA_REN = rRdState; // Not S_SGR128_RD_WAIT
assign VALID = rCapState; // S_SGR128_CAP_RDY
assign EMPTY = (BUF_DATA_EMPTY & rRdState); // Not S_SGR128_RD_WAIT
assign ADDR = rAddr;
assign LEN = rLen;
// Capture address and length as it comes out of the FIFO
always @ (posedge CLK) begin
rRdState <= #1 (RST ? `S_SGR128_RD_0 : _rRdState);
rCapState <= #1 (RST ? `S_SGR128_CAP_0 : _rCapState);
rData <= #1 _rData;
rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
end
always @ (*) begin
_rRdState = rRdState;
_rCapState = rCapState;
_rAddr = rAddr;
_rLen = rLen;
_rData = BUF_DATA;
_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
_rDataValid = rFifoValid;
case (rCapState)
`S_SGR128_CAP_0: begin
if (rDataValid) begin
_rAddr = rData[63:0];
_rLen = rData[95:64];
_rCapState = `S_SGR128_CAP_RDY;
end
end
`S_SGR128_CAP_RDY: begin
if (REN)
_rCapState = `S_SGR128_CAP_0;
end
endcase
case (rRdState)
`S_SGR128_RD_0: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR128_RD_WAIT;
end
`S_SGR128_RD_WAIT: begin // Wait for the data to be consumed
if (REN)
_rRdState = `S_SGR128_RD_0;
end
endcase
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sg_list_requester.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives scatter gather address/length info and requests
// the scatter gather data from the RX engine. Monitors the state of the scatter
// gather FIFO to make sure it can accommodate the requested data. Also signals
// when the entire scatter gather data has been received so the buffer can be
// overwritten with new data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_SGREQ_IDLE 8'b0000_0001
`define S_SGREQ_WAIT_0 8'b0000_0010
`define S_SGREQ_WAIT_1 8'b0000_0100
`define S_SGREQ_CHECK 8'b0000_1000
`define S_SGREQ_ISSUE 8'b0001_0000
`define S_SGREQ_UPDATE 8'b0010_0000
`define S_SGREQ_COUNT 8'b0100_0000
`define S_SGREQ_FLUSH 8'b1000_0000
`timescale 1ns/1ns
module sg_list_requester #(
parameter C_FIFO_DATA_WIDTH = 9'd64,
parameter C_FIFO_DEPTH = 1024,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_WORDS_PER_ELEM = 4,
parameter C_MAX_ELEMS = 200,
parameter C_MAX_ENTRIES = (C_MAX_ELEMS*C_WORDS_PER_ELEM),
parameter C_FIFO_COUNT_THRESH = C_FIFO_DEPTH - C_MAX_ENTRIES
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input USER_RST, // User reset, should clear FIFO data too
output BUF_RECVD, // Signals when scatter gather buffer received
input [31:0] BUF_DATA, // Buffer data
input BUF_LEN_VALID, // Buffer length valid
input BUF_ADDR_HI_VALID, // Buffer high address valid
input BUF_ADDR_LO_VALID, // Buffer low address valid
input [C_FIFO_DEPTH_WIDTH-1:0] FIFO_COUNT, // Scatter gather FIFO count
output FIFO_FLUSH, // Scatter gather FIFO flush request
input FIFO_FLUSHED, // Scatter gather FIFO flushed
output FIFO_RST, // Scatter gather FIFO data reset request
output RX_REQ, // Issue a read request
output [63:0] RX_ADDR, // Request address
output [9:0] RX_LEN, // Request length
input RX_REQ_ACK, // Request has been issued
input RX_DONE // Request has completed (data received)
);
`include "functions.vh"
reg [31:0] rData=0, _rData=0;
reg rAddrHiValid=0, _rAddrHiValid=0;
reg rAddrLoValid=0, _rAddrLoValid=0;
reg rLenValid=0, _rLenValid=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [7:0] rState=`S_SGREQ_IDLE, _rState=`S_SGREQ_IDLE;
reg rDone=0, _rDone=0;
reg rDelay=0, _rDelay=0;
reg [2:0] rCarry=0, _rCarry=0;
reg [3:0] rValsProp=0, _rValsProp=0;
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rBufWords=0, _rBufWords=0;
reg [10:0] rPageRem=0, _rPageRem=0;
reg rPageSpill=0, _rPageSpill=0;
reg [10:0] rPreLen=0, _rPreLen=0;
reg [2:0] rMaxPayloadTrain=0, _rMaxPayloadTrain=0;
reg [2:0] rMaxPayloadShift=0, _rMaxPayloadShift=0;
reg [9:0] rMaxPayload=0, _rMaxPayload=0;
reg rPayloadSpill=0, _rPayloadSpill=0;
reg [9:0] rLen=0, _rLen=0;
reg rBufWordsEQ0Hi=0, _rBufWordsEQ0Hi=0;
reg rBufWordsEQ0Lo=0, _rBufWordsEQ0Lo=0;
reg rUserRst=0, _rUserRst=0;
reg rRecvdAll=0, _rRecvdAll=0;
reg [10:0] rAckCount=0, _rAckCount=0;
assign BUF_RECVD = rDone;
assign FIFO_FLUSH = rState[7]; // S_SGREQ_FLUSH
assign FIFO_RST = (rUserRst & rState[0]); // S_SGREQ_IDLE
assign RX_ADDR = rAddr;
assign RX_LEN = rLen;
assign RX_REQ = rState[4]; // S_SGREQ_ISSUE
// Buffer signals coming from outside the rx_port.
always @ (posedge CLK) begin
rData <= #1 _rData;
rAddrHiValid <= #1 _rAddrHiValid;
rAddrLoValid <= #1 _rAddrLoValid;
rLenValid <= #1 _rLenValid;
end
always @ (*) begin
_rData = BUF_DATA;
_rAddrHiValid = BUF_ADDR_HI_VALID;
_rAddrLoValid = BUF_ADDR_LO_VALID;
_rLenValid = BUF_LEN_VALID;
end
// Handle requesting the next scatter gather buffer data.
wire [9:0] wAddrLoInv = ~rAddr[11:2];
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_SGREQ_IDLE : _rState);
rDone <= #1 (RST ? 1'd0 : _rDone);
rDelay <= #1 _rDelay;
rAddr <= #1 _rAddr;
rCarry <= #1 _rCarry;
rBufWords <= #1 _rBufWords;
rValsProp <= #1 _rValsProp;
rPageRem <= #1 _rPageRem;
rPageSpill <= #1 _rPageSpill;
rPreLen <= #1 _rPreLen;
rMaxPayloadTrain <= #1 _rMaxPayloadTrain;
rMaxPayloadShift <= #1 _rMaxPayloadShift;
rMaxPayload <= #1 _rMaxPayload;
rPayloadSpill <= #1 _rPayloadSpill;
rLen <= #1 _rLen;
rBufWordsEQ0Hi <= #1 _rBufWordsEQ0Hi;
rBufWordsEQ0Lo <= #1 _rBufWordsEQ0Lo;
rUserRst <= #1 (RST ? 1'd0 : _rUserRst);
end
always @ (*) begin
_rState = rState;
_rDone = rDone;
_rDelay = rDelay;
_rUserRst = ((rUserRst & !rState[0]) | USER_RST);
_rValsProp = ((rValsProp<<1) | RX_REQ_ACK);
{_rCarry[0], _rAddr[15:0]} = (rAddrLoValid ? rData[15:0] : (rAddr[15:0] + ({12{RX_REQ_ACK}} & {2'b0,rLen}<<2)));
{_rCarry[1], _rAddr[31:16]} = (rAddrLoValid ? rData[31:16] : (rAddr[31:16] + rCarry[0]));
{_rCarry[2], _rAddr[47:32]} = (rAddrHiValid ? rData[15:0] : (rAddr[47:32] + rCarry[1]));
_rAddr[63:48] = (rAddrHiValid ? rData[31:16] : (rAddr[63:48] + rCarry[2]));
_rBufWords = (rLenValid ? rData : rBufWords) - ({10{RX_REQ_ACK}} & rLen);
_rPageRem = (wAddrLoInv + 1'd1);
_rPageSpill = (rBufWords > rPageRem);
_rPreLen = (rPageSpill ? rPageRem : rBufWords[10:0]);
_rMaxPayloadTrain = (CONFIG_MAX_READ_REQUEST_SIZE > 3'd4 ? 3'd4 : CONFIG_MAX_READ_REQUEST_SIZE);
_rMaxPayloadShift = (C_MAX_READ_REQ[2:0] < rMaxPayloadTrain ? C_MAX_READ_REQ[2:0] : rMaxPayloadTrain);
_rMaxPayload = (6'd32<<rMaxPayloadShift);
_rPayloadSpill = (rPreLen > rMaxPayload);
_rLen = (rPayloadSpill ? rMaxPayload : rPreLen[9:0]);
_rBufWordsEQ0Hi = (16'd0 == rBufWords[31:16]);
_rBufWordsEQ0Lo = (16'd0 == rBufWords[15:0]);
case (rState)
`S_SGREQ_IDLE: begin // Wait for addr & length
_rDone = 0;
if (rLenValid)
_rState = `S_SGREQ_WAIT_0;
end
`S_SGREQ_WAIT_0: begin // Wait 1 cycle for values to propagate
_rDelay = 0;
_rState = `S_SGREQ_WAIT_1;
end
`S_SGREQ_WAIT_1: begin // Wait 2 cycles for values to propagate
_rDelay = 1;
if (rDelay)
_rState = `S_SGREQ_CHECK;
end
`S_SGREQ_CHECK: begin // Wait for space to be made available
if (FIFO_COUNT < C_FIFO_COUNT_THRESH)
_rState = `S_SGREQ_ISSUE;
else if (rUserRst)
_rState = `S_SGREQ_COUNT;
end
`S_SGREQ_ISSUE: begin // Wait for read request to be serviced
if (RX_REQ_ACK)
_rState = `S_SGREQ_UPDATE;
end
`S_SGREQ_UPDATE: begin // Update the address and length
if (rUserRst | (rBufWordsEQ0Hi & rBufWordsEQ0Lo))
_rState = `S_SGREQ_COUNT;
else if (rValsProp[3])
_rState = `S_SGREQ_ISSUE;
end
`S_SGREQ_COUNT: begin // Wait for read data to arrive
if (rRecvdAll)
_rState = `S_SGREQ_FLUSH;
end
`S_SGREQ_FLUSH: begin // Wait for read data to arrive
if (FIFO_FLUSHED) begin
_rDone = !rUserRst;
_rState = `S_SGREQ_IDLE;
end
end
default: begin
_rState = `S_SGREQ_IDLE;
end
endcase
end
// Keep track of requests made and requests completed so we know when all
// the outstanding data has been received.
always @ (posedge CLK) begin
rAckCount <= #1 (RST ? 10'd0 : _rAckCount);
rRecvdAll <= #1 _rRecvdAll;
end
always @ (*) begin
// Track REQ_DONE and SG_DONE to maintain an outstanding request count.
_rRecvdAll = (rAckCount == 10'd0);
if (rState[0]) // S_SGREQ_IDLE
_rAckCount = 0;
else
_rAckCount = rAckCount + RX_REQ_ACK - RX_DONE;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sg_list_requester.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives scatter gather address/length info and requests
// the scatter gather data from the RX engine. Monitors the state of the scatter
// gather FIFO to make sure it can accommodate the requested data. Also signals
// when the entire scatter gather data has been received so the buffer can be
// overwritten with new data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_SGREQ_IDLE 8'b0000_0001
`define S_SGREQ_WAIT_0 8'b0000_0010
`define S_SGREQ_WAIT_1 8'b0000_0100
`define S_SGREQ_CHECK 8'b0000_1000
`define S_SGREQ_ISSUE 8'b0001_0000
`define S_SGREQ_UPDATE 8'b0010_0000
`define S_SGREQ_COUNT 8'b0100_0000
`define S_SGREQ_FLUSH 8'b1000_0000
`timescale 1ns/1ns
module sg_list_requester #(
parameter C_FIFO_DATA_WIDTH = 9'd64,
parameter C_FIFO_DEPTH = 1024,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_WORDS_PER_ELEM = 4,
parameter C_MAX_ELEMS = 200,
parameter C_MAX_ENTRIES = (C_MAX_ELEMS*C_WORDS_PER_ELEM),
parameter C_FIFO_COUNT_THRESH = C_FIFO_DEPTH - C_MAX_ENTRIES
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input USER_RST, // User reset, should clear FIFO data too
output BUF_RECVD, // Signals when scatter gather buffer received
input [31:0] BUF_DATA, // Buffer data
input BUF_LEN_VALID, // Buffer length valid
input BUF_ADDR_HI_VALID, // Buffer high address valid
input BUF_ADDR_LO_VALID, // Buffer low address valid
input [C_FIFO_DEPTH_WIDTH-1:0] FIFO_COUNT, // Scatter gather FIFO count
output FIFO_FLUSH, // Scatter gather FIFO flush request
input FIFO_FLUSHED, // Scatter gather FIFO flushed
output FIFO_RST, // Scatter gather FIFO data reset request
output RX_REQ, // Issue a read request
output [63:0] RX_ADDR, // Request address
output [9:0] RX_LEN, // Request length
input RX_REQ_ACK, // Request has been issued
input RX_DONE // Request has completed (data received)
);
`include "functions.vh"
reg [31:0] rData=0, _rData=0;
reg rAddrHiValid=0, _rAddrHiValid=0;
reg rAddrLoValid=0, _rAddrLoValid=0;
reg rLenValid=0, _rLenValid=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [7:0] rState=`S_SGREQ_IDLE, _rState=`S_SGREQ_IDLE;
reg rDone=0, _rDone=0;
reg rDelay=0, _rDelay=0;
reg [2:0] rCarry=0, _rCarry=0;
reg [3:0] rValsProp=0, _rValsProp=0;
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rBufWords=0, _rBufWords=0;
reg [10:0] rPageRem=0, _rPageRem=0;
reg rPageSpill=0, _rPageSpill=0;
reg [10:0] rPreLen=0, _rPreLen=0;
reg [2:0] rMaxPayloadTrain=0, _rMaxPayloadTrain=0;
reg [2:0] rMaxPayloadShift=0, _rMaxPayloadShift=0;
reg [9:0] rMaxPayload=0, _rMaxPayload=0;
reg rPayloadSpill=0, _rPayloadSpill=0;
reg [9:0] rLen=0, _rLen=0;
reg rBufWordsEQ0Hi=0, _rBufWordsEQ0Hi=0;
reg rBufWordsEQ0Lo=0, _rBufWordsEQ0Lo=0;
reg rUserRst=0, _rUserRst=0;
reg rRecvdAll=0, _rRecvdAll=0;
reg [10:0] rAckCount=0, _rAckCount=0;
assign BUF_RECVD = rDone;
assign FIFO_FLUSH = rState[7]; // S_SGREQ_FLUSH
assign FIFO_RST = (rUserRst & rState[0]); // S_SGREQ_IDLE
assign RX_ADDR = rAddr;
assign RX_LEN = rLen;
assign RX_REQ = rState[4]; // S_SGREQ_ISSUE
// Buffer signals coming from outside the rx_port.
always @ (posedge CLK) begin
rData <= #1 _rData;
rAddrHiValid <= #1 _rAddrHiValid;
rAddrLoValid <= #1 _rAddrLoValid;
rLenValid <= #1 _rLenValid;
end
always @ (*) begin
_rData = BUF_DATA;
_rAddrHiValid = BUF_ADDR_HI_VALID;
_rAddrLoValid = BUF_ADDR_LO_VALID;
_rLenValid = BUF_LEN_VALID;
end
// Handle requesting the next scatter gather buffer data.
wire [9:0] wAddrLoInv = ~rAddr[11:2];
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_SGREQ_IDLE : _rState);
rDone <= #1 (RST ? 1'd0 : _rDone);
rDelay <= #1 _rDelay;
rAddr <= #1 _rAddr;
rCarry <= #1 _rCarry;
rBufWords <= #1 _rBufWords;
rValsProp <= #1 _rValsProp;
rPageRem <= #1 _rPageRem;
rPageSpill <= #1 _rPageSpill;
rPreLen <= #1 _rPreLen;
rMaxPayloadTrain <= #1 _rMaxPayloadTrain;
rMaxPayloadShift <= #1 _rMaxPayloadShift;
rMaxPayload <= #1 _rMaxPayload;
rPayloadSpill <= #1 _rPayloadSpill;
rLen <= #1 _rLen;
rBufWordsEQ0Hi <= #1 _rBufWordsEQ0Hi;
rBufWordsEQ0Lo <= #1 _rBufWordsEQ0Lo;
rUserRst <= #1 (RST ? 1'd0 : _rUserRst);
end
always @ (*) begin
_rState = rState;
_rDone = rDone;
_rDelay = rDelay;
_rUserRst = ((rUserRst & !rState[0]) | USER_RST);
_rValsProp = ((rValsProp<<1) | RX_REQ_ACK);
{_rCarry[0], _rAddr[15:0]} = (rAddrLoValid ? rData[15:0] : (rAddr[15:0] + ({12{RX_REQ_ACK}} & {2'b0,rLen}<<2)));
{_rCarry[1], _rAddr[31:16]} = (rAddrLoValid ? rData[31:16] : (rAddr[31:16] + rCarry[0]));
{_rCarry[2], _rAddr[47:32]} = (rAddrHiValid ? rData[15:0] : (rAddr[47:32] + rCarry[1]));
_rAddr[63:48] = (rAddrHiValid ? rData[31:16] : (rAddr[63:48] + rCarry[2]));
_rBufWords = (rLenValid ? rData : rBufWords) - ({10{RX_REQ_ACK}} & rLen);
_rPageRem = (wAddrLoInv + 1'd1);
_rPageSpill = (rBufWords > rPageRem);
_rPreLen = (rPageSpill ? rPageRem : rBufWords[10:0]);
_rMaxPayloadTrain = (CONFIG_MAX_READ_REQUEST_SIZE > 3'd4 ? 3'd4 : CONFIG_MAX_READ_REQUEST_SIZE);
_rMaxPayloadShift = (C_MAX_READ_REQ[2:0] < rMaxPayloadTrain ? C_MAX_READ_REQ[2:0] : rMaxPayloadTrain);
_rMaxPayload = (6'd32<<rMaxPayloadShift);
_rPayloadSpill = (rPreLen > rMaxPayload);
_rLen = (rPayloadSpill ? rMaxPayload : rPreLen[9:0]);
_rBufWordsEQ0Hi = (16'd0 == rBufWords[31:16]);
_rBufWordsEQ0Lo = (16'd0 == rBufWords[15:0]);
case (rState)
`S_SGREQ_IDLE: begin // Wait for addr & length
_rDone = 0;
if (rLenValid)
_rState = `S_SGREQ_WAIT_0;
end
`S_SGREQ_WAIT_0: begin // Wait 1 cycle for values to propagate
_rDelay = 0;
_rState = `S_SGREQ_WAIT_1;
end
`S_SGREQ_WAIT_1: begin // Wait 2 cycles for values to propagate
_rDelay = 1;
if (rDelay)
_rState = `S_SGREQ_CHECK;
end
`S_SGREQ_CHECK: begin // Wait for space to be made available
if (FIFO_COUNT < C_FIFO_COUNT_THRESH)
_rState = `S_SGREQ_ISSUE;
else if (rUserRst)
_rState = `S_SGREQ_COUNT;
end
`S_SGREQ_ISSUE: begin // Wait for read request to be serviced
if (RX_REQ_ACK)
_rState = `S_SGREQ_UPDATE;
end
`S_SGREQ_UPDATE: begin // Update the address and length
if (rUserRst | (rBufWordsEQ0Hi & rBufWordsEQ0Lo))
_rState = `S_SGREQ_COUNT;
else if (rValsProp[3])
_rState = `S_SGREQ_ISSUE;
end
`S_SGREQ_COUNT: begin // Wait for read data to arrive
if (rRecvdAll)
_rState = `S_SGREQ_FLUSH;
end
`S_SGREQ_FLUSH: begin // Wait for read data to arrive
if (FIFO_FLUSHED) begin
_rDone = !rUserRst;
_rState = `S_SGREQ_IDLE;
end
end
default: begin
_rState = `S_SGREQ_IDLE;
end
endcase
end
// Keep track of requests made and requests completed so we know when all
// the outstanding data has been received.
always @ (posedge CLK) begin
rAckCount <= #1 (RST ? 10'd0 : _rAckCount);
rRecvdAll <= #1 _rRecvdAll;
end
always @ (*) begin
// Track REQ_DONE and SG_DONE to maintain an outstanding request count.
_rRecvdAll = (rAckCount == 10'd0);
if (rState[0]) // S_SGREQ_IDLE
_rAckCount = 0;
else
_rAckCount = rAckCount + RX_REQ_ACK - RX_DONE;
end
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31; // Data width
parameter DATA_DEPTH = 128;
parameter AW = 6; // Address width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data),
// Unused
// synopsys translate_off
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
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// of Xilinx, Inc. and is protected under U.S. and
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_queue.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Bank machine queue controller.
//
// Bank machines are always associated with a queue. When the system is
// idle, all bank machines are in the idle queue. As requests are
// received, the bank machine at the head of the idle queue accepts
// the request, removes itself from the idle queue and places itself
// in a queue associated with the rank-bank of the new request.
//
// If the new request is to an idle rank-bank, a new queue is created
// for that rank-bank. If the rank-bank is not idle, then the new
// request is added to the end of the existing rank-bank queue.
//
// When the head of the idle queue accepts a new request, all other
// bank machines move down one in the idle queue. When the idle queue
// is empty, the memory interface deasserts its accept signal.
//
// When new requests are received, the first step is to classify them
// as to whether the request targets an already open rank-bank, and if
// so, does the new request also hit on the already open page? As mentioned
// above, a new request places itself in the existing queue for a
// rank-bank hit. If it is also detected that the last entry in the
// existing rank-bank queue has the same page, then the current tail
// sets a bit telling itself to pass the open row when the column
// command is issued. The "passee" knows its in the head minus one
// position and hence takes control of the rank-bank.
//
// Requests are retired out of order to optimize DRAM array resources.
// However it is required that the user cannot "observe" this out of
// order processing as a data corruption. An ordering queue is
// used to enforce some ordering rules. As controlled by a paramter,
// there can be no ordering (RELAXED), ordering of writes only (NORM), and
// strict (STRICT) ordering whereby input request ordering is
// strictly adhered to.
//
// Note that ordering applies only to column commands. Row commands
// such as activate and precharge are allowed to proceed in any order
// with the proviso that within a rank-bank row commands are processed in
// the request order.
//
// When a bank machine accepts a new request, it looks at the ordering
// mode. If no ordering, nothing is done. If strict ordering, then
// it always places itself at the end of the ordering queue. If "normal"
// or write ordering, the row machine places itself in the ordering
// queue only if the new request is a write. The bank state machine
// looks at the ordering queue, and will only issue a column
// command when it sees itself at the head of the ordering queue.
//
// When a bank machine has completed its request, it must re-enter the
// idle queue. This is done by setting the idle_r bit, and setting q_entry_r
// to the idle count.
//
// There are several situations where more than one bank machine
// will enter the idle queue simultaneously. If two or more
// simply use the idle count to place themselves in the idle queue, multiple
// bank machines will end up at the same location in the idle queue, which
// is illegal.
//
// Based on the bank machine instance numbers, a count is made of
// the number of bank machines entering idle "below" this instance. This
// number is added to the idle count to compute the location in
// idle queue.
//
// There is also a single bit computed that says there were bank machines
// entering the idle queue "above" this instance. This is used to
// compute the tail bit.
//
// The word "queue" is used frequently to describe the behavior of the
// bank_queue block. In reality, there are no queues in the ordinary sense.
// As instantiated in this block, each bank machine has a q_entry_r number.
// This number represents the position of the bank machine in its current
// queue. At any given time, a bank machine may be in the idle queue,
// one of the dynamic rank-bank queues, or a single entry manitenance queue.
// A complete description of which queue a bank machine is currently in is
// given by idle_r, its rank-bank, mainteance status and its q_entry_r number.
//
// DRAM refresh and ZQ have a private single entry queue/channel. However,
// when a refresh request is made, it must be injected into the main queue
// properly. At the time of injection, the refresh rank is compared against
// all entryies in the queue. For those that match, if timing allows, and
// they are the tail of the rank-bank queue, then the auto_pre bit is set.
// Otherwise precharge is in progress. This results in a fully precharged
// rank.
//
// At the time of injection, the refresh channel builds a bit
// vector of queue entries that hit on the refresh rank. Once all
// of these entries finish, the refresh is forced in at the row arbiter.
//
// New requests that come after the refresh request will notice that
// a refresh is in progress for their rank and wait for the refresh
// to finish before attempting to arbitrate to send an activate.
//
// Injection of a refresh sets the q_has_rd bit for all queues hitting
// on the refresh rank. This insures a starved write request will not
// indefinitely hold off a refresh.
//
// Periodic reads are required to compare themselves against requests
// that are in progress. Adding a unique compare channel for this
// is not worthwhile. Periodic read requests inhibit the accept
// signal and override any new request that might be trying to
// enter the queue.
//
// Once a periodic read has entered the queue it is nearly indistinguishable
// from a normal read request. The req_periodic_rd_r bit is set for
// queue entry. This signal is used to inhibit the rd_data_en signal.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v1_9_bank_queue #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter nBANK_MACHS = 4,
parameter ORDERING = "NORM",
parameter ID = 0
)
(/*AUTOARG*/
// Outputs
head_r, tail_r, idle_ns, idle_r, pass_open_bank_ns,
pass_open_bank_r, auto_pre_r, bm_end, passing_open_bank,
ordered_issued, ordered_r, order_q_zero, rcv_open_bank,
rb_hit_busies_r, q_has_rd, q_has_priority, wait_for_maint_r,
// Inputs
clk, rst, accept_internal_r, use_addr, periodic_rd_ack_r, bm_end_in,
idle_cnt, rb_hit_busy_cnt, accept_req, rb_hit_busy_r, maint_idle,
maint_hit, row_hit_r, pre_wait_r, allow_auto_pre, sending_col,
bank_wait_in_progress, precharge_bm_end, req_wr_r, rd_wr_r,
adv_order_q, order_cnt, rb_hit_busy_ns_in, passing_open_bank_in,
was_wr, maint_req_r, was_priority
);
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
// Decide if this bank machine should accept a new request.
reg idle_r_lcl;
reg head_r_lcl;
input accept_internal_r;
wire bm_ready = idle_r_lcl && head_r_lcl && accept_internal_r;
// Accept request in this bank machine. Could be maintenance or
// regular request.
input use_addr;
input periodic_rd_ack_r;
wire accept_this_bm = bm_ready && (use_addr || periodic_rd_ack_r);
// Multiple machines may enter the idle queue in a single state.
// Based on bank machine instance number, compute how many
// bank machines with lower instance numbers are entering
// the idle queue.
input [(nBANK_MACHS*2)-1:0] bm_end_in;
reg [BM_CNT_WIDTH-1:0] idlers_below;
integer i;
always @(/*AS*/bm_end_in) begin
idlers_below = BM_CNT_ZERO;
for (i=0; i<ID; i=i+1)
idlers_below = idlers_below + bm_end_in[i];
end
reg idlers_above;
always @(/*AS*/bm_end_in) begin
idlers_above = 1'b0;
for (i=ID+1; i<ID+nBANK_MACHS; i=i+1)
idlers_above = idlers_above || bm_end_in[i];
end
`ifdef MC_SVA
bm_end_and_idlers_above: cover property (@(posedge clk)
(~rst && bm_end && idlers_above));
bm_end_and_idlers_below: cover property (@(posedge clk)
(~rst && bm_end && |idlers_below));
`endif
// Compute the q_entry number.
input [BM_CNT_WIDTH-1:0] idle_cnt;
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
input accept_req;
wire bm_end_lcl;
reg adv_queue = 1'b0;
reg [BM_CNT_WIDTH-1:0] q_entry_r;
reg [BM_CNT_WIDTH-1:0] q_entry_ns;
wire [BM_CNT_WIDTH-1:0] temp;
// always @(/*AS*/accept_req or accept_this_bm or adv_queue
// or bm_end_lcl or idle_cnt or idle_r_lcl or idlers_below
// or q_entry_r or rb_hit_busy_cnt /*or rst*/) begin
//// if (rst) q_entry_ns = ID[BM_CNT_WIDTH-1:0];
//// else begin
// q_entry_ns = q_entry_r;
// if ((~idle_r_lcl && adv_queue) ||
// (idle_r_lcl && accept_req && ~accept_this_bm))
// q_entry_ns = q_entry_r - BM_CNT_ONE;
// if (accept_this_bm)
//// q_entry_ns = rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO);
// q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
// if (bm_end_lcl) begin
// q_entry_ns = idle_cnt + idlers_below;
// if (accept_req) q_entry_ns = q_entry_ns - BM_CNT_ONE;
//// end
// end
// end
assign temp = idle_cnt + idlers_below;
always @ (*)
begin
if (accept_req & bm_end_lcl)
q_entry_ns = temp - BM_CNT_ONE;
else if (bm_end_lcl)
q_entry_ns = temp;
else if (accept_this_bm)
q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
else if ((!idle_r_lcl & adv_queue) |
(idle_r_lcl & accept_req & !accept_this_bm))
q_entry_ns = q_entry_r - BM_CNT_ONE;
else
q_entry_ns = q_entry_r;
end
always @(posedge clk)
if (rst)
q_entry_r <= #TCQ ID[BM_CNT_WIDTH-1:0];
else
q_entry_r <= #TCQ q_entry_ns;
// Determine if this entry is the head of its queue.
reg head_ns;
always @(/*AS*/accept_req or accept_this_bm or adv_queue
or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl
or idlers_below or q_entry_r or rb_hit_busy_cnt or rst) begin
if (rst) head_ns = ~|ID[BM_CNT_WIDTH-1:0];
else begin
head_ns = head_r_lcl;
if (accept_this_bm)
head_ns = ~|(rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO));
if ((~idle_r_lcl && adv_queue) ||
(idle_r_lcl && accept_req && ~accept_this_bm))
head_ns = ~|(q_entry_r - BM_CNT_ONE);
if (bm_end_lcl) begin
head_ns = ~|(idle_cnt - (accept_req ? BM_CNT_ONE : BM_CNT_ZERO)) &&
~|idlers_below;
end
end
end
always @(posedge clk) head_r_lcl <= #TCQ head_ns;
output wire head_r;
assign head_r = head_r_lcl;
// Determine if this entry is the tail of its queue. Note that
// an entry can be both head and tail.
input rb_hit_busy_r;
reg tail_r_lcl = 1'b1;
generate
if (nBANK_MACHS > 1) begin : compute_tail
reg tail_ns;
always @(accept_req or accept_this_bm
or bm_end_in or bm_end_lcl or idle_r_lcl
or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin
if (rst) tail_ns = (ID == nBANK_MACHS);
// The order of the statements below is important in the case where
// another bank machine is retiring and this bank machine is accepting.
else begin
tail_ns = tail_r_lcl;
if ((accept_req && rb_hit_busy_r) ||
(|bm_end_in[`BM_SHARED_BV] && idle_r_lcl))
tail_ns = 1'b0;
if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1;
end
end
always @(posedge clk) tail_r_lcl <= #TCQ tail_ns;
end // if (nBANK_MACHS > 1)
endgenerate
output wire tail_r;
assign tail_r = tail_r_lcl;
wire clear_req = bm_end_lcl || rst;
// Is this entry in the idle queue?
reg idle_ns_lcl;
always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin
idle_ns_lcl = idle_r_lcl;
if (accept_this_bm) idle_ns_lcl = 1'b0;
if (clear_req) idle_ns_lcl = 1'b1;
end
always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl;
output wire idle_ns;
assign idle_ns = idle_ns_lcl;
output wire idle_r;
assign idle_r = idle_r_lcl;
// Maintenance hitting on this active bank machine is in progress.
input maint_idle;
input maint_hit;
wire maint_hit_this_bm = ~maint_idle && maint_hit;
// Does new request hit on this bank machine while it is able to pass the
// open bank?
input row_hit_r;
input pre_wait_r;
wire pass_open_bank_eligible =
tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r;
// Set pass open bank bit, but not if request preceded active maintenance.
reg wait_for_maint_r_lcl;
reg pass_open_bank_r_lcl;
wire pass_open_bank_ns_lcl = ~clear_req &&
(pass_open_bank_r_lcl ||
(accept_req && pass_open_bank_eligible &&
(~maint_hit_this_bm || wait_for_maint_r_lcl)));
always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl;
output wire pass_open_bank_ns;
assign pass_open_bank_ns = pass_open_bank_ns_lcl;
output wire pass_open_bank_r;
assign pass_open_bank_r = pass_open_bank_r_lcl;
`ifdef MC_SVA
pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns));
pass_open_bank_killed_by_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && ~wait_for_maint_r_lcl));
pass_open_bank_following_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && wait_for_maint_r_lcl));
`endif
// Should the column command be sent with the auto precharge bit set? This
// will happen when it is detected that next request is to a different row,
// or the next reqest is the next request is refresh to this rank.
reg auto_pre_r_lcl;
reg auto_pre_ns;
input allow_auto_pre;
always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl
or clear_req or maint_hit_this_bm or rb_hit_busy_r
or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin
auto_pre_ns = auto_pre_r_lcl;
if (clear_req) auto_pre_ns = 1'b0;
else
if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r &&
(~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl)))
auto_pre_ns = 1'b1;
end
always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns;
output wire auto_pre_r;
assign auto_pre_r = auto_pre_r_lcl;
`ifdef MC_SVA
auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns));
maint_triggers_auto_precharge: cover property (@(posedge clk)
(~rst && auto_pre_ns && ~auto_pre_r && row_hit_r));
`endif
// Determine when the current request is finished.
input sending_col;
input req_wr_r;
input rd_wr_r;
wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r);
input bank_wait_in_progress;
input precharge_bm_end;
reg pre_bm_end_r;
wire pre_bm_end_ns = precharge_bm_end ||
(bank_wait_in_progress && pass_open_bank_ns_lcl);
always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns;
assign bm_end_lcl =
pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
output wire bm_end;
assign bm_end = bm_end_lcl;
// Determine that the open bank should be passed to the successor bank machine.
reg pre_passing_open_bank_r;
wire pre_passing_open_bank_ns =
bank_wait_in_progress && pass_open_bank_ns_lcl;
always @(posedge clk) pre_passing_open_bank_r <= #TCQ
pre_passing_open_bank_ns;
output wire passing_open_bank;
assign passing_open_bank =
pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
reg ordered_ns;
wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") &&
req_wr_r)) && accept_this_bm;
wire ordered_issued_lcl =
sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) &&
((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r));
output wire ordered_issued;
assign ordered_issued = ordered_issued_lcl;
reg ordered_r_lcl;
always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst
or set_order_q) begin
if (rst) ordered_ns = 1'b0;
else begin
ordered_ns = ordered_r_lcl;
// Should never see accept_this_bm and adv_order_q at the same time.
if (set_order_q) ordered_ns = 1'b1;
if (ordered_issued_lcl) ordered_ns = 1'b0;
end
end
always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns;
output wire ordered_r;
assign ordered_r = ordered_r_lcl;
// Figure out when to advance the ordering queue.
input adv_order_q;
input [BM_CNT_WIDTH-1:0] order_cnt;
reg [BM_CNT_WIDTH-1:0] order_q_r;
reg [BM_CNT_WIDTH-1:0] order_q_ns;
always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst
or set_order_q) begin
order_q_ns = order_q_r;
if (rst) order_q_ns = BM_CNT_ZERO;
if (set_order_q)
if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE;
else order_q_ns = order_cnt;
if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE;
end
always @(posedge clk) order_q_r <= #TCQ order_q_ns;
output wire order_q_zero;
assign order_q_zero = ~|order_q_r ||
(adv_order_q && (order_q_r == BM_CNT_ONE)) ||
((ORDERING == "NORM") && rd_wr_r);
// Keep track of which other bank machine are ahead of this one in a
// rank-bank queue. This is necessary to know when to advance this bank
// machine in the queue, and when to update bank state machine counter upon
// passing a bank.
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;
reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}};
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;
output reg rcv_open_bank = 1'b0;
generate
if (nBANK_MACHS > 1) begin : rb_hit_busies
// The clear_vector resets bits in the rb_hit_busies vector as bank machines
// completes requests. rst also resets all the bits.
wire [nBANK_MACHS-2:0] clear_vector =
({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]);
// As this bank machine takes on a new request, capture the vector of
// which other bank machines are in the same queue.
wire [`BM_SHARED_BV] rb_hit_busies_ns =
~clear_vector &
(idle_ns_lcl
? rb_hit_busy_ns_in[`BM_SHARED_BV]
: rb_hit_busies_r_lcl[`BM_SHARED_BV]);
always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <=
#TCQ rb_hit_busies_ns;
// Compute when to advance this queue entry based on seeing other bank machines
// in the same queue finish.
always @(bm_end_in or rb_hit_busies_r_lcl)
adv_queue =
|(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]);
// Decide when to receive an open bank based on knowing this bank machine is
// one entry from the head, and a passing_open_bank hits on the
// rb_hit_busies vector.
always @(idle_r_lcl
or passing_open_bank_in or q_entry_r
or rb_hit_busies_r_lcl) rcv_open_bank =
|(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV])
&& (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl;
end
endgenerate
output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r;
assign rb_hit_busies_r = rb_hit_busies_r_lcl;
// Keep track if the queue this entry is in has priority content.
input was_wr;
input maint_req_r;
reg q_has_rd_r;
wire q_has_rd_ns = ~clear_req &&
(q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) ||
(maint_req_r && maint_hit && ~idle_r_lcl));
always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns;
output wire q_has_rd;
assign q_has_rd = q_has_rd_r;
input was_priority;
reg q_has_priority_r;
wire q_has_priority_ns = ~clear_req &&
(q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority));
always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns;
output wire q_has_priority;
assign q_has_priority = q_has_priority_r;
// Figure out if this entry should wait for maintenance to end.
wire wait_for_maint_ns = ~rst && ~maint_idle &&
(wait_for_maint_r_lcl || (maint_hit && accept_this_bm));
always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns;
output wire wait_for_maint_r;
assign wait_for_maint_r = wait_for_maint_r_lcl;
endmodule // bank_queue
|
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// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_queue.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Bank machine queue controller.
//
// Bank machines are always associated with a queue. When the system is
// idle, all bank machines are in the idle queue. As requests are
// received, the bank machine at the head of the idle queue accepts
// the request, removes itself from the idle queue and places itself
// in a queue associated with the rank-bank of the new request.
//
// If the new request is to an idle rank-bank, a new queue is created
// for that rank-bank. If the rank-bank is not idle, then the new
// request is added to the end of the existing rank-bank queue.
//
// When the head of the idle queue accepts a new request, all other
// bank machines move down one in the idle queue. When the idle queue
// is empty, the memory interface deasserts its accept signal.
//
// When new requests are received, the first step is to classify them
// as to whether the request targets an already open rank-bank, and if
// so, does the new request also hit on the already open page? As mentioned
// above, a new request places itself in the existing queue for a
// rank-bank hit. If it is also detected that the last entry in the
// existing rank-bank queue has the same page, then the current tail
// sets a bit telling itself to pass the open row when the column
// command is issued. The "passee" knows its in the head minus one
// position and hence takes control of the rank-bank.
//
// Requests are retired out of order to optimize DRAM array resources.
// However it is required that the user cannot "observe" this out of
// order processing as a data corruption. An ordering queue is
// used to enforce some ordering rules. As controlled by a paramter,
// there can be no ordering (RELAXED), ordering of writes only (NORM), and
// strict (STRICT) ordering whereby input request ordering is
// strictly adhered to.
//
// Note that ordering applies only to column commands. Row commands
// such as activate and precharge are allowed to proceed in any order
// with the proviso that within a rank-bank row commands are processed in
// the request order.
//
// When a bank machine accepts a new request, it looks at the ordering
// mode. If no ordering, nothing is done. If strict ordering, then
// it always places itself at the end of the ordering queue. If "normal"
// or write ordering, the row machine places itself in the ordering
// queue only if the new request is a write. The bank state machine
// looks at the ordering queue, and will only issue a column
// command when it sees itself at the head of the ordering queue.
//
// When a bank machine has completed its request, it must re-enter the
// idle queue. This is done by setting the idle_r bit, and setting q_entry_r
// to the idle count.
//
// There are several situations where more than one bank machine
// will enter the idle queue simultaneously. If two or more
// simply use the idle count to place themselves in the idle queue, multiple
// bank machines will end up at the same location in the idle queue, which
// is illegal.
//
// Based on the bank machine instance numbers, a count is made of
// the number of bank machines entering idle "below" this instance. This
// number is added to the idle count to compute the location in
// idle queue.
//
// There is also a single bit computed that says there were bank machines
// entering the idle queue "above" this instance. This is used to
// compute the tail bit.
//
// The word "queue" is used frequently to describe the behavior of the
// bank_queue block. In reality, there are no queues in the ordinary sense.
// As instantiated in this block, each bank machine has a q_entry_r number.
// This number represents the position of the bank machine in its current
// queue. At any given time, a bank machine may be in the idle queue,
// one of the dynamic rank-bank queues, or a single entry manitenance queue.
// A complete description of which queue a bank machine is currently in is
// given by idle_r, its rank-bank, mainteance status and its q_entry_r number.
//
// DRAM refresh and ZQ have a private single entry queue/channel. However,
// when a refresh request is made, it must be injected into the main queue
// properly. At the time of injection, the refresh rank is compared against
// all entryies in the queue. For those that match, if timing allows, and
// they are the tail of the rank-bank queue, then the auto_pre bit is set.
// Otherwise precharge is in progress. This results in a fully precharged
// rank.
//
// At the time of injection, the refresh channel builds a bit
// vector of queue entries that hit on the refresh rank. Once all
// of these entries finish, the refresh is forced in at the row arbiter.
//
// New requests that come after the refresh request will notice that
// a refresh is in progress for their rank and wait for the refresh
// to finish before attempting to arbitrate to send an activate.
//
// Injection of a refresh sets the q_has_rd bit for all queues hitting
// on the refresh rank. This insures a starved write request will not
// indefinitely hold off a refresh.
//
// Periodic reads are required to compare themselves against requests
// that are in progress. Adding a unique compare channel for this
// is not worthwhile. Periodic read requests inhibit the accept
// signal and override any new request that might be trying to
// enter the queue.
//
// Once a periodic read has entered the queue it is nearly indistinguishable
// from a normal read request. The req_periodic_rd_r bit is set for
// queue entry. This signal is used to inhibit the rd_data_en signal.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v1_9_bank_queue #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter nBANK_MACHS = 4,
parameter ORDERING = "NORM",
parameter ID = 0
)
(/*AUTOARG*/
// Outputs
head_r, tail_r, idle_ns, idle_r, pass_open_bank_ns,
pass_open_bank_r, auto_pre_r, bm_end, passing_open_bank,
ordered_issued, ordered_r, order_q_zero, rcv_open_bank,
rb_hit_busies_r, q_has_rd, q_has_priority, wait_for_maint_r,
// Inputs
clk, rst, accept_internal_r, use_addr, periodic_rd_ack_r, bm_end_in,
idle_cnt, rb_hit_busy_cnt, accept_req, rb_hit_busy_r, maint_idle,
maint_hit, row_hit_r, pre_wait_r, allow_auto_pre, sending_col,
bank_wait_in_progress, precharge_bm_end, req_wr_r, rd_wr_r,
adv_order_q, order_cnt, rb_hit_busy_ns_in, passing_open_bank_in,
was_wr, maint_req_r, was_priority
);
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
// Decide if this bank machine should accept a new request.
reg idle_r_lcl;
reg head_r_lcl;
input accept_internal_r;
wire bm_ready = idle_r_lcl && head_r_lcl && accept_internal_r;
// Accept request in this bank machine. Could be maintenance or
// regular request.
input use_addr;
input periodic_rd_ack_r;
wire accept_this_bm = bm_ready && (use_addr || periodic_rd_ack_r);
// Multiple machines may enter the idle queue in a single state.
// Based on bank machine instance number, compute how many
// bank machines with lower instance numbers are entering
// the idle queue.
input [(nBANK_MACHS*2)-1:0] bm_end_in;
reg [BM_CNT_WIDTH-1:0] idlers_below;
integer i;
always @(/*AS*/bm_end_in) begin
idlers_below = BM_CNT_ZERO;
for (i=0; i<ID; i=i+1)
idlers_below = idlers_below + bm_end_in[i];
end
reg idlers_above;
always @(/*AS*/bm_end_in) begin
idlers_above = 1'b0;
for (i=ID+1; i<ID+nBANK_MACHS; i=i+1)
idlers_above = idlers_above || bm_end_in[i];
end
`ifdef MC_SVA
bm_end_and_idlers_above: cover property (@(posedge clk)
(~rst && bm_end && idlers_above));
bm_end_and_idlers_below: cover property (@(posedge clk)
(~rst && bm_end && |idlers_below));
`endif
// Compute the q_entry number.
input [BM_CNT_WIDTH-1:0] idle_cnt;
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
input accept_req;
wire bm_end_lcl;
reg adv_queue = 1'b0;
reg [BM_CNT_WIDTH-1:0] q_entry_r;
reg [BM_CNT_WIDTH-1:0] q_entry_ns;
wire [BM_CNT_WIDTH-1:0] temp;
// always @(/*AS*/accept_req or accept_this_bm or adv_queue
// or bm_end_lcl or idle_cnt or idle_r_lcl or idlers_below
// or q_entry_r or rb_hit_busy_cnt /*or rst*/) begin
//// if (rst) q_entry_ns = ID[BM_CNT_WIDTH-1:0];
//// else begin
// q_entry_ns = q_entry_r;
// if ((~idle_r_lcl && adv_queue) ||
// (idle_r_lcl && accept_req && ~accept_this_bm))
// q_entry_ns = q_entry_r - BM_CNT_ONE;
// if (accept_this_bm)
//// q_entry_ns = rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO);
// q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
// if (bm_end_lcl) begin
// q_entry_ns = idle_cnt + idlers_below;
// if (accept_req) q_entry_ns = q_entry_ns - BM_CNT_ONE;
//// end
// end
// end
assign temp = idle_cnt + idlers_below;
always @ (*)
begin
if (accept_req & bm_end_lcl)
q_entry_ns = temp - BM_CNT_ONE;
else if (bm_end_lcl)
q_entry_ns = temp;
else if (accept_this_bm)
q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
else if ((!idle_r_lcl & adv_queue) |
(idle_r_lcl & accept_req & !accept_this_bm))
q_entry_ns = q_entry_r - BM_CNT_ONE;
else
q_entry_ns = q_entry_r;
end
always @(posedge clk)
if (rst)
q_entry_r <= #TCQ ID[BM_CNT_WIDTH-1:0];
else
q_entry_r <= #TCQ q_entry_ns;
// Determine if this entry is the head of its queue.
reg head_ns;
always @(/*AS*/accept_req or accept_this_bm or adv_queue
or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl
or idlers_below or q_entry_r or rb_hit_busy_cnt or rst) begin
if (rst) head_ns = ~|ID[BM_CNT_WIDTH-1:0];
else begin
head_ns = head_r_lcl;
if (accept_this_bm)
head_ns = ~|(rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO));
if ((~idle_r_lcl && adv_queue) ||
(idle_r_lcl && accept_req && ~accept_this_bm))
head_ns = ~|(q_entry_r - BM_CNT_ONE);
if (bm_end_lcl) begin
head_ns = ~|(idle_cnt - (accept_req ? BM_CNT_ONE : BM_CNT_ZERO)) &&
~|idlers_below;
end
end
end
always @(posedge clk) head_r_lcl <= #TCQ head_ns;
output wire head_r;
assign head_r = head_r_lcl;
// Determine if this entry is the tail of its queue. Note that
// an entry can be both head and tail.
input rb_hit_busy_r;
reg tail_r_lcl = 1'b1;
generate
if (nBANK_MACHS > 1) begin : compute_tail
reg tail_ns;
always @(accept_req or accept_this_bm
or bm_end_in or bm_end_lcl or idle_r_lcl
or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin
if (rst) tail_ns = (ID == nBANK_MACHS);
// The order of the statements below is important in the case where
// another bank machine is retiring and this bank machine is accepting.
else begin
tail_ns = tail_r_lcl;
if ((accept_req && rb_hit_busy_r) ||
(|bm_end_in[`BM_SHARED_BV] && idle_r_lcl))
tail_ns = 1'b0;
if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1;
end
end
always @(posedge clk) tail_r_lcl <= #TCQ tail_ns;
end // if (nBANK_MACHS > 1)
endgenerate
output wire tail_r;
assign tail_r = tail_r_lcl;
wire clear_req = bm_end_lcl || rst;
// Is this entry in the idle queue?
reg idle_ns_lcl;
always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin
idle_ns_lcl = idle_r_lcl;
if (accept_this_bm) idle_ns_lcl = 1'b0;
if (clear_req) idle_ns_lcl = 1'b1;
end
always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl;
output wire idle_ns;
assign idle_ns = idle_ns_lcl;
output wire idle_r;
assign idle_r = idle_r_lcl;
// Maintenance hitting on this active bank machine is in progress.
input maint_idle;
input maint_hit;
wire maint_hit_this_bm = ~maint_idle && maint_hit;
// Does new request hit on this bank machine while it is able to pass the
// open bank?
input row_hit_r;
input pre_wait_r;
wire pass_open_bank_eligible =
tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r;
// Set pass open bank bit, but not if request preceded active maintenance.
reg wait_for_maint_r_lcl;
reg pass_open_bank_r_lcl;
wire pass_open_bank_ns_lcl = ~clear_req &&
(pass_open_bank_r_lcl ||
(accept_req && pass_open_bank_eligible &&
(~maint_hit_this_bm || wait_for_maint_r_lcl)));
always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl;
output wire pass_open_bank_ns;
assign pass_open_bank_ns = pass_open_bank_ns_lcl;
output wire pass_open_bank_r;
assign pass_open_bank_r = pass_open_bank_r_lcl;
`ifdef MC_SVA
pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns));
pass_open_bank_killed_by_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && ~wait_for_maint_r_lcl));
pass_open_bank_following_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && wait_for_maint_r_lcl));
`endif
// Should the column command be sent with the auto precharge bit set? This
// will happen when it is detected that next request is to a different row,
// or the next reqest is the next request is refresh to this rank.
reg auto_pre_r_lcl;
reg auto_pre_ns;
input allow_auto_pre;
always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl
or clear_req or maint_hit_this_bm or rb_hit_busy_r
or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin
auto_pre_ns = auto_pre_r_lcl;
if (clear_req) auto_pre_ns = 1'b0;
else
if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r &&
(~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl)))
auto_pre_ns = 1'b1;
end
always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns;
output wire auto_pre_r;
assign auto_pre_r = auto_pre_r_lcl;
`ifdef MC_SVA
auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns));
maint_triggers_auto_precharge: cover property (@(posedge clk)
(~rst && auto_pre_ns && ~auto_pre_r && row_hit_r));
`endif
// Determine when the current request is finished.
input sending_col;
input req_wr_r;
input rd_wr_r;
wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r);
input bank_wait_in_progress;
input precharge_bm_end;
reg pre_bm_end_r;
wire pre_bm_end_ns = precharge_bm_end ||
(bank_wait_in_progress && pass_open_bank_ns_lcl);
always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns;
assign bm_end_lcl =
pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
output wire bm_end;
assign bm_end = bm_end_lcl;
// Determine that the open bank should be passed to the successor bank machine.
reg pre_passing_open_bank_r;
wire pre_passing_open_bank_ns =
bank_wait_in_progress && pass_open_bank_ns_lcl;
always @(posedge clk) pre_passing_open_bank_r <= #TCQ
pre_passing_open_bank_ns;
output wire passing_open_bank;
assign passing_open_bank =
pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
reg ordered_ns;
wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") &&
req_wr_r)) && accept_this_bm;
wire ordered_issued_lcl =
sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) &&
((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r));
output wire ordered_issued;
assign ordered_issued = ordered_issued_lcl;
reg ordered_r_lcl;
always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst
or set_order_q) begin
if (rst) ordered_ns = 1'b0;
else begin
ordered_ns = ordered_r_lcl;
// Should never see accept_this_bm and adv_order_q at the same time.
if (set_order_q) ordered_ns = 1'b1;
if (ordered_issued_lcl) ordered_ns = 1'b0;
end
end
always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns;
output wire ordered_r;
assign ordered_r = ordered_r_lcl;
// Figure out when to advance the ordering queue.
input adv_order_q;
input [BM_CNT_WIDTH-1:0] order_cnt;
reg [BM_CNT_WIDTH-1:0] order_q_r;
reg [BM_CNT_WIDTH-1:0] order_q_ns;
always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst
or set_order_q) begin
order_q_ns = order_q_r;
if (rst) order_q_ns = BM_CNT_ZERO;
if (set_order_q)
if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE;
else order_q_ns = order_cnt;
if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE;
end
always @(posedge clk) order_q_r <= #TCQ order_q_ns;
output wire order_q_zero;
assign order_q_zero = ~|order_q_r ||
(adv_order_q && (order_q_r == BM_CNT_ONE)) ||
((ORDERING == "NORM") && rd_wr_r);
// Keep track of which other bank machine are ahead of this one in a
// rank-bank queue. This is necessary to know when to advance this bank
// machine in the queue, and when to update bank state machine counter upon
// passing a bank.
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;
reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}};
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;
output reg rcv_open_bank = 1'b0;
generate
if (nBANK_MACHS > 1) begin : rb_hit_busies
// The clear_vector resets bits in the rb_hit_busies vector as bank machines
// completes requests. rst also resets all the bits.
wire [nBANK_MACHS-2:0] clear_vector =
({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]);
// As this bank machine takes on a new request, capture the vector of
// which other bank machines are in the same queue.
wire [`BM_SHARED_BV] rb_hit_busies_ns =
~clear_vector &
(idle_ns_lcl
? rb_hit_busy_ns_in[`BM_SHARED_BV]
: rb_hit_busies_r_lcl[`BM_SHARED_BV]);
always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <=
#TCQ rb_hit_busies_ns;
// Compute when to advance this queue entry based on seeing other bank machines
// in the same queue finish.
always @(bm_end_in or rb_hit_busies_r_lcl)
adv_queue =
|(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]);
// Decide when to receive an open bank based on knowing this bank machine is
// one entry from the head, and a passing_open_bank hits on the
// rb_hit_busies vector.
always @(idle_r_lcl
or passing_open_bank_in or q_entry_r
or rb_hit_busies_r_lcl) rcv_open_bank =
|(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV])
&& (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl;
end
endgenerate
output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r;
assign rb_hit_busies_r = rb_hit_busies_r_lcl;
// Keep track if the queue this entry is in has priority content.
input was_wr;
input maint_req_r;
reg q_has_rd_r;
wire q_has_rd_ns = ~clear_req &&
(q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) ||
(maint_req_r && maint_hit && ~idle_r_lcl));
always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns;
output wire q_has_rd;
assign q_has_rd = q_has_rd_r;
input was_priority;
reg q_has_priority_r;
wire q_has_priority_ns = ~clear_req &&
(q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority));
always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns;
output wire q_has_priority;
assign q_has_priority = q_has_priority_r;
// Figure out if this entry should wait for maintenance to end.
wire wait_for_maint_ns = ~rst && ~maint_idle &&
(wait_for_maint_r_lcl || (maint_hit && accept_this_bm));
always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns;
output wire wait_for_maint_r;
assign wait_for_maint_r = wait_for_maint_r_lcl;
endmodule // bank_queue
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sync_fifo.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A synchronous capable parameterized FIFO. As with all
// traditional FIFOs, the RD_DATA will be valid one cycle following a RD_EN
// assertion. EMPTY will remain low until the cycle following the last RD_EN
// assertion. Note, that EMPTY may actually be high on the same cycle that
// RD_DATA contains valid data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module sync_fifo #(
parameter C_WIDTH = 32, // Data bus width
parameter C_DEPTH = 1024, // Depth of the FIFO
parameter C_PROVIDE_COUNT = 0, // Include code for counts
// Local parameters
parameter C_REAL_DEPTH = 2**clog2(C_DEPTH),
parameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH),
parameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH+1)
)
(
input CLK, // Clock
input RST, // Sync reset, active high
input [C_WIDTH-1:0] WR_DATA, // Write data input
input WR_EN, // Write enable, high active
output [C_WIDTH-1:0] RD_DATA, // Read data output
input RD_EN, // Read enable, high active
output FULL, // Full condition
output EMPTY, // Empty condition
output [C_DEPTH_P1_BITS-1:0] COUNT // Data count
);
`include "functions.vh"
reg [C_DEPTH_BITS:0] rWrPtr=0, _rWrPtr=0;
reg [C_DEPTH_BITS:0] rWrPtrPlus1=1, _rWrPtrPlus1=1;
reg [C_DEPTH_BITS:0] rRdPtr=0, _rRdPtr=0;
reg [C_DEPTH_BITS:0] rRdPtrPlus1=1, _rRdPtrPlus1=1;
reg rFull=0, _rFull=0;
reg rEmpty=1, _rEmpty=1;
// Memory block (synthesis attributes applied to this module will
// determine the memory option).
ram_1clk_1w_1r #(.C_RAM_WIDTH(C_WIDTH), .C_RAM_DEPTH(C_REAL_DEPTH)) mem (
.CLK(CLK),
.ADDRA(rWrPtr[C_DEPTH_BITS-1:0]),
.WEA(WR_EN & !rFull),
.DINA(WR_DATA),
.ADDRB(rRdPtr[C_DEPTH_BITS-1:0]),
.DOUTB(RD_DATA)
);
// Write pointer logic.
always @ (posedge CLK) begin
if (RST) begin
rWrPtr <= #1 0;
rWrPtrPlus1 <= #1 1;
end
else begin
rWrPtr <= #1 _rWrPtr;
rWrPtrPlus1 <= #1 _rWrPtrPlus1;
end
end
always @ (*) begin
if (WR_EN & !rFull) begin
_rWrPtr = rWrPtrPlus1;
_rWrPtrPlus1 = rWrPtrPlus1 + 1'd1;
end
else begin
_rWrPtr = rWrPtr;
_rWrPtrPlus1 = rWrPtrPlus1;
end
end
// Read pointer logic.
always @ (posedge CLK) begin
if (RST) begin
rRdPtr <= #1 0;
rRdPtrPlus1 <= #1 1;
end
else begin
rRdPtr <= #1 _rRdPtr;
rRdPtrPlus1 <= #1 _rRdPtrPlus1;
end
end
always @ (*) begin
if (RD_EN & !rEmpty) begin
_rRdPtr = rRdPtrPlus1;
_rRdPtrPlus1 = rRdPtrPlus1 + 1'd1;
end
else begin
_rRdPtr = rRdPtr;
_rRdPtrPlus1 = rRdPtrPlus1;
end
end
// Calculate empty
assign EMPTY = rEmpty;
always @ (posedge CLK) begin
rEmpty <= #1 (RST ? 1'd1 : _rEmpty);
end
always @ (*) begin
_rEmpty = (rWrPtr == rRdPtr) || (RD_EN && !rEmpty && (rWrPtr == rRdPtrPlus1));
end
// Calculate full
assign FULL = rFull;
always @ (posedge CLK) begin
rFull <= #1 (RST ? 1'd0 : _rFull);
end
always @ (*) begin
_rFull = ((rWrPtr[C_DEPTH_BITS-1:0] == rRdPtr[C_DEPTH_BITS-1:0]) && (rWrPtr[C_DEPTH_BITS] != rRdPtr[C_DEPTH_BITS])) ||
(WR_EN && (rWrPtrPlus1[C_DEPTH_BITS-1:0] == rRdPtr[C_DEPTH_BITS-1:0]) && (rWrPtrPlus1[C_DEPTH_BITS] != rRdPtr[C_DEPTH_BITS]));
end
generate
if (C_PROVIDE_COUNT) begin: provide_count
reg [C_DEPTH_BITS:0] rCount=0, _rCount=0;
assign COUNT = (rFull ? C_REAL_DEPTH[C_DEPTH_P1_BITS-1:0] : rCount);
// Calculate read count
always @ (posedge CLK) begin
if (RST)
rCount <= #1 0;
else
rCount <= #1 _rCount;
end
always @ (*) begin
_rCount = (rWrPtr - rRdPtr);
end
end
else begin: provide_no_count
assign COUNT = 0;
end
endgenerate
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sync_fifo.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A synchronous capable parameterized FIFO. As with all
// traditional FIFOs, the RD_DATA will be valid one cycle following a RD_EN
// assertion. EMPTY will remain low until the cycle following the last RD_EN
// assertion. Note, that EMPTY may actually be high on the same cycle that
// RD_DATA contains valid data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module sync_fifo #(
parameter C_WIDTH = 32, // Data bus width
parameter C_DEPTH = 1024, // Depth of the FIFO
parameter C_PROVIDE_COUNT = 0, // Include code for counts
// Local parameters
parameter C_REAL_DEPTH = 2**clog2(C_DEPTH),
parameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH),
parameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH+1)
)
(
input CLK, // Clock
input RST, // Sync reset, active high
input [C_WIDTH-1:0] WR_DATA, // Write data input
input WR_EN, // Write enable, high active
output [C_WIDTH-1:0] RD_DATA, // Read data output
input RD_EN, // Read enable, high active
output FULL, // Full condition
output EMPTY, // Empty condition
output [C_DEPTH_P1_BITS-1:0] COUNT // Data count
);
`include "functions.vh"
reg [C_DEPTH_BITS:0] rWrPtr=0, _rWrPtr=0;
reg [C_DEPTH_BITS:0] rWrPtrPlus1=1, _rWrPtrPlus1=1;
reg [C_DEPTH_BITS:0] rRdPtr=0, _rRdPtr=0;
reg [C_DEPTH_BITS:0] rRdPtrPlus1=1, _rRdPtrPlus1=1;
reg rFull=0, _rFull=0;
reg rEmpty=1, _rEmpty=1;
// Memory block (synthesis attributes applied to this module will
// determine the memory option).
ram_1clk_1w_1r #(.C_RAM_WIDTH(C_WIDTH), .C_RAM_DEPTH(C_REAL_DEPTH)) mem (
.CLK(CLK),
.ADDRA(rWrPtr[C_DEPTH_BITS-1:0]),
.WEA(WR_EN & !rFull),
.DINA(WR_DATA),
.ADDRB(rRdPtr[C_DEPTH_BITS-1:0]),
.DOUTB(RD_DATA)
);
// Write pointer logic.
always @ (posedge CLK) begin
if (RST) begin
rWrPtr <= #1 0;
rWrPtrPlus1 <= #1 1;
end
else begin
rWrPtr <= #1 _rWrPtr;
rWrPtrPlus1 <= #1 _rWrPtrPlus1;
end
end
always @ (*) begin
if (WR_EN & !rFull) begin
_rWrPtr = rWrPtrPlus1;
_rWrPtrPlus1 = rWrPtrPlus1 + 1'd1;
end
else begin
_rWrPtr = rWrPtr;
_rWrPtrPlus1 = rWrPtrPlus1;
end
end
// Read pointer logic.
always @ (posedge CLK) begin
if (RST) begin
rRdPtr <= #1 0;
rRdPtrPlus1 <= #1 1;
end
else begin
rRdPtr <= #1 _rRdPtr;
rRdPtrPlus1 <= #1 _rRdPtrPlus1;
end
end
always @ (*) begin
if (RD_EN & !rEmpty) begin
_rRdPtr = rRdPtrPlus1;
_rRdPtrPlus1 = rRdPtrPlus1 + 1'd1;
end
else begin
_rRdPtr = rRdPtr;
_rRdPtrPlus1 = rRdPtrPlus1;
end
end
// Calculate empty
assign EMPTY = rEmpty;
always @ (posedge CLK) begin
rEmpty <= #1 (RST ? 1'd1 : _rEmpty);
end
always @ (*) begin
_rEmpty = (rWrPtr == rRdPtr) || (RD_EN && !rEmpty && (rWrPtr == rRdPtrPlus1));
end
// Calculate full
assign FULL = rFull;
always @ (posedge CLK) begin
rFull <= #1 (RST ? 1'd0 : _rFull);
end
always @ (*) begin
_rFull = ((rWrPtr[C_DEPTH_BITS-1:0] == rRdPtr[C_DEPTH_BITS-1:0]) && (rWrPtr[C_DEPTH_BITS] != rRdPtr[C_DEPTH_BITS])) ||
(WR_EN && (rWrPtrPlus1[C_DEPTH_BITS-1:0] == rRdPtr[C_DEPTH_BITS-1:0]) && (rWrPtrPlus1[C_DEPTH_BITS] != rRdPtr[C_DEPTH_BITS]));
end
generate
if (C_PROVIDE_COUNT) begin: provide_count
reg [C_DEPTH_BITS:0] rCount=0, _rCount=0;
assign COUNT = (rFull ? C_REAL_DEPTH[C_DEPTH_P1_BITS-1:0] : rCount);
// Calculate read count
always @ (posedge CLK) begin
if (RST)
rCount <= #1 0;
else
rCount <= #1 _rCount;
end
always @ (*) begin
_rCount = (rWrPtr - rRdPtr);
end
end
else begin: provide_no_count
assign COUNT = 0;
end
endgenerate
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_buffer_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Wraps a FIFO for saving channel data and provides a
// registered read output. Data is available 3 cycles after RD_EN is asserted
// (not 1, like a traditional FIFO).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_buffer_32 #(
parameter C_FIFO_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input RST,
input CLK,
input [C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
input WR_EN, // Input data write enable
output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Input data FIFO is full
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // Output data
input RD_EN // Output data read enable
);
`include "functions.vh"
reg rFifoRdEn=0, _rFifoRdEn=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
wire [C_FIFO_DATA_WIDTH-1:0] wFifoData;
assign RD_DATA = rFifoData;
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
end
always @ (*) begin
_rFifoRdEn = RD_EN;
end
// FIFO for storing data from the channel.
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
.CLK(CLK),
.RST(RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.FULL(),
.COUNT(WR_COUNT),
.RD_EN(rFifoRdEn),
.RD_DATA(wFifoData),
.EMPTY()
);
// Buffer data from the FIFO.
always @ (posedge CLK) begin
rFifoData <= #1 _rFifoData;
end
always @ (*) begin
_rFifoData = wFifoData;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_buffer_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Wraps a FIFO for saving channel data and provides a
// registered read output. Data is available 3 cycles after RD_EN is asserted
// (not 1, like a traditional FIFO).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_buffer_32 #(
parameter C_FIFO_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input RST,
input CLK,
input [C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
input WR_EN, // Input data write enable
output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Input data FIFO is full
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // Output data
input RD_EN // Output data read enable
);
`include "functions.vh"
reg rFifoRdEn=0, _rFifoRdEn=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
wire [C_FIFO_DATA_WIDTH-1:0] wFifoData;
assign RD_DATA = rFifoData;
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
end
always @ (*) begin
_rFifoRdEn = RD_EN;
end
// FIFO for storing data from the channel.
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
.CLK(CLK),
.RST(RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.FULL(),
.COUNT(WR_COUNT),
.RD_EN(rFifoRdEn),
.RD_DATA(wFifoData),
.EMPTY()
);
// Buffer data from the FIFO.
always @ (posedge CLK) begin
rFifoData <= #1 _rFifoData;
end
always @ (*) begin
_rFifoData = wFifoData;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_buffer_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Wraps a FIFO for saving channel data and provides a
// registered read output. Data is available 3 cycles after RD_EN is asserted
// (not 1, like a traditional FIFO).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_buffer_32 #(
parameter C_FIFO_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input RST,
input CLK,
input [C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
input WR_EN, // Input data write enable
output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Input data FIFO is full
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // Output data
input RD_EN // Output data read enable
);
`include "functions.vh"
reg rFifoRdEn=0, _rFifoRdEn=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
wire [C_FIFO_DATA_WIDTH-1:0] wFifoData;
assign RD_DATA = rFifoData;
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
end
always @ (*) begin
_rFifoRdEn = RD_EN;
end
// FIFO for storing data from the channel.
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
.CLK(CLK),
.RST(RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.FULL(),
.COUNT(WR_COUNT),
.RD_EN(rFifoRdEn),
.RD_DATA(wFifoData),
.EMPTY()
);
// Buffer data from the FIFO.
always @ (posedge CLK) begin
rFifoData <= #1 _rFifoData;
end
always @ (*) begin
_rFifoData = wFifoData;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_dqs_found_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling calibration logic
// NOTES:
// 1. Phaser_In DQSFOUND calibration
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
**$Date: 2011/06/02 08:35:08 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_dqs_found_cal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter nCL = 5, // Read CAS latency
parameter AL = "0",
parameter nCWL = 5, // Write CAS latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RANKS = 1, // # of memory ranks in the system
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
parameter N_CTL_LANES = 3, // Number of control byte lanes
parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
parameter HIGHEST_BANK = 3, // Sum of I/O Banks
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf
)
(
input clk,
input rst,
input dqsfound_retry,
// From phy_init
input pi_dqs_found_start,
input detect_pi_found_dqs,
input prech_done,
// DQSFOUND per Phaser_IN
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
// To phy_init
output [5:0] rd_data_offset_0,
output [5:0] rd_data_offset_1,
output [5:0] rd_data_offset_2,
output pi_dqs_found_rank_done,
output pi_dqs_found_done,
output reg pi_dqs_found_err,
output [6*RANKS-1:0] rd_data_offset_ranks_0,
output [6*RANKS-1:0] rd_data_offset_ranks_1,
output [6*RANKS-1:0] rd_data_offset_ranks_2,
output reg dqsfound_retry_done,
output reg dqs_found_prech_req,
//To MC
output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
input [8:0] po_counter_read_val,
output rd_data_offset_cal_done,
output fine_adjust_done,
output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
output reg ck_po_stg2_f_indec,
output reg ck_po_stg2_f_en,
output [255:0] dbg_dqs_found_cal
);
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Added to reduce simulation time
localparam LATENCY_FACTOR = 13;
localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
localparam FINE_ADJ_IDLE = 4'h0;
localparam RST_POSTWAIT = 4'h1;
localparam RST_POSTWAIT1 = 4'h2;
localparam RST_WAIT = 4'h3;
localparam FINE_ADJ_INIT = 4'h4;
localparam FINE_INC = 4'h5;
localparam FINE_INC_WAIT = 4'h6;
localparam FINE_INC_PREWAIT = 4'h7;
localparam DETECT_PREWAIT = 4'h8;
localparam DETECT_DQSFOUND = 4'h9;
localparam PRECH_WAIT = 4'hA;
localparam FINE_DEC = 4'hB;
localparam FINE_DEC_WAIT = 4'hC;
localparam FINE_DEC_PREWAIT = 4'hD;
localparam FINAL_WAIT = 4'hE;
localparam FINE_ADJ_DONE = 4'hF;
integer k,l,m,n,p,q,r,s;
reg dqs_found_start_r;
reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
reg rank_done_r;
reg rank_done_r1;
reg dqs_found_done_r;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
reg init_dqsfound_done_r;
reg init_dqsfound_done_r1;
reg init_dqsfound_done_r2;
reg init_dqsfound_done_r3;
reg init_dqsfound_done_r4;
reg init_dqsfound_done_r5;
reg [1:0] rnk_cnt_r;
reg [2:0 ] final_do_index[0:RANKS-1];
reg [5:0 ] final_do_max[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
reg [10*HIGHEST_BANK-1:0] retry_cnt;
reg dqsfound_retry_r1;
wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
// CK/Control byte lanes fine adjust stage
reg fine_adjust;
reg [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [3:0] fine_adj_state_r;
reg fine_adjust_done_r;
reg rst_dqs_find;
reg rst_dqs_find_r1;
reg rst_dqs_find_r2;
reg [5:0] init_dec_cnt;
reg [5:0] dec_cnt;
reg [5:0] inc_cnt;
reg final_dec_done;
reg init_dec_done;
reg first_fail_detect;
reg second_fail_detect;
reg [5:0] first_fail_taps;
reg [5:0] second_fail_taps;
reg [5:0] stable_pass_cnt;
reg [3:0] detect_rd_cnt;
//***************************************************************************
// Debug signals
//
//***************************************************************************
assign dbg_dqs_found_cal[5:0] = first_fail_taps;
assign dbg_dqs_found_cal[11:6] = second_fail_taps;
assign dbg_dqs_found_cal[12] = first_fail_detect;
assign dbg_dqs_found_cal[13] = second_fail_detect;
assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
assign pi_dqs_found_rank_done = rank_done_r;
assign pi_dqs_found_done = dqs_found_done_r;
generate
genvar rnk_cnt;
if (HIGHEST_BANK == 3) begin // Three Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
end
end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end else begin // Single Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end
endgenerate
// final_data_offset is used during write calibration and during
// normal operation. One rd_data_offset value per rank for entire
// interface
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
final_data_offset[rnk_cnt_r][12+:6];
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = 'd0;
end else begin
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = 'd0;
assign rd_data_offset_2 = 'd0;
end
endgenerate
assign rd_data_offset_cal_done = init_dqsfound_done_r;
assign fine_adjust_lane_cnt = ctl_lane_cnt;
//**************************************************************************
// DQSFOUND all and any generation
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
// asserted
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
// is asserted
//**************************************************************************
generate
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
end
end else if (pi_dqs_found_start) begin
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
end
end
end
always @(posedge clk) begin
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
end
//*****************************************************************************
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
// per CK/A/C tap value
//*****************************************************************************
always @(posedge clk) begin
if (rst || (detect_rd_cnt == 'd0))
detect_rd_cnt <= #TCQ NUM_READS;
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
end
//**************************************************************************
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
//
//**************************************************************************
assign fine_adjust_done = fine_adjust_done_r;
always @(posedge clk) begin
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
end
always @(posedge clk) begin
if(rst)begin
fine_adjust <= #TCQ 1'b0;
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
fine_adjust_done_r <= #TCQ 1'b0;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b0;
init_dec_cnt <= #TCQ 'd31;
dec_cnt <= #TCQ 'd0;
inc_cnt <= #TCQ 'd0;
init_dec_done <= #TCQ 1'b0;
final_dec_done <= #TCQ 1'b0;
first_fail_detect <= #TCQ 1'b0;
second_fail_detect <= #TCQ 1'b0;
first_fail_taps <= #TCQ 'd0;
second_fail_taps <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
dqs_found_prech_req<= #TCQ 1'b0;
end else begin
case (fine_adj_state_r)
FINE_ADJ_IDLE: begin
if (init_dqsfound_done_r5) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
rst_dqs_find <= #TCQ 1'b0;
end else begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
rst_dqs_find <= #TCQ 1'b1;
end
end
end
RST_WAIT: begin
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
rst_dqs_find <= #TCQ 1'b0;
if (|init_dec_cnt)
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else if (final_dec_done)
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
else
fine_adj_state_r <= #TCQ RST_POSTWAIT;
end
end
RST_POSTWAIT: begin
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
end
RST_POSTWAIT1: begin
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
end
FINE_ADJ_INIT: begin
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
fine_adj_state_r <= #TCQ FINE_INC;
end
FINE_INC: begin
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b1;
ck_po_stg2_f_en <= #TCQ 1'b1;
if (ctl_lane_cnt == N_CTL_LANES-1)
inc_cnt <= #TCQ inc_cnt + 1;
end
FINE_INC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
end
FINE_INC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_INC;
end
DETECT_PREWAIT: begin
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
else
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
DETECT_DQSFOUND: begin
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ 'd0;
if (~first_fail_detect && (inc_cnt == 'd63)) begin
// First failing tap detected at 63 taps
// then decrement to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
// First failing tap detected at greater than 30 taps
// then stop looking for second edge and decrement
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
// First failing tap detected, continue incrementing
// until either second failing tap detected or 63
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
// Consecutive 30 taps of passing region was not found
// continue incrementing
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
if (stable_pass_cnt < 'd30) begin
// Consecutive 30 taps of passing region was not found
// from tap 0 to 63 so decrement back to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else begin
// Consecutive 30 taps of passing region was found
// between first_fail_taps and 63
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end else begin
// Second failing tap detected, decrement to center of
// failing taps
second_fail_detect <= #TCQ 1'b1;
second_fail_taps <= #TCQ inc_cnt;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
fine_adj_state_r <= #TCQ FINE_DEC;
end
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else if (inc_cnt < 'd63) begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end else begin
fine_adj_state_r <= #TCQ FINE_DEC;
if (~first_fail_detect || (first_fail_taps > 'd33))
// No failing taps detected, decrement by 31
dec_cnt <= #TCQ 'd32;
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
// // First failing tap detected between 0 and 34
// // decrement midpoint between 63 and failing tap
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
else
// First failing tap detected
// decrement to midpoint between 63 and failing tap
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end
end
PRECH_WAIT: begin
if (prech_done) begin
dqs_found_prech_req <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
end
FINE_DEC: begin
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b1;
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
init_dec_cnt <= #TCQ init_dec_cnt - 1;
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
dec_cnt <= #TCQ dec_cnt - 1;
end
FINE_DEC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else begin
fine_adj_state_r <= #TCQ FINAL_WAIT;
if ((init_dec_cnt == 'd0) && ~init_dec_done)
init_dec_done <= #TCQ 1'b1;
else
final_dec_done <= #TCQ 1'b1;
end
end
end
FINE_DEC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_DEC;
end
FINAL_WAIT: begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
FINE_ADJ_DONE: begin
if (&pi_dqs_found_all_bank) begin
fine_adjust_done_r <= #TCQ 1'b1;
rst_dqs_find <= #TCQ 1'b0;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
end
end
endcase
end
end
//*****************************************************************************
always@(posedge clk)
dqs_found_start_r <= #TCQ pi_dqs_found_start;
always @(posedge clk) begin
if (rst)
rnk_cnt_r <= #TCQ 2'b00;
else if (init_dqsfound_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r;
else if (rank_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
end
//*****************************************************************
// Read data_offset calibration done signal
//*****************************************************************
always @(posedge clk) begin
if (rst || (|pi_rst_stg1_cal_r))
init_dqsfound_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank) begin
if (rnk_cnt_r == RANKS-1)
init_dqsfound_done_r <= #TCQ 1'b1;
else
init_dqsfound_done_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst ||
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
rank_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
rank_done_r <= #TCQ 1'b1;
else
rank_done_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
rank_done_r1 <= #TCQ rank_done_r;
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
end
always @(posedge clk) begin
if (rst)
dqs_found_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
(fine_adj_state_r == FINE_ADJ_DONE))
dqs_found_done_r <= #TCQ 1'b1;
else
dqs_found_done_r <= #TCQ 1'b0;
end
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[2]) ||
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[20+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[2])
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
else
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
//(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][12+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] - 1;
end
//*****************************************************************************
// Two I/O Bank Interface
//*****************************************************************************
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;
end
//*****************************************************************************
// One I/O Bank Interface
//*****************************************************************************
end else begin // One I/O Bank Interface
// Read data offset value for all DQS in Bank0
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
rd_byte_data_offset[l] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r]
<= #TCQ rd_byte_data_offset[rnk_cnt_r] - 1;
end
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted even with 3 dqfound retries
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk) begin
if (rst)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
else if (rst_dqs_find)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
else
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
end
// Final read data offset value to be used during write calibration and
// normal operation
generate
genvar i;
genvar j;
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
reg [5:0] final_do_cand [RANKS-1:0];
// combinatorially select the candidate offset for the bank
// indexed by final_do_index
if (HIGHEST_BANK == 3) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
default: final_do_cand[i] = 'd0;
endcase
end
end else if (HIGHEST_BANK == 2) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end else begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = 'd0;
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end
always @(posedge clk or posedge rst) begin
if (rst)
final_do_max[i] <= #TCQ 0;
else begin
final_do_max[i] <= #TCQ final_do_max[i]; // default
case (final_do_index[i])
3'b000: if ( | DATA_PRESENT[3:0])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b001: if ( | DATA_PRESENT[7:4])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b010: if ( | DATA_PRESENT[11:8])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
default:
final_do_max[i] <= #TCQ final_do_max[i];
endcase
end
end
always @(posedge clk)
if (rst) begin
final_do_index[i] <= #TCQ 0;
end
else begin
final_do_index[i] <= #TCQ final_do_index[i] + 1;
end
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
always @(posedge clk) begin
if (rst) begin
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
end
else begin
//if (dqsfound_retry[j])
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
//else
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
if (CWL_M % 2) // odd latency CAS slot 1
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
else // even latency CAS slot 0
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
end
end
else if (init_dqsfound_done_r5 ) begin
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
end
end
end
end
end
end
endgenerate
// Error generation in case pi_found_dqs signal from Phaser_IN
// is not asserted when a common rddata_offset value is used
always @(posedge clk) begin
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_dqs_found_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling calibration logic
// NOTES:
// 1. Phaser_In DQSFOUND calibration
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
**$Date: 2011/06/02 08:35:08 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_dqs_found_cal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter nCL = 5, // Read CAS latency
parameter AL = "0",
parameter nCWL = 5, // Write CAS latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RANKS = 1, // # of memory ranks in the system
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
parameter N_CTL_LANES = 3, // Number of control byte lanes
parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
parameter HIGHEST_BANK = 3, // Sum of I/O Banks
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf
)
(
input clk,
input rst,
input dqsfound_retry,
// From phy_init
input pi_dqs_found_start,
input detect_pi_found_dqs,
input prech_done,
// DQSFOUND per Phaser_IN
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
// To phy_init
output [5:0] rd_data_offset_0,
output [5:0] rd_data_offset_1,
output [5:0] rd_data_offset_2,
output pi_dqs_found_rank_done,
output pi_dqs_found_done,
output reg pi_dqs_found_err,
output [6*RANKS-1:0] rd_data_offset_ranks_0,
output [6*RANKS-1:0] rd_data_offset_ranks_1,
output [6*RANKS-1:0] rd_data_offset_ranks_2,
output reg dqsfound_retry_done,
output reg dqs_found_prech_req,
//To MC
output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
input [8:0] po_counter_read_val,
output rd_data_offset_cal_done,
output fine_adjust_done,
output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
output reg ck_po_stg2_f_indec,
output reg ck_po_stg2_f_en,
output [255:0] dbg_dqs_found_cal
);
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Added to reduce simulation time
localparam LATENCY_FACTOR = 13;
localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
localparam FINE_ADJ_IDLE = 4'h0;
localparam RST_POSTWAIT = 4'h1;
localparam RST_POSTWAIT1 = 4'h2;
localparam RST_WAIT = 4'h3;
localparam FINE_ADJ_INIT = 4'h4;
localparam FINE_INC = 4'h5;
localparam FINE_INC_WAIT = 4'h6;
localparam FINE_INC_PREWAIT = 4'h7;
localparam DETECT_PREWAIT = 4'h8;
localparam DETECT_DQSFOUND = 4'h9;
localparam PRECH_WAIT = 4'hA;
localparam FINE_DEC = 4'hB;
localparam FINE_DEC_WAIT = 4'hC;
localparam FINE_DEC_PREWAIT = 4'hD;
localparam FINAL_WAIT = 4'hE;
localparam FINE_ADJ_DONE = 4'hF;
integer k,l,m,n,p,q,r,s;
reg dqs_found_start_r;
reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
reg rank_done_r;
reg rank_done_r1;
reg dqs_found_done_r;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
reg init_dqsfound_done_r;
reg init_dqsfound_done_r1;
reg init_dqsfound_done_r2;
reg init_dqsfound_done_r3;
reg init_dqsfound_done_r4;
reg init_dqsfound_done_r5;
reg [1:0] rnk_cnt_r;
reg [2:0 ] final_do_index[0:RANKS-1];
reg [5:0 ] final_do_max[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
reg [10*HIGHEST_BANK-1:0] retry_cnt;
reg dqsfound_retry_r1;
wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
// CK/Control byte lanes fine adjust stage
reg fine_adjust;
reg [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [3:0] fine_adj_state_r;
reg fine_adjust_done_r;
reg rst_dqs_find;
reg rst_dqs_find_r1;
reg rst_dqs_find_r2;
reg [5:0] init_dec_cnt;
reg [5:0] dec_cnt;
reg [5:0] inc_cnt;
reg final_dec_done;
reg init_dec_done;
reg first_fail_detect;
reg second_fail_detect;
reg [5:0] first_fail_taps;
reg [5:0] second_fail_taps;
reg [5:0] stable_pass_cnt;
reg [3:0] detect_rd_cnt;
//***************************************************************************
// Debug signals
//
//***************************************************************************
assign dbg_dqs_found_cal[5:0] = first_fail_taps;
assign dbg_dqs_found_cal[11:6] = second_fail_taps;
assign dbg_dqs_found_cal[12] = first_fail_detect;
assign dbg_dqs_found_cal[13] = second_fail_detect;
assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
assign pi_dqs_found_rank_done = rank_done_r;
assign pi_dqs_found_done = dqs_found_done_r;
generate
genvar rnk_cnt;
if (HIGHEST_BANK == 3) begin // Three Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
end
end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end else begin // Single Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end
endgenerate
// final_data_offset is used during write calibration and during
// normal operation. One rd_data_offset value per rank for entire
// interface
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
final_data_offset[rnk_cnt_r][12+:6];
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = 'd0;
end else begin
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = 'd0;
assign rd_data_offset_2 = 'd0;
end
endgenerate
assign rd_data_offset_cal_done = init_dqsfound_done_r;
assign fine_adjust_lane_cnt = ctl_lane_cnt;
//**************************************************************************
// DQSFOUND all and any generation
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
// asserted
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
// is asserted
//**************************************************************************
generate
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
end
end else if (pi_dqs_found_start) begin
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
end
end
end
always @(posedge clk) begin
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
end
//*****************************************************************************
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
// per CK/A/C tap value
//*****************************************************************************
always @(posedge clk) begin
if (rst || (detect_rd_cnt == 'd0))
detect_rd_cnt <= #TCQ NUM_READS;
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
end
//**************************************************************************
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
//
//**************************************************************************
assign fine_adjust_done = fine_adjust_done_r;
always @(posedge clk) begin
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
end
always @(posedge clk) begin
if(rst)begin
fine_adjust <= #TCQ 1'b0;
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
fine_adjust_done_r <= #TCQ 1'b0;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b0;
init_dec_cnt <= #TCQ 'd31;
dec_cnt <= #TCQ 'd0;
inc_cnt <= #TCQ 'd0;
init_dec_done <= #TCQ 1'b0;
final_dec_done <= #TCQ 1'b0;
first_fail_detect <= #TCQ 1'b0;
second_fail_detect <= #TCQ 1'b0;
first_fail_taps <= #TCQ 'd0;
second_fail_taps <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
dqs_found_prech_req<= #TCQ 1'b0;
end else begin
case (fine_adj_state_r)
FINE_ADJ_IDLE: begin
if (init_dqsfound_done_r5) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
rst_dqs_find <= #TCQ 1'b0;
end else begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
rst_dqs_find <= #TCQ 1'b1;
end
end
end
RST_WAIT: begin
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
rst_dqs_find <= #TCQ 1'b0;
if (|init_dec_cnt)
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else if (final_dec_done)
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
else
fine_adj_state_r <= #TCQ RST_POSTWAIT;
end
end
RST_POSTWAIT: begin
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
end
RST_POSTWAIT1: begin
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
end
FINE_ADJ_INIT: begin
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
fine_adj_state_r <= #TCQ FINE_INC;
end
FINE_INC: begin
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b1;
ck_po_stg2_f_en <= #TCQ 1'b1;
if (ctl_lane_cnt == N_CTL_LANES-1)
inc_cnt <= #TCQ inc_cnt + 1;
end
FINE_INC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
end
FINE_INC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_INC;
end
DETECT_PREWAIT: begin
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
else
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
DETECT_DQSFOUND: begin
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ 'd0;
if (~first_fail_detect && (inc_cnt == 'd63)) begin
// First failing tap detected at 63 taps
// then decrement to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
// First failing tap detected at greater than 30 taps
// then stop looking for second edge and decrement
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
// First failing tap detected, continue incrementing
// until either second failing tap detected or 63
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
// Consecutive 30 taps of passing region was not found
// continue incrementing
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
if (stable_pass_cnt < 'd30) begin
// Consecutive 30 taps of passing region was not found
// from tap 0 to 63 so decrement back to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else begin
// Consecutive 30 taps of passing region was found
// between first_fail_taps and 63
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end else begin
// Second failing tap detected, decrement to center of
// failing taps
second_fail_detect <= #TCQ 1'b1;
second_fail_taps <= #TCQ inc_cnt;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
fine_adj_state_r <= #TCQ FINE_DEC;
end
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else if (inc_cnt < 'd63) begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end else begin
fine_adj_state_r <= #TCQ FINE_DEC;
if (~first_fail_detect || (first_fail_taps > 'd33))
// No failing taps detected, decrement by 31
dec_cnt <= #TCQ 'd32;
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
// // First failing tap detected between 0 and 34
// // decrement midpoint between 63 and failing tap
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
else
// First failing tap detected
// decrement to midpoint between 63 and failing tap
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end
end
PRECH_WAIT: begin
if (prech_done) begin
dqs_found_prech_req <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
end
FINE_DEC: begin
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b1;
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
init_dec_cnt <= #TCQ init_dec_cnt - 1;
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
dec_cnt <= #TCQ dec_cnt - 1;
end
FINE_DEC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else begin
fine_adj_state_r <= #TCQ FINAL_WAIT;
if ((init_dec_cnt == 'd0) && ~init_dec_done)
init_dec_done <= #TCQ 1'b1;
else
final_dec_done <= #TCQ 1'b1;
end
end
end
FINE_DEC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_DEC;
end
FINAL_WAIT: begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
FINE_ADJ_DONE: begin
if (&pi_dqs_found_all_bank) begin
fine_adjust_done_r <= #TCQ 1'b1;
rst_dqs_find <= #TCQ 1'b0;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
end
end
endcase
end
end
//*****************************************************************************
always@(posedge clk)
dqs_found_start_r <= #TCQ pi_dqs_found_start;
always @(posedge clk) begin
if (rst)
rnk_cnt_r <= #TCQ 2'b00;
else if (init_dqsfound_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r;
else if (rank_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
end
//*****************************************************************
// Read data_offset calibration done signal
//*****************************************************************
always @(posedge clk) begin
if (rst || (|pi_rst_stg1_cal_r))
init_dqsfound_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank) begin
if (rnk_cnt_r == RANKS-1)
init_dqsfound_done_r <= #TCQ 1'b1;
else
init_dqsfound_done_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst ||
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
rank_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
rank_done_r <= #TCQ 1'b1;
else
rank_done_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
rank_done_r1 <= #TCQ rank_done_r;
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
end
always @(posedge clk) begin
if (rst)
dqs_found_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
(fine_adj_state_r == FINE_ADJ_DONE))
dqs_found_done_r <= #TCQ 1'b1;
else
dqs_found_done_r <= #TCQ 1'b0;
end
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[2]) ||
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[20+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[2])
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
else
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
//(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][12+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] - 1;
end
//*****************************************************************************
// Two I/O Bank Interface
//*****************************************************************************
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] - 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] - 1;
end
//*****************************************************************************
// One I/O Bank Interface
//*****************************************************************************
end else begin // One I/O Bank Interface
// Read data offset value for all DQS in Bank0
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
rd_byte_data_offset[l] <= #TCQ nCL + nAL + LATENCY_FACTOR;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL - 1)))
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL + LATENCY_FACTOR;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL -1)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r]
<= #TCQ rd_byte_data_offset[rnk_cnt_r] - 1;
end
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted even with 3 dqfound retries
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk) begin
if (rst)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
else if (rst_dqs_find)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
else
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
end
// Final read data offset value to be used during write calibration and
// normal operation
generate
genvar i;
genvar j;
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
reg [5:0] final_do_cand [RANKS-1:0];
// combinatorially select the candidate offset for the bank
// indexed by final_do_index
if (HIGHEST_BANK == 3) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
default: final_do_cand[i] = 'd0;
endcase
end
end else if (HIGHEST_BANK == 2) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end else begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = 'd0;
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end
always @(posedge clk or posedge rst) begin
if (rst)
final_do_max[i] <= #TCQ 0;
else begin
final_do_max[i] <= #TCQ final_do_max[i]; // default
case (final_do_index[i])
3'b000: if ( | DATA_PRESENT[3:0])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b001: if ( | DATA_PRESENT[7:4])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b010: if ( | DATA_PRESENT[11:8])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
default:
final_do_max[i] <= #TCQ final_do_max[i];
endcase
end
end
always @(posedge clk)
if (rst) begin
final_do_index[i] <= #TCQ 0;
end
else begin
final_do_index[i] <= #TCQ final_do_index[i] + 1;
end
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
always @(posedge clk) begin
if (rst) begin
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
end
else begin
//if (dqsfound_retry[j])
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
//else
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
if (CWL_M % 2) // odd latency CAS slot 1
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
else // even latency CAS slot 0
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
end
end
else if (init_dqsfound_done_r5 ) begin
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
end
end
end
end
end
end
endgenerate
// Error generation in case pi_found_dqs signal from Phaser_IN
// is not asserted when a common rddata_offset value is used
always @(posedge clk) begin
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Allowed import return types:
// void, byte, shortint, int, longint, real, shortreal, chandle, and string
// Scalar bit and logic
//
// Allowed argument types:
// Same as above plus packed arrays
import "DPI-C" pure function bit dpii_f_bit (input bit i);
import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i);
import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i);
import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i);
import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i);
import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i);
// Illegal to return > 32 bits, so we use longint
import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i);
import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i);
import "DPI-C" pure function int dpii_f_int (input int i);
import "DPI-C" pure function byte dpii_f_byte (input byte i);
import "DPI-C" pure function shortint dpii_f_shortint (input shortint i);
import "DPI-C" pure function longint dpii_f_longint (input longint i);
import "DPI-C" pure function chandle dpii_f_chandle (input chandle i);
import "DPI-C" pure function string dpii_f_string (input string i);
import "DPI-C" pure function real dpii_f_real (input real i);
`ifndef NO_SHORTREAL
import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i);
`endif
import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o);
import "DPI-C" pure function void dpii_v_int (input int i, output int o);
import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o);
import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o);
import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o);
import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o);
import "DPI-C" pure function void dpii_v_string (input string i, output string o);
import "DPI-C" pure function void dpii_v_real (input real i, output real o);
import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o);
import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o);
import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o);
`ifndef NO_SHORTREAL
import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o);
`endif
import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o);
import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o);
import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o);
import "DPI-C" pure function int dpii_f_strlen (input string i);
import "DPI-C" function void dpii_f_void ();
// Try a task
import "DPI-C" task dpii_t_void ();
import "DPI-C" context task dpii_t_void_context ();
import "DPI-C" task dpii_t_int (input int i, output int o);
// Try non-pure, aliasing with name
import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i);
import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i);
bit i_b, o_b;
bit [7:0] i_b8;
bit [8:0] i_b9;
bit [15:0] i_b16;
bit [16:0] i_b17;
bit [31:0] i_b32;
bit [32:0] i_b33, o_b33;
bit [63:0] i_b64, o_b64;
bit [94:0] i_b95, o_b95;
bit [95:0] i_b96, o_b96;
int i_i, o_i;
byte i_y, o_y;
shortint i_s, o_s;
longint i_l, o_l;
int unsigned i_iu, o_iu;
shortint unsigned i_su, o_su;
longint unsigned i_lu, o_lu;
// verilator lint_off UNDRIVEN
chandle i_c, o_c;
string i_n, o_n;
// verilator lint_on UNDRIVEN
real i_d, o_d;
`ifndef NO_SHORTREAL
shortreal i_f, o_f;
`endif
bit [94:0] wide;
bit [6*8:1] string6;
initial begin
wide = 95'h15caff7a73c48afee4ffcb57;
i_b = 1'b1;
i_b8 = {1'b1,wide[8-2:0]};
i_b9 = {1'b1,wide[9-2:0]};
i_b16 = {1'b1,wide[16-2:0]};
i_b17 = {1'b1,wide[17-2:0]};
i_b32 = {1'b1,wide[32-2:0]};
i_b33 = {1'b1,wide[33-2:0]};
i_b64 = {1'b1,wide[64-2:0]};
i_b95 = {1'b1,wide[95-2:0]};
i_b96 = {1'b1,wide[96-2:0]};
i_i = {1'b1,wide[32-2:0]};
i_iu= {1'b1,wide[32-2:0]};
i_y = {1'b1,wide[8-2:0]};
i_s = {1'b1,wide[16-2:0]};
i_su= {1'b1,wide[16-2:0]};
i_l = {1'b1,wide[64-2:0]};
i_lu= {1'b1,wide[64-2:0]};
i_d = 32.1;
`ifndef NO_SHORTREAL
i_f = 30.2;
`endif
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop;
if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop;
if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop;
if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop;
if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop;
// These return different sizes, so we need to truncate
// verilator lint_off WIDTH
o_b33 = dpii_f_bit33 (i_b33);
o_b64 = dpii_f_bit64 (i_b64);
// verilator lint_on WIDTH
if (o_b33 !== ~i_b33) $stop;
if (o_b64 !== ~i_b64) $stop;
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_int (i_i) !== ~i_i) $stop;
if (dpii_f_byte (i_y) !== ~i_y) $stop;
if (dpii_f_shortint (i_s) !== ~i_s) $stop;
if (dpii_f_longint (i_l) !== ~i_l) $stop;
if (dpii_f_chandle (i_c) !== i_c) $stop;
if (dpii_f_string (i_n) != i_n) $stop;
if (dpii_f_real (i_d) != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
if (dpii_f_shortreal(i_f) != i_f+1.5) $stop;
`endif
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop;
dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop;
dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop;
dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop;
dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop;
dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop;
dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop;
dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop;
dpii_v_string (i_n,o_n); if (o_n != i_n) $stop;
dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop;
`endif
dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop;
dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop;
dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop;
if (dpii_f_strlen ("")!=0) $stop;
if (dpii_f_strlen ("s")!=1) $stop;
if (dpii_f_strlen ("st")!=2) $stop;
if (dpii_f_strlen ("str")!=3) $stop;
if (dpii_f_strlen ("stri")!=4) $stop;
if (dpii_f_strlen ("string_l")!=8) $stop;
if (dpii_f_strlen ("string_len")!=10) $stop;
string6 = "hello6";
`ifdef VERILATOR
string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function
`endif
if (dpii_f_strlen (string6) != 6) $stop;
dpii_f_void();
dpii_t_void();
dpii_t_void_context();
i_i = 32'h456789ab;
dpii_t_int (i_i,o_i); if (o_b !== ~i_b) $stop;
// Check alias
if (oth_f_int1(32'd123) !== ~32'd123) $stop;
if (oth_f_int2(32'd124) !== ~32'd124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
i_b <= ~i_b;
// This once mis-threw a BLKSEQ warning
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Allowed import return types:
// void, byte, shortint, int, longint, real, shortreal, chandle, and string
// Scalar bit and logic
//
// Allowed argument types:
// Same as above plus packed arrays
import "DPI-C" pure function bit dpii_f_bit (input bit i);
import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i);
import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i);
import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i);
import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i);
import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i);
// Illegal to return > 32 bits, so we use longint
import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i);
import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i);
import "DPI-C" pure function int dpii_f_int (input int i);
import "DPI-C" pure function byte dpii_f_byte (input byte i);
import "DPI-C" pure function shortint dpii_f_shortint (input shortint i);
import "DPI-C" pure function longint dpii_f_longint (input longint i);
import "DPI-C" pure function chandle dpii_f_chandle (input chandle i);
import "DPI-C" pure function string dpii_f_string (input string i);
import "DPI-C" pure function real dpii_f_real (input real i);
`ifndef NO_SHORTREAL
import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i);
`endif
import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o);
import "DPI-C" pure function void dpii_v_int (input int i, output int o);
import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o);
import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o);
import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o);
import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o);
import "DPI-C" pure function void dpii_v_string (input string i, output string o);
import "DPI-C" pure function void dpii_v_real (input real i, output real o);
import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o);
import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o);
import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o);
`ifndef NO_SHORTREAL
import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o);
`endif
import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o);
import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o);
import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o);
import "DPI-C" pure function int dpii_f_strlen (input string i);
import "DPI-C" function void dpii_f_void ();
// Try a task
import "DPI-C" task dpii_t_void ();
import "DPI-C" context task dpii_t_void_context ();
import "DPI-C" task dpii_t_int (input int i, output int o);
// Try non-pure, aliasing with name
import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i);
import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i);
bit i_b, o_b;
bit [7:0] i_b8;
bit [8:0] i_b9;
bit [15:0] i_b16;
bit [16:0] i_b17;
bit [31:0] i_b32;
bit [32:0] i_b33, o_b33;
bit [63:0] i_b64, o_b64;
bit [94:0] i_b95, o_b95;
bit [95:0] i_b96, o_b96;
int i_i, o_i;
byte i_y, o_y;
shortint i_s, o_s;
longint i_l, o_l;
int unsigned i_iu, o_iu;
shortint unsigned i_su, o_su;
longint unsigned i_lu, o_lu;
// verilator lint_off UNDRIVEN
chandle i_c, o_c;
string i_n, o_n;
// verilator lint_on UNDRIVEN
real i_d, o_d;
`ifndef NO_SHORTREAL
shortreal i_f, o_f;
`endif
bit [94:0] wide;
bit [6*8:1] string6;
initial begin
wide = 95'h15caff7a73c48afee4ffcb57;
i_b = 1'b1;
i_b8 = {1'b1,wide[8-2:0]};
i_b9 = {1'b1,wide[9-2:0]};
i_b16 = {1'b1,wide[16-2:0]};
i_b17 = {1'b1,wide[17-2:0]};
i_b32 = {1'b1,wide[32-2:0]};
i_b33 = {1'b1,wide[33-2:0]};
i_b64 = {1'b1,wide[64-2:0]};
i_b95 = {1'b1,wide[95-2:0]};
i_b96 = {1'b1,wide[96-2:0]};
i_i = {1'b1,wide[32-2:0]};
i_iu= {1'b1,wide[32-2:0]};
i_y = {1'b1,wide[8-2:0]};
i_s = {1'b1,wide[16-2:0]};
i_su= {1'b1,wide[16-2:0]};
i_l = {1'b1,wide[64-2:0]};
i_lu= {1'b1,wide[64-2:0]};
i_d = 32.1;
`ifndef NO_SHORTREAL
i_f = 30.2;
`endif
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop;
if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop;
if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop;
if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop;
if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop;
// These return different sizes, so we need to truncate
// verilator lint_off WIDTH
o_b33 = dpii_f_bit33 (i_b33);
o_b64 = dpii_f_bit64 (i_b64);
// verilator lint_on WIDTH
if (o_b33 !== ~i_b33) $stop;
if (o_b64 !== ~i_b64) $stop;
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_int (i_i) !== ~i_i) $stop;
if (dpii_f_byte (i_y) !== ~i_y) $stop;
if (dpii_f_shortint (i_s) !== ~i_s) $stop;
if (dpii_f_longint (i_l) !== ~i_l) $stop;
if (dpii_f_chandle (i_c) !== i_c) $stop;
if (dpii_f_string (i_n) != i_n) $stop;
if (dpii_f_real (i_d) != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
if (dpii_f_shortreal(i_f) != i_f+1.5) $stop;
`endif
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop;
dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop;
dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop;
dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop;
dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop;
dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop;
dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop;
dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop;
dpii_v_string (i_n,o_n); if (o_n != i_n) $stop;
dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop;
`endif
dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop;
dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop;
dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop;
if (dpii_f_strlen ("")!=0) $stop;
if (dpii_f_strlen ("s")!=1) $stop;
if (dpii_f_strlen ("st")!=2) $stop;
if (dpii_f_strlen ("str")!=3) $stop;
if (dpii_f_strlen ("stri")!=4) $stop;
if (dpii_f_strlen ("string_l")!=8) $stop;
if (dpii_f_strlen ("string_len")!=10) $stop;
string6 = "hello6";
`ifdef VERILATOR
string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function
`endif
if (dpii_f_strlen (string6) != 6) $stop;
dpii_f_void();
dpii_t_void();
dpii_t_void_context();
i_i = 32'h456789ab;
dpii_t_int (i_i,o_i); if (o_b !== ~i_b) $stop;
// Check alias
if (oth_f_int1(32'd123) !== ~32'd123) $stop;
if (oth_f_int2(32'd124) !== ~32'd124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
i_b <= ~i_b;
// This once mis-threw a BLKSEQ warning
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef int unit_type_t;
function [3:0] unit_plusone(input [3:0] i);
unit_plusone = i+1;
endfunction
package p;
typedef int package_type_t;
integer pi = 123;
function [3:0] plusone(input [3:0] i);
plusone = i+1;
endfunction
endpackage
package p2;
typedef int package2_type_t;
function [3:0] plustwo(input [3:0] i);
plustwo = i+2;
endfunction
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
unit_type_t vu;
$unit::unit_type_t vdu;
p::package_type_t vp;
t2 t2 ();
initial begin
if (unit_plusone(1) !== 2) $stop;
if ($unit::unit_plusone(1) !== 2) $stop;
if (p::plusone(1) !== 2) $stop;
p::pi = 124;
if (p::pi !== 124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
p::pi += 1;
if (p::pi < 124) $stop;
end
endmodule
module t2;
import p::*;
import p2::plustwo;
import p2::package2_type_t;
package_type_t vp;
package2_type_t vp2;
initial begin
if (plusone(1) !== 2) $stop;
if (plustwo(1) !== 3) $stop;
if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef int unit_type_t;
function [3:0] unit_plusone(input [3:0] i);
unit_plusone = i+1;
endfunction
package p;
typedef int package_type_t;
integer pi = 123;
function [3:0] plusone(input [3:0] i);
plusone = i+1;
endfunction
endpackage
package p2;
typedef int package2_type_t;
function [3:0] plustwo(input [3:0] i);
plustwo = i+2;
endfunction
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
unit_type_t vu;
$unit::unit_type_t vdu;
p::package_type_t vp;
t2 t2 ();
initial begin
if (unit_plusone(1) !== 2) $stop;
if ($unit::unit_plusone(1) !== 2) $stop;
if (p::plusone(1) !== 2) $stop;
p::pi = 124;
if (p::pi !== 124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
p::pi += 1;
if (p::pi < 124) $stop;
end
endmodule
module t2;
import p::*;
import p2::plustwo;
import p2::package2_type_t;
package_type_t vp;
package2_type_t vp2;
initial begin
if (plusone(1) !== 2) $stop;
if (plustwo(1) !== 3) $stop;
if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [19:10] bitout;
wire [29:24] short_bitout;
wire [7:0] allbits;
wire [15:0] twobits;
sub
i_sub1 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14])),
i_sub2 [3:0] (.allbits (allbits),
.twobits (twobits[7:0]),
.bitout (bitout[13:10]));
sub
i_sub3 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14]));
sub
i_sub4 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (short_bitout[27:24]));
sub
i_sub5 [7:0] (.allbits (allbits),
.twobits (twobits),
.bitout (bitout[17:10]));
sub
i_sub6 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout ({bitout[18+:2],short_bitout[28+:2]}));
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Signals under test
assign allbits = crc[7:0];
assign twobits = crc[15:0];
wire [63:0] result = {48'h0, short_bitout, bitout};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha1da9ff8082a4ff6
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule // t
module sub
( input wire [7:0] allbits,
input wire [1:0] twobits,
output wire bitout);
assign bitout = (^ twobits) ^ (^ allbits);
endmodule // sub
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [19:10] bitout;
wire [29:24] short_bitout;
wire [7:0] allbits;
wire [15:0] twobits;
sub
i_sub1 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14])),
i_sub2 [3:0] (.allbits (allbits),
.twobits (twobits[7:0]),
.bitout (bitout[13:10]));
sub
i_sub3 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14]));
sub
i_sub4 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (short_bitout[27:24]));
sub
i_sub5 [7:0] (.allbits (allbits),
.twobits (twobits),
.bitout (bitout[17:10]));
sub
i_sub6 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout ({bitout[18+:2],short_bitout[28+:2]}));
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Signals under test
assign allbits = crc[7:0];
assign twobits = crc[15:0];
wire [63:0] result = {48'h0, short_bitout, bitout};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha1da9ff8082a4ff6
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule // t
module sub
( input wire [7:0] allbits,
input wire [1:0] twobits,
output wire bitout);
assign bitout = (^ twobits) ^ (^ allbits);
endmodule // sub
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Ltac f_equiv' := repeat (repeat f_equiv; try intros ? ? ?; auto).
Module NStrongRecProp (Import N : NAxiomsRecSig').
Include NSubProp N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows defining a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0; f_equiv'.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt; f_equiv'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
f_equiv.
rewrite recursion_succ; f_equiv'.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ; f_equiv'.
rewrite strong_rec0_0. reflexivity.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
f_equiv.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Arguments strong_rec [A] a f n.
End NStrongRecProp.
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
//*****************************************************************************
// This block is responsible for managing various rank level timing
// parameters. For now, only Four Activate Window (FAW) and Write
// To Read delay are implemented here.
//
// Each rank machine generates its own inhbt_act_faw_r and inhbt_rd.
// These per rank machines are driven into the bank machines. Each
// bank machines selects the correct inhibits based on the rank
// of its current request.
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v1_9_rank_cntrl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter BURST_MODE = "8", // Burst length
parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay
parameter CL = 5, // Read CAS latency
parameter CWL = 5, // Write CAS latency
parameter ID = 0, // Unique ID for each instance
parameter nBANK_MACHS = 4, // # bank machines in MC
parameter nCK_PER_CLK = 2, // DRAM clock : MC clock
parameter nFAW = 30, // four activate window (CKs)
parameter nREFRESH_BANK = 8, // # REF commands to pull-in
parameter nRRD = 4, // ACT->ACT period (CKs)
parameter nWTR = 4, // Internal write->read
// delay (CKs)
parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor
// for periodic read timer
parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a
// single bit rank signal among
// all the bank machines
parameter RANK_WIDTH = 2, // # of bits to count ranks
parameter RANKS = 4, // # of ranks of DRAM
parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor
// for refresh timer
)
(
// Maintenance requests
output periodic_rd_request,
output wire refresh_request,
// Inhibit signals
output reg inhbt_act_faw_r,
output reg inhbt_rd,
output reg inhbt_wr,
// System Inputs
input clk,
input rst,
// User maintenance requests
input app_periodic_rd_req,
input app_ref_req,
// Inputs
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
input clear_periodic_rd_request,
input col_rd_wr,
input init_calib_complete,
input insert_maint_r1,
input maint_prescaler_tick_r,
input [RANK_WIDTH-1:0] maint_rank_r,
input maint_zq_r,
input maint_sre_r,
input maint_srx_r,
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
input refresh_tick,
input [nBANK_MACHS-1:0] sending_col,
input [nBANK_MACHS-1:0] sending_row,
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r
);
//***************************************************************************
// RRD configuration. The bank machines have a mechanism to prevent RAS to
// RAS on adjacent fabric CLK states to the same rank. When
// nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD
// when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the
// higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit
// is worked into the inhbt_faw signal.
//***************************************************************************
localparam nADD_RRD = nRRD -
(
(nCK_PER_CLK == 1) ? 2 :
(nCK_PER_CLK == 2) ? 4 :
/*(nCK_PER_CLK == 4)*/ 8
);
// divide by nCK_PER_CLK and add a cycle if there's a remainder
localparam nRRD_CLKS =
(nCK_PER_CLK == 1) ? nADD_RRD :
(nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) :
/*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0));
// take binary log to obtain counter width and add a tick for the idle cycle
localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1);
//***************************************************************************
// Internal signals
//***************************************************************************
reg act_this_rank;
integer i; // loop invariant
//***************************************************************************
// Function clogb2
// Description:
// This function performs binary logarithm and rounds up
// Inputs:
// size: integer to perform binary log upon
// Outputs:
// clogb2: result of binary logarithm, rounded up
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
// increment clogb2 from 1 for each bit in size
for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1)
size = size >> 1;
end
endfunction // clogb2
//***************************************************************************
// Determine if this rank has been activated. act_this_rank_r is a
// registered bit vector from individual bank machines indicating the
// corresponding bank machine is sending
// an activate. Timing is improved with this method.
//***************************************************************************
always @(/*AS*/act_this_rank_r or sending_row) begin
act_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
act_this_rank =
act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]);
end
reg add_rrd_inhbt = 1'b0;
generate
if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
add_rrd_ns = add_rrd_r;
if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
else
if (act_this_rank)
add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
else if (|add_rrd_r) add_rrd_ns =
add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1};
end
always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
end // add_rdd1
else if (nADD_RRD > 0) begin :add_rdd0
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
add_rrd_ns = add_rrd_r;
if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
else
if (act_this_rank)
add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
else if (|add_rrd_r) add_rrd_ns =
add_rrd_r - {1'b1};
end
always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
end // add_rdd0
endgenerate
// Compute inhbt_act_faw_r. Only allow a limited number of activates
// in a window. Both the number of activates and the window are
// configurable. This depends on the RRD mechanism to prevent
// two consecutive activates to the same rank.
//
// Subtract three from the specified nFAW. Subtract three because:
// -Zero for the delay into the SRL is really one state.
// -Sending_row is used to trigger the delay. Sending_row is one
// state delayed from the arb.
// -inhbt_act_faw_r is registered to make timing work, hence the
// generation needs to be one state early.
localparam nFAW_CLKS = (nCK_PER_CLK == 1)
? nFAW
: (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) :
((nFAW/4) + ((nFAW%4) ? 1 : 0));
generate
begin : inhbt_act_faw
wire act_delayed;
wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3;
SRLC32E #(.INIT(32'h00000000) ) SRLC32E0
(.Q(act_delayed), // SRL data output
.Q31(), // SRL cascade output pin
.A(shift_depth), // 5-bit shift depth select input
.CE(1'b1), // Clock enable input
.CLK(clk), // Clock input
.D(act_this_rank) // SRL data input
);
reg [2:0] faw_cnt_ns;
reg [2:0] faw_cnt_r;
reg inhbt_act_faw_ns;
always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt
or faw_cnt_r or rst) begin
if (rst) faw_cnt_ns = 3'b0;
else begin
faw_cnt_ns = faw_cnt_r;
if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1;
if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1;
end
inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt;
end
always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns;
always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns;
end // block: inhbt_act_faw
endgenerate
// In the DRAM spec, tWTR starts from CK following the end of the data
// burst. Since we don't directly have that spec, the wtr timer is
// based on when the CAS write command is sent to the DRAM.
//
// To compute the wtr timer value, first compute the time from the write command
// to the read command. This is CWL + data_time + nWTR.
//
// Two is subtracted from the required wtr time since the timer
// starts two states after the arbitration cycle.
localparam ONE = 1;
localparam TWO = 2;
localparam CASWR2CASRD = CWL + (BURST_MODE == "4" ? 2 : 4) + nWTR;
localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1)
? CASWR2CASRD :
(nCK_PER_CLK == 2)
? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) :
((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0));
localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS);
generate
begin : wtr_timer
reg write_this_rank;
always @(/*AS*/sending_col or wr_this_rank_r) begin
write_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
write_this_rank =
write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]);
end
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r;
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns;
always @(/*AS*/rst or write_this_rank or wtr_cnt_r)
if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}};
else begin
wtr_cnt_ns = wtr_cnt_r;
if (write_this_rank) wtr_cnt_ns =
CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0];
else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0];
end
wire inhbt_rd_ns = |wtr_cnt_ns;
always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns;
always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns;
end
endgenerate
// In the DRAM spec (with AL = 0), the read-to-write command delay is implied to
// be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the
// read and write data do not collide on the DQ bus. The 2 tCK ensures a gap
// between them. Here, we allow the user to tune this fixed term via the
// DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating
// this to the rank_common module, since this is a DQ/DQS bus-level requirement,
// not a per-rank requirement.
localparam CASRD2CASWR = CL + (BURST_MODE == "4" ? 2 : 4) + DQRD2DQWR_DLY - CWL;
localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1)
? CASRD2CASWR :
(nCK_PER_CLK == 2)
? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) :
((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0));
localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS);
generate
begin : rtw_timer
reg read_this_rank;
always @(/*AS*/sending_col or rd_this_rank_r) begin
read_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
read_this_rank =
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
end
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r;
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns;
always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r)
if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}};
else begin
rtw_cnt_ns = rtw_cnt_r;
if (col_rd_wr && |sending_col) rtw_cnt_ns =
CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0];
else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0];
end
wire inhbt_wr_ns = |rtw_cnt_ns;
always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns;
always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns;
end
endgenerate
// Refresh request generation. Implement a "refresh bank". Referred
// to as pullin-in refresh in the JEDEC spec.
// The refresh_rank_r counter increments when a refresh to this
// rank has been decoded. In the up direction, the count saturates
// at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK
// is normally eight. The counter decrements with each refresh_tick,
// saturating at zero. A refresh will be requests when the rank is
// not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r
// equals zero.
localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1);
generate begin : refresh_generation
reg my_rank_busy;
always @(/*AS*/rank_busy_r) begin
my_rank_busy = 1'b0;
for (i=0; i < nBANK_MACHS; i=i+1)
my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID];
end
wire my_refresh =
insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r &&
(maint_rank_r == ID[RANK_WIDTH-1:0]);
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r;
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns;
always @(/*AS*/app_ref_req or init_calib_complete or my_refresh
or refresh_bank_r or refresh_tick)
if (~init_calib_complete)
if (REFRESH_TIMER_DIV == 0)
refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH];
else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}};
else
case ({my_refresh, refresh_tick, app_ref_req})
3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r;
3'b010, 3'b001, 3'b011 : refresh_bank_ns =
(|refresh_bank_r)?
refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]:
refresh_bank_r;
3'b100 : refresh_bank_ns =
refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH];
endcase // case ({my_refresh, refresh_tick})
always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns;
`ifdef MC_SVA
refresh_bank_overflow: assert property (@(posedge clk)
(rst || (refresh_bank_r <= nREFRESH_BANK)));
refresh_bank_underflow: assert property (@(posedge clk)
(rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick)));
refresh_hi_priority: cover property (@(posedge clk)
(rst && ~|refresh_bank_ns && (refresh_bank_r ==
ONE[0+:REFRESH_BANK_WIDTH])));
refresh_bank_full: cover property (@(posedge clk)
(rst && (refresh_bank_r ==
nREFRESH_BANK[0+:REFRESH_BANK_WIDTH])));
`endif
assign refresh_request = init_calib_complete &&
(~|refresh_bank_r ||
((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy));
end
endgenerate
// Periodic read request generation.
localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1);
generate begin : periodic_rd_generation
if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads
reg read_this_rank;
always @(/*AS*/rd_this_rank_r or sending_col) begin
read_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
read_this_rank =
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
end
reg read_this_rank_r;
reg read_this_rank_r1;
always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank;
always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r;
wire int_read_this_rank = read_this_rank &&
(((nCK_PER_CLK == 4) && read_this_rank_r) ||
((nCK_PER_CLK != 4) && read_this_rank_r1));
reg periodic_rd_cntr1_ns;
reg periodic_rd_cntr1_r;
always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin
periodic_rd_cntr1_ns = periodic_rd_cntr1_r;
if (clear_periodic_rd_request)
periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1;
end
always @(posedge clk) begin
if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0;
else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns;
end
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r;
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r
or periodic_rd_timer_r or int_read_this_rank) begin
periodic_rd_timer_ns = periodic_rd_timer_r;
if (~init_calib_complete)
periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}};
else if (int_read_this_rank)
periodic_rd_timer_ns =
PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH];
else if (|periodic_rd_timer_r && maint_prescaler_tick_r)
periodic_rd_timer_ns =
periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH];
end
always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns;
wire periodic_rd_timer_one = maint_prescaler_tick_r &&
(periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]);
reg periodic_rd_request_r;
wire periodic_rd_request_ns = ~rst &&
((app_periodic_rd_req && init_calib_complete) ||
((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) ||
// (~(read_this_rank || clear_periodic_rd_request) &&
(~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) &&
(periodic_rd_request_r || periodic_rd_timer_one)));
always @(posedge clk) periodic_rd_request_r <=
#TCQ periodic_rd_request_ns;
`ifdef MC_SVA
read_clears_periodic_rd_request: cover property (@(posedge clk)
(rst && (periodic_rd_request_r && read_this_rank)));
`endif
assign periodic_rd_request = init_calib_complete && periodic_rd_request_r;
end else
assign periodic_rd_request = 1'b0; //to disable periodic reads
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
//*****************************************************************************
// This block is responsible for managing various rank level timing
// parameters. For now, only Four Activate Window (FAW) and Write
// To Read delay are implemented here.
//
// Each rank machine generates its own inhbt_act_faw_r and inhbt_rd.
// These per rank machines are driven into the bank machines. Each
// bank machines selects the correct inhibits based on the rank
// of its current request.
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v1_9_rank_cntrl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter BURST_MODE = "8", // Burst length
parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay
parameter CL = 5, // Read CAS latency
parameter CWL = 5, // Write CAS latency
parameter ID = 0, // Unique ID for each instance
parameter nBANK_MACHS = 4, // # bank machines in MC
parameter nCK_PER_CLK = 2, // DRAM clock : MC clock
parameter nFAW = 30, // four activate window (CKs)
parameter nREFRESH_BANK = 8, // # REF commands to pull-in
parameter nRRD = 4, // ACT->ACT period (CKs)
parameter nWTR = 4, // Internal write->read
// delay (CKs)
parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor
// for periodic read timer
parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a
// single bit rank signal among
// all the bank machines
parameter RANK_WIDTH = 2, // # of bits to count ranks
parameter RANKS = 4, // # of ranks of DRAM
parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor
// for refresh timer
)
(
// Maintenance requests
output periodic_rd_request,
output wire refresh_request,
// Inhibit signals
output reg inhbt_act_faw_r,
output reg inhbt_rd,
output reg inhbt_wr,
// System Inputs
input clk,
input rst,
// User maintenance requests
input app_periodic_rd_req,
input app_ref_req,
// Inputs
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
input clear_periodic_rd_request,
input col_rd_wr,
input init_calib_complete,
input insert_maint_r1,
input maint_prescaler_tick_r,
input [RANK_WIDTH-1:0] maint_rank_r,
input maint_zq_r,
input maint_sre_r,
input maint_srx_r,
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
input refresh_tick,
input [nBANK_MACHS-1:0] sending_col,
input [nBANK_MACHS-1:0] sending_row,
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r
);
//***************************************************************************
// RRD configuration. The bank machines have a mechanism to prevent RAS to
// RAS on adjacent fabric CLK states to the same rank. When
// nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD
// when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the
// higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit
// is worked into the inhbt_faw signal.
//***************************************************************************
localparam nADD_RRD = nRRD -
(
(nCK_PER_CLK == 1) ? 2 :
(nCK_PER_CLK == 2) ? 4 :
/*(nCK_PER_CLK == 4)*/ 8
);
// divide by nCK_PER_CLK and add a cycle if there's a remainder
localparam nRRD_CLKS =
(nCK_PER_CLK == 1) ? nADD_RRD :
(nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) :
/*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0));
// take binary log to obtain counter width and add a tick for the idle cycle
localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1);
//***************************************************************************
// Internal signals
//***************************************************************************
reg act_this_rank;
integer i; // loop invariant
//***************************************************************************
// Function clogb2
// Description:
// This function performs binary logarithm and rounds up
// Inputs:
// size: integer to perform binary log upon
// Outputs:
// clogb2: result of binary logarithm, rounded up
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
// increment clogb2 from 1 for each bit in size
for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1)
size = size >> 1;
end
endfunction // clogb2
//***************************************************************************
// Determine if this rank has been activated. act_this_rank_r is a
// registered bit vector from individual bank machines indicating the
// corresponding bank machine is sending
// an activate. Timing is improved with this method.
//***************************************************************************
always @(/*AS*/act_this_rank_r or sending_row) begin
act_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
act_this_rank =
act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]);
end
reg add_rrd_inhbt = 1'b0;
generate
if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
add_rrd_ns = add_rrd_r;
if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
else
if (act_this_rank)
add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
else if (|add_rrd_r) add_rrd_ns =
add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1};
end
always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
end // add_rdd1
else if (nADD_RRD > 0) begin :add_rdd0
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
add_rrd_ns = add_rrd_r;
if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
else
if (act_this_rank)
add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
else if (|add_rrd_r) add_rrd_ns =
add_rrd_r - {1'b1};
end
always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
end // add_rdd0
endgenerate
// Compute inhbt_act_faw_r. Only allow a limited number of activates
// in a window. Both the number of activates and the window are
// configurable. This depends on the RRD mechanism to prevent
// two consecutive activates to the same rank.
//
// Subtract three from the specified nFAW. Subtract three because:
// -Zero for the delay into the SRL is really one state.
// -Sending_row is used to trigger the delay. Sending_row is one
// state delayed from the arb.
// -inhbt_act_faw_r is registered to make timing work, hence the
// generation needs to be one state early.
localparam nFAW_CLKS = (nCK_PER_CLK == 1)
? nFAW
: (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) :
((nFAW/4) + ((nFAW%4) ? 1 : 0));
generate
begin : inhbt_act_faw
wire act_delayed;
wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3;
SRLC32E #(.INIT(32'h00000000) ) SRLC32E0
(.Q(act_delayed), // SRL data output
.Q31(), // SRL cascade output pin
.A(shift_depth), // 5-bit shift depth select input
.CE(1'b1), // Clock enable input
.CLK(clk), // Clock input
.D(act_this_rank) // SRL data input
);
reg [2:0] faw_cnt_ns;
reg [2:0] faw_cnt_r;
reg inhbt_act_faw_ns;
always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt
or faw_cnt_r or rst) begin
if (rst) faw_cnt_ns = 3'b0;
else begin
faw_cnt_ns = faw_cnt_r;
if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1;
if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1;
end
inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt;
end
always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns;
always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns;
end // block: inhbt_act_faw
endgenerate
// In the DRAM spec, tWTR starts from CK following the end of the data
// burst. Since we don't directly have that spec, the wtr timer is
// based on when the CAS write command is sent to the DRAM.
//
// To compute the wtr timer value, first compute the time from the write command
// to the read command. This is CWL + data_time + nWTR.
//
// Two is subtracted from the required wtr time since the timer
// starts two states after the arbitration cycle.
localparam ONE = 1;
localparam TWO = 2;
localparam CASWR2CASRD = CWL + (BURST_MODE == "4" ? 2 : 4) + nWTR;
localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1)
? CASWR2CASRD :
(nCK_PER_CLK == 2)
? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) :
((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0));
localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS);
generate
begin : wtr_timer
reg write_this_rank;
always @(/*AS*/sending_col or wr_this_rank_r) begin
write_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
write_this_rank =
write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]);
end
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r;
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns;
always @(/*AS*/rst or write_this_rank or wtr_cnt_r)
if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}};
else begin
wtr_cnt_ns = wtr_cnt_r;
if (write_this_rank) wtr_cnt_ns =
CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0];
else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0];
end
wire inhbt_rd_ns = |wtr_cnt_ns;
always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns;
always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns;
end
endgenerate
// In the DRAM spec (with AL = 0), the read-to-write command delay is implied to
// be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the
// read and write data do not collide on the DQ bus. The 2 tCK ensures a gap
// between them. Here, we allow the user to tune this fixed term via the
// DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating
// this to the rank_common module, since this is a DQ/DQS bus-level requirement,
// not a per-rank requirement.
localparam CASRD2CASWR = CL + (BURST_MODE == "4" ? 2 : 4) + DQRD2DQWR_DLY - CWL;
localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1)
? CASRD2CASWR :
(nCK_PER_CLK == 2)
? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) :
((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0));
localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS);
generate
begin : rtw_timer
reg read_this_rank;
always @(/*AS*/sending_col or rd_this_rank_r) begin
read_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
read_this_rank =
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
end
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r;
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns;
always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r)
if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}};
else begin
rtw_cnt_ns = rtw_cnt_r;
if (col_rd_wr && |sending_col) rtw_cnt_ns =
CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0];
else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0];
end
wire inhbt_wr_ns = |rtw_cnt_ns;
always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns;
always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns;
end
endgenerate
// Refresh request generation. Implement a "refresh bank". Referred
// to as pullin-in refresh in the JEDEC spec.
// The refresh_rank_r counter increments when a refresh to this
// rank has been decoded. In the up direction, the count saturates
// at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK
// is normally eight. The counter decrements with each refresh_tick,
// saturating at zero. A refresh will be requests when the rank is
// not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r
// equals zero.
localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1);
generate begin : refresh_generation
reg my_rank_busy;
always @(/*AS*/rank_busy_r) begin
my_rank_busy = 1'b0;
for (i=0; i < nBANK_MACHS; i=i+1)
my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID];
end
wire my_refresh =
insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r &&
(maint_rank_r == ID[RANK_WIDTH-1:0]);
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r;
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns;
always @(/*AS*/app_ref_req or init_calib_complete or my_refresh
or refresh_bank_r or refresh_tick)
if (~init_calib_complete)
if (REFRESH_TIMER_DIV == 0)
refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH];
else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}};
else
case ({my_refresh, refresh_tick, app_ref_req})
3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r;
3'b010, 3'b001, 3'b011 : refresh_bank_ns =
(|refresh_bank_r)?
refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]:
refresh_bank_r;
3'b100 : refresh_bank_ns =
refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH];
endcase // case ({my_refresh, refresh_tick})
always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns;
`ifdef MC_SVA
refresh_bank_overflow: assert property (@(posedge clk)
(rst || (refresh_bank_r <= nREFRESH_BANK)));
refresh_bank_underflow: assert property (@(posedge clk)
(rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick)));
refresh_hi_priority: cover property (@(posedge clk)
(rst && ~|refresh_bank_ns && (refresh_bank_r ==
ONE[0+:REFRESH_BANK_WIDTH])));
refresh_bank_full: cover property (@(posedge clk)
(rst && (refresh_bank_r ==
nREFRESH_BANK[0+:REFRESH_BANK_WIDTH])));
`endif
assign refresh_request = init_calib_complete &&
(~|refresh_bank_r ||
((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy));
end
endgenerate
// Periodic read request generation.
localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1);
generate begin : periodic_rd_generation
if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads
reg read_this_rank;
always @(/*AS*/rd_this_rank_r or sending_col) begin
read_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
read_this_rank =
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
end
reg read_this_rank_r;
reg read_this_rank_r1;
always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank;
always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r;
wire int_read_this_rank = read_this_rank &&
(((nCK_PER_CLK == 4) && read_this_rank_r) ||
((nCK_PER_CLK != 4) && read_this_rank_r1));
reg periodic_rd_cntr1_ns;
reg periodic_rd_cntr1_r;
always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin
periodic_rd_cntr1_ns = periodic_rd_cntr1_r;
if (clear_periodic_rd_request)
periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1;
end
always @(posedge clk) begin
if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0;
else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns;
end
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r;
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r
or periodic_rd_timer_r or int_read_this_rank) begin
periodic_rd_timer_ns = periodic_rd_timer_r;
if (~init_calib_complete)
periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}};
else if (int_read_this_rank)
periodic_rd_timer_ns =
PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH];
else if (|periodic_rd_timer_r && maint_prescaler_tick_r)
periodic_rd_timer_ns =
periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH];
end
always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns;
wire periodic_rd_timer_one = maint_prescaler_tick_r &&
(periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]);
reg periodic_rd_request_r;
wire periodic_rd_request_ns = ~rst &&
((app_periodic_rd_req && init_calib_complete) ||
((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) ||
// (~(read_this_rank || clear_periodic_rd_request) &&
(~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) &&
(periodic_rd_request_r || periodic_rd_timer_one)));
always @(posedge clk) periodic_rd_request_r <=
#TCQ periodic_rd_request_ns;
`ifdef MC_SVA
read_clears_periodic_rd_request: cover property (@(posedge clk)
(rst && (periodic_rd_request_r && read_this_rank)));
`endif
assign periodic_rd_request = init_calib_complete && periodic_rd_request_r;
end else
assign periodic_rd_request = 1'b0; //to disable periodic reads
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef struct packed {
bit b9;
byte b1;
bit b0;
} pack_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
pack_t in;
always @* in = crc[9:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
pack_t out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out),
// Inputs
.in (in));
// Aggregate outputs into a single result vector
wire [63:0] result = {54'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x in=%x result=%x\n",$time, cyc, crc, in, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h99c434d9b08c2a8a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input pack_t in,
output pack_t out);
always @* begin
out = in;
out.b1 = in.b1 + 1;
out.b0 = 1'b1;
end
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef struct packed {
bit b9;
byte b1;
bit b0;
} pack_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
pack_t in;
always @* in = crc[9:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
pack_t out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out),
// Inputs
.in (in));
// Aggregate outputs into a single result vector
wire [63:0] result = {54'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x in=%x result=%x\n",$time, cyc, crc, in, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h99c434d9b08c2a8a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input pack_t in,
output pack_t out);
always @* begin
out = in;
out.b1 = in.b1 + 1;
out.b0 = 1'b1;
end
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fir_shift_reg_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 32;
parameter AWIDTH = 4;
parameter MEM_SIZE = 11;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./fir_shift_reg_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module fir_shift_reg(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd11;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
fir_shift_reg_ram fir_shift_reg_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fir_shift_reg_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 32;
parameter AWIDTH = 4;
parameter MEM_SIZE = 11;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./fir_shift_reg_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module fir_shift_reg(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd11;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
fir_shift_reg_ram fir_shift_reg_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: INSTITUTO TECNOLOGICO DE COSTA RICA
// Engineer: MAURICIO CARVAJAL DELGADO
//
// Create Date: 10:32:12 03/17/2013
// Design Name:
// Module Name: Receptor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//////////////////////////////////////////////////////////////////////////////////
module Receptor#(
parameter DBIT=8, // #databits
SB_TICK=16 //#ticks for stop bits
)
(
input wire clk, reset,
input wire rx, s_tick,
output reg rx_done_tick,
output wire [7:0] dout
);
//symbolic state declaration
localparam [1:0]
idle = 2'b00,
start = 2'b01,
data = 2'b10,
stop = 2'b11;
// signal declaration
reg [1:0] state_reg=0, state_next=0;
reg [3:0] s_reg=0, s_next=0;
reg [2:0] n_reg=0, n_next=0;
reg [7:0] b_reg=0, b_next=0;
// body
// FSMD state&data registers
always @( posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0;
end
else
begin
state_reg <=state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
end
// FSMD next_state logic
always @*
begin
state_next = state_reg;
rx_done_tick = 1'b0;
s_next = s_reg;
n_next = n_reg;
b_next = b_reg;
case (state_reg)
idle:
if (~rx)
begin
state_next = start;
s_next =0;
end
start:
if (s_tick)
if (s_reg==7)
begin
state_next = data;
s_next = 0;
n_next = 0;
end
else
s_next = s_reg+1;
data:
if (s_tick)
if (s_reg == 15)
begin
s_next = 0;
b_next = {rx,b_reg [7:1]};
if (n_reg==(DBIT-1))
state_next = stop;
else
n_next = n_reg + 1;
end
else
s_next = s_reg + 1;
stop:
if (s_tick)
if (s_reg==(SB_TICK-1))
begin
state_next = idle;
rx_done_tick = 1'b1;
end
else
s_next = s_reg + 1;
endcase
end
//output
assign dout = b_reg;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: INSTITUTO TECNOLOGICO DE COSTA RICA
// Engineer: MAURICIO CARVAJAL DELGADO
//
// Create Date: 10:32:12 03/17/2013
// Design Name:
// Module Name: Receptor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//////////////////////////////////////////////////////////////////////////////////
module Receptor#(
parameter DBIT=8, // #databits
SB_TICK=16 //#ticks for stop bits
)
(
input wire clk, reset,
input wire rx, s_tick,
output reg rx_done_tick,
output wire [7:0] dout
);
//symbolic state declaration
localparam [1:0]
idle = 2'b00,
start = 2'b01,
data = 2'b10,
stop = 2'b11;
// signal declaration
reg [1:0] state_reg=0, state_next=0;
reg [3:0] s_reg=0, s_next=0;
reg [2:0] n_reg=0, n_next=0;
reg [7:0] b_reg=0, b_next=0;
// body
// FSMD state&data registers
always @( posedge clk, posedge reset)
if (reset)
begin
state_reg <= idle;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0;
end
else
begin
state_reg <=state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
end
// FSMD next_state logic
always @*
begin
state_next = state_reg;
rx_done_tick = 1'b0;
s_next = s_reg;
n_next = n_reg;
b_next = b_reg;
case (state_reg)
idle:
if (~rx)
begin
state_next = start;
s_next =0;
end
start:
if (s_tick)
if (s_reg==7)
begin
state_next = data;
s_next = 0;
n_next = 0;
end
else
s_next = s_reg+1;
data:
if (s_tick)
if (s_reg == 15)
begin
s_next = 0;
b_next = {rx,b_reg [7:1]};
if (n_reg==(DBIT-1))
state_next = stop;
else
n_next = n_reg + 1;
end
else
s_next = s_reg + 1;
stop:
if (s_tick)
if (s_reg==(SB_TICK-1))
begin
state_next = idle;
rx_done_tick = 1'b1;
end
else
s_next = s_reg + 1;
endcase
end
//output
assign dout = b_reg;
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Bool NAxioms NSub NPow NDiv NParity NLog.
(** Derived properties of bitwise operations *)
Module Type NBitsProp
(Import A : NAxiomsSig')
(Import B : NSubProp A)
(Import C : NParityProp A B)
(Import D : NPowProp A B C)
(Import E : NDivProp A B)
(Import F : NLog2Prop A B C D).
Include BoolEqualityFacts A.
Ltac order_nz := try apply pow_nonzero; order'.
Hint Rewrite div_0_l mod_0_l div_1_r mod_1_r : nz.
(** Some properties of power and division *)
Lemma pow_sub_r : forall a b c, a~=0 -> c<=b -> a^(b-c) == a^b / a^c.
Proof.
intros a b c Ha H.
apply div_unique with 0.
generalize (pow_nonzero a c Ha) (le_0_l (a^c)); order'.
nzsimpl. now rewrite <- pow_add_r, add_comm, sub_add.
Qed.
Lemma pow_div_l : forall a b c, b~=0 -> a mod b == 0 ->
(a/b)^c == a^c / b^c.
Proof.
intros a b c Hb H.
apply div_unique with 0.
generalize (pow_nonzero b c Hb) (le_0_l (b^c)); order'.
nzsimpl. rewrite <- pow_mul_l. f_equiv. now apply div_exact.
Qed.
(** An injection from bits [true] and [false] to numbers 1 and 0.
We declare it as a (local) coercion for shorter statements. *)
Definition b2n (b:bool) := if b then 1 else 0.
Local Coercion b2n : bool >-> t.
Instance b2n_proper : Proper (Logic.eq ==> eq) b2n.
Proof. solve_proper. Qed.
Lemma exists_div2 a : exists a' (b:bool), a == 2*a' + b.
Proof.
elim (Even_or_Odd a); [intros (a',H)| intros (a',H)].
exists a'. exists false. now nzsimpl.
exists a'. exists true. now simpl.
Qed.
(** We can compact [testbit_odd_0] [testbit_even_0]
[testbit_even_succ] [testbit_odd_succ] in only two lemmas. *)
Lemma testbit_0_r a (b:bool) : testbit (2*a+b) 0 = b.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_0.
apply testbit_even_0.
Qed.
Lemma testbit_succ_r a (b:bool) n :
testbit (2*a+b) (succ n) = testbit a n.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_succ, le_0_l.
apply testbit_even_succ, le_0_l.
Qed.
(** Alternative caracterisations of [testbit] *)
(** This concise equation could have been taken as specification
for testbit in the interface, but it would have been hard to
implement with little initial knowledge about div and mod *)
Lemma testbit_spec' a n : a.[n] == (a / 2^n) mod 2.
Proof.
revert a. induct n.
intros a. nzsimpl.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_0_r. apply mod_unique with a'; trivial.
destruct b; order'.
intros n IH a.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_succ_r, IH. f_equiv.
rewrite pow_succ_r', <- div_div by order_nz. f_equiv.
apply div_unique with b; trivial.
destruct b; order'.
Qed.
(** This caracterisation that uses only basic operations and
power was initially taken as specification for testbit.
We describe [a] as having a low part and a high part, with
the corresponding bit in the middle. This caracterisation
is moderatly complex to implement, but also moderately
usable... *)
Lemma testbit_spec a n :
exists l h, 0<=l<2^n /\ a == l + (a.[n] + 2*h)*2^n.
Proof.
exists (a mod 2^n). exists (a / 2^n / 2). split.
split; [apply le_0_l | apply mod_upper_bound; order_nz].
rewrite add_comm, mul_comm, (add_comm a.[n]).
rewrite (div_mod a (2^n)) at 1 by order_nz. do 2 f_equiv.
rewrite testbit_spec'. apply div_mod. order'.
Qed.
Lemma testbit_true : forall a n,
a.[n] = true <-> (a / 2^n) mod 2 == 1.
Proof.
intros a n.
rewrite <- testbit_spec'; destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_false : forall a n,
a.[n] = false <-> (a / 2^n) mod 2 == 0.
Proof.
intros a n.
rewrite <- testbit_spec'; destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_eqb : forall a n,
a.[n] = eqb ((a / 2^n) mod 2) 1.
Proof.
intros a n.
apply eq_true_iff_eq. now rewrite testbit_true, eqb_eq.
Qed.
(** Results about the injection [b2n] *)
Lemma b2n_inj : forall (a0 b0:bool), a0 == b0 -> a0 = b0.
Proof.
intros [|] [|]; simpl; trivial; order'.
Qed.
Lemma add_b2n_double_div2 : forall (a0:bool) a, (a0+2*a)/2 == a.
Proof.
intros a0 a. rewrite mul_comm, div_add by order'.
now rewrite div_small, add_0_l by (destruct a0; order').
Qed.
Lemma add_b2n_double_bit0 : forall (a0:bool) a, (a0+2*a).[0] = a0.
Proof.
intros a0 a. apply b2n_inj.
rewrite testbit_spec'. nzsimpl. rewrite mul_comm, mod_add by order'.
now rewrite mod_small by (destruct a0; order').
Qed.
Lemma b2n_div2 : forall (a0:bool), a0/2 == 0.
Proof.
intros a0. rewrite <- (add_b2n_double_div2 a0 0). now nzsimpl.
Qed.
Lemma b2n_bit0 : forall (a0:bool), a0.[0] = a0.
Proof.
intros a0. rewrite <- (add_b2n_double_bit0 a0 0) at 2. now nzsimpl.
Qed.
(** The specification of testbit by low and high parts is complete *)
Lemma testbit_unique : forall a n (a0:bool) l h,
l<2^n -> a == l + (a0 + 2*h)*2^n -> a.[n] = a0.
Proof.
intros a n a0 l h Hl EQ.
apply b2n_inj. rewrite testbit_spec' by trivial.
symmetry. apply mod_unique with h. destruct a0; simpl; order'.
symmetry. apply div_unique with l; trivial.
now rewrite add_comm, (add_comm _ a0), mul_comm.
Qed.
(** All bits of number 0 are 0 *)
Lemma bits_0 : forall n, 0.[n] = false.
Proof.
intros n. apply testbit_false. nzsimpl; order_nz.
Qed.
(** Various ways to refer to the lowest bit of a number *)
Lemma bit0_odd : forall a, a.[0] = odd a.
Proof.
intros. symmetry.
destruct (exists_div2 a) as (a' & b & EQ).
rewrite EQ, testbit_0_r, add_comm, odd_add_mul_2.
destruct b; simpl; apply odd_1 || apply odd_0.
Qed.
Lemma bit0_eqb : forall a, a.[0] = eqb (a mod 2) 1.
Proof.
intros a. rewrite testbit_eqb. now nzsimpl.
Qed.
Lemma bit0_mod : forall a, a.[0] == a mod 2.
Proof.
intros a. rewrite testbit_spec'. now nzsimpl.
Qed.
(** Hence testing a bit is equivalent to shifting and testing parity *)
Lemma testbit_odd : forall a n, a.[n] = odd (a>>n).
Proof.
intros. now rewrite <- bit0_odd, shiftr_spec, add_0_l.
Qed.
(** [log2] gives the highest nonzero bit *)
Lemma bit_log2 : forall a, a~=0 -> a.[log2 a] = true.
Proof.
intros a Ha.
assert (Ha' : 0 < a) by (generalize (le_0_l a); order).
destruct (log2_spec_alt a Ha') as (r & EQ & (_,Hr)).
rewrite EQ at 1.
rewrite testbit_true, add_comm.
rewrite <- (mul_1_l (2^log2 a)) at 1.
rewrite div_add by order_nz.
rewrite div_small by trivial.
rewrite add_0_l. apply mod_small. order'.
Qed.
Lemma bits_above_log2 : forall a n, log2 a < n ->
a.[n] = false.
Proof.
intros a n H.
rewrite testbit_false.
rewrite div_small. nzsimpl; order'.
apply log2_lt_cancel. rewrite log2_pow2; trivial using le_0_l.
Qed.
(** Hence the number of bits of [a] is [1+log2 a]
(see [Pos.size_nat] and [Pos.size]).
*)
(** Testing bits after division or multiplication by a power of two *)
Lemma div2_bits : forall a n, (a/2).[n] = a.[S n].
Proof.
intros. apply eq_true_iff_eq.
rewrite 2 testbit_true.
rewrite pow_succ_r by apply le_0_l.
now rewrite div_div by order_nz.
Qed.
Lemma div_pow2_bits : forall a n m, (a/2^n).[m] = a.[m+n].
Proof.
intros a n. revert a. induct n.
intros a m. now nzsimpl.
intros n IH a m. nzsimpl; try apply le_0_l.
rewrite <- div_div by order_nz.
now rewrite IH, div2_bits.
Qed.
Lemma double_bits_succ : forall a n, (2*a).[S n] = a.[n].
Proof.
intros. rewrite <- div2_bits. now rewrite mul_comm, div_mul by order'.
Qed.
Lemma mul_pow2_bits_add : forall a n m, (a*2^n).[m+n] = a.[m].
Proof.
intros. rewrite <- div_pow2_bits. now rewrite div_mul by order_nz.
Qed.
Lemma mul_pow2_bits_high : forall a n m, n<=m -> (a*2^n).[m] = a.[m-n].
Proof.
intros.
rewrite <- (sub_add n m) at 1 by order'.
now rewrite mul_pow2_bits_add.
Qed.
Lemma mul_pow2_bits_low : forall a n m, m<n -> (a*2^n).[m] = false.
Proof.
intros. apply testbit_false.
rewrite <- (sub_add m n) by order'. rewrite pow_add_r, mul_assoc.
rewrite div_mul by order_nz.
rewrite <- (succ_pred (n-m)). rewrite pow_succ_r.
now rewrite (mul_comm 2), mul_assoc, mod_mul by order'.
apply lt_le_pred.
apply sub_gt in H. generalize (le_0_l (n-m)); order.
now apply sub_gt.
Qed.
(** Selecting the low part of a number can be done by a modulo *)
Lemma mod_pow2_bits_high : forall a n m, n<=m ->
(a mod 2^n).[m] = false.
Proof.
intros a n m H.
destruct (eq_0_gt_0_cases (a mod 2^n)) as [EQ|LT].
now rewrite EQ, bits_0.
apply bits_above_log2.
apply lt_le_trans with n; trivial.
apply log2_lt_pow2; trivial.
apply mod_upper_bound; order_nz.
Qed.
Lemma mod_pow2_bits_low : forall a n m, m<n ->
(a mod 2^n).[m] = a.[m].
Proof.
intros a n m H.
rewrite testbit_eqb.
rewrite <- (mod_add _ (2^(P (n-m))*(a/2^n))) by order'.
rewrite <- div_add by order_nz.
rewrite (mul_comm _ 2), mul_assoc, <- pow_succ_r', succ_pred
by now apply sub_gt.
rewrite mul_comm, mul_assoc, <- pow_add_r, (add_comm m), sub_add
by order.
rewrite add_comm, <- div_mod by order_nz.
symmetry. apply testbit_eqb.
Qed.
(** We now prove that having the same bits implies equality.
For that we use a notion of equality over functional
streams of bits. *)
Definition eqf (f g:t -> bool) := forall n:t, f n = g n.
Instance eqf_equiv : Equivalence eqf.
Proof.
split; congruence.
Qed.
Local Infix "===" := eqf (at level 70, no associativity).
Instance testbit_eqf : Proper (eq==>eqf) testbit.
Proof.
intros a a' Ha n. now rewrite Ha.
Qed.
(** Only zero corresponds to the always-false stream. *)
Lemma bits_inj_0 :
forall a, (forall n, a.[n] = false) -> a == 0.
Proof.
intros a H. destruct (eq_decidable a 0) as [EQ|NEQ]; trivial.
apply bit_log2 in NEQ. now rewrite H in NEQ.
Qed.
(** If two numbers produce the same stream of bits, they are equal. *)
Lemma bits_inj : forall a b, testbit a === testbit b -> a == b.
Proof.
intros a. pattern a.
apply strong_right_induction with 0;[solve_proper|clear a|apply le_0_l].
intros a _ IH b H.
destruct (eq_0_gt_0_cases a) as [EQ|LT].
rewrite EQ in H |- *. symmetry. apply bits_inj_0.
intros n. now rewrite <- H, bits_0.
rewrite (div_mod a 2), (div_mod b 2) by order'.
f_equiv; [ | now rewrite <- 2 bit0_mod, H].
f_equiv.
apply IH; trivial using le_0_l.
apply div_lt; order'.
intro n. rewrite 2 div2_bits. apply H.
Qed.
Lemma bits_inj_iff : forall a b, testbit a === testbit b <-> a == b.
Proof.
split. apply bits_inj. intros EQ; now rewrite EQ.
Qed.
Hint Rewrite lxor_spec lor_spec land_spec ldiff_spec bits_0 : bitwise.
Ltac bitwise := apply bits_inj; intros ?m; autorewrite with bitwise.
(** The streams of bits that correspond to a natural numbers are
exactly the ones that are always 0 after some point *)
Lemma are_bits : forall (f:t->bool), Proper (eq==>Logic.eq) f ->
((exists n, f === testbit n) <->
(exists k, forall m, k<=m -> f m = false)).
Proof.
intros f Hf. split.
intros (a,H).
exists (S (log2 a)). intros m Hm. apply le_succ_l in Hm.
rewrite H, bits_above_log2; trivial using lt_succ_diag_r.
intros (k,Hk).
revert f Hf Hk. induct k.
intros f Hf H0.
exists 0. intros m. rewrite bits_0, H0; trivial. apply le_0_l.
intros k IH f Hf Hk.
destruct (IH (fun m => f (S m))) as (n, Hn).
solve_proper.
intros m Hm. apply Hk. now rewrite <- succ_le_mono.
exists (f 0 + 2*n). intros m.
destruct (zero_or_succ m) as [Hm|(m', Hm)]; rewrite Hm.
symmetry. apply add_b2n_double_bit0.
rewrite Hn, <- div2_bits.
rewrite mul_comm, div_add, b2n_div2, add_0_l; trivial. order'.
Qed.
(** Properties of shifts *)
Lemma shiftr_spec' : forall a n m, (a >> n).[m] = a.[m+n].
Proof.
intros. apply shiftr_spec. apply le_0_l.
Qed.
Lemma shiftl_spec_high' : forall a n m, n<=m -> (a << n).[m] = a.[m-n].
Proof.
intros. apply shiftl_spec_high; trivial. apply le_0_l.
Qed.
Lemma shiftr_div_pow2 : forall a n, a >> n == a / 2^n.
Proof.
intros. bitwise. rewrite shiftr_spec'.
symmetry. apply div_pow2_bits.
Qed.
Lemma shiftl_mul_pow2 : forall a n, a << n == a * 2^n.
Proof.
intros. bitwise.
destruct (le_gt_cases n m) as [H|H].
now rewrite shiftl_spec_high', mul_pow2_bits_high.
now rewrite shiftl_spec_low, mul_pow2_bits_low.
Qed.
Lemma shiftl_spec_alt : forall a n m, (a << n).[m+n] = a.[m].
Proof.
intros. now rewrite shiftl_mul_pow2, mul_pow2_bits_add.
Qed.
Instance shiftr_wd : Proper (eq==>eq==>eq) shiftr.
Proof.
intros a a' Ha b b' Hb. now rewrite 2 shiftr_div_pow2, Ha, Hb.
Qed.
Instance shiftl_wd : Proper (eq==>eq==>eq) shiftl.
Proof.
intros a a' Ha b b' Hb. now rewrite 2 shiftl_mul_pow2, Ha, Hb.
Qed.
Lemma shiftl_shiftl : forall a n m,
(a << n) << m == a << (n+m).
Proof.
intros. now rewrite !shiftl_mul_pow2, pow_add_r, mul_assoc.
Qed.
Lemma shiftr_shiftr : forall a n m,
(a >> n) >> m == a >> (n+m).
Proof.
intros.
now rewrite !shiftr_div_pow2, pow_add_r, div_div by order_nz.
Qed.
Lemma shiftr_shiftl_l : forall a n m, m<=n ->
(a << n) >> m == a << (n-m).
Proof.
intros.
rewrite shiftr_div_pow2, !shiftl_mul_pow2.
rewrite <- (sub_add m n) at 1 by trivial.
now rewrite pow_add_r, mul_assoc, div_mul by order_nz.
Qed.
Lemma shiftr_shiftl_r : forall a n m, n<=m ->
(a << n) >> m == a >> (m-n).
Proof.
intros.
rewrite !shiftr_div_pow2, shiftl_mul_pow2.
rewrite <- (sub_add n m) at 1 by trivial.
rewrite pow_add_r, (mul_comm (2^(m-n))).
now rewrite <- div_div, div_mul by order_nz.
Qed.
(** shifts and constants *)
Lemma shiftl_1_l : forall n, 1 << n == 2^n.
Proof.
intros. now rewrite shiftl_mul_pow2, mul_1_l.
Qed.
Lemma shiftl_0_r : forall a, a << 0 == a.
Proof.
intros. rewrite shiftl_mul_pow2. now nzsimpl.
Qed.
Lemma shiftr_0_r : forall a, a >> 0 == a.
Proof.
intros. rewrite shiftr_div_pow2. now nzsimpl.
Qed.
Lemma shiftl_0_l : forall n, 0 << n == 0.
Proof.
intros. rewrite shiftl_mul_pow2. now nzsimpl.
Qed.
Lemma shiftr_0_l : forall n, 0 >> n == 0.
Proof.
intros. rewrite shiftr_div_pow2. nzsimpl; order_nz.
Qed.
Lemma shiftl_eq_0_iff : forall a n, a << n == 0 <-> a == 0.
Proof.
intros a n. rewrite shiftl_mul_pow2. rewrite eq_mul_0. split.
intros [H | H]; trivial. contradict H; order_nz.
intros H. now left.
Qed.
Lemma shiftr_eq_0_iff : forall a n,
a >> n == 0 <-> a==0 \/ (0<a /\ log2 a < n).
Proof.
intros a n.
rewrite shiftr_div_pow2, div_small_iff by order_nz.
destruct (eq_0_gt_0_cases a) as [EQ|LT].
rewrite EQ. split. now left. intros _.
assert (H : 2~=0) by order'.
generalize (pow_nonzero 2 n H) (le_0_l (2^n)); order.
rewrite log2_lt_pow2; trivial.
split. right; split; trivial. intros [H|[_ H]]; now order.
Qed.
Lemma shiftr_eq_0 : forall a n, log2 a < n -> a >> n == 0.
Proof.
intros a n H. rewrite shiftr_eq_0_iff.
destruct (eq_0_gt_0_cases a) as [EQ|LT]. now left. right; now split.
Qed.
(** Properties of [div2]. *)
Lemma div2_div : forall a, div2 a == a/2.
Proof.
intros. rewrite div2_spec, shiftr_div_pow2. now nzsimpl.
Qed.
Instance div2_wd : Proper (eq==>eq) div2.
Proof.
intros a a' Ha. now rewrite 2 div2_div, Ha.
Qed.
Lemma div2_odd : forall a, a == 2*(div2 a) + odd a.
Proof.
intros a. rewrite div2_div, <- bit0_odd, bit0_mod.
apply div_mod. order'.
Qed.
(** Properties of [lxor] and others, directly deduced
from properties of [xorb] and others. *)
Instance lxor_wd : Proper (eq ==> eq ==> eq) lxor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance land_wd : Proper (eq ==> eq ==> eq) land.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance lor_wd : Proper (eq ==> eq ==> eq) lor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance ldiff_wd : Proper (eq ==> eq ==> eq) ldiff.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Lemma lxor_eq : forall a a', lxor a a' == 0 -> a == a'.
Proof.
intros a a' H. bitwise. apply xorb_eq.
now rewrite <- lxor_spec, H, bits_0.
Qed.
Lemma lxor_nilpotent : forall a, lxor a a == 0.
Proof.
intros. bitwise. apply xorb_nilpotent.
Qed.
Lemma lxor_eq_0_iff : forall a a', lxor a a' == 0 <-> a == a'.
Proof.
split. apply lxor_eq. intros EQ; rewrite EQ; apply lxor_nilpotent.
Qed.
Lemma lxor_0_l : forall a, lxor 0 a == a.
Proof.
intros. bitwise. apply xorb_false_l.
Qed.
Lemma lxor_0_r : forall a, lxor a 0 == a.
Proof.
intros. bitwise. apply xorb_false_r.
Qed.
Lemma lxor_comm : forall a b, lxor a b == lxor b a.
Proof.
intros. bitwise. apply xorb_comm.
Qed.
Lemma lxor_assoc :
forall a b c, lxor (lxor a b) c == lxor a (lxor b c).
Proof.
intros. bitwise. apply xorb_assoc.
Qed.
Lemma lor_0_l : forall a, lor 0 a == a.
Proof.
intros. bitwise. trivial.
Qed.
Lemma lor_0_r : forall a, lor a 0 == a.
Proof.
intros. bitwise. apply orb_false_r.
Qed.
Lemma lor_comm : forall a b, lor a b == lor b a.
Proof.
intros. bitwise. apply orb_comm.
Qed.
Lemma lor_assoc :
forall a b c, lor a (lor b c) == lor (lor a b) c.
Proof.
intros. bitwise. apply orb_assoc.
Qed.
Lemma lor_diag : forall a, lor a a == a.
Proof.
intros. bitwise. apply orb_diag.
Qed.
Lemma lor_eq_0_l : forall a b, lor a b == 0 -> a == 0.
Proof.
intros a b H. bitwise.
apply (orb_false_iff a.[m] b.[m]).
now rewrite <- lor_spec, H, bits_0.
Qed.
Lemma lor_eq_0_iff : forall a b, lor a b == 0 <-> a == 0 /\ b == 0.
Proof.
intros a b. split.
split. now apply lor_eq_0_l in H.
rewrite lor_comm in H. now apply lor_eq_0_l in H.
intros (EQ,EQ'). now rewrite EQ, lor_0_l.
Qed.
Lemma land_0_l : forall a, land 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma land_0_r : forall a, land a 0 == 0.
Proof.
intros. bitwise. apply andb_false_r.
Qed.
Lemma land_comm : forall a b, land a b == land b a.
Proof.
intros. bitwise. apply andb_comm.
Qed.
Lemma land_assoc :
forall a b c, land a (land b c) == land (land a b) c.
Proof.
intros. bitwise. apply andb_assoc.
Qed.
Lemma land_diag : forall a, land a a == a.
Proof.
intros. bitwise. apply andb_diag.
Qed.
Lemma ldiff_0_l : forall a, ldiff 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma ldiff_0_r : forall a, ldiff a 0 == a.
Proof.
intros. bitwise. now rewrite andb_true_r.
Qed.
Lemma ldiff_diag : forall a, ldiff a a == 0.
Proof.
intros. bitwise. apply andb_negb_r.
Qed.
Lemma lor_land_distr_l : forall a b c,
lor (land a b) c == land (lor a c) (lor b c).
Proof.
intros. bitwise. apply orb_andb_distrib_l.
Qed.
Lemma lor_land_distr_r : forall a b c,
lor a (land b c) == land (lor a b) (lor a c).
Proof.
intros. bitwise. apply orb_andb_distrib_r.
Qed.
Lemma land_lor_distr_l : forall a b c,
land (lor a b) c == lor (land a c) (land b c).
Proof.
intros. bitwise. apply andb_orb_distrib_l.
Qed.
Lemma land_lor_distr_r : forall a b c,
land a (lor b c) == lor (land a b) (land a c).
Proof.
intros. bitwise. apply andb_orb_distrib_r.
Qed.
Lemma ldiff_ldiff_l : forall a b c,
ldiff (ldiff a b) c == ldiff a (lor b c).
Proof.
intros. bitwise. now rewrite negb_orb, andb_assoc.
Qed.
Lemma lor_ldiff_and : forall a b,
lor (ldiff a b) (land a b) == a.
Proof.
intros. bitwise.
now rewrite <- andb_orb_distrib_r, orb_comm, orb_negb_r, andb_true_r.
Qed.
Lemma land_ldiff : forall a b,
land (ldiff a b) b == 0.
Proof.
intros. bitwise.
now rewrite <-andb_assoc, (andb_comm (negb _)), andb_negb_r, andb_false_r.
Qed.
(** Properties of [setbit] and [clearbit] *)
Definition setbit a n := lor a (1<<n).
Definition clearbit a n := ldiff a (1<<n).
Lemma setbit_spec' : forall a n, setbit a n == lor a (2^n).
Proof.
intros. unfold setbit. now rewrite shiftl_1_l.
Qed.
Lemma clearbit_spec' : forall a n, clearbit a n == ldiff a (2^n).
Proof.
intros. unfold clearbit. now rewrite shiftl_1_l.
Qed.
Instance setbit_wd : Proper (eq==>eq==>eq) setbit.
Proof. unfold setbit. solve_proper. Qed.
Instance clearbit_wd : Proper (eq==>eq==>eq) clearbit.
Proof. unfold clearbit. solve_proper. Qed.
Lemma pow2_bits_true : forall n, (2^n).[n] = true.
Proof.
intros. rewrite <- (mul_1_l (2^n)). rewrite <- (add_0_l n) at 2.
now rewrite mul_pow2_bits_add, bit0_odd, odd_1.
Qed.
Lemma pow2_bits_false : forall n m, n~=m -> (2^n).[m] = false.
Proof.
intros.
rewrite <- (mul_1_l (2^n)).
destruct (le_gt_cases n m).
rewrite mul_pow2_bits_high; trivial.
rewrite <- (succ_pred (m-n)) by (apply sub_gt; order).
now rewrite <- div2_bits, div_small, bits_0 by order'.
rewrite mul_pow2_bits_low; trivial.
Qed.
Lemma pow2_bits_eqb : forall n m, (2^n).[m] = eqb n m.
Proof.
intros. apply eq_true_iff_eq. rewrite eqb_eq. split.
destruct (eq_decidable n m) as [H|H]. trivial.
now rewrite (pow2_bits_false _ _ H).
intros EQ. rewrite EQ. apply pow2_bits_true.
Qed.
Lemma setbit_eqb : forall a n m,
(setbit a n).[m] = eqb n m || a.[m].
Proof.
intros. now rewrite setbit_spec', lor_spec, pow2_bits_eqb, orb_comm.
Qed.
Lemma setbit_iff : forall a n m,
(setbit a n).[m] = true <-> n==m \/ a.[m] = true.
Proof.
intros. now rewrite setbit_eqb, orb_true_iff, eqb_eq.
Qed.
Lemma setbit_eq : forall a n, (setbit a n).[n] = true.
Proof.
intros. apply setbit_iff. now left.
Qed.
Lemma setbit_neq : forall a n m, n~=m ->
(setbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite setbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. now rewrite H.
Qed.
Lemma clearbit_eqb : forall a n m,
(clearbit a n).[m] = a.[m] && negb (eqb n m).
Proof.
intros. now rewrite clearbit_spec', ldiff_spec, pow2_bits_eqb.
Qed.
Lemma clearbit_iff : forall a n m,
(clearbit a n).[m] = true <-> a.[m] = true /\ n~=m.
Proof.
intros. rewrite clearbit_eqb, andb_true_iff, <- eqb_eq.
now rewrite negb_true_iff, not_true_iff_false.
Qed.
Lemma clearbit_eq : forall a n, (clearbit a n).[n] = false.
Proof.
intros. rewrite clearbit_eqb, (proj2 (eqb_eq _ _) (eq_refl n)).
apply andb_false_r.
Qed.
Lemma clearbit_neq : forall a n m, n~=m ->
(clearbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite clearbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. rewrite H.
apply andb_true_r.
Qed.
(** Shifts of bitwise operations *)
Lemma shiftl_lxor : forall a b n,
(lxor a b) << n == lxor (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', lxor_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_lxor : forall a b n,
(lxor a b) >> n == lxor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', lxor_spec.
Qed.
Lemma shiftl_land : forall a b n,
(land a b) << n == land (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', land_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_land : forall a b n,
(land a b) >> n == land (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', land_spec.
Qed.
Lemma shiftl_lor : forall a b n,
(lor a b) << n == lor (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', lor_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_lor : forall a b n,
(lor a b) >> n == lor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', lor_spec.
Qed.
Lemma shiftl_ldiff : forall a b n,
(ldiff a b) << n == ldiff (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', ldiff_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_ldiff : forall a b n,
(ldiff a b) >> n == ldiff (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', ldiff_spec.
Qed.
(** We cannot have a function complementing all bits of a number,
otherwise it would have an infinity of bit 1. Nonetheless,
we can design a bounded complement *)
Definition ones n := P (1 << n).
Definition lnot a n := lxor a (ones n).
Instance ones_wd : Proper (eq==>eq) ones.
Proof. unfold ones. solve_proper. Qed.
Instance lnot_wd : Proper (eq==>eq==>eq) lnot.
Proof. unfold lnot. solve_proper. Qed.
Lemma ones_equiv : forall n, ones n == P (2^n).
Proof.
intros; unfold ones; now rewrite shiftl_1_l.
Qed.
Lemma ones_add : forall n m, ones (m+n) == 2^m * ones n + ones m.
Proof.
intros n m. rewrite !ones_equiv.
rewrite <- !sub_1_r, mul_sub_distr_l, mul_1_r, <- pow_add_r.
rewrite add_sub_assoc, sub_add. reflexivity.
apply pow_le_mono_r. order'.
rewrite <- (add_0_r m) at 1. apply add_le_mono_l, le_0_l.
rewrite <- (pow_0_r 2). apply pow_le_mono_r. order'. apply le_0_l.
Qed.
Lemma ones_div_pow2 : forall n m, m<=n -> ones n / 2^m == ones (n-m).
Proof.
intros n m H. symmetry. apply div_unique with (ones m).
rewrite ones_equiv.
apply le_succ_l. rewrite succ_pred; order_nz.
rewrite <- (sub_add m n H) at 1. rewrite (add_comm _ m).
apply ones_add.
Qed.
Lemma ones_mod_pow2 : forall n m, m<=n -> (ones n) mod (2^m) == ones m.
Proof.
intros n m H. symmetry. apply mod_unique with (ones (n-m)).
rewrite ones_equiv.
apply le_succ_l. rewrite succ_pred; order_nz.
rewrite <- (sub_add m n H) at 1. rewrite (add_comm _ m).
apply ones_add.
Qed.
Lemma ones_spec_low : forall n m, m<n -> (ones n).[m] = true.
Proof.
intros. apply testbit_true. rewrite ones_div_pow2 by order.
rewrite <- (pow_1_r 2). rewrite ones_mod_pow2.
rewrite ones_equiv. now nzsimpl'.
apply le_add_le_sub_r. nzsimpl. now apply le_succ_l.
Qed.
Lemma ones_spec_high : forall n m, n<=m -> (ones n).[m] = false.
Proof.
intros.
destruct (eq_0_gt_0_cases n) as [EQ|LT]; rewrite ones_equiv.
now rewrite EQ, pow_0_r, one_succ, pred_succ, bits_0.
apply bits_above_log2.
rewrite log2_pred_pow2; trivial. rewrite <-le_succ_l, succ_pred; order.
Qed.
Lemma ones_spec_iff : forall n m, (ones n).[m] = true <-> m<n.
Proof.
intros. split. intros H.
apply lt_nge. intro H'. apply ones_spec_high in H'.
rewrite H in H'; discriminate.
apply ones_spec_low.
Qed.
Lemma lnot_spec_low : forall a n m, m<n ->
(lnot a n).[m] = negb a.[m].
Proof.
intros. unfold lnot. now rewrite lxor_spec, ones_spec_low.
Qed.
Lemma lnot_spec_high : forall a n m, n<=m ->
(lnot a n).[m] = a.[m].
Proof.
intros. unfold lnot. now rewrite lxor_spec, ones_spec_high, xorb_false_r.
Qed.
Lemma lnot_involutive : forall a n, lnot (lnot a n) n == a.
Proof.
intros a n. bitwise.
destruct (le_gt_cases n m).
now rewrite 2 lnot_spec_high.
now rewrite 2 lnot_spec_low, negb_involutive.
Qed.
Lemma lnot_0_l : forall n, lnot 0 n == ones n.
Proof.
intros. unfold lnot. apply lxor_0_l.
Qed.
Lemma lnot_ones : forall n, lnot (ones n) n == 0.
Proof.
intros. unfold lnot. apply lxor_nilpotent.
Qed.
(** Bounded complement and other operations *)
Lemma lor_ones_low : forall a n, log2 a < n ->
lor a (ones n) == ones n.
Proof.
intros a n H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, orb_true_r.
Qed.
Lemma land_ones : forall a n, land a (ones n) == a mod 2^n.
Proof.
intros a n. bitwise. destruct (le_gt_cases n m).
now rewrite ones_spec_high, mod_pow2_bits_high, andb_false_r.
now rewrite ones_spec_low, mod_pow2_bits_low, andb_true_r.
Qed.
Lemma land_ones_low : forall a n, log2 a < n ->
land a (ones n) == a.
Proof.
intros; rewrite land_ones. apply mod_small.
apply log2_lt_cancel. rewrite log2_pow2; trivial using le_0_l.
Qed.
Lemma ldiff_ones_r : forall a n,
ldiff a (ones n) == (a >> n) << n.
Proof.
intros a n. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, shiftl_spec_high', shiftr_spec'; trivial.
rewrite sub_add; trivial. apply andb_true_r.
now rewrite ones_spec_low, shiftl_spec_low, andb_false_r.
Qed.
Lemma ldiff_ones_r_low : forall a n, log2 a < n ->
ldiff a (ones n) == 0.
Proof.
intros a n H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, andb_false_r.
Qed.
Lemma ldiff_ones_l_low : forall a n, log2 a < n ->
ldiff (ones n) a == lnot a n.
Proof.
intros a n H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, lnot_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, lnot_spec_low.
Qed.
Lemma lor_lnot_diag : forall a n,
lor a (lnot a n) == lor a (ones n).
Proof.
intros a n. bitwise.
destruct (le_gt_cases n m).
rewrite lnot_spec_high, ones_spec_high; trivial. now destruct a.[m].
rewrite lnot_spec_low, ones_spec_low; trivial. now destruct a.[m].
Qed.
Lemma lor_lnot_diag_low : forall a n, log2 a < n ->
lor a (lnot a n) == ones n.
Proof.
intros a n H. now rewrite lor_lnot_diag, lor_ones_low.
Qed.
Lemma land_lnot_diag : forall a n,
land a (lnot a n) == ldiff a (ones n).
Proof.
intros a n. bitwise.
destruct (le_gt_cases n m).
rewrite lnot_spec_high, ones_spec_high; trivial. now destruct a.[m].
rewrite lnot_spec_low, ones_spec_low; trivial. now destruct a.[m].
Qed.
Lemma land_lnot_diag_low : forall a n, log2 a < n ->
land a (lnot a n) == 0.
Proof.
intros. now rewrite land_lnot_diag, ldiff_ones_r_low.
Qed.
Lemma lnot_lor_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (lor a b) n == land (lnot a n) (lnot b n).
Proof.
intros a b n Ha Hb. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lor_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, lor_spec, negb_orb.
Qed.
Lemma lnot_land_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (land a b) n == lor (lnot a n) (lnot b n).
Proof.
intros a b n Ha Hb. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, land_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, land_spec, negb_andb.
Qed.
Lemma ldiff_land_low : forall a b n, log2 a < n ->
ldiff a b == land a (lnot b n).
Proof.
intros a b n Ha. bitwise. destruct (le_gt_cases n m).
rewrite (bits_above_log2 a m). trivial.
now apply lt_le_trans with n.
rewrite !lnot_spec_low; trivial.
Qed.
Lemma lnot_ldiff_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (ldiff a b) n == lor (lnot a n) b.
Proof.
intros a b n Ha Hb. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, ldiff_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, ldiff_spec, negb_andb, negb_involutive.
Qed.
Lemma lxor_lnot_lnot : forall a b n,
lxor (lnot a n) (lnot b n) == lxor a b.
Proof.
intros a b n. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high; trivial.
rewrite !lnot_spec_low, xorb_negb_negb; trivial.
Qed.
Lemma lnot_lxor_l : forall a b n,
lnot (lxor a b) n == lxor (lnot a n) b.
Proof.
intros a b n. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lxor_spec; trivial.
rewrite !lnot_spec_low, lxor_spec, negb_xorb_l; trivial.
Qed.
Lemma lnot_lxor_r : forall a b n,
lnot (lxor a b) n == lxor a (lnot b n).
Proof.
intros a b n. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lxor_spec; trivial.
rewrite !lnot_spec_low, lxor_spec, negb_xorb_r; trivial.
Qed.
Lemma lxor_lor : forall a b, land a b == 0 ->
lxor a b == lor a b.
Proof.
intros a b H. bitwise.
assert (a.[m] && b.[m] = false)
by now rewrite <- land_spec, H, bits_0.
now destruct a.[m], b.[m].
Qed.
(** Bitwise operations and log2 *)
Lemma log2_bits_unique : forall a n,
a.[n] = true ->
(forall m, n<m -> a.[m] = false) ->
log2 a == n.
Proof.
intros a n H H'.
destruct (eq_0_gt_0_cases a) as [Ha|Ha].
now rewrite Ha, bits_0 in H.
apply le_antisymm; apply le_ngt; intros LT.
specialize (H' _ LT). now rewrite bit_log2 in H' by order.
now rewrite bits_above_log2 in H by order.
Qed.
Lemma log2_shiftr : forall a n, log2 (a >> n) == log2 a - n.
Proof.
intros a n.
destruct (eq_0_gt_0_cases a) as [Ha|Ha].
now rewrite Ha, shiftr_0_l, log2_nonpos, sub_0_l by order.
destruct (lt_ge_cases (log2 a) n).
rewrite shiftr_eq_0, log2_nonpos by order.
symmetry. rewrite sub_0_le; order.
apply log2_bits_unique.
now rewrite shiftr_spec', sub_add, bit_log2 by order.
intros m Hm.
rewrite shiftr_spec'; trivial. apply bits_above_log2; try order.
now apply lt_sub_lt_add_r.
Qed.
Lemma log2_shiftl : forall a n, a~=0 -> log2 (a << n) == log2 a + n.
Proof.
intros a n Ha.
rewrite shiftl_mul_pow2, add_comm by trivial.
apply log2_mul_pow2. generalize (le_0_l a); order. apply le_0_l.
Qed.
Lemma log2_lor : forall a b,
log2 (lor a b) == max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (lor a b) == log2 b).
intros a b H.
destruct (eq_0_gt_0_cases a) as [Ha|Ha]. now rewrite Ha, lor_0_l.
apply log2_bits_unique.
now rewrite lor_spec, bit_log2, orb_true_r by order.
intros m Hm. assert (H' := log2_le_mono _ _ H).
now rewrite lor_spec, 2 bits_above_log2 by order.
(* main *)
intros a b. destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono.
now apply AUX.
rewrite max_l by now apply log2_le_mono.
rewrite lor_comm. now apply AUX.
Qed.
Lemma log2_land : forall a b,
log2 (land a b) <= min (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (land a b) <= log2 a).
intros a b H.
apply le_ngt. intros H'.
destruct (eq_decidable (land a b) 0) as [EQ|NEQ].
rewrite EQ in H'. apply log2_lt_cancel in H'. generalize (le_0_l a); order.
generalize (bit_log2 (land a b) NEQ).
now rewrite land_spec, bits_above_log2.
(* main *)
intros a b.
destruct (le_ge_cases a b) as [H|H].
rewrite min_l by now apply log2_le_mono. now apply AUX.
rewrite min_r by now apply log2_le_mono. rewrite land_comm. now apply AUX.
Qed.
Lemma log2_lxor : forall a b,
log2 (lxor a b) <= max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (lxor a b) <= log2 b).
intros a b H.
apply le_ngt. intros H'.
destruct (eq_decidable (lxor a b) 0) as [EQ|NEQ].
rewrite EQ in H'. apply log2_lt_cancel in H'. generalize (le_0_l a); order.
generalize (bit_log2 (lxor a b) NEQ).
rewrite lxor_spec, 2 bits_above_log2; try order. discriminate.
apply le_lt_trans with (log2 b); trivial. now apply log2_le_mono.
(* main *)
intros a b.
destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono. now apply AUX.
rewrite max_l by now apply log2_le_mono. rewrite lxor_comm. now apply AUX.
Qed.
(** Bitwise operations and arithmetical operations *)
Local Notation xor3 a b c := (xorb (xorb a b) c).
Local Notation lxor3 a b c := (lxor (lxor a b) c).
Local Notation nextcarry a b c := ((a&&b) || (c && (a||b))).
Local Notation lnextcarry a b c := (lor (land a b) (land c (lor a b))).
Lemma add_bit0 : forall a b, (a+b).[0] = xorb a.[0] b.[0].
Proof.
intros. now rewrite !bit0_odd, odd_add.
Qed.
Lemma add3_bit0 : forall a b c,
(a+b+c).[0] = xor3 a.[0] b.[0] c.[0].
Proof.
intros. now rewrite !add_bit0.
Qed.
Lemma add3_bits_div2 : forall (a0 b0 c0 : bool),
(a0 + b0 + c0)/2 == nextcarry a0 b0 c0.
Proof.
assert (H : 1+1 == 2) by now nzsimpl'.
intros [|] [|] [|]; simpl; rewrite ?add_0_l, ?add_0_r, ?H;
(apply div_same; order') || (apply div_small; order') || idtac.
symmetry. apply div_unique with 1. order'. now nzsimpl'.
Qed.
Lemma add_carry_div2 : forall a b (c0:bool),
(a + b + c0)/2 == a/2 + b/2 + nextcarry a.[0] b.[0] c0.
Proof.
intros.
rewrite <- add3_bits_div2.
rewrite (add_comm ((a/2)+_)).
rewrite <- div_add by order'.
f_equiv.
rewrite <- !div2_div, mul_comm, mul_add_distr_l.
rewrite (div2_odd a), <- bit0_odd at 1. fold (b2n a.[0]).
rewrite (div2_odd b), <- bit0_odd at 1. fold (b2n b.[0]).
rewrite add_shuffle1.
rewrite <-(add_assoc _ _ c0). apply add_comm.
Qed.
(** The main result concerning addition: we express the bits of the sum
in term of bits of [a] and [b] and of some carry stream which is also
recursively determined by another equation.
*)
Lemma add_carry_bits : forall a b (c0:bool), exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros a b c0.
(* induction over some n such that [a<2^n] and [b<2^n] *)
set (n:=max a b).
assert (Ha : a<2^n).
apply lt_le_trans with (2^a). apply pow_gt_lin_r, lt_1_2.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases a b); [rewrite max_r|rewrite max_l]; order'.
assert (Hb : b<2^n).
apply lt_le_trans with (2^b). apply pow_gt_lin_r, lt_1_2.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases a b); [rewrite max_r|rewrite max_l]; order'.
clearbody n.
revert a b c0 Ha Hb. induct n.
(*base*)
intros a b c0. rewrite !pow_0_r, !one_succ, !lt_succ_r. intros Ha Hb.
exists c0.
setoid_replace a with 0 by (generalize (le_0_l a); order').
setoid_replace b with 0 by (generalize (le_0_l b); order').
rewrite !add_0_l, !lxor_0_l, !lor_0_r, !land_0_r, !lor_0_r.
rewrite b2n_div2, b2n_bit0; now repeat split.
(*step*)
intros n IH a b c0 Ha Hb.
set (c1:=nextcarry a.[0] b.[0] c0).
destruct (IH (a/2) (b/2) c1) as (c & IH1 & IH2 & Hc); clear IH.
apply div_lt_upper_bound; trivial. order'. now rewrite <- pow_succ_r'.
apply div_lt_upper_bound; trivial. order'. now rewrite <- pow_succ_r'.
exists (c0 + 2*c). repeat split.
(* - add *)
bitwise.
destruct (zero_or_succ m) as [EQ|[m' EQ]]; rewrite EQ; clear EQ.
now rewrite add_b2n_double_bit0, add3_bit0, b2n_bit0.
rewrite <- !div2_bits, <- 2 lxor_spec.
f_equiv.
rewrite add_b2n_double_div2, <- IH1. apply add_carry_div2.
(* - carry *)
rewrite add_b2n_double_div2.
bitwise.
destruct (zero_or_succ m) as [EQ|[m' EQ]]; rewrite EQ; clear EQ.
now rewrite add_b2n_double_bit0.
rewrite <- !div2_bits, IH2. autorewrite with bitwise.
now rewrite add_b2n_double_div2.
(* - carry0 *)
apply add_b2n_double_bit0.
Qed.
(** Particular case : the second bit of an addition *)
Lemma add_bit1 : forall a b,
(a+b).[1] = xor3 a.[1] b.[1] (a.[0] && b.[0]).
Proof.
intros a b.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
autorewrite with bitwise. f_equal.
rewrite one_succ, <- div2_bits, EQ2.
autorewrite with bitwise.
rewrite Hc. simpl. apply orb_false_r.
Qed.
(** In an addition, there will be no carries iff there is
no common bits in the numbers to add *)
Lemma nocarry_equiv : forall a b c,
c/2 == lnextcarry a b c -> c.[0] = false ->
(c == 0 <-> land a b == 0).
Proof.
intros a b c H H'.
split. intros EQ; rewrite EQ in *.
rewrite div_0_l in H by order'.
symmetry in H. now apply lor_eq_0_l in H.
intros EQ. rewrite EQ, lor_0_l in H.
apply bits_inj_0.
induct n. trivial.
intros n IH.
rewrite <- div2_bits, H.
autorewrite with bitwise.
now rewrite IH.
Qed.
(** When there is no common bits, the addition is just a xor *)
Lemma add_nocarry_lxor : forall a b, land a b == 0 ->
a+b == lxor a b.
Proof.
intros a b H.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
apply (nocarry_equiv a b c) in H; trivial.
rewrite H. now rewrite lxor_0_r.
Qed.
(** A null [ldiff] implies being smaller *)
Lemma ldiff_le : forall a b, ldiff a b == 0 -> a <= b.
Proof.
cut (forall n a b, a < 2^n -> ldiff a b == 0 -> a <= b).
intros H a b. apply (H a), pow_gt_lin_r; order'.
induct n.
intros a b Ha _. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
assert (Ha' : a == 0) by (generalize (le_0_l a); order').
rewrite Ha'. apply le_0_l.
intros n IH a b Ha H.
assert (NEQ : 2 ~= 0) by order'.
rewrite (div_mod a 2 NEQ), (div_mod b 2 NEQ).
apply add_le_mono.
apply mul_le_mono_l.
apply IH.
apply div_lt_upper_bound; trivial. now rewrite <- pow_succ_r'.
rewrite <- (pow_1_r 2), <- 2 shiftr_div_pow2.
now rewrite <- shiftr_ldiff, H, shiftr_div_pow2, pow_1_r, div_0_l.
rewrite <- 2 bit0_mod.
apply bits_inj_iff in H. specialize (H 0).
rewrite ldiff_spec, bits_0 in H.
destruct a.[0], b.[0]; try discriminate; simpl; order'.
Qed.
(** Subtraction can be a ldiff when the opposite ldiff is null. *)
Lemma sub_nocarry_ldiff : forall a b, ldiff b a == 0 ->
a-b == ldiff a b.
Proof.
intros a b H.
apply add_cancel_r with b.
rewrite sub_add.
symmetry.
rewrite add_nocarry_lxor.
bitwise.
apply bits_inj_iff in H. specialize (H m).
rewrite ldiff_spec, bits_0 in H.
now destruct a.[m], b.[m].
apply land_ldiff.
now apply ldiff_le.
Qed.
(** We can express lnot in term of subtraction *)
Lemma add_lnot_diag_low : forall a n, log2 a < n ->
a + lnot a n == ones n.
Proof.
intros a n H.
assert (H' := land_lnot_diag_low a n H).
rewrite add_nocarry_lxor, lxor_lor by trivial.
now apply lor_lnot_diag_low.
Qed.
Lemma lnot_sub_low : forall a n, log2 a < n ->
lnot a n == ones n - a.
Proof.
intros a n H.
now rewrite <- (add_lnot_diag_low a n H), add_comm, add_sub.
Qed.
(** Adding numbers with no common bits cannot lead to a much bigger number *)
Lemma add_nocarry_lt_pow2 : forall a b n, land a b == 0 ->
a < 2^n -> b < 2^n -> a+b < 2^n.
Proof.
intros a b n H Ha Hb.
rewrite add_nocarry_lxor by trivial.
apply div_small_iff. order_nz.
rewrite <- shiftr_div_pow2, shiftr_lxor, !shiftr_div_pow2.
rewrite 2 div_small by trivial.
apply lxor_0_l.
Qed.
Lemma add_nocarry_mod_lt_pow2 : forall a b n, land a b == 0 ->
a mod 2^n + b mod 2^n < 2^n.
Proof.
intros a b n H.
apply add_nocarry_lt_pow2.
bitwise.
destruct (le_gt_cases n m).
now rewrite mod_pow2_bits_high.
now rewrite !mod_pow2_bits_low, <- land_spec, H, bits_0.
apply mod_upper_bound; order_nz.
apply mod_upper_bound; order_nz.
Qed.
End NBitsProp.
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// materials, including for any direct, or any indirect,
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// PART OF THIS FILE AT ALL TIMES.
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level bank machine block. A structural block instantiating the configured
// individual bank machines, and a common block that computes various items shared
// by all bank machines.
`timescale 1ps/1ps
module mig_7series_v1_9_bank_mach #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter LOW_IDLE_CNT = 1,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCS_PER_RANK = 1,
parameter nOP_WAIT = 0,
parameter nRAS = 20,
parameter nRCD = 5,
parameter nRFC = 44,
parameter nRTP = 4,
parameter CKE_ODT_AUX = "FALSE", //Parameter to turn on/off the aux_out signal
parameter nRP = 10,
parameter nSLOTS = 2,
parameter nWR = 6,
parameter nXSDLL = 512,
parameter ORDERING = "NORM",
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010,
parameter tZQCS = 64
)
(/*AUTOARG*/
// Outputs
output accept, // From bank_common0 of bank_common.v
output accept_ns, // From bank_common0 of bank_common.v
output [BM_CNT_WIDTH-1:0] bank_mach_next, // From bank_common0 of bank_common.v
output [ROW_WIDTH-1:0] col_a, // From arb_mux0 of arb_mux.v
output [BANK_WIDTH-1:0] col_ba, // From arb_mux0 of arb_mux.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_mux0 of arb_mux.v
output col_periodic_rd, // From arb_mux0 of arb_mux.v
output [RANK_WIDTH-1:0] col_ra, // From arb_mux0 of arb_mux.v
output col_rmw, // From arb_mux0 of arb_mux.v
output col_rd_wr,
output [ROW_WIDTH-1:0] col_row, // From arb_mux0 of arb_mux.v
output col_size, // From arb_mux0 of arb_mux.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_mux0 of arb_mux.v
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output [5:0] mc_data_offset,
output [5:0] mc_data_offset_1,
output [5:0] mc_data_offset_2,
output [1:0] mc_cas_slot,
output insert_maint_r1, // From arb_mux0 of arb_mux.v
output maint_wip_r, // From bank_common0 of bank_common.v
output wire [nBANK_MACHS-1:0] sending_row,
output wire [nBANK_MACHS-1:0] sending_col,
output wire sent_col,
output wire sent_col_r,
output periodic_rd_ack_r,
output wire [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
output wire [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r,
output wire [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
output wire [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
output idle,
// Inputs
input [BANK_WIDTH-1:0] bank, // To bank0 of bank_cntrl.v
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input clk, // To bank0 of bank_cntrl.v, ...
input [2:0] cmd, // To bank0 of bank_cntrl.v, ...
input [COL_WIDTH-1:0] col, // To bank0 of bank_cntrl.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr,// To bank0 of bank_cntrl.v
input init_calib_complete, // To bank_common0 of bank_common.v
input phy_rddata_valid, // To bank0 of bank_cntrl.v
input dq_busy_data, // To bank0 of bank_cntrl.v
input hi_priority, // To bank0 of bank_cntrl.v, ...
input [RANKS-1:0] inhbt_act_faw_r, // To bank0 of bank_cntrl.v
input [RANKS-1:0] inhbt_rd, // To bank0 of bank_cntrl.v
input [RANKS-1:0] inhbt_wr, // To bank0 of bank_cntrl.v
input [RANK_WIDTH-1:0] maint_rank_r, // To bank0 of bank_cntrl.v, ...
input maint_req_r, // To bank0 of bank_cntrl.v, ...
input maint_zq_r, // To bank0 of bank_cntrl.v, ...
input maint_sre_r, // To bank0 of bank_cntrl.v, ...
input maint_srx_r, // To bank0 of bank_cntrl.v, ...
input periodic_rd_r, // To bank_common0 of bank_common.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r, // To bank0 of bank_cntrl.v
input phy_mc_ctl_full,
input phy_mc_cmd_full,
input phy_mc_data_full,
input [RANK_WIDTH-1:0] rank, // To bank0 of bank_cntrl.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr, // To bank0 of bank_cntrl.v
input rd_rmw, // To bank0 of bank_cntrl.v
input [ROW_WIDTH-1:0] row, // To bank0 of bank_cntrl.v
input rst, // To bank0 of bank_cntrl.v, ...
input size, // To bank0 of bank_cntrl.v
input [7:0] slot_0_present, // To bank_common0 of bank_common.v, ...
input [7:0] slot_1_present, // To bank_common0 of bank_common.v, ...
input use_addr
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam RANK_VECT_INDX = (nBANK_MACHS *RANK_WIDTH) - 1;
localparam BANK_VECT_INDX = (nBANK_MACHS * BANK_WIDTH) - 1;
localparam ROW_VECT_INDX = (nBANK_MACHS * ROW_WIDTH) - 1;
localparam DATA_BUF_ADDR_VECT_INDX = (nBANK_MACHS * DATA_BUF_ADDR_WIDTH) - 1;
localparam nRAS_CLKS = (nCK_PER_CLK == 1) ? nRAS : (nCK_PER_CLK == 2) ? ((nRAS/2) + (nRAS % 2)) : ((nRAS/4) + ((nRAS%4) ? 1 : 0));
localparam nWTP = CWL + ((BURST_MODE == "4") ? 2 : 4) + nWR;
// Unless 2T mode, add one to nWTP_CLKS for 2:1 mode. This accounts for loss of
// one DRAM CK due to column command to row command fixed offset. In 2T mode,
// Add the remainder. In 4:1 mode, the fixed offset is -2. Add 2 unless in 2T
// mode, in which case we add 1 if the remainder exceeds the fixed offset.
localparam nWTP_CLKS = (nCK_PER_CLK == 1)
? nWTP :
(nCK_PER_CLK == 2)
? (nWTP/2) + ((ADDR_CMD_MODE == "2T") ? nWTP%2 : 1) :
(nWTP/4) + ((ADDR_CMD_MODE == "2T") ? (nWTP%4 > 2 ? 2 : 1) : 2);
localparam RAS_TIMER_WIDTH = clogb2(((nRAS_CLKS > nWTP_CLKS)
? nRAS_CLKS
: nWTP_CLKS) - 1);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire accept_internal_r; // From bank_common0 of bank_common.v
wire accept_req; // From bank_common0 of bank_common.v
wire adv_order_q; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] idle_cnt; // From bank_common0 of bank_common.v
wire insert_maint_r; // From bank_common0 of bank_common.v
wire low_idle_cnt_r; // From bank_common0 of bank_common.v
wire maint_idle; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] order_cnt; // From bank_common0 of bank_common.v
wire periodic_rd_insert; // From bank_common0 of bank_common.v
wire [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // From bank_common0 of bank_common.v
wire sent_row; // From arb_mux0 of arb_mux.v
wire was_priority; // From bank_common0 of bank_common.v
wire was_wr; // From bank_common0 of bank_common.v
// End of automatics
wire [RANK_WIDTH-1:0] rnk_config;
wire rnk_config_strobe;
wire rnk_config_kill_rts_col;
wire rnk_config_valid_r;
wire [nBANK_MACHS-1:0] rts_row;
wire [nBANK_MACHS-1:0] rts_col;
wire [nBANK_MACHS-1:0] rts_pre;
wire [nBANK_MACHS-1:0] col_rdy_wr;
wire [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] sending_pre;
wire [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r;
wire [nBANK_MACHS-1:0] req_size_r;
wire [RANK_VECT_INDX:0] req_rank_r;
wire [BANK_VECT_INDX:0] req_bank_r;
wire [ROW_VECT_INDX:0] req_row_r;
wire [ROW_VECT_INDX:0] col_addr;
wire [nBANK_MACHS-1:0] req_periodic_rd_r;
wire [nBANK_MACHS-1:0] req_wr_r;
wire [nBANK_MACHS-1:0] rd_wr_r;
wire [nBANK_MACHS-1:0] req_ras;
wire [nBANK_MACHS-1:0] req_cas;
wire [ROW_VECT_INDX:0] row_addr;
wire [nBANK_MACHS-1:0] row_cmd_wr;
wire [nBANK_MACHS-1:0] demand_priority;
wire [nBANK_MACHS-1:0] demand_act_priority;
wire [nBANK_MACHS-1:0] idle_ns;
wire [nBANK_MACHS-1:0] rb_hit_busy_r;
wire [nBANK_MACHS-1:0] bm_end;
wire [nBANK_MACHS-1:0] passing_open_bank;
wire [nBANK_MACHS-1:0] ordered_r;
wire [nBANK_MACHS-1:0] ordered_issued;
wire [nBANK_MACHS-1:0] rb_hit_busy_ns;
wire [nBANK_MACHS-1:0] maint_hit;
wire [nBANK_MACHS-1:0] idle_r;
wire [nBANK_MACHS-1:0] head_r;
wire [nBANK_MACHS-1:0] start_rcd;
wire [nBANK_MACHS-1:0] end_rtp;
wire [nBANK_MACHS-1:0] op_exit_req;
wire [nBANK_MACHS-1:0] op_exit_grant;
wire [nBANK_MACHS-1:0] start_pre_wait;
wire [(RAS_TIMER_WIDTH*nBANK_MACHS)-1:0] ras_timer_ns;
genvar ID;
generate for (ID=0; ID<nBANK_MACHS; ID=ID+1) begin:bank_cntrl
mig_7series_v1_9_bank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRCD (nRCD),
.nRTP (nRTP),
.nRP (nRP),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank0
(.demand_priority (demand_priority[ID]),
.demand_priority_in ({2{demand_priority}}),
.demand_act_priority (demand_act_priority[ID]),
.demand_act_priority_in ({2{demand_act_priority}}),
.rts_row (rts_row[ID]),
.rts_col (rts_col[ID]),
.rts_pre (rts_pre[ID]),
.col_rdy_wr (col_rdy_wr[ID]),
.rtc (rtc[ID]),
.sending_row (sending_row[ID]),
.sending_pre (sending_pre[ID]),
.sending_col (sending_col[ID]),
.req_data_buf_addr_r (req_data_buf_addr_r[(ID*DATA_BUF_ADDR_WIDTH)+:DATA_BUF_ADDR_WIDTH]),
.req_size_r (req_size_r[ID]),
.req_rank_r (req_rank_r[(ID*RANK_WIDTH)+:RANK_WIDTH]),
.req_bank_r (req_bank_r[(ID*BANK_WIDTH)+:BANK_WIDTH]),
.req_row_r (req_row_r[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.col_addr (col_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.req_wr_r (req_wr_r[ID]),
.rd_wr_r (rd_wr_r[ID]),
.req_periodic_rd_r (req_periodic_rd_r[ID]),
.req_ras (req_ras[ID]),
.req_cas (req_cas[ID]),
.row_addr (row_addr[(ID*ROW_WIDTH)+:ROW_WIDTH]),
.row_cmd_wr (row_cmd_wr[ID]),
.act_this_rank_r (act_this_rank_r[(ID*RANKS)+:RANKS]),
.wr_this_rank_r (wr_this_rank_r[(ID*RANKS)+:RANKS]),
.rd_this_rank_r (rd_this_rank_r[(ID*RANKS)+:RANKS]),
.idle_ns (idle_ns[ID]),
.rb_hit_busy_r (rb_hit_busy_r[ID]),
.bm_end (bm_end[ID]),
.bm_end_in ({2{bm_end}}),
.passing_open_bank (passing_open_bank[ID]),
.passing_open_bank_in ({2{passing_open_bank}}),
.ordered_r (ordered_r[ID]),
.ordered_issued (ordered_issued[ID]),
.rb_hit_busy_ns (rb_hit_busy_ns[ID]),
.rb_hit_busy_ns_in ({2{rb_hit_busy_ns}}),
.maint_hit (maint_hit[ID]),
.req_rank_r_in ({2{req_rank_r}}),
.idle_r (idle_r[ID]),
.head_r (head_r[ID]),
.start_rcd (start_rcd[ID]),
.start_rcd_in ({2{start_rcd}}),
.end_rtp (end_rtp[ID]),
.op_exit_req (op_exit_req[ID]),
.op_exit_grant (op_exit_grant[ID]),
.start_pre_wait (start_pre_wait[ID]),
.ras_timer_ns (ras_timer_ns[(ID*RAS_TIMER_WIDTH)+:RAS_TIMER_WIDTH]),
.ras_timer_ns_in ({2{ras_timer_ns}}),
.rank_busy_r (rank_busy_r[ID*RANKS+:RANKS]),
/*AUTOINST*/
// Inputs
.accept_internal_r (accept_internal_r),
.accept_req (accept_req),
.adv_order_q (adv_order_q),
.bank (bank[BANK_WIDTH-1:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.dq_busy_data (dq_busy_data),
.hi_priority (hi_priority),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.low_idle_cnt_r (low_idle_cnt_r),
.maint_idle (maint_idle),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rank (rank[RANK_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_rmw (rd_rmw),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.sent_col (sent_col),
.sent_row (sent_row),
.size (size),
.use_addr (use_addr),
.was_priority (was_priority),
.was_wr (was_wr));
end
endgenerate
mig_7series_v1_9_bank_common #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.LOW_IDLE_CNT (LOW_IDLE_CNT),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRFC (nRFC),
.nXSDLL (nXSDLL),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.CWL (CWL),
.tZQCS (tZQCS))
bank_common0
(.op_exit_grant (op_exit_grant[nBANK_MACHS-1:0]),
/*AUTOINST*/
// Outputs
.accept_internal_r (accept_internal_r),
.accept_ns (accept_ns),
.accept (accept),
.periodic_rd_insert (periodic_rd_insert),
.periodic_rd_ack_r (periodic_rd_ack_r),
.accept_req (accept_req),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.idle (idle),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.adv_order_q (adv_order_q),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.low_idle_cnt_r (low_idle_cnt_r),
.was_wr (was_wr),
.was_priority (was_priority),
.maint_wip_r (maint_wip_r),
.maint_idle (maint_idle),
.insert_maint_r (insert_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.idle_ns (idle_ns[nBANK_MACHS-1:0]),
.init_calib_complete (init_calib_complete),
.periodic_rd_r (periodic_rd_r),
.use_addr (use_addr),
.rb_hit_busy_r (rb_hit_busy_r[nBANK_MACHS-1:0]),
.idle_r (idle_r[nBANK_MACHS-1:0]),
.ordered_r (ordered_r[nBANK_MACHS-1:0]),
.ordered_issued (ordered_issued[nBANK_MACHS-1:0]),
.head_r (head_r[nBANK_MACHS-1:0]),
.end_rtp (end_rtp[nBANK_MACHS-1:0]),
.passing_open_bank (passing_open_bank[nBANK_MACHS-1:0]),
.op_exit_req (op_exit_req[nBANK_MACHS-1:0]),
.start_pre_wait (start_pre_wait[nBANK_MACHS-1:0]),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.maint_req_r (maint_req_r),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_hit (maint_hit[nBANK_MACHS-1:0]),
.bm_end (bm_end[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]));
mig_7series_v1_9_arb_mux #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.EVEN_CWL_2T_MODE (EVEN_CWL_2T_MODE),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_VECT_INDX (BANK_VECT_INDX),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.CS_WIDTH (CS_WIDTH),
.CL (CL),
.CWL (CWL),
.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nRAS (nRAS),
.nRCD (nRCD),
.CKE_ODT_AUX (CKE_ODT_AUX),
.nSLOTS (nSLOTS),
.nWR (nWR),
.RANKS (RANKS),
.RANK_VECT_INDX (RANK_VECT_INDX),
.RANK_WIDTH (RANK_WIDTH),
.ROW_VECT_INDX (ROW_VECT_INDX),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG))
arb_mux0
(.rts_col (rts_col[nBANK_MACHS-1:0]), // AUTOs wants to make this an input.
/*AUTOINST*/
// Outputs
.col_a (col_a[ROW_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_size (col_size),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank),
.mc_address (mc_address),
.mc_ras_n (mc_ras_n),
.mc_cas_n (mc_cas_n),
.mc_we_n (mc_we_n),
.mc_cs_n (mc_cs_n),
.mc_odt (mc_odt),
.mc_cke (mc_cke),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_cmd (mc_cmd),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_valid_r (rnk_config_valid_r),
.mc_cas_slot (mc_cas_slot),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_pre (sending_pre[nBANK_MACHS-1:0]),
.sent_col (sent_col),
.sent_col_r (sent_col_r),
.sent_row (sent_row),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.insert_maint_r1 (insert_maint_r1),
// Inputs
.init_calib_complete (init_calib_complete),
.calib_rddata_offset (calib_rddata_offset),
.calib_rddata_offset_1 (calib_rddata_offset_1),
.calib_rddata_offset_2 (calib_rddata_offset_2),
.col_addr (col_addr[ROW_VECT_INDX:0]),
.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]),
.insert_maint_r (insert_maint_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
.req_cas (req_cas[nBANK_MACHS-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
.req_ras (req_ras[nBANK_MACHS-1:0]),
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
.row_addr (row_addr[ROW_VECT_INDX:0]),
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
.rts_row (rts_row[nBANK_MACHS-1:0]),
.rtc (rtc[nBANK_MACHS-1:0]),
.rts_pre (rts_pre[nBANK_MACHS-1:0]),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.clk (clk),
.rst (rst));
endmodule // bank_mach
|
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2008 www.xilinx.com
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : serdes_n_to_1.v
//
// Description : 1-bit generic n:1 transmitter module
// Takes in n bits of data and serialises this to 1 bit
// data is transmitted LSB first
// 0, 1, 2 ......
//
// Date - revision : August 1st 2008 - v 1.0
//
// Author : NJS
//
// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement,or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrantor
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits,cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the
// essential purpose of any limited remedies herein.
//
// Copyright © 2008 Xilinx, Inc.
// All rights reserved
//
//////////////////////////////////////////////////////////////////////////////
//
`timescale 1ps/1ps
module serdes_n_to_1 (ioclk, serdesstrobe, reset, gclk, datain, iob_data_out) ;
parameter integer SF = 8 ; // Parameter to set the serdes factor 1..8
input ioclk ; // IO Clock network
input serdesstrobe ; // Parallel data capture strobe
input reset ; // Reset
input gclk ; // Global clock
input [SF-1 : 0] datain ; // Data for output
output iob_data_out ; // output data
wire cascade_di ; //
wire cascade_do ; //
wire cascade_ti ; //
wire cascade_to ; //
wire [8:0] mdatain ; //
genvar i ; // Pad out the input data bus with 0's to 8 bits to avoid errors
generate
for (i = 0 ; i <= (SF - 1) ; i = i + 1)
begin : loop0
assign mdatain[i] = datain[i] ;
end
endgenerate
generate
for (i = (SF) ; i <= 8 ; i = i + 1)
begin : loop1
assign mdatain[i] = 1'b0 ;
end
endgenerate
OSERDES2 #(
.DATA_WIDTH (SF), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE_OQ ("SDR"), // <SDR>, DDR
.DATA_RATE_OT ("SDR"), // <SDR>, DDR
.SERDES_MODE ("MASTER"), // <DEFAULT>, MASTER, SLAVE
.OUTPUT_MODE ("DIFFERENTIAL"))
oserdes_m (
.OQ (iob_data_out),
.OCE (1'b1),
.CLK0 (ioclk),
.CLK1 (1'b0),
.IOCE (serdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.D4 (mdatain[7]),
.D3 (mdatain[6]),
.D2 (mdatain[5]),
.D1 (mdatain[4]),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TRAIN (1'b0),
.TCE (1'b1),
.SHIFTIN1 (1'b1), // Dummy input in Master
.SHIFTIN2 (1'b1), // Dummy input in Master
.SHIFTIN3 (cascade_do), // Cascade output D data from slave
.SHIFTIN4 (cascade_to), // Cascade output T data from slave
.SHIFTOUT1 (cascade_di), // Cascade input D data to slave
.SHIFTOUT2 (cascade_ti), // Cascade input T data to slave
.SHIFTOUT3 (), // Dummy output in Master
.SHIFTOUT4 ()) ; // Dummy output in Master
OSERDES2 #(
.DATA_WIDTH (SF), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE_OQ ("SDR"), // <SDR>, DDR
.DATA_RATE_OT ("SDR"), // <SDR>, DDR
.SERDES_MODE ("SLAVE"), // <DEFAULT>, MASTER, SLAVE
.OUTPUT_MODE ("DIFFERENTIAL"))
oserdes_s (
.OQ (),
.OCE (1'b1),
.CLK0 (ioclk),
.CLK1 (1'b0),
.IOCE (serdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.D4 (mdatain[3]),
.D3 (mdatain[2]),
.D2 (mdatain[1]),
.D1 (mdatain[0]),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TRAIN (1'b0),
.TCE (1'b1),
.SHIFTIN1 (cascade_di), // Cascade input D from Master
.SHIFTIN2 (cascade_ti), // Cascade input T from Master
.SHIFTIN3 (1'b1), // Dummy input in Slave
.SHIFTIN4 (1'b1), // Dummy input in Slave
.SHIFTOUT1 (), // Dummy output in Slave
.SHIFTOUT2 (), // Dummy output in Slave
.SHIFTOUT3 (cascade_do), // Cascade output D data to Master
.SHIFTOUT4 (cascade_to)) ; // Cascade output T data to Master
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2008 www.xilinx.com
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : serdes_n_to_1.v
//
// Description : 1-bit generic n:1 transmitter module
// Takes in n bits of data and serialises this to 1 bit
// data is transmitted LSB first
// 0, 1, 2 ......
//
// Date - revision : August 1st 2008 - v 1.0
//
// Author : NJS
//
// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement,or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrantor
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits,cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the
// essential purpose of any limited remedies herein.
//
// Copyright © 2008 Xilinx, Inc.
// All rights reserved
//
//////////////////////////////////////////////////////////////////////////////
//
`timescale 1ps/1ps
module serdes_n_to_1 (ioclk, serdesstrobe, reset, gclk, datain, iob_data_out) ;
parameter integer SF = 8 ; // Parameter to set the serdes factor 1..8
input ioclk ; // IO Clock network
input serdesstrobe ; // Parallel data capture strobe
input reset ; // Reset
input gclk ; // Global clock
input [SF-1 : 0] datain ; // Data for output
output iob_data_out ; // output data
wire cascade_di ; //
wire cascade_do ; //
wire cascade_ti ; //
wire cascade_to ; //
wire [8:0] mdatain ; //
genvar i ; // Pad out the input data bus with 0's to 8 bits to avoid errors
generate
for (i = 0 ; i <= (SF - 1) ; i = i + 1)
begin : loop0
assign mdatain[i] = datain[i] ;
end
endgenerate
generate
for (i = (SF) ; i <= 8 ; i = i + 1)
begin : loop1
assign mdatain[i] = 1'b0 ;
end
endgenerate
OSERDES2 #(
.DATA_WIDTH (SF), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE_OQ ("SDR"), // <SDR>, DDR
.DATA_RATE_OT ("SDR"), // <SDR>, DDR
.SERDES_MODE ("MASTER"), // <DEFAULT>, MASTER, SLAVE
.OUTPUT_MODE ("DIFFERENTIAL"))
oserdes_m (
.OQ (iob_data_out),
.OCE (1'b1),
.CLK0 (ioclk),
.CLK1 (1'b0),
.IOCE (serdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.D4 (mdatain[7]),
.D3 (mdatain[6]),
.D2 (mdatain[5]),
.D1 (mdatain[4]),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TRAIN (1'b0),
.TCE (1'b1),
.SHIFTIN1 (1'b1), // Dummy input in Master
.SHIFTIN2 (1'b1), // Dummy input in Master
.SHIFTIN3 (cascade_do), // Cascade output D data from slave
.SHIFTIN4 (cascade_to), // Cascade output T data from slave
.SHIFTOUT1 (cascade_di), // Cascade input D data to slave
.SHIFTOUT2 (cascade_ti), // Cascade input T data to slave
.SHIFTOUT3 (), // Dummy output in Master
.SHIFTOUT4 ()) ; // Dummy output in Master
OSERDES2 #(
.DATA_WIDTH (SF), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE_OQ ("SDR"), // <SDR>, DDR
.DATA_RATE_OT ("SDR"), // <SDR>, DDR
.SERDES_MODE ("SLAVE"), // <DEFAULT>, MASTER, SLAVE
.OUTPUT_MODE ("DIFFERENTIAL"))
oserdes_s (
.OQ (),
.OCE (1'b1),
.CLK0 (ioclk),
.CLK1 (1'b0),
.IOCE (serdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.D4 (mdatain[3]),
.D3 (mdatain[2]),
.D2 (mdatain[1]),
.D1 (mdatain[0]),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TRAIN (1'b0),
.TCE (1'b1),
.SHIFTIN1 (cascade_di), // Cascade input D from Master
.SHIFTIN2 (cascade_ti), // Cascade input T from Master
.SHIFTIN3 (1'b1), // Dummy input in Slave
.SHIFTIN4 (1'b1), // Dummy input in Slave
.SHIFTOUT1 (), // Dummy output in Slave
.SHIFTOUT2 (), // Dummy output in Slave
.SHIFTOUT3 (cascade_do), // Cascade output D data to Master
.SHIFTOUT4 (cascade_to)) ; // Cascade output T data to Master
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2008 www.xilinx.com
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : serdes_n_to_1.v
//
// Description : 1-bit generic n:1 transmitter module
// Takes in n bits of data and serialises this to 1 bit
// data is transmitted LSB first
// 0, 1, 2 ......
//
// Date - revision : August 1st 2008 - v 1.0
//
// Author : NJS
//
// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement,or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrantor
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits,cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the
// essential purpose of any limited remedies herein.
//
// Copyright © 2008 Xilinx, Inc.
// All rights reserved
//
//////////////////////////////////////////////////////////////////////////////
//
`timescale 1ps/1ps
module serdes_n_to_1 (ioclk, serdesstrobe, reset, gclk, datain, iob_data_out) ;
parameter integer SF = 8 ; // Parameter to set the serdes factor 1..8
input ioclk ; // IO Clock network
input serdesstrobe ; // Parallel data capture strobe
input reset ; // Reset
input gclk ; // Global clock
input [SF-1 : 0] datain ; // Data for output
output iob_data_out ; // output data
wire cascade_di ; //
wire cascade_do ; //
wire cascade_ti ; //
wire cascade_to ; //
wire [8:0] mdatain ; //
genvar i ; // Pad out the input data bus with 0's to 8 bits to avoid errors
generate
for (i = 0 ; i <= (SF - 1) ; i = i + 1)
begin : loop0
assign mdatain[i] = datain[i] ;
end
endgenerate
generate
for (i = (SF) ; i <= 8 ; i = i + 1)
begin : loop1
assign mdatain[i] = 1'b0 ;
end
endgenerate
OSERDES2 #(
.DATA_WIDTH (SF), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE_OQ ("SDR"), // <SDR>, DDR
.DATA_RATE_OT ("SDR"), // <SDR>, DDR
.SERDES_MODE ("MASTER"), // <DEFAULT>, MASTER, SLAVE
.OUTPUT_MODE ("DIFFERENTIAL"))
oserdes_m (
.OQ (iob_data_out),
.OCE (1'b1),
.CLK0 (ioclk),
.CLK1 (1'b0),
.IOCE (serdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.D4 (mdatain[7]),
.D3 (mdatain[6]),
.D2 (mdatain[5]),
.D1 (mdatain[4]),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TRAIN (1'b0),
.TCE (1'b1),
.SHIFTIN1 (1'b1), // Dummy input in Master
.SHIFTIN2 (1'b1), // Dummy input in Master
.SHIFTIN3 (cascade_do), // Cascade output D data from slave
.SHIFTIN4 (cascade_to), // Cascade output T data from slave
.SHIFTOUT1 (cascade_di), // Cascade input D data to slave
.SHIFTOUT2 (cascade_ti), // Cascade input T data to slave
.SHIFTOUT3 (), // Dummy output in Master
.SHIFTOUT4 ()) ; // Dummy output in Master
OSERDES2 #(
.DATA_WIDTH (SF), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE_OQ ("SDR"), // <SDR>, DDR
.DATA_RATE_OT ("SDR"), // <SDR>, DDR
.SERDES_MODE ("SLAVE"), // <DEFAULT>, MASTER, SLAVE
.OUTPUT_MODE ("DIFFERENTIAL"))
oserdes_s (
.OQ (),
.OCE (1'b1),
.CLK0 (ioclk),
.CLK1 (1'b0),
.IOCE (serdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.D4 (mdatain[3]),
.D3 (mdatain[2]),
.D2 (mdatain[1]),
.D1 (mdatain[0]),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TRAIN (1'b0),
.TCE (1'b1),
.SHIFTIN1 (cascade_di), // Cascade input D from Master
.SHIFTIN2 (cascade_ti), // Cascade input T from Master
.SHIFTIN3 (1'b1), // Dummy input in Slave
.SHIFTIN4 (1'b1), // Dummy input in Slave
.SHIFTOUT1 (), // Dummy output in Slave
.SHIFTOUT2 (), // Dummy output in Slave
.SHIFTOUT3 (cascade_do), // Cascade output D data to Master
.SHIFTOUT4 (cascade_to)) ; // Cascade output T data to Master
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
v95 v95 ();
v01 v01 ();
v05 v05 ();
s05 s05 ();
s09 s09 ();
a23 a23 ();
s12 s12 ();
initial begin
$finish;
end
endmodule
`begin_keywords "1364-1995"
module v95;
integer signed; initial signed = 1;
endmodule
`end_keywords
`begin_keywords "1364-2001"
module v01;
integer bit; initial bit = 1;
endmodule
`end_keywords
`begin_keywords "1364-2005"
module v05;
integer final; initial final = 1;
endmodule
`end_keywords
`begin_keywords "1800-2005"
module s05;
integer global; initial global = 1;
endmodule
`end_keywords
`begin_keywords "1800-2009"
module s09;
integer soft; initial soft = 1;
endmodule
`end_keywords
`begin_keywords "1800-2012"
module s12;
final begin
$write("*-* All Finished *-*\n");
end
endmodule
`end_keywords
`begin_keywords "VAMS-2.3"
module a23;
real foo; initial foo = sqrt(2.0);
endmodule
`end_keywords
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v1_9_ddr_phy_tempmon.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Jul 25 2012
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Monitors chip temperature via the XADC and adjusts the
// stage 2 tap values as appropriate.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v1_9_ddr_phy_tempmon #
(
parameter TCQ = 100, // Register delay (simulation only)
// Temperature bands must be in order. To disable bands, set to extreme.
parameter BAND1_TEMP_MIN = 0, // Degrees C. Min=-273. Max=231
parameter BAND2_TEMP_MIN = 12, // Degrees C. Min=-273. Max=231
parameter BAND3_TEMP_MIN = 46, // Degrees C. Min=-273. Max=231
parameter BAND4_TEMP_MIN = 82, // Degrees C. Min=-273. Max=231
parameter TEMP_HYST = 5
)
(
input clk, // Fabric clock
input rst, // System reset
input calib_complete, // Calibration complete
input tempmon_sample_en, // Signal to enable sampling
input [11:0] device_temp, // Current device temperature
output tempmon_pi_f_inc, // Increment PHASER_IN taps
output tempmon_pi_f_dec, // Decrement PHASER_IN taps
output tempmon_sel_pi_incdec // Assume control of PHASER_IN taps
);
// translate hysteresis into XADC units
localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504;
// translate band boundaries into XADC units
localparam BAND1_OFFSET = ((BAND1_TEMP_MIN + 273) * 4096) / 504;
localparam BAND2_OFFSET = ((BAND2_TEMP_MIN + 273) * 4096) / 504;
localparam BAND3_OFFSET = ((BAND3_TEMP_MIN + 273) * 4096) / 504;
localparam BAND4_OFFSET = ((BAND4_TEMP_MIN + 273) * 4096) / 504;
// incorporate hysteresis into band boundaries
localparam BAND0_DEC_OFFSET =
BAND1_OFFSET - HYST_OFFSET > 0 ? BAND1_OFFSET - HYST_OFFSET : 0 ;
localparam BAND1_INC_OFFSET =
BAND1_OFFSET + HYST_OFFSET < 4096 ? BAND1_OFFSET + HYST_OFFSET : 4096 ;
localparam BAND1_DEC_OFFSET =
BAND2_OFFSET - HYST_OFFSET > 0 ? BAND2_OFFSET - HYST_OFFSET : 0 ;
localparam BAND2_INC_OFFSET =
BAND2_OFFSET + HYST_OFFSET < 4096 ? BAND2_OFFSET + HYST_OFFSET : 4096 ;
localparam BAND2_DEC_OFFSET =
BAND3_OFFSET - HYST_OFFSET > 0 ? BAND3_OFFSET - HYST_OFFSET : 0 ;
localparam BAND3_INC_OFFSET =
BAND3_OFFSET + HYST_OFFSET < 4096 ? BAND3_OFFSET + HYST_OFFSET : 4096 ;
localparam BAND3_DEC_OFFSET =
BAND4_OFFSET - HYST_OFFSET > 0 ? BAND4_OFFSET - HYST_OFFSET : 0 ;
localparam BAND4_INC_OFFSET =
BAND4_OFFSET + HYST_OFFSET < 4096 ? BAND4_OFFSET + HYST_OFFSET : 4096 ;
// Temperature sampler FSM encoding
localparam INIT = 2'b00;
localparam IDLE = 2'b01;
localparam UPDATE = 2'b10;
localparam WAIT = 2'b11;
// Temperature sampler state
reg [2:0] tempmon_state = INIT;
reg [2:0] tempmon_next_state = INIT;
// Temperature storage
reg [11:0] previous_temp = 12'b0;
// Temperature bands
reg [2:0] target_band = 3'b000;
reg [2:0] current_band = 3'b000;
// Tap count and control
reg pi_f_inc = 1'b0;
reg pi_f_dec = 1'b0;
reg sel_pi_incdec = 1'b0;
// Temperature and band comparisons
reg device_temp_lt_previous_temp = 1'b0;
reg device_temp_gt_previous_temp = 1'b0;
reg device_temp_lt_band1 = 1'b0;
reg device_temp_lt_band2 = 1'b0;
reg device_temp_lt_band3 = 1'b0;
reg device_temp_lt_band4 = 1'b0;
reg device_temp_lt_band0_dec = 1'b0;
reg device_temp_lt_band1_dec = 1'b0;
reg device_temp_lt_band2_dec = 1'b0;
reg device_temp_lt_band3_dec = 1'b0;
reg device_temp_gt_band1_inc = 1'b0;
reg device_temp_gt_band2_inc = 1'b0;
reg device_temp_gt_band3_inc = 1'b0;
reg device_temp_gt_band4_inc = 1'b0;
reg current_band_lt_target_band = 1'b0;
reg current_band_gt_target_band = 1'b0;
reg target_band_gt_1 = 1'b0;
reg target_band_gt_2 = 1'b0;
reg target_band_gt_3 = 1'b0;
reg target_band_lt_1 = 1'b0;
reg target_band_lt_2 = 1'b0;
reg target_band_lt_3 = 1'b0;
// Pass tap control signals back up to PHY
assign tempmon_pi_f_inc = pi_f_inc;
assign tempmon_pi_f_dec = pi_f_dec;
assign tempmon_sel_pi_incdec = sel_pi_incdec;
// XADC sampler state transition
always @(posedge clk)
if(rst)
tempmon_state <= #TCQ INIT;
else
tempmon_state <= #TCQ tempmon_next_state;
// XADC sampler next state transition
always @(tempmon_state or calib_complete or tempmon_sample_en) begin
tempmon_next_state = tempmon_state;
case(tempmon_state)
INIT:
if(calib_complete)
tempmon_next_state = IDLE;
IDLE:
if(tempmon_sample_en)
tempmon_next_state = UPDATE;
UPDATE:
tempmon_next_state = WAIT;
WAIT:
if(~tempmon_sample_en)
tempmon_next_state = IDLE;
default:
tempmon_next_state = INIT;
endcase
end
// Record previous temperature during update cycle
always @(posedge clk)
if((tempmon_state == INIT) || (tempmon_state == UPDATE))
previous_temp <= #TCQ device_temp;
// Update target band
always @(posedge clk) begin
// register temperature comparisons
device_temp_lt_previous_temp <= #TCQ (device_temp < previous_temp) ? 1'b1 : 1'b0;
device_temp_gt_previous_temp <= #TCQ (device_temp > previous_temp) ? 1'b1 : 1'b0;
device_temp_lt_band1 <= #TCQ (device_temp < BAND1_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band2 <= #TCQ (device_temp < BAND2_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band3 <= #TCQ (device_temp < BAND3_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band4 <= #TCQ (device_temp < BAND4_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band0_dec <= #TCQ (device_temp < BAND0_DEC_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band1_dec <= #TCQ (device_temp < BAND1_DEC_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band2_dec <= #TCQ (device_temp < BAND2_DEC_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band3_dec <= #TCQ (device_temp < BAND3_DEC_OFFSET) ? 1'b1 : 1'b0;
device_temp_gt_band1_inc <= #TCQ (device_temp > BAND1_INC_OFFSET) ? 1'b1 : 1'b0;
device_temp_gt_band2_inc <= #TCQ (device_temp > BAND2_INC_OFFSET) ? 1'b1 : 1'b0;
device_temp_gt_band3_inc <= #TCQ (device_temp > BAND3_INC_OFFSET) ? 1'b1 : 1'b0;
device_temp_gt_band4_inc <= #TCQ (device_temp > BAND4_INC_OFFSET) ? 1'b1 : 1'b0;
target_band_gt_1 <= #TCQ (target_band > 3'b001) ? 1'b1 : 1'b0;
target_band_gt_2 <= #TCQ (target_band > 3'b010) ? 1'b1 : 1'b0;
target_band_gt_3 <= #TCQ (target_band > 3'b011) ? 1'b1 : 1'b0;
target_band_lt_1 <= #TCQ (target_band < 3'b001) ? 1'b1 : 1'b0;
target_band_lt_2 <= #TCQ (target_band < 3'b010) ? 1'b1 : 1'b0;
target_band_lt_3 <= #TCQ (target_band < 3'b011) ? 1'b1 : 1'b0;
// Initialize band
if(tempmon_state == INIT) begin
if(device_temp_lt_band1)
target_band <= #TCQ 3'b000;
else if(device_temp_lt_band2)
target_band <= #TCQ 3'b001;
else if(device_temp_lt_band3)
target_band <= #TCQ 3'b010;
else if(device_temp_lt_band4)
target_band <= #TCQ 3'b011;
else
target_band <= #TCQ 3'b100;
end
// Ready to update
else if(tempmon_state == IDLE) begin
// Temperature has increased, see if it is in a new band
if(device_temp_gt_previous_temp) begin
if(device_temp_gt_band4_inc)
target_band <= #TCQ 3'b100;
else if(device_temp_gt_band3_inc && target_band_lt_3)
target_band <= #TCQ 3'b011;
else if(device_temp_gt_band2_inc && target_band_lt_2)
target_band <= #TCQ 3'b010;
else if(device_temp_gt_band1_inc && target_band_lt_1)
target_band <= #TCQ 3'b001;
end
// Temperature has decreased, see if it is in new band
else if(device_temp_lt_previous_temp) begin
if(device_temp_lt_band0_dec)
target_band <= #TCQ 3'b000;
else if(device_temp_lt_band1_dec && target_band_gt_1)
target_band <= #TCQ 3'b001;
else if(device_temp_lt_band2_dec && target_band_gt_2)
target_band <= #TCQ 3'b010;
else if(device_temp_lt_band3_dec && target_band_gt_3)
target_band <= #TCQ 3'b011;
end
end
end
// Current band
always @(posedge clk) begin
current_band_lt_target_band = (current_band < target_band) ? 1'b1 : 1'b0;
current_band_gt_target_band = (current_band > target_band) ? 1'b1 : 1'b0;
if(tempmon_state == INIT) begin
if(device_temp_lt_band1)
current_band <= #TCQ 3'b000;
else if(device_temp_lt_band2)
current_band <= #TCQ 3'b001;
else if(device_temp_lt_band3)
current_band <= #TCQ 3'b010;
else if(device_temp_lt_band4)
current_band <= #TCQ 3'b011;
else
current_band <= #TCQ 3'b100;
end
else if(tempmon_state == UPDATE) begin
if(current_band_lt_target_band)
current_band <= #TCQ current_band + 1;
else if(current_band_gt_target_band)
current_band <= #TCQ current_band - 1;
end
end
// Tap control
always @(posedge clk) begin
if(rst) begin
pi_f_inc <= #TCQ 1'b0;
pi_f_dec <= #TCQ 1'b0;
sel_pi_incdec <= #TCQ 1'b0;
end
else if(tempmon_state == UPDATE) begin
if(current_band_lt_target_band) begin
sel_pi_incdec <= #TCQ 1'b1;
pi_f_dec <= #TCQ 1'b1;
end
else if(current_band_gt_target_band) begin
sel_pi_incdec <= #TCQ 1'b1;
pi_f_inc <= #TCQ 1'b1;
end
end
else begin
pi_f_inc <= #TCQ 1'b0;
pi_f_dec <= #TCQ 1'b0;
sel_pi_incdec <= #TCQ 1'b0;
end
end
endmodule
|
(** * ImpCEvalFun: Evaluation Function for Imp *)
(* #################################### *)
(** * Evaluation Function *)
Require Import Imp.
(** Here's a first try at an evaluation function for commands,
omitting [WHILE]. *)
Fixpoint ceval_step1 (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step1 st c1 in
ceval_step1 st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step1 st c1
else ceval_step1 st c2
| WHILE b1 DO c1 END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the WHILE case as follows:
<<
| WHILE b1 DO c1 END =>
if (beval st b1)
then ceval_step1 st (c1;; WHILE b1 DO c1 END)
else st
>>
Coq doesn't accept such a definition ([Error: Cannot guess
decreasing argument of fix]) because the function we want to
define is not guaranteed to terminate. Indeed, the changed
[ceval_step1] function applied to the [loop] program from [Imp.v] would
never terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is an
invalid(!) Coq program showing what would go wrong if Coq allowed
non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become
provable (e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_step1] cannot be written in Coq -- at least not
without one additional trick... *)
(** Second try, using an extra numeric argument as a "step index" to
ensure that evaluation always terminates. *)
Fixpoint ceval_step2 (st : state) (c : com) (i : nat) : state :=
match i with
| O => empty_state
| S i' =>
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step2 st c1 i' in
ceval_step2 st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step2 st c1 i'
else ceval_step2 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then let st' := ceval_step2 st c1 i' in
ceval_step2 st' c i'
else st
end
end.
(** _Note_: It is tempting to think that the index [i] here is
counting the "number of steps of evaluation." But if you look
closely you'll see that this is not the case: for example, in the
rule for sequencing, the same [i] is passed to both recursive
calls. Understanding the exact way that [i] is treated will be
important in the proof of [ceval__ceval_step], which is given as
an exercise below. *)
(** Third try, returning an [option state] instead of just a [state]
so that we can distinguish between normal and abnormal
termination. *)
Fixpoint ceval_step3 (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c2 i'
| None => None
end
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step3 st c1 i'
else ceval_step3 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c i'
| None => None
end
else Some st
end
end.
(** We can improve the readability of this definition by introducing a
bit of auxiliary notation to hide the "plumbing" involved in
repeatedly matching against optional states. *)
Notation "'LETOPT' x <== e1 'IN' e2"
:= (match e1 with
| Some x => e2
| None => None
end)
(right associativity, at level 60).
Fixpoint ceval_step (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step st c1 i'
else ceval_step st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c i'
else Some st
end
end.
Definition test_ceval (st:state) (c:com) :=
match ceval_step st c 500 with
| None => None
| Some st => Some (st X, st Y, st Z)
end.
(* Eval compute in
(test_ceval empty_state
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)).
====>
Some (2, 0, 4) *)
(** **** Exercise: 2 stars (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y]. Make sure
your solution satisfies the test that follows. *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
(*
Example pup_to_n_1 :
test_ceval (update empty_state X 5) pup_to_n
= Some (0, 15, 0).
Proof. reflexivity. Qed.
*)
(** [] *)
(** **** Exercise: 2 stars, optional (peven) *)
(** Write a [While] program that sets [Z] to [0] if [X] is even and
sets [Z] to [1] otherwise. Use [ceval_test] to test your
program. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################ *)
(** * Equivalence of Relational and Step-Indexed Evaluation *)
(** As with arithmetic and boolean expressions, we'd hope that
the two alternative definitions of evaluation actually boil down
to the same thing. This section shows that this is the case.
Make sure you understand the statements of the theorems and can
follow the structure of the proofs. *)
Theorem ceval_step__ceval: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros c st st' H.
inversion H as [i E].
clear H.
generalize dependent st'.
generalize dependent st.
generalize dependent c.
induction i as [| i' ].
Case "i = 0 -- contradictory".
intros c st st' H. inversion H.
Case "i = S i'".
intros c st st' H.
com_cases (destruct c) SCase;
simpl in H; inversion H; subst; clear H.
SCase "SKIP". apply E_Skip.
SCase "::=". apply E_Ass. reflexivity.
SCase ";;".
destruct (ceval_step st c1 i') eqn:Heqr1.
SSCase "Evaluation of r1 terminates normally".
apply E_Seq with s.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSCase "Otherwise -- contradiction".
inversion H1.
SCase "IFB".
destruct (beval st b) eqn:Heqr.
SSCase "r = true".
apply E_IfTrue. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SSCase "r = false".
apply E_IfFalse. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SCase "WHILE". destruct (beval st b) eqn :Heqr.
SSCase "r = true".
destruct (ceval_step st c i') eqn:Heqr1.
SSSCase "r1 = Some s".
apply E_WhileLoop with s. rewrite Heqr. reflexivity.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSSCase "r1 = None".
inversion H1.
SSCase "r = false".
inversion H1.
apply E_WhileEnd.
rewrite <- Heqr. subst. reflexivity. Qed.
(** **** Exercise: 4 stars (ceval_step__ceval_inf) *)
(** Write an informal proof of [ceval_step__ceval], following the
usual template. (The template for case analysis on an inductively
defined value should look the same as for induction, except that
there is no induction hypothesis.) Make your proof communicate
the main ideas to a human reader; do not simply transcribe the
steps of the formal proof.
(* FILL IN HERE *)
[]
*)
Theorem ceval_step_more: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
induction i1 as [|i1']; intros i2 st st' c Hle Hceval.
Case "i1 = 0".
simpl in Hceval. inversion Hceval.
Case "i1 = S i1'".
destruct i2 as [|i2']. inversion Hle.
assert (Hle': i1' <= i2') by omega.
com_cases (destruct c) SCase.
SCase "SKIP".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase "::=".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase ";;".
simpl in Hceval. simpl.
destruct (ceval_step st c1 i1') eqn:Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "st1'o = None".
inversion Hceval.
SCase "IFB".
simpl in Hceval. simpl.
destruct (beval st b); apply (IHi1' i2') in Hceval; assumption.
SCase "WHILE".
simpl in Hceval. simpl.
destruct (beval st b); try assumption.
destruct (ceval_step st c i1') eqn: Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite -> Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "i1'o = None".
simpl in Hceval. inversion Hceval. Qed.
(** **** Exercise: 3 stars (ceval__ceval_step) *)
(** Finish the following proof. You'll need [ceval_step_more] in a
few places, as well as some basic facts about [<=] and [plus]. *)
Theorem ceval__ceval_step: forall c st st',
c / st || st' ->
exists i, ceval_step st c i = Some st'.
Proof.
intros c st st' Hce.
ceval_cases (induction Hce) Case.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem ceval_and_ceval_step_coincide: forall c st st',
c / st || st'
<-> exists i, ceval_step st c i = Some st'.
Proof.
intros c st st'.
split. apply ceval__ceval_step. apply ceval_step__ceval.
Qed.
(* ####################################################### *)
(** * Determinism of Evaluation (Simpler Proof) *)
(** Here's a slicker proof showing that the evaluation relation is
deterministic, using the fact that the relational and step-indexed
definition of evaluation are the same. *)
Theorem ceval_deterministic' : forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 He1 He2.
apply ceval__ceval_step in He1.
apply ceval__ceval_step in He2.
inversion He1 as [i1 E1].
inversion He2 as [i2 E2].
apply ceval_step_more with (i2 := i1 + i2) in E1.
apply ceval_step_more with (i2 := i1 + i2) in E2.
rewrite E1 in E2. inversion E2. reflexivity.
omega. omega. Qed.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import
Bool ZAxioms ZMulOrder ZPow ZDivFloor ZSgnAbs ZParity NZLog.
(** Derived properties of bitwise operations *)
Module Type ZBitsProp
(Import A : ZAxiomsSig')
(Import B : ZMulOrderProp A)
(Import C : ZParityProp A B)
(Import D : ZSgnAbsProp A B)
(Import E : ZPowProp A B C D)
(Import F : ZDivProp A B D)
(Import G : NZLog2Prop A A A B E).
Include BoolEqualityFacts A.
Ltac order_nz := try apply pow_nonzero; order'.
Ltac order_pos' := try apply abs_nonneg; order_pos.
Hint Rewrite div_0_l mod_0_l div_1_r mod_1_r : nz.
(** Some properties of power and division *)
Lemma pow_sub_r : forall a b c, a~=0 -> 0<=c<=b -> a^(b-c) == a^b / a^c.
Proof.
intros a b c Ha (H,H'). rewrite <- (sub_simpl_r b c) at 2.
rewrite pow_add_r; trivial.
rewrite div_mul. reflexivity.
now apply pow_nonzero.
now apply le_0_sub.
Qed.
Lemma pow_div_l : forall a b c, b~=0 -> 0<=c -> a mod b == 0 ->
(a/b)^c == a^c / b^c.
Proof.
intros a b c Hb Hc H. rewrite (div_mod a b Hb) at 2.
rewrite H, add_0_r, pow_mul_l, mul_comm, div_mul. reflexivity.
now apply pow_nonzero.
Qed.
(** An injection from bits [true] and [false] to numbers 1 and 0.
We declare it as a (local) coercion for shorter statements. *)
Definition b2z (b:bool) := if b then 1 else 0.
Local Coercion b2z : bool >-> t.
Instance b2z_wd : Proper (Logic.eq ==> eq) b2z := _.
Lemma exists_div2 a : exists a' (b:bool), a == 2*a' + b.
Proof.
elim (Even_or_Odd a); [intros (a',H)| intros (a',H)].
exists a'. exists false. now nzsimpl.
exists a'. exists true. now simpl.
Qed.
(** We can compact [testbit_odd_0] [testbit_even_0]
[testbit_even_succ] [testbit_odd_succ] in only two lemmas. *)
Lemma testbit_0_r a (b:bool) : testbit (2*a+b) 0 = b.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_0.
apply testbit_even_0.
Qed.
Lemma testbit_succ_r a (b:bool) n : 0<=n ->
testbit (2*a+b) (succ n) = testbit a n.
Proof.
destruct b; simpl; rewrite ?add_0_r.
now apply testbit_odd_succ.
now apply testbit_even_succ.
Qed.
(** Alternative caracterisations of [testbit] *)
(** This concise equation could have been taken as specification
for testbit in the interface, but it would have been hard to
implement with little initial knowledge about div and mod *)
Lemma testbit_spec' a n : 0<=n -> a.[n] == (a / 2^n) mod 2.
Proof.
intro Hn. revert a. apply le_ind with (4:=Hn).
solve_proper.
intros a. nzsimpl.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_0_r. apply mod_unique with a'; trivial.
left. destruct b; split; simpl; order'.
clear n Hn. intros n Hn IH a.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_succ_r, IH by trivial. f_equiv.
rewrite pow_succ_r, <- div_div by order_pos. f_equiv.
apply div_unique with b; trivial.
left. destruct b; split; simpl; order'.
Qed.
(** This caracterisation that uses only basic operations and
power was initially taken as specification for testbit.
We describe [a] as having a low part and a high part, with
the corresponding bit in the middle. This caracterisation
is moderatly complex to implement, but also moderately
usable... *)
Lemma testbit_spec a n : 0<=n ->
exists l h, 0<=l<2^n /\ a == l + (a.[n] + 2*h)*2^n.
Proof.
intro Hn. exists (a mod 2^n). exists (a / 2^n / 2). split.
apply mod_pos_bound; order_pos.
rewrite add_comm, mul_comm, (add_comm a.[n]).
rewrite (div_mod a (2^n)) at 1 by order_nz. do 2 f_equiv.
rewrite testbit_spec' by trivial. apply div_mod. order'.
Qed.
Lemma testbit_true : forall a n, 0<=n ->
(a.[n] = true <-> (a / 2^n) mod 2 == 1).
Proof.
intros a n Hn.
rewrite <- testbit_spec' by trivial.
destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_false : forall a n, 0<=n ->
(a.[n] = false <-> (a / 2^n) mod 2 == 0).
Proof.
intros a n Hn.
rewrite <- testbit_spec' by trivial.
destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_eqb : forall a n, 0<=n ->
a.[n] = eqb ((a / 2^n) mod 2) 1.
Proof.
intros a n Hn.
apply eq_true_iff_eq. now rewrite testbit_true, eqb_eq.
Qed.
(** Results about the injection [b2z] *)
Lemma b2z_inj : forall (a0 b0:bool), a0 == b0 -> a0 = b0.
Proof.
intros [|] [|]; simpl; trivial; order'.
Qed.
Lemma add_b2z_double_div2 : forall (a0:bool) a, (a0+2*a)/2 == a.
Proof.
intros a0 a. rewrite mul_comm, div_add by order'.
now rewrite div_small, add_0_l by (destruct a0; split; simpl; order').
Qed.
Lemma add_b2z_double_bit0 : forall (a0:bool) a, (a0+2*a).[0] = a0.
Proof.
intros a0 a. apply b2z_inj.
rewrite testbit_spec' by order.
nzsimpl. rewrite mul_comm, mod_add by order'.
now rewrite mod_small by (destruct a0; split; simpl; order').
Qed.
Lemma b2z_div2 : forall (a0:bool), a0/2 == 0.
Proof.
intros a0. rewrite <- (add_b2z_double_div2 a0 0). now nzsimpl.
Qed.
Lemma b2z_bit0 : forall (a0:bool), a0.[0] = a0.
Proof.
intros a0. rewrite <- (add_b2z_double_bit0 a0 0) at 2. now nzsimpl.
Qed.
(** The specification of testbit by low and high parts is complete *)
Lemma testbit_unique : forall a n (a0:bool) l h,
0<=l<2^n -> a == l + (a0 + 2*h)*2^n -> a.[n] = a0.
Proof.
intros a n a0 l h Hl EQ.
assert (0<=n).
destruct (le_gt_cases 0 n) as [Hn|Hn]; trivial.
rewrite pow_neg_r in Hl by trivial. destruct Hl; order.
apply b2z_inj. rewrite testbit_spec' by trivial.
symmetry. apply mod_unique with h.
left; destruct a0; simpl; split; order'.
symmetry. apply div_unique with l.
now left.
now rewrite add_comm, (add_comm _ a0), mul_comm.
Qed.
(** All bits of number 0 are 0 *)
Lemma bits_0 : forall n, 0.[n] = false.
Proof.
intros n.
destruct (le_gt_cases 0 n).
apply testbit_false; trivial. nzsimpl; order_nz.
now apply testbit_neg_r.
Qed.
(** For negative numbers, we are actually doing two's complement *)
Lemma bits_opp : forall a n, 0<=n -> (-a).[n] = negb (P a).[n].
Proof.
intros a n Hn.
destruct (testbit_spec (-a) n Hn) as (l & h & Hl & EQ).
fold (b2z (-a).[n]) in EQ.
apply negb_sym.
apply testbit_unique with (2^n-l-1) (-h-1).
split.
apply lt_succ_r. rewrite sub_1_r, succ_pred. now apply lt_0_sub.
apply le_succ_l. rewrite sub_1_r, succ_pred. apply le_sub_le_add_r.
rewrite <- (add_0_r (2^n)) at 1. now apply add_le_mono_l.
rewrite <- add_sub_swap, sub_1_r. f_equiv.
apply opp_inj. rewrite opp_add_distr, opp_sub_distr.
rewrite (add_comm _ l), <- add_assoc.
rewrite EQ at 1. apply add_cancel_l.
rewrite <- opp_add_distr.
rewrite <- (mul_1_l (2^n)) at 2. rewrite <- mul_add_distr_r.
rewrite <- mul_opp_l.
f_equiv.
rewrite !opp_add_distr.
rewrite <- mul_opp_r.
rewrite opp_sub_distr, opp_involutive.
rewrite (add_comm h).
rewrite mul_add_distr_l.
rewrite !add_assoc.
apply add_cancel_r.
rewrite mul_1_r.
rewrite add_comm, add_assoc, !add_opp_r, sub_1_r, two_succ, pred_succ.
destruct (-a).[n]; simpl. now rewrite sub_0_r. now nzsimpl'.
Qed.
(** All bits of number (-1) are 1 *)
Lemma bits_m1 : forall n, 0<=n -> (-1).[n] = true.
Proof.
intros. now rewrite bits_opp, one_succ, pred_succ, bits_0.
Qed.
(** Various ways to refer to the lowest bit of a number *)
Lemma bit0_odd : forall a, a.[0] = odd a.
Proof.
intros. symmetry.
destruct (exists_div2 a) as (a' & b & EQ).
rewrite EQ, testbit_0_r, add_comm, odd_add_mul_2.
destruct b; simpl; apply odd_1 || apply odd_0.
Qed.
Lemma bit0_eqb : forall a, a.[0] = eqb (a mod 2) 1.
Proof.
intros a. rewrite testbit_eqb by order. now nzsimpl.
Qed.
Lemma bit0_mod : forall a, a.[0] == a mod 2.
Proof.
intros a. rewrite testbit_spec' by order. now nzsimpl.
Qed.
(** Hence testing a bit is equivalent to shifting and testing parity *)
Lemma testbit_odd : forall a n, a.[n] = odd (a>>n).
Proof.
intros. now rewrite <- bit0_odd, shiftr_spec, add_0_l.
Qed.
(** [log2] gives the highest nonzero bit of positive numbers *)
Lemma bit_log2 : forall a, 0<a -> a.[log2 a] = true.
Proof.
intros a Ha.
assert (Ha' := log2_nonneg a).
destruct (log2_spec_alt a Ha) as (r & EQ & Hr).
rewrite EQ at 1.
rewrite testbit_true, add_comm by trivial.
rewrite <- (mul_1_l (2^log2 a)) at 1.
rewrite div_add by order_nz.
rewrite div_small; trivial.
rewrite add_0_l. apply mod_small. split; order'.
Qed.
Lemma bits_above_log2 : forall a n, 0<=a -> log2 a < n ->
a.[n] = false.
Proof.
intros a n Ha H.
assert (Hn : 0<=n).
transitivity (log2 a). apply log2_nonneg. order'.
rewrite testbit_false by trivial.
rewrite div_small. nzsimpl; order'.
split. order. apply log2_lt_cancel. now rewrite log2_pow2.
Qed.
(** Hence the number of bits of [a] is [1+log2 a]
(see [Pos.size_nat] and [Pos.size]).
*)
(** For negative numbers, things are the other ways around:
log2 gives the highest zero bit (for numbers below -1).
*)
Lemma bit_log2_neg : forall a, a < -1 -> a.[log2 (P (-a))] = false.
Proof.
intros a Ha.
rewrite <- (opp_involutive a) at 1.
rewrite bits_opp.
apply negb_false_iff.
apply bit_log2.
apply opp_lt_mono in Ha. rewrite opp_involutive in Ha.
apply lt_succ_lt_pred. now rewrite <- one_succ.
apply log2_nonneg.
Qed.
Lemma bits_above_log2_neg : forall a n, a < 0 -> log2 (P (-a)) < n ->
a.[n] = true.
Proof.
intros a n Ha H.
assert (Hn : 0<=n).
transitivity (log2 (P (-a))). apply log2_nonneg. order'.
rewrite <- (opp_involutive a), bits_opp, negb_true_iff by trivial.
apply bits_above_log2; trivial.
now rewrite <- opp_succ, opp_nonneg_nonpos, le_succ_l.
Qed.
(** Accesing a high enough bit of a number gives its sign *)
Lemma bits_iff_nonneg : forall a n, log2 (abs a) < n ->
(0<=a <-> a.[n] = false).
Proof.
intros a n Hn. split; intros H.
rewrite abs_eq in Hn; trivial. now apply bits_above_log2.
destruct (le_gt_cases 0 a); trivial.
rewrite abs_neq in Hn by order.
rewrite bits_above_log2_neg in H; try easy.
apply le_lt_trans with (log2 (-a)); trivial.
apply log2_le_mono. apply le_pred_l.
Qed.
Lemma bits_iff_nonneg' : forall a,
0<=a <-> a.[S (log2 (abs a))] = false.
Proof.
intros. apply bits_iff_nonneg. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_nonneg_ex : forall a,
0<=a <-> (exists k, forall m, k<m -> a.[m] = false).
Proof.
intros a. split.
intros Ha. exists (log2 a). intros m Hm. now apply bits_above_log2.
intros (k,Hk). destruct (le_gt_cases k (log2 (abs a))).
now apply bits_iff_nonneg', Hk, lt_succ_r.
apply (bits_iff_nonneg a (S k)).
now apply lt_succ_r, lt_le_incl.
apply Hk. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_neg : forall a n, log2 (abs a) < n ->
(a<0 <-> a.[n] = true).
Proof.
intros a n Hn.
now rewrite lt_nge, <- not_false_iff_true, (bits_iff_nonneg a n).
Qed.
Lemma bits_iff_neg' : forall a, a<0 <-> a.[S (log2 (abs a))] = true.
Proof.
intros. apply bits_iff_neg. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_neg_ex : forall a,
a<0 <-> (exists k, forall m, k<m -> a.[m] = true).
Proof.
intros a. split.
intros Ha. exists (log2 (P (-a))). intros m Hm. now apply bits_above_log2_neg.
intros (k,Hk). destruct (le_gt_cases k (log2 (abs a))).
now apply bits_iff_neg', Hk, lt_succ_r.
apply (bits_iff_neg a (S k)).
now apply lt_succ_r, lt_le_incl.
apply Hk. apply lt_succ_diag_r.
Qed.
(** Testing bits after division or multiplication by a power of two *)
Lemma div2_bits : forall a n, 0<=n -> (a/2).[n] = a.[S n].
Proof.
intros a n Hn.
apply eq_true_iff_eq. rewrite 2 testbit_true by order_pos.
rewrite pow_succ_r by trivial.
now rewrite div_div by order_pos.
Qed.
Lemma div_pow2_bits : forall a n m, 0<=n -> 0<=m -> (a/2^n).[m] = a.[m+n].
Proof.
intros a n m Hn. revert a m. apply le_ind with (4:=Hn).
solve_proper.
intros a m Hm. now nzsimpl.
clear n Hn. intros n Hn IH a m Hm. nzsimpl; trivial.
rewrite <- div_div by order_pos.
now rewrite IH, div2_bits by order_pos.
Qed.
Lemma double_bits_succ : forall a n, (2*a).[S n] = a.[n].
Proof.
intros a n.
destruct (le_gt_cases 0 n) as [Hn|Hn].
now rewrite <- div2_bits, mul_comm, div_mul by order'.
rewrite (testbit_neg_r a n Hn).
apply le_succ_l in Hn. le_elim Hn.
now rewrite testbit_neg_r.
now rewrite Hn, bit0_odd, odd_mul, odd_2.
Qed.
Lemma double_bits : forall a n, (2*a).[n] = a.[P n].
Proof.
intros a n. rewrite <- (succ_pred n) at 1. apply double_bits_succ.
Qed.
Lemma mul_pow2_bits_add : forall a n m, 0<=n -> (a*2^n).[n+m] = a.[m].
Proof.
intros a n m Hn. revert a m. apply le_ind with (4:=Hn).
solve_proper.
intros a m. now nzsimpl.
clear n Hn. intros n Hn IH a m. nzsimpl; trivial.
rewrite mul_assoc, (mul_comm _ 2), <- mul_assoc.
now rewrite double_bits_succ.
Qed.
Lemma mul_pow2_bits : forall a n m, 0<=n -> (a*2^n).[m] = a.[m-n].
Proof.
intros.
rewrite <- (add_simpl_r m n) at 1. rewrite add_sub_swap, add_comm.
now apply mul_pow2_bits_add.
Qed.
Lemma mul_pow2_bits_low : forall a n m, m<n -> (a*2^n).[m] = false.
Proof.
intros.
destruct (le_gt_cases 0 n).
rewrite mul_pow2_bits by trivial.
apply testbit_neg_r. now apply lt_sub_0.
now rewrite pow_neg_r, mul_0_r, bits_0.
Qed.
(** Selecting the low part of a number can be done by a modulo *)
Lemma mod_pow2_bits_high : forall a n m, 0<=n<=m ->
(a mod 2^n).[m] = false.
Proof.
intros a n m (Hn,H).
destruct (mod_pos_bound a (2^n)) as [LE LT]. order_pos.
le_elim LE.
apply bits_above_log2; try order.
apply lt_le_trans with n; trivial.
apply log2_lt_pow2; trivial.
now rewrite <- LE, bits_0.
Qed.
Lemma mod_pow2_bits_low : forall a n m, m<n ->
(a mod 2^n).[m] = a.[m].
Proof.
intros a n m H.
destruct (le_gt_cases 0 m) as [Hm|Hm]; [|now rewrite !testbit_neg_r].
rewrite testbit_eqb; trivial.
rewrite <- (mod_add _ (2^(P (n-m))*(a/2^n))) by order'.
rewrite <- div_add by order_nz.
rewrite (mul_comm _ 2), mul_assoc, <- pow_succ_r, succ_pred.
rewrite mul_comm, mul_assoc, <- pow_add_r, (add_comm m), sub_add; trivial.
rewrite add_comm, <- div_mod by order_nz.
symmetry. apply testbit_eqb; trivial.
apply le_0_sub; order.
now apply lt_le_pred, lt_0_sub.
Qed.
(** We now prove that having the same bits implies equality.
For that we use a notion of equality over functional
streams of bits. *)
Definition eqf (f g:t -> bool) := forall n:t, f n = g n.
Instance eqf_equiv : Equivalence eqf.
Proof.
split; congruence.
Qed.
Local Infix "===" := eqf (at level 70, no associativity).
Instance testbit_eqf : Proper (eq==>eqf) testbit.
Proof.
intros a a' Ha n. now rewrite Ha.
Qed.
(** Only zero corresponds to the always-false stream. *)
Lemma bits_inj_0 :
forall a, (forall n, a.[n] = false) -> a == 0.
Proof.
intros a H. destruct (lt_trichotomy a 0) as [Ha|[Ha|Ha]]; trivial.
apply (bits_above_log2_neg a (S (log2 (P (-a))))) in Ha.
now rewrite H in Ha.
apply lt_succ_diag_r.
apply bit_log2 in Ha. now rewrite H in Ha.
Qed.
(** If two numbers produce the same stream of bits, they are equal. *)
Lemma bits_inj : forall a b, testbit a === testbit b -> a == b.
Proof.
assert (AUX : forall n, 0<=n -> forall a b,
0<=a<2^n -> testbit a === testbit b -> a == b).
intros n Hn. apply le_ind with (4:=Hn).
solve_proper.
intros a b Ha H. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
assert (Ha' : a == 0) by (destruct Ha; order).
rewrite Ha' in *.
symmetry. apply bits_inj_0.
intros m. now rewrite <- H, bits_0.
clear n Hn. intros n Hn IH a b (Ha,Ha') H.
rewrite (div_mod a 2), (div_mod b 2) by order'.
f_equiv; [ | now rewrite <- 2 bit0_mod, H].
f_equiv.
apply IH.
split. apply div_pos; order'.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
intros m.
destruct (le_gt_cases 0 m).
rewrite 2 div2_bits by trivial. apply H.
now rewrite 2 testbit_neg_r.
intros a b H.
destruct (le_gt_cases 0 a) as [Ha|Ha].
apply (AUX a); trivial. split; trivial.
apply pow_gt_lin_r; order'.
apply succ_inj, opp_inj.
assert (0 <= - S a).
apply opp_le_mono. now rewrite opp_involutive, opp_0, le_succ_l.
apply (AUX (-(S a))); trivial. split; trivial.
apply pow_gt_lin_r; order'.
intros m. destruct (le_gt_cases 0 m).
now rewrite 2 bits_opp, 2 pred_succ, H.
now rewrite 2 testbit_neg_r.
Qed.
Lemma bits_inj_iff : forall a b, testbit a === testbit b <-> a == b.
Proof.
split. apply bits_inj. intros EQ; now rewrite EQ.
Qed.
(** In fact, checking the bits at positive indexes is enough. *)
Lemma bits_inj' : forall a b,
(forall n, 0<=n -> a.[n] = b.[n]) -> a == b.
Proof.
intros a b H. apply bits_inj.
intros n. destruct (le_gt_cases 0 n).
now apply H.
now rewrite 2 testbit_neg_r.
Qed.
Lemma bits_inj_iff' : forall a b, (forall n, 0<=n -> a.[n] = b.[n]) <-> a == b.
Proof.
split. apply bits_inj'. intros EQ n Hn; now rewrite EQ.
Qed.
Ltac bitwise := apply bits_inj'; intros ?m ?Hm; autorewrite with bitwise.
Hint Rewrite lxor_spec lor_spec land_spec ldiff_spec bits_0 : bitwise.
(** The streams of bits that correspond to a numbers are
exactly the ones which are stationary after some point. *)
Lemma are_bits : forall (f:t->bool), Proper (eq==>Logic.eq) f ->
((exists n, forall m, 0<=m -> f m = n.[m]) <->
(exists k, forall m, k<=m -> f m = f k)).
Proof.
intros f Hf. split.
intros (a,H).
destruct (le_gt_cases 0 a).
exists (S (log2 a)). intros m Hm. apply le_succ_l in Hm.
rewrite 2 H, 2 bits_above_log2; trivial using lt_succ_diag_r.
order_pos. apply le_trans with (log2 a); order_pos.
exists (S (log2 (P (-a)))). intros m Hm. apply le_succ_l in Hm.
rewrite 2 H, 2 bits_above_log2_neg; trivial using lt_succ_diag_r.
order_pos. apply le_trans with (log2 (P (-a))); order_pos.
intros (k,Hk).
destruct (lt_ge_cases k 0) as [LT|LE].
case_eq (f 0); intros H0.
exists (-1). intros m Hm. rewrite bits_m1, Hk by order.
symmetry; rewrite <- H0. apply Hk; order.
exists 0. intros m Hm. rewrite bits_0, Hk by order.
symmetry; rewrite <- H0. apply Hk; order.
revert f Hf Hk. apply le_ind with (4:=LE).
(* compat : solve_proper fails here *)
apply proper_sym_impl_iff. exact eq_sym.
clear k LE. intros k k' Hk IH f Hf H. apply IH; trivial.
now setoid_rewrite Hk.
(* /compat *)
intros f Hf H0. destruct (f 0).
exists (-1). intros m Hm. now rewrite bits_m1, H0.
exists 0. intros m Hm. now rewrite bits_0, H0.
clear k LE. intros k LE IH f Hf Hk.
destruct (IH (fun m => f (S m))) as (n, Hn).
solve_proper.
intros m Hm. apply Hk. now rewrite <- succ_le_mono.
exists (f 0 + 2*n). intros m Hm.
le_elim Hm.
rewrite <- (succ_pred m), Hn, <- div2_bits.
rewrite mul_comm, div_add, b2z_div2, add_0_l; trivial. order'.
now rewrite <- lt_succ_r, succ_pred.
now rewrite <- lt_succ_r, succ_pred.
rewrite <- Hm.
symmetry. apply add_b2z_double_bit0.
Qed.
(** * Properties of shifts *)
(** First, a unified specification for [shiftl] : the [shiftl_spec]
below (combined with [testbit_neg_r]) is equivalent to
[shiftl_spec_low] and [shiftl_spec_high]. *)
Lemma shiftl_spec : forall a n m, 0<=m -> (a << n).[m] = a.[m-n].
Proof.
intros.
destruct (le_gt_cases n m).
now apply shiftl_spec_high.
rewrite shiftl_spec_low, testbit_neg_r; trivial. now apply lt_sub_0.
Qed.
(** A shiftl by a negative number is a shiftr, and vice-versa *)
Lemma shiftr_opp_r : forall a n, a >> (-n) == a << n.
Proof.
intros. bitwise. now rewrite shiftr_spec, shiftl_spec, add_opp_r.
Qed.
Lemma shiftl_opp_r : forall a n, a << (-n) == a >> n.
Proof.
intros. bitwise. now rewrite shiftr_spec, shiftl_spec, sub_opp_r.
Qed.
(** Shifts correspond to multiplication or division by a power of two *)
Lemma shiftr_div_pow2 : forall a n, 0<=n -> a >> n == a / 2^n.
Proof.
intros. bitwise. now rewrite shiftr_spec, div_pow2_bits.
Qed.
Lemma shiftr_mul_pow2 : forall a n, n<=0 -> a >> n == a * 2^(-n).
Proof.
intros. bitwise. rewrite shiftr_spec, mul_pow2_bits; trivial.
now rewrite sub_opp_r.
now apply opp_nonneg_nonpos.
Qed.
Lemma shiftl_mul_pow2 : forall a n, 0<=n -> a << n == a * 2^n.
Proof.
intros. bitwise. now rewrite shiftl_spec, mul_pow2_bits.
Qed.
Lemma shiftl_div_pow2 : forall a n, n<=0 -> a << n == a / 2^(-n).
Proof.
intros. bitwise. rewrite shiftl_spec, div_pow2_bits; trivial.
now rewrite add_opp_r.
now apply opp_nonneg_nonpos.
Qed.
(** Shifts are morphisms *)
Instance shiftr_wd : Proper (eq==>eq==>eq) shiftr.
Proof.
intros a a' Ha n n' Hn.
destruct (le_ge_cases n 0) as [H|H]; assert (H':=H); rewrite Hn in H'.
now rewrite 2 shiftr_mul_pow2, Ha, Hn.
now rewrite 2 shiftr_div_pow2, Ha, Hn.
Qed.
Instance shiftl_wd : Proper (eq==>eq==>eq) shiftl.
Proof.
intros a a' Ha n n' Hn. now rewrite <- 2 shiftr_opp_r, Ha, Hn.
Qed.
(** We could also have specified shiftl with an addition on the left. *)
Lemma shiftl_spec_alt : forall a n m, 0<=n -> (a << n).[m+n] = a.[m].
Proof.
intros. now rewrite shiftl_mul_pow2, mul_pow2_bits, add_simpl_r.
Qed.
(** Chaining several shifts. The only case for which
there isn't any simple expression is a true shiftr
followed by a true shiftl.
*)
Lemma shiftl_shiftl : forall a n m, 0<=n ->
(a << n) << m == a << (n+m).
Proof.
intros a n p Hn. bitwise.
rewrite 2 (shiftl_spec _ _ m) by trivial.
rewrite add_comm, sub_add_distr.
destruct (le_gt_cases 0 (m-p)) as [H|H].
now rewrite shiftl_spec.
rewrite 2 testbit_neg_r; trivial.
apply lt_sub_0. now apply lt_le_trans with 0.
Qed.
Lemma shiftr_shiftl_l : forall a n m, 0<=n ->
(a << n) >> m == a << (n-m).
Proof.
intros. now rewrite <- shiftl_opp_r, shiftl_shiftl, add_opp_r.
Qed.
Lemma shiftr_shiftl_r : forall a n m, 0<=n ->
(a << n) >> m == a >> (m-n).
Proof.
intros. now rewrite <- 2 shiftl_opp_r, shiftl_shiftl, opp_sub_distr, add_comm.
Qed.
Lemma shiftr_shiftr : forall a n m, 0<=m ->
(a >> n) >> m == a >> (n+m).
Proof.
intros a n p Hn. bitwise.
rewrite 3 shiftr_spec; trivial.
now rewrite (add_comm n p), add_assoc.
now apply add_nonneg_nonneg.
Qed.
(** shifts and constants *)
Lemma shiftl_1_l : forall n, 1 << n == 2^n.
Proof.
intros n. destruct (le_gt_cases 0 n).
now rewrite shiftl_mul_pow2, mul_1_l.
rewrite shiftl_div_pow2, div_1_l, pow_neg_r; try order.
apply pow_gt_1. order'. now apply opp_pos_neg.
Qed.
Lemma shiftl_0_r : forall a, a << 0 == a.
Proof.
intros. rewrite shiftl_mul_pow2 by order. now nzsimpl.
Qed.
Lemma shiftr_0_r : forall a, a >> 0 == a.
Proof.
intros. now rewrite <- shiftl_opp_r, opp_0, shiftl_0_r.
Qed.
Lemma shiftl_0_l : forall n, 0 << n == 0.
Proof.
intros.
destruct (le_ge_cases 0 n).
rewrite shiftl_mul_pow2 by trivial. now nzsimpl.
rewrite shiftl_div_pow2 by trivial.
rewrite <- opp_nonneg_nonpos in H. nzsimpl; order_nz.
Qed.
Lemma shiftr_0_l : forall n, 0 >> n == 0.
Proof.
intros. now rewrite <- shiftl_opp_r, shiftl_0_l.
Qed.
Lemma shiftl_eq_0_iff : forall a n, 0<=n -> (a << n == 0 <-> a == 0).
Proof.
intros a n Hn.
rewrite shiftl_mul_pow2 by trivial. rewrite eq_mul_0. split.
intros [H | H]; trivial. contradict H; order_nz.
intros H. now left.
Qed.
Lemma shiftr_eq_0_iff : forall a n,
a >> n == 0 <-> a==0 \/ (0<a /\ log2 a < n).
Proof.
intros a n.
destruct (le_gt_cases 0 n) as [Hn|Hn].
rewrite shiftr_div_pow2, div_small_iff by order_nz.
destruct (lt_trichotomy a 0) as [LT|[EQ|LT]].
split.
intros [(H,_)|(H,H')]. order. generalize (pow_nonneg 2 n le_0_2); order.
intros [H|(H,H')]; order.
rewrite EQ. split. now left. intros _; left. split; order_pos.
split. intros [(H,H')|(H,H')]; right. split; trivial.
apply log2_lt_pow2; trivial.
generalize (pow_nonneg 2 n le_0_2); order.
intros [H|(H,H')]. order. left.
split. order. now apply log2_lt_pow2.
rewrite shiftr_mul_pow2 by order. rewrite eq_mul_0.
split; intros [H|H].
now left.
elim (pow_nonzero 2 (-n)); try apply opp_nonneg_nonpos; order'.
now left.
destruct H. generalize (log2_nonneg a); order.
Qed.
Lemma shiftr_eq_0 : forall a n, 0<=a -> log2 a < n -> a >> n == 0.
Proof.
intros a n Ha H. apply shiftr_eq_0_iff.
le_elim Ha. right. now split. now left.
Qed.
(** Properties of [div2]. *)
Lemma div2_div : forall a, div2 a == a/2.
Proof.
intros. rewrite div2_spec, shiftr_div_pow2. now nzsimpl. order'.
Qed.
Instance div2_wd : Proper (eq==>eq) div2.
Proof.
intros a a' Ha. now rewrite 2 div2_div, Ha.
Qed.
Lemma div2_odd : forall a, a == 2*(div2 a) + odd a.
Proof.
intros a. rewrite div2_div, <- bit0_odd, bit0_mod.
apply div_mod. order'.
Qed.
(** Properties of [lxor] and others, directly deduced
from properties of [xorb] and others. *)
Instance lxor_wd : Proper (eq ==> eq ==> eq) lxor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance land_wd : Proper (eq ==> eq ==> eq) land.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance lor_wd : Proper (eq ==> eq ==> eq) lor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance ldiff_wd : Proper (eq ==> eq ==> eq) ldiff.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Lemma lxor_eq : forall a a', lxor a a' == 0 -> a == a'.
Proof.
intros a a' H. bitwise. apply xorb_eq.
now rewrite <- lxor_spec, H, bits_0.
Qed.
Lemma lxor_nilpotent : forall a, lxor a a == 0.
Proof.
intros. bitwise. apply xorb_nilpotent.
Qed.
Lemma lxor_eq_0_iff : forall a a', lxor a a' == 0 <-> a == a'.
Proof.
split. apply lxor_eq. intros EQ; rewrite EQ; apply lxor_nilpotent.
Qed.
Lemma lxor_0_l : forall a, lxor 0 a == a.
Proof.
intros. bitwise. apply xorb_false_l.
Qed.
Lemma lxor_0_r : forall a, lxor a 0 == a.
Proof.
intros. bitwise. apply xorb_false_r.
Qed.
Lemma lxor_comm : forall a b, lxor a b == lxor b a.
Proof.
intros. bitwise. apply xorb_comm.
Qed.
Lemma lxor_assoc :
forall a b c, lxor (lxor a b) c == lxor a (lxor b c).
Proof.
intros. bitwise. apply xorb_assoc.
Qed.
Lemma lor_0_l : forall a, lor 0 a == a.
Proof.
intros. bitwise. trivial.
Qed.
Lemma lor_0_r : forall a, lor a 0 == a.
Proof.
intros. bitwise. apply orb_false_r.
Qed.
Lemma lor_comm : forall a b, lor a b == lor b a.
Proof.
intros. bitwise. apply orb_comm.
Qed.
Lemma lor_assoc :
forall a b c, lor a (lor b c) == lor (lor a b) c.
Proof.
intros. bitwise. apply orb_assoc.
Qed.
Lemma lor_diag : forall a, lor a a == a.
Proof.
intros. bitwise. apply orb_diag.
Qed.
Lemma lor_eq_0_l : forall a b, lor a b == 0 -> a == 0.
Proof.
intros a b H. bitwise.
apply (orb_false_iff a.[m] b.[m]).
now rewrite <- lor_spec, H, bits_0.
Qed.
Lemma lor_eq_0_iff : forall a b, lor a b == 0 <-> a == 0 /\ b == 0.
Proof.
intros a b. split.
split. now apply lor_eq_0_l in H.
rewrite lor_comm in H. now apply lor_eq_0_l in H.
intros (EQ,EQ'). now rewrite EQ, lor_0_l.
Qed.
Lemma land_0_l : forall a, land 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma land_0_r : forall a, land a 0 == 0.
Proof.
intros. bitwise. apply andb_false_r.
Qed.
Lemma land_comm : forall a b, land a b == land b a.
Proof.
intros. bitwise. apply andb_comm.
Qed.
Lemma land_assoc :
forall a b c, land a (land b c) == land (land a b) c.
Proof.
intros. bitwise. apply andb_assoc.
Qed.
Lemma land_diag : forall a, land a a == a.
Proof.
intros. bitwise. apply andb_diag.
Qed.
Lemma ldiff_0_l : forall a, ldiff 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma ldiff_0_r : forall a, ldiff a 0 == a.
Proof.
intros. bitwise. now rewrite andb_true_r.
Qed.
Lemma ldiff_diag : forall a, ldiff a a == 0.
Proof.
intros. bitwise. apply andb_negb_r.
Qed.
Lemma lor_land_distr_l : forall a b c,
lor (land a b) c == land (lor a c) (lor b c).
Proof.
intros. bitwise. apply orb_andb_distrib_l.
Qed.
Lemma lor_land_distr_r : forall a b c,
lor a (land b c) == land (lor a b) (lor a c).
Proof.
intros. bitwise. apply orb_andb_distrib_r.
Qed.
Lemma land_lor_distr_l : forall a b c,
land (lor a b) c == lor (land a c) (land b c).
Proof.
intros. bitwise. apply andb_orb_distrib_l.
Qed.
Lemma land_lor_distr_r : forall a b c,
land a (lor b c) == lor (land a b) (land a c).
Proof.
intros. bitwise. apply andb_orb_distrib_r.
Qed.
Lemma ldiff_ldiff_l : forall a b c,
ldiff (ldiff a b) c == ldiff a (lor b c).
Proof.
intros. bitwise. now rewrite negb_orb, andb_assoc.
Qed.
Lemma lor_ldiff_and : forall a b,
lor (ldiff a b) (land a b) == a.
Proof.
intros. bitwise.
now rewrite <- andb_orb_distrib_r, orb_comm, orb_negb_r, andb_true_r.
Qed.
Lemma land_ldiff : forall a b,
land (ldiff a b) b == 0.
Proof.
intros. bitwise.
now rewrite <-andb_assoc, (andb_comm (negb _)), andb_negb_r, andb_false_r.
Qed.
(** Properties of [setbit] and [clearbit] *)
Definition setbit a n := lor a (1 << n).
Definition clearbit a n := ldiff a (1 << n).
Lemma setbit_spec' : forall a n, setbit a n == lor a (2^n).
Proof.
intros. unfold setbit. now rewrite shiftl_1_l.
Qed.
Lemma clearbit_spec' : forall a n, clearbit a n == ldiff a (2^n).
Proof.
intros. unfold clearbit. now rewrite shiftl_1_l.
Qed.
Instance setbit_wd : Proper (eq==>eq==>eq) setbit.
Proof. unfold setbit. solve_proper. Qed.
Instance clearbit_wd : Proper (eq==>eq==>eq) clearbit.
Proof. unfold clearbit. solve_proper. Qed.
Lemma pow2_bits_true : forall n, 0<=n -> (2^n).[n] = true.
Proof.
intros. rewrite <- (mul_1_l (2^n)).
now rewrite mul_pow2_bits, sub_diag, bit0_odd, odd_1.
Qed.
Lemma pow2_bits_false : forall n m, n~=m -> (2^n).[m] = false.
Proof.
intros.
destruct (le_gt_cases 0 n); [|now rewrite pow_neg_r, bits_0].
destruct (le_gt_cases n m).
rewrite <- (mul_1_l (2^n)), mul_pow2_bits; trivial.
rewrite <- (succ_pred (m-n)), <- div2_bits.
now rewrite div_small, bits_0 by (split; order').
rewrite <- lt_succ_r, succ_pred, lt_0_sub. order.
rewrite <- (mul_1_l (2^n)), mul_pow2_bits_low; trivial.
Qed.
Lemma pow2_bits_eqb : forall n m, 0<=n -> (2^n).[m] = eqb n m.
Proof.
intros n m Hn. apply eq_true_iff_eq. rewrite eqb_eq. split.
destruct (eq_decidable n m) as [H|H]. trivial.
now rewrite (pow2_bits_false _ _ H).
intros EQ. rewrite EQ. apply pow2_bits_true; order.
Qed.
Lemma setbit_eqb : forall a n m, 0<=n ->
(setbit a n).[m] = eqb n m || a.[m].
Proof.
intros. now rewrite setbit_spec', lor_spec, pow2_bits_eqb, orb_comm.
Qed.
Lemma setbit_iff : forall a n m, 0<=n ->
((setbit a n).[m] = true <-> n==m \/ a.[m] = true).
Proof.
intros. now rewrite setbit_eqb, orb_true_iff, eqb_eq.
Qed.
Lemma setbit_eq : forall a n, 0<=n -> (setbit a n).[n] = true.
Proof.
intros. apply setbit_iff; trivial. now left.
Qed.
Lemma setbit_neq : forall a n m, 0<=n -> n~=m ->
(setbit a n).[m] = a.[m].
Proof.
intros a n m Hn H. rewrite setbit_eqb; trivial.
rewrite <- eqb_eq in H. apply not_true_is_false in H. now rewrite H.
Qed.
Lemma clearbit_eqb : forall a n m,
(clearbit a n).[m] = a.[m] && negb (eqb n m).
Proof.
intros.
destruct (le_gt_cases 0 m); [| now rewrite 2 testbit_neg_r].
rewrite clearbit_spec', ldiff_spec. f_equal. f_equal.
destruct (le_gt_cases 0 n) as [Hn|Hn].
now apply pow2_bits_eqb.
symmetry. rewrite pow_neg_r, bits_0, <- not_true_iff_false, eqb_eq; order.
Qed.
Lemma clearbit_iff : forall a n m,
(clearbit a n).[m] = true <-> a.[m] = true /\ n~=m.
Proof.
intros. rewrite clearbit_eqb, andb_true_iff, <- eqb_eq.
now rewrite negb_true_iff, not_true_iff_false.
Qed.
Lemma clearbit_eq : forall a n, (clearbit a n).[n] = false.
Proof.
intros. rewrite clearbit_eqb, (proj2 (eqb_eq _ _) (eq_refl n)).
apply andb_false_r.
Qed.
Lemma clearbit_neq : forall a n m, n~=m ->
(clearbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite clearbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. rewrite H.
apply andb_true_r.
Qed.
(** Shifts of bitwise operations *)
Lemma shiftl_lxor : forall a b n,
(lxor a b) << n == lxor (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, lxor_spec.
Qed.
Lemma shiftr_lxor : forall a b n,
(lxor a b) >> n == lxor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, lxor_spec.
Qed.
Lemma shiftl_land : forall a b n,
(land a b) << n == land (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, land_spec.
Qed.
Lemma shiftr_land : forall a b n,
(land a b) >> n == land (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, land_spec.
Qed.
Lemma shiftl_lor : forall a b n,
(lor a b) << n == lor (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, lor_spec.
Qed.
Lemma shiftr_lor : forall a b n,
(lor a b) >> n == lor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, lor_spec.
Qed.
Lemma shiftl_ldiff : forall a b n,
(ldiff a b) << n == ldiff (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, ldiff_spec.
Qed.
Lemma shiftr_ldiff : forall a b n,
(ldiff a b) >> n == ldiff (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, ldiff_spec.
Qed.
(** For integers, we do have a binary complement function *)
Definition lnot a := P (-a).
Instance lnot_wd : Proper (eq==>eq) lnot.
Proof. unfold lnot. solve_proper. Qed.
Lemma lnot_spec : forall a n, 0<=n -> (lnot a).[n] = negb a.[n].
Proof.
intros. unfold lnot. rewrite <- (opp_involutive a) at 2.
rewrite bits_opp, negb_involutive; trivial.
Qed.
Lemma lnot_involutive : forall a, lnot (lnot a) == a.
Proof.
intros a. bitwise. now rewrite 2 lnot_spec, negb_involutive.
Qed.
Lemma lnot_0 : lnot 0 == -1.
Proof.
unfold lnot. now rewrite opp_0, <- sub_1_r, sub_0_l.
Qed.
Lemma lnot_m1 : lnot (-1) == 0.
Proof.
unfold lnot. now rewrite opp_involutive, one_succ, pred_succ.
Qed.
(** Complement and other operations *)
Lemma lor_m1_r : forall a, lor a (-1) == -1.
Proof.
intros. bitwise. now rewrite bits_m1, orb_true_r.
Qed.
Lemma lor_m1_l : forall a, lor (-1) a == -1.
Proof.
intros. now rewrite lor_comm, lor_m1_r.
Qed.
Lemma land_m1_r : forall a, land a (-1) == a.
Proof.
intros. bitwise. now rewrite bits_m1, andb_true_r.
Qed.
Lemma land_m1_l : forall a, land (-1) a == a.
Proof.
intros. now rewrite land_comm, land_m1_r.
Qed.
Lemma ldiff_m1_r : forall a, ldiff a (-1) == 0.
Proof.
intros. bitwise. now rewrite bits_m1, andb_false_r.
Qed.
Lemma ldiff_m1_l : forall a, ldiff (-1) a == lnot a.
Proof.
intros. bitwise. now rewrite lnot_spec, bits_m1.
Qed.
Lemma lor_lnot_diag : forall a, lor a (lnot a) == -1.
Proof.
intros a. bitwise. rewrite lnot_spec, bits_m1; trivial.
now destruct a.[m].
Qed.
Lemma add_lnot_diag : forall a, a + lnot a == -1.
Proof.
intros a. unfold lnot.
now rewrite add_pred_r, add_opp_r, sub_diag, one_succ, opp_succ, opp_0.
Qed.
Lemma ldiff_land : forall a b, ldiff a b == land a (lnot b).
Proof.
intros. bitwise. now rewrite lnot_spec.
Qed.
Lemma land_lnot_diag : forall a, land a (lnot a) == 0.
Proof.
intros. now rewrite <- ldiff_land, ldiff_diag.
Qed.
Lemma lnot_lor : forall a b, lnot (lor a b) == land (lnot a) (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, lor_spec, negb_orb.
Qed.
Lemma lnot_land : forall a b, lnot (land a b) == lor (lnot a) (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, land_spec, negb_andb.
Qed.
Lemma lnot_ldiff : forall a b, lnot (ldiff a b) == lor (lnot a) b.
Proof.
intros a b. bitwise.
now rewrite !lnot_spec, ldiff_spec, negb_andb, negb_involutive.
Qed.
Lemma lxor_lnot_lnot : forall a b, lxor (lnot a) (lnot b) == lxor a b.
Proof.
intros a b. bitwise. now rewrite !lnot_spec, xorb_negb_negb.
Qed.
Lemma lnot_lxor_l : forall a b, lnot (lxor a b) == lxor (lnot a) b.
Proof.
intros a b. bitwise. now rewrite !lnot_spec, !lxor_spec, negb_xorb_l.
Qed.
Lemma lnot_lxor_r : forall a b, lnot (lxor a b) == lxor a (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, !lxor_spec, negb_xorb_r.
Qed.
Lemma lxor_m1_r : forall a, lxor a (-1) == lnot a.
Proof.
intros. now rewrite <- (lxor_0_r (lnot a)), <- lnot_m1, lxor_lnot_lnot.
Qed.
Lemma lxor_m1_l : forall a, lxor (-1) a == lnot a.
Proof.
intros. now rewrite lxor_comm, lxor_m1_r.
Qed.
Lemma lxor_lor : forall a b, land a b == 0 ->
lxor a b == lor a b.
Proof.
intros a b H. bitwise.
assert (a.[m] && b.[m] = false)
by now rewrite <- land_spec, H, bits_0.
now destruct a.[m], b.[m].
Qed.
Lemma lnot_shiftr : forall a n, 0<=n -> lnot (a >> n) == (lnot a) >> n.
Proof.
intros a n Hn. bitwise.
now rewrite lnot_spec, 2 shiftr_spec, lnot_spec by order_pos.
Qed.
(** [(ones n)] is [2^n-1], the number with [n] digits 1 *)
Definition ones n := P (1<<n).
Instance ones_wd : Proper (eq==>eq) ones.
Proof. unfold ones. solve_proper. Qed.
Lemma ones_equiv : forall n, ones n == P (2^n).
Proof.
intros. unfold ones.
destruct (le_gt_cases 0 n).
now rewrite shiftl_mul_pow2, mul_1_l.
f_equiv. rewrite pow_neg_r; trivial.
rewrite <- shiftr_opp_r. apply shiftr_eq_0_iff. right; split.
order'. rewrite log2_1. now apply opp_pos_neg.
Qed.
Lemma ones_add : forall n m, 0<=n -> 0<=m ->
ones (m+n) == 2^m * ones n + ones m.
Proof.
intros n m Hn Hm. rewrite !ones_equiv.
rewrite <- !sub_1_r, mul_sub_distr_l, mul_1_r, <- pow_add_r by trivial.
rewrite add_sub_assoc, sub_add. reflexivity.
Qed.
Lemma ones_div_pow2 : forall n m, 0<=m<=n -> ones n / 2^m == ones (n-m).
Proof.
intros n m (Hm,H). symmetry. apply div_unique with (ones m).
left. rewrite ones_equiv. split.
rewrite <- lt_succ_r, succ_pred. order_pos.
now rewrite <- le_succ_l, succ_pred.
rewrite <- (sub_add m n) at 1. rewrite (add_comm _ m).
apply ones_add; trivial. now apply le_0_sub.
Qed.
Lemma ones_mod_pow2 : forall n m, 0<=m<=n -> (ones n) mod (2^m) == ones m.
Proof.
intros n m (Hm,H). symmetry. apply mod_unique with (ones (n-m)).
left. rewrite ones_equiv. split.
rewrite <- lt_succ_r, succ_pred. order_pos.
now rewrite <- le_succ_l, succ_pred.
rewrite <- (sub_add m n) at 1. rewrite (add_comm _ m).
apply ones_add; trivial. now apply le_0_sub.
Qed.
Lemma ones_spec_low : forall n m, 0<=m<n -> (ones n).[m] = true.
Proof.
intros n m (Hm,H). apply testbit_true; trivial.
rewrite ones_div_pow2 by (split; order).
rewrite <- (pow_1_r 2). rewrite ones_mod_pow2.
rewrite ones_equiv. now nzsimpl'.
split. order'. apply le_add_le_sub_r. nzsimpl. now apply le_succ_l.
Qed.
Lemma ones_spec_high : forall n m, 0<=n<=m -> (ones n).[m] = false.
Proof.
intros n m (Hn,H). le_elim Hn.
apply bits_above_log2; rewrite ones_equiv.
rewrite <-lt_succ_r, succ_pred; order_pos.
rewrite log2_pred_pow2; trivial. now rewrite <-le_succ_l, succ_pred.
rewrite ones_equiv. now rewrite <- Hn, pow_0_r, one_succ, pred_succ, bits_0.
Qed.
Lemma ones_spec_iff : forall n m, 0<=n ->
((ones n).[m] = true <-> 0<=m<n).
Proof.
intros n m Hn. split. intros H.
destruct (lt_ge_cases m 0) as [Hm|Hm].
now rewrite testbit_neg_r in H.
split; trivial. apply lt_nge. intro H'. rewrite ones_spec_high in H.
discriminate. now split.
apply ones_spec_low.
Qed.
Lemma lor_ones_low : forall a n, 0<=a -> log2 a < n ->
lor a (ones n) == ones n.
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; try split; trivial.
now apply lt_le_trans with n.
apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, orb_true_r; try split; trivial.
Qed.
Lemma land_ones : forall a n, 0<=n -> land a (ones n) == a mod 2^n.
Proof.
intros a n Hn. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, mod_pow2_bits_high, andb_false_r;
try split; trivial.
rewrite ones_spec_low, mod_pow2_bits_low, andb_true_r;
try split; trivial.
Qed.
Lemma land_ones_low : forall a n, 0<=a -> log2 a < n ->
land a (ones n) == a.
Proof.
intros a n Ha H.
assert (Hn : 0<=n) by (generalize (log2_nonneg a); order).
rewrite land_ones; trivial. apply mod_small.
split; trivial.
apply log2_lt_cancel. now rewrite log2_pow2.
Qed.
Lemma ldiff_ones_r : forall a n, 0<=n ->
ldiff a (ones n) == (a >> n) << n.
Proof.
intros a n Hn. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, shiftl_spec_high, shiftr_spec; trivial.
rewrite sub_add; trivial. apply andb_true_r.
now apply le_0_sub.
now split.
rewrite ones_spec_low, shiftl_spec_low, andb_false_r;
try split; trivial.
Qed.
Lemma ldiff_ones_r_low : forall a n, 0<=a -> log2 a < n ->
ldiff a (ones n) == 0.
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
split; trivial. now apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, andb_false_r; try split; trivial.
Qed.
Lemma ldiff_ones_l_low : forall a n, 0<=a -> log2 a < n ->
ldiff (ones n) a == lxor a (ones n).
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
split; trivial. now apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, xorb_true_r; try split; trivial.
Qed.
(** Bitwise operations and sign *)
Lemma shiftl_nonneg : forall a n, 0 <= (a << n) <-> 0 <= a.
Proof.
intros a n.
destruct (le_ge_cases 0 n) as [Hn|Hn].
(* 0<=n *)
rewrite 2 bits_iff_nonneg_ex. split; intros (k,Hk).
exists (k-n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite <- (add_simpl_r m n), <- (shiftl_spec a n) by order_pos.
apply Hk. now apply lt_sub_lt_add_r.
exists (k+n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftl_spec by trivial. apply Hk. now apply lt_add_lt_sub_r.
(* n<=0*)
rewrite <- shiftr_opp_r, 2 bits_iff_nonneg_ex. split; intros (k,Hk).
destruct (le_gt_cases 0 k).
exists (k-n). intros m Hm. apply lt_sub_lt_add_r in Hm.
rewrite <- (add_simpl_r m n), <- add_opp_r, <- (shiftr_spec a (-n)).
now apply Hk. order.
assert (EQ : a >> (-n) == 0).
apply bits_inj'. intros m Hm. rewrite bits_0. apply Hk; order.
apply shiftr_eq_0_iff in EQ.
rewrite <- bits_iff_nonneg_ex. destruct EQ as [EQ|[LT _]]; order.
exists (k+n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftr_spec by trivial. apply Hk.
rewrite add_opp_r. now apply lt_add_lt_sub_r.
Qed.
Lemma shiftl_neg : forall a n, (a << n) < 0 <-> a < 0.
Proof.
intros a n. now rewrite 2 lt_nge, shiftl_nonneg.
Qed.
Lemma shiftr_nonneg : forall a n, 0 <= (a >> n) <-> 0 <= a.
Proof.
intros. rewrite <- shiftl_opp_r. apply shiftl_nonneg.
Qed.
Lemma shiftr_neg : forall a n, (a >> n) < 0 <-> a < 0.
Proof.
intros a n. now rewrite 2 lt_nge, shiftr_nonneg.
Qed.
Lemma div2_nonneg : forall a, 0 <= div2 a <-> 0 <= a.
Proof.
intros. rewrite div2_spec. apply shiftr_nonneg.
Qed.
Lemma div2_neg : forall a, div2 a < 0 <-> a < 0.
Proof.
intros a. now rewrite 2 lt_nge, div2_nonneg.
Qed.
Lemma lor_nonneg : forall a b, 0 <= lor a b <-> 0<=a /\ 0<=b.
Proof.
intros a b.
rewrite 3 bits_iff_nonneg_ex. split. intros (k,Hk).
split; exists k; intros m Hm; apply (orb_false_elim a.[m] b.[m]);
rewrite <- lor_spec; now apply Hk.
intros ((k,Hk),(k',Hk')).
destruct (le_ge_cases k k'); [ exists k' | exists k ];
intros m Hm; rewrite lor_spec, Hk, Hk'; trivial; order.
Qed.
Lemma lor_neg : forall a b, lor a b < 0 <-> a < 0 \/ b < 0.
Proof.
intros a b. rewrite 3 lt_nge, lor_nonneg. split.
apply not_and. apply le_decidable.
now intros [H|H] (H',H'').
Qed.
Lemma lnot_nonneg : forall a, 0 <= lnot a <-> a < 0.
Proof.
intros a; unfold lnot.
now rewrite <- opp_succ, opp_nonneg_nonpos, le_succ_l.
Qed.
Lemma lnot_neg : forall a, lnot a < 0 <-> 0 <= a.
Proof.
intros a. now rewrite le_ngt, lt_nge, lnot_nonneg.
Qed.
Lemma land_nonneg : forall a b, 0 <= land a b <-> 0<=a \/ 0<=b.
Proof.
intros a b.
now rewrite <- (lnot_involutive (land a b)), lnot_land, lnot_nonneg,
lor_neg, !lnot_neg.
Qed.
Lemma land_neg : forall a b, land a b < 0 <-> a < 0 /\ b < 0.
Proof.
intros a b.
now rewrite <- (lnot_involutive (land a b)), lnot_land, lnot_neg,
lor_nonneg, !lnot_nonneg.
Qed.
Lemma ldiff_nonneg : forall a b, 0 <= ldiff a b <-> 0<=a \/ b<0.
Proof.
intros. now rewrite ldiff_land, land_nonneg, lnot_nonneg.
Qed.
Lemma ldiff_neg : forall a b, ldiff a b < 0 <-> a<0 /\ 0<=b.
Proof.
intros. now rewrite ldiff_land, land_neg, lnot_neg.
Qed.
Lemma lxor_nonneg : forall a b, 0 <= lxor a b <-> (0<=a <-> 0<=b).
Proof.
assert (H : forall a b, 0<=a -> 0<=b -> 0<=lxor a b).
intros a b. rewrite 3 bits_iff_nonneg_ex. intros (k,Hk) (k', Hk').
destruct (le_ge_cases k k'); [ exists k' | exists k];
intros m Hm; rewrite lxor_spec, Hk, Hk'; trivial; order.
assert (H' : forall a b, 0<=a -> b<0 -> lxor a b<0).
intros a b. rewrite bits_iff_nonneg_ex, 2 bits_iff_neg_ex.
intros (k,Hk) (k', Hk').
destruct (le_ge_cases k k'); [ exists k' | exists k];
intros m Hm; rewrite lxor_spec, Hk, Hk'; trivial; order.
intros a b.
split.
intros Hab. split.
intros Ha. destruct (le_gt_cases 0 b) as [Hb|Hb]; trivial.
generalize (H' _ _ Ha Hb). order.
intros Hb. destruct (le_gt_cases 0 a) as [Ha|Ha]; trivial.
generalize (H' _ _ Hb Ha). rewrite lxor_comm. order.
intros E.
destruct (le_gt_cases 0 a) as [Ha|Ha]. apply H; trivial. apply E; trivial.
destruct (le_gt_cases 0 b) as [Hb|Hb]. apply H; trivial. apply E; trivial.
rewrite <- lxor_lnot_lnot. apply H; now apply lnot_nonneg.
Qed.
(** Bitwise operations and log2 *)
Lemma log2_bits_unique : forall a n,
a.[n] = true ->
(forall m, n<m -> a.[m] = false) ->
log2 a == n.
Proof.
intros a n H H'.
destruct (lt_trichotomy a 0) as [Ha|[Ha|Ha]].
(* a < 0 *)
destruct (proj1 (bits_iff_neg_ex a) Ha) as (k,Hk).
destruct (le_gt_cases n k).
specialize (Hk (S k) (lt_succ_diag_r _)).
rewrite H' in Hk. discriminate. apply lt_succ_r; order.
specialize (H' (S n) (lt_succ_diag_r _)).
rewrite Hk in H'. discriminate. apply lt_succ_r; order.
(* a = 0 *)
now rewrite Ha, bits_0 in H.
(* 0 < a *)
apply le_antisymm; apply le_ngt; intros LT.
specialize (H' _ LT). now rewrite bit_log2 in H'.
now rewrite bits_above_log2 in H by order.
Qed.
Lemma log2_shiftr : forall a n, 0<a -> log2 (a >> n) == max 0 (log2 a - n).
Proof.
intros a n Ha.
destruct (le_gt_cases 0 (log2 a - n));
[rewrite max_r | rewrite max_l]; try order.
apply log2_bits_unique.
now rewrite shiftr_spec, sub_add, bit_log2.
intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftr_spec; trivial. apply bits_above_log2; try order.
now apply lt_sub_lt_add_r.
rewrite lt_sub_lt_add_r, add_0_l in H.
apply log2_nonpos. apply le_lteq; right.
apply shiftr_eq_0_iff. right. now split.
Qed.
Lemma log2_shiftl : forall a n, 0<a -> 0<=n -> log2 (a << n) == log2 a + n.
Proof.
intros a n Ha Hn.
rewrite shiftl_mul_pow2, add_comm by trivial.
now apply log2_mul_pow2.
Qed.
Lemma log2_shiftl' : forall a n, 0<a -> log2 (a << n) == max 0 (log2 a + n).
Proof.
intros a n Ha.
rewrite <- shiftr_opp_r, log2_shiftr by trivial.
destruct (le_gt_cases 0 (log2 a + n));
[rewrite 2 max_r | rewrite 2 max_l]; rewrite ?sub_opp_r; try order.
Qed.
Lemma log2_lor : forall a b, 0<=a -> 0<=b ->
log2 (lor a b) == max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (lor a b) == log2 b).
intros a b Ha H.
le_elim Ha; [|now rewrite <- Ha, lor_0_l].
apply log2_bits_unique.
now rewrite lor_spec, bit_log2, orb_true_r by order.
intros m Hm. assert (H' := log2_le_mono _ _ H).
now rewrite lor_spec, 2 bits_above_log2 by order.
(* main *)
intros a b Ha Hb. destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono.
now apply AUX.
rewrite max_l by now apply log2_le_mono.
rewrite lor_comm. now apply AUX.
Qed.
Lemma log2_land : forall a b, 0<=a -> 0<=b ->
log2 (land a b) <= min (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (land a b) <= log2 a).
intros a b Ha Hb.
apply le_ngt. intros LT.
assert (H : 0 <= land a b) by (apply land_nonneg; now left).
le_elim H.
generalize (bit_log2 (land a b) H).
now rewrite land_spec, bits_above_log2.
rewrite <- H in LT. apply log2_lt_cancel in LT; order.
(* main *)
intros a b Ha Hb.
destruct (le_ge_cases a b) as [H|H].
rewrite min_l by now apply log2_le_mono. now apply AUX.
rewrite min_r by now apply log2_le_mono. rewrite land_comm. now apply AUX.
Qed.
Lemma log2_lxor : forall a b, 0<=a -> 0<=b ->
log2 (lxor a b) <= max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (lxor a b) <= log2 b).
intros a b Ha Hb.
apply le_ngt. intros LT.
assert (H : 0 <= lxor a b) by (apply lxor_nonneg; split; order).
le_elim H.
generalize (bit_log2 (lxor a b) H).
rewrite lxor_spec, 2 bits_above_log2; try order. discriminate.
apply le_lt_trans with (log2 b); trivial. now apply log2_le_mono.
rewrite <- H in LT. apply log2_lt_cancel in LT; order.
(* main *)
intros a b Ha Hb.
destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono. now apply AUX.
rewrite max_l by now apply log2_le_mono. rewrite lxor_comm. now apply AUX.
Qed.
(** Bitwise operations and arithmetical operations *)
Local Notation xor3 a b c := (xorb (xorb a b) c).
Local Notation lxor3 a b c := (lxor (lxor a b) c).
Local Notation nextcarry a b c := ((a&&b) || (c && (a||b))).
Local Notation lnextcarry a b c := (lor (land a b) (land c (lor a b))).
Lemma add_bit0 : forall a b, (a+b).[0] = xorb a.[0] b.[0].
Proof.
intros. now rewrite !bit0_odd, odd_add.
Qed.
Lemma add3_bit0 : forall a b c,
(a+b+c).[0] = xor3 a.[0] b.[0] c.[0].
Proof.
intros. now rewrite !add_bit0.
Qed.
Lemma add3_bits_div2 : forall (a0 b0 c0 : bool),
(a0 + b0 + c0)/2 == nextcarry a0 b0 c0.
Proof.
assert (H : 1+1 == 2) by now nzsimpl'.
intros [|] [|] [|]; simpl; rewrite ?add_0_l, ?add_0_r, ?H;
(apply div_same; order') || (apply div_small; split; order') || idtac.
symmetry. apply div_unique with 1. left; split; order'. now nzsimpl'.
Qed.
Lemma add_carry_div2 : forall a b (c0:bool),
(a + b + c0)/2 == a/2 + b/2 + nextcarry a.[0] b.[0] c0.
Proof.
intros.
rewrite <- add3_bits_div2.
rewrite (add_comm ((a/2)+_)).
rewrite <- div_add by order'.
f_equiv.
rewrite <- !div2_div, mul_comm, mul_add_distr_l.
rewrite (div2_odd a), <- bit0_odd at 1.
rewrite (div2_odd b), <- bit0_odd at 1.
rewrite add_shuffle1.
rewrite <-(add_assoc _ _ c0). apply add_comm.
Qed.
(** The main result concerning addition: we express the bits of the sum
in term of bits of [a] and [b] and of some carry stream which is also
recursively determined by another equation.
*)
Lemma add_carry_bits_aux : forall n, 0<=n ->
forall a b (c0:bool), -(2^n) <= a < 2^n -> -(2^n) <= b < 2^n ->
exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros n Hn. apply le_ind with (4:=Hn).
solve_proper.
(* base *)
intros a b c0. rewrite !pow_0_r, !one_succ, !lt_succ_r, <- !one_succ.
intros (Ha1,Ha2) (Hb1,Hb2).
le_elim Ha1; rewrite <- ?le_succ_l, ?succ_m1 in Ha1;
le_elim Hb1; rewrite <- ?le_succ_l, ?succ_m1 in Hb1.
(* base, a = 0, b = 0 *)
exists c0.
rewrite (le_antisymm _ _ Ha2 Ha1), (le_antisymm _ _ Hb2 Hb1).
rewrite !add_0_l, !lxor_0_l, !lor_0_r, !land_0_r, !lor_0_r.
rewrite b2z_div2, b2z_bit0; now repeat split.
(* base, a = 0, b = -1 *)
exists (-c0). rewrite <- Hb1, (le_antisymm _ _ Ha2 Ha1). repeat split.
rewrite add_0_l, lxor_0_l, lxor_m1_l.
unfold lnot. now rewrite opp_involutive, add_comm, add_opp_r, sub_1_r.
rewrite land_0_l, !lor_0_l, land_m1_r.
symmetry. apply div_unique with c0. left; destruct c0; simpl; split; order'.
now rewrite two_succ, mul_succ_l, mul_1_l, add_opp_r, sub_add.
rewrite bit0_odd, odd_opp; destruct c0; simpl; apply odd_1 || apply odd_0.
(* base, a = -1, b = 0 *)
exists (-c0). rewrite <- Ha1, (le_antisymm _ _ Hb2 Hb1). repeat split.
rewrite add_0_r, lxor_0_r, lxor_m1_l.
unfold lnot. now rewrite opp_involutive, add_comm, add_opp_r, sub_1_r.
rewrite land_0_r, lor_0_r, lor_0_l, land_m1_r.
symmetry. apply div_unique with c0. left; destruct c0; simpl; split; order'.
now rewrite two_succ, mul_succ_l, mul_1_l, add_opp_r, sub_add.
rewrite bit0_odd, odd_opp; destruct c0; simpl; apply odd_1 || apply odd_0.
(* base, a = -1, b = -1 *)
exists (c0 + 2*(-1)). rewrite <- Ha1, <- Hb1. repeat split.
rewrite lxor_m1_l, lnot_m1, lxor_0_l.
now rewrite two_succ, mul_succ_l, mul_1_l, add_comm, add_assoc.
rewrite land_m1_l, lor_m1_l.
apply add_b2z_double_div2.
apply add_b2z_double_bit0.
(* step *)
clear n Hn. intros n Hn IH a b c0 Ha Hb.
set (c1:=nextcarry a.[0] b.[0] c0).
destruct (IH (a/2) (b/2) c1) as (c & IH1 & IH2 & Hc); clear IH.
split.
apply div_le_lower_bound. order'. now rewrite mul_opp_r, <- pow_succ_r.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
split.
apply div_le_lower_bound. order'. now rewrite mul_opp_r, <- pow_succ_r.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
exists (c0 + 2*c). repeat split.
(* step, add *)
bitwise.
le_elim Hm.
rewrite <- (succ_pred m), lt_succ_r in Hm.
rewrite <- (succ_pred m), <- !div2_bits, <- 2 lxor_spec by trivial.
f_equiv.
rewrite add_b2z_double_div2, <- IH1. apply add_carry_div2.
rewrite <- Hm.
now rewrite add_b2z_double_bit0, add3_bit0, b2z_bit0.
(* step, carry *)
rewrite add_b2z_double_div2.
bitwise.
le_elim Hm.
rewrite <- (succ_pred m), lt_succ_r in Hm.
rewrite <- (succ_pred m), <- !div2_bits, IH2 by trivial.
autorewrite with bitwise. now rewrite add_b2z_double_div2.
rewrite <- Hm.
now rewrite add_b2z_double_bit0.
(* step, carry0 *)
apply add_b2z_double_bit0.
Qed.
Lemma add_carry_bits : forall a b (c0:bool), exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros a b c0.
set (n := max (abs a) (abs b)).
apply (add_carry_bits_aux n).
(* positivity *)
unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; order_pos'.
(* bound for a *)
assert (Ha : abs a < 2^n).
apply lt_le_trans with (2^(abs a)). apply pow_gt_lin_r; order_pos'.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; try order.
apply abs_lt in Ha. destruct Ha; split; order.
(* bound for b *)
assert (Hb : abs b < 2^n).
apply lt_le_trans with (2^(abs b)). apply pow_gt_lin_r; order_pos'.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; try order.
apply abs_lt in Hb. destruct Hb; split; order.
Qed.
(** Particular case : the second bit of an addition *)
Lemma add_bit1 : forall a b,
(a+b).[1] = xor3 a.[1] b.[1] (a.[0] && b.[0]).
Proof.
intros a b.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
autorewrite with bitwise. f_equal.
rewrite one_succ, <- div2_bits, EQ2 by order.
autorewrite with bitwise.
rewrite Hc. simpl. apply orb_false_r.
Qed.
(** In an addition, there will be no carries iff there is
no common bits in the numbers to add *)
Lemma nocarry_equiv : forall a b c,
c/2 == lnextcarry a b c -> c.[0] = false ->
(c == 0 <-> land a b == 0).
Proof.
intros a b c H H'.
split. intros EQ; rewrite EQ in *.
rewrite div_0_l in H by order'.
symmetry in H. now apply lor_eq_0_l in H.
intros EQ. rewrite EQ, lor_0_l in H.
apply bits_inj'. intros n Hn. rewrite bits_0.
apply le_ind with (4:=Hn).
solve_proper.
trivial.
clear n Hn. intros n Hn IH.
rewrite <- div2_bits, H; trivial.
autorewrite with bitwise.
now rewrite IH.
Qed.
(** When there is no common bits, the addition is just a xor *)
Lemma add_nocarry_lxor : forall a b, land a b == 0 ->
a+b == lxor a b.
Proof.
intros a b H.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
apply (nocarry_equiv a b c) in H; trivial.
rewrite H. now rewrite lxor_0_r.
Qed.
(** A null [ldiff] implies being smaller *)
Lemma ldiff_le : forall a b, 0<=b -> ldiff a b == 0 -> 0 <= a <= b.
Proof.
assert (AUX : forall n, 0<=n ->
forall a b, 0 <= a < 2^n -> 0<=b -> ldiff a b == 0 -> a <= b).
intros n Hn. apply le_ind with (4:=Hn); clear n Hn.
solve_proper.
intros a b Ha Hb _. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
setoid_replace a with 0 by (destruct Ha; order'); trivial.
intros n Hn IH a b (Ha,Ha') Hb H.
assert (NEQ : 2 ~= 0) by order'.
rewrite (div_mod a 2 NEQ), (div_mod b 2 NEQ).
apply add_le_mono.
apply mul_le_mono_pos_l; try order'.
apply IH.
split. apply div_pos; order'.
apply div_lt_upper_bound; try order'. now rewrite <- pow_succ_r.
apply div_pos; order'.
rewrite <- (pow_1_r 2), <- 2 shiftr_div_pow2 by order'.
rewrite <- shiftr_ldiff, H, shiftr_div_pow2, pow_1_r, div_0_l; order'.
rewrite <- 2 bit0_mod.
apply bits_inj_iff in H. specialize (H 0).
rewrite ldiff_spec, bits_0 in H.
destruct a.[0], b.[0]; try discriminate; simpl; order'.
(* main *)
intros a b Hb Hd.
assert (Ha : 0<=a).
apply le_ngt; intros Ha'. apply (lt_irrefl 0). rewrite <- Hd at 1.
apply ldiff_neg. now split.
split; trivial. apply (AUX a); try split; trivial. apply pow_gt_lin_r; order'.
Qed.
(** Subtraction can be a ldiff when the opposite ldiff is null. *)
Lemma sub_nocarry_ldiff : forall a b, ldiff b a == 0 ->
a-b == ldiff a b.
Proof.
intros a b H.
apply add_cancel_r with b.
rewrite sub_add.
symmetry.
rewrite add_nocarry_lxor; trivial.
bitwise.
apply bits_inj_iff in H. specialize (H m).
rewrite ldiff_spec, bits_0 in H.
now destruct a.[m], b.[m].
apply land_ldiff.
Qed.
(** Adding numbers with no common bits cannot lead to a much bigger number *)
Lemma add_nocarry_lt_pow2 : forall a b n, land a b == 0 ->
a < 2^n -> b < 2^n -> a+b < 2^n.
Proof.
intros a b n H Ha Hb.
destruct (le_gt_cases a 0) as [Ha'|Ha'].
apply le_lt_trans with (0+b). now apply add_le_mono_r. now nzsimpl.
destruct (le_gt_cases b 0) as [Hb'|Hb'].
apply le_lt_trans with (a+0). now apply add_le_mono_l. now nzsimpl.
rewrite add_nocarry_lxor by order.
destruct (lt_ge_cases 0 (lxor a b)); [|apply le_lt_trans with 0; order_pos].
apply log2_lt_pow2; trivial.
apply log2_lt_pow2 in Ha; trivial.
apply log2_lt_pow2 in Hb; trivial.
apply le_lt_trans with (max (log2 a) (log2 b)).
apply log2_lxor; order.
destruct (le_ge_cases (log2 a) (log2 b));
[rewrite max_r|rewrite max_l]; order.
Qed.
Lemma add_nocarry_mod_lt_pow2 : forall a b n, 0<=n -> land a b == 0 ->
a mod 2^n + b mod 2^n < 2^n.
Proof.
intros a b n Hn H.
apply add_nocarry_lt_pow2.
bitwise.
destruct (le_gt_cases n m).
rewrite mod_pow2_bits_high; now split.
now rewrite !mod_pow2_bits_low, <- land_spec, H, bits_0.
apply mod_pos_bound; order_pos.
apply mod_pos_bound; order_pos.
Qed.
End ZBitsProp.
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import
Bool ZAxioms ZMulOrder ZPow ZDivFloor ZSgnAbs ZParity NZLog.
(** Derived properties of bitwise operations *)
Module Type ZBitsProp
(Import A : ZAxiomsSig')
(Import B : ZMulOrderProp A)
(Import C : ZParityProp A B)
(Import D : ZSgnAbsProp A B)
(Import E : ZPowProp A B C D)
(Import F : ZDivProp A B D)
(Import G : NZLog2Prop A A A B E).
Include BoolEqualityFacts A.
Ltac order_nz := try apply pow_nonzero; order'.
Ltac order_pos' := try apply abs_nonneg; order_pos.
Hint Rewrite div_0_l mod_0_l div_1_r mod_1_r : nz.
(** Some properties of power and division *)
Lemma pow_sub_r : forall a b c, a~=0 -> 0<=c<=b -> a^(b-c) == a^b / a^c.
Proof.
intros a b c Ha (H,H'). rewrite <- (sub_simpl_r b c) at 2.
rewrite pow_add_r; trivial.
rewrite div_mul. reflexivity.
now apply pow_nonzero.
now apply le_0_sub.
Qed.
Lemma pow_div_l : forall a b c, b~=0 -> 0<=c -> a mod b == 0 ->
(a/b)^c == a^c / b^c.
Proof.
intros a b c Hb Hc H. rewrite (div_mod a b Hb) at 2.
rewrite H, add_0_r, pow_mul_l, mul_comm, div_mul. reflexivity.
now apply pow_nonzero.
Qed.
(** An injection from bits [true] and [false] to numbers 1 and 0.
We declare it as a (local) coercion for shorter statements. *)
Definition b2z (b:bool) := if b then 1 else 0.
Local Coercion b2z : bool >-> t.
Instance b2z_wd : Proper (Logic.eq ==> eq) b2z := _.
Lemma exists_div2 a : exists a' (b:bool), a == 2*a' + b.
Proof.
elim (Even_or_Odd a); [intros (a',H)| intros (a',H)].
exists a'. exists false. now nzsimpl.
exists a'. exists true. now simpl.
Qed.
(** We can compact [testbit_odd_0] [testbit_even_0]
[testbit_even_succ] [testbit_odd_succ] in only two lemmas. *)
Lemma testbit_0_r a (b:bool) : testbit (2*a+b) 0 = b.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_0.
apply testbit_even_0.
Qed.
Lemma testbit_succ_r a (b:bool) n : 0<=n ->
testbit (2*a+b) (succ n) = testbit a n.
Proof.
destruct b; simpl; rewrite ?add_0_r.
now apply testbit_odd_succ.
now apply testbit_even_succ.
Qed.
(** Alternative caracterisations of [testbit] *)
(** This concise equation could have been taken as specification
for testbit in the interface, but it would have been hard to
implement with little initial knowledge about div and mod *)
Lemma testbit_spec' a n : 0<=n -> a.[n] == (a / 2^n) mod 2.
Proof.
intro Hn. revert a. apply le_ind with (4:=Hn).
solve_proper.
intros a. nzsimpl.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_0_r. apply mod_unique with a'; trivial.
left. destruct b; split; simpl; order'.
clear n Hn. intros n Hn IH a.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_succ_r, IH by trivial. f_equiv.
rewrite pow_succ_r, <- div_div by order_pos. f_equiv.
apply div_unique with b; trivial.
left. destruct b; split; simpl; order'.
Qed.
(** This caracterisation that uses only basic operations and
power was initially taken as specification for testbit.
We describe [a] as having a low part and a high part, with
the corresponding bit in the middle. This caracterisation
is moderatly complex to implement, but also moderately
usable... *)
Lemma testbit_spec a n : 0<=n ->
exists l h, 0<=l<2^n /\ a == l + (a.[n] + 2*h)*2^n.
Proof.
intro Hn. exists (a mod 2^n). exists (a / 2^n / 2). split.
apply mod_pos_bound; order_pos.
rewrite add_comm, mul_comm, (add_comm a.[n]).
rewrite (div_mod a (2^n)) at 1 by order_nz. do 2 f_equiv.
rewrite testbit_spec' by trivial. apply div_mod. order'.
Qed.
Lemma testbit_true : forall a n, 0<=n ->
(a.[n] = true <-> (a / 2^n) mod 2 == 1).
Proof.
intros a n Hn.
rewrite <- testbit_spec' by trivial.
destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_false : forall a n, 0<=n ->
(a.[n] = false <-> (a / 2^n) mod 2 == 0).
Proof.
intros a n Hn.
rewrite <- testbit_spec' by trivial.
destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_eqb : forall a n, 0<=n ->
a.[n] = eqb ((a / 2^n) mod 2) 1.
Proof.
intros a n Hn.
apply eq_true_iff_eq. now rewrite testbit_true, eqb_eq.
Qed.
(** Results about the injection [b2z] *)
Lemma b2z_inj : forall (a0 b0:bool), a0 == b0 -> a0 = b0.
Proof.
intros [|] [|]; simpl; trivial; order'.
Qed.
Lemma add_b2z_double_div2 : forall (a0:bool) a, (a0+2*a)/2 == a.
Proof.
intros a0 a. rewrite mul_comm, div_add by order'.
now rewrite div_small, add_0_l by (destruct a0; split; simpl; order').
Qed.
Lemma add_b2z_double_bit0 : forall (a0:bool) a, (a0+2*a).[0] = a0.
Proof.
intros a0 a. apply b2z_inj.
rewrite testbit_spec' by order.
nzsimpl. rewrite mul_comm, mod_add by order'.
now rewrite mod_small by (destruct a0; split; simpl; order').
Qed.
Lemma b2z_div2 : forall (a0:bool), a0/2 == 0.
Proof.
intros a0. rewrite <- (add_b2z_double_div2 a0 0). now nzsimpl.
Qed.
Lemma b2z_bit0 : forall (a0:bool), a0.[0] = a0.
Proof.
intros a0. rewrite <- (add_b2z_double_bit0 a0 0) at 2. now nzsimpl.
Qed.
(** The specification of testbit by low and high parts is complete *)
Lemma testbit_unique : forall a n (a0:bool) l h,
0<=l<2^n -> a == l + (a0 + 2*h)*2^n -> a.[n] = a0.
Proof.
intros a n a0 l h Hl EQ.
assert (0<=n).
destruct (le_gt_cases 0 n) as [Hn|Hn]; trivial.
rewrite pow_neg_r in Hl by trivial. destruct Hl; order.
apply b2z_inj. rewrite testbit_spec' by trivial.
symmetry. apply mod_unique with h.
left; destruct a0; simpl; split; order'.
symmetry. apply div_unique with l.
now left.
now rewrite add_comm, (add_comm _ a0), mul_comm.
Qed.
(** All bits of number 0 are 0 *)
Lemma bits_0 : forall n, 0.[n] = false.
Proof.
intros n.
destruct (le_gt_cases 0 n).
apply testbit_false; trivial. nzsimpl; order_nz.
now apply testbit_neg_r.
Qed.
(** For negative numbers, we are actually doing two's complement *)
Lemma bits_opp : forall a n, 0<=n -> (-a).[n] = negb (P a).[n].
Proof.
intros a n Hn.
destruct (testbit_spec (-a) n Hn) as (l & h & Hl & EQ).
fold (b2z (-a).[n]) in EQ.
apply negb_sym.
apply testbit_unique with (2^n-l-1) (-h-1).
split.
apply lt_succ_r. rewrite sub_1_r, succ_pred. now apply lt_0_sub.
apply le_succ_l. rewrite sub_1_r, succ_pred. apply le_sub_le_add_r.
rewrite <- (add_0_r (2^n)) at 1. now apply add_le_mono_l.
rewrite <- add_sub_swap, sub_1_r. f_equiv.
apply opp_inj. rewrite opp_add_distr, opp_sub_distr.
rewrite (add_comm _ l), <- add_assoc.
rewrite EQ at 1. apply add_cancel_l.
rewrite <- opp_add_distr.
rewrite <- (mul_1_l (2^n)) at 2. rewrite <- mul_add_distr_r.
rewrite <- mul_opp_l.
f_equiv.
rewrite !opp_add_distr.
rewrite <- mul_opp_r.
rewrite opp_sub_distr, opp_involutive.
rewrite (add_comm h).
rewrite mul_add_distr_l.
rewrite !add_assoc.
apply add_cancel_r.
rewrite mul_1_r.
rewrite add_comm, add_assoc, !add_opp_r, sub_1_r, two_succ, pred_succ.
destruct (-a).[n]; simpl. now rewrite sub_0_r. now nzsimpl'.
Qed.
(** All bits of number (-1) are 1 *)
Lemma bits_m1 : forall n, 0<=n -> (-1).[n] = true.
Proof.
intros. now rewrite bits_opp, one_succ, pred_succ, bits_0.
Qed.
(** Various ways to refer to the lowest bit of a number *)
Lemma bit0_odd : forall a, a.[0] = odd a.
Proof.
intros. symmetry.
destruct (exists_div2 a) as (a' & b & EQ).
rewrite EQ, testbit_0_r, add_comm, odd_add_mul_2.
destruct b; simpl; apply odd_1 || apply odd_0.
Qed.
Lemma bit0_eqb : forall a, a.[0] = eqb (a mod 2) 1.
Proof.
intros a. rewrite testbit_eqb by order. now nzsimpl.
Qed.
Lemma bit0_mod : forall a, a.[0] == a mod 2.
Proof.
intros a. rewrite testbit_spec' by order. now nzsimpl.
Qed.
(** Hence testing a bit is equivalent to shifting and testing parity *)
Lemma testbit_odd : forall a n, a.[n] = odd (a>>n).
Proof.
intros. now rewrite <- bit0_odd, shiftr_spec, add_0_l.
Qed.
(** [log2] gives the highest nonzero bit of positive numbers *)
Lemma bit_log2 : forall a, 0<a -> a.[log2 a] = true.
Proof.
intros a Ha.
assert (Ha' := log2_nonneg a).
destruct (log2_spec_alt a Ha) as (r & EQ & Hr).
rewrite EQ at 1.
rewrite testbit_true, add_comm by trivial.
rewrite <- (mul_1_l (2^log2 a)) at 1.
rewrite div_add by order_nz.
rewrite div_small; trivial.
rewrite add_0_l. apply mod_small. split; order'.
Qed.
Lemma bits_above_log2 : forall a n, 0<=a -> log2 a < n ->
a.[n] = false.
Proof.
intros a n Ha H.
assert (Hn : 0<=n).
transitivity (log2 a). apply log2_nonneg. order'.
rewrite testbit_false by trivial.
rewrite div_small. nzsimpl; order'.
split. order. apply log2_lt_cancel. now rewrite log2_pow2.
Qed.
(** Hence the number of bits of [a] is [1+log2 a]
(see [Pos.size_nat] and [Pos.size]).
*)
(** For negative numbers, things are the other ways around:
log2 gives the highest zero bit (for numbers below -1).
*)
Lemma bit_log2_neg : forall a, a < -1 -> a.[log2 (P (-a))] = false.
Proof.
intros a Ha.
rewrite <- (opp_involutive a) at 1.
rewrite bits_opp.
apply negb_false_iff.
apply bit_log2.
apply opp_lt_mono in Ha. rewrite opp_involutive in Ha.
apply lt_succ_lt_pred. now rewrite <- one_succ.
apply log2_nonneg.
Qed.
Lemma bits_above_log2_neg : forall a n, a < 0 -> log2 (P (-a)) < n ->
a.[n] = true.
Proof.
intros a n Ha H.
assert (Hn : 0<=n).
transitivity (log2 (P (-a))). apply log2_nonneg. order'.
rewrite <- (opp_involutive a), bits_opp, negb_true_iff by trivial.
apply bits_above_log2; trivial.
now rewrite <- opp_succ, opp_nonneg_nonpos, le_succ_l.
Qed.
(** Accesing a high enough bit of a number gives its sign *)
Lemma bits_iff_nonneg : forall a n, log2 (abs a) < n ->
(0<=a <-> a.[n] = false).
Proof.
intros a n Hn. split; intros H.
rewrite abs_eq in Hn; trivial. now apply bits_above_log2.
destruct (le_gt_cases 0 a); trivial.
rewrite abs_neq in Hn by order.
rewrite bits_above_log2_neg in H; try easy.
apply le_lt_trans with (log2 (-a)); trivial.
apply log2_le_mono. apply le_pred_l.
Qed.
Lemma bits_iff_nonneg' : forall a,
0<=a <-> a.[S (log2 (abs a))] = false.
Proof.
intros. apply bits_iff_nonneg. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_nonneg_ex : forall a,
0<=a <-> (exists k, forall m, k<m -> a.[m] = false).
Proof.
intros a. split.
intros Ha. exists (log2 a). intros m Hm. now apply bits_above_log2.
intros (k,Hk). destruct (le_gt_cases k (log2 (abs a))).
now apply bits_iff_nonneg', Hk, lt_succ_r.
apply (bits_iff_nonneg a (S k)).
now apply lt_succ_r, lt_le_incl.
apply Hk. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_neg : forall a n, log2 (abs a) < n ->
(a<0 <-> a.[n] = true).
Proof.
intros a n Hn.
now rewrite lt_nge, <- not_false_iff_true, (bits_iff_nonneg a n).
Qed.
Lemma bits_iff_neg' : forall a, a<0 <-> a.[S (log2 (abs a))] = true.
Proof.
intros. apply bits_iff_neg. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_neg_ex : forall a,
a<0 <-> (exists k, forall m, k<m -> a.[m] = true).
Proof.
intros a. split.
intros Ha. exists (log2 (P (-a))). intros m Hm. now apply bits_above_log2_neg.
intros (k,Hk). destruct (le_gt_cases k (log2 (abs a))).
now apply bits_iff_neg', Hk, lt_succ_r.
apply (bits_iff_neg a (S k)).
now apply lt_succ_r, lt_le_incl.
apply Hk. apply lt_succ_diag_r.
Qed.
(** Testing bits after division or multiplication by a power of two *)
Lemma div2_bits : forall a n, 0<=n -> (a/2).[n] = a.[S n].
Proof.
intros a n Hn.
apply eq_true_iff_eq. rewrite 2 testbit_true by order_pos.
rewrite pow_succ_r by trivial.
now rewrite div_div by order_pos.
Qed.
Lemma div_pow2_bits : forall a n m, 0<=n -> 0<=m -> (a/2^n).[m] = a.[m+n].
Proof.
intros a n m Hn. revert a m. apply le_ind with (4:=Hn).
solve_proper.
intros a m Hm. now nzsimpl.
clear n Hn. intros n Hn IH a m Hm. nzsimpl; trivial.
rewrite <- div_div by order_pos.
now rewrite IH, div2_bits by order_pos.
Qed.
Lemma double_bits_succ : forall a n, (2*a).[S n] = a.[n].
Proof.
intros a n.
destruct (le_gt_cases 0 n) as [Hn|Hn].
now rewrite <- div2_bits, mul_comm, div_mul by order'.
rewrite (testbit_neg_r a n Hn).
apply le_succ_l in Hn. le_elim Hn.
now rewrite testbit_neg_r.
now rewrite Hn, bit0_odd, odd_mul, odd_2.
Qed.
Lemma double_bits : forall a n, (2*a).[n] = a.[P n].
Proof.
intros a n. rewrite <- (succ_pred n) at 1. apply double_bits_succ.
Qed.
Lemma mul_pow2_bits_add : forall a n m, 0<=n -> (a*2^n).[n+m] = a.[m].
Proof.
intros a n m Hn. revert a m. apply le_ind with (4:=Hn).
solve_proper.
intros a m. now nzsimpl.
clear n Hn. intros n Hn IH a m. nzsimpl; trivial.
rewrite mul_assoc, (mul_comm _ 2), <- mul_assoc.
now rewrite double_bits_succ.
Qed.
Lemma mul_pow2_bits : forall a n m, 0<=n -> (a*2^n).[m] = a.[m-n].
Proof.
intros.
rewrite <- (add_simpl_r m n) at 1. rewrite add_sub_swap, add_comm.
now apply mul_pow2_bits_add.
Qed.
Lemma mul_pow2_bits_low : forall a n m, m<n -> (a*2^n).[m] = false.
Proof.
intros.
destruct (le_gt_cases 0 n).
rewrite mul_pow2_bits by trivial.
apply testbit_neg_r. now apply lt_sub_0.
now rewrite pow_neg_r, mul_0_r, bits_0.
Qed.
(** Selecting the low part of a number can be done by a modulo *)
Lemma mod_pow2_bits_high : forall a n m, 0<=n<=m ->
(a mod 2^n).[m] = false.
Proof.
intros a n m (Hn,H).
destruct (mod_pos_bound a (2^n)) as [LE LT]. order_pos.
le_elim LE.
apply bits_above_log2; try order.
apply lt_le_trans with n; trivial.
apply log2_lt_pow2; trivial.
now rewrite <- LE, bits_0.
Qed.
Lemma mod_pow2_bits_low : forall a n m, m<n ->
(a mod 2^n).[m] = a.[m].
Proof.
intros a n m H.
destruct (le_gt_cases 0 m) as [Hm|Hm]; [|now rewrite !testbit_neg_r].
rewrite testbit_eqb; trivial.
rewrite <- (mod_add _ (2^(P (n-m))*(a/2^n))) by order'.
rewrite <- div_add by order_nz.
rewrite (mul_comm _ 2), mul_assoc, <- pow_succ_r, succ_pred.
rewrite mul_comm, mul_assoc, <- pow_add_r, (add_comm m), sub_add; trivial.
rewrite add_comm, <- div_mod by order_nz.
symmetry. apply testbit_eqb; trivial.
apply le_0_sub; order.
now apply lt_le_pred, lt_0_sub.
Qed.
(** We now prove that having the same bits implies equality.
For that we use a notion of equality over functional
streams of bits. *)
Definition eqf (f g:t -> bool) := forall n:t, f n = g n.
Instance eqf_equiv : Equivalence eqf.
Proof.
split; congruence.
Qed.
Local Infix "===" := eqf (at level 70, no associativity).
Instance testbit_eqf : Proper (eq==>eqf) testbit.
Proof.
intros a a' Ha n. now rewrite Ha.
Qed.
(** Only zero corresponds to the always-false stream. *)
Lemma bits_inj_0 :
forall a, (forall n, a.[n] = false) -> a == 0.
Proof.
intros a H. destruct (lt_trichotomy a 0) as [Ha|[Ha|Ha]]; trivial.
apply (bits_above_log2_neg a (S (log2 (P (-a))))) in Ha.
now rewrite H in Ha.
apply lt_succ_diag_r.
apply bit_log2 in Ha. now rewrite H in Ha.
Qed.
(** If two numbers produce the same stream of bits, they are equal. *)
Lemma bits_inj : forall a b, testbit a === testbit b -> a == b.
Proof.
assert (AUX : forall n, 0<=n -> forall a b,
0<=a<2^n -> testbit a === testbit b -> a == b).
intros n Hn. apply le_ind with (4:=Hn).
solve_proper.
intros a b Ha H. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
assert (Ha' : a == 0) by (destruct Ha; order).
rewrite Ha' in *.
symmetry. apply bits_inj_0.
intros m. now rewrite <- H, bits_0.
clear n Hn. intros n Hn IH a b (Ha,Ha') H.
rewrite (div_mod a 2), (div_mod b 2) by order'.
f_equiv; [ | now rewrite <- 2 bit0_mod, H].
f_equiv.
apply IH.
split. apply div_pos; order'.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
intros m.
destruct (le_gt_cases 0 m).
rewrite 2 div2_bits by trivial. apply H.
now rewrite 2 testbit_neg_r.
intros a b H.
destruct (le_gt_cases 0 a) as [Ha|Ha].
apply (AUX a); trivial. split; trivial.
apply pow_gt_lin_r; order'.
apply succ_inj, opp_inj.
assert (0 <= - S a).
apply opp_le_mono. now rewrite opp_involutive, opp_0, le_succ_l.
apply (AUX (-(S a))); trivial. split; trivial.
apply pow_gt_lin_r; order'.
intros m. destruct (le_gt_cases 0 m).
now rewrite 2 bits_opp, 2 pred_succ, H.
now rewrite 2 testbit_neg_r.
Qed.
Lemma bits_inj_iff : forall a b, testbit a === testbit b <-> a == b.
Proof.
split. apply bits_inj. intros EQ; now rewrite EQ.
Qed.
(** In fact, checking the bits at positive indexes is enough. *)
Lemma bits_inj' : forall a b,
(forall n, 0<=n -> a.[n] = b.[n]) -> a == b.
Proof.
intros a b H. apply bits_inj.
intros n. destruct (le_gt_cases 0 n).
now apply H.
now rewrite 2 testbit_neg_r.
Qed.
Lemma bits_inj_iff' : forall a b, (forall n, 0<=n -> a.[n] = b.[n]) <-> a == b.
Proof.
split. apply bits_inj'. intros EQ n Hn; now rewrite EQ.
Qed.
Ltac bitwise := apply bits_inj'; intros ?m ?Hm; autorewrite with bitwise.
Hint Rewrite lxor_spec lor_spec land_spec ldiff_spec bits_0 : bitwise.
(** The streams of bits that correspond to a numbers are
exactly the ones which are stationary after some point. *)
Lemma are_bits : forall (f:t->bool), Proper (eq==>Logic.eq) f ->
((exists n, forall m, 0<=m -> f m = n.[m]) <->
(exists k, forall m, k<=m -> f m = f k)).
Proof.
intros f Hf. split.
intros (a,H).
destruct (le_gt_cases 0 a).
exists (S (log2 a)). intros m Hm. apply le_succ_l in Hm.
rewrite 2 H, 2 bits_above_log2; trivial using lt_succ_diag_r.
order_pos. apply le_trans with (log2 a); order_pos.
exists (S (log2 (P (-a)))). intros m Hm. apply le_succ_l in Hm.
rewrite 2 H, 2 bits_above_log2_neg; trivial using lt_succ_diag_r.
order_pos. apply le_trans with (log2 (P (-a))); order_pos.
intros (k,Hk).
destruct (lt_ge_cases k 0) as [LT|LE].
case_eq (f 0); intros H0.
exists (-1). intros m Hm. rewrite bits_m1, Hk by order.
symmetry; rewrite <- H0. apply Hk; order.
exists 0. intros m Hm. rewrite bits_0, Hk by order.
symmetry; rewrite <- H0. apply Hk; order.
revert f Hf Hk. apply le_ind with (4:=LE).
(* compat : solve_proper fails here *)
apply proper_sym_impl_iff. exact eq_sym.
clear k LE. intros k k' Hk IH f Hf H. apply IH; trivial.
now setoid_rewrite Hk.
(* /compat *)
intros f Hf H0. destruct (f 0).
exists (-1). intros m Hm. now rewrite bits_m1, H0.
exists 0. intros m Hm. now rewrite bits_0, H0.
clear k LE. intros k LE IH f Hf Hk.
destruct (IH (fun m => f (S m))) as (n, Hn).
solve_proper.
intros m Hm. apply Hk. now rewrite <- succ_le_mono.
exists (f 0 + 2*n). intros m Hm.
le_elim Hm.
rewrite <- (succ_pred m), Hn, <- div2_bits.
rewrite mul_comm, div_add, b2z_div2, add_0_l; trivial. order'.
now rewrite <- lt_succ_r, succ_pred.
now rewrite <- lt_succ_r, succ_pred.
rewrite <- Hm.
symmetry. apply add_b2z_double_bit0.
Qed.
(** * Properties of shifts *)
(** First, a unified specification for [shiftl] : the [shiftl_spec]
below (combined with [testbit_neg_r]) is equivalent to
[shiftl_spec_low] and [shiftl_spec_high]. *)
Lemma shiftl_spec : forall a n m, 0<=m -> (a << n).[m] = a.[m-n].
Proof.
intros.
destruct (le_gt_cases n m).
now apply shiftl_spec_high.
rewrite shiftl_spec_low, testbit_neg_r; trivial. now apply lt_sub_0.
Qed.
(** A shiftl by a negative number is a shiftr, and vice-versa *)
Lemma shiftr_opp_r : forall a n, a >> (-n) == a << n.
Proof.
intros. bitwise. now rewrite shiftr_spec, shiftl_spec, add_opp_r.
Qed.
Lemma shiftl_opp_r : forall a n, a << (-n) == a >> n.
Proof.
intros. bitwise. now rewrite shiftr_spec, shiftl_spec, sub_opp_r.
Qed.
(** Shifts correspond to multiplication or division by a power of two *)
Lemma shiftr_div_pow2 : forall a n, 0<=n -> a >> n == a / 2^n.
Proof.
intros. bitwise. now rewrite shiftr_spec, div_pow2_bits.
Qed.
Lemma shiftr_mul_pow2 : forall a n, n<=0 -> a >> n == a * 2^(-n).
Proof.
intros. bitwise. rewrite shiftr_spec, mul_pow2_bits; trivial.
now rewrite sub_opp_r.
now apply opp_nonneg_nonpos.
Qed.
Lemma shiftl_mul_pow2 : forall a n, 0<=n -> a << n == a * 2^n.
Proof.
intros. bitwise. now rewrite shiftl_spec, mul_pow2_bits.
Qed.
Lemma shiftl_div_pow2 : forall a n, n<=0 -> a << n == a / 2^(-n).
Proof.
intros. bitwise. rewrite shiftl_spec, div_pow2_bits; trivial.
now rewrite add_opp_r.
now apply opp_nonneg_nonpos.
Qed.
(** Shifts are morphisms *)
Instance shiftr_wd : Proper (eq==>eq==>eq) shiftr.
Proof.
intros a a' Ha n n' Hn.
destruct (le_ge_cases n 0) as [H|H]; assert (H':=H); rewrite Hn in H'.
now rewrite 2 shiftr_mul_pow2, Ha, Hn.
now rewrite 2 shiftr_div_pow2, Ha, Hn.
Qed.
Instance shiftl_wd : Proper (eq==>eq==>eq) shiftl.
Proof.
intros a a' Ha n n' Hn. now rewrite <- 2 shiftr_opp_r, Ha, Hn.
Qed.
(** We could also have specified shiftl with an addition on the left. *)
Lemma shiftl_spec_alt : forall a n m, 0<=n -> (a << n).[m+n] = a.[m].
Proof.
intros. now rewrite shiftl_mul_pow2, mul_pow2_bits, add_simpl_r.
Qed.
(** Chaining several shifts. The only case for which
there isn't any simple expression is a true shiftr
followed by a true shiftl.
*)
Lemma shiftl_shiftl : forall a n m, 0<=n ->
(a << n) << m == a << (n+m).
Proof.
intros a n p Hn. bitwise.
rewrite 2 (shiftl_spec _ _ m) by trivial.
rewrite add_comm, sub_add_distr.
destruct (le_gt_cases 0 (m-p)) as [H|H].
now rewrite shiftl_spec.
rewrite 2 testbit_neg_r; trivial.
apply lt_sub_0. now apply lt_le_trans with 0.
Qed.
Lemma shiftr_shiftl_l : forall a n m, 0<=n ->
(a << n) >> m == a << (n-m).
Proof.
intros. now rewrite <- shiftl_opp_r, shiftl_shiftl, add_opp_r.
Qed.
Lemma shiftr_shiftl_r : forall a n m, 0<=n ->
(a << n) >> m == a >> (m-n).
Proof.
intros. now rewrite <- 2 shiftl_opp_r, shiftl_shiftl, opp_sub_distr, add_comm.
Qed.
Lemma shiftr_shiftr : forall a n m, 0<=m ->
(a >> n) >> m == a >> (n+m).
Proof.
intros a n p Hn. bitwise.
rewrite 3 shiftr_spec; trivial.
now rewrite (add_comm n p), add_assoc.
now apply add_nonneg_nonneg.
Qed.
(** shifts and constants *)
Lemma shiftl_1_l : forall n, 1 << n == 2^n.
Proof.
intros n. destruct (le_gt_cases 0 n).
now rewrite shiftl_mul_pow2, mul_1_l.
rewrite shiftl_div_pow2, div_1_l, pow_neg_r; try order.
apply pow_gt_1. order'. now apply opp_pos_neg.
Qed.
Lemma shiftl_0_r : forall a, a << 0 == a.
Proof.
intros. rewrite shiftl_mul_pow2 by order. now nzsimpl.
Qed.
Lemma shiftr_0_r : forall a, a >> 0 == a.
Proof.
intros. now rewrite <- shiftl_opp_r, opp_0, shiftl_0_r.
Qed.
Lemma shiftl_0_l : forall n, 0 << n == 0.
Proof.
intros.
destruct (le_ge_cases 0 n).
rewrite shiftl_mul_pow2 by trivial. now nzsimpl.
rewrite shiftl_div_pow2 by trivial.
rewrite <- opp_nonneg_nonpos in H. nzsimpl; order_nz.
Qed.
Lemma shiftr_0_l : forall n, 0 >> n == 0.
Proof.
intros. now rewrite <- shiftl_opp_r, shiftl_0_l.
Qed.
Lemma shiftl_eq_0_iff : forall a n, 0<=n -> (a << n == 0 <-> a == 0).
Proof.
intros a n Hn.
rewrite shiftl_mul_pow2 by trivial. rewrite eq_mul_0. split.
intros [H | H]; trivial. contradict H; order_nz.
intros H. now left.
Qed.
Lemma shiftr_eq_0_iff : forall a n,
a >> n == 0 <-> a==0 \/ (0<a /\ log2 a < n).
Proof.
intros a n.
destruct (le_gt_cases 0 n) as [Hn|Hn].
rewrite shiftr_div_pow2, div_small_iff by order_nz.
destruct (lt_trichotomy a 0) as [LT|[EQ|LT]].
split.
intros [(H,_)|(H,H')]. order. generalize (pow_nonneg 2 n le_0_2); order.
intros [H|(H,H')]; order.
rewrite EQ. split. now left. intros _; left. split; order_pos.
split. intros [(H,H')|(H,H')]; right. split; trivial.
apply log2_lt_pow2; trivial.
generalize (pow_nonneg 2 n le_0_2); order.
intros [H|(H,H')]. order. left.
split. order. now apply log2_lt_pow2.
rewrite shiftr_mul_pow2 by order. rewrite eq_mul_0.
split; intros [H|H].
now left.
elim (pow_nonzero 2 (-n)); try apply opp_nonneg_nonpos; order'.
now left.
destruct H. generalize (log2_nonneg a); order.
Qed.
Lemma shiftr_eq_0 : forall a n, 0<=a -> log2 a < n -> a >> n == 0.
Proof.
intros a n Ha H. apply shiftr_eq_0_iff.
le_elim Ha. right. now split. now left.
Qed.
(** Properties of [div2]. *)
Lemma div2_div : forall a, div2 a == a/2.
Proof.
intros. rewrite div2_spec, shiftr_div_pow2. now nzsimpl. order'.
Qed.
Instance div2_wd : Proper (eq==>eq) div2.
Proof.
intros a a' Ha. now rewrite 2 div2_div, Ha.
Qed.
Lemma div2_odd : forall a, a == 2*(div2 a) + odd a.
Proof.
intros a. rewrite div2_div, <- bit0_odd, bit0_mod.
apply div_mod. order'.
Qed.
(** Properties of [lxor] and others, directly deduced
from properties of [xorb] and others. *)
Instance lxor_wd : Proper (eq ==> eq ==> eq) lxor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance land_wd : Proper (eq ==> eq ==> eq) land.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance lor_wd : Proper (eq ==> eq ==> eq) lor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance ldiff_wd : Proper (eq ==> eq ==> eq) ldiff.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Lemma lxor_eq : forall a a', lxor a a' == 0 -> a == a'.
Proof.
intros a a' H. bitwise. apply xorb_eq.
now rewrite <- lxor_spec, H, bits_0.
Qed.
Lemma lxor_nilpotent : forall a, lxor a a == 0.
Proof.
intros. bitwise. apply xorb_nilpotent.
Qed.
Lemma lxor_eq_0_iff : forall a a', lxor a a' == 0 <-> a == a'.
Proof.
split. apply lxor_eq. intros EQ; rewrite EQ; apply lxor_nilpotent.
Qed.
Lemma lxor_0_l : forall a, lxor 0 a == a.
Proof.
intros. bitwise. apply xorb_false_l.
Qed.
Lemma lxor_0_r : forall a, lxor a 0 == a.
Proof.
intros. bitwise. apply xorb_false_r.
Qed.
Lemma lxor_comm : forall a b, lxor a b == lxor b a.
Proof.
intros. bitwise. apply xorb_comm.
Qed.
Lemma lxor_assoc :
forall a b c, lxor (lxor a b) c == lxor a (lxor b c).
Proof.
intros. bitwise. apply xorb_assoc.
Qed.
Lemma lor_0_l : forall a, lor 0 a == a.
Proof.
intros. bitwise. trivial.
Qed.
Lemma lor_0_r : forall a, lor a 0 == a.
Proof.
intros. bitwise. apply orb_false_r.
Qed.
Lemma lor_comm : forall a b, lor a b == lor b a.
Proof.
intros. bitwise. apply orb_comm.
Qed.
Lemma lor_assoc :
forall a b c, lor a (lor b c) == lor (lor a b) c.
Proof.
intros. bitwise. apply orb_assoc.
Qed.
Lemma lor_diag : forall a, lor a a == a.
Proof.
intros. bitwise. apply orb_diag.
Qed.
Lemma lor_eq_0_l : forall a b, lor a b == 0 -> a == 0.
Proof.
intros a b H. bitwise.
apply (orb_false_iff a.[m] b.[m]).
now rewrite <- lor_spec, H, bits_0.
Qed.
Lemma lor_eq_0_iff : forall a b, lor a b == 0 <-> a == 0 /\ b == 0.
Proof.
intros a b. split.
split. now apply lor_eq_0_l in H.
rewrite lor_comm in H. now apply lor_eq_0_l in H.
intros (EQ,EQ'). now rewrite EQ, lor_0_l.
Qed.
Lemma land_0_l : forall a, land 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma land_0_r : forall a, land a 0 == 0.
Proof.
intros. bitwise. apply andb_false_r.
Qed.
Lemma land_comm : forall a b, land a b == land b a.
Proof.
intros. bitwise. apply andb_comm.
Qed.
Lemma land_assoc :
forall a b c, land a (land b c) == land (land a b) c.
Proof.
intros. bitwise. apply andb_assoc.
Qed.
Lemma land_diag : forall a, land a a == a.
Proof.
intros. bitwise. apply andb_diag.
Qed.
Lemma ldiff_0_l : forall a, ldiff 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma ldiff_0_r : forall a, ldiff a 0 == a.
Proof.
intros. bitwise. now rewrite andb_true_r.
Qed.
Lemma ldiff_diag : forall a, ldiff a a == 0.
Proof.
intros. bitwise. apply andb_negb_r.
Qed.
Lemma lor_land_distr_l : forall a b c,
lor (land a b) c == land (lor a c) (lor b c).
Proof.
intros. bitwise. apply orb_andb_distrib_l.
Qed.
Lemma lor_land_distr_r : forall a b c,
lor a (land b c) == land (lor a b) (lor a c).
Proof.
intros. bitwise. apply orb_andb_distrib_r.
Qed.
Lemma land_lor_distr_l : forall a b c,
land (lor a b) c == lor (land a c) (land b c).
Proof.
intros. bitwise. apply andb_orb_distrib_l.
Qed.
Lemma land_lor_distr_r : forall a b c,
land a (lor b c) == lor (land a b) (land a c).
Proof.
intros. bitwise. apply andb_orb_distrib_r.
Qed.
Lemma ldiff_ldiff_l : forall a b c,
ldiff (ldiff a b) c == ldiff a (lor b c).
Proof.
intros. bitwise. now rewrite negb_orb, andb_assoc.
Qed.
Lemma lor_ldiff_and : forall a b,
lor (ldiff a b) (land a b) == a.
Proof.
intros. bitwise.
now rewrite <- andb_orb_distrib_r, orb_comm, orb_negb_r, andb_true_r.
Qed.
Lemma land_ldiff : forall a b,
land (ldiff a b) b == 0.
Proof.
intros. bitwise.
now rewrite <-andb_assoc, (andb_comm (negb _)), andb_negb_r, andb_false_r.
Qed.
(** Properties of [setbit] and [clearbit] *)
Definition setbit a n := lor a (1 << n).
Definition clearbit a n := ldiff a (1 << n).
Lemma setbit_spec' : forall a n, setbit a n == lor a (2^n).
Proof.
intros. unfold setbit. now rewrite shiftl_1_l.
Qed.
Lemma clearbit_spec' : forall a n, clearbit a n == ldiff a (2^n).
Proof.
intros. unfold clearbit. now rewrite shiftl_1_l.
Qed.
Instance setbit_wd : Proper (eq==>eq==>eq) setbit.
Proof. unfold setbit. solve_proper. Qed.
Instance clearbit_wd : Proper (eq==>eq==>eq) clearbit.
Proof. unfold clearbit. solve_proper. Qed.
Lemma pow2_bits_true : forall n, 0<=n -> (2^n).[n] = true.
Proof.
intros. rewrite <- (mul_1_l (2^n)).
now rewrite mul_pow2_bits, sub_diag, bit0_odd, odd_1.
Qed.
Lemma pow2_bits_false : forall n m, n~=m -> (2^n).[m] = false.
Proof.
intros.
destruct (le_gt_cases 0 n); [|now rewrite pow_neg_r, bits_0].
destruct (le_gt_cases n m).
rewrite <- (mul_1_l (2^n)), mul_pow2_bits; trivial.
rewrite <- (succ_pred (m-n)), <- div2_bits.
now rewrite div_small, bits_0 by (split; order').
rewrite <- lt_succ_r, succ_pred, lt_0_sub. order.
rewrite <- (mul_1_l (2^n)), mul_pow2_bits_low; trivial.
Qed.
Lemma pow2_bits_eqb : forall n m, 0<=n -> (2^n).[m] = eqb n m.
Proof.
intros n m Hn. apply eq_true_iff_eq. rewrite eqb_eq. split.
destruct (eq_decidable n m) as [H|H]. trivial.
now rewrite (pow2_bits_false _ _ H).
intros EQ. rewrite EQ. apply pow2_bits_true; order.
Qed.
Lemma setbit_eqb : forall a n m, 0<=n ->
(setbit a n).[m] = eqb n m || a.[m].
Proof.
intros. now rewrite setbit_spec', lor_spec, pow2_bits_eqb, orb_comm.
Qed.
Lemma setbit_iff : forall a n m, 0<=n ->
((setbit a n).[m] = true <-> n==m \/ a.[m] = true).
Proof.
intros. now rewrite setbit_eqb, orb_true_iff, eqb_eq.
Qed.
Lemma setbit_eq : forall a n, 0<=n -> (setbit a n).[n] = true.
Proof.
intros. apply setbit_iff; trivial. now left.
Qed.
Lemma setbit_neq : forall a n m, 0<=n -> n~=m ->
(setbit a n).[m] = a.[m].
Proof.
intros a n m Hn H. rewrite setbit_eqb; trivial.
rewrite <- eqb_eq in H. apply not_true_is_false in H. now rewrite H.
Qed.
Lemma clearbit_eqb : forall a n m,
(clearbit a n).[m] = a.[m] && negb (eqb n m).
Proof.
intros.
destruct (le_gt_cases 0 m); [| now rewrite 2 testbit_neg_r].
rewrite clearbit_spec', ldiff_spec. f_equal. f_equal.
destruct (le_gt_cases 0 n) as [Hn|Hn].
now apply pow2_bits_eqb.
symmetry. rewrite pow_neg_r, bits_0, <- not_true_iff_false, eqb_eq; order.
Qed.
Lemma clearbit_iff : forall a n m,
(clearbit a n).[m] = true <-> a.[m] = true /\ n~=m.
Proof.
intros. rewrite clearbit_eqb, andb_true_iff, <- eqb_eq.
now rewrite negb_true_iff, not_true_iff_false.
Qed.
Lemma clearbit_eq : forall a n, (clearbit a n).[n] = false.
Proof.
intros. rewrite clearbit_eqb, (proj2 (eqb_eq _ _) (eq_refl n)).
apply andb_false_r.
Qed.
Lemma clearbit_neq : forall a n m, n~=m ->
(clearbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite clearbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. rewrite H.
apply andb_true_r.
Qed.
(** Shifts of bitwise operations *)
Lemma shiftl_lxor : forall a b n,
(lxor a b) << n == lxor (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, lxor_spec.
Qed.
Lemma shiftr_lxor : forall a b n,
(lxor a b) >> n == lxor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, lxor_spec.
Qed.
Lemma shiftl_land : forall a b n,
(land a b) << n == land (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, land_spec.
Qed.
Lemma shiftr_land : forall a b n,
(land a b) >> n == land (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, land_spec.
Qed.
Lemma shiftl_lor : forall a b n,
(lor a b) << n == lor (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, lor_spec.
Qed.
Lemma shiftr_lor : forall a b n,
(lor a b) >> n == lor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, lor_spec.
Qed.
Lemma shiftl_ldiff : forall a b n,
(ldiff a b) << n == ldiff (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, ldiff_spec.
Qed.
Lemma shiftr_ldiff : forall a b n,
(ldiff a b) >> n == ldiff (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, ldiff_spec.
Qed.
(** For integers, we do have a binary complement function *)
Definition lnot a := P (-a).
Instance lnot_wd : Proper (eq==>eq) lnot.
Proof. unfold lnot. solve_proper. Qed.
Lemma lnot_spec : forall a n, 0<=n -> (lnot a).[n] = negb a.[n].
Proof.
intros. unfold lnot. rewrite <- (opp_involutive a) at 2.
rewrite bits_opp, negb_involutive; trivial.
Qed.
Lemma lnot_involutive : forall a, lnot (lnot a) == a.
Proof.
intros a. bitwise. now rewrite 2 lnot_spec, negb_involutive.
Qed.
Lemma lnot_0 : lnot 0 == -1.
Proof.
unfold lnot. now rewrite opp_0, <- sub_1_r, sub_0_l.
Qed.
Lemma lnot_m1 : lnot (-1) == 0.
Proof.
unfold lnot. now rewrite opp_involutive, one_succ, pred_succ.
Qed.
(** Complement and other operations *)
Lemma lor_m1_r : forall a, lor a (-1) == -1.
Proof.
intros. bitwise. now rewrite bits_m1, orb_true_r.
Qed.
Lemma lor_m1_l : forall a, lor (-1) a == -1.
Proof.
intros. now rewrite lor_comm, lor_m1_r.
Qed.
Lemma land_m1_r : forall a, land a (-1) == a.
Proof.
intros. bitwise. now rewrite bits_m1, andb_true_r.
Qed.
Lemma land_m1_l : forall a, land (-1) a == a.
Proof.
intros. now rewrite land_comm, land_m1_r.
Qed.
Lemma ldiff_m1_r : forall a, ldiff a (-1) == 0.
Proof.
intros. bitwise. now rewrite bits_m1, andb_false_r.
Qed.
Lemma ldiff_m1_l : forall a, ldiff (-1) a == lnot a.
Proof.
intros. bitwise. now rewrite lnot_spec, bits_m1.
Qed.
Lemma lor_lnot_diag : forall a, lor a (lnot a) == -1.
Proof.
intros a. bitwise. rewrite lnot_spec, bits_m1; trivial.
now destruct a.[m].
Qed.
Lemma add_lnot_diag : forall a, a + lnot a == -1.
Proof.
intros a. unfold lnot.
now rewrite add_pred_r, add_opp_r, sub_diag, one_succ, opp_succ, opp_0.
Qed.
Lemma ldiff_land : forall a b, ldiff a b == land a (lnot b).
Proof.
intros. bitwise. now rewrite lnot_spec.
Qed.
Lemma land_lnot_diag : forall a, land a (lnot a) == 0.
Proof.
intros. now rewrite <- ldiff_land, ldiff_diag.
Qed.
Lemma lnot_lor : forall a b, lnot (lor a b) == land (lnot a) (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, lor_spec, negb_orb.
Qed.
Lemma lnot_land : forall a b, lnot (land a b) == lor (lnot a) (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, land_spec, negb_andb.
Qed.
Lemma lnot_ldiff : forall a b, lnot (ldiff a b) == lor (lnot a) b.
Proof.
intros a b. bitwise.
now rewrite !lnot_spec, ldiff_spec, negb_andb, negb_involutive.
Qed.
Lemma lxor_lnot_lnot : forall a b, lxor (lnot a) (lnot b) == lxor a b.
Proof.
intros a b. bitwise. now rewrite !lnot_spec, xorb_negb_negb.
Qed.
Lemma lnot_lxor_l : forall a b, lnot (lxor a b) == lxor (lnot a) b.
Proof.
intros a b. bitwise. now rewrite !lnot_spec, !lxor_spec, negb_xorb_l.
Qed.
Lemma lnot_lxor_r : forall a b, lnot (lxor a b) == lxor a (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, !lxor_spec, negb_xorb_r.
Qed.
Lemma lxor_m1_r : forall a, lxor a (-1) == lnot a.
Proof.
intros. now rewrite <- (lxor_0_r (lnot a)), <- lnot_m1, lxor_lnot_lnot.
Qed.
Lemma lxor_m1_l : forall a, lxor (-1) a == lnot a.
Proof.
intros. now rewrite lxor_comm, lxor_m1_r.
Qed.
Lemma lxor_lor : forall a b, land a b == 0 ->
lxor a b == lor a b.
Proof.
intros a b H. bitwise.
assert (a.[m] && b.[m] = false)
by now rewrite <- land_spec, H, bits_0.
now destruct a.[m], b.[m].
Qed.
Lemma lnot_shiftr : forall a n, 0<=n -> lnot (a >> n) == (lnot a) >> n.
Proof.
intros a n Hn. bitwise.
now rewrite lnot_spec, 2 shiftr_spec, lnot_spec by order_pos.
Qed.
(** [(ones n)] is [2^n-1], the number with [n] digits 1 *)
Definition ones n := P (1<<n).
Instance ones_wd : Proper (eq==>eq) ones.
Proof. unfold ones. solve_proper. Qed.
Lemma ones_equiv : forall n, ones n == P (2^n).
Proof.
intros. unfold ones.
destruct (le_gt_cases 0 n).
now rewrite shiftl_mul_pow2, mul_1_l.
f_equiv. rewrite pow_neg_r; trivial.
rewrite <- shiftr_opp_r. apply shiftr_eq_0_iff. right; split.
order'. rewrite log2_1. now apply opp_pos_neg.
Qed.
Lemma ones_add : forall n m, 0<=n -> 0<=m ->
ones (m+n) == 2^m * ones n + ones m.
Proof.
intros n m Hn Hm. rewrite !ones_equiv.
rewrite <- !sub_1_r, mul_sub_distr_l, mul_1_r, <- pow_add_r by trivial.
rewrite add_sub_assoc, sub_add. reflexivity.
Qed.
Lemma ones_div_pow2 : forall n m, 0<=m<=n -> ones n / 2^m == ones (n-m).
Proof.
intros n m (Hm,H). symmetry. apply div_unique with (ones m).
left. rewrite ones_equiv. split.
rewrite <- lt_succ_r, succ_pred. order_pos.
now rewrite <- le_succ_l, succ_pred.
rewrite <- (sub_add m n) at 1. rewrite (add_comm _ m).
apply ones_add; trivial. now apply le_0_sub.
Qed.
Lemma ones_mod_pow2 : forall n m, 0<=m<=n -> (ones n) mod (2^m) == ones m.
Proof.
intros n m (Hm,H). symmetry. apply mod_unique with (ones (n-m)).
left. rewrite ones_equiv. split.
rewrite <- lt_succ_r, succ_pred. order_pos.
now rewrite <- le_succ_l, succ_pred.
rewrite <- (sub_add m n) at 1. rewrite (add_comm _ m).
apply ones_add; trivial. now apply le_0_sub.
Qed.
Lemma ones_spec_low : forall n m, 0<=m<n -> (ones n).[m] = true.
Proof.
intros n m (Hm,H). apply testbit_true; trivial.
rewrite ones_div_pow2 by (split; order).
rewrite <- (pow_1_r 2). rewrite ones_mod_pow2.
rewrite ones_equiv. now nzsimpl'.
split. order'. apply le_add_le_sub_r. nzsimpl. now apply le_succ_l.
Qed.
Lemma ones_spec_high : forall n m, 0<=n<=m -> (ones n).[m] = false.
Proof.
intros n m (Hn,H). le_elim Hn.
apply bits_above_log2; rewrite ones_equiv.
rewrite <-lt_succ_r, succ_pred; order_pos.
rewrite log2_pred_pow2; trivial. now rewrite <-le_succ_l, succ_pred.
rewrite ones_equiv. now rewrite <- Hn, pow_0_r, one_succ, pred_succ, bits_0.
Qed.
Lemma ones_spec_iff : forall n m, 0<=n ->
((ones n).[m] = true <-> 0<=m<n).
Proof.
intros n m Hn. split. intros H.
destruct (lt_ge_cases m 0) as [Hm|Hm].
now rewrite testbit_neg_r in H.
split; trivial. apply lt_nge. intro H'. rewrite ones_spec_high in H.
discriminate. now split.
apply ones_spec_low.
Qed.
Lemma lor_ones_low : forall a n, 0<=a -> log2 a < n ->
lor a (ones n) == ones n.
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; try split; trivial.
now apply lt_le_trans with n.
apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, orb_true_r; try split; trivial.
Qed.
Lemma land_ones : forall a n, 0<=n -> land a (ones n) == a mod 2^n.
Proof.
intros a n Hn. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, mod_pow2_bits_high, andb_false_r;
try split; trivial.
rewrite ones_spec_low, mod_pow2_bits_low, andb_true_r;
try split; trivial.
Qed.
Lemma land_ones_low : forall a n, 0<=a -> log2 a < n ->
land a (ones n) == a.
Proof.
intros a n Ha H.
assert (Hn : 0<=n) by (generalize (log2_nonneg a); order).
rewrite land_ones; trivial. apply mod_small.
split; trivial.
apply log2_lt_cancel. now rewrite log2_pow2.
Qed.
Lemma ldiff_ones_r : forall a n, 0<=n ->
ldiff a (ones n) == (a >> n) << n.
Proof.
intros a n Hn. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, shiftl_spec_high, shiftr_spec; trivial.
rewrite sub_add; trivial. apply andb_true_r.
now apply le_0_sub.
now split.
rewrite ones_spec_low, shiftl_spec_low, andb_false_r;
try split; trivial.
Qed.
Lemma ldiff_ones_r_low : forall a n, 0<=a -> log2 a < n ->
ldiff a (ones n) == 0.
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
split; trivial. now apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, andb_false_r; try split; trivial.
Qed.
Lemma ldiff_ones_l_low : forall a n, 0<=a -> log2 a < n ->
ldiff (ones n) a == lxor a (ones n).
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
split; trivial. now apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, xorb_true_r; try split; trivial.
Qed.
(** Bitwise operations and sign *)
Lemma shiftl_nonneg : forall a n, 0 <= (a << n) <-> 0 <= a.
Proof.
intros a n.
destruct (le_ge_cases 0 n) as [Hn|Hn].
(* 0<=n *)
rewrite 2 bits_iff_nonneg_ex. split; intros (k,Hk).
exists (k-n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite <- (add_simpl_r m n), <- (shiftl_spec a n) by order_pos.
apply Hk. now apply lt_sub_lt_add_r.
exists (k+n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftl_spec by trivial. apply Hk. now apply lt_add_lt_sub_r.
(* n<=0*)
rewrite <- shiftr_opp_r, 2 bits_iff_nonneg_ex. split; intros (k,Hk).
destruct (le_gt_cases 0 k).
exists (k-n). intros m Hm. apply lt_sub_lt_add_r in Hm.
rewrite <- (add_simpl_r m n), <- add_opp_r, <- (shiftr_spec a (-n)).
now apply Hk. order.
assert (EQ : a >> (-n) == 0).
apply bits_inj'. intros m Hm. rewrite bits_0. apply Hk; order.
apply shiftr_eq_0_iff in EQ.
rewrite <- bits_iff_nonneg_ex. destruct EQ as [EQ|[LT _]]; order.
exists (k+n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftr_spec by trivial. apply Hk.
rewrite add_opp_r. now apply lt_add_lt_sub_r.
Qed.
Lemma shiftl_neg : forall a n, (a << n) < 0 <-> a < 0.
Proof.
intros a n. now rewrite 2 lt_nge, shiftl_nonneg.
Qed.
Lemma shiftr_nonneg : forall a n, 0 <= (a >> n) <-> 0 <= a.
Proof.
intros. rewrite <- shiftl_opp_r. apply shiftl_nonneg.
Qed.
Lemma shiftr_neg : forall a n, (a >> n) < 0 <-> a < 0.
Proof.
intros a n. now rewrite 2 lt_nge, shiftr_nonneg.
Qed.
Lemma div2_nonneg : forall a, 0 <= div2 a <-> 0 <= a.
Proof.
intros. rewrite div2_spec. apply shiftr_nonneg.
Qed.
Lemma div2_neg : forall a, div2 a < 0 <-> a < 0.
Proof.
intros a. now rewrite 2 lt_nge, div2_nonneg.
Qed.
Lemma lor_nonneg : forall a b, 0 <= lor a b <-> 0<=a /\ 0<=b.
Proof.
intros a b.
rewrite 3 bits_iff_nonneg_ex. split. intros (k,Hk).
split; exists k; intros m Hm; apply (orb_false_elim a.[m] b.[m]);
rewrite <- lor_spec; now apply Hk.
intros ((k,Hk),(k',Hk')).
destruct (le_ge_cases k k'); [ exists k' | exists k ];
intros m Hm; rewrite lor_spec, Hk, Hk'; trivial; order.
Qed.
Lemma lor_neg : forall a b, lor a b < 0 <-> a < 0 \/ b < 0.
Proof.
intros a b. rewrite 3 lt_nge, lor_nonneg. split.
apply not_and. apply le_decidable.
now intros [H|H] (H',H'').
Qed.
Lemma lnot_nonneg : forall a, 0 <= lnot a <-> a < 0.
Proof.
intros a; unfold lnot.
now rewrite <- opp_succ, opp_nonneg_nonpos, le_succ_l.
Qed.
Lemma lnot_neg : forall a, lnot a < 0 <-> 0 <= a.
Proof.
intros a. now rewrite le_ngt, lt_nge, lnot_nonneg.
Qed.
Lemma land_nonneg : forall a b, 0 <= land a b <-> 0<=a \/ 0<=b.
Proof.
intros a b.
now rewrite <- (lnot_involutive (land a b)), lnot_land, lnot_nonneg,
lor_neg, !lnot_neg.
Qed.
Lemma land_neg : forall a b, land a b < 0 <-> a < 0 /\ b < 0.
Proof.
intros a b.
now rewrite <- (lnot_involutive (land a b)), lnot_land, lnot_neg,
lor_nonneg, !lnot_nonneg.
Qed.
Lemma ldiff_nonneg : forall a b, 0 <= ldiff a b <-> 0<=a \/ b<0.
Proof.
intros. now rewrite ldiff_land, land_nonneg, lnot_nonneg.
Qed.
Lemma ldiff_neg : forall a b, ldiff a b < 0 <-> a<0 /\ 0<=b.
Proof.
intros. now rewrite ldiff_land, land_neg, lnot_neg.
Qed.
Lemma lxor_nonneg : forall a b, 0 <= lxor a b <-> (0<=a <-> 0<=b).
Proof.
assert (H : forall a b, 0<=a -> 0<=b -> 0<=lxor a b).
intros a b. rewrite 3 bits_iff_nonneg_ex. intros (k,Hk) (k', Hk').
destruct (le_ge_cases k k'); [ exists k' | exists k];
intros m Hm; rewrite lxor_spec, Hk, Hk'; trivial; order.
assert (H' : forall a b, 0<=a -> b<0 -> lxor a b<0).
intros a b. rewrite bits_iff_nonneg_ex, 2 bits_iff_neg_ex.
intros (k,Hk) (k', Hk').
destruct (le_ge_cases k k'); [ exists k' | exists k];
intros m Hm; rewrite lxor_spec, Hk, Hk'; trivial; order.
intros a b.
split.
intros Hab. split.
intros Ha. destruct (le_gt_cases 0 b) as [Hb|Hb]; trivial.
generalize (H' _ _ Ha Hb). order.
intros Hb. destruct (le_gt_cases 0 a) as [Ha|Ha]; trivial.
generalize (H' _ _ Hb Ha). rewrite lxor_comm. order.
intros E.
destruct (le_gt_cases 0 a) as [Ha|Ha]. apply H; trivial. apply E; trivial.
destruct (le_gt_cases 0 b) as [Hb|Hb]. apply H; trivial. apply E; trivial.
rewrite <- lxor_lnot_lnot. apply H; now apply lnot_nonneg.
Qed.
(** Bitwise operations and log2 *)
Lemma log2_bits_unique : forall a n,
a.[n] = true ->
(forall m, n<m -> a.[m] = false) ->
log2 a == n.
Proof.
intros a n H H'.
destruct (lt_trichotomy a 0) as [Ha|[Ha|Ha]].
(* a < 0 *)
destruct (proj1 (bits_iff_neg_ex a) Ha) as (k,Hk).
destruct (le_gt_cases n k).
specialize (Hk (S k) (lt_succ_diag_r _)).
rewrite H' in Hk. discriminate. apply lt_succ_r; order.
specialize (H' (S n) (lt_succ_diag_r _)).
rewrite Hk in H'. discriminate. apply lt_succ_r; order.
(* a = 0 *)
now rewrite Ha, bits_0 in H.
(* 0 < a *)
apply le_antisymm; apply le_ngt; intros LT.
specialize (H' _ LT). now rewrite bit_log2 in H'.
now rewrite bits_above_log2 in H by order.
Qed.
Lemma log2_shiftr : forall a n, 0<a -> log2 (a >> n) == max 0 (log2 a - n).
Proof.
intros a n Ha.
destruct (le_gt_cases 0 (log2 a - n));
[rewrite max_r | rewrite max_l]; try order.
apply log2_bits_unique.
now rewrite shiftr_spec, sub_add, bit_log2.
intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftr_spec; trivial. apply bits_above_log2; try order.
now apply lt_sub_lt_add_r.
rewrite lt_sub_lt_add_r, add_0_l in H.
apply log2_nonpos. apply le_lteq; right.
apply shiftr_eq_0_iff. right. now split.
Qed.
Lemma log2_shiftl : forall a n, 0<a -> 0<=n -> log2 (a << n) == log2 a + n.
Proof.
intros a n Ha Hn.
rewrite shiftl_mul_pow2, add_comm by trivial.
now apply log2_mul_pow2.
Qed.
Lemma log2_shiftl' : forall a n, 0<a -> log2 (a << n) == max 0 (log2 a + n).
Proof.
intros a n Ha.
rewrite <- shiftr_opp_r, log2_shiftr by trivial.
destruct (le_gt_cases 0 (log2 a + n));
[rewrite 2 max_r | rewrite 2 max_l]; rewrite ?sub_opp_r; try order.
Qed.
Lemma log2_lor : forall a b, 0<=a -> 0<=b ->
log2 (lor a b) == max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (lor a b) == log2 b).
intros a b Ha H.
le_elim Ha; [|now rewrite <- Ha, lor_0_l].
apply log2_bits_unique.
now rewrite lor_spec, bit_log2, orb_true_r by order.
intros m Hm. assert (H' := log2_le_mono _ _ H).
now rewrite lor_spec, 2 bits_above_log2 by order.
(* main *)
intros a b Ha Hb. destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono.
now apply AUX.
rewrite max_l by now apply log2_le_mono.
rewrite lor_comm. now apply AUX.
Qed.
Lemma log2_land : forall a b, 0<=a -> 0<=b ->
log2 (land a b) <= min (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (land a b) <= log2 a).
intros a b Ha Hb.
apply le_ngt. intros LT.
assert (H : 0 <= land a b) by (apply land_nonneg; now left).
le_elim H.
generalize (bit_log2 (land a b) H).
now rewrite land_spec, bits_above_log2.
rewrite <- H in LT. apply log2_lt_cancel in LT; order.
(* main *)
intros a b Ha Hb.
destruct (le_ge_cases a b) as [H|H].
rewrite min_l by now apply log2_le_mono. now apply AUX.
rewrite min_r by now apply log2_le_mono. rewrite land_comm. now apply AUX.
Qed.
Lemma log2_lxor : forall a b, 0<=a -> 0<=b ->
log2 (lxor a b) <= max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (lxor a b) <= log2 b).
intros a b Ha Hb.
apply le_ngt. intros LT.
assert (H : 0 <= lxor a b) by (apply lxor_nonneg; split; order).
le_elim H.
generalize (bit_log2 (lxor a b) H).
rewrite lxor_spec, 2 bits_above_log2; try order. discriminate.
apply le_lt_trans with (log2 b); trivial. now apply log2_le_mono.
rewrite <- H in LT. apply log2_lt_cancel in LT; order.
(* main *)
intros a b Ha Hb.
destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono. now apply AUX.
rewrite max_l by now apply log2_le_mono. rewrite lxor_comm. now apply AUX.
Qed.
(** Bitwise operations and arithmetical operations *)
Local Notation xor3 a b c := (xorb (xorb a b) c).
Local Notation lxor3 a b c := (lxor (lxor a b) c).
Local Notation nextcarry a b c := ((a&&b) || (c && (a||b))).
Local Notation lnextcarry a b c := (lor (land a b) (land c (lor a b))).
Lemma add_bit0 : forall a b, (a+b).[0] = xorb a.[0] b.[0].
Proof.
intros. now rewrite !bit0_odd, odd_add.
Qed.
Lemma add3_bit0 : forall a b c,
(a+b+c).[0] = xor3 a.[0] b.[0] c.[0].
Proof.
intros. now rewrite !add_bit0.
Qed.
Lemma add3_bits_div2 : forall (a0 b0 c0 : bool),
(a0 + b0 + c0)/2 == nextcarry a0 b0 c0.
Proof.
assert (H : 1+1 == 2) by now nzsimpl'.
intros [|] [|] [|]; simpl; rewrite ?add_0_l, ?add_0_r, ?H;
(apply div_same; order') || (apply div_small; split; order') || idtac.
symmetry. apply div_unique with 1. left; split; order'. now nzsimpl'.
Qed.
Lemma add_carry_div2 : forall a b (c0:bool),
(a + b + c0)/2 == a/2 + b/2 + nextcarry a.[0] b.[0] c0.
Proof.
intros.
rewrite <- add3_bits_div2.
rewrite (add_comm ((a/2)+_)).
rewrite <- div_add by order'.
f_equiv.
rewrite <- !div2_div, mul_comm, mul_add_distr_l.
rewrite (div2_odd a), <- bit0_odd at 1.
rewrite (div2_odd b), <- bit0_odd at 1.
rewrite add_shuffle1.
rewrite <-(add_assoc _ _ c0). apply add_comm.
Qed.
(** The main result concerning addition: we express the bits of the sum
in term of bits of [a] and [b] and of some carry stream which is also
recursively determined by another equation.
*)
Lemma add_carry_bits_aux : forall n, 0<=n ->
forall a b (c0:bool), -(2^n) <= a < 2^n -> -(2^n) <= b < 2^n ->
exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros n Hn. apply le_ind with (4:=Hn).
solve_proper.
(* base *)
intros a b c0. rewrite !pow_0_r, !one_succ, !lt_succ_r, <- !one_succ.
intros (Ha1,Ha2) (Hb1,Hb2).
le_elim Ha1; rewrite <- ?le_succ_l, ?succ_m1 in Ha1;
le_elim Hb1; rewrite <- ?le_succ_l, ?succ_m1 in Hb1.
(* base, a = 0, b = 0 *)
exists c0.
rewrite (le_antisymm _ _ Ha2 Ha1), (le_antisymm _ _ Hb2 Hb1).
rewrite !add_0_l, !lxor_0_l, !lor_0_r, !land_0_r, !lor_0_r.
rewrite b2z_div2, b2z_bit0; now repeat split.
(* base, a = 0, b = -1 *)
exists (-c0). rewrite <- Hb1, (le_antisymm _ _ Ha2 Ha1). repeat split.
rewrite add_0_l, lxor_0_l, lxor_m1_l.
unfold lnot. now rewrite opp_involutive, add_comm, add_opp_r, sub_1_r.
rewrite land_0_l, !lor_0_l, land_m1_r.
symmetry. apply div_unique with c0. left; destruct c0; simpl; split; order'.
now rewrite two_succ, mul_succ_l, mul_1_l, add_opp_r, sub_add.
rewrite bit0_odd, odd_opp; destruct c0; simpl; apply odd_1 || apply odd_0.
(* base, a = -1, b = 0 *)
exists (-c0). rewrite <- Ha1, (le_antisymm _ _ Hb2 Hb1). repeat split.
rewrite add_0_r, lxor_0_r, lxor_m1_l.
unfold lnot. now rewrite opp_involutive, add_comm, add_opp_r, sub_1_r.
rewrite land_0_r, lor_0_r, lor_0_l, land_m1_r.
symmetry. apply div_unique with c0. left; destruct c0; simpl; split; order'.
now rewrite two_succ, mul_succ_l, mul_1_l, add_opp_r, sub_add.
rewrite bit0_odd, odd_opp; destruct c0; simpl; apply odd_1 || apply odd_0.
(* base, a = -1, b = -1 *)
exists (c0 + 2*(-1)). rewrite <- Ha1, <- Hb1. repeat split.
rewrite lxor_m1_l, lnot_m1, lxor_0_l.
now rewrite two_succ, mul_succ_l, mul_1_l, add_comm, add_assoc.
rewrite land_m1_l, lor_m1_l.
apply add_b2z_double_div2.
apply add_b2z_double_bit0.
(* step *)
clear n Hn. intros n Hn IH a b c0 Ha Hb.
set (c1:=nextcarry a.[0] b.[0] c0).
destruct (IH (a/2) (b/2) c1) as (c & IH1 & IH2 & Hc); clear IH.
split.
apply div_le_lower_bound. order'. now rewrite mul_opp_r, <- pow_succ_r.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
split.
apply div_le_lower_bound. order'. now rewrite mul_opp_r, <- pow_succ_r.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
exists (c0 + 2*c). repeat split.
(* step, add *)
bitwise.
le_elim Hm.
rewrite <- (succ_pred m), lt_succ_r in Hm.
rewrite <- (succ_pred m), <- !div2_bits, <- 2 lxor_spec by trivial.
f_equiv.
rewrite add_b2z_double_div2, <- IH1. apply add_carry_div2.
rewrite <- Hm.
now rewrite add_b2z_double_bit0, add3_bit0, b2z_bit0.
(* step, carry *)
rewrite add_b2z_double_div2.
bitwise.
le_elim Hm.
rewrite <- (succ_pred m), lt_succ_r in Hm.
rewrite <- (succ_pred m), <- !div2_bits, IH2 by trivial.
autorewrite with bitwise. now rewrite add_b2z_double_div2.
rewrite <- Hm.
now rewrite add_b2z_double_bit0.
(* step, carry0 *)
apply add_b2z_double_bit0.
Qed.
Lemma add_carry_bits : forall a b (c0:bool), exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros a b c0.
set (n := max (abs a) (abs b)).
apply (add_carry_bits_aux n).
(* positivity *)
unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; order_pos'.
(* bound for a *)
assert (Ha : abs a < 2^n).
apply lt_le_trans with (2^(abs a)). apply pow_gt_lin_r; order_pos'.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; try order.
apply abs_lt in Ha. destruct Ha; split; order.
(* bound for b *)
assert (Hb : abs b < 2^n).
apply lt_le_trans with (2^(abs b)). apply pow_gt_lin_r; order_pos'.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; try order.
apply abs_lt in Hb. destruct Hb; split; order.
Qed.
(** Particular case : the second bit of an addition *)
Lemma add_bit1 : forall a b,
(a+b).[1] = xor3 a.[1] b.[1] (a.[0] && b.[0]).
Proof.
intros a b.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
autorewrite with bitwise. f_equal.
rewrite one_succ, <- div2_bits, EQ2 by order.
autorewrite with bitwise.
rewrite Hc. simpl. apply orb_false_r.
Qed.
(** In an addition, there will be no carries iff there is
no common bits in the numbers to add *)
Lemma nocarry_equiv : forall a b c,
c/2 == lnextcarry a b c -> c.[0] = false ->
(c == 0 <-> land a b == 0).
Proof.
intros a b c H H'.
split. intros EQ; rewrite EQ in *.
rewrite div_0_l in H by order'.
symmetry in H. now apply lor_eq_0_l in H.
intros EQ. rewrite EQ, lor_0_l in H.
apply bits_inj'. intros n Hn. rewrite bits_0.
apply le_ind with (4:=Hn).
solve_proper.
trivial.
clear n Hn. intros n Hn IH.
rewrite <- div2_bits, H; trivial.
autorewrite with bitwise.
now rewrite IH.
Qed.
(** When there is no common bits, the addition is just a xor *)
Lemma add_nocarry_lxor : forall a b, land a b == 0 ->
a+b == lxor a b.
Proof.
intros a b H.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
apply (nocarry_equiv a b c) in H; trivial.
rewrite H. now rewrite lxor_0_r.
Qed.
(** A null [ldiff] implies being smaller *)
Lemma ldiff_le : forall a b, 0<=b -> ldiff a b == 0 -> 0 <= a <= b.
Proof.
assert (AUX : forall n, 0<=n ->
forall a b, 0 <= a < 2^n -> 0<=b -> ldiff a b == 0 -> a <= b).
intros n Hn. apply le_ind with (4:=Hn); clear n Hn.
solve_proper.
intros a b Ha Hb _. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
setoid_replace a with 0 by (destruct Ha; order'); trivial.
intros n Hn IH a b (Ha,Ha') Hb H.
assert (NEQ : 2 ~= 0) by order'.
rewrite (div_mod a 2 NEQ), (div_mod b 2 NEQ).
apply add_le_mono.
apply mul_le_mono_pos_l; try order'.
apply IH.
split. apply div_pos; order'.
apply div_lt_upper_bound; try order'. now rewrite <- pow_succ_r.
apply div_pos; order'.
rewrite <- (pow_1_r 2), <- 2 shiftr_div_pow2 by order'.
rewrite <- shiftr_ldiff, H, shiftr_div_pow2, pow_1_r, div_0_l; order'.
rewrite <- 2 bit0_mod.
apply bits_inj_iff in H. specialize (H 0).
rewrite ldiff_spec, bits_0 in H.
destruct a.[0], b.[0]; try discriminate; simpl; order'.
(* main *)
intros a b Hb Hd.
assert (Ha : 0<=a).
apply le_ngt; intros Ha'. apply (lt_irrefl 0). rewrite <- Hd at 1.
apply ldiff_neg. now split.
split; trivial. apply (AUX a); try split; trivial. apply pow_gt_lin_r; order'.
Qed.
(** Subtraction can be a ldiff when the opposite ldiff is null. *)
Lemma sub_nocarry_ldiff : forall a b, ldiff b a == 0 ->
a-b == ldiff a b.
Proof.
intros a b H.
apply add_cancel_r with b.
rewrite sub_add.
symmetry.
rewrite add_nocarry_lxor; trivial.
bitwise.
apply bits_inj_iff in H. specialize (H m).
rewrite ldiff_spec, bits_0 in H.
now destruct a.[m], b.[m].
apply land_ldiff.
Qed.
(** Adding numbers with no common bits cannot lead to a much bigger number *)
Lemma add_nocarry_lt_pow2 : forall a b n, land a b == 0 ->
a < 2^n -> b < 2^n -> a+b < 2^n.
Proof.
intros a b n H Ha Hb.
destruct (le_gt_cases a 0) as [Ha'|Ha'].
apply le_lt_trans with (0+b). now apply add_le_mono_r. now nzsimpl.
destruct (le_gt_cases b 0) as [Hb'|Hb'].
apply le_lt_trans with (a+0). now apply add_le_mono_l. now nzsimpl.
rewrite add_nocarry_lxor by order.
destruct (lt_ge_cases 0 (lxor a b)); [|apply le_lt_trans with 0; order_pos].
apply log2_lt_pow2; trivial.
apply log2_lt_pow2 in Ha; trivial.
apply log2_lt_pow2 in Hb; trivial.
apply le_lt_trans with (max (log2 a) (log2 b)).
apply log2_lxor; order.
destruct (le_ge_cases (log2 a) (log2 b));
[rewrite max_r|rewrite max_l]; order.
Qed.
Lemma add_nocarry_mod_lt_pow2 : forall a b n, 0<=n -> land a b == 0 ->
a mod 2^n + b mod 2^n < 2^n.
Proof.
intros a b n Hn H.
apply add_nocarry_lt_pow2.
bitwise.
destruct (le_gt_cases n m).
rewrite mod_pow2_bits_high; now split.
now rewrite !mod_pow2_bits_low, <- land_spec, H, bits_0.
apply mod_pos_bound; order_pos.
apply mod_pos_bound; order_pos.
Qed.
End ZBitsProp.
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_port_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the rx_engine and buffers the output
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module rx_port_128 #(
parameter C_DATA_WIDTH = 9'd128,
parameter C_MAIN_FIFO_DEPTH = 1024,
parameter C_SG_FIFO_DEPTH = 512,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),
parameter C_MAIN_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_MAIN_FIFO_DEPTH))+1),
parameter C_SG_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_SG_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input [31:0] SG_RX_BUF_DATA, // Scatter gather RX buffer data
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input [31:0] SG_TX_BUF_DATA, // Scatter gather TX buffer data
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
output [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather TX buffer data
output SG_DATA_EMPTY, // Scatter gather TX buffer data empty
input SG_DATA_REN, // Scatter gather TX buffer data read enable
input SG_RST, // Scatter gather TX buffer data reset
output SG_ERR, // Scatter gather TX encountered an error
input [31:0] TXN_DATA, // Read transaction data
input TXN_LEN_VALID, // Read transaction length valid
input TXN_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_DONE_LEN, // Read transaction actual transfer length
output TXN_DONE, // Read transaction done
input TXN_DONE_ACK, // Read transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
input [C_DATA_WIDTH-1:0] MAIN_DATA, // Main incoming data
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WIDTH-1:0] SG_RX_DATA, // Scatter gather for RX incoming data
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WIDTH-1:0] SG_TX_DATA, // Scatter gather for TX incoming data
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN // Channel read data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wPackedMainData;
wire wPackedMainWen;
wire wPackedMainDone;
wire wPackedMainErr;
wire wMainFlush;
wire wMainFlushed;
wire [C_DATA_WIDTH-1:0] wPackedSgRxData;
wire wPackedSgRxWen;
wire wPackedSgRxDone;
wire wPackedSgRxErr;
wire wSgRxFlush;
wire wSgRxFlushed;
wire [C_DATA_WIDTH-1:0] wPackedSgTxData;
wire wPackedSgTxWen;
wire wPackedSgTxDone;
wire wPackedSgTxErr;
wire wSgTxFlush;
wire wSgTxFlushed;
wire wMainDataRen;
wire wMainDataEmpty;
wire [C_DATA_WIDTH-1:0] wMainData;
wire wSgRxRst;
wire wSgRxDataRen;
wire wSgRxDataEmpty;
wire [C_DATA_WIDTH-1:0] wSgRxData;
wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgRxFifoCount;
wire wSgTxRst;
wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgTxFifoCount;
wire wSgRxReq;
wire [63:0] wSgRxReqAddr;
wire [9:0] wSgRxReqLen;
wire wSgTxReq;
wire [63:0] wSgTxReqAddr;
wire [9:0] wSgTxReqLen;
wire wSgRxReqProc;
wire wSgTxReqProc;
wire wMainReqProc;
wire wReqAck;
wire wSgElemRdy;
wire wSgElemRen;
wire [63:0] wSgElemAddr;
wire [31:0] wSgElemLen;
wire wSgRst;
wire wMainReq;
wire [63:0] wMainReqAddr;
wire [9:0] wMainReqLen;
wire wTxnErr;
wire wChnlRx;
wire wChnlRxRecvd;
wire wChnlRxAckRecvd;
wire wChnlRxLast;
wire [31:0] wChnlRxLen;
wire [30:0] wChnlRxOff;
wire [31:0] wChnlRxConsumed;
reg [4:0] rWideRst=0;
reg rRst=0;
assign SG_ERR = (wPackedSgTxDone & wPackedSgTxErr);
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Pack received data tightly into our FIFOs
fifo_packer_128 mainFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(MAIN_DATA),
.DATA_IN_EN(MAIN_DATA_EN),
.DATA_IN_DONE(MAIN_DONE),
.DATA_IN_ERR(MAIN_ERR),
.DATA_IN_FLUSH(wMainFlush),
.PACKED_DATA(wPackedMainData),
.PACKED_WEN(wPackedMainWen),
.PACKED_DATA_DONE(wPackedMainDone),
.PACKED_DATA_ERR(wPackedMainErr),
.PACKED_DATA_FLUSHED(wMainFlushed)
);
fifo_packer_128 sgRxFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(SG_RX_DATA),
.DATA_IN_EN(SG_RX_DATA_EN),
.DATA_IN_DONE(SG_RX_DONE),
.DATA_IN_ERR(SG_RX_ERR),
.DATA_IN_FLUSH(wSgRxFlush),
.PACKED_DATA(wPackedSgRxData),
.PACKED_WEN(wPackedSgRxWen),
.PACKED_DATA_DONE(wPackedSgRxDone),
.PACKED_DATA_ERR(wPackedSgRxErr),
.PACKED_DATA_FLUSHED(wSgRxFlushed)
);
fifo_packer_128 sgTxFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(SG_TX_DATA),
.DATA_IN_EN(SG_TX_DATA_EN),
.DATA_IN_DONE(SG_TX_DONE),
.DATA_IN_ERR(SG_TX_ERR),
.DATA_IN_FLUSH(wSgTxFlush),
.PACKED_DATA(wPackedSgTxData),
.PACKED_WEN(wPackedSgTxWen),
.PACKED_DATA_DONE(wPackedSgTxDone),
.PACKED_DATA_ERR(wPackedSgTxErr),
.PACKED_DATA_FLUSHED(wSgTxFlushed)
);
// FIFOs for storing received data for the channel.
(* RAM_STYLE="BLOCK" *)
async_fifo_fwft #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_MAIN_FIFO_DEPTH)) mainFifo (
.WR_CLK(CLK),
.WR_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
.WR_EN(wPackedMainWen),
.WR_DATA(wPackedMainData),
.WR_FULL(),
.RD_CLK(CHNL_CLK),
.RD_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
.RD_EN(wMainDataRen),
.RD_DATA(wMainData),
.RD_EMPTY(wMainDataEmpty)
);
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgRxFifo (
.RST(rRst | wSgRxRst),
.CLK(CLK),
.WR_EN(wPackedSgRxWen),
.WR_DATA(wPackedSgRxData),
.FULL(),
.RD_EN(wSgRxDataRen),
.RD_DATA(wSgRxData),
.EMPTY(wSgRxDataEmpty),
.COUNT(wSgRxFifoCount)
);
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgTxFifo (
.RST(rRst | wSgTxRst),
.CLK(CLK),
.WR_EN(wPackedSgTxWen),
.WR_DATA(wPackedSgTxData),
.FULL(),
.RD_EN(SG_DATA_REN),
.RD_DATA(SG_DATA),
.EMPTY(SG_DATA_EMPTY),
.COUNT(wSgTxFifoCount)
);
// Manage requesting and acknowledging scatter gather data. Note that
// these modules will share the main requestor's RX channel. They will
// take priority over the main logic's use of the RX channel.
sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgRxReq (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.USER_RST(wSgRst),
.BUF_RECVD(SG_RX_BUF_RECVD),
.BUF_DATA(SG_RX_BUF_DATA),
.BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.FIFO_COUNT(wSgRxFifoCount),
.FIFO_FLUSH(wSgRxFlush),
.FIFO_FLUSHED(wSgRxFlushed),
.FIFO_RST(wSgRxRst),
.RX_REQ(wSgRxReq),
.RX_ADDR(wSgRxReqAddr),
.RX_LEN(wSgRxReqLen),
.RX_REQ_ACK(wReqAck & wSgRxReqProc),
.RX_DONE(wPackedSgRxDone)
);
sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgTxReq (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.USER_RST(SG_RST),
.BUF_RECVD(SG_TX_BUF_RECVD),
.BUF_DATA(SG_TX_BUF_DATA),
.BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.FIFO_COUNT(wSgTxFifoCount),
.FIFO_FLUSH(wSgTxFlush),
.FIFO_FLUSHED(wSgTxFlushed),
.FIFO_RST(wSgTxRst),
.RX_REQ(wSgTxReq),
.RX_ADDR(wSgTxReqAddr),
.RX_LEN(wSgTxReqLen),
.RX_REQ_ACK(wReqAck & wSgTxReqProc),
.RX_DONE(wPackedSgTxDone)
);
// A read requester for the channel and scatter gather requesters.
rx_port_requester_mux requesterMux (
.RST(rRst),
.CLK(CLK),
.SG_RX_REQ(wSgRxReq),
.SG_RX_LEN(wSgRxReqLen),
.SG_RX_ADDR(wSgRxReqAddr),
.SG_RX_REQ_PROC(wSgRxReqProc),
.SG_TX_REQ(wSgTxReq),
.SG_TX_LEN(wSgTxReqLen),
.SG_TX_ADDR(wSgTxReqAddr),
.SG_TX_REQ_PROC(wSgTxReqProc),
.MAIN_REQ(wMainReq),
.MAIN_LEN(wMainReqLen),
.MAIN_ADDR(wMainReqAddr),
.MAIN_REQ_PROC(wMainReqProc),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.REQ_ACK(wReqAck)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_128 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | wSgRst),
.BUF_DATA(wSgRxData),
.BUF_DATA_EMPTY(wSgRxDataEmpty),
.BUF_DATA_REN(wSgRxDataRen),
.VALID(wSgElemRdy),
.EMPTY(),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Main port reader logic
rx_port_reader #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_MAIN_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) reader (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.TXN_DATA(TXN_DATA),
.TXN_LEN_VALID(TXN_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.TXN_DATA_FLUSH(wMainFlush),
.TXN_DATA_FLUSHED(wMainFlushed),
.RX_REQ(wMainReq),
.RX_ADDR(wMainReqAddr),
.RX_LEN(wMainReqLen),
.RX_REQ_ACK(wReqAck & wMainReqProc),
.RX_DATA_EN(MAIN_DATA_EN),
.RX_DONE(wPackedMainDone),
.RX_ERR(wPackedMainErr),
.SG_DONE(wPackedSgRxDone),
.SG_ERR(wPackedSgRxErr),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(wSgRst),
.CHNL_RX(wChnlRx),
.CHNL_RX_LEN(wChnlRxLen),
.CHNL_RX_LAST(wChnlRxLast),
.CHNL_RX_OFF(wChnlRxOff),
.CHNL_RX_RECVD(wChnlRxRecvd),
.CHNL_RX_ACK_RECVD(wChnlRxAckRecvd),
.CHNL_RX_CONSUMED(wChnlRxConsumed)
);
// Manage the CHNL_RX* signals in the CHNL_CLK domain.
rx_port_channel_gate #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.CLK(CLK),
.RX(wChnlRx),
.RX_RECVD(wChnlRxRecvd),
.RX_ACK_RECVD(wChnlRxAckRecvd),
.RX_LAST(wChnlRxLast),
.RX_LEN(wChnlRxLen),
.RX_OFF(wChnlRxOff),
.RX_CONSUMED(wChnlRxConsumed),
.RD_DATA(wMainData),
.RD_EMPTY(wMainDataEmpty),
.RD_EN(wMainDataRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
/*
reg [31:0] rCounter=0;
always @ (posedge CLK) begin
if (RST)
rCounter <= #1 0;
else
rCounter <= #1 (RX_REQ_ACK ? rCounter + 1 : rCounter);
end
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512_max a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({(SG_RX_DATA_EN != 0) | (MAIN_DATA_EN != 0),
RX_REQ_ACK,
wSgElemRen,
(SG_RX_BUF_ADDR_LO_VALID | SG_RX_BUF_ADDR_HI_VALID | SG_RX_BUF_LEN_VALID | SG_TX_BUF_ADDR_HI_VALID | SG_TX_BUF_LEN_VALID | TXN_OFF_LAST_VALID | TXN_LEN_VALID | wSgRst),
rCounter[10:7]}),
// .TRIG0({wSgRxReq & wSgRxReqProc & wReqAck,
// wSgElemRen,
// wMainReq | wSgRxReq | wSgTxReq,
// (SG_RX_DATA_EN != 0),
// SG_RX_BUF_ADDR_LO_VALID | SG_RX_BUF_ADDR_HI_VALID | SG_RX_BUF_LEN_VALID | TXN_OFF_LAST_VALID | TXN_LEN_VALID,
// rSgElemRenCount > 1100,
// wSgRst | wTxnErr | wSgRxFlush | wSgRxFlushed,
// wPackedSgRxDone | wPackedSgRxErr}),
.DATA({
MAIN_DATA_EN, // 3
//wPackedSgRxData, // 128
SG_RX_DONE, // 1
SG_RX_DATA_EN, // 3
SG_RX_DATA, // 128
wSgRxDataRen, // 1
wSgRxDataEmpty, // 1
MAIN_DATA, // 128
wSgRst, // 1
SG_RST, // 1
wPackedSgRxDone, // 1
wSgRxRst, // 1
wSgRxFlushed, // 1
wSgRxFlush, // 1
SG_RX_BUF_ADDR_LO_VALID, // 1
SG_RX_BUF_ADDR_HI_VALID, // 1
SG_RX_BUF_LEN_VALID, // 1
//SG_RX_BUF_DATA, // 32
rCounter, // 32
RX_REQ_ADDR, // 64
RX_REQ_TAG, // 2
RX_REQ_ACK, // 1
RX_REQ, // 1
wSgTxReqProc, // 1
wSgTxReq, // 1
wSgRxReqProc, // 1
//wSgRxReqAddr, // 64
//wSgElemAddr, // 64
44'd0, // 44
wSgRxReqLen, // 10
RX_REQ_LEN, // 10
wSgRxReq, // 1
wMainReqProc, // 1
wMainReqAddr, // 64
wMainReq, // 1
wReqAck, // 1
wTxnErr, // 1
TXN_OFF_LAST_VALID, // 1
TXN_LEN_VALID}) // 1
);
*/
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the tx_engine and buffers the input
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_128 #(
parameter C_DATA_WIDTH = 9'd128,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
input TXN_DONE_ACK, // Write transaction actual transfer length read
input [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather data
input SG_DATA_EMPTY, // Scatter gather buffer empty
output SG_DATA_REN, // Scatter gather data read enable
output SG_RST, // Scatter gather reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire wGateRen;
wire wGateEmpty;
wire [C_DATA_WIDTH:0] wGateData;
wire wBufWen;
wire [C_FIFO_DEPTH_WIDTH-1:0] wBufCount;
wire [C_DATA_WIDTH-1:0] wBufData;
wire wTxn;
wire wTxnAck;
wire wTxnLast;
wire [31:0] wTxnLen;
wire [30:0] wTxnOff;
wire [31:0] wTxnWordsRecvd;
wire wTxnDone;
wire wTxnErr;
wire wSgElemRen;
wire wSgElemRdy;
wire wSgElemEmpty;
wire [31:0] wSgElemLen;
wire [63:0] wSgElemAddr;
wire wTxLast;
reg [4:0] rWideRst=0;
reg rRst=0;
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Capture channel transaction open/close events as well as channel data.
tx_port_channel_gate_128 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.RD_CLK(CLK),
.RD_DATA(wGateData),
.RD_EMPTY(wGateEmpty),
.RD_EN(wGateRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
// Filter transaction events from channel data. Use the events to put only
// the requested amount of data into the port buffer.
tx_port_monitor_128 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
.RST(rRst),
.CLK(CLK),
.EVT_DATA(wGateData),
.EVT_DATA_EMPTY(wGateEmpty),
.EVT_DATA_RD_EN(wGateRen),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount),
.TXN(wTxn),
.ACK(wTxnAck),
.LAST(wTxnLast),
.LEN(wTxnLen),
.OFF(wTxnOff),
.WORDS_RECVD(wTxnWordsRecvd),
.DONE(wTxnDone),
.TX_ERR(SG_ERR)
);
// Buffer the incoming channel data. Also make sure to discard only as
// much data as is needed for a transfer (which may involve non-integral
// packets (i.e. reading only 1, 2, or 3 words out of the packet).
tx_port_buffer_128 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
.CLK(CLK),
.RST(rRst | (TXN_DONE & wTxnErr)),
.RD_DATA(TX_DATA),
.RD_EN(TX_DATA_REN),
.LEN_VALID(TX_REQ_ACK),
.LEN_LSB(TX_LEN[1:0]),
.LEN_LAST(wTxLast),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_128 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | SG_RST),
.BUF_DATA(SG_DATA),
.BUF_DATA_EMPTY(SG_DATA_EMPTY),
.BUF_DATA_REN(SG_DATA_REN),
.VALID(wSgElemRdy),
.EMPTY(wSgElemEmpty),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Controls the flow of request to the tx engine for transfers in a transaction.
tx_port_writer writer (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN),
.TXN_ACK(TXN_ACK),
.TXN_LEN(TXN_LEN),
.TXN_OFF_LAST(TXN_OFF_LAST),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.NEW_TXN(wTxn),
.NEW_TXN_ACK(wTxnAck),
.NEW_TXN_LAST(wTxnLast),
.NEW_TXN_LEN(wTxnLen),
.NEW_TXN_OFF(wTxnOff),
.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
.NEW_TXN_DONE(wTxnDone),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_EMPTY(wSgElemEmpty),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(SG_RST),
.SG_ERR(SG_ERR),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_LAST(wTxLast),
.TX_SENT(TX_SENT)
);
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads and writes data to the RS232 connector on Altera's *
* DE-series Development and Education Boards. *
* *
******************************************************************************/
module soc_design_UART_COM (
// Inputs
clk,
reset,
address,
chipselect,
byteenable,
read,
write,
writedata,
UART_RXD,
// Bidirectionals
// Outputs
irq,
readdata,
UART_TXD
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 10; // Baud counter width
parameter BAUD_TICK_COUNT = 868;
parameter HALF_BAUD_TICK_COUNT = 434;
parameter TDW = 10; // Total data width
parameter DW = 8; // Data width
parameter ODD_PARITY = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input address;
input chipselect;
input [ 3: 0] byteenable;
input read;
input write;
input [31: 0] writedata;
input UART_RXD;
// Bidirectionals
// Outputs
output reg irq;
output reg [31: 0] readdata;
output UART_TXD;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_fifo_read_en;
wire [ 7: 0] read_available;
wire read_data_valid;
wire [(DW-1):0] read_data;
wire parity_error;
wire write_data_parity;
wire [ 7: 0] write_space;
// Internal Registers
reg read_interrupt_en;
reg write_interrupt_en;
reg read_interrupt;
reg write_interrupt;
reg write_fifo_write_en;
reg [(DW-1):0] data_to_uart;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
irq <= 1'b0;
else
irq <= write_interrupt | read_interrupt;
end
always @(posedge clk)
begin
if (reset)
readdata <= 32'h00000000;
else if (chipselect)
begin
if (address == 1'b0)
readdata <=
{8'h00,
read_available,
read_data_valid,
5'h00,
parity_error,
1'b0,
read_data[(DW - 1):0]};
else
readdata <=
{8'h00,
write_space,
6'h00,
write_interrupt,
read_interrupt,
6'h00,
write_interrupt_en,
read_interrupt_en};
end
end
always @(posedge clk)
begin
if (reset)
read_interrupt_en <= 1'b0;
else if ((chipselect) && (write) && (address) && (byteenable[0]))
read_interrupt_en <= writedata[0];
end
always @(posedge clk)
begin
if (reset)
write_interrupt_en <= 1'b0;
else if ((chipselect) && (write) && (address) && (byteenable[0]))
write_interrupt_en <= writedata[1];
end
always @(posedge clk)
begin
if (reset)
read_interrupt <= 1'b0;
else if (read_interrupt_en == 1'b0)
read_interrupt <= 1'b0;
else
read_interrupt <= (&(read_available[6:5]) | read_available[7]);
end
always @(posedge clk)
begin
if (reset)
write_interrupt <= 1'b0;
else if (write_interrupt_en == 1'b0)
write_interrupt <= 1'b0;
else
write_interrupt <= (&(write_space[6:5]) | write_space[7]);
end
always @(posedge clk)
begin
if (reset)
write_fifo_write_en <= 1'b0;
else
write_fifo_write_en <=
chipselect & write & ~address & byteenable[0];
end
always @(posedge clk)
begin
if (reset)
data_to_uart <= 'h0;
else
data_to_uart <= writedata[(DW - 1):0];
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign parity_error = 1'b0;
assign read_fifo_read_en = chipselect & read & ~address & byteenable[0];
assign write_data_parity = (^(data_to_uart)) ^ ODD_PARITY;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_in_deserializer RS232_In_Deserializer (
// Inputs
.clk (clk),
.reset (reset),
.serial_data_in (UART_RXD),
.receive_data_en (read_fifo_read_en),
// Bidirectionals
// Outputs
.fifo_read_available (read_available),
.received_data_valid (read_data_valid),
.received_data (read_data)
);
defparam
RS232_In_Deserializer.CW = CW,
RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Deserializer.TDW = TDW,
RS232_In_Deserializer.DW = (DW - 1);
altera_up_rs232_out_serializer RS232_Out_Serializer (
// Inputs
.clk (clk),
.reset (reset),
.transmit_data (data_to_uart),
.transmit_data_en (write_fifo_write_en),
// Bidirectionals
// Outputs
.fifo_write_space (write_space),
.serial_data_out (UART_TXD)
);
defparam
RS232_Out_Serializer.CW = CW,
RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Serializer.TDW = TDW,
RS232_Out_Serializer.DW = (DW - 1);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_port_requester.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Issues read requests to the tx_engine for the rx_port
// and sg_list_requester modules in the rx_port. Expects those modules to update
// their address and length values after every request issued. Also expects them
// to update their space available values within 6 cycles of a change to the
// RX_LEN.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_RXPORTREQ_RX_TX 2'b00
`define S_RXPORTREQ_TX_RX 2'b01
`define S_RXPORTREQ_ISSUE 2'b10
`timescale 1ns/1ns
module rx_port_requester_mux (
input RST,
input CLK,
input SG_RX_REQ, // Scatter gather RX read request
input [9:0] SG_RX_LEN, // Scatter gather RX read request length
input [63:0] SG_RX_ADDR, // Scatter gather RX read request address
output SG_RX_REQ_PROC, // Scatter gather RX read request processing
input SG_TX_REQ, // Scatter gather TX read request
input [9:0] SG_TX_LEN, // Scatter gather TX read request length
input [63:0] SG_TX_ADDR, // Scatter gather TX read request address
output SG_TX_REQ_PROC, // Scatter gather TX read request processing
input MAIN_REQ, // Main read request
input [9:0] MAIN_LEN, // Main read request length
input [63:0] MAIN_ADDR, // Main read request address
output MAIN_REQ_PROC, // Main read request processing
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output REQ_ACK // Request accepted
);
reg rRxReqAck=0, _rRxReqAck=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_RXPORTREQ_RX_TX, _rState=`S_RXPORTREQ_RX_TX;
reg [9:0] rLen=0, _rLen=0;
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg rSgRxAck=0, _rSgRxAck=0;
reg rSgTxAck=0, _rSgTxAck=0;
reg rMainAck=0, _rMainAck=0;
reg rAck=0, _rAck=0;
assign SG_RX_REQ_PROC = rSgRxAck;
assign SG_TX_REQ_PROC = rSgTxAck;
assign MAIN_REQ_PROC = rMainAck;
assign RX_REQ = rState[1]; // S_RXPORTREQ_ISSUE
assign RX_REQ_TAG = {rSgTxAck, rSgRxAck};
assign RX_REQ_ADDR = rAddr;
assign RX_REQ_LEN = rLen;
assign REQ_ACK = rAck;
// Buffer signals that come from outside the rx_port.
always @ (posedge CLK) begin
rRxReqAck <= #1 (RST ? 1'd0 : _rRxReqAck);
end
always @ (*) begin
_rRxReqAck = RX_REQ_ACK;
end
// Handle issuing read requests. Scatter gather requests are processed
// with higher priority than the main channel.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_RXPORTREQ_RX_TX : _rState);
rLen <= #1 _rLen;
rAddr <= #1 _rAddr;
rSgRxAck <= #1 _rSgRxAck;
rSgTxAck <= #1 _rSgTxAck;
rMainAck <= #1 _rMainAck;
rAck <= #1 _rAck;
end
always @ (*) begin
_rState = rState;
_rLen = rLen;
_rAddr = rAddr;
_rSgRxAck = rSgRxAck;
_rSgTxAck = rSgTxAck;
_rMainAck = rMainAck;
_rAck = rAck;
case (rState)
`S_RXPORTREQ_RX_TX: begin // Wait for a new read request
if (SG_RX_REQ) begin
_rLen = SG_RX_LEN;
_rAddr = SG_RX_ADDR;
_rSgRxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (SG_TX_REQ) begin
_rLen = SG_TX_LEN;
_rAddr = SG_TX_ADDR;
_rSgTxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (MAIN_REQ) begin
_rLen = MAIN_LEN;
_rAddr = MAIN_ADDR;
_rMainAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else begin
_rState = `S_RXPORTREQ_TX_RX;
end
end
`S_RXPORTREQ_TX_RX: begin // Wait for a new read request
if (SG_TX_REQ) begin
_rLen = SG_TX_LEN;
_rAddr = SG_TX_ADDR;
_rSgTxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (SG_RX_REQ) begin
_rLen = SG_RX_LEN;
_rAddr = SG_RX_ADDR;
_rSgRxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (MAIN_REQ) begin
_rLen = MAIN_LEN;
_rAddr = MAIN_ADDR;
_rMainAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else begin
_rState = `S_RXPORTREQ_RX_TX;
end
end
`S_RXPORTREQ_ISSUE: begin // Issue the request
_rAck = 0;
if (rRxReqAck) begin
_rSgRxAck = 0;
_rSgTxAck = 0;
_rMainAck = 0;
if (rSgRxAck)
_rState = `S_RXPORTREQ_TX_RX;
else
_rState = `S_RXPORTREQ_RX_TX;
end
end
default: begin
_rState = `S_RXPORTREQ_RX_TX;
end
endcase
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_port_requester.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Issues read requests to the tx_engine for the rx_port
// and sg_list_requester modules in the rx_port. Expects those modules to update
// their address and length values after every request issued. Also expects them
// to update their space available values within 6 cycles of a change to the
// RX_LEN.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_RXPORTREQ_RX_TX 2'b00
`define S_RXPORTREQ_TX_RX 2'b01
`define S_RXPORTREQ_ISSUE 2'b10
`timescale 1ns/1ns
module rx_port_requester_mux (
input RST,
input CLK,
input SG_RX_REQ, // Scatter gather RX read request
input [9:0] SG_RX_LEN, // Scatter gather RX read request length
input [63:0] SG_RX_ADDR, // Scatter gather RX read request address
output SG_RX_REQ_PROC, // Scatter gather RX read request processing
input SG_TX_REQ, // Scatter gather TX read request
input [9:0] SG_TX_LEN, // Scatter gather TX read request length
input [63:0] SG_TX_ADDR, // Scatter gather TX read request address
output SG_TX_REQ_PROC, // Scatter gather TX read request processing
input MAIN_REQ, // Main read request
input [9:0] MAIN_LEN, // Main read request length
input [63:0] MAIN_ADDR, // Main read request address
output MAIN_REQ_PROC, // Main read request processing
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output REQ_ACK // Request accepted
);
reg rRxReqAck=0, _rRxReqAck=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_RXPORTREQ_RX_TX, _rState=`S_RXPORTREQ_RX_TX;
reg [9:0] rLen=0, _rLen=0;
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg rSgRxAck=0, _rSgRxAck=0;
reg rSgTxAck=0, _rSgTxAck=0;
reg rMainAck=0, _rMainAck=0;
reg rAck=0, _rAck=0;
assign SG_RX_REQ_PROC = rSgRxAck;
assign SG_TX_REQ_PROC = rSgTxAck;
assign MAIN_REQ_PROC = rMainAck;
assign RX_REQ = rState[1]; // S_RXPORTREQ_ISSUE
assign RX_REQ_TAG = {rSgTxAck, rSgRxAck};
assign RX_REQ_ADDR = rAddr;
assign RX_REQ_LEN = rLen;
assign REQ_ACK = rAck;
// Buffer signals that come from outside the rx_port.
always @ (posedge CLK) begin
rRxReqAck <= #1 (RST ? 1'd0 : _rRxReqAck);
end
always @ (*) begin
_rRxReqAck = RX_REQ_ACK;
end
// Handle issuing read requests. Scatter gather requests are processed
// with higher priority than the main channel.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_RXPORTREQ_RX_TX : _rState);
rLen <= #1 _rLen;
rAddr <= #1 _rAddr;
rSgRxAck <= #1 _rSgRxAck;
rSgTxAck <= #1 _rSgTxAck;
rMainAck <= #1 _rMainAck;
rAck <= #1 _rAck;
end
always @ (*) begin
_rState = rState;
_rLen = rLen;
_rAddr = rAddr;
_rSgRxAck = rSgRxAck;
_rSgTxAck = rSgTxAck;
_rMainAck = rMainAck;
_rAck = rAck;
case (rState)
`S_RXPORTREQ_RX_TX: begin // Wait for a new read request
if (SG_RX_REQ) begin
_rLen = SG_RX_LEN;
_rAddr = SG_RX_ADDR;
_rSgRxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (SG_TX_REQ) begin
_rLen = SG_TX_LEN;
_rAddr = SG_TX_ADDR;
_rSgTxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (MAIN_REQ) begin
_rLen = MAIN_LEN;
_rAddr = MAIN_ADDR;
_rMainAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else begin
_rState = `S_RXPORTREQ_TX_RX;
end
end
`S_RXPORTREQ_TX_RX: begin // Wait for a new read request
if (SG_TX_REQ) begin
_rLen = SG_TX_LEN;
_rAddr = SG_TX_ADDR;
_rSgTxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (SG_RX_REQ) begin
_rLen = SG_RX_LEN;
_rAddr = SG_RX_ADDR;
_rSgRxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (MAIN_REQ) begin
_rLen = MAIN_LEN;
_rAddr = MAIN_ADDR;
_rMainAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else begin
_rState = `S_RXPORTREQ_RX_TX;
end
end
`S_RXPORTREQ_ISSUE: begin // Issue the request
_rAck = 0;
if (rRxReqAck) begin
_rSgRxAck = 0;
_rSgTxAck = 0;
_rMainAck = 0;
if (rSgRxAck)
_rState = `S_RXPORTREQ_TX_RX;
else
_rState = `S_RXPORTREQ_RX_TX;
end
end
default: begin
_rState = `S_RXPORTREQ_RX_TX;
end
endcase
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2008 www.xilinx.com
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : encode.v
//
// Description : TMDS encoder
//
// Date - revision : Jan. 2008 - v 1.0
//
// Author : Bob Feng
//
// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement,or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrantor
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits,cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the
// essential purpose of any limited remedies herein.
//
// Copyright © 2006 Xilinx, Inc.
// All rights reserved
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1ps
module encode (
input clkin, // pixel clock input
input rstin, // async. reset input (active high)
input [7:0] din, // data inputs: expect registered
input c0, // c0 input
input c1, // c1 input
input de, // de input
output reg [9:0] dout // data outputs
);
////////////////////////////////////////////////////////////
// Counting number of 1s and 0s for each incoming pixel
// component. Pipe line the result.
// Register Data Input so it matches the pipe lined adder
// output
////////////////////////////////////////////////////////////
reg [3:0] n1d; //number of 1s in din
reg [7:0] din_q;
always @ (posedge clkin) begin
n1d <=#1 din[0] + din[1] + din[2] + din[3] + din[4] + din[5] + din[6] + din[7];
din_q <=#1 din;
end
///////////////////////////////////////////////////////
// Stage 1: 8 bit -> 9 bit
// Refer to DVI 1.0 Specification, page 29, Figure 3-5
///////////////////////////////////////////////////////
wire decision1;
assign decision1 = (n1d > 4'h4) | ((n1d == 4'h4) & (din_q[0] == 1'b0));
/*
reg [8:0] q_m;
always @ (posedge clkin) begin
q_m[0] <=#1 din_q[0];
q_m[1] <=#1 (decision1) ? (q_m[0] ^~ din_q[1]) : (q_m[0] ^ din_q[1]);
q_m[2] <=#1 (decision1) ? (q_m[1] ^~ din_q[2]) : (q_m[1] ^ din_q[2]);
q_m[3] <=#1 (decision1) ? (q_m[2] ^~ din_q[3]) : (q_m[2] ^ din_q[3]);
q_m[4] <=#1 (decision1) ? (q_m[3] ^~ din_q[4]) : (q_m[3] ^ din_q[4]);
q_m[5] <=#1 (decision1) ? (q_m[4] ^~ din_q[5]) : (q_m[4] ^ din_q[5]);
q_m[6] <=#1 (decision1) ? (q_m[5] ^~ din_q[6]) : (q_m[5] ^ din_q[6]);
q_m[7] <=#1 (decision1) ? (q_m[6] ^~ din_q[7]) : (q_m[6] ^ din_q[7]);
q_m[8] <=#1 (decision1) ? 1'b0 : 1'b1;
end
*/
wire [8:0] q_m;
assign q_m[0] = din_q[0];
assign q_m[1] = (decision1) ? (q_m[0] ^~ din_q[1]) : (q_m[0] ^ din_q[1]);
assign q_m[2] = (decision1) ? (q_m[1] ^~ din_q[2]) : (q_m[1] ^ din_q[2]);
assign q_m[3] = (decision1) ? (q_m[2] ^~ din_q[3]) : (q_m[2] ^ din_q[3]);
assign q_m[4] = (decision1) ? (q_m[3] ^~ din_q[4]) : (q_m[3] ^ din_q[4]);
assign q_m[5] = (decision1) ? (q_m[4] ^~ din_q[5]) : (q_m[4] ^ din_q[5]);
assign q_m[6] = (decision1) ? (q_m[5] ^~ din_q[6]) : (q_m[5] ^ din_q[6]);
assign q_m[7] = (decision1) ? (q_m[6] ^~ din_q[7]) : (q_m[6] ^ din_q[7]);
assign q_m[8] = (decision1) ? 1'b0 : 1'b1;
/////////////////////////////////////////////////////////
// Stage 2: 9 bit -> 10 bit
// Refer to DVI 1.0 Specification, page 29, Figure 3-5
/////////////////////////////////////////////////////////
reg [3:0] n1q_m, n0q_m; // number of 1s and 0s for q_m
always @ (posedge clkin) begin
n1q_m <=#1 q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7];
n0q_m <=#1 4'h8 - (q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7]);
end
parameter CTRLTOKEN0 = 10'b1101010100;
parameter CTRLTOKEN1 = 10'b0010101011;
parameter CTRLTOKEN2 = 10'b0101010100;
parameter CTRLTOKEN3 = 10'b1010101011;
reg [4:0] cnt; //disparity counter, MSB is the sign bit
wire decision2, decision3;
assign decision2 = (cnt == 5'h0) | (n1q_m == n0q_m);
/////////////////////////////////////////////////////////////////////////
// [(cnt > 0) and (N1q_m > N0q_m)] or [(cnt < 0) and (N0q_m > N1q_m)]
/////////////////////////////////////////////////////////////////////////
assign decision3 = (~cnt[4] & (n1q_m > n0q_m)) | (cnt[4] & (n0q_m > n1q_m));
////////////////////////////////////
// pipe line alignment
////////////////////////////////////
reg de_q, de_reg;
reg c0_q, c1_q;
reg c0_reg, c1_reg;
reg [8:0] q_m_reg;
always @ (posedge clkin) begin
de_q <=#1 de;
de_reg <=#1 de_q;
c0_q <=#1 c0;
c0_reg <=#1 c0_q;
c1_q <=#1 c1;
c1_reg <=#1 c1_q;
q_m_reg <=#1 q_m;
end
///////////////////////////////
// 10-bit out
// disparity counter
///////////////////////////////
always @ (posedge clkin or posedge rstin) begin
if(rstin) begin
dout <= 10'h0;
cnt <= 5'h0;
end else begin
if (de_reg) begin
if(decision2) begin
dout[9] <=#1 ~q_m_reg[8];
dout[8] <=#1 q_m_reg[8];
dout[7:0] <=#1 (q_m_reg[8]) ? q_m_reg[7:0] : ~q_m_reg[7:0];
cnt <=#1 (~q_m_reg[8]) ? (cnt + n0q_m - n1q_m) : (cnt + n1q_m - n0q_m);
end else begin
if(decision3) begin
dout[9] <=#1 1'b1;
dout[8] <=#1 q_m_reg[8];
dout[7:0] <=#1 ~q_m_reg[7:0];
cnt <=#1 cnt + {q_m_reg[8], 1'b0} + (n0q_m - n1q_m);
end else begin
dout[9] <=#1 1'b0;
dout[8] <=#1 q_m_reg[8];
dout[7:0] <=#1 q_m_reg[7:0];
cnt <=#1 cnt - {~q_m_reg[8], 1'b0} + (n1q_m - n0q_m);
end
end
end else begin
case ({c1_reg, c0_reg})
2'b00: dout <=#1 CTRLTOKEN0;
2'b01: dout <=#1 CTRLTOKEN1;
2'b10: dout <=#1 CTRLTOKEN2;
default: dout <=#1 CTRLTOKEN3;
endcase
cnt <=#1 5'h0;
end
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_row_col.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block receives request to send row and column commands. These requests
// come the individual bank machines. The arbitration winner is selected
// and driven back to the bank machines.
//
// The CS enables are generated. For 2:1 mode, row commands are sent
// in the "0" phase, and column commands are sent in the "1" phase.
//
// In 2T mode, a further arbitration is performed between the row
// and column commands. The winner of this arbitration inhibits
// arbitration by the loser. The winner is allowed to arbitrate, the loser is
// blocked until the next state. The winning address command
// is repeated on both the "0" and the "1" phases and the CS
// is asserted for just the "1" phase.
`timescale 1 ps / 1 ps
module mig_7series_v1_9_arb_row_col #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter CWL = 5,
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
parameter nRCD = 12500, // ACT->R/W delay (CKs)
parameter nWR = 6 // Write recovery (CKs)
)
(/*AUTOARG*/
// Outputs
grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r,
rnk_config_strobe, rnk_config_valid_r, grant_col_r,
sending_col, sent_col, sent_col_r, grant_col_wr, send_cmd0_row, send_cmd0_col,
send_cmd1_row, send_cmd1_col, send_cmd2_row, send_cmd2_col, send_cmd2_pre,
send_cmd3_col, col_channel_offset, cs_en0, cs_en1, cs_en2, cs_en3,
insert_maint_r1, rnk_config_kill_rts_col,
// Inputs
clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc, col_rdy_wr
);
// Create a delay when switching ranks
localparam RNK2RNK_DLY = 12;
localparam RNK2RNK_DLY_CLKS =
(RNK2RNK_DLY / nCK_PER_CLK) + (RNK2RNK_DLY % nCK_PER_CLK ? 1 : 0);
input clk;
input rst;
input [nBANK_MACHS-1:0] rts_row;
input insert_maint_r;
input [nBANK_MACHS-1:0] rts_col;
reg [RNK2RNK_DLY_CLKS-1:0] rnk_config_strobe_r;
wire block_grant_row;
wire block_grant_col;
wire rnk_config_kill_rts_col_lcl =
RNK2RNK_DLY_CLKS > 0 ? |rnk_config_strobe_r : 1'b0;
output rnk_config_kill_rts_col;
assign rnk_config_kill_rts_col = rnk_config_kill_rts_col_lcl;
wire [nBANK_MACHS-1:0] col_request;
wire granted_col_ns = |col_request;
wire [nBANK_MACHS-1:0] row_request =
rts_row & {nBANK_MACHS{~insert_maint_r}};
wire granted_row_ns = |row_request;
generate
if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK != 4) begin : row_col_2T_arb
assign col_request =
rts_col & {nBANK_MACHS{~(rnk_config_kill_rts_col_lcl || insert_maint_r)}};
// Give column command priority whenever previous state has no row request.
wire [1:0] row_col_grant;
wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant;
wire upd_last_master = ~granted_row_ns || |row_col_grant;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (2))
row_col_arb0
(.grant_ns (),
.grant_r (row_col_grant),
.upd_last_master (upd_last_master),
.current_master (current_master),
.clk (clk),
.rst (rst),
.req ({granted_row_ns, granted_col_ns}),
.disable_grant (1'b0));
assign {block_grant_col, block_grant_row} = row_col_grant;
end
else begin : row_col_1T_arb
assign col_request = rts_col & {nBANK_MACHS{~rnk_config_kill_rts_col_lcl}};
assign block_grant_row = 1'b0;
assign block_grant_col = 1'b0;
end
endgenerate
// Row address/command arbitration.
wire[nBANK_MACHS-1:0] grant_row_r_lcl;
output wire[nBANK_MACHS-1:0] grant_row_r;
assign grant_row_r = grant_row_r_lcl;
reg granted_row_r;
always @(posedge clk) granted_row_r <= #TCQ granted_row_ns;
wire sent_row_lcl = granted_row_r && ~block_grant_row;
output wire sent_row;
assign sent_row = sent_row_lcl;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (nBANK_MACHS))
row_arb0
(.grant_ns (),
.grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_row_lcl),
.current_master (grant_row_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (row_request),
.disable_grant (1'b0));
output wire [nBANK_MACHS-1:0] sending_row;
assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}};
// Precharge arbitration for 4:1 mode
input [nBANK_MACHS-1:0] rts_pre;
output wire[nBANK_MACHS-1:0] grant_pre_r;
output wire [nBANK_MACHS-1:0] sending_pre;
wire sent_pre_lcl;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_4_1_1T_arb
reg granted_pre_r;
wire[nBANK_MACHS-1:0] grant_pre_r_lcl;
wire granted_pre_ns = |rts_pre;
assign grant_pre_r = grant_pre_r_lcl;
always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns;
assign sent_pre_lcl = granted_pre_r;
assign sending_pre = grant_pre_r_lcl;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (nBANK_MACHS))
pre_arb0
(.grant_ns (),
.grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_pre_lcl),
.current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rts_pre),
.disable_grant (1'b0));
end
endgenerate
`ifdef MC_SVA
all_bank_machines_row_arb:
cover property (@(posedge clk) (~rst && &rts_row));
`endif
// Rank config arbitration.
input [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] grant_config_r_lcl;
output wire [nBANK_MACHS-1:0] grant_config_r;
assign grant_config_r = grant_config_r_lcl;
wire upd_rnk_config_last_master;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (nBANK_MACHS))
config_arb0
(.grant_ns (),
.grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (upd_rnk_config_last_master),
.current_master (grant_config_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rtc[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc));
`endif
wire rnk_config_strobe_ns = ~rnk_config_strobe_r[0] && |rtc && ~granted_col_ns;
always @(posedge clk) rnk_config_strobe_r[0] <= #TCQ rnk_config_strobe_ns;
genvar i;
generate
for(i = 1; i < RNK2RNK_DLY_CLKS; i = i + 1)
always @(posedge clk)
rnk_config_strobe_r[i] <= #TCQ rnk_config_strobe_r[i-1];
endgenerate
output wire rnk_config_strobe;
assign rnk_config_strobe = rnk_config_strobe_r[0];
assign upd_rnk_config_last_master = rnk_config_strobe_r[0];
// Generate rnk_config_valid.
reg rnk_config_valid_r_lcl;
wire rnk_config_valid_ns;
assign rnk_config_valid_ns =
~rst && (rnk_config_valid_r_lcl || rnk_config_strobe_ns);
always @(posedge clk) rnk_config_valid_r_lcl <= #TCQ rnk_config_valid_ns;
output wire rnk_config_valid_r;
assign rnk_config_valid_r = rnk_config_valid_r_lcl;
// Column address/command arbitration.
wire [nBANK_MACHS-1:0] grant_col_r_lcl;
output wire [nBANK_MACHS-1:0] grant_col_r;
assign grant_col_r = grant_col_r_lcl;
reg granted_col_r;
always @(posedge clk) granted_col_r <= #TCQ granted_col_ns;
wire sent_col_lcl;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (),
.grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_request),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_col_arb:
cover property (@(posedge clk) (~rst && &rts_col));
`endif
output wire [nBANK_MACHS-1:0] sending_col;
assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}};
assign sent_col_lcl = granted_col_r && ~block_grant_col;
reg sent_col_lcl_r = 1'b0;
always @(posedge clk) sent_col_lcl_r <= #TCQ sent_col_lcl;
output wire sent_col;
assign sent_col = sent_col_lcl;
output wire sent_col_r;
assign sent_col_r = sent_col_lcl_r;
// If we need early wr_data_addr because ECC is on, arbitrate
// to see which bank machine might sent the next wr_data_addr;
input [nBANK_MACHS-1:0] col_rdy_wr;
output wire [nBANK_MACHS-1:0] grant_col_wr;
generate
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off
assign grant_col_wr = {nBANK_MACHS{1'b0}};
end
else begin : early_wr_addr_arb_on
wire [nBANK_MACHS-1:0] grant_col_wr_raw;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (grant_col_wr_raw),
.grant_r (),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_rdy_wr),
.disable_grant (1'b0));
reg [nBANK_MACHS-1:0] grant_col_wr_r;
wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns
? grant_col_wr_raw
: grant_col_wr_r;
always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns;
assign grant_col_wr = grant_col_wr_ns;
end // block: early_wr_addr_arb_on
endgenerate
output reg send_cmd0_row = 1'b0;
output reg send_cmd0_col = 1'b0;
output reg send_cmd1_row = 1'b0;
output reg send_cmd1_col = 1'b0;
output reg send_cmd2_row = 1'b0;
output reg send_cmd2_col = 1'b0;
output reg send_cmd2_pre = 1'b0;
output reg send_cmd3_col = 1'b0;
output reg cs_en0 = 1'b0;
output reg cs_en1 = 1'b0;
output reg cs_en2 = 1'b0;
output reg cs_en3 = 1'b0;
output wire [5:0] col_channel_offset;
reg insert_maint_r1_lcl;
always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r;
output wire insert_maint_r1;
assign insert_maint_r1 = insert_maint_r1_lcl;
wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl;
reg sent_row_or_maint_r = 1'b0;
always @(posedge clk) sent_row_or_maint_r <= #TCQ sent_row_or_maint;
generate
case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")})
3'b000 : begin : one_one_not2T
end
3'b001 : begin : one_one_2T
end
3'b010 : begin : two_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) begin
cs_en0 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en1 = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
end
3'b011 : begin : two_one_2T
if(!(CWL % 2)) begin // Place column commands on slot 1->0 for even CWL
always @(sent_row_or_maint_r or sent_col_lcl_r)
cs_en0 = sent_row_or_maint_r || sent_col_lcl_r;
always @(sent_row_or_maint or sent_row_or_maint_r) begin
send_cmd0_row = sent_row_or_maint_r;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl or sent_col_lcl_r) begin
send_cmd0_col = sent_col_lcl_r;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 0->1 for odd CWL
always @(sent_col_lcl or sent_row_or_maint)
cs_en1 = sent_row_or_maint || sent_col_lcl;
always @(sent_row_or_maint) begin
send_cmd0_row = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
send_cmd0_col = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
end
3'b100 : begin : four_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) begin
cs_en0 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en1 = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
always @(sent_pre_lcl) begin
cs_en2 = sent_pre_lcl;
send_cmd2_pre = sent_pre_lcl;
end
end
3'b101 : begin : four_one_2T
if(!(CWL % 2)) begin // Place column commands on slot 3->0 for even CWL
always @(sent_col_lcl or sent_col_lcl_r) begin
cs_en0 = sent_col_lcl_r;
send_cmd0_col = sent_col_lcl_r;
send_cmd3_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en2 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
send_cmd2_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 2->3 for odd CWL
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en3 = sent_col_lcl;
send_cmd2_col = sent_col_lcl;
send_cmd3_col = sent_col_lcl;
end
assign col_channel_offset = 3;
end
end
endcase
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_row_col.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block receives request to send row and column commands. These requests
// come the individual bank machines. The arbitration winner is selected
// and driven back to the bank machines.
//
// The CS enables are generated. For 2:1 mode, row commands are sent
// in the "0" phase, and column commands are sent in the "1" phase.
//
// In 2T mode, a further arbitration is performed between the row
// and column commands. The winner of this arbitration inhibits
// arbitration by the loser. The winner is allowed to arbitrate, the loser is
// blocked until the next state. The winning address command
// is repeated on both the "0" and the "1" phases and the CS
// is asserted for just the "1" phase.
`timescale 1 ps / 1 ps
module mig_7series_v1_9_arb_row_col #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter CWL = 5,
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
parameter nRCD = 12500, // ACT->R/W delay (CKs)
parameter nWR = 6 // Write recovery (CKs)
)
(/*AUTOARG*/
// Outputs
grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r,
rnk_config_strobe, rnk_config_valid_r, grant_col_r,
sending_col, sent_col, sent_col_r, grant_col_wr, send_cmd0_row, send_cmd0_col,
send_cmd1_row, send_cmd1_col, send_cmd2_row, send_cmd2_col, send_cmd2_pre,
send_cmd3_col, col_channel_offset, cs_en0, cs_en1, cs_en2, cs_en3,
insert_maint_r1, rnk_config_kill_rts_col,
// Inputs
clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc, col_rdy_wr
);
// Create a delay when switching ranks
localparam RNK2RNK_DLY = 12;
localparam RNK2RNK_DLY_CLKS =
(RNK2RNK_DLY / nCK_PER_CLK) + (RNK2RNK_DLY % nCK_PER_CLK ? 1 : 0);
input clk;
input rst;
input [nBANK_MACHS-1:0] rts_row;
input insert_maint_r;
input [nBANK_MACHS-1:0] rts_col;
reg [RNK2RNK_DLY_CLKS-1:0] rnk_config_strobe_r;
wire block_grant_row;
wire block_grant_col;
wire rnk_config_kill_rts_col_lcl =
RNK2RNK_DLY_CLKS > 0 ? |rnk_config_strobe_r : 1'b0;
output rnk_config_kill_rts_col;
assign rnk_config_kill_rts_col = rnk_config_kill_rts_col_lcl;
wire [nBANK_MACHS-1:0] col_request;
wire granted_col_ns = |col_request;
wire [nBANK_MACHS-1:0] row_request =
rts_row & {nBANK_MACHS{~insert_maint_r}};
wire granted_row_ns = |row_request;
generate
if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK != 4) begin : row_col_2T_arb
assign col_request =
rts_col & {nBANK_MACHS{~(rnk_config_kill_rts_col_lcl || insert_maint_r)}};
// Give column command priority whenever previous state has no row request.
wire [1:0] row_col_grant;
wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant;
wire upd_last_master = ~granted_row_ns || |row_col_grant;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (2))
row_col_arb0
(.grant_ns (),
.grant_r (row_col_grant),
.upd_last_master (upd_last_master),
.current_master (current_master),
.clk (clk),
.rst (rst),
.req ({granted_row_ns, granted_col_ns}),
.disable_grant (1'b0));
assign {block_grant_col, block_grant_row} = row_col_grant;
end
else begin : row_col_1T_arb
assign col_request = rts_col & {nBANK_MACHS{~rnk_config_kill_rts_col_lcl}};
assign block_grant_row = 1'b0;
assign block_grant_col = 1'b0;
end
endgenerate
// Row address/command arbitration.
wire[nBANK_MACHS-1:0] grant_row_r_lcl;
output wire[nBANK_MACHS-1:0] grant_row_r;
assign grant_row_r = grant_row_r_lcl;
reg granted_row_r;
always @(posedge clk) granted_row_r <= #TCQ granted_row_ns;
wire sent_row_lcl = granted_row_r && ~block_grant_row;
output wire sent_row;
assign sent_row = sent_row_lcl;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (nBANK_MACHS))
row_arb0
(.grant_ns (),
.grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_row_lcl),
.current_master (grant_row_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (row_request),
.disable_grant (1'b0));
output wire [nBANK_MACHS-1:0] sending_row;
assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}};
// Precharge arbitration for 4:1 mode
input [nBANK_MACHS-1:0] rts_pre;
output wire[nBANK_MACHS-1:0] grant_pre_r;
output wire [nBANK_MACHS-1:0] sending_pre;
wire sent_pre_lcl;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_4_1_1T_arb
reg granted_pre_r;
wire[nBANK_MACHS-1:0] grant_pre_r_lcl;
wire granted_pre_ns = |rts_pre;
assign grant_pre_r = grant_pre_r_lcl;
always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns;
assign sent_pre_lcl = granted_pre_r;
assign sending_pre = grant_pre_r_lcl;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (nBANK_MACHS))
pre_arb0
(.grant_ns (),
.grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_pre_lcl),
.current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rts_pre),
.disable_grant (1'b0));
end
endgenerate
`ifdef MC_SVA
all_bank_machines_row_arb:
cover property (@(posedge clk) (~rst && &rts_row));
`endif
// Rank config arbitration.
input [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] grant_config_r_lcl;
output wire [nBANK_MACHS-1:0] grant_config_r;
assign grant_config_r = grant_config_r_lcl;
wire upd_rnk_config_last_master;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (nBANK_MACHS))
config_arb0
(.grant_ns (),
.grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (upd_rnk_config_last_master),
.current_master (grant_config_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rtc[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc));
`endif
wire rnk_config_strobe_ns = ~rnk_config_strobe_r[0] && |rtc && ~granted_col_ns;
always @(posedge clk) rnk_config_strobe_r[0] <= #TCQ rnk_config_strobe_ns;
genvar i;
generate
for(i = 1; i < RNK2RNK_DLY_CLKS; i = i + 1)
always @(posedge clk)
rnk_config_strobe_r[i] <= #TCQ rnk_config_strobe_r[i-1];
endgenerate
output wire rnk_config_strobe;
assign rnk_config_strobe = rnk_config_strobe_r[0];
assign upd_rnk_config_last_master = rnk_config_strobe_r[0];
// Generate rnk_config_valid.
reg rnk_config_valid_r_lcl;
wire rnk_config_valid_ns;
assign rnk_config_valid_ns =
~rst && (rnk_config_valid_r_lcl || rnk_config_strobe_ns);
always @(posedge clk) rnk_config_valid_r_lcl <= #TCQ rnk_config_valid_ns;
output wire rnk_config_valid_r;
assign rnk_config_valid_r = rnk_config_valid_r_lcl;
// Column address/command arbitration.
wire [nBANK_MACHS-1:0] grant_col_r_lcl;
output wire [nBANK_MACHS-1:0] grant_col_r;
assign grant_col_r = grant_col_r_lcl;
reg granted_col_r;
always @(posedge clk) granted_col_r <= #TCQ granted_col_ns;
wire sent_col_lcl;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (),
.grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_request),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_col_arb:
cover property (@(posedge clk) (~rst && &rts_col));
`endif
output wire [nBANK_MACHS-1:0] sending_col;
assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}};
assign sent_col_lcl = granted_col_r && ~block_grant_col;
reg sent_col_lcl_r = 1'b0;
always @(posedge clk) sent_col_lcl_r <= #TCQ sent_col_lcl;
output wire sent_col;
assign sent_col = sent_col_lcl;
output wire sent_col_r;
assign sent_col_r = sent_col_lcl_r;
// If we need early wr_data_addr because ECC is on, arbitrate
// to see which bank machine might sent the next wr_data_addr;
input [nBANK_MACHS-1:0] col_rdy_wr;
output wire [nBANK_MACHS-1:0] grant_col_wr;
generate
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off
assign grant_col_wr = {nBANK_MACHS{1'b0}};
end
else begin : early_wr_addr_arb_on
wire [nBANK_MACHS-1:0] grant_col_wr_raw;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (grant_col_wr_raw),
.grant_r (),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_rdy_wr),
.disable_grant (1'b0));
reg [nBANK_MACHS-1:0] grant_col_wr_r;
wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns
? grant_col_wr_raw
: grant_col_wr_r;
always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns;
assign grant_col_wr = grant_col_wr_ns;
end // block: early_wr_addr_arb_on
endgenerate
output reg send_cmd0_row = 1'b0;
output reg send_cmd0_col = 1'b0;
output reg send_cmd1_row = 1'b0;
output reg send_cmd1_col = 1'b0;
output reg send_cmd2_row = 1'b0;
output reg send_cmd2_col = 1'b0;
output reg send_cmd2_pre = 1'b0;
output reg send_cmd3_col = 1'b0;
output reg cs_en0 = 1'b0;
output reg cs_en1 = 1'b0;
output reg cs_en2 = 1'b0;
output reg cs_en3 = 1'b0;
output wire [5:0] col_channel_offset;
reg insert_maint_r1_lcl;
always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r;
output wire insert_maint_r1;
assign insert_maint_r1 = insert_maint_r1_lcl;
wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl;
reg sent_row_or_maint_r = 1'b0;
always @(posedge clk) sent_row_or_maint_r <= #TCQ sent_row_or_maint;
generate
case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")})
3'b000 : begin : one_one_not2T
end
3'b001 : begin : one_one_2T
end
3'b010 : begin : two_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) begin
cs_en0 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en1 = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
end
3'b011 : begin : two_one_2T
if(!(CWL % 2)) begin // Place column commands on slot 1->0 for even CWL
always @(sent_row_or_maint_r or sent_col_lcl_r)
cs_en0 = sent_row_or_maint_r || sent_col_lcl_r;
always @(sent_row_or_maint or sent_row_or_maint_r) begin
send_cmd0_row = sent_row_or_maint_r;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl or sent_col_lcl_r) begin
send_cmd0_col = sent_col_lcl_r;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 0->1 for odd CWL
always @(sent_col_lcl or sent_row_or_maint)
cs_en1 = sent_row_or_maint || sent_col_lcl;
always @(sent_row_or_maint) begin
send_cmd0_row = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
send_cmd0_col = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
end
3'b100 : begin : four_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) begin
cs_en0 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en1 = sent_col_lcl;
send_cmd1_col = sent_col_lcl;
end
assign col_channel_offset = 1;
end
always @(sent_pre_lcl) begin
cs_en2 = sent_pre_lcl;
send_cmd2_pre = sent_pre_lcl;
end
end
3'b101 : begin : four_one_2T
if(!(CWL % 2)) begin // Place column commands on slot 3->0 for even CWL
always @(sent_col_lcl or sent_col_lcl_r) begin
cs_en0 = sent_col_lcl_r;
send_cmd0_col = sent_col_lcl_r;
send_cmd3_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en2 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
send_cmd2_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 2->3 for odd CWL
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd0_row = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en3 = sent_col_lcl;
send_cmd2_col = sent_col_lcl;
send_cmd3_col = sent_col_lcl;
end
assign col_channel_offset = 3;
end
end
endcase
endgenerate
endmodule
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: blk_mem_gen_v8_3_3.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_3 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_3
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_3 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_3
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_3
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_3
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_3
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (blk_mem_gen_v8_3_3) which is
// declared/implemented further down in this file.
//*****************************************************************************
module blk_mem_gen_v8_3_3_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module blk_mem_gen_v8_3_3_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module blk_mem_gen_v8_3_3_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_3_3",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_3_3" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_3_3_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY)))))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
//assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
// To Fix CR855535
assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
// Modified for Implementing CR_859399
current_contents[0] = !(current_contents[30]);
current_contents[1] = !(current_contents[62]);
/*current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);*/
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
blk_mem_gen_v8_3_3_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
blk_mem_gen_v8_3_3_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
blk_mem_gen_v8_3_3_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_3_3
#(parameter C_CORENAME = "blk_mem_gen_v8_3_3",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = "",
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
output rsta_busy,
output rstb_busy,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
reg RSTA_BUSY = 0;
reg RSTB_BUSY = 0;
// Declaration of internal signals to avoid warnings #927399
wire CLKA;
wire RSTA;
wire ENA;
wire REGCEA;
wire CLKB;
wire RSTB;
wire ENB;
wire REGCEB;
wire INJECTSBITERR;
wire INJECTDBITERR;
wire S_ACLK;
wire S_ARESETN;
wire S_AXI_AWVALID;
wire S_AXI_WLAST;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
wire S_AXI_INJECTSBITERR;
wire S_AXI_INJECTDBITERR;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign rsta_busy = RSTA_BUSY;
assign rstb_busy = RSTB_BUSY;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
// Safety logic related signals
reg [4:0] RSTA_SHFT_REG = 0;
reg POR_A = 0;
reg [4:0] RSTB_SHFT_REG = 0;
reg POR_B = 0;
reg ENA_dly = 0;
reg ENA_dly_D = 0;
reg ENB_dly = 0;
reg ENB_dly_D = 0;
wire RSTA_I_SAFE;
wire RSTB_I_SAFE;
wire ENA_I_SAFE;
wire ENB_I_SAFE;
reg ram_rstram_a_busy = 0;
reg ram_rstreg_a_busy = 0;
reg ram_rstram_b_busy = 0;
reg ram_rstreg_b_busy = 0;
reg ENA_dly_reg = 0;
reg ENB_dly_reg = 0;
reg ENA_dly_reg_D = 0;
reg ENB_dly_reg_D = 0;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
//**************************************************************************
// NO SAFETY LOGIC
//**************************************************************************
generate
if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN
assign ENA_I_SAFE = ena_in;
assign ENB_I_SAFE = ENB;
assign RSTA_I_SAFE = rsta_in;
assign RSTB_I_SAFE = RSTB;
end
endgenerate
//***************************************************************************
// SAFETY LOGIC
// Power-ON Reset Generation
//***************************************************************************
generate
if (C_EN_SAFETY_CKT == 1) begin
always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;
always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];
always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;
always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0];
assign RSTA_I_SAFE = rsta_in | POR_A;
assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);
end
endgenerate
//-----------------------------------------------------------------------------
// -- RSTA/B_BUSY Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG
always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG
always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;
end
endgenerate
generate
if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY
always @(*) RSTB_BUSY = 1'b0;
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG
always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG
always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;
end
endgenerate
//-----------------------------------------------------------------------------
// -- ENA/ENB Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG
always @(posedge clka) begin
ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_D <= #FLOP_DELAY ENA_dly;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG
always @(posedge clka) begin
ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);
end
endgenerate
generate
if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB
assign ENB_I_SAFE = 1'b0;
end
endgenerate
generate
if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_D <= #FLOP_DELAY ENB_dly;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);
end
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
blk_mem_gen_v8_3_3_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_3_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
blk_mem_gen_v8_3_3_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_3_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_3
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
blk_mem_gen_v8_3_3_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_3_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
`ifdef INLINE_A //verilator inline_module
`else //verilator no_inline_module
`endif
bmod bsub3 (.clk, .n(3));
bmod bsub2 (.clk, .n(2));
bmod bsub1 (.clk, .n(1));
bmod bsub0 (.clk, .n(0));
endmodule
module bmod
(input clk,
input [31:0] n);
`ifdef INLINE_B //verilator inline_module
`else //verilator no_inline_module
`endif
cmod csub (.clk, .n);
endmodule
module cmod
(input clk, input [31:0] n);
`ifdef INLINE_C //verilator inline_module
`else //verilator no_inline_module
`endif
reg [31:0] clocal;
always @ (posedge clk) clocal <= n;
dmod dsub (.clk, .n);
endmodule
module dmod (input clk, input [31:0] n);
`ifdef INLINE_D //verilator inline_module
`else //verilator no_inline_module
`endif
reg [31:0] dlocal;
always @ (posedge clk) dlocal <= n;
int cyc;
always @(posedge clk) begin
cyc <= cyc+1;
end
always @(posedge clk) begin
if (cyc>10) begin
`ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); `endif
if (csub.clocal !== n) $stop;
if (dlocal !== n) $stop;
end
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
`ifdef INLINE_A //verilator inline_module
`else //verilator no_inline_module
`endif
bmod bsub3 (.clk, .n(3));
bmod bsub2 (.clk, .n(2));
bmod bsub1 (.clk, .n(1));
bmod bsub0 (.clk, .n(0));
endmodule
module bmod
(input clk,
input [31:0] n);
`ifdef INLINE_B //verilator inline_module
`else //verilator no_inline_module
`endif
cmod csub (.clk, .n);
endmodule
module cmod
(input clk, input [31:0] n);
`ifdef INLINE_C //verilator inline_module
`else //verilator no_inline_module
`endif
reg [31:0] clocal;
always @ (posedge clk) clocal <= n;
dmod dsub (.clk, .n);
endmodule
module dmod (input clk, input [31:0] n);
`ifdef INLINE_D //verilator inline_module
`else //verilator no_inline_module
`endif
reg [31:0] dlocal;
always @ (posedge clk) dlocal <= n;
int cyc;
always @(posedge clk) begin
cyc <= cyc+1;
end
always @(posedge clk) begin
if (cyc>10) begin
`ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); `endif
if (csub.clocal !== n) $stop;
if (dlocal !== n) $stop;
end
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sg_list_reader_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Reads data from the scatter gather list buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_SGR64_RD_0 2'b01
`define S_SGR64_RD_1 2'b11
`define S_SGR64_RD_WAIT 2'b10
`define S_SGR64_CAP_0 2'b00
`define S_SGR64_CAP_1 2'b01
`define S_SGR64_CAP_RDY 2'b10
`timescale 1ns/1ns
module sg_list_reader_64 #(
parameter C_DATA_WIDTH = 9'd64
)
(
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output VALID, // Scatter gather element data is valid
output EMPTY, // Scatter gather elements empty
input REN, // Scatter gather element data read enable
output [63:0] ADDR, // Scatter gather element address
output [31:0] LEN // Scatter gather element length (in words)
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rRdState=`S_SGR64_RD_0, _rRdState=`S_SGR64_RD_0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rCapState=`S_SGR64_CAP_0, _rCapState=`S_SGR64_CAP_0;
reg [C_DATA_WIDTH-1:0] rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rLen=0, _rLen=0;
reg rFifoValid=0, _rFifoValid=0;
reg rDataValid=0, _rDataValid=0;
assign BUF_DATA_REN = rRdState[0]; // Not S_SGR64_RD_WAIT
assign VALID = rCapState[1]; // S_SGR64_CAP_RDY
assign EMPTY = (BUF_DATA_EMPTY & rRdState[0]); // Not S_SGR64_RD_WAIT
assign ADDR = rAddr;
assign LEN = rLen;
// Capture address and length as it comes out of the FIFO
always @ (posedge CLK) begin
rRdState <= #1 (RST ? `S_SGR64_RD_0 : _rRdState);
rCapState <= #1 (RST ? `S_SGR64_CAP_0 : _rCapState);
rData <= #1 _rData;
rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
end
always @ (*) begin
_rRdState = rRdState;
_rCapState = rCapState;
_rAddr = rAddr;
_rLen = rLen;
_rData = BUF_DATA;
_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
_rDataValid = rFifoValid;
case (rCapState)
`S_SGR64_CAP_0: begin
if (rDataValid) begin
_rAddr = rData;
_rCapState = `S_SGR64_CAP_1;
end
end
`S_SGR64_CAP_1: begin
if (rDataValid) begin
_rLen = rData[31:0];
_rCapState = `S_SGR64_CAP_RDY;
end
end
`S_SGR64_CAP_RDY: begin
if (REN)
_rCapState = `S_SGR64_CAP_0;
end
default: begin
_rCapState = `S_SGR64_CAP_0;
end
endcase
case (rRdState)
`S_SGR64_RD_0: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR64_RD_1;
end
`S_SGR64_RD_1: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR64_RD_WAIT;
end
`S_SGR64_RD_WAIT: begin // Wait for the data to be consumed
if (REN)
_rRdState = `S_SGR64_RD_0;
end
default: begin
_rRdState = `S_SGR64_RD_0;
end
endcase
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_128 #(
parameter C_DATA_WIDTH = 9'd128,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_128 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_128 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
/*
Filename: shiftreg.v
Version: 1.0
Verilog Standard: Verilog-2001
Description: A simple parameterized shift register.
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
`timescale 1ns/1ns
module shiftreg
#(parameter C_DEPTH=10,
parameter C_WIDTH=32,
parameter C_VALUE=0
)
(input CLK,
input RST_IN,
input [C_WIDTH-1:0] WR_DATA,
output [(C_DEPTH+1)*C_WIDTH-1:0] RD_DATA);
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
wire [(C_DEPTH+1)*C_WIDTH-1:0] wDataShift;
reg [C_WIDTH-1:0] rDataShift[C_DEPTH:0];
assign wDataShift[(C_WIDTH*0)+:C_WIDTH] = WR_DATA;
always @(posedge CLK) begin
rDataShift[0] <= WR_DATA;
end
genvar i;
generate
for (i = 1 ; i <= C_DEPTH; i = i + 1) begin : gen_sr_registers
assign wDataShift[(C_WIDTH*i)+:C_WIDTH] = rDataShift[i-1];
always @(posedge CLK) begin
if(RST_IN)
rDataShift[i] <= C_VALUE;
else
rDataShift[i] <= rDataShift[i-1];
end
end
endgenerate
assign RD_DATA = wDataShift;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
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// nor the names of its contributors may be used to endorse or
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_port_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the rx_engine and buffers the output
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module rx_port_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_MAIN_FIFO_DEPTH = 1024,
parameter C_SG_FIFO_DEPTH = 512,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),
parameter C_MAIN_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_MAIN_FIFO_DEPTH))+1),
parameter C_SG_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_SG_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input [31:0] SG_RX_BUF_DATA, // Scatter gather RX buffer data
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input [31:0] SG_TX_BUF_DATA, // Scatter gather TX buffer data
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
output [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather TX buffer data
output SG_DATA_EMPTY, // Scatter gather TX buffer data empty
input SG_DATA_REN, // Scatter gather TX buffer data read enable
input SG_RST, // Scatter gather TX buffer data reset
output SG_ERR, // Scatter gather TX encountered an error
input [31:0] TXN_DATA, // Read transaction data
input TXN_LEN_VALID, // Read transaction length valid
input TXN_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_DONE_LEN, // Read transaction actual transfer length
output TXN_DONE, // Read transaction done
input TXN_DONE_ACK, // Read transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
input [C_DATA_WIDTH-1:0] MAIN_DATA, // Main incoming data
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WIDTH-1:0] SG_RX_DATA, // Scatter gather for RX incoming data
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WIDTH-1:0] SG_TX_DATA, // Scatter gather for TX incoming data
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN // Channel read data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wPackedMainData;
wire wPackedMainWen;
wire wPackedMainDone;
wire wPackedMainErr;
wire wMainFlush;
wire wMainFlushed;
wire [C_DATA_WIDTH-1:0] wPackedSgRxData;
wire wPackedSgRxWen;
wire wPackedSgRxDone;
wire wPackedSgRxErr;
wire wSgRxFlush;
wire wSgRxFlushed;
wire [C_DATA_WIDTH-1:0] wPackedSgTxData;
wire wPackedSgTxWen;
wire wPackedSgTxDone;
wire wPackedSgTxErr;
wire wSgTxFlush;
wire wSgTxFlushed;
wire wMainDataRen;
wire wMainDataEmpty;
wire [C_DATA_WIDTH-1:0] wMainData;
wire wSgRxRst;
wire wSgRxDataRen;
wire wSgRxDataEmpty;
wire [C_DATA_WIDTH-1:0] wSgRxData;
wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgRxFifoCount;
wire wSgTxRst;
wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgTxFifoCount;
wire wSgRxReq;
wire [63:0] wSgRxReqAddr;
wire [9:0] wSgRxReqLen;
wire wSgTxReq;
wire [63:0] wSgTxReqAddr;
wire [9:0] wSgTxReqLen;
wire wSgRxReqProc;
wire wSgTxReqProc;
wire wMainReqProc;
wire wReqAck;
wire wSgElemRdy;
wire wSgElemRen;
wire [63:0] wSgElemAddr;
wire [31:0] wSgElemLen;
wire wSgRst;
wire wMainReq;
wire [63:0] wMainReqAddr;
wire [9:0] wMainReqLen;
wire wTxnErr;
wire wChnlRx;
wire wChnlRxRecvd;
wire wChnlRxAckRecvd;
wire wChnlRxLast;
wire [31:0] wChnlRxLen;
wire [30:0] wChnlRxOff;
wire [31:0] wChnlRxConsumed;
reg [4:0] rWideRst=0;
reg rRst=0;
assign SG_ERR = (wPackedSgTxDone & wPackedSgTxErr);
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Pack received data tightly into our FIFOs
fifo_packer_64 mainFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(MAIN_DATA),
.DATA_IN_EN(MAIN_DATA_EN),
.DATA_IN_DONE(MAIN_DONE),
.DATA_IN_ERR(MAIN_ERR),
.DATA_IN_FLUSH(wMainFlush),
.PACKED_DATA(wPackedMainData),
.PACKED_WEN(wPackedMainWen),
.PACKED_DATA_DONE(wPackedMainDone),
.PACKED_DATA_ERR(wPackedMainErr),
.PACKED_DATA_FLUSHED(wMainFlushed)
);
fifo_packer_64 sgRxFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(SG_RX_DATA),
.DATA_IN_EN(SG_RX_DATA_EN),
.DATA_IN_DONE(SG_RX_DONE),
.DATA_IN_ERR(SG_RX_ERR),
.DATA_IN_FLUSH(wSgRxFlush),
.PACKED_DATA(wPackedSgRxData),
.PACKED_WEN(wPackedSgRxWen),
.PACKED_DATA_DONE(wPackedSgRxDone),
.PACKED_DATA_ERR(wPackedSgRxErr),
.PACKED_DATA_FLUSHED(wSgRxFlushed)
);
fifo_packer_64 sgTxFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(SG_TX_DATA),
.DATA_IN_EN(SG_TX_DATA_EN),
.DATA_IN_DONE(SG_TX_DONE),
.DATA_IN_ERR(SG_TX_ERR),
.DATA_IN_FLUSH(wSgTxFlush),
.PACKED_DATA(wPackedSgTxData),
.PACKED_WEN(wPackedSgTxWen),
.PACKED_DATA_DONE(wPackedSgTxDone),
.PACKED_DATA_ERR(wPackedSgTxErr),
.PACKED_DATA_FLUSHED(wSgTxFlushed)
);
// FIFOs for storing received data for the channel.
(* RAM_STYLE="BLOCK" *)
async_fifo_fwft #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_MAIN_FIFO_DEPTH)) mainFifo (
.WR_CLK(CLK),
.WR_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
.WR_EN(wPackedMainWen),
.WR_DATA(wPackedMainData),
.WR_FULL(),
.RD_CLK(CHNL_CLK),
.RD_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
.RD_EN(wMainDataRen),
.RD_DATA(wMainData),
.RD_EMPTY(wMainDataEmpty)
);
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgRxFifo (
.RST(rRst | wSgRxRst),
.CLK(CLK),
.WR_EN(wPackedSgRxWen),
.WR_DATA(wPackedSgRxData),
.FULL(),
.RD_EN(wSgRxDataRen),
.RD_DATA(wSgRxData),
.EMPTY(wSgRxDataEmpty),
.COUNT(wSgRxFifoCount)
);
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgTxFifo (
.RST(rRst | wSgTxRst),
.CLK(CLK),
.WR_EN(wPackedSgTxWen),
.WR_DATA(wPackedSgTxData),
.FULL(),
.RD_EN(SG_DATA_REN),
.RD_DATA(SG_DATA),
.EMPTY(SG_DATA_EMPTY),
.COUNT(wSgTxFifoCount)
);
// Manage requesting and acknowledging scatter gather data. Note that
// these modules will share the main requestor's RX channel. They will
// take priority over the main logic's use of the RX channel.
sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgRxReq (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.USER_RST(wSgRst),
.BUF_RECVD(SG_RX_BUF_RECVD),
.BUF_DATA(SG_RX_BUF_DATA),
.BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.FIFO_COUNT(wSgRxFifoCount),
.FIFO_FLUSH(wSgRxFlush),
.FIFO_FLUSHED(wSgRxFlushed),
.FIFO_RST(wSgRxRst),
.RX_REQ(wSgRxReq),
.RX_ADDR(wSgRxReqAddr),
.RX_LEN(wSgRxReqLen),
.RX_REQ_ACK(wReqAck & wSgRxReqProc),
.RX_DONE(wPackedSgRxDone)
);
sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgTxReq (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.USER_RST(SG_RST),
.BUF_RECVD(SG_TX_BUF_RECVD),
.BUF_DATA(SG_TX_BUF_DATA),
.BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.FIFO_COUNT(wSgTxFifoCount),
.FIFO_FLUSH(wSgTxFlush),
.FIFO_FLUSHED(wSgTxFlushed),
.FIFO_RST(wSgTxRst),
.RX_REQ(wSgTxReq),
.RX_ADDR(wSgTxReqAddr),
.RX_LEN(wSgTxReqLen),
.RX_REQ_ACK(wReqAck & wSgTxReqProc),
.RX_DONE(wPackedSgTxDone)
);
// A read requester for the channel and scatter gather requesters.
rx_port_requester_mux requesterMux (
.RST(rRst),
.CLK(CLK),
.SG_RX_REQ(wSgRxReq),
.SG_RX_LEN(wSgRxReqLen),
.SG_RX_ADDR(wSgRxReqAddr),
.SG_RX_REQ_PROC(wSgRxReqProc),
.SG_TX_REQ(wSgTxReq),
.SG_TX_LEN(wSgTxReqLen),
.SG_TX_ADDR(wSgTxReqAddr),
.SG_TX_REQ_PROC(wSgTxReqProc),
.MAIN_REQ(wMainReq),
.MAIN_LEN(wMainReqLen),
.MAIN_ADDR(wMainReqAddr),
.MAIN_REQ_PROC(wMainReqProc),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.REQ_ACK(wReqAck)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | wSgRst),
.BUF_DATA(wSgRxData),
.BUF_DATA_EMPTY(wSgRxDataEmpty),
.BUF_DATA_REN(wSgRxDataRen),
.VALID(wSgElemRdy),
.EMPTY(),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Main port reader logic
rx_port_reader #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_MAIN_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) reader (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.TXN_DATA(TXN_DATA),
.TXN_LEN_VALID(TXN_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.TXN_DATA_FLUSH(wMainFlush),
.TXN_DATA_FLUSHED(wMainFlushed),
.RX_REQ(wMainReq),
.RX_ADDR(wMainReqAddr),
.RX_LEN(wMainReqLen),
.RX_REQ_ACK(wReqAck & wMainReqProc),
.RX_DATA_EN(MAIN_DATA_EN),
.RX_DONE(wPackedMainDone),
.RX_ERR(wPackedMainErr),
.SG_DONE(wPackedSgRxDone),
.SG_ERR(wPackedSgRxErr),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(wSgRst),
.CHNL_RX(wChnlRx),
.CHNL_RX_LEN(wChnlRxLen),
.CHNL_RX_LAST(wChnlRxLast),
.CHNL_RX_OFF(wChnlRxOff),
.CHNL_RX_RECVD(wChnlRxRecvd),
.CHNL_RX_ACK_RECVD(wChnlRxAckRecvd),
.CHNL_RX_CONSUMED(wChnlRxConsumed)
);
// Manage the CHNL_RX* signals in the CHNL_CLK domain.
rx_port_channel_gate #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.CLK(CLK),
.RX(wChnlRx),
.RX_RECVD(wChnlRxRecvd),
.RX_ACK_RECVD(wChnlRxAckRecvd),
.RX_LAST(wChnlRxLast),
.RX_LEN(wChnlRxLen),
.RX_OFF(wChnlRxOff),
.RX_CONSUMED(wChnlRxConsumed),
.RD_DATA(wMainData),
.RD_EMPTY(wMainDataEmpty),
.RD_EN(wMainDataRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({SG_RX_DATA_EN != 0, wSgElemRen, wMainReq | wSgRxReq | wSgTxReq,
RX_REQ, SG_RX_BUF_ADDR_LO_VALID | SG_RX_BUF_ADDR_HI_VALID | SG_RX_BUF_LEN_VALID,
wSgRst, wTxnErr | wPackedSgRxDone | wSgRxFlush | wSgRxFlushed, TXN_OFF_LAST_VALID | TXN_LEN_VALID}),
.DATA({
wPackedSgRxErr, // 1
wPackedSgRxDone, // 1
wPackedSgRxWen, // 1
wPackedSgRxData, // 64
SG_RX_ERR, // 1
SG_RX_DONE, // 1
SG_RX_DATA_EN, // 2
SG_RX_DATA, // 64
wSgRxDataRen, // 1
wSgRxDataEmpty, // 1
wSgRxData, // 64
wSgRst, // 1
SG_RST, // 1
wPackedSgRxDone, // 1
wSgRxRst, // 1
wSgRxFlushed, // 1
wSgRxFlush, // 1
SG_RX_BUF_ADDR_LO_VALID, // 1
SG_RX_BUF_ADDR_HI_VALID, // 1
SG_RX_BUF_LEN_VALID, // 1
SG_RX_BUF_DATA, // 32
RX_REQ_ADDR, // 64
RX_REQ_TAG, // 2
RX_REQ_ACK, // 1
RX_REQ, // 1
wSgTxReqProc, // 1
wSgTxReqAddr, // 64
wSgTxReq, // 1
wSgRxReqProc, // 1
wSgRxReqAddr, // 64
wSgRxReq, // 1
wMainReqProc, // 1
wMainReqAddr, // 64
wMainReq, // 1
wReqAck, // 1
wTxnErr, // 1
TXN_OFF_LAST_VALID, // 1
TXN_LEN_VALID}) // 1
);
*/
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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// possibility of the same.
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// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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// applications related to the deployment of airbags, or any
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// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : round_robin_arb.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// A simple round robin arbiter implemented in a not so simple
// way. Two things make this special. First, it takes width as
// a parameter and secondly it's constructed in a way to work with
// restrictions synthesis programs.
//
// Consider each req/grant pair to be a
// "channel". The arbiter computes a grant response to a request
// on a channel by channel basis.
//
// The arbiter implementes a "round robin" algorithm. Ie, the granting
// process is totally fair and symmetric. Each requester is given
// equal priority. If all requests are asserted, the arbiter will
// work sequentially around the list of requesters, giving each a grant.
//
// Grant priority is based on the "last_master". The last_master
// vector stores the channel receiving the most recent grant. The
// next higher numbered channel (wrapping around to zero) has highest
// priority in subsequent cycles. Relative priority wraps around
// the request vector with the last_master channel having lowest priority.
//
// At the highest implementation level, a per channel inhibit signal is computed.
// This inhibit is bit-wise AND'ed with the incoming requests to
// generate the grant.
//
// There will be at most a single grant per state. The logic
// of the arbiter depends on this.
//
// Once a grant is given, it is stored as the last_master. The
// last_master vector is initialized at reset to the zero'th channel.
// Although the particular channel doesn't matter, it does matter
// that the last_master contains a valid grant pattern.
//
// The heavy lifting is in computing the per channel inhibit signals.
// This is accomplished in the generate statement.
//
// The first "for" loop in the generate statement steps through the channels.
//
// The second "for" loop steps through the last mast_master vector
// for each channel. For each last_master bit, an inh_group is generated.
// Following the end of the second "for" loop, the inh_group signals are OR'ed
// together to generate the overall inhibit bit for the channel.
//
// For a four bit wide arbiter, this is what's generated for channel zero:
//
// inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits
// inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit
// inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits
//
// For req[0], last_master[3] is ignored because channel zero is highest priority
// if last_master[3] is true.
//
`timescale 1ps/1ps
module mig_7series_v1_9_round_robin_arb
#(
parameter TCQ = 100,
parameter WIDTH = 3
)
(
/*AUTOARG*/
// Outputs
grant_ns, grant_r,
// Inputs
clk, rst, req, disable_grant, current_master, upd_last_master
);
input clk;
input rst;
input [WIDTH-1:0] req;
wire [WIDTH-1:0] last_master_ns;
reg [WIDTH*2-1:0] dbl_last_master_ns;
always @(/*AS*/last_master_ns)
dbl_last_master_ns = {last_master_ns, last_master_ns};
reg [WIDTH*2-1:0] dbl_req;
always @(/*AS*/req) dbl_req = {req, req};
reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}};
genvar i;
genvar j;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : channel
wire [WIDTH-1:1] inh_group;
for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master
assign inh_group[j+1] =
dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1];
end
always @(/*AS*/inh_group) inhibit[i] = |inh_group;
end
endgenerate
input disable_grant;
output wire [WIDTH-1:0] grant_ns;
assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}};
output reg [WIDTH-1:0] grant_r;
always @(posedge clk) grant_r <= #TCQ grant_ns;
input [WIDTH-1:0] current_master;
input upd_last_master;
reg [WIDTH-1:0] last_master_r;
localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024
//A '1' in the LSB of the last_master_r
//signal gives a low priority to req[0]
//after reset. To avoid this made MSB as
//'1' at reset.
assign last_master_ns = rst
? ONE[0+:WIDTH]
: upd_last_master
? current_master
: last_master_r;
always @(posedge clk) last_master_r <= #TCQ last_master_ns;
`ifdef MC_SVA
grant_is_one_hot_zero:
assert property (@(posedge clk) (rst || $onehot0(grant_ns)));
last_master_r_is_one_hot:
assert property (@(posedge clk) (rst || $onehot(last_master_r)));
`endif
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
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// reasonably foreseeable or Xilinx had been advised of the
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_select.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Based on granta_r and grantc_r, this module selects a
// row and column command from the request information
// provided by the bank machines.
//
// Depending on address mode configuration, nCL and nCWL, a column
// command pipeline of up to three states will be created.
`timescale 1 ps / 1 ps
module mig_7series_v1_9_arb_select #
(
parameter TCQ = 100,
parameter EVEN_CWL_2T_MODE = "OFF",
parameter ADDR_CMD_MODE = "1T",
parameter BANK_VECT_INDX = 11,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter CL = 5,
parameter CWL = 5,
parameter DATA_BUF_ADDR_VECT_INDX = 31,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCS_PER_RANK = 1,
parameter CKE_ODT_AUX = "FALSE",
parameter nSLOTS = 2,
parameter RANKS = 1,
parameter RANK_VECT_INDX = 15,
parameter RANK_WIDTH = 2,
parameter ROW_VECT_INDX = 63,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010
)
(
// Outputs
output wire col_periodic_rd,
output wire [RANK_WIDTH-1:0] col_ra,
output wire [BANK_WIDTH-1:0] col_ba,
output wire [ROW_WIDTH-1:0] col_a,
output wire col_rmw,
output wire col_rd_wr,
output wire col_size,
output wire [ROW_WIDTH-1:0] col_row,
output wire [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,
output wire [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [1:0] mc_odt,
output wire [nCK_PER_CLK-1:0] mc_cke,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output wire [5:0] mc_data_offset,
output wire [5:0] mc_data_offset_1,
output wire [5:0] mc_data_offset_2,
output wire [1:0] mc_cas_slot,
output wire [RANK_WIDTH-1:0] rnk_config,
// Inputs
input clk,
input rst,
input init_calib_complete,
input [RANK_VECT_INDX:0] req_rank_r,
input [BANK_VECT_INDX:0] req_bank_r,
input [nBANK_MACHS-1:0] req_ras,
input [nBANK_MACHS-1:0] req_cas,
input [nBANK_MACHS-1:0] req_wr_r,
input [nBANK_MACHS-1:0] grant_row_r,
input [nBANK_MACHS-1:0] grant_pre_r,
input [ROW_VECT_INDX:0] row_addr,
input [nBANK_MACHS-1:0] row_cmd_wr,
input insert_maint_r1,
input maint_zq_r,
input maint_sre_r,
input maint_srx_r,
input [RANK_WIDTH-1:0] maint_rank_r,
input [nBANK_MACHS-1:0] req_periodic_rd_r,
input [nBANK_MACHS-1:0] req_size_r,
input [nBANK_MACHS-1:0] rd_wr_r,
input [ROW_VECT_INDX:0] req_row_r,
input [ROW_VECT_INDX:0] col_addr,
input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,
input [nBANK_MACHS-1:0] grant_col_r,
input [nBANK_MACHS-1:0] grant_col_wr,
input [6*RANKS-1:0] calib_rddata_offset,
input [6*RANKS-1:0] calib_rddata_offset_1,
input [6*RANKS-1:0] calib_rddata_offset_2,
input [5:0] col_channel_offset,
input [nBANK_MACHS-1:0] grant_config_r,
input rnk_config_strobe,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
input send_cmd0_row,
input send_cmd0_col,
input send_cmd1_row,
input send_cmd1_col,
input send_cmd2_row,
input send_cmd2_col,
input send_cmd2_pre,
input send_cmd3_col,
input sent_col,
input cs_en0,
input cs_en1,
input cs_en2,
input cs_en3
);
localparam OUT_CMD_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + 1 + 1 + 1;
reg col_rd_wr_ns;
reg col_rd_wr_r = 1'b0;
reg [OUT_CMD_WIDTH-1:0] col_cmd_r = {OUT_CMD_WIDTH {1'b0}};
reg [OUT_CMD_WIDTH-1:0] row_cmd_r = {OUT_CMD_WIDTH {1'b0}};
// calib_rd_data_offset for currently targeted rank
reg [5:0] rank_rddata_offset_0;
reg [5:0] rank_rddata_offset_1;
reg [5:0] rank_rddata_offset_2;
// Toggle CKE[0] when entering and exiting self-refresh, disable CKE[1]
assign mc_aux_out0[0] = (maint_sre_r || maint_srx_r) & insert_maint_r1;
assign mc_aux_out0[2] = 1'b0;
reg cke_r;
reg cke_ns;
generate
if(CKE_ODT_AUX == "FALSE")begin
always @(posedge clk)
begin
if (rst)
cke_r = 1'b1;
else
cke_r = cke_ns;
end
always @(*)
begin
cke_ns = 1'b1;
if (maint_sre_r & insert_maint_r1)
cke_ns = 1'b0;
else if (cke_r==1'b0)
begin
if (maint_srx_r & insert_maint_r1)
cke_ns = 1'b1;
else
cke_ns = 1'b0;
end
end
end
endgenerate
// Disable ODT & CKE toggle enable high bits
assign mc_aux_out1 = 4'b0;
// implement PHY command word
assign mc_cmd[0] = sent_col;
assign mc_cmd[1] = EVEN_CWL_2T_MODE == "ON" ?
sent_col && col_rd_wr_r :
sent_col && col_rd_wr_ns;
assign mc_cmd[2] = ~sent_col;
// generate calib_rd_data_offset for current rank - only use rank 0 values for now
always @(calib_rddata_offset or calib_rddata_offset_1 or calib_rddata_offset_2) begin
rank_rddata_offset_0 = calib_rddata_offset[5:0];
rank_rddata_offset_1 = calib_rddata_offset_1[5:0];
rank_rddata_offset_2 = calib_rddata_offset_2[5:0];
end
// generate data offset
generate
if(EVEN_CWL_2T_MODE == "ON") begin : gen_mc_data_offset_even_cwl_2t
assign mc_data_offset = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_0 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_1 = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_1 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_2 = ~sent_col ?
6'b0 :
col_rd_wr_r ?
rank_rddata_offset_2 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
end
else begin : gen_mc_data_offset_not_even_cwl_2t
assign mc_data_offset = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_0 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_1 = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_1 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
assign mc_data_offset_2 = ~sent_col ?
6'b0 :
col_rd_wr_ns ?
rank_rddata_offset_2 + col_channel_offset :
nCK_PER_CLK == 2 ?
CWL - 2 + col_channel_offset :
// nCK_PER_CLK == 4
CWL + 2 + col_channel_offset;
end
endgenerate
assign mc_cas_slot = col_channel_offset[1:0];
// Based on arbitration results, select the row and column commands.
integer i;
reg [OUT_CMD_WIDTH-1:0] row_cmd_ns;
generate
begin : row_mux
wire [OUT_CMD_WIDTH-1:0] maint_cmd =
{maint_rank_r, // maintenance rank
row_cmd_r[15+:(BANK_WIDTH+ROW_WIDTH-11)],
// bank plus upper address bits
1'b0, // A10 = 0 for ZQCS
row_cmd_r[3+:10], // address bits [9:0]
// ZQ, SRX or SRE/REFRESH
(maint_zq_r ? 3'b110 : maint_srx_r ? 3'b111 : 3'b001)
};
always @(/*AS*/grant_row_r or insert_maint_r1 or maint_cmd
or req_bank_r or req_cas or req_rank_r or req_ras
or row_addr or row_cmd_r or row_cmd_wr or rst)
begin
row_cmd_ns = rst
? {RANK_WIDTH{1'b0}}
: insert_maint_r1
? maint_cmd
: row_cmd_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_row_r[i])
row_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
row_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
req_ras[i],
req_cas[i],
row_cmd_wr[i]};
end
if (ADDR_CMD_MODE == "2T" && nCK_PER_CLK == 2)
always @(posedge clk) row_cmd_r <= #TCQ row_cmd_ns;
end // row_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] pre_cmd_ns;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_mux
reg [OUT_CMD_WIDTH-1:0] pre_cmd_r = {OUT_CMD_WIDTH {1'b0}};
always @(/*AS*/grant_pre_r or req_bank_r or req_cas or req_rank_r or req_ras
or row_addr or pre_cmd_r or row_cmd_wr or rst)
begin
pre_cmd_ns = rst
? {RANK_WIDTH{1'b0}}
: pre_cmd_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_pre_r[i])
pre_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
row_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
req_ras[i],
req_cas[i],
row_cmd_wr[i]};
end
end // pre_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] col_cmd_ns;
generate
begin : col_mux
reg col_periodic_rd_ns;
reg col_periodic_rd_r;
reg col_rmw_ns;
reg col_rmw_r;
reg col_size_ns;
reg col_size_r;
reg [ROW_WIDTH-1:0] col_row_ns;
reg [ROW_WIDTH-1:0] col_row_r;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr_ns;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr_r;
always @(col_addr or col_cmd_r or col_data_buf_addr_r
or col_periodic_rd_r or col_rmw_r or col_row_r
or col_size_r or grant_col_r or rd_wr_r or req_bank_r
or req_data_buf_addr_r or req_periodic_rd_r
or req_rank_r or req_row_r or req_size_r or req_wr_r
or rst or col_rd_wr_r)
begin
col_periodic_rd_ns = ~rst && col_periodic_rd_r;
col_cmd_ns = {(rst ? {RANK_WIDTH{1'b0}}
: col_cmd_r[(OUT_CMD_WIDTH-1)-:RANK_WIDTH]),
((rst && ECC != "OFF")
? {OUT_CMD_WIDTH-3-RANK_WIDTH{1'b0}}
: col_cmd_r[3+:(OUT_CMD_WIDTH-3-RANK_WIDTH)]),
(rst ? 3'b0 : col_cmd_r[2:0])};
col_rmw_ns = col_rmw_r;
col_size_ns = rst ? 1'b0 : col_size_r;
col_row_ns = col_row_r;
col_rd_wr_ns = col_rd_wr_r;
col_data_buf_addr_ns = col_data_buf_addr_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_col_r[i]) begin
col_periodic_rd_ns = req_periodic_rd_r[i];
col_cmd_ns = {req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH],
req_bank_r[(BANK_WIDTH*i)+:BANK_WIDTH],
col_addr[(ROW_WIDTH*i)+:ROW_WIDTH],
1'b1,
1'b0,
rd_wr_r[i]};
col_rmw_ns = req_wr_r[i] && rd_wr_r[i];
col_size_ns = req_size_r[i];
col_row_ns = req_row_r[(ROW_WIDTH*i)+:ROW_WIDTH];
col_rd_wr_ns = rd_wr_r[i];
col_data_buf_addr_ns =
req_data_buf_addr_r[(DATA_BUF_ADDR_WIDTH*i)+:DATA_BUF_ADDR_WIDTH];
end
end // always @ (...
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_data_addr_off
assign col_wr_data_buf_addr = col_data_buf_addr_ns;
end
else begin : early_wr_data_addr_on
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_ns;
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(/*AS*/col_wr_data_buf_addr_r or grant_col_wr
or req_data_buf_addr_r) begin
col_wr_data_buf_addr_ns = col_wr_data_buf_addr_r;
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_col_wr[i])
col_wr_data_buf_addr_ns =
req_data_buf_addr_r[(DATA_BUF_ADDR_WIDTH*i)+:DATA_BUF_ADDR_WIDTH];
end
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr_ns;
assign col_wr_data_buf_addr = col_wr_data_buf_addr_ns;
end
always @(posedge clk) col_periodic_rd_r <= #TCQ col_periodic_rd_ns;
always @(posedge clk) col_rmw_r <= #TCQ col_rmw_ns;
always @(posedge clk) col_size_r <= #TCQ col_size_ns;
always @(posedge clk) col_data_buf_addr_r <=
#TCQ col_data_buf_addr_ns;
if (ECC != "OFF" || EVEN_CWL_2T_MODE == "ON") begin
always @(posedge clk) col_cmd_r <= #TCQ col_cmd_ns;
always @(posedge clk) col_row_r <= #TCQ col_row_ns;
end
always @(posedge clk) col_rd_wr_r <= #TCQ col_rd_wr_ns;
if(EVEN_CWL_2T_MODE == "ON") begin
assign col_periodic_rd = col_periodic_rd_r;
assign col_ra = col_cmd_r[3+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign col_ba = col_cmd_r[3+ROW_WIDTH+:BANK_WIDTH];
assign col_a = col_cmd_r[3+:ROW_WIDTH];
assign col_rmw = col_rmw_r;
assign col_rd_wr = col_rd_wr_r;
assign col_size = col_size_r;
assign col_row = col_row_r;
assign col_data_buf_addr = col_data_buf_addr_r;
end
else begin
assign col_periodic_rd = col_periodic_rd_ns;
assign col_ra = col_cmd_ns[3+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign col_ba = col_cmd_ns[3+ROW_WIDTH+:BANK_WIDTH];
assign col_a = col_cmd_ns[3+:ROW_WIDTH];
assign col_rmw = col_rmw_ns;
assign col_rd_wr = col_rd_wr_ns;
assign col_size = col_size_ns;
assign col_row = col_row_ns;
assign col_data_buf_addr = col_data_buf_addr_ns;
end
end // col_mux
endgenerate
reg [OUT_CMD_WIDTH-1:0] cmd0 = {OUT_CMD_WIDTH{1'b1}};
reg cke0;
always @(send_cmd0_row or send_cmd0_col or row_cmd_ns or row_cmd_r or col_cmd_ns or col_cmd_r or cke_ns or cke_r ) begin
cmd0 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd0_row) cmd0 = row_cmd_ns;
if (send_cmd0_row && EVEN_CWL_2T_MODE == "ON" && nCK_PER_CLK == 2) cmd0 = row_cmd_r;
if (send_cmd0_col) cmd0 = col_cmd_ns;
if (send_cmd0_col && EVEN_CWL_2T_MODE == "ON") cmd0 = col_cmd_r;
if (send_cmd0_row) cke0 = cke_ns;
else cke0 = cke_r ;
end
reg [OUT_CMD_WIDTH-1:0] cmd1 = {OUT_CMD_WIDTH{1'b1}};
generate
if ((nCK_PER_CLK == 2) || (nCK_PER_CLK == 4))
always @(send_cmd1_row or send_cmd1_col or row_cmd_ns or col_cmd_ns or pre_cmd_ns) begin
cmd1 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd1_row) cmd1 = row_cmd_ns;
if (send_cmd1_col) cmd1 = col_cmd_ns;
end
endgenerate
reg [OUT_CMD_WIDTH-1:0] cmd2 = {OUT_CMD_WIDTH{1'b1}};
reg [OUT_CMD_WIDTH-1:0] cmd3 = {OUT_CMD_WIDTH{1'b1}};
generate
if (nCK_PER_CLK == 4)
always @(send_cmd2_row or send_cmd2_col or send_cmd2_pre or send_cmd3_col or row_cmd_ns or col_cmd_ns or pre_cmd_ns) begin
cmd2 = {OUT_CMD_WIDTH{1'b1}};
cmd3 = {OUT_CMD_WIDTH{1'b1}};
if (send_cmd2_row) cmd2 = row_cmd_ns;
if (send_cmd2_col) cmd2 = col_cmd_ns;
if (send_cmd2_pre) cmd2 = pre_cmd_ns;
if (send_cmd3_col) cmd3 = col_cmd_ns;
end
endgenerate
// Output command bus 0.
wire [RANK_WIDTH-1:0] ra0;
// assign address
assign {ra0, mc_bank[BANK_WIDTH-1:0], mc_address[ROW_WIDTH-1:0], mc_ras_n[0], mc_cas_n[0], mc_we_n[0]} = cmd0;
// Output command bus 1.
wire [RANK_WIDTH-1:0] ra1;
// assign address
assign {ra1, mc_bank[2*BANK_WIDTH-1:BANK_WIDTH], mc_address[2*ROW_WIDTH-1:ROW_WIDTH], mc_ras_n[1], mc_cas_n[1], mc_we_n[1]} = cmd1;
wire [RANK_WIDTH-1:0] ra2;
wire [RANK_WIDTH-1:0] ra3;
generate
if(nCK_PER_CLK == 4) begin
// Output command bus 2.
// assign address
assign {ra2, mc_bank[3*BANK_WIDTH-1:2*BANK_WIDTH], mc_address[3*ROW_WIDTH-1:2*ROW_WIDTH], mc_ras_n[2], mc_cas_n[2], mc_we_n[2]} = cmd2;
// Output command bus 3.
// assign address
assign {ra3, mc_bank[4*BANK_WIDTH-1:3*BANK_WIDTH], mc_address[4*ROW_WIDTH-1:3*ROW_WIDTH], mc_ras_n[3], mc_cas_n[3], mc_we_n[3]} =
cmd3;
end
endgenerate
generate
if(CKE_ODT_AUX == "FALSE")begin
assign mc_cke[0] = cke0;
assign mc_cke[1] = cke_ns;
if(nCK_PER_CLK == 4) begin
assign mc_cke[2] = cke_ns;
assign mc_cke[3] = cke_ns;
end
end
endgenerate
// Output cs busses.
localparam ONE = {nCS_PER_RANK{1'b1}};
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] cs_one_hot =
{{CS_WIDTH{1'b0}},ONE};
assign mc_cs_n[CS_WIDTH*nCS_PER_RANK -1 :0 ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra0)) | {CS_WIDTH*nCS_PER_RANK{~cs_en0}})};
assign mc_cs_n[2*CS_WIDTH*nCS_PER_RANK -1 : CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra1)) | {CS_WIDTH*nCS_PER_RANK{~cs_en1}})};
generate
if(nCK_PER_CLK == 4) begin
assign mc_cs_n[3*CS_WIDTH*nCS_PER_RANK -1 :2*CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra2)) | {CS_WIDTH*nCS_PER_RANK{~cs_en2}})};
assign mc_cs_n[4*CS_WIDTH*nCS_PER_RANK -1 :3*CS_WIDTH*nCS_PER_RANK ] =
{(~(cs_one_hot << (nCS_PER_RANK*ra3)) | {CS_WIDTH*nCS_PER_RANK{~cs_en3}})};
end
endgenerate
// Output rnk_config info.
reg [RANK_WIDTH-1:0] rnk_config_ns;
reg [RANK_WIDTH-1:0] rnk_config_r;
always @(/*AS*/grant_config_r
or rnk_config_r or rnk_config_strobe or req_rank_r or rst) begin
if (rst) rnk_config_ns = {RANK_WIDTH{1'b0}};
else begin
rnk_config_ns = rnk_config_r;
if (rnk_config_strobe)
for (i=0; i<nBANK_MACHS; i=i+1)
if (grant_config_r[i]) rnk_config_ns = req_rank_r[(RANK_WIDTH*i)+:RANK_WIDTH];
end
end
always @(posedge clk) rnk_config_r <= #TCQ rnk_config_ns;
assign rnk_config = rnk_config_ns;
// Generate ODT signals.
wire [CS_WIDTH-1:0] col_ra_one_hot = cs_one_hot << col_ra;
wire slot_0_select = (nSLOTS == 1) ? |(col_ra_one_hot & slot_0_present)
: (slot_0_present[2] & slot_0_present[0]) ?
|(col_ra_one_hot[CS_WIDTH-1:0] & {slot_0_present[2],
slot_0_present[0]}) : (slot_0_present[0])?
col_ra_one_hot[0] : 1'b0;
wire slot_0_read = EVEN_CWL_2T_MODE == "ON" ?
slot_0_select && col_rd_wr_r :
slot_0_select && col_rd_wr_ns;
wire slot_0_write = EVEN_CWL_2T_MODE == "ON" ?
slot_0_select && ~col_rd_wr_r :
slot_0_select && ~col_rd_wr_ns;
reg [1:0] slot_1_population = 2'b0;
reg[1:0] slot_0_population;
always @(/*AS*/slot_0_present) begin
slot_0_population = 2'b0;
for (i=0; i<8; i=i+1)
if (~slot_0_population[1])
if (slot_0_present[i] == 1'b1) slot_0_population =
slot_0_population + 2'b1;
end
// ODT on in slot 0 for writes to slot 0 (and R/W to slot 1 for DDR3)
wire slot_0_odt = (DRAM_TYPE == "DDR3") ? ~slot_0_read : slot_0_write;
assign mc_aux_out0[1] = slot_0_odt & sent_col; // Only send for COL cmds
generate
if (nSLOTS > 1) begin : slot_1_configured
wire slot_1_select = (slot_1_present[3] & slot_1_present[1])?
|({col_ra_one_hot[slot_0_population+1],
col_ra_one_hot[slot_0_population]}) :
(slot_1_present[1]) ? col_ra_one_hot[slot_0_population] :1'b0;
wire slot_1_read = EVEN_CWL_2T_MODE == "ON" ?
slot_1_select && col_rd_wr_r :
slot_1_select && col_rd_wr_ns;
wire slot_1_write = EVEN_CWL_2T_MODE == "ON" ?
slot_1_select && ~col_rd_wr_r :
slot_1_select && ~col_rd_wr_ns;
// ODT on in slot 1 for writes to slot 1 (and R/W to slot 0 for DDR3)
wire slot_1_odt = (DRAM_TYPE == "DDR3") ? ~slot_1_read : slot_1_write;
assign mc_aux_out0[3] = slot_1_odt & sent_col; // Only send for COL cmds
end // if (nSLOTS > 1)
else begin
// Disable slot 1 ODT when not present
assign mc_aux_out0[3] = 1'b0;
end // else: !if(nSLOTS > 1)
endgenerate
generate
if(CKE_ODT_AUX == "FALSE")begin
reg[1:0] mc_aux_out_r ;
reg[1:0] mc_aux_out_r_1 ;
reg[1:0] mc_aux_out_r_2 ;
always@(posedge clk) begin
mc_aux_out_r[0] <= #TCQ mc_aux_out0[1] ;
mc_aux_out_r[1] <= #TCQ mc_aux_out0[3] ;
mc_aux_out_r_1 <= #TCQ mc_aux_out_r ;
mc_aux_out_r_2 <= #TCQ mc_aux_out_r_1 ;
end
if((nCK_PER_CLK == 4) && (nSLOTS > 1 )) begin:odt_high_time_4_1_dslot
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0];
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1];
end else if(nCK_PER_CLK == 4) begin:odt_high_time_4_1
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] ;
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] ;
end else if(nCK_PER_CLK == 2) begin:odt_high_time_2_1
assign mc_odt[0] = mc_aux_out0[1] | mc_aux_out_r[0] | mc_aux_out_r_1[0] | mc_aux_out_r_2[0] ;
assign mc_odt[1] = mc_aux_out0[3] | mc_aux_out_r[1] | mc_aux_out_r_1[1] | mc_aux_out_r_2[1] ;
end
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_oclkdelay_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Center write DQS in write DQ valid window using Phaser_Out Stage3
// delay
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_oclkdelay_cal #
(
parameter TCQ = 100,
parameter tCK = 2500,
parameter nCK_PER_CLK = 4,
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8,
parameter DQ_WIDTH = 64,
parameter SIM_CAL_OPTION = "NONE",
parameter OCAL_EN = "ON"
)
(
input clk,
input rst,
// Start only after PO and PI FINE delay decremented
input oclk_init_delay_start,
input oclkdelay_calib_start,
input [5:0] oclkdelay_init_val,
// Detect write valid data edge during OCLKDELAY calib
input phy_rddata_en,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Precharge done status from ddr_phy_init
input prech_done,
// Write Level signals during OCLKDELAY calibration
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
output reg wrlvl_final,
// Inc/dec Phaser_Out fine delay line
output reg po_stg3_incdec,
output reg po_en_stg3,
output reg po_stg23_sel,
output reg po_stg23_incdec,
output reg po_en_stg23,
// Completed initial delay increment
output oclk_init_delay_done,
output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt,
output reg oclk_prech_req,
output reg oclk_calib_resume,
output oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [16*DRAM_WIDTH-1:0] dbg_oclkdelay_rd_data
);
// Start with an initial delay of 0 on OCLKDELAY. This is required to
// detect two valid data edges when possible. Two edges cannot be
// detected if write DQ and DQS are exactly edge aligned at stage3 tap0.
localparam TAP_CNT = 0;
//(tCK <= 938) ? 13 :
//(tCK <= 1072) ? 14 :
//(tCK <= 1250) ? 15 :
//(tCK <= 1500) ? 16 : 17;
localparam WAIT_CNT = 15;
// Default set to TRUE because there can be a case where the ocal_rise_right_edge
// may not be detected if WRLVL stage2 tap value is large upto 63 and the initial
// DQS position is more than 225 degrees
localparam MINUS_32 = "TRUE";
localparam [4:0] OCAL_IDLE = 5'h00;
localparam [4:0] OCAL_NEW_DQS_WAIT = 5'h01;
localparam [4:0] OCAL_STG3_SEL = 5'h02;
localparam [4:0] OCAL_STG3_SEL_WAIT = 5'h03;
localparam [4:0] OCAL_STG3_EN_WAIT = 5'h04;
localparam [4:0] OCAL_STG3_DEC = 5'h05;
localparam [4:0] OCAL_STG3_WAIT = 5'h06;
localparam [4:0] OCAL_STG3_CALC = 5'h07;
localparam [4:0] OCAL_STG3_INC = 5'h08;
localparam [4:0] OCAL_STG3_INC_WAIT = 5'h09;
localparam [4:0] OCAL_STG2_SEL = 5'h0A;
localparam [4:0] OCAL_STG2_WAIT = 5'h0B;
localparam [4:0] OCAL_STG2_INC = 5'h0C;
localparam [4:0] OCAL_STG2_DEC = 5'h0D;
localparam [4:0] OCAL_STG2_DEC_WAIT = 5'h0E;
localparam [4:0] OCAL_NEXT_DQS = 5'h0F;
localparam [4:0] OCAL_NEW_DQS_READ = 5'h10;
localparam [4:0] OCAL_INC_DONE_WAIT = 5'h11;
localparam [4:0] OCAL_STG3_DEC_WAIT = 5'h12;
localparam [4:0] OCAL_DEC_DONE_WAIT = 5'h13;
localparam [4:0] OCAL_DONE = 5'h14;
integer i;
reg oclk_init_delay_start_r;
reg [3:0] count;
reg delay_done;
reg delay_done_r1;
reg delay_done_r2;
reg delay_done_r3;
reg delay_done_r4;
reg [5:0] delay_cnt_r;
reg po_stg3_dec;
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
reg [DQS_CNT_WIDTH:0] cnt_dqs_r;
reg [DQS_CNT_WIDTH:0] mux_sel_r;
reg [DRAM_WIDTH-1:0] sel_rd_rise0_r;
reg [DRAM_WIDTH-1:0] sel_rd_fall0_r;
reg [DRAM_WIDTH-1:0] sel_rd_rise1_r;
reg [DRAM_WIDTH-1:0] sel_rd_fall1_r;
reg [DRAM_WIDTH-1:0] sel_rd_rise2_r;
reg [DRAM_WIDTH-1:0] sel_rd_fall2_r;
reg [DRAM_WIDTH-1:0] sel_rd_rise3_r;
reg [DRAM_WIDTH-1:0] sel_rd_fall3_r;
reg [DRAM_WIDTH-1:0] prev_rd_rise0_r;
reg [DRAM_WIDTH-1:0] prev_rd_fall0_r;
reg [DRAM_WIDTH-1:0] prev_rd_rise1_r;
reg [DRAM_WIDTH-1:0] prev_rd_fall1_r;
reg [DRAM_WIDTH-1:0] prev_rd_rise2_r;
reg [DRAM_WIDTH-1:0] prev_rd_fall2_r;
reg [DRAM_WIDTH-1:0] prev_rd_rise3_r;
reg [DRAM_WIDTH-1:0] prev_rd_fall3_r;
reg rd_active_r;
reg rd_active_r1;
reg rd_active_r2;
reg rd_active_r3;
reg rd_active_r4;
reg [DRAM_WIDTH-1:0] pat_match_fall0_r;
reg pat_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall1_r;
reg pat_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall2_r;
reg pat_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall3_r;
reg pat_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise0_r;
reg pat_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise1_r;
reg pat_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise2_r;
reg pat_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise3_r;
reg pat_match_rise3_and_r;
reg pat_data_match_r;
reg pat_data_match_valid_r;
reg pat_data_match_valid_r1;
//reg [3:0] stable_stg3_cnt;
//reg stable_eye_r;
reg [3:0] stable_rise_stg3_cnt;
reg stable_rise_eye_r;
reg [3:0] stable_fall_stg3_cnt;
reg stable_fall_eye_r;
reg wait_cnt_en_r;
reg [3:0] wait_cnt_r;
reg cnt_next_state;
reg oclkdelay_calib_start_r;
reg [5:0] stg3_tap_cnt;
reg [5:0] stg3_incdec_limit;
reg stg3_dec2inc;
reg [5:0] stg2_tap_cnt;
reg [1:0] stg2_inc2_cnt;
reg [1:0] stg2_dec2_cnt;
reg [5:0] stg2_dec_cnt;
reg stg3_dec;
reg stg3_dec_r;
reg [4:0] ocal_state_r;
reg [4:0] ocal_state_r1;
reg [5:0] ocal_final_cnt_r;
reg ocal_final_cnt_r_calc;
reg [5:0] ocal_inc_cnt;
reg [5:0] ocal_dec_cnt;
reg ocal_stg3_inc_en;
reg ocal_rise_edge1_found;
reg ocal_rise_edge2_found;
reg ocal_rise_edge1_found_timing;
reg ocal_rise_edge2_found_timing;
reg [5:0] ocal_rise_edge1_taps;
reg [5:0] ocal_rise_edge2_taps;
reg [5:0] ocal_rise_right_edge;
reg ocal_fall_edge1_found;
reg ocal_fall_edge2_found;
reg [5:0] ocal_fall_edge1_taps;
reg [5:0] ocal_fall_edge2_taps;
reg [5:0] ocal_final_cnt_r_mux_a;
reg [5:0] ocal_final_cnt_r_mux_b;
reg [5:0] ocal_final_cnt_r_mux_c;
reg [5:0] ocal_final_cnt_r_mux_d;
reg ocal_byte_done;
reg ocal_wrlvl_done;
reg ocal_wrlvl_done_r;
(* keep = "true", max_fanout = 10 *) reg ocal_done_r /* synthesis syn_maxfan = 10 */;
reg [5:0] ocal_tap_cnt_r[0:DQS_WIDTH-1];
reg prech_done_r;
reg rise_win;
reg fall_win;
// timing registers
reg stg3_tap_cnt_eq_oclkdelay_init_val;
reg stg3_tap_cnt_eq_0;
//reg stg3_tap_cnt_gt_20;
reg stg3_tap_cnt_eq_63;
reg stg3_tap_cnt_less_oclkdelay_init_val;
reg stg3_limit;
wire [5:0] wl_po_fine_cnt_w[0:DQS_WIDTH-1];
//**************************************************************************
// Debug signals
//**************************************************************************
genvar dqs_i;
generate
for (dqs_i=0; dqs_i < DQS_WIDTH; dqs_i = dqs_i + 1) begin: oclkdelay_tap_cnt
assign dbg_phy_oclkdelay_cal[6*dqs_i+:6] = ocal_tap_cnt_r[dqs_i][5:0];
end
endgenerate
assign dbg_phy_oclkdelay_cal[57:54] = cnt_dqs_r;
assign dbg_phy_oclkdelay_cal[58] = ocal_rise_edge1_found_timing;
assign dbg_phy_oclkdelay_cal[59] = ocal_rise_edge2_found_timing;
assign dbg_phy_oclkdelay_cal[65:60] = ocal_rise_edge1_taps;
assign dbg_phy_oclkdelay_cal[71:66] = ocal_rise_edge2_taps;
assign dbg_phy_oclkdelay_cal[76:72] = ocal_state_r1;
assign dbg_phy_oclkdelay_cal[77] = pat_data_match_valid_r;
assign dbg_phy_oclkdelay_cal[78] = pat_data_match_r;
assign dbg_phy_oclkdelay_cal[84:79] = stg3_tap_cnt;
assign dbg_phy_oclkdelay_cal[88:85] = stable_rise_stg3_cnt;
assign dbg_phy_oclkdelay_cal[89] = stable_rise_eye_r;
assign dbg_phy_oclkdelay_cal[97:90] = prev_rd_rise0_r;
assign dbg_phy_oclkdelay_cal[105:98] = prev_rd_fall0_r;
assign dbg_phy_oclkdelay_cal[113:106] = prev_rd_rise1_r;
assign dbg_phy_oclkdelay_cal[121:114] = prev_rd_fall1_r;
assign dbg_phy_oclkdelay_cal[129:122] = prev_rd_rise2_r;
assign dbg_phy_oclkdelay_cal[137:130] = prev_rd_fall2_r;
assign dbg_phy_oclkdelay_cal[145:138] = prev_rd_rise3_r;
assign dbg_phy_oclkdelay_cal[153:146] = prev_rd_fall3_r;
assign dbg_phy_oclkdelay_cal[154] = rd_active_r;
assign dbg_phy_oclkdelay_cal[162:155] = sel_rd_rise0_r;
assign dbg_phy_oclkdelay_cal[170:163] = sel_rd_fall0_r;
assign dbg_phy_oclkdelay_cal[178:171] = sel_rd_rise1_r;
assign dbg_phy_oclkdelay_cal[186:179] = sel_rd_fall1_r;
assign dbg_phy_oclkdelay_cal[194:187] = sel_rd_rise2_r;
assign dbg_phy_oclkdelay_cal[202:195] = sel_rd_fall2_r;
assign dbg_phy_oclkdelay_cal[210:203] = sel_rd_rise3_r;
assign dbg_phy_oclkdelay_cal[218:211] = sel_rd_fall3_r;
assign dbg_phy_oclkdelay_cal[219+:6] = stg2_tap_cnt;
assign dbg_phy_oclkdelay_cal[225] = ocal_fall_edge1_found;
assign dbg_phy_oclkdelay_cal[226] = ocal_fall_edge2_found;
assign dbg_phy_oclkdelay_cal[232:227] = ocal_fall_edge1_taps;
assign dbg_phy_oclkdelay_cal[238:233] = ocal_fall_edge2_taps;
assign dbg_phy_oclkdelay_cal[244:239] = ocal_rise_right_edge;
assign dbg_phy_oclkdelay_cal[250:245] = 'd0;
assign dbg_phy_oclkdelay_cal[251] = stable_fall_eye_r;
assign dbg_phy_oclkdelay_cal[252] = rise_win;
assign dbg_phy_oclkdelay_cal[253] = fall_win;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*1 -1:0] = prev_rd_rise0_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*2 -1:DRAM_WIDTH*1] = prev_rd_fall0_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*3 -1:DRAM_WIDTH*2] = prev_rd_rise1_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*4 -1:DRAM_WIDTH*3] = prev_rd_fall1_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*5 -1:DRAM_WIDTH*4] = prev_rd_rise2_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*6 -1:DRAM_WIDTH*5] = prev_rd_fall2_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*7 -1:DRAM_WIDTH*6] = prev_rd_rise3_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*8 -1:DRAM_WIDTH*7] = prev_rd_fall3_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*9 -1:DRAM_WIDTH*8] = sel_rd_rise0_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*10 -1:DRAM_WIDTH*9] = sel_rd_fall0_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*11 -1:DRAM_WIDTH*10] = sel_rd_rise1_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*12 -1:DRAM_WIDTH*11] = sel_rd_fall1_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*13 -1:DRAM_WIDTH*12] = sel_rd_rise2_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*14 -1:DRAM_WIDTH*13] = sel_rd_fall2_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*15 -1:DRAM_WIDTH*14] = sel_rd_rise3_r;
assign dbg_oclkdelay_rd_data[DRAM_WIDTH*16 -1:DRAM_WIDTH*15] = sel_rd_fall3_r;
assign oclk_init_delay_done = ((SIM_CAL_OPTION == "FAST_CAL") || (DRAM_TYPE!="DDR3")) ? 1'b1 : delay_done_r4; //(SIM_CAL_OPTION != "NONE")
assign oclkdelay_calib_cnt = cnt_dqs_r;
assign oclkdelay_calib_done = (OCAL_EN == "ON") ? ocal_done_r : 1'b1;
always @(posedge clk)
oclk_init_delay_start_r <= #TCQ oclk_init_delay_start;
always @(posedge clk) begin
if (rst || po_stg3_dec)
count <= #TCQ WAIT_CNT;
else if (oclk_init_delay_start && (count > 'd0))
count <= #TCQ count - 1;
end
always @(posedge clk) begin
if (rst)
po_stg3_dec <= #TCQ 1'b0;
else if ((count == 'd1) && (delay_cnt_r != 'd0))
po_stg3_dec <= #TCQ 1'b1;
else
po_stg3_dec <= #TCQ 1'b0;
end
//po_stg3_incdec and po_en_stg3 asserted for all data byte lanes
always @(posedge clk) begin
if (rst) begin
po_stg3_incdec <= #TCQ 1'b0;
po_en_stg3 <= #TCQ 1'b0;
end else if (po_stg3_dec) begin
po_stg3_incdec <= #TCQ 1'b0;
po_en_stg3 <= #TCQ 1'b1;
end else begin
po_stg3_incdec <= #TCQ 1'b0;
po_en_stg3 <= #TCQ 1'b0;
end
end
// delay counter to count TAP_CNT cycles
always @(posedge clk) begin
// load delay counter with init value of TAP_CNT
if (rst)
delay_cnt_r <= #TCQ TAP_CNT;
else if (po_stg3_dec && (delay_cnt_r > 6'd0))
delay_cnt_r <= #TCQ delay_cnt_r - 1;
end
// when all the ctl_lanes have their output phase shifted by 1/4 cycle, delay shifting is done.
always @(posedge clk) begin
if (rst) begin
delay_done <= #TCQ 1'b0;
end else if ((TAP_CNT == 6'd0) || ((delay_cnt_r == 6'd1) &&
(count == 'd1))) begin
delay_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
delay_done_r1 <= #TCQ delay_done;
delay_done_r2 <= #TCQ delay_done_r1;
delay_done_r3 <= #TCQ delay_done_r2;
delay_done_r4 <= #TCQ delay_done_r3;
end
//**************************************************************************
// OCLKDELAY Calibration
//**************************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_rd_data_div4
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
end
endgenerate
always @(posedge clk) begin
mux_sel_r <= #TCQ cnt_dqs_r;
oclkdelay_calib_start_r <= #TCQ oclkdelay_calib_start;
ocal_wrlvl_done_r <= #TCQ ocal_wrlvl_done;
rd_active_r <= #TCQ phy_rddata_en;
rd_active_r1 <= #TCQ rd_active_r;
rd_active_r2 <= #TCQ rd_active_r1;
rd_active_r3 <= #TCQ rd_active_r2;
rd_active_r4 <= #TCQ rd_active_r3;
stg3_dec_r <= #TCQ stg3_dec;
ocal_state_r1 <= #TCQ ocal_state_r;
end
// Register outputs for improved timing.
// All bits in selected DQS group are checked in aggregate
generate
genvar mux_j;
for (mux_j = 0; mux_j < DRAM_WIDTH; mux_j = mux_j + 1) begin: gen_mux_rd
always @(posedge clk) begin
if (phy_rddata_en) begin
sel_rd_rise0_r[mux_j] <= #TCQ rd_data_rise0[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_fall0_r[mux_j] <= #TCQ rd_data_fall0[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_rise1_r[mux_j] <= #TCQ rd_data_rise1[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_fall1_r[mux_j] <= #TCQ rd_data_fall1[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_rise2_r[mux_j] <= #TCQ rd_data_rise2[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_fall2_r[mux_j] <= #TCQ rd_data_fall2[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_rise3_r[mux_j] <= #TCQ rd_data_rise3[DRAM_WIDTH*mux_sel_r + mux_j];
sel_rd_fall3_r[mux_j] <= #TCQ rd_data_fall3[DRAM_WIDTH*mux_sel_r + mux_j];
end
end
end
endgenerate
always @(posedge clk)
if (((stg3_tap_cnt_eq_oclkdelay_init_val) && rd_active_r) |
rd_active_r4) begin
prev_rd_rise0_r <= #TCQ sel_rd_rise0_r;
prev_rd_fall0_r <= #TCQ sel_rd_fall0_r;
prev_rd_rise1_r <= #TCQ sel_rd_rise1_r;
prev_rd_fall1_r <= #TCQ sel_rd_fall1_r;
prev_rd_rise2_r <= #TCQ sel_rd_rise2_r;
prev_rd_fall2_r <= #TCQ sel_rd_fall2_r;
prev_rd_rise3_r <= #TCQ sel_rd_rise3_r;
prev_rd_fall3_r <= #TCQ sel_rd_fall3_r;
end
// Each bit of each byte is compared with previous data to
// detect an edge
generate
genvar pt_j;
if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
always @(posedge clk) begin
if (rd_active_r) begin
rise_win <= #TCQ ((|sel_rd_rise0_r) | (|sel_rd_rise1_r) | (|sel_rd_rise2_r) | (|sel_rd_rise3_r));
fall_win <= #TCQ ((&sel_rd_rise0_r) & (&sel_rd_rise1_r) & (&sel_rd_rise2_r) & (&sel_rd_rise3_r));
end
end
for (pt_j = 0; pt_j < DRAM_WIDTH; pt_j = pt_j + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sel_rd_rise0_r[pt_j] == prev_rd_rise0_r[pt_j])
pat_match_rise0_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall0_r[pt_j] == prev_rd_fall0_r[pt_j])
pat_match_fall0_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_rise1_r[pt_j] == prev_rd_rise1_r[pt_j])
pat_match_rise1_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall1_r[pt_j] == prev_rd_fall1_r[pt_j])
pat_match_fall1_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_rise2_r[pt_j] == prev_rd_rise2_r[pt_j])
pat_match_rise2_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise2_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall2_r[pt_j] == prev_rd_fall2_r[pt_j])
pat_match_fall2_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall2_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_rise3_r[pt_j] == prev_rd_rise3_r[pt_j])
pat_match_rise3_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise3_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall3_r[pt_j] == prev_rd_fall3_r[pt_j])
pat_match_fall3_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall3_r[pt_j] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r;
pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r;
pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r;
pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r;
pat_data_match_r <= #TCQ (//pat_match_rise0_and_r &&
//pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r &&
pat_match_rise2_and_r &&
pat_match_fall2_and_r &&
pat_match_rise3_and_r &&
pat_match_fall3_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r2;
end
always @(posedge clk)
pat_data_match_valid_r1 <= #TCQ pat_data_match_valid_r;
end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
always @(posedge clk) begin
if (rd_active_r) begin
rise_win <= #TCQ ((|sel_rd_rise0_r) | (|sel_rd_rise1_r));
fall_win <= #TCQ ((&sel_rd_rise0_r) & (&sel_rd_rise1_r));
end
end
for (pt_j = 0; pt_j < DRAM_WIDTH; pt_j = pt_j + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sel_rd_rise0_r[pt_j] == prev_rd_rise0_r[pt_j])
pat_match_rise0_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall0_r[pt_j] == prev_rd_fall0_r[pt_j])
pat_match_fall0_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_rise1_r[pt_j] == prev_rd_rise1_r[pt_j])
pat_match_rise1_r[pt_j] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_j] <= #TCQ 1'b0;
if (sel_rd_fall1_r[pt_j] == prev_rd_fall1_r[pt_j])
pat_match_fall1_r[pt_j] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_j] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_data_match_r <= #TCQ (//pat_match_rise0_and_r &&
//pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r2;
end
always @(posedge clk)
pat_data_match_valid_r1 <= #TCQ pat_data_match_valid_r;
end
endgenerate
// Stable count of 16 PO Stage3 taps at 2x the resolution of stage2 taps
// Required to inhibit false edge detection due to clock jitter
always @(posedge clk)begin
if (rst | (pat_data_match_valid_r & ~pat_data_match_r &
(ocal_state_r == OCAL_NEW_DQS_WAIT)) |
(ocal_state_r == OCAL_STG3_CALC))
stable_rise_stg3_cnt <= #TCQ 'd0;
else if ((!stg3_tap_cnt_eq_oclkdelay_init_val) &
pat_data_match_valid_r & pat_data_match_r &
(ocal_state_r == OCAL_NEW_DQS_WAIT) &
(stable_rise_stg3_cnt < 'd8) & ~rise_win)
stable_rise_stg3_cnt <= #TCQ stable_rise_stg3_cnt + 1;
end
always @(posedge clk) begin
if (rst | (stable_rise_stg3_cnt != 'd8))
stable_rise_eye_r <= #TCQ 1'b0;
else if (stable_rise_stg3_cnt == 'd8)
stable_rise_eye_r <= #TCQ 1'b1;
end
always @(posedge clk)begin
if (rst | (pat_data_match_valid_r & ~pat_data_match_r &
(ocal_state_r == OCAL_NEW_DQS_WAIT)) |
(ocal_state_r == OCAL_STG3_CALC))
stable_fall_stg3_cnt <= #TCQ 'd0;
else if ((!stg3_tap_cnt_eq_oclkdelay_init_val) &
pat_data_match_valid_r & pat_data_match_r &
(ocal_state_r == OCAL_NEW_DQS_WAIT) &
(stable_fall_stg3_cnt < 'd8) & fall_win)
stable_fall_stg3_cnt <= #TCQ stable_fall_stg3_cnt + 1;
end
always @(posedge clk) begin
if (rst | (stable_fall_stg3_cnt != 'd8))
stable_fall_eye_r <= #TCQ 1'b0;
else if (stable_fall_stg3_cnt == 'd8)
stable_fall_eye_r <= #TCQ 1'b1;
end
always @(posedge clk)
if ((ocal_state_r == OCAL_STG3_SEL_WAIT) ||
(ocal_state_r == OCAL_STG3_EN_WAIT) ||
(ocal_state_r == OCAL_STG3_WAIT) ||
(ocal_state_r == OCAL_STG3_INC_WAIT) ||
(ocal_state_r == OCAL_STG3_DEC_WAIT) ||
(ocal_state_r == OCAL_STG2_WAIT) ||
(ocal_state_r == OCAL_STG2_DEC_WAIT) ||
(ocal_state_r == OCAL_INC_DONE_WAIT) ||
(ocal_state_r == OCAL_DEC_DONE_WAIT))
wait_cnt_en_r <= #TCQ 1'b1;
else
wait_cnt_en_r <= #TCQ 1'b0;
always @(posedge clk)
if (!wait_cnt_en_r) begin
wait_cnt_r <= #TCQ 'b0;
cnt_next_state <= #TCQ 1'b0;
end else begin
if (wait_cnt_r != WAIT_CNT - 1) begin
wait_cnt_r <= #TCQ wait_cnt_r + 1;
cnt_next_state <= #TCQ 1'b0;
end else begin
// Need to reset to 0 to handle the case when there are two
// different WAIT states back-to-back
wait_cnt_r <= #TCQ 'b0;
cnt_next_state <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
for (i=0; i < DQS_WIDTH; i = i + 1) begin: rst_ocal_tap_cnt
ocal_tap_cnt_r[i] <= #TCQ 'b0;
end
end else if (stg3_dec_r && ~stg3_dec)
ocal_tap_cnt_r[cnt_dqs_r][5:0] <= #TCQ stg3_tap_cnt;
end
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEW_DQS_READ) ||
(ocal_state_r == OCAL_STG3_CALC) ||
(ocal_state_r == OCAL_DONE))
prech_done_r <= #TCQ 1'b0;
else if (prech_done)
prech_done_r <= #TCQ 1'b1;
end
// setting stg3_tap_cnt == oclkdelay_int_val
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS)) begin
stg3_tap_cnt_eq_oclkdelay_init_val <= #TCQ 1'b1;
end else begin
if (ocal_state_r == OCAL_DONE)
stg3_tap_cnt_eq_oclkdelay_init_val <= #TCQ 1'b0;
else if (ocal_state_r == OCAL_STG3_DEC)
stg3_tap_cnt_eq_oclkdelay_init_val <= #TCQ (stg3_tap_cnt == oclkdelay_init_val+1);
else if (ocal_state_r == OCAL_STG3_INC)
stg3_tap_cnt_eq_oclkdelay_init_val <= #TCQ (stg3_tap_cnt == oclkdelay_init_val-1);
end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
end // always @ (posedge clk)
// setting sg3_tap_cng > 20
// always @(posedge clk) begin
// if ((rst)|| (ocal_state_r == OCAL_NEXT_DQS)) begin
// stg3_tap_cnt_gt_20 <= #TCQ 1'b0;
// end else begin // if (rst)
// if (ocal_state_r == OCAL_STG3_DEC)
// stg3_tap_cnt_gt_20 <= #TCQ (stg3_tap_cnt >= 'd22);
// else if (ocal_state_r == OCAL_STG3_INC)
// stg3_tap_cnt_gt_20 <= #TCQ (stg3_tap_cnt >= 'd20);
// end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
// end // always @ (posedge clk)
// setting sg3_tap_cnt == 0
always @(posedge clk) begin
if ((rst)|| (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_STG3_INC) ) begin
stg3_tap_cnt_eq_0 <= #TCQ 1'b0;
end else begin // if (rst)
if (ocal_state_r == OCAL_STG3_DEC)
stg3_tap_cnt_eq_0 <= #TCQ (stg3_tap_cnt == 'd1);
end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
end // always @ (posedge clk)
// setting sg3_tap_cnt == 63
always @(posedge clk) begin
if ((rst)|| (ocal_state_r == OCAL_NEXT_DQS)) begin
stg3_tap_cnt_eq_63 <= #TCQ 1'b0;
end else begin // if (rst)
if (ocal_state_r == OCAL_STG3_INC)
stg3_tap_cnt_eq_63 <= #TCQ (stg3_tap_cnt >= 'd62);
else if (ocal_state_r == OCAL_STG3_DEC)
stg3_tap_cnt_eq_63 <= #TCQ 1'b0;
end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
end // always @ (posedge clk)
// setting sg3_tap_cnt < ocaldelay_init_val
always @(posedge clk) begin
if ((rst)|| (ocal_state_r == OCAL_NEXT_DQS)) begin
stg3_tap_cnt_less_oclkdelay_init_val <= #TCQ 1'b0;
end else begin // if (rst)
if (ocal_state_r == OCAL_STG3_DEC)
stg3_tap_cnt_less_oclkdelay_init_val <= #TCQ (stg3_tap_cnt <= oclkdelay_init_val);
else if (ocal_state_r == OCAL_STG3_INC)
stg3_tap_cnt_less_oclkdelay_init_val <= #TCQ (stg3_tap_cnt <= oclkdelay_init_val-2);
end // else: !if((rst || (ocal_state_r == OCAL_IDLE)) begin...
end // always @ (posedge clk)
// setting stg3_incdec_limit == 15
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_DONE)) begin
stg3_limit <= #TCQ 1'b0;
end else if ((ocal_state_r == OCAL_STG3_WAIT) || (ocal_state_r == OCAL_STG2_WAIT)) begin
stg3_limit <= #TCQ (stg3_incdec_limit == 'd14);
end
end
// Registers feeding into the ocal_final_cnt_r computation
// Equation is in the form of ((A-B)/2) + C + D where the values taken are
// A = ocal_fall_edge_taps, ocal_rise_right_edge, stg3_tap_cnt or ocal_fall_edge2_taps
// B = ocal_fall_edge1_taps, ocal_rise_edge1_taps or '0'
// C = (stg3_tap_cnt - ocal_rise_right_edge), '0' or '1'
// D = '32' or '0'
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_DONE))
ocal_final_cnt_r_mux_a <= #TCQ 'd0;
else if (|ocal_rise_right_edge) begin
if (ocal_fall_edge2_found && ocal_fall_edge1_found)
ocal_final_cnt_r_mux_a <= #TCQ ocal_fall_edge2_taps;
else
ocal_final_cnt_r_mux_a <= #TCQ ocal_rise_right_edge;
end else if (ocal_rise_edge2_found)
ocal_final_cnt_r_mux_a <= #TCQ ocal_rise_edge2_taps;
else if (~ocal_rise_edge2_found && ocal_rise_edge1_found)
ocal_final_cnt_r_mux_a <= #TCQ stg3_tap_cnt;
else if (ocal_fall_edge2_found && ocal_fall_edge1_found)
ocal_final_cnt_r_mux_a <= #TCQ ocal_fall_edge2_taps;
end
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_DONE))
ocal_final_cnt_r_mux_b <= #TCQ 'd0;
else if (|ocal_rise_right_edge) begin
if (ocal_fall_edge2_found && ocal_fall_edge1_found)
ocal_final_cnt_r_mux_b <= #TCQ ocal_fall_edge1_taps;
else
ocal_final_cnt_r_mux_b <= #TCQ ocal_rise_edge1_taps;
end else if (ocal_rise_edge2_found && ocal_rise_edge1_found)
ocal_final_cnt_r_mux_b <= #TCQ ocal_rise_edge1_taps;
else if (ocal_rise_edge2_found && ~ocal_rise_edge1_found)
ocal_final_cnt_r_mux_b <= #TCQ 'd0;
else if (~ocal_rise_edge2_found && ocal_rise_edge1_found)
ocal_final_cnt_r_mux_b <= #TCQ ocal_rise_edge1_taps;
else if (ocal_fall_edge2_found && ocal_fall_edge1_found)
ocal_final_cnt_r_mux_b <= #TCQ ocal_fall_edge1_taps;
end
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_DONE))
ocal_final_cnt_r_mux_c <= #TCQ 'd0;
else if (|ocal_rise_right_edge) begin
if (ocal_fall_edge2_found && ocal_fall_edge1_found)
ocal_final_cnt_r_mux_c <= #TCQ 'd1;
else
ocal_final_cnt_r_mux_c <= #TCQ (stg3_tap_cnt - ocal_rise_right_edge);
end else if (~ocal_rise_edge2_found && ocal_rise_edge1_found)
ocal_final_cnt_r_mux_c <= #TCQ 'd0;
else
ocal_final_cnt_r_mux_c <= #TCQ 'd1;
end
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_DONE))
ocal_final_cnt_r_mux_d <= #TCQ 'd0;
else if (((|ocal_rise_right_edge) &&
(ocal_fall_edge2_found && ocal_fall_edge1_found)) ||
(ocal_fall_edge2_found && ocal_fall_edge1_found))
ocal_final_cnt_r_mux_d <= #TCQ 'd32;
else
ocal_final_cnt_r_mux_d <= #TCQ 'd0;
end
always @(posedge clk) begin
if (rst || (ocal_state_r == OCAL_NEXT_DQS) || (ocal_state_r == OCAL_DONE))
ocal_final_cnt_r <= #TCQ 'd0;
else if (ocal_state_r == OCAL_STG3_CALC)
ocal_final_cnt_r <= #TCQ ((ocal_final_cnt_r_mux_a - ocal_final_cnt_r_mux_b)>>1) +
ocal_final_cnt_r_mux_c + ocal_final_cnt_r_mux_d;
end
genvar dqs_q;
generate
for (dqs_q=0; dqs_q < DQS_WIDTH; dqs_q = dqs_q + 1) begin: tap_cnt_split
assign wl_po_fine_cnt_w[dqs_q] = wl_po_fine_cnt[6*dqs_q+:6];
end
endgenerate
// State Machine
always @(posedge clk) begin
if (rst) begin
ocal_state_r <= #TCQ OCAL_IDLE;
cnt_dqs_r <= #TCQ 'd0;
stg3_tap_cnt <= #TCQ oclkdelay_init_val;
stg3_incdec_limit <= #TCQ 'd0;
stg3_dec2inc <= #TCQ 1'b0;
stg2_tap_cnt <= #TCQ 'd0;
stg2_inc2_cnt <= #TCQ 2'b00;
stg2_dec2_cnt <= #TCQ 2'b00;
stg2_dec_cnt <= #TCQ 'd0;
stg3_dec <= #TCQ 1'b0;
wrlvl_final <= #TCQ 1'b0;
oclk_calib_resume <= #TCQ 1'b0;
oclk_prech_req <= #TCQ 1'b0;
ocal_inc_cnt <= #TCQ 'd0;
ocal_dec_cnt <= #TCQ 'd0;
ocal_stg3_inc_en <= #TCQ 1'b0;
ocal_rise_edge1_found <= #TCQ 1'b0;
ocal_rise_edge2_found <= #TCQ 1'b0;
ocal_rise_edge1_found_timing <= #TCQ 1'b0;
ocal_rise_edge2_found_timing <= #TCQ 1'b0;
ocal_rise_right_edge <= #TCQ 'd0;
ocal_rise_edge1_taps <= #TCQ 'd0;
ocal_rise_edge2_taps <= #TCQ 'd0;
ocal_fall_edge1_found <= #TCQ 1'b0;
ocal_fall_edge2_found <= #TCQ 1'b0;
ocal_fall_edge1_taps <= #TCQ 'd0;
ocal_fall_edge2_taps <= #TCQ 'd0;
ocal_byte_done <= #TCQ 1'b0;
ocal_wrlvl_done <= #TCQ 1'b0;
ocal_done_r <= #TCQ 1'b0;
po_stg23_sel <= #TCQ 1'b0;
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
ocal_final_cnt_r_calc <= #TCQ 1'b0;
end else begin
case (ocal_state_r)
OCAL_IDLE: begin
if (oclkdelay_calib_start && ~oclkdelay_calib_start_r) begin
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
stg3_tap_cnt <= #TCQ oclkdelay_init_val;
stg2_tap_cnt <= #TCQ wl_po_fine_cnt_w[cnt_dqs_r];
end
end
OCAL_NEW_DQS_READ: begin
oclk_prech_req <= #TCQ 1'b0;
oclk_calib_resume <= #TCQ 1'b0;
if (pat_data_match_valid_r)
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
end
OCAL_NEW_DQS_WAIT: begin
oclk_calib_resume <= #TCQ 1'b0;
oclk_prech_req <= #TCQ 1'b0;
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
if (pat_data_match_valid_r && !stg3_tap_cnt_eq_oclkdelay_init_val) begin
if ((stg3_limit && ~ocal_stg3_inc_en) ||
stg3_tap_cnt == 'd0) begin
// No write levling performed to avoid stage 2 coarse dec.
// Therefore stage 3 taps can only be decremented by an
// additional 15 taps after stage 2 taps reach 63.
ocal_state_r <= #TCQ OCAL_STG3_SEL;
ocal_stg3_inc_en <= #TCQ 1'b1;
stg3_incdec_limit <= #TCQ 'd0;
// An edge was detected
end else if (~pat_data_match_r) begin
// Sticky bit - asserted after we encounter an edge, although
// the current edge may not be considered the "first edge" this
// just means we found at least one edge
if (~ocal_stg3_inc_en) begin
if (|stable_fall_stg3_cnt && ~ocal_fall_edge1_found) begin
ocal_fall_edge1_found <= #TCQ 1'b1;
ocal_fall_edge1_taps <= #TCQ stg3_tap_cnt + 1;
end else begin
ocal_rise_edge1_found <= #TCQ 1'b1;
ocal_rise_edge1_found_timing <= #TCQ 1'b1;
end
end
// Sarting point was in the jitter region close to the right edge
if (~stable_rise_eye_r && ~ocal_stg3_inc_en) begin
ocal_rise_right_edge <= #TCQ stg3_tap_cnt;
ocal_state_r <= #TCQ OCAL_STG3_SEL;
// Starting point was in the valid window close to the right edge
// Or away from the right edge hence no stable_eye_r condition
// Or starting point was in the right jitter region and ocal_rise_right_edge
// is detected
end else if (ocal_stg3_inc_en) begin
// Both edges found
if (stable_fall_eye_r) begin
ocal_state_r <= #TCQ OCAL_STG3_CALC;
ocal_fall_edge2_found <= #TCQ 1'b1;
ocal_fall_edge2_taps <= #TCQ stg3_tap_cnt - 1;
end else begin
ocal_state_r <= #TCQ OCAL_STG3_CALC;
ocal_rise_edge2_found <= #TCQ 1'b1;
ocal_rise_edge2_found_timing <= #TCQ 1'b1;
ocal_rise_edge2_taps <= #TCQ stg3_tap_cnt - 1;
end
// Starting point in the valid window away from left edge
// Assuming starting point will not be in valid window close to
// left edge
end else if (stable_rise_eye_r) begin
ocal_rise_edge1_taps <= #TCQ stg3_tap_cnt + 1;
ocal_state_r <= #TCQ OCAL_STG3_SEL;
ocal_stg3_inc_en <= #TCQ 1'b1;
stg3_incdec_limit <= #TCQ 'd0;
end else
ocal_state_r <= #TCQ OCAL_STG3_SEL;
end else
ocal_state_r <= #TCQ OCAL_STG3_SEL;
end else if (stg3_tap_cnt_eq_oclkdelay_init_val)
ocal_state_r <= #TCQ OCAL_STG3_SEL;
else if ((stg3_limit && ocal_stg3_inc_en) ||
(stg3_tap_cnt_eq_63)) begin
ocal_state_r <= #TCQ OCAL_STG3_CALC;
stg3_incdec_limit <= #TCQ 'd0;
end
end
OCAL_STG3_SEL: begin
po_stg23_sel <= #TCQ 1'b1;
ocal_wrlvl_done <= #TCQ 1'b0;
ocal_state_r <= #TCQ OCAL_STG3_SEL_WAIT;
ocal_final_cnt_r_calc <= #TCQ 1'b0;
end
OCAL_STG3_SEL_WAIT: begin
if (cnt_next_state) begin
ocal_state_r <= #TCQ OCAL_STG3_EN_WAIT;
if (ocal_stg3_inc_en) begin
po_stg23_incdec <= #TCQ 1'b1;
if (stg3_tap_cnt_less_oclkdelay_init_val) begin
ocal_inc_cnt <= #TCQ oclkdelay_init_val - stg3_tap_cnt;
stg3_dec2inc <= #TCQ 1'b1;
oclk_prech_req <= #TCQ 1'b1;
end
end else begin
po_stg23_incdec <= #TCQ 1'b0;
if (stg3_dec)
ocal_dec_cnt <= #TCQ ocal_final_cnt_r;
end
end
end
OCAL_STG3_EN_WAIT: begin
if (cnt_next_state) begin
if (ocal_stg3_inc_en)
ocal_state_r <= #TCQ OCAL_STG3_INC;
else
ocal_state_r <= #TCQ OCAL_STG3_DEC;
end
end
OCAL_STG3_DEC: begin
po_en_stg23 <= #TCQ 1'b1;
stg3_tap_cnt <= #TCQ stg3_tap_cnt - 1;
if (ocal_dec_cnt == 1) begin
ocal_byte_done <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_DEC_DONE_WAIT;
ocal_dec_cnt <= #TCQ ocal_dec_cnt - 1;
end else if (ocal_dec_cnt > 'd0) begin
ocal_state_r <= #TCQ OCAL_STG3_DEC_WAIT;
ocal_dec_cnt <= #TCQ ocal_dec_cnt - 1;
end else
ocal_state_r <= #TCQ OCAL_STG3_WAIT;
end
OCAL_STG3_DEC_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
if (cnt_next_state) begin
if (ocal_dec_cnt > 'd0)
ocal_state_r <= #TCQ OCAL_STG3_DEC;
else
ocal_state_r <= #TCQ OCAL_DEC_DONE_WAIT;
end
end
OCAL_DEC_DONE_WAIT: begin
// Required to make sure that po_stg23_incdec
// de-asserts some time after de-assertion of
// po_en_stg23
po_en_stg23 <= #TCQ 1'b0;
if (cnt_next_state) begin
// Final stage 3 decrement completed, proceed
// to stage 2 tap decrement
ocal_state_r <= #TCQ OCAL_STG2_SEL;
po_stg23_incdec <= #TCQ 1'b0;
stg3_dec <= #TCQ 1'b0;
end
end
OCAL_STG3_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
if (cnt_next_state) begin
po_stg23_incdec <= #TCQ 1'b0;
if ((stg2_tap_cnt != 6'd63) || (stg2_tap_cnt != 6'd0))
ocal_state_r <= #TCQ OCAL_STG2_SEL;
else begin
oclk_calib_resume <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
stg3_incdec_limit <= #TCQ stg3_incdec_limit + 1;
end
end
end
OCAL_STG2_SEL: begin
po_stg23_sel <= #TCQ 1'b0;
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
stg2_inc2_cnt <= #TCQ 2'b01;
stg2_dec2_cnt <= #TCQ 2'b01;
end
OCAL_STG2_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
if (cnt_next_state) begin
if (ocal_byte_done) begin
if (stg2_tap_cnt > 'd0) begin
// Decrement stage 2 taps to '0' before
// final write level is performed
ocal_state_r <= #TCQ OCAL_STG2_DEC;
stg2_dec_cnt <= #TCQ stg2_tap_cnt;
end else begin
ocal_state_r <= #TCQ OCAL_NEXT_DQS;
ocal_byte_done <= #TCQ 1'b0;
end
end else if (stg3_dec2inc && (stg2_tap_cnt > 'd0)) begin
// Decrement stage 2 tap to initial value before
// edge 2 detection begins
ocal_state_r <= #TCQ OCAL_STG2_DEC;
stg2_dec_cnt <= #TCQ stg2_tap_cnt - wl_po_fine_cnt_w[cnt_dqs_r];
end else if (~ocal_stg3_inc_en && (stg2_tap_cnt < 6'd63)) begin
// Increment stage 2 taps by 2 for every stage 3 tap decrement
// as part of edge 1 detection to avoid tDQSS violation between
// write DQS and CK
ocal_state_r <= #TCQ OCAL_STG2_INC;
end else if (ocal_stg3_inc_en && (stg2_tap_cnt > 6'd0)) begin
// Decrement stage 2 taps by 2 for every stage 3 tap increment
// as part of edge 2 detection to avoid tDQSS violation between
// write DQS and CK
ocal_state_r <= #TCQ OCAL_STG2_DEC;
end else begin
oclk_calib_resume <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
stg3_incdec_limit <= #TCQ stg3_incdec_limit + 1;
end
end
end
OCAL_STG2_INC: begin
po_en_stg23 <= #TCQ 1'b1;
po_stg23_incdec <= #TCQ 1'b1;
stg2_tap_cnt <= #TCQ stg2_tap_cnt + 1;
if (stg2_inc2_cnt > 2'b00) begin
stg2_inc2_cnt <= stg2_inc2_cnt - 1;
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
end else if (stg2_tap_cnt == 6'd62) begin
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
end else begin
oclk_calib_resume <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
end
end
OCAL_STG2_DEC: begin
po_en_stg23 <= #TCQ 1'b1;
po_stg23_incdec <= #TCQ 1'b0;
stg2_tap_cnt <= #TCQ stg2_tap_cnt - 1;
if (stg2_dec_cnt > 6'd0) begin
stg2_dec_cnt <= #TCQ stg2_dec_cnt - 1;
ocal_state_r <= #TCQ OCAL_STG2_DEC_WAIT;
end else if (stg2_dec2_cnt > 2'b00) begin
stg2_dec2_cnt <= stg2_dec2_cnt - 1;
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
end else if (stg2_tap_cnt == 6'd1)
ocal_state_r <= #TCQ OCAL_STG2_WAIT;
else begin
oclk_calib_resume <= #TCQ 1'b1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_WAIT;
end
end
OCAL_STG2_DEC_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
if (cnt_next_state) begin
if (stg2_dec_cnt > 6'd0) begin
ocal_state_r <= #TCQ OCAL_STG2_DEC;
end else if (ocal_byte_done) begin
ocal_state_r <= #TCQ OCAL_NEXT_DQS;
ocal_byte_done <= #TCQ 1'b0;
end else if (prech_done_r && stg3_dec2inc) begin
stg3_dec2inc <= #TCQ 1'b0;
if (stg3_tap_cnt_eq_63)
ocal_state_r <= #TCQ OCAL_STG3_CALC;
else begin
ocal_state_r <= #TCQ OCAL_NEW_DQS_READ;
oclk_calib_resume <= #TCQ 1'b1;
end
end
end
end
OCAL_STG3_CALC: begin
if (ocal_final_cnt_r_calc) begin
ocal_state_r <= #TCQ OCAL_STG3_SEL;
stg3_dec <= #TCQ 1'b1;
ocal_stg3_inc_en <= #TCQ 1'b0;
end else
ocal_final_cnt_r_calc <= #TCQ 1'b1;
end
OCAL_STG3_INC: begin
po_en_stg23 <= #TCQ 1'b1;
stg3_tap_cnt <= #TCQ stg3_tap_cnt + 1;
if (ocal_inc_cnt > 'd0)
ocal_inc_cnt <= #TCQ ocal_inc_cnt - 1;
if (ocal_inc_cnt == 1)
ocal_state_r <= #TCQ OCAL_INC_DONE_WAIT;
else
ocal_state_r <= #TCQ OCAL_STG3_INC_WAIT;
end
OCAL_STG3_INC_WAIT: begin
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b1;
if (cnt_next_state) begin
if (ocal_inc_cnt > 'd0)
ocal_state_r <= #TCQ OCAL_STG3_INC;
else begin
ocal_state_r <= #TCQ OCAL_STG2_SEL;
po_stg23_incdec <= #TCQ 1'b0;
end
end
end
OCAL_INC_DONE_WAIT: begin
// Required to make sure that po_stg23_incdec
// de-asserts some time after de-assertion of
// po_en_stg23
po_en_stg23 <= #TCQ 1'b0;
oclk_prech_req <= #TCQ 1'b0;
if (cnt_next_state) begin
ocal_state_r <= #TCQ OCAL_STG2_SEL;
po_stg23_incdec <= #TCQ 1'b0;
end
end
OCAL_NEXT_DQS: begin
ocal_final_cnt_r_calc <= #TCQ 1'b0;
po_en_stg23 <= #TCQ 1'b0;
po_stg23_incdec <= #TCQ 1'b0;
stg3_tap_cnt <= #TCQ 6'd0;
ocal_rise_edge1_found <= #TCQ 1'b0;
ocal_rise_edge2_found <= #TCQ 1'b0;
ocal_rise_edge1_found_timing <= #TCQ 1'b0;
ocal_rise_edge2_found_timing <= #TCQ 1'b0;
ocal_rise_edge1_taps <= #TCQ 'd0;
ocal_rise_edge2_taps <= #TCQ 'd0;
ocal_rise_right_edge <= #TCQ 'd0;
ocal_fall_edge1_found <= #TCQ 1'b0;
ocal_fall_edge2_found <= #TCQ 1'b0;
ocal_fall_edge1_taps <= #TCQ 'd0;
ocal_fall_edge2_taps <= #TCQ 'd0;
stg3_incdec_limit <= #TCQ 'd0;
oclk_prech_req <= #TCQ 1'b1;
if (cnt_dqs_r == DQS_WIDTH-1)
wrlvl_final <= #TCQ 1'b1;
if (prech_done) begin
if (cnt_dqs_r == DQS_WIDTH-1)
// If the last DQS group was just finished,
// then end of calibration
ocal_state_r <= #TCQ OCAL_DONE;
else begin
// Continue to next DQS group
cnt_dqs_r <= #TCQ cnt_dqs_r + 1;
ocal_state_r <= #TCQ OCAL_NEW_DQS_READ;
stg3_tap_cnt <= #TCQ oclkdelay_init_val;
stg2_tap_cnt <= #TCQ wl_po_fine_cnt_w[cnt_dqs_r + 1'b1];
end
end
end
OCAL_DONE: begin
ocal_final_cnt_r_calc <= #TCQ 1'b0;
oclk_prech_req <= #TCQ 1'b0;
po_stg23_sel <= #TCQ 1'b0;
ocal_done_r <= #TCQ 1'b1;
end
endcase
end
end
endmodule
|
(** * Smallstep: Small-step Operational Semantics *)
Require Export Imp.
(** The evaluators we have seen so far (e.g., the ones for
[aexp]s, [bexp]s, and commands) have been formulated in a
"big-step" style -- they specify how a given expression can be
evaluated to its final value (or a command plus a store to a final
store) "all in one big step."
This style is simple and natural for many purposes -- indeed,
Gilles Kahn, who popularized its use, called it _natural
semantics_. But there are some things it does not do well. In
particular, it does not give us a natural way of talking about
_concurrent_ programming languages, where the "semantics" of a
program -- i.e., the essence of how it behaves -- is not just
which input states get mapped to which output states, but also
includes the intermediate states that it passes through along the
way, since these states can also be observed by concurrently
executing code.
Another shortcoming of the big-step style is more technical, but
critical in some situations. To see the issue, suppose we wanted
to define a variant of Imp where variables could hold _either_
numbers _or_ lists of numbers (see the [HoareList] chapter for
details). In the syntax of this extended language, it will be
possible to write strange expressions like [2 + nil], and our
semantics for arithmetic expressions will then need to say
something about how such expressions behave. One
possibility (explored in the [HoareList] chapter) is to maintain
the convention that every arithmetic expressions evaluates to some
number by choosing some way of viewing a list as a number -- e.g.,
by specifying that a list should be interpreted as [0] when it
occurs in a context expecting a number. But this is really a bit
of a hack.
A much more natural approach is simply to say that the behavior of
an expression like [2+nil] is _undefined_ -- it doesn't evaluate
to any result at all. And we can easily do this: we just have to
formulate [aeval] and [beval] as [Inductive] propositions rather
than Fixpoints, so that we can make them partial functions instead
of total ones.
However, now we encounter a serious deficiency. In this language,
a command might _fail_ to map a given starting state to any ending
state for two quite different reasons: either because the
execution gets into an infinite loop or because, at some point,
the program tries to do an operation that makes no sense, such as
adding a number to a list, and none of the evaluation rules can be
applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- are quite different. In particular, we
want to allow the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but prevent the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a
different way of presenting the semantics that allows us to
distinguish nontermination from erroneous "stuck states."
So, for lots of reasons, we'd like to have a finer-grained way of
defining and reasoning about program behaviors. This is the topic
of the present chapter. We replace the "big-step" [eval] relation
with a "small-step" relation that specifies, for a given program,
how the "atomic steps" of computation are performed. *)
(* ########################################################### *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] -- for the
constructor names, for brevity.) At the end of the chapter, we'll
see how to apply the same techniques to the full Imp language. *)
Inductive tm : Type :=
| C : nat -> tm (* Constant *)
| P : tm -> tm -> tm. (* Plus *)
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P" ].
(** Here is a standard evaluator for this language, written in the
same (big-step) style as we've been using up to this point. *)
Fixpoint evalF (t : tm) : nat :=
match t with
| C n => n
| P a1 a2 => evalF a1 + evalF a2
end.
(** Now, here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation. Again,
we use the notation [t || n] for "[t] evaluates to [n]." *)
(**
-------- (E_Const)
C n || n
t1 || n1
t2 || n2
---------------------- (E_Plus)
P t1 t2 || C (n1 + n2)
*)
Reserved Notation " t '||' n " (at level 50, left associativity).
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n || n
| E_Plus : forall t1 t2 n1 n2,
t1 || n1 ->
t2 || n2 ->
P t1 t2 || (n1 + n2)
where " t '||' n " := (eval t n).
Tactic Notation "eval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Const" | Case_aux c "E_Plus" ].
Module SimpleArith1.
(** Now, here is a small-step version. *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
t2 ==> t2'
--------------------------- (ST_Plus2)
P (C n1) t2 ==> P (C n1) t2'
*)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 ==> t2' ->
P (C n1) t2 ==> P (C n1) t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** Let's pause and check a couple of examples of reasoning with
the [step] relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [P t1' t2]: *)
Example test_step_1 :
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>
P
(C (0 + 3))
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 1 star (test_step_2) *)
(** Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n)
t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>
P
(C 0)
(P
(C 2)
(C (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** * Relations *)
(** We will be using several different step relations, so it is
helpful to generalize a bit and state a few definitions and
theorems about relations in general. (The optional chapter
[Rel.v] develops some of these ideas in a bit more detail; it may
be useful if the treatment here is too dense.) *)
(** A (binary) _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Our main examples of such relations in this chapter will be
the single-step and multi-step reduction relations on terms, [==>]
and [==>*], but there are many other examples -- some that come to
mind are the "equals," "less than," "less than or equal to," and
"is the square of" relations on numbers, and the "prefix of"
relation on lists and strings. *)
(** One simple property of the [==>] relation is that, like the
evaluation relation for our language of Imp programs, it is
_deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t ==> t'] is provable). Formally, this is the
same as saying that [==>] is deterministic. *)
(** _Proof sketch_: We show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal, by induction on a derivation of
[step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and in the given derivation
of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] has both the form [P t1 t2] and
the form [C n]. [] *)
Definition deterministic {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2.
Case "ST_PlusConstConst". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". reflexivity.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2". inversion H2.
Case "ST_Plus1". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H0 in Hy1. inversion Hy1.
SCase "ST_Plus1".
rewrite <- (IHHy1 t1'0).
reflexivity. assumption.
SCase "ST_Plus2". rewrite <- H in Hy1. inversion Hy1.
Case "ST_Plus2". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H1 in Hy1. inversion Hy1.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2".
rewrite <- (IHHy1 t2'0).
reflexivity. assumption.
Qed.
(** There is some annoying repetition in this proof.
Each use of [inversion Hy2] results in three subcases,
only one of which is relevant (the one which matches the
current case in the induction on [Hy1]). The other two
subcases need to be dismissed by finding the contradiction
among the hypotheses and doing inversion on it.
There is a tactic called [solve by inversion] defined in [SfLib.v]
that can be of use in such cases. It will solve the goal if it
can be solved by inverting some hypothesis; otherwise, it fails.
(There are variants [solve by inversion 2] and [solve by inversion 3]
that work if two or three consecutive inversions will solve the goal.)
The example below shows how a proof of the previous theorem can be
simplified using this tactic.
*)
Theorem step_deterministic_alt: deterministic step.
Proof.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2;
inversion Hy2; subst; try (solve by inversion).
Case "ST_PlusConstConst". reflexivity.
Case "ST_Plus1".
apply IHHy1 in H2. rewrite H2. reflexivity.
Case "ST_Plus2".
apply IHHy1 in H2. rewrite H2. reflexivity.
Qed.
End SimpleArith1.
(* ########################################################### *)
(** ** Values *)
(** Let's take a moment to slightly generalize the way we state the
definition of single-step reduction. *)
(** It is useful to think of the [==>] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation.
- The _halting states_ of the machine are ones where there is no
more computation to be done.
*)
(**
We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [==>] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [==>] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
value v1
t2 ==> t2'
-------------------- (ST_Plus2)
P v1 t2 ==> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant. We'll keep it for now,
to maintain a close correspondence between the informal and Coq
versions of the rules, but later on we'll drop it in informal
rules, for the sake of brevity.) *)
(** Here are the formal rules: *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <----- n.b. *)
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** **** Exercise: 3 stars (redo_determinism) *)
(** As a sanity check on this change, let's re-verify determinism
Proof sketch: We must show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal. Consider the final rules used in
the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) AND one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] both has the form [P t1 t2] and
is a value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write it from
scratch and just use the earlier one if you get stuck. *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language is
fairly simple, but for a larger language it would be pretty easy
to forget one of the rules and create a situation where some term
cannot take a step even though it has not been completely reduced
to a value. The following theorem shows that we did not, in fact,
make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): If [t] is a term, then either [t]
is a value, or there exists a term [t'] such that [t ==> t']. *)
(** _Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a [value].
- Suppose [t = P t1 t2], where (by the IH) [t1] is either a
value or can step to some [t1'], and where [t2] is either a
value or can step to some [t2']. We must show [P t1 t2] is
either a value or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. [] *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
tm_cases (induction t) Case.
Case "C". left. apply v_const.
Case "P". right. inversion IHt1.
SCase "l". inversion IHt2.
SSCase "l". inversion H. inversion H0.
exists (C (n + n0)).
apply ST_PlusConstConst.
SSCase "r". inversion H0 as [t' H1].
exists (P t1 t').
apply ST_Plus2. apply H. apply H1.
SCase "r". inversion H as [t' H0].
exists (P t' t2).
apply ST_Plus1. apply H0. Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
simply "progress.") *)
(** The idea of "making progress" can be extended to tell us something
interesting about [value]s: in this language [value]s are exactly
the terms that _cannot_ make progress in this sense.
To state this observation formally, let's begin by giving a name
to terms that cannot make progress. We'll call them _normal
forms_. *)
Definition normal_form {X:Type} (R:relation X) (t:X) : Prop :=
~ exists t', R t t'.
(** This definition actually specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma value_is_nf : forall v,
value v -> normal_form step v.
Proof.
unfold normal_form. intros v H. inversion H.
intros contra. inversion contra. inversion H1.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t ==> t').
SCase "Proof of assertion". apply strong_progress.
inversion G.
SCase "l". apply H0.
SCase "r". apply ex_falso_quodlibet. apply H. assumption. Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf. Qed.
(** Why is this interesting?
Because [value] is a syntactic concept -- it is defined by looking
at the form of a term -- while [normal_form] is a semantic one --
it is defined by looking at how the term steps. It is not obvious
that these concepts should coincide!
Indeed, we could easily have written the definitions so that they
would not coincide... *)
(* ##################################################### *)
(** We might, for example, mistakenly define [value] so that it
includes some terms that are not finished reducing. *)
Module Temp1.
(* Open an inner module so we can redefine value and step. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2, (* <---- *)
value (P t1 (C n2)).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp1.
(* ##################################################### *)
(** Alternatively, we might mistakenly define [step] so that it
permits something designated as a value to reduce further. *)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n, (* <---- *)
C n ==> P (C n) (C 0)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 2 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp2.
(* ########################################################### *)
(** Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, even in a correct language definition, it makes
sense to allow some terms to be stuck. *)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
where " t '==>' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form') *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp3.
(* ########################################################### *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just plus and numbers, are just the booleans true and false and a
conditional expression... *)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** **** Exercise: 1 star (smallstep_bools) *)
(** Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
tfalse ==> tfalse.
(* FILL IN HERE *)
Definition bool_step_prop2 :=
tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>
ttrue.
(* FILL IN HERE *)
Definition bool_step_prop3 :=
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (progress_bool) *)
(** Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars (smallstep_bool_shortcut) *)
(** Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[ttrue] or [tfalse]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
(* FILL IN HERE *)
where " t '==>' t' " := (step t t').
Definition bool_step_prop4 :=
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (properties_of_altered_step) *)
(** It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
(* FILL IN HERE *)
*)
(** [] *)
End Temp5.
End Temp4.
(* ########################################################### *)
(** * Multi-Step Reduction *)
(** Until now, we've been working with the _single-step reduction_
relation [==>], which formalizes the individual steps of an
_abstract machine_ for executing programs.
We can also use this machine to reduce programs to completion --
to find out what final result they yield. This can be formalized
as follows:
- First, we define a _multi-step reduction relation_ [==>*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
of single reduction steps (including zero steps!).
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(* ########################################################### *)
(** Since we'll want to reuse the idea of multi-step reduction many
times in this and future chapters, let's take a little extra
trouble here and define it generically.
Given a relation [R], we define a relation [multi R], called the
_multi-step closure of [R]_ as follows: *)
Inductive multi {X:Type} (R: relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** The effect of this definition is that [multi R] relates two
elements [x] and [y] if either
- [x = y], or else
- there is some sequence [z1], [z2], ..., [zn]
such that
R x z1
R z1 z2
...
R zn y.
Thus, if [R] describes a single-step of computation, [z1],
... [zn] is the sequence of intermediate steps of computation
between [x] and [y].
*)
Tactic Notation "multi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "multi_refl" | Case_aux c "multi_step" ].
(** We write [==>*] for the [multi step] relation -- i.e., the
relation that relates two terms [t] and [t'] if we can get from
[t] to [t'] using the [step] relation zero or more times. *)
Notation " t '==>*' t' " := (multi step t t') (at level 40).
(** The relation [multi R] has several crucial properties.
First, it is obviously _reflexive_ (that is, [forall x, multi R x
x]). In the case of the [==>*] (i.e. [multi step]) relation, the
intuition is that a term can execute to itself by taking zero
steps of execution.
Second, it contains [R] -- that is, single-step executions are a
particular case of multi-step executions. (It is this fact that
justifies the word "closure" in the term "multi-step closure of
[R].") *)
Theorem multi_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl. Qed.
(** Third, [multi R] is _transitive_. *)
Theorem multi_trans :
forall (X:Type) (R: relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
multi_cases (induction G) Case.
Case "multi_refl". assumption.
Case "multi_step".
apply multi_step with y. assumption.
apply IHG. assumption. Qed.
(** That is, if [t1==>*t2] and [t2==>*t3], then [t1==>*t3]. *)
(* ########################################################### *)
(** ** Examples *)
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P
(C (0 + 3))
(P (C 2) (C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with
(P
(C (0 + 3))
(C (2 + 4))).
apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
apply multi_R.
apply ST_PlusConstConst. Qed.
(** Here's an alternate proof that uses [eapply] to avoid explicitly
constructing all the intermediate terms. *)
Lemma test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
eapply multi_step. apply ST_PlusConstConst.
apply multi_refl. Qed.
(** **** Exercise: 1 star, optional (test_multistep_2) *)
Lemma test_multistep_2:
C 3 ==>* C 3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (test_multistep_3) *)
Lemma test_multistep_3:
P (C 0) (C 3)
==>*
P (C 0) (C 3).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (test_multistep_4) *)
Lemma test_multistep_4:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t ==>* t' /\ step_normal_form t').
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, optional (normal_forms_unique) *)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
unfold deterministic. unfold normal_form_of. intros x y1 y2 P1 P2.
inversion P1 as [P11 P12]; clear P1. inversion P2 as [P21 P22]; clear P2.
generalize dependent y2.
(* We recommend using this initial setup as-is! *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X:Type} (R:relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the left-hand child of a [P] node, and
similarly when [t] appears as the right-hand child of a [P]
node whose left-hand child is a value. *)
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros t1 t1' t2 H. multi_cases (induction H) Case.
Case "multi_refl". apply multi_refl.
Case "multi_step". apply multi_step with (P y t2).
apply ST_Plus1. apply H.
apply IHmulti. Qed.
(** **** Exercise: 2 stars (multistep_congr_2) *)
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** _Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] steps to [t'] and [t'] is
a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step,
and we have [t' = t]. We can derive the left-hand side by
reflexivity and the right-hand side by observing (a) that values
are normal forms (by [nf_same_as_value]) and (b) that [t] is a
value (by [v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and
[t2] have normal forms [t1'] and [t2']. Recall that normal
forms are values (by [nf_same_as_value]); we know that [t1' =
C n1] and [t2' = C n2], for some [n1] and [n2].
We can combine the [==>*] derivations for [t1] and [t2] to prove
that [P t1 t2] reduces in many steps to [C (n1 + n2)].
It is clear that our choice of [t' = C (n1 + n2)] is a
value, which is in turn a normal form. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
tm_cases (induction t) Case.
Case "C".
exists (C n).
split.
SCase "l". apply multi_refl.
SCase "r".
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
Case "P".
inversion IHt1 as [t1' H1]; clear IHt1. inversion IHt2 as [t2' H2]; clear IHt2.
inversion H1 as [H11 H12]; clear H1. inversion H2 as [H21 H22]; clear H2.
rewrite nf_same_as_value in H12. rewrite nf_same_as_value in H22.
inversion H12 as [n1]. inversion H22 as [n2].
rewrite <- H in H11.
rewrite <- H0 in H21.
exists (C (n1 + n2)).
split.
SCase "l".
apply multi_trans with (P (C n1) t2).
apply multistep_congr_1. apply H11.
apply multi_trans with
(P (C n1) (C n2)).
apply multistep_congr_2. apply v_const. apply H21.
apply multi_R. apply ST_PlusConstConst.
SCase "r".
rewrite nf_same_as_value. apply v_const. Qed.
(* ########################################################### *)
(** ** Equivalence of Big-Step and Small-Step Reduction *)
(** Having defined the operational semantics of our tiny programming
language in two different styles, it makes sense to ask whether
these definitions actually define the same thing! They do, though
it takes a little work to show it. (The details are left as an
exercise). *)
(** **** Exercise: 3 stars (eval__multistep) *)
Theorem eval__multistep : forall t n,
t || n -> t ==>* C n.
(** The key idea behind the proof comes from the following picture:
P t1 t2 ==> (by ST_Plus1)
P t1' t2 ==> (by ST_Plus1)
P t1'' t2 ==> (by ST_Plus1)
...
P (C n1) t2 ==> (by ST_Plus2)
P (C n1) t2' ==> (by ST_Plus2)
P (C n1) t2'' ==> (by ST_Plus2)
...
P (C n1) (C n2) ==> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)]. *)
(** To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [==>*]: that it is reflexive, transitive, and
includes [==>]. *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (eval__multistep_inf) *)
(** Write a detailed informal version of the proof of [eval__multistep].
(* FILL IN HERE *)
[]
*)
(** For the other direction, we need one lemma, which establishes a
relation between single-step reduction and big-step evaluation. *)
(** **** Exercise: 3 stars (step__eval) *)
Lemma step__eval : forall t t' n,
t ==> t' ->
t' || n ->
t || n.
Proof.
intros t t' n Hs. generalize dependent n.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The fact that small-step reduction implies big-step is now
straightforward to prove, once it is stated correctly.
The proof proceeds by induction on the multi-step reduction
sequence that is buried in the hypothesis [normal_form_of t t']. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars (multistep__eval) *)
Theorem multistep__eval : forall t t',
normal_form_of t t' -> exists n, t' = C n /\ t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 3 stars, optional (interp_tm) *)
(** Remember that we also defined big-step evaluation of [tm]s as a
function [evalF]. Prove that it is equivalent to the existing
semantics.
Hint: we just proved that [eval] and [multistep] are
equivalent, so logically it doesn't matter which you choose.
One will be easier than the other, though! *)
Theorem evalF_eval : forall t n,
evalF t = n <-> t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (combined_properties) *)
(** We've considered the arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P"
| Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2"
| Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Prove or disprove these two properties for the combined language. *)
(* FILL IN HERE *)
(** [] *)
End Combined.
(* ########################################################### *)
(** * Small-Step Imp *)
(** For a more serious example, here is the small-step version of the
Imp operational semantics. *)
(** The small-step evaluation relations for arithmetic and boolean
expressions are straightforward extensions of the tiny language
we've been working up to now. To make them easier to read, we
introduce the symbolic notations [==>a] and [==>b], respectively,
for the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values, since they aren't needed in the definition of [==>b]
below (why?), though they might be if our language were a bit
larger (why?). *)
Reserved Notation " t '/' st '==>a' t' " (at level 40, st at level 39).
Inductive astep : state -> aexp -> aexp -> Prop :=
| AS_Id : forall st i,
AId i / st ==>a ANum (st i)
| AS_Plus : forall st n1 n2,
APlus (ANum n1) (ANum n2) / st ==>a ANum (n1 + n2)
| AS_Plus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(APlus a1 a2) / st ==>a (APlus a1' a2)
| AS_Plus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(APlus v1 a2) / st ==>a (APlus v1 a2')
| AS_Minus : forall st n1 n2,
(AMinus (ANum n1) (ANum n2)) / st ==>a (ANum (minus n1 n2))
| AS_Minus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMinus a1 a2) / st ==>a (AMinus a1' a2)
| AS_Minus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMinus v1 a2) / st ==>a (AMinus v1 a2')
| AS_Mult : forall st n1 n2,
(AMult (ANum n1) (ANum n2)) / st ==>a (ANum (mult n1 n2))
| AS_Mult1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMult (a1) (a2)) / st ==>a (AMult (a1') (a2))
| AS_Mult2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMult v1 a2) / st ==>a (AMult v1 a2')
where " t '/' st '==>a' t' " := (astep st t t').
Reserved Notation " t '/' st '==>b' t' " (at level 40, st at level 39).
Inductive bstep : state -> bexp -> bexp -> Prop :=
| BS_Eq : forall st n1 n2,
(BEq (ANum n1) (ANum n2)) / st ==>b
(if (beq_nat n1 n2) then BTrue else BFalse)
| BS_Eq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BEq a1 a2) / st ==>b (BEq a1' a2)
| BS_Eq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BEq v1 a2) / st ==>b (BEq v1 a2')
| BS_LtEq : forall st n1 n2,
(BLe (ANum n1) (ANum n2)) / st ==>b
(if (ble_nat n1 n2) then BTrue else BFalse)
| BS_LtEq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BLe a1 a2) / st ==>b (BLe a1' a2)
| BS_LtEq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BLe v1 a2) / st ==>b (BLe v1 (a2'))
| BS_NotTrue : forall st,
(BNot BTrue) / st ==>b BFalse
| BS_NotFalse : forall st,
(BNot BFalse) / st ==>b BTrue
| BS_NotStep : forall st b1 b1',
b1 / st ==>b b1' ->
(BNot b1) / st ==>b (BNot b1')
| BS_AndTrueTrue : forall st,
(BAnd BTrue BTrue) / st ==>b BTrue
| BS_AndTrueFalse : forall st,
(BAnd BTrue BFalse) / st ==>b BFalse
| BS_AndFalse : forall st b2,
(BAnd BFalse b2) / st ==>b BFalse
| BS_AndTrueStep : forall st b2 b2',
b2 / st ==>b b2' ->
(BAnd BTrue b2) / st ==>b (BAnd BTrue b2')
| BS_AndStep : forall st b1 b1' b2,
b1 / st ==>b b1' ->
(BAnd b1 b2) / st ==>b (BAnd b1' b2)
where " t '/' st '==>b' t' " := (bstep st t t').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [SKIP] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [SKIP] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [SKIP], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [WHILE] command by transforming it into a
conditional followed by the same [WHILE]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [WHILE]
command needs to be saved somewhere while a single copy of the loop
body is being evaluated.) *)
Reserved Notation " t '/' st '==>' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
IFB BTrue THEN c1 ELSE c2 FI / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
IFB BFalse THEN c1 ELSE c2 FI / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b / st ==>b b' ->
IFB b THEN c1 ELSE c2 FI / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
(* ########################################################### *)
(** * Concurrent Imp *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
(* New: *)
| CPar : com -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "PAR" ].
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' b 'THEN' c1 'ELSE' c2 'FI'" :=
(CIf b c1 c2) (at level 80, right associativity).
Notation "'PAR' c1 'WITH' c2 'END'" :=
(CPar c1 c2) (at level 80, right associativity).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
(IFB BTrue THEN c1 ELSE c2 FI) / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
(IFB BFalse THEN c1 ELSE c2 FI) / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b /st ==>b b' ->
(IFB b THEN c1 ELSE c2 FI) / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st ==>
(IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st ==> c1' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1' WITH c2 END) / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st ==> c2' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1 WITH c2' END) / st'
| CS_ParDone : forall st,
(PAR SKIP WITH SKIP END) / st ==> SKIP / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '==>*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value... *)
Definition par_loop : com :=
PAR
Y ::= ANum 1
WITH
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END
END.
(** In particular, it can terminate with [X] set to [0]: *)
Example par_loop_example_0:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st ==>* par_loop / (update st X (S n)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st ==>* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_state).
split; unfold update; reflexivity.
rename x into st.
inversion H as [H' [HX HY]]; clear H.
exists (update st Y 1). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite update_neq. assumption. intro X; inversion X.
Qed.
End CImp.
(* ########################################################### *)
(** * A Small-Step Stack Machine *)
(** Last example: a small-step semantics for the stack machine example
from Imp.v. *)
Definition stack := list nat.
Definition prog := list sinstr.
Inductive stack_step : state -> prog * stack -> prog * stack -> Prop :=
| SS_Push : forall st stk n p',
stack_step st (SPush n :: p', stk) (p', n :: stk)
| SS_Load : forall st stk i p',
stack_step st (SLoad i :: p', stk) (p', st i :: stk)
| SS_Plus : forall st stk n m p',
stack_step st (SPlus :: p', n::m::stk) (p', (m+n)::stk)
| SS_Minus : forall st stk n m p',
stack_step st (SMinus :: p', n::m::stk) (p', (m-n)::stk)
| SS_Mult : forall st stk n m p',
stack_step st (SMult :: p', n::m::stk) (p', (m*n)::stk).
Theorem stack_step_deterministic : forall st,
deterministic (stack_step st).
Proof.
unfold deterministic. intros st x y1 y2 H1 H2.
induction H1; inversion H2; reflexivity.
Qed.
Definition stack_multistep st := multi (stack_step st).
(** **** Exercise: 3 stars, advanced (compiler_is_correct) *)
(** Remember the definition of [compile] for [aexp] given in the
[Imp] chapter. We want now to prove [compile] correct with respect
to the stack machine.
State what it means for the compiler to be correct according to
the stack machine small step semantics and then prove it. *)
Definition compiler_is_correct_statement : Prop :=
(* FILL IN HERE *) admit.
Theorem compiler_is_correct : compiler_is_correct_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** $Date: 2014-12-31 15:16:58 -0500 (Wed, 31 Dec 2014) $ *)
|
(** * Smallstep: Small-step Operational Semantics *)
Require Export Imp.
(** The evaluators we have seen so far (e.g., the ones for
[aexp]s, [bexp]s, and commands) have been formulated in a
"big-step" style -- they specify how a given expression can be
evaluated to its final value (or a command plus a store to a final
store) "all in one big step."
This style is simple and natural for many purposes -- indeed,
Gilles Kahn, who popularized its use, called it _natural
semantics_. But there are some things it does not do well. In
particular, it does not give us a natural way of talking about
_concurrent_ programming languages, where the "semantics" of a
program -- i.e., the essence of how it behaves -- is not just
which input states get mapped to which output states, but also
includes the intermediate states that it passes through along the
way, since these states can also be observed by concurrently
executing code.
Another shortcoming of the big-step style is more technical, but
critical in some situations. To see the issue, suppose we wanted
to define a variant of Imp where variables could hold _either_
numbers _or_ lists of numbers (see the [HoareList] chapter for
details). In the syntax of this extended language, it will be
possible to write strange expressions like [2 + nil], and our
semantics for arithmetic expressions will then need to say
something about how such expressions behave. One
possibility (explored in the [HoareList] chapter) is to maintain
the convention that every arithmetic expressions evaluates to some
number by choosing some way of viewing a list as a number -- e.g.,
by specifying that a list should be interpreted as [0] when it
occurs in a context expecting a number. But this is really a bit
of a hack.
A much more natural approach is simply to say that the behavior of
an expression like [2+nil] is _undefined_ -- it doesn't evaluate
to any result at all. And we can easily do this: we just have to
formulate [aeval] and [beval] as [Inductive] propositions rather
than Fixpoints, so that we can make them partial functions instead
of total ones.
However, now we encounter a serious deficiency. In this language,
a command might _fail_ to map a given starting state to any ending
state for two quite different reasons: either because the
execution gets into an infinite loop or because, at some point,
the program tries to do an operation that makes no sense, such as
adding a number to a list, and none of the evaluation rules can be
applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- are quite different. In particular, we
want to allow the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but prevent the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a
different way of presenting the semantics that allows us to
distinguish nontermination from erroneous "stuck states."
So, for lots of reasons, we'd like to have a finer-grained way of
defining and reasoning about program behaviors. This is the topic
of the present chapter. We replace the "big-step" [eval] relation
with a "small-step" relation that specifies, for a given program,
how the "atomic steps" of computation are performed. *)
(* ########################################################### *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] -- for the
constructor names, for brevity.) At the end of the chapter, we'll
see how to apply the same techniques to the full Imp language. *)
Inductive tm : Type :=
| C : nat -> tm (* Constant *)
| P : tm -> tm -> tm. (* Plus *)
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P" ].
(** Here is a standard evaluator for this language, written in the
same (big-step) style as we've been using up to this point. *)
Fixpoint evalF (t : tm) : nat :=
match t with
| C n => n
| P a1 a2 => evalF a1 + evalF a2
end.
(** Now, here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation. Again,
we use the notation [t || n] for "[t] evaluates to [n]." *)
(**
-------- (E_Const)
C n || n
t1 || n1
t2 || n2
---------------------- (E_Plus)
P t1 t2 || C (n1 + n2)
*)
Reserved Notation " t '||' n " (at level 50, left associativity).
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n || n
| E_Plus : forall t1 t2 n1 n2,
t1 || n1 ->
t2 || n2 ->
P t1 t2 || (n1 + n2)
where " t '||' n " := (eval t n).
Tactic Notation "eval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Const" | Case_aux c "E_Plus" ].
Module SimpleArith1.
(** Now, here is a small-step version. *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
t2 ==> t2'
--------------------------- (ST_Plus2)
P (C n1) t2 ==> P (C n1) t2'
*)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 ==> t2' ->
P (C n1) t2 ==> P (C n1) t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** Let's pause and check a couple of examples of reasoning with
the [step] relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [P t1' t2]: *)
Example test_step_1 :
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>
P
(C (0 + 3))
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 1 star (test_step_2) *)
(** Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n)
t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>
P
(C 0)
(P
(C 2)
(C (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** * Relations *)
(** We will be using several different step relations, so it is
helpful to generalize a bit and state a few definitions and
theorems about relations in general. (The optional chapter
[Rel.v] develops some of these ideas in a bit more detail; it may
be useful if the treatment here is too dense.) *)
(** A (binary) _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Our main examples of such relations in this chapter will be
the single-step and multi-step reduction relations on terms, [==>]
and [==>*], but there are many other examples -- some that come to
mind are the "equals," "less than," "less than or equal to," and
"is the square of" relations on numbers, and the "prefix of"
relation on lists and strings. *)
(** One simple property of the [==>] relation is that, like the
evaluation relation for our language of Imp programs, it is
_deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t ==> t'] is provable). Formally, this is the
same as saying that [==>] is deterministic. *)
(** _Proof sketch_: We show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal, by induction on a derivation of
[step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and in the given derivation
of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] has both the form [P t1 t2] and
the form [C n]. [] *)
Definition deterministic {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2.
Case "ST_PlusConstConst". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". reflexivity.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2". inversion H2.
Case "ST_Plus1". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H0 in Hy1. inversion Hy1.
SCase "ST_Plus1".
rewrite <- (IHHy1 t1'0).
reflexivity. assumption.
SCase "ST_Plus2". rewrite <- H in Hy1. inversion Hy1.
Case "ST_Plus2". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H1 in Hy1. inversion Hy1.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2".
rewrite <- (IHHy1 t2'0).
reflexivity. assumption.
Qed.
(** There is some annoying repetition in this proof.
Each use of [inversion Hy2] results in three subcases,
only one of which is relevant (the one which matches the
current case in the induction on [Hy1]). The other two
subcases need to be dismissed by finding the contradiction
among the hypotheses and doing inversion on it.
There is a tactic called [solve by inversion] defined in [SfLib.v]
that can be of use in such cases. It will solve the goal if it
can be solved by inverting some hypothesis; otherwise, it fails.
(There are variants [solve by inversion 2] and [solve by inversion 3]
that work if two or three consecutive inversions will solve the goal.)
The example below shows how a proof of the previous theorem can be
simplified using this tactic.
*)
Theorem step_deterministic_alt: deterministic step.
Proof.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2;
inversion Hy2; subst; try (solve by inversion).
Case "ST_PlusConstConst". reflexivity.
Case "ST_Plus1".
apply IHHy1 in H2. rewrite H2. reflexivity.
Case "ST_Plus2".
apply IHHy1 in H2. rewrite H2. reflexivity.
Qed.
End SimpleArith1.
(* ########################################################### *)
(** ** Values *)
(** Let's take a moment to slightly generalize the way we state the
definition of single-step reduction. *)
(** It is useful to think of the [==>] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation.
- The _halting states_ of the machine are ones where there is no
more computation to be done.
*)
(**
We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [==>] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [==>] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
value v1
t2 ==> t2'
-------------------- (ST_Plus2)
P v1 t2 ==> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant. We'll keep it for now,
to maintain a close correspondence between the informal and Coq
versions of the rules, but later on we'll drop it in informal
rules, for the sake of brevity.) *)
(** Here are the formal rules: *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <----- n.b. *)
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** **** Exercise: 3 stars (redo_determinism) *)
(** As a sanity check on this change, let's re-verify determinism
Proof sketch: We must show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal. Consider the final rules used in
the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) AND one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] both has the form [P t1 t2] and
is a value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write it from
scratch and just use the earlier one if you get stuck. *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language is
fairly simple, but for a larger language it would be pretty easy
to forget one of the rules and create a situation where some term
cannot take a step even though it has not been completely reduced
to a value. The following theorem shows that we did not, in fact,
make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): If [t] is a term, then either [t]
is a value, or there exists a term [t'] such that [t ==> t']. *)
(** _Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a [value].
- Suppose [t = P t1 t2], where (by the IH) [t1] is either a
value or can step to some [t1'], and where [t2] is either a
value or can step to some [t2']. We must show [P t1 t2] is
either a value or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. [] *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
tm_cases (induction t) Case.
Case "C". left. apply v_const.
Case "P". right. inversion IHt1.
SCase "l". inversion IHt2.
SSCase "l". inversion H. inversion H0.
exists (C (n + n0)).
apply ST_PlusConstConst.
SSCase "r". inversion H0 as [t' H1].
exists (P t1 t').
apply ST_Plus2. apply H. apply H1.
SCase "r". inversion H as [t' H0].
exists (P t' t2).
apply ST_Plus1. apply H0. Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
simply "progress.") *)
(** The idea of "making progress" can be extended to tell us something
interesting about [value]s: in this language [value]s are exactly
the terms that _cannot_ make progress in this sense.
To state this observation formally, let's begin by giving a name
to terms that cannot make progress. We'll call them _normal
forms_. *)
Definition normal_form {X:Type} (R:relation X) (t:X) : Prop :=
~ exists t', R t t'.
(** This definition actually specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma value_is_nf : forall v,
value v -> normal_form step v.
Proof.
unfold normal_form. intros v H. inversion H.
intros contra. inversion contra. inversion H1.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t ==> t').
SCase "Proof of assertion". apply strong_progress.
inversion G.
SCase "l". apply H0.
SCase "r". apply ex_falso_quodlibet. apply H. assumption. Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf. Qed.
(** Why is this interesting?
Because [value] is a syntactic concept -- it is defined by looking
at the form of a term -- while [normal_form] is a semantic one --
it is defined by looking at how the term steps. It is not obvious
that these concepts should coincide!
Indeed, we could easily have written the definitions so that they
would not coincide... *)
(* ##################################################### *)
(** We might, for example, mistakenly define [value] so that it
includes some terms that are not finished reducing. *)
Module Temp1.
(* Open an inner module so we can redefine value and step. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2, (* <---- *)
value (P t1 (C n2)).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp1.
(* ##################################################### *)
(** Alternatively, we might mistakenly define [step] so that it
permits something designated as a value to reduce further. *)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n, (* <---- *)
C n ==> P (C n) (C 0)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 2 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp2.
(* ########################################################### *)
(** Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, even in a correct language definition, it makes
sense to allow some terms to be stuck. *)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
where " t '==>' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form') *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp3.
(* ########################################################### *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just plus and numbers, are just the booleans true and false and a
conditional expression... *)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** **** Exercise: 1 star (smallstep_bools) *)
(** Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
tfalse ==> tfalse.
(* FILL IN HERE *)
Definition bool_step_prop2 :=
tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>
ttrue.
(* FILL IN HERE *)
Definition bool_step_prop3 :=
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (progress_bool) *)
(** Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars (smallstep_bool_shortcut) *)
(** Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[ttrue] or [tfalse]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
(* FILL IN HERE *)
where " t '==>' t' " := (step t t').
Definition bool_step_prop4 :=
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (properties_of_altered_step) *)
(** It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
(* FILL IN HERE *)
*)
(** [] *)
End Temp5.
End Temp4.
(* ########################################################### *)
(** * Multi-Step Reduction *)
(** Until now, we've been working with the _single-step reduction_
relation [==>], which formalizes the individual steps of an
_abstract machine_ for executing programs.
We can also use this machine to reduce programs to completion --
to find out what final result they yield. This can be formalized
as follows:
- First, we define a _multi-step reduction relation_ [==>*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
of single reduction steps (including zero steps!).
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(* ########################################################### *)
(** Since we'll want to reuse the idea of multi-step reduction many
times in this and future chapters, let's take a little extra
trouble here and define it generically.
Given a relation [R], we define a relation [multi R], called the
_multi-step closure of [R]_ as follows: *)
Inductive multi {X:Type} (R: relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** The effect of this definition is that [multi R] relates two
elements [x] and [y] if either
- [x = y], or else
- there is some sequence [z1], [z2], ..., [zn]
such that
R x z1
R z1 z2
...
R zn y.
Thus, if [R] describes a single-step of computation, [z1],
... [zn] is the sequence of intermediate steps of computation
between [x] and [y].
*)
Tactic Notation "multi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "multi_refl" | Case_aux c "multi_step" ].
(** We write [==>*] for the [multi step] relation -- i.e., the
relation that relates two terms [t] and [t'] if we can get from
[t] to [t'] using the [step] relation zero or more times. *)
Notation " t '==>*' t' " := (multi step t t') (at level 40).
(** The relation [multi R] has several crucial properties.
First, it is obviously _reflexive_ (that is, [forall x, multi R x
x]). In the case of the [==>*] (i.e. [multi step]) relation, the
intuition is that a term can execute to itself by taking zero
steps of execution.
Second, it contains [R] -- that is, single-step executions are a
particular case of multi-step executions. (It is this fact that
justifies the word "closure" in the term "multi-step closure of
[R].") *)
Theorem multi_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl. Qed.
(** Third, [multi R] is _transitive_. *)
Theorem multi_trans :
forall (X:Type) (R: relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
multi_cases (induction G) Case.
Case "multi_refl". assumption.
Case "multi_step".
apply multi_step with y. assumption.
apply IHG. assumption. Qed.
(** That is, if [t1==>*t2] and [t2==>*t3], then [t1==>*t3]. *)
(* ########################################################### *)
(** ** Examples *)
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P
(C (0 + 3))
(P (C 2) (C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with
(P
(C (0 + 3))
(C (2 + 4))).
apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
apply multi_R.
apply ST_PlusConstConst. Qed.
(** Here's an alternate proof that uses [eapply] to avoid explicitly
constructing all the intermediate terms. *)
Lemma test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
eapply multi_step. apply ST_PlusConstConst.
apply multi_refl. Qed.
(** **** Exercise: 1 star, optional (test_multistep_2) *)
Lemma test_multistep_2:
C 3 ==>* C 3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (test_multistep_3) *)
Lemma test_multistep_3:
P (C 0) (C 3)
==>*
P (C 0) (C 3).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (test_multistep_4) *)
Lemma test_multistep_4:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t ==>* t' /\ step_normal_form t').
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, optional (normal_forms_unique) *)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
unfold deterministic. unfold normal_form_of. intros x y1 y2 P1 P2.
inversion P1 as [P11 P12]; clear P1. inversion P2 as [P21 P22]; clear P2.
generalize dependent y2.
(* We recommend using this initial setup as-is! *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X:Type} (R:relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the left-hand child of a [P] node, and
similarly when [t] appears as the right-hand child of a [P]
node whose left-hand child is a value. *)
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros t1 t1' t2 H. multi_cases (induction H) Case.
Case "multi_refl". apply multi_refl.
Case "multi_step". apply multi_step with (P y t2).
apply ST_Plus1. apply H.
apply IHmulti. Qed.
(** **** Exercise: 2 stars (multistep_congr_2) *)
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** _Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] steps to [t'] and [t'] is
a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step,
and we have [t' = t]. We can derive the left-hand side by
reflexivity and the right-hand side by observing (a) that values
are normal forms (by [nf_same_as_value]) and (b) that [t] is a
value (by [v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and
[t2] have normal forms [t1'] and [t2']. Recall that normal
forms are values (by [nf_same_as_value]); we know that [t1' =
C n1] and [t2' = C n2], for some [n1] and [n2].
We can combine the [==>*] derivations for [t1] and [t2] to prove
that [P t1 t2] reduces in many steps to [C (n1 + n2)].
It is clear that our choice of [t' = C (n1 + n2)] is a
value, which is in turn a normal form. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
tm_cases (induction t) Case.
Case "C".
exists (C n).
split.
SCase "l". apply multi_refl.
SCase "r".
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
Case "P".
inversion IHt1 as [t1' H1]; clear IHt1. inversion IHt2 as [t2' H2]; clear IHt2.
inversion H1 as [H11 H12]; clear H1. inversion H2 as [H21 H22]; clear H2.
rewrite nf_same_as_value in H12. rewrite nf_same_as_value in H22.
inversion H12 as [n1]. inversion H22 as [n2].
rewrite <- H in H11.
rewrite <- H0 in H21.
exists (C (n1 + n2)).
split.
SCase "l".
apply multi_trans with (P (C n1) t2).
apply multistep_congr_1. apply H11.
apply multi_trans with
(P (C n1) (C n2)).
apply multistep_congr_2. apply v_const. apply H21.
apply multi_R. apply ST_PlusConstConst.
SCase "r".
rewrite nf_same_as_value. apply v_const. Qed.
(* ########################################################### *)
(** ** Equivalence of Big-Step and Small-Step Reduction *)
(** Having defined the operational semantics of our tiny programming
language in two different styles, it makes sense to ask whether
these definitions actually define the same thing! They do, though
it takes a little work to show it. (The details are left as an
exercise). *)
(** **** Exercise: 3 stars (eval__multistep) *)
Theorem eval__multistep : forall t n,
t || n -> t ==>* C n.
(** The key idea behind the proof comes from the following picture:
P t1 t2 ==> (by ST_Plus1)
P t1' t2 ==> (by ST_Plus1)
P t1'' t2 ==> (by ST_Plus1)
...
P (C n1) t2 ==> (by ST_Plus2)
P (C n1) t2' ==> (by ST_Plus2)
P (C n1) t2'' ==> (by ST_Plus2)
...
P (C n1) (C n2) ==> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)]. *)
(** To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [==>*]: that it is reflexive, transitive, and
includes [==>]. *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (eval__multistep_inf) *)
(** Write a detailed informal version of the proof of [eval__multistep].
(* FILL IN HERE *)
[]
*)
(** For the other direction, we need one lemma, which establishes a
relation between single-step reduction and big-step evaluation. *)
(** **** Exercise: 3 stars (step__eval) *)
Lemma step__eval : forall t t' n,
t ==> t' ->
t' || n ->
t || n.
Proof.
intros t t' n Hs. generalize dependent n.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The fact that small-step reduction implies big-step is now
straightforward to prove, once it is stated correctly.
The proof proceeds by induction on the multi-step reduction
sequence that is buried in the hypothesis [normal_form_of t t']. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars (multistep__eval) *)
Theorem multistep__eval : forall t t',
normal_form_of t t' -> exists n, t' = C n /\ t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 3 stars, optional (interp_tm) *)
(** Remember that we also defined big-step evaluation of [tm]s as a
function [evalF]. Prove that it is equivalent to the existing
semantics.
Hint: we just proved that [eval] and [multistep] are
equivalent, so logically it doesn't matter which you choose.
One will be easier than the other, though! *)
Theorem evalF_eval : forall t n,
evalF t = n <-> t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (combined_properties) *)
(** We've considered the arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P"
| Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2"
| Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Prove or disprove these two properties for the combined language. *)
(* FILL IN HERE *)
(** [] *)
End Combined.
(* ########################################################### *)
(** * Small-Step Imp *)
(** For a more serious example, here is the small-step version of the
Imp operational semantics. *)
(** The small-step evaluation relations for arithmetic and boolean
expressions are straightforward extensions of the tiny language
we've been working up to now. To make them easier to read, we
introduce the symbolic notations [==>a] and [==>b], respectively,
for the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values, since they aren't needed in the definition of [==>b]
below (why?), though they might be if our language were a bit
larger (why?). *)
Reserved Notation " t '/' st '==>a' t' " (at level 40, st at level 39).
Inductive astep : state -> aexp -> aexp -> Prop :=
| AS_Id : forall st i,
AId i / st ==>a ANum (st i)
| AS_Plus : forall st n1 n2,
APlus (ANum n1) (ANum n2) / st ==>a ANum (n1 + n2)
| AS_Plus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(APlus a1 a2) / st ==>a (APlus a1' a2)
| AS_Plus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(APlus v1 a2) / st ==>a (APlus v1 a2')
| AS_Minus : forall st n1 n2,
(AMinus (ANum n1) (ANum n2)) / st ==>a (ANum (minus n1 n2))
| AS_Minus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMinus a1 a2) / st ==>a (AMinus a1' a2)
| AS_Minus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMinus v1 a2) / st ==>a (AMinus v1 a2')
| AS_Mult : forall st n1 n2,
(AMult (ANum n1) (ANum n2)) / st ==>a (ANum (mult n1 n2))
| AS_Mult1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMult (a1) (a2)) / st ==>a (AMult (a1') (a2))
| AS_Mult2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMult v1 a2) / st ==>a (AMult v1 a2')
where " t '/' st '==>a' t' " := (astep st t t').
Reserved Notation " t '/' st '==>b' t' " (at level 40, st at level 39).
Inductive bstep : state -> bexp -> bexp -> Prop :=
| BS_Eq : forall st n1 n2,
(BEq (ANum n1) (ANum n2)) / st ==>b
(if (beq_nat n1 n2) then BTrue else BFalse)
| BS_Eq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BEq a1 a2) / st ==>b (BEq a1' a2)
| BS_Eq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BEq v1 a2) / st ==>b (BEq v1 a2')
| BS_LtEq : forall st n1 n2,
(BLe (ANum n1) (ANum n2)) / st ==>b
(if (ble_nat n1 n2) then BTrue else BFalse)
| BS_LtEq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BLe a1 a2) / st ==>b (BLe a1' a2)
| BS_LtEq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BLe v1 a2) / st ==>b (BLe v1 (a2'))
| BS_NotTrue : forall st,
(BNot BTrue) / st ==>b BFalse
| BS_NotFalse : forall st,
(BNot BFalse) / st ==>b BTrue
| BS_NotStep : forall st b1 b1',
b1 / st ==>b b1' ->
(BNot b1) / st ==>b (BNot b1')
| BS_AndTrueTrue : forall st,
(BAnd BTrue BTrue) / st ==>b BTrue
| BS_AndTrueFalse : forall st,
(BAnd BTrue BFalse) / st ==>b BFalse
| BS_AndFalse : forall st b2,
(BAnd BFalse b2) / st ==>b BFalse
| BS_AndTrueStep : forall st b2 b2',
b2 / st ==>b b2' ->
(BAnd BTrue b2) / st ==>b (BAnd BTrue b2')
| BS_AndStep : forall st b1 b1' b2,
b1 / st ==>b b1' ->
(BAnd b1 b2) / st ==>b (BAnd b1' b2)
where " t '/' st '==>b' t' " := (bstep st t t').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [SKIP] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [SKIP] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [SKIP], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [WHILE] command by transforming it into a
conditional followed by the same [WHILE]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [WHILE]
command needs to be saved somewhere while a single copy of the loop
body is being evaluated.) *)
Reserved Notation " t '/' st '==>' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
IFB BTrue THEN c1 ELSE c2 FI / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
IFB BFalse THEN c1 ELSE c2 FI / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b / st ==>b b' ->
IFB b THEN c1 ELSE c2 FI / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
(* ########################################################### *)
(** * Concurrent Imp *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
(* New: *)
| CPar : com -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "PAR" ].
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' b 'THEN' c1 'ELSE' c2 'FI'" :=
(CIf b c1 c2) (at level 80, right associativity).
Notation "'PAR' c1 'WITH' c2 'END'" :=
(CPar c1 c2) (at level 80, right associativity).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
(IFB BTrue THEN c1 ELSE c2 FI) / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
(IFB BFalse THEN c1 ELSE c2 FI) / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b /st ==>b b' ->
(IFB b THEN c1 ELSE c2 FI) / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st ==>
(IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st ==> c1' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1' WITH c2 END) / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st ==> c2' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1 WITH c2' END) / st'
| CS_ParDone : forall st,
(PAR SKIP WITH SKIP END) / st ==> SKIP / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '==>*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value... *)
Definition par_loop : com :=
PAR
Y ::= ANum 1
WITH
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END
END.
(** In particular, it can terminate with [X] set to [0]: *)
Example par_loop_example_0:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st ==>* par_loop / (update st X (S n)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st ==>* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_state).
split; unfold update; reflexivity.
rename x into st.
inversion H as [H' [HX HY]]; clear H.
exists (update st Y 1). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite update_neq. assumption. intro X; inversion X.
Qed.
End CImp.
(* ########################################################### *)
(** * A Small-Step Stack Machine *)
(** Last example: a small-step semantics for the stack machine example
from Imp.v. *)
Definition stack := list nat.
Definition prog := list sinstr.
Inductive stack_step : state -> prog * stack -> prog * stack -> Prop :=
| SS_Push : forall st stk n p',
stack_step st (SPush n :: p', stk) (p', n :: stk)
| SS_Load : forall st stk i p',
stack_step st (SLoad i :: p', stk) (p', st i :: stk)
| SS_Plus : forall st stk n m p',
stack_step st (SPlus :: p', n::m::stk) (p', (m+n)::stk)
| SS_Minus : forall st stk n m p',
stack_step st (SMinus :: p', n::m::stk) (p', (m-n)::stk)
| SS_Mult : forall st stk n m p',
stack_step st (SMult :: p', n::m::stk) (p', (m*n)::stk).
Theorem stack_step_deterministic : forall st,
deterministic (stack_step st).
Proof.
unfold deterministic. intros st x y1 y2 H1 H2.
induction H1; inversion H2; reflexivity.
Qed.
Definition stack_multistep st := multi (stack_step st).
(** **** Exercise: 3 stars, advanced (compiler_is_correct) *)
(** Remember the definition of [compile] for [aexp] given in the
[Imp] chapter. We want now to prove [compile] correct with respect
to the stack machine.
State what it means for the compiler to be correct according to
the stack machine small step semantics and then prove it. *)
Definition compiler_is_correct_statement : Prop :=
(* FILL IN HERE *) admit.
Theorem compiler_is_correct : compiler_is_correct_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** $Date: 2014-12-31 15:16:58 -0500 (Wed, 31 Dec 2014) $ *)
|
(** * Smallstep: Small-step Operational Semantics *)
Require Export Imp.
(** The evaluators we have seen so far (e.g., the ones for
[aexp]s, [bexp]s, and commands) have been formulated in a
"big-step" style -- they specify how a given expression can be
evaluated to its final value (or a command plus a store to a final
store) "all in one big step."
This style is simple and natural for many purposes -- indeed,
Gilles Kahn, who popularized its use, called it _natural
semantics_. But there are some things it does not do well. In
particular, it does not give us a natural way of talking about
_concurrent_ programming languages, where the "semantics" of a
program -- i.e., the essence of how it behaves -- is not just
which input states get mapped to which output states, but also
includes the intermediate states that it passes through along the
way, since these states can also be observed by concurrently
executing code.
Another shortcoming of the big-step style is more technical, but
critical in some situations. To see the issue, suppose we wanted
to define a variant of Imp where variables could hold _either_
numbers _or_ lists of numbers (see the [HoareList] chapter for
details). In the syntax of this extended language, it will be
possible to write strange expressions like [2 + nil], and our
semantics for arithmetic expressions will then need to say
something about how such expressions behave. One
possibility (explored in the [HoareList] chapter) is to maintain
the convention that every arithmetic expressions evaluates to some
number by choosing some way of viewing a list as a number -- e.g.,
by specifying that a list should be interpreted as [0] when it
occurs in a context expecting a number. But this is really a bit
of a hack.
A much more natural approach is simply to say that the behavior of
an expression like [2+nil] is _undefined_ -- it doesn't evaluate
to any result at all. And we can easily do this: we just have to
formulate [aeval] and [beval] as [Inductive] propositions rather
than Fixpoints, so that we can make them partial functions instead
of total ones.
However, now we encounter a serious deficiency. In this language,
a command might _fail_ to map a given starting state to any ending
state for two quite different reasons: either because the
execution gets into an infinite loop or because, at some point,
the program tries to do an operation that makes no sense, such as
adding a number to a list, and none of the evaluation rules can be
applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- are quite different. In particular, we
want to allow the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but prevent the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a
different way of presenting the semantics that allows us to
distinguish nontermination from erroneous "stuck states."
So, for lots of reasons, we'd like to have a finer-grained way of
defining and reasoning about program behaviors. This is the topic
of the present chapter. We replace the "big-step" [eval] relation
with a "small-step" relation that specifies, for a given program,
how the "atomic steps" of computation are performed. *)
(* ########################################################### *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] -- for the
constructor names, for brevity.) At the end of the chapter, we'll
see how to apply the same techniques to the full Imp language. *)
Inductive tm : Type :=
| C : nat -> tm (* Constant *)
| P : tm -> tm -> tm. (* Plus *)
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P" ].
(** Here is a standard evaluator for this language, written in the
same (big-step) style as we've been using up to this point. *)
Fixpoint evalF (t : tm) : nat :=
match t with
| C n => n
| P a1 a2 => evalF a1 + evalF a2
end.
(** Now, here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation. Again,
we use the notation [t || n] for "[t] evaluates to [n]." *)
(**
-------- (E_Const)
C n || n
t1 || n1
t2 || n2
---------------------- (E_Plus)
P t1 t2 || C (n1 + n2)
*)
Reserved Notation " t '||' n " (at level 50, left associativity).
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n || n
| E_Plus : forall t1 t2 n1 n2,
t1 || n1 ->
t2 || n2 ->
P t1 t2 || (n1 + n2)
where " t '||' n " := (eval t n).
Tactic Notation "eval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Const" | Case_aux c "E_Plus" ].
Module SimpleArith1.
(** Now, here is a small-step version. *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
t2 ==> t2'
--------------------------- (ST_Plus2)
P (C n1) t2 ==> P (C n1) t2'
*)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 ==> t2' ->
P (C n1) t2 ==> P (C n1) t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** Let's pause and check a couple of examples of reasoning with
the [step] relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [P t1' t2]: *)
Example test_step_1 :
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>
P
(C (0 + 3))
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 1 star (test_step_2) *)
(** Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n)
t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>
P
(C 0)
(P
(C 2)
(C (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** * Relations *)
(** We will be using several different step relations, so it is
helpful to generalize a bit and state a few definitions and
theorems about relations in general. (The optional chapter
[Rel.v] develops some of these ideas in a bit more detail; it may
be useful if the treatment here is too dense.) *)
(** A (binary) _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Our main examples of such relations in this chapter will be
the single-step and multi-step reduction relations on terms, [==>]
and [==>*], but there are many other examples -- some that come to
mind are the "equals," "less than," "less than or equal to," and
"is the square of" relations on numbers, and the "prefix of"
relation on lists and strings. *)
(** One simple property of the [==>] relation is that, like the
evaluation relation for our language of Imp programs, it is
_deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t ==> t'] is provable). Formally, this is the
same as saying that [==>] is deterministic. *)
(** _Proof sketch_: We show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal, by induction on a derivation of
[step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and in the given derivation
of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] has both the form [P t1 t2] and
the form [C n]. [] *)
Definition deterministic {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2.
Case "ST_PlusConstConst". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". reflexivity.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2". inversion H2.
Case "ST_Plus1". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H0 in Hy1. inversion Hy1.
SCase "ST_Plus1".
rewrite <- (IHHy1 t1'0).
reflexivity. assumption.
SCase "ST_Plus2". rewrite <- H in Hy1. inversion Hy1.
Case "ST_Plus2". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H1 in Hy1. inversion Hy1.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2".
rewrite <- (IHHy1 t2'0).
reflexivity. assumption.
Qed.
(** There is some annoying repetition in this proof.
Each use of [inversion Hy2] results in three subcases,
only one of which is relevant (the one which matches the
current case in the induction on [Hy1]). The other two
subcases need to be dismissed by finding the contradiction
among the hypotheses and doing inversion on it.
There is a tactic called [solve by inversion] defined in [SfLib.v]
that can be of use in such cases. It will solve the goal if it
can be solved by inverting some hypothesis; otherwise, it fails.
(There are variants [solve by inversion 2] and [solve by inversion 3]
that work if two or three consecutive inversions will solve the goal.)
The example below shows how a proof of the previous theorem can be
simplified using this tactic.
*)
Theorem step_deterministic_alt: deterministic step.
Proof.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2;
inversion Hy2; subst; try (solve by inversion).
Case "ST_PlusConstConst". reflexivity.
Case "ST_Plus1".
apply IHHy1 in H2. rewrite H2. reflexivity.
Case "ST_Plus2".
apply IHHy1 in H2. rewrite H2. reflexivity.
Qed.
End SimpleArith1.
(* ########################################################### *)
(** ** Values *)
(** Let's take a moment to slightly generalize the way we state the
definition of single-step reduction. *)
(** It is useful to think of the [==>] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation.
- The _halting states_ of the machine are ones where there is no
more computation to be done.
*)
(**
We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [==>] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [==>] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
value v1
t2 ==> t2'
-------------------- (ST_Plus2)
P v1 t2 ==> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant. We'll keep it for now,
to maintain a close correspondence between the informal and Coq
versions of the rules, but later on we'll drop it in informal
rules, for the sake of brevity.) *)
(** Here are the formal rules: *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <----- n.b. *)
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** **** Exercise: 3 stars (redo_determinism) *)
(** As a sanity check on this change, let's re-verify determinism
Proof sketch: We must show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal. Consider the final rules used in
the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) AND one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] both has the form [P t1 t2] and
is a value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write it from
scratch and just use the earlier one if you get stuck. *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language is
fairly simple, but for a larger language it would be pretty easy
to forget one of the rules and create a situation where some term
cannot take a step even though it has not been completely reduced
to a value. The following theorem shows that we did not, in fact,
make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): If [t] is a term, then either [t]
is a value, or there exists a term [t'] such that [t ==> t']. *)
(** _Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a [value].
- Suppose [t = P t1 t2], where (by the IH) [t1] is either a
value or can step to some [t1'], and where [t2] is either a
value or can step to some [t2']. We must show [P t1 t2] is
either a value or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. [] *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
tm_cases (induction t) Case.
Case "C". left. apply v_const.
Case "P". right. inversion IHt1.
SCase "l". inversion IHt2.
SSCase "l". inversion H. inversion H0.
exists (C (n + n0)).
apply ST_PlusConstConst.
SSCase "r". inversion H0 as [t' H1].
exists (P t1 t').
apply ST_Plus2. apply H. apply H1.
SCase "r". inversion H as [t' H0].
exists (P t' t2).
apply ST_Plus1. apply H0. Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
simply "progress.") *)
(** The idea of "making progress" can be extended to tell us something
interesting about [value]s: in this language [value]s are exactly
the terms that _cannot_ make progress in this sense.
To state this observation formally, let's begin by giving a name
to terms that cannot make progress. We'll call them _normal
forms_. *)
Definition normal_form {X:Type} (R:relation X) (t:X) : Prop :=
~ exists t', R t t'.
(** This definition actually specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma value_is_nf : forall v,
value v -> normal_form step v.
Proof.
unfold normal_form. intros v H. inversion H.
intros contra. inversion contra. inversion H1.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t ==> t').
SCase "Proof of assertion". apply strong_progress.
inversion G.
SCase "l". apply H0.
SCase "r". apply ex_falso_quodlibet. apply H. assumption. Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf. Qed.
(** Why is this interesting?
Because [value] is a syntactic concept -- it is defined by looking
at the form of a term -- while [normal_form] is a semantic one --
it is defined by looking at how the term steps. It is not obvious
that these concepts should coincide!
Indeed, we could easily have written the definitions so that they
would not coincide... *)
(* ##################################################### *)
(** We might, for example, mistakenly define [value] so that it
includes some terms that are not finished reducing. *)
Module Temp1.
(* Open an inner module so we can redefine value and step. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2, (* <---- *)
value (P t1 (C n2)).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp1.
(* ##################################################### *)
(** Alternatively, we might mistakenly define [step] so that it
permits something designated as a value to reduce further. *)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n, (* <---- *)
C n ==> P (C n) (C 0)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 2 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp2.
(* ########################################################### *)
(** Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, even in a correct language definition, it makes
sense to allow some terms to be stuck. *)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
where " t '==>' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form') *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp3.
(* ########################################################### *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just plus and numbers, are just the booleans true and false and a
conditional expression... *)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** **** Exercise: 1 star (smallstep_bools) *)
(** Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
tfalse ==> tfalse.
(* FILL IN HERE *)
Definition bool_step_prop2 :=
tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>
ttrue.
(* FILL IN HERE *)
Definition bool_step_prop3 :=
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (progress_bool) *)
(** Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars (smallstep_bool_shortcut) *)
(** Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[ttrue] or [tfalse]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
(* FILL IN HERE *)
where " t '==>' t' " := (step t t').
Definition bool_step_prop4 :=
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (properties_of_altered_step) *)
(** It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
(* FILL IN HERE *)
*)
(** [] *)
End Temp5.
End Temp4.
(* ########################################################### *)
(** * Multi-Step Reduction *)
(** Until now, we've been working with the _single-step reduction_
relation [==>], which formalizes the individual steps of an
_abstract machine_ for executing programs.
We can also use this machine to reduce programs to completion --
to find out what final result they yield. This can be formalized
as follows:
- First, we define a _multi-step reduction relation_ [==>*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
of single reduction steps (including zero steps!).
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(* ########################################################### *)
(** Since we'll want to reuse the idea of multi-step reduction many
times in this and future chapters, let's take a little extra
trouble here and define it generically.
Given a relation [R], we define a relation [multi R], called the
_multi-step closure of [R]_ as follows: *)
Inductive multi {X:Type} (R: relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** The effect of this definition is that [multi R] relates two
elements [x] and [y] if either
- [x = y], or else
- there is some sequence [z1], [z2], ..., [zn]
such that
R x z1
R z1 z2
...
R zn y.
Thus, if [R] describes a single-step of computation, [z1],
... [zn] is the sequence of intermediate steps of computation
between [x] and [y].
*)
Tactic Notation "multi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "multi_refl" | Case_aux c "multi_step" ].
(** We write [==>*] for the [multi step] relation -- i.e., the
relation that relates two terms [t] and [t'] if we can get from
[t] to [t'] using the [step] relation zero or more times. *)
Notation " t '==>*' t' " := (multi step t t') (at level 40).
(** The relation [multi R] has several crucial properties.
First, it is obviously _reflexive_ (that is, [forall x, multi R x
x]). In the case of the [==>*] (i.e. [multi step]) relation, the
intuition is that a term can execute to itself by taking zero
steps of execution.
Second, it contains [R] -- that is, single-step executions are a
particular case of multi-step executions. (It is this fact that
justifies the word "closure" in the term "multi-step closure of
[R].") *)
Theorem multi_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl. Qed.
(** Third, [multi R] is _transitive_. *)
Theorem multi_trans :
forall (X:Type) (R: relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
multi_cases (induction G) Case.
Case "multi_refl". assumption.
Case "multi_step".
apply multi_step with y. assumption.
apply IHG. assumption. Qed.
(** That is, if [t1==>*t2] and [t2==>*t3], then [t1==>*t3]. *)
(* ########################################################### *)
(** ** Examples *)
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P
(C (0 + 3))
(P (C 2) (C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with
(P
(C (0 + 3))
(C (2 + 4))).
apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
apply multi_R.
apply ST_PlusConstConst. Qed.
(** Here's an alternate proof that uses [eapply] to avoid explicitly
constructing all the intermediate terms. *)
Lemma test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
eapply multi_step. apply ST_PlusConstConst.
apply multi_refl. Qed.
(** **** Exercise: 1 star, optional (test_multistep_2) *)
Lemma test_multistep_2:
C 3 ==>* C 3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (test_multistep_3) *)
Lemma test_multistep_3:
P (C 0) (C 3)
==>*
P (C 0) (C 3).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (test_multistep_4) *)
Lemma test_multistep_4:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t ==>* t' /\ step_normal_form t').
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, optional (normal_forms_unique) *)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
unfold deterministic. unfold normal_form_of. intros x y1 y2 P1 P2.
inversion P1 as [P11 P12]; clear P1. inversion P2 as [P21 P22]; clear P2.
generalize dependent y2.
(* We recommend using this initial setup as-is! *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X:Type} (R:relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the left-hand child of a [P] node, and
similarly when [t] appears as the right-hand child of a [P]
node whose left-hand child is a value. *)
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros t1 t1' t2 H. multi_cases (induction H) Case.
Case "multi_refl". apply multi_refl.
Case "multi_step". apply multi_step with (P y t2).
apply ST_Plus1. apply H.
apply IHmulti. Qed.
(** **** Exercise: 2 stars (multistep_congr_2) *)
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** _Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] steps to [t'] and [t'] is
a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step,
and we have [t' = t]. We can derive the left-hand side by
reflexivity and the right-hand side by observing (a) that values
are normal forms (by [nf_same_as_value]) and (b) that [t] is a
value (by [v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and
[t2] have normal forms [t1'] and [t2']. Recall that normal
forms are values (by [nf_same_as_value]); we know that [t1' =
C n1] and [t2' = C n2], for some [n1] and [n2].
We can combine the [==>*] derivations for [t1] and [t2] to prove
that [P t1 t2] reduces in many steps to [C (n1 + n2)].
It is clear that our choice of [t' = C (n1 + n2)] is a
value, which is in turn a normal form. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
tm_cases (induction t) Case.
Case "C".
exists (C n).
split.
SCase "l". apply multi_refl.
SCase "r".
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
Case "P".
inversion IHt1 as [t1' H1]; clear IHt1. inversion IHt2 as [t2' H2]; clear IHt2.
inversion H1 as [H11 H12]; clear H1. inversion H2 as [H21 H22]; clear H2.
rewrite nf_same_as_value in H12. rewrite nf_same_as_value in H22.
inversion H12 as [n1]. inversion H22 as [n2].
rewrite <- H in H11.
rewrite <- H0 in H21.
exists (C (n1 + n2)).
split.
SCase "l".
apply multi_trans with (P (C n1) t2).
apply multistep_congr_1. apply H11.
apply multi_trans with
(P (C n1) (C n2)).
apply multistep_congr_2. apply v_const. apply H21.
apply multi_R. apply ST_PlusConstConst.
SCase "r".
rewrite nf_same_as_value. apply v_const. Qed.
(* ########################################################### *)
(** ** Equivalence of Big-Step and Small-Step Reduction *)
(** Having defined the operational semantics of our tiny programming
language in two different styles, it makes sense to ask whether
these definitions actually define the same thing! They do, though
it takes a little work to show it. (The details are left as an
exercise). *)
(** **** Exercise: 3 stars (eval__multistep) *)
Theorem eval__multistep : forall t n,
t || n -> t ==>* C n.
(** The key idea behind the proof comes from the following picture:
P t1 t2 ==> (by ST_Plus1)
P t1' t2 ==> (by ST_Plus1)
P t1'' t2 ==> (by ST_Plus1)
...
P (C n1) t2 ==> (by ST_Plus2)
P (C n1) t2' ==> (by ST_Plus2)
P (C n1) t2'' ==> (by ST_Plus2)
...
P (C n1) (C n2) ==> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)]. *)
(** To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [==>*]: that it is reflexive, transitive, and
includes [==>]. *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (eval__multistep_inf) *)
(** Write a detailed informal version of the proof of [eval__multistep].
(* FILL IN HERE *)
[]
*)
(** For the other direction, we need one lemma, which establishes a
relation between single-step reduction and big-step evaluation. *)
(** **** Exercise: 3 stars (step__eval) *)
Lemma step__eval : forall t t' n,
t ==> t' ->
t' || n ->
t || n.
Proof.
intros t t' n Hs. generalize dependent n.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The fact that small-step reduction implies big-step is now
straightforward to prove, once it is stated correctly.
The proof proceeds by induction on the multi-step reduction
sequence that is buried in the hypothesis [normal_form_of t t']. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars (multistep__eval) *)
Theorem multistep__eval : forall t t',
normal_form_of t t' -> exists n, t' = C n /\ t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 3 stars, optional (interp_tm) *)
(** Remember that we also defined big-step evaluation of [tm]s as a
function [evalF]. Prove that it is equivalent to the existing
semantics.
Hint: we just proved that [eval] and [multistep] are
equivalent, so logically it doesn't matter which you choose.
One will be easier than the other, though! *)
Theorem evalF_eval : forall t n,
evalF t = n <-> t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (combined_properties) *)
(** We've considered the arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P"
| Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2"
| Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Prove or disprove these two properties for the combined language. *)
(* FILL IN HERE *)
(** [] *)
End Combined.
(* ########################################################### *)
(** * Small-Step Imp *)
(** For a more serious example, here is the small-step version of the
Imp operational semantics. *)
(** The small-step evaluation relations for arithmetic and boolean
expressions are straightforward extensions of the tiny language
we've been working up to now. To make them easier to read, we
introduce the symbolic notations [==>a] and [==>b], respectively,
for the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values, since they aren't needed in the definition of [==>b]
below (why?), though they might be if our language were a bit
larger (why?). *)
Reserved Notation " t '/' st '==>a' t' " (at level 40, st at level 39).
Inductive astep : state -> aexp -> aexp -> Prop :=
| AS_Id : forall st i,
AId i / st ==>a ANum (st i)
| AS_Plus : forall st n1 n2,
APlus (ANum n1) (ANum n2) / st ==>a ANum (n1 + n2)
| AS_Plus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(APlus a1 a2) / st ==>a (APlus a1' a2)
| AS_Plus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(APlus v1 a2) / st ==>a (APlus v1 a2')
| AS_Minus : forall st n1 n2,
(AMinus (ANum n1) (ANum n2)) / st ==>a (ANum (minus n1 n2))
| AS_Minus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMinus a1 a2) / st ==>a (AMinus a1' a2)
| AS_Minus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMinus v1 a2) / st ==>a (AMinus v1 a2')
| AS_Mult : forall st n1 n2,
(AMult (ANum n1) (ANum n2)) / st ==>a (ANum (mult n1 n2))
| AS_Mult1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMult (a1) (a2)) / st ==>a (AMult (a1') (a2))
| AS_Mult2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMult v1 a2) / st ==>a (AMult v1 a2')
where " t '/' st '==>a' t' " := (astep st t t').
Reserved Notation " t '/' st '==>b' t' " (at level 40, st at level 39).
Inductive bstep : state -> bexp -> bexp -> Prop :=
| BS_Eq : forall st n1 n2,
(BEq (ANum n1) (ANum n2)) / st ==>b
(if (beq_nat n1 n2) then BTrue else BFalse)
| BS_Eq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BEq a1 a2) / st ==>b (BEq a1' a2)
| BS_Eq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BEq v1 a2) / st ==>b (BEq v1 a2')
| BS_LtEq : forall st n1 n2,
(BLe (ANum n1) (ANum n2)) / st ==>b
(if (ble_nat n1 n2) then BTrue else BFalse)
| BS_LtEq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BLe a1 a2) / st ==>b (BLe a1' a2)
| BS_LtEq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BLe v1 a2) / st ==>b (BLe v1 (a2'))
| BS_NotTrue : forall st,
(BNot BTrue) / st ==>b BFalse
| BS_NotFalse : forall st,
(BNot BFalse) / st ==>b BTrue
| BS_NotStep : forall st b1 b1',
b1 / st ==>b b1' ->
(BNot b1) / st ==>b (BNot b1')
| BS_AndTrueTrue : forall st,
(BAnd BTrue BTrue) / st ==>b BTrue
| BS_AndTrueFalse : forall st,
(BAnd BTrue BFalse) / st ==>b BFalse
| BS_AndFalse : forall st b2,
(BAnd BFalse b2) / st ==>b BFalse
| BS_AndTrueStep : forall st b2 b2',
b2 / st ==>b b2' ->
(BAnd BTrue b2) / st ==>b (BAnd BTrue b2')
| BS_AndStep : forall st b1 b1' b2,
b1 / st ==>b b1' ->
(BAnd b1 b2) / st ==>b (BAnd b1' b2)
where " t '/' st '==>b' t' " := (bstep st t t').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [SKIP] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [SKIP] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [SKIP], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [WHILE] command by transforming it into a
conditional followed by the same [WHILE]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [WHILE]
command needs to be saved somewhere while a single copy of the loop
body is being evaluated.) *)
Reserved Notation " t '/' st '==>' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
IFB BTrue THEN c1 ELSE c2 FI / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
IFB BFalse THEN c1 ELSE c2 FI / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b / st ==>b b' ->
IFB b THEN c1 ELSE c2 FI / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
(* ########################################################### *)
(** * Concurrent Imp *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
(* New: *)
| CPar : com -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "PAR" ].
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' b 'THEN' c1 'ELSE' c2 'FI'" :=
(CIf b c1 c2) (at level 80, right associativity).
Notation "'PAR' c1 'WITH' c2 'END'" :=
(CPar c1 c2) (at level 80, right associativity).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
(IFB BTrue THEN c1 ELSE c2 FI) / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
(IFB BFalse THEN c1 ELSE c2 FI) / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b /st ==>b b' ->
(IFB b THEN c1 ELSE c2 FI) / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st ==>
(IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st ==> c1' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1' WITH c2 END) / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st ==> c2' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1 WITH c2' END) / st'
| CS_ParDone : forall st,
(PAR SKIP WITH SKIP END) / st ==> SKIP / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '==>*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value... *)
Definition par_loop : com :=
PAR
Y ::= ANum 1
WITH
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END
END.
(** In particular, it can terminate with [X] set to [0]: *)
Example par_loop_example_0:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st ==>* par_loop / (update st X (S n)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st ==>* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_state).
split; unfold update; reflexivity.
rename x into st.
inversion H as [H' [HX HY]]; clear H.
exists (update st Y 1). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite update_neq. assumption. intro X; inversion X.
Qed.
End CImp.
(* ########################################################### *)
(** * A Small-Step Stack Machine *)
(** Last example: a small-step semantics for the stack machine example
from Imp.v. *)
Definition stack := list nat.
Definition prog := list sinstr.
Inductive stack_step : state -> prog * stack -> prog * stack -> Prop :=
| SS_Push : forall st stk n p',
stack_step st (SPush n :: p', stk) (p', n :: stk)
| SS_Load : forall st stk i p',
stack_step st (SLoad i :: p', stk) (p', st i :: stk)
| SS_Plus : forall st stk n m p',
stack_step st (SPlus :: p', n::m::stk) (p', (m+n)::stk)
| SS_Minus : forall st stk n m p',
stack_step st (SMinus :: p', n::m::stk) (p', (m-n)::stk)
| SS_Mult : forall st stk n m p',
stack_step st (SMult :: p', n::m::stk) (p', (m*n)::stk).
Theorem stack_step_deterministic : forall st,
deterministic (stack_step st).
Proof.
unfold deterministic. intros st x y1 y2 H1 H2.
induction H1; inversion H2; reflexivity.
Qed.
Definition stack_multistep st := multi (stack_step st).
(** **** Exercise: 3 stars, advanced (compiler_is_correct) *)
(** Remember the definition of [compile] for [aexp] given in the
[Imp] chapter. We want now to prove [compile] correct with respect
to the stack machine.
State what it means for the compiler to be correct according to
the stack machine small step semantics and then prove it. *)
Definition compiler_is_correct_statement : Prop :=
(* FILL IN HERE *) admit.
Theorem compiler_is_correct : compiler_is_correct_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** $Date: 2014-12-31 15:16:58 -0500 (Wed, 31 Dec 2014) $ *)
|
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