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// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_channel_gate_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Captures transaction open/close events as well as data
// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
// CHNL_TX drops, the channel closes (until the next transaction -- signaled by
// CHNL_TX going up again).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTGATE64_IDLE 2'b00
`define S_TXPORTGATE64_OPENING 2'b01
`define S_TXPORTGATE64_OPEN 2'b10
`define S_TXPORTGATE64_CLOSED 2'b11
`timescale 1ns/1ns
module tx_port_channel_gate_64 #(
parameter C_DATA_WIDTH = 9'd64,
// Local parameters
parameter C_FIFO_DEPTH = 8,
parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1
)
(
input RST,
input RD_CLK, // FIFO read clock
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data
output RD_EMPTY, // FIFO is empty
input RD_EN, // FIFO read enable
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXPORTGATE64_IDLE, _rState=`S_TXPORTGATE64_IDLE;
reg rFifoWen=0, _rFifoWen=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0;
wire wFifoFull;
reg rChnlTx=0, _rChnlTx=0;
reg rChnlLast=0, _rChnlLast=0;
reg [31:0] rChnlLen=0, _rChnlLen=0;
reg [30:0] rChnlOff=0, _rChnlOff=0;
reg rAck=0, _rAck=0;
reg rPause=0, _rPause=0;
reg rClosed=0, _rClosed=0;
assign CHNL_TX_ACK = rAck;
assign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE64_OPEN
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CHNL_CLK) begin
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
rChnlLast <= #1 _rChnlLast;
rChnlLen <= #1 _rChnlLen;
rChnlOff <= #1 _rChnlOff;
end
always @ (*) begin
_rChnlTx = CHNL_TX;
_rChnlLast = CHNL_TX_LAST;
_rChnlLen = CHNL_TX_LEN;
_rChnlOff = CHNL_TX_OFF;
end
// FIFO for temporarily storing data from the channel.
(* RAM_STYLE="DISTRIBUTED" *)
async_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (
.WR_CLK(CHNL_CLK),
.WR_RST(RST),
.WR_EN(rFifoWen),
.WR_DATA(rFifoData),
.WR_FULL(wFifoFull),
.RD_CLK(RD_CLK),
.RD_RST(RST),
.RD_EN(RD_EN),
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY)
);
// Pass the transaction open event, transaction data, and the transaction
// close event through to the RD_CLK domain via the async_fifo.
always @ (posedge CHNL_CLK) begin
rState <= #1 (RST ? `S_TXPORTGATE64_IDLE : _rState);
rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
rFifoData <= #1 _rFifoData;
rAck <= #1 (RST ? 1'd0 : _rAck);
rPause <= #1 (RST ? 1'd0 : _rPause);
rClosed <= #1 (RST ? 1'd0 : _rClosed);
end
always @ (*) begin
_rState = rState;
_rFifoWen = rFifoWen;
_rFifoData = rFifoData;
_rPause = rPause;
_rAck = rAck;
_rClosed = rClosed;
case (rState)
`S_TXPORTGATE64_IDLE: begin // Write the len, off, last
_rPause = 0;
_rClosed = 0;
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoWen = rChnlTx;
_rFifoData = {1'd1, rChnlLen, rChnlOff, rChnlLast};
if (rChnlTx)
_rState = `S_TXPORTGATE64_OPENING;
end
end
`S_TXPORTGATE64_OPENING: begin // Write the len, off, last (again)
_rAck = 0;
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE64_CLOSED;
else
_rState = `S_TXPORTGATE64_OPEN;
end
end
`S_TXPORTGATE64_OPEN: begin // Copy channel data into the FIFO
if (!wFifoFull) begin
_rFifoWen = CHNL_TX_DATA_VALID; // CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
_rFifoData = {1'd0, CHNL_TX_DATA}; // but the VALID+REN model seem to make this difficult.
end
if (!rChnlTx)
_rState = `S_TXPORTGATE64_CLOSED;
end
`S_TXPORTGATE64_CLOSED: begin // Write the end marker (twice)
if (!wFifoFull) begin
_rPause = 1;
_rFifoWen = 1;
_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
if (rPause)
_rState = `S_TXPORTGATE64_IDLE;
end
end
endcase
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CHNL_CLK),
.CONTROL(wControl0),
.TRIG0({4'd0, wFifoFull, CHNL_TX, rState}),
.DATA({313'd0,
rChnlOff, // 31
rChnlLen, // 32
rChnlLast, // 1
rChnlTx, // 1
CHNL_TX_OFF, // 31
CHNL_TX_LEN, // 32
CHNL_TX_LAST, // 1
CHNL_TX, // 1
wFifoFull, // 1
rFifoData, // 65
rFifoWen, // 1
rState}) // 2
);
*/
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_channel_gate_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Captures transaction open/close events as well as data
// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
// CHNL_TX drops, the channel closes (until the next transaction -- signaled by
// CHNL_TX going up again).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTGATE64_IDLE 2'b00
`define S_TXPORTGATE64_OPENING 2'b01
`define S_TXPORTGATE64_OPEN 2'b10
`define S_TXPORTGATE64_CLOSED 2'b11
`timescale 1ns/1ns
module tx_port_channel_gate_64 #(
parameter C_DATA_WIDTH = 9'd64,
// Local parameters
parameter C_FIFO_DEPTH = 8,
parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1
)
(
input RST,
input RD_CLK, // FIFO read clock
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data
output RD_EMPTY, // FIFO is empty
input RD_EN, // FIFO read enable
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXPORTGATE64_IDLE, _rState=`S_TXPORTGATE64_IDLE;
reg rFifoWen=0, _rFifoWen=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0;
wire wFifoFull;
reg rChnlTx=0, _rChnlTx=0;
reg rChnlLast=0, _rChnlLast=0;
reg [31:0] rChnlLen=0, _rChnlLen=0;
reg [30:0] rChnlOff=0, _rChnlOff=0;
reg rAck=0, _rAck=0;
reg rPause=0, _rPause=0;
reg rClosed=0, _rClosed=0;
assign CHNL_TX_ACK = rAck;
assign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE64_OPEN
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CHNL_CLK) begin
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
rChnlLast <= #1 _rChnlLast;
rChnlLen <= #1 _rChnlLen;
rChnlOff <= #1 _rChnlOff;
end
always @ (*) begin
_rChnlTx = CHNL_TX;
_rChnlLast = CHNL_TX_LAST;
_rChnlLen = CHNL_TX_LEN;
_rChnlOff = CHNL_TX_OFF;
end
// FIFO for temporarily storing data from the channel.
(* RAM_STYLE="DISTRIBUTED" *)
async_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (
.WR_CLK(CHNL_CLK),
.WR_RST(RST),
.WR_EN(rFifoWen),
.WR_DATA(rFifoData),
.WR_FULL(wFifoFull),
.RD_CLK(RD_CLK),
.RD_RST(RST),
.RD_EN(RD_EN),
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY)
);
// Pass the transaction open event, transaction data, and the transaction
// close event through to the RD_CLK domain via the async_fifo.
always @ (posedge CHNL_CLK) begin
rState <= #1 (RST ? `S_TXPORTGATE64_IDLE : _rState);
rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
rFifoData <= #1 _rFifoData;
rAck <= #1 (RST ? 1'd0 : _rAck);
rPause <= #1 (RST ? 1'd0 : _rPause);
rClosed <= #1 (RST ? 1'd0 : _rClosed);
end
always @ (*) begin
_rState = rState;
_rFifoWen = rFifoWen;
_rFifoData = rFifoData;
_rPause = rPause;
_rAck = rAck;
_rClosed = rClosed;
case (rState)
`S_TXPORTGATE64_IDLE: begin // Write the len, off, last
_rPause = 0;
_rClosed = 0;
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoWen = rChnlTx;
_rFifoData = {1'd1, rChnlLen, rChnlOff, rChnlLast};
if (rChnlTx)
_rState = `S_TXPORTGATE64_OPENING;
end
end
`S_TXPORTGATE64_OPENING: begin // Write the len, off, last (again)
_rAck = 0;
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE64_CLOSED;
else
_rState = `S_TXPORTGATE64_OPEN;
end
end
`S_TXPORTGATE64_OPEN: begin // Copy channel data into the FIFO
if (!wFifoFull) begin
_rFifoWen = CHNL_TX_DATA_VALID; // CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
_rFifoData = {1'd0, CHNL_TX_DATA}; // but the VALID+REN model seem to make this difficult.
end
if (!rChnlTx)
_rState = `S_TXPORTGATE64_CLOSED;
end
`S_TXPORTGATE64_CLOSED: begin // Write the end marker (twice)
if (!wFifoFull) begin
_rPause = 1;
_rFifoWen = 1;
_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
if (rPause)
_rState = `S_TXPORTGATE64_IDLE;
end
end
endcase
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CHNL_CLK),
.CONTROL(wControl0),
.TRIG0({4'd0, wFifoFull, CHNL_TX, rState}),
.DATA({313'd0,
rChnlOff, // 31
rChnlLen, // 32
rChnlLast, // 1
rChnlTx, // 1
CHNL_TX_OFF, // 31
CHNL_TX_LEN, // 32
CHNL_TX_LAST, // 1
CHNL_TX, // 1
wFifoFull, // 1
rFifoData, // 65
rFifoWen, // 1
rState}) // 2
);
*/
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_channel_gate_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Captures transaction open/close events as well as data
// and passes it to the RD_CLK domain through the async_fifo. CHNL_TX_DATA_REN can
// only be high after CHNL_TX goes high and after the CHNL_TX_ACK pulse. When
// CHNL_TX drops, the channel closes (until the next transaction -- signaled by
// CHNL_TX going up again).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTGATE64_IDLE 2'b00
`define S_TXPORTGATE64_OPENING 2'b01
`define S_TXPORTGATE64_OPEN 2'b10
`define S_TXPORTGATE64_CLOSED 2'b11
`timescale 1ns/1ns
module tx_port_channel_gate_64 #(
parameter C_DATA_WIDTH = 9'd64,
// Local parameters
parameter C_FIFO_DEPTH = 8,
parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1
)
(
input RST,
input RD_CLK, // FIFO read clock
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data
output RD_EMPTY, // FIFO is empty
input RD_EN, // FIFO read enable
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXPORTGATE64_IDLE, _rState=`S_TXPORTGATE64_IDLE;
reg rFifoWen=0, _rFifoWen=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0;
wire wFifoFull;
reg rChnlTx=0, _rChnlTx=0;
reg rChnlLast=0, _rChnlLast=0;
reg [31:0] rChnlLen=0, _rChnlLen=0;
reg [30:0] rChnlOff=0, _rChnlOff=0;
reg rAck=0, _rAck=0;
reg rPause=0, _rPause=0;
reg rClosed=0, _rClosed=0;
assign CHNL_TX_ACK = rAck;
assign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE64_OPEN
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CHNL_CLK) begin
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
rChnlLast <= #1 _rChnlLast;
rChnlLen <= #1 _rChnlLen;
rChnlOff <= #1 _rChnlOff;
end
always @ (*) begin
_rChnlTx = CHNL_TX;
_rChnlLast = CHNL_TX_LAST;
_rChnlLen = CHNL_TX_LEN;
_rChnlOff = CHNL_TX_OFF;
end
// FIFO for temporarily storing data from the channel.
(* RAM_STYLE="DISTRIBUTED" *)
async_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (
.WR_CLK(CHNL_CLK),
.WR_RST(RST),
.WR_EN(rFifoWen),
.WR_DATA(rFifoData),
.WR_FULL(wFifoFull),
.RD_CLK(RD_CLK),
.RD_RST(RST),
.RD_EN(RD_EN),
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY)
);
// Pass the transaction open event, transaction data, and the transaction
// close event through to the RD_CLK domain via the async_fifo.
always @ (posedge CHNL_CLK) begin
rState <= #1 (RST ? `S_TXPORTGATE64_IDLE : _rState);
rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
rFifoData <= #1 _rFifoData;
rAck <= #1 (RST ? 1'd0 : _rAck);
rPause <= #1 (RST ? 1'd0 : _rPause);
rClosed <= #1 (RST ? 1'd0 : _rClosed);
end
always @ (*) begin
_rState = rState;
_rFifoWen = rFifoWen;
_rFifoData = rFifoData;
_rPause = rPause;
_rAck = rAck;
_rClosed = rClosed;
case (rState)
`S_TXPORTGATE64_IDLE: begin // Write the len, off, last
_rPause = 0;
_rClosed = 0;
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoWen = rChnlTx;
_rFifoData = {1'd1, rChnlLen, rChnlOff, rChnlLast};
if (rChnlTx)
_rState = `S_TXPORTGATE64_OPENING;
end
end
`S_TXPORTGATE64_OPENING: begin // Write the len, off, last (again)
_rAck = 0;
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE64_CLOSED;
else
_rState = `S_TXPORTGATE64_OPEN;
end
end
`S_TXPORTGATE64_OPEN: begin // Copy channel data into the FIFO
if (!wFifoFull) begin
_rFifoWen = CHNL_TX_DATA_VALID; // CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
_rFifoData = {1'd0, CHNL_TX_DATA}; // but the VALID+REN model seem to make this difficult.
end
if (!rChnlTx)
_rState = `S_TXPORTGATE64_CLOSED;
end
`S_TXPORTGATE64_CLOSED: begin // Write the end marker (twice)
if (!wFifoFull) begin
_rPause = 1;
_rFifoWen = 1;
_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
if (rPause)
_rState = `S_TXPORTGATE64_IDLE;
end
end
endcase
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CHNL_CLK),
.CONTROL(wControl0),
.TRIG0({4'd0, wFifoFull, CHNL_TX, rState}),
.DATA({313'd0,
rChnlOff, // 31
rChnlLen, // 32
rChnlLast, // 1
rChnlTx, // 1
CHNL_TX_OFF, // 31
CHNL_TX_LEN, // 32
CHNL_TX_LAST, // 1
CHNL_TX, // 1
wFifoFull, // 1
rFifoData, // 65
rFifoWen, // 1
rState}) // 2
);
*/
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: counter.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple up-counter. The maximum value is the largest expected
// value. The counter will not pass the SAT_VALUE. If the SAT_VALUE > MAX_VALUE,
// the counter will roll over and never stop. On RST_IN, the counter
// synchronously resets to the RST_VALUE
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module counter
#(parameter C_MAX_VALUE = 10,
parameter C_SAT_VALUE = 10,
parameter C_RST_VALUE = 0)
(
input CLK,
input RST_IN,
input ENABLE,
output [clog2s(C_MAX_VALUE+1)-1:0] VALUE
);
wire wEnable;
reg [clog2s(C_MAX_VALUE+1)-1:0] wCtrValue;
reg [clog2s(C_MAX_VALUE+1)-1:0] rCtrValue;
/* verilator lint_off WIDTH */
assign wEnable = ENABLE & (C_SAT_VALUE > rCtrValue);
/* verilator lint_on WIDTH */
assign VALUE = rCtrValue;
always @(posedge CLK) begin
if(RST_IN) begin
rCtrValue <= C_RST_VALUE[clog2s(C_MAX_VALUE+1)-1:0];
end else if(wEnable) begin
rCtrValue <= rCtrValue + 1;
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// InterChannelSyndromeBuffer.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: InterChannelSyndromeBuffer
// File Name: InterChannelSyndromeBuffer.v
//
// Version: v1.0.0
//
// Description: Syndrome buffer array
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module InterChannelSyndromeBuffer
#(
parameter Channel = 4,
parameter Multi = 2,
parameter GaloisFieldDegree = 12,
parameter Syndromes = 27
)
(
iClock ,
iReset ,
iErrorDetectionEnd ,
iDecodeNeeded ,
iSyndromes ,
oSharedKESReady ,
iKESAvailable ,
oExecuteKES ,
oErroredChunkNumber ,
oDataFowarding ,
oLastChunk ,
oSyndromes ,
oChannelSel
);
input iClock ;
input iReset ;
input [Channel*Multi - 1:0] iErrorDetectionEnd ;
input [Channel*Multi - 1:0] iDecodeNeeded ;
input [Channel*Multi*GaloisFieldDegree*Syndromes - 1:0] iSyndromes ;
output [Channel - 1:0] oSharedKESReady ;
input iKESAvailable ;
output oExecuteKES ;
output oErroredChunkNumber ;
output oDataFowarding ;
output oLastChunk ;
output [GaloisFieldDegree*Syndromes - 1:0] oSyndromes ;
output [3:0] oChannelSel ;
wire [Channel - 1:0] wKESAvailable ;
wire [3:0] wChannelSel ;
reg [3:0] rChannelSel ;
wire [1:0] wChannelNum ;
wire [Channel - 1:0] wExecuteKES ;
wire [Channel - 1:0] wErroredChunkNumber ;
wire [Channel - 1:0] wDataFowarding ;
wire [Channel - 1:0] wLastChunk ;
wire [Channel*GaloisFieldDegree*Syndromes - 1:0] wSyndromes ;
always @ (posedge iClock)
if (iReset)
rChannelSel <= 4'b0000;
else
rChannelSel <= wChannelSel;
genvar c;
generate
for (c = 0; c < Channel; c = c + 1)
d_SC_KES_buffer
#
(
.Multi(2),
.GF(12)
)
PageDecoderSyndromeBuffer
(
.i_clk (iClock),
.i_RESET (iReset),
.i_stop_dec (1'b0),
.i_kes_available (wChannelSel[c]),
.i_exe_buf (|iErrorDetectionEnd[ (c+1)*Multi - 1 : (c)*Multi ]),
.i_ELP_search_needed(iErrorDetectionEnd[ (c+1)*Multi - 1 : (c)*Multi] & iDecodeNeeded[ (c+1)*Multi - 1 : (c)*Multi ]),
.i_syndromes (iSyndromes[(c+1)*Multi*GaloisFieldDegree*Syndromes - 1 : (c)*Multi*GaloisFieldDegree*Syndromes ]),
.o_buf_available (oSharedKESReady[c]),
.o_exe_kes (wExecuteKES[c]),
.o_chunk_number (wErroredChunkNumber[c]),
.o_data_fowarding (wDataFowarding[c]),
.o_buf_sequence_end (wLastChunk[c]),
.o_syndromes (wSyndromes[ (c+1)*GaloisFieldDegree*Syndromes - 1: (c)*GaloisFieldDegree*Syndromes ])
);
endgenerate
ChannelArbiter
Inst_ChannelSelector
(
.iClock (iClock),
.iReset (iReset),
.iRequestChannel(~oSharedKESReady),
.iLastChunk (wLastChunk),
.oKESAvail (wChannelSel),
.oChannelNumber (wChannelNum),
.iKESAvail (iKESAvailable)
);
assign oChannelSel = rChannelSel;
assign oExecuteKES = (wChannelNum == 1) ? wExecuteKES[1] :
(wChannelNum == 2) ? wExecuteKES[2] :
(wChannelNum == 3) ? wExecuteKES[3] :
wExecuteKES[0] ;
assign oDataFowarding = (wChannelNum == 1) ? wDataFowarding[1] :
(wChannelNum == 2) ? wDataFowarding[2] :
(wChannelNum == 3) ? wDataFowarding[3] :
wDataFowarding[0] ;
assign oErroredChunkNumber = (wChannelNum == 1) ? wErroredChunkNumber[1] :
(wChannelNum == 2) ? wErroredChunkNumber[2] :
(wChannelNum == 3) ? wErroredChunkNumber[3] :
wErroredChunkNumber[0] ;
assign oLastChunk = (wChannelNum == 1) ? wLastChunk[1] :
(wChannelNum == 2) ? wLastChunk[2] :
(wChannelNum == 3) ? wLastChunk[3] :
wLastChunk[0] ;
assign oSyndromes = (wChannelNum == 1) ? wSyndromes[2*GaloisFieldDegree*Syndromes - 1: 1*GaloisFieldDegree*Syndromes] :
(wChannelNum == 2) ? wSyndromes[3*GaloisFieldDegree*Syndromes - 1: 2*GaloisFieldDegree*Syndromes] :
(wChannelNum == 3) ? wSyndromes[4*GaloisFieldDegree*Syndromes - 1: 3*GaloisFieldDegree*Syndromes] :
wSyndromes[GaloisFieldDegree*Syndromes - 1:0] ;
endmodule |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: txc_engine_ultrascale.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TXC Engine takes unformatted completions, formats
// these packets into AXI-style packets. These packets must meet max-request,
// max-payload, and payload termination requirements (see Read Completion
// Boundary). The TXC Engine does not check these requirements during operation,
// but may do so during simulation.
//
// This Engine is capable of operating at "line rate".
//
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "ultrascale.vh"
module txc_engine_ultrascale
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_PAYLOAD_DWORDS = 256)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_TXC_RST,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY
);
localparam C_VENDOR = "XILINX";
localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
localparam C_MAX_HDR_WIDTH = 128; // It's really 96... But it gets trimmed
localparam C_MAX_HDR_DWORDS = C_MAX_HDR_WIDTH/32;
localparam C_MAX_ALIGN_DWORDS = 0;
localparam C_MAX_NONPAY_DWORDS = C_MAX_HDR_DWORDS + C_MAX_ALIGN_DWORDS;
//
localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_FORMATTER_OUTPUT = 1;
localparam C_FORMATTER_DELAY = 1 + C_PIPELINE_FORMATTER_INPUT;
localparam C_RST_COUNT = 10;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire RST_OUT; // From txc_trans_inst of txc_translation_layer.v
// End of automatics
/*AUTOINPUT*/
///*AUTOOUTPUT*/
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
wire wTxDataReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxData;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
wire wTxDataStartFlag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataWordValid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataWordReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxcPkt;
wire wTxcPktEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktEndOffset;
wire wTxcPktStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktStartOffset;
wire wTxcPktValid;
wire wTxcPktReady;
wire wTransDoneRst;
wire wTransRstOut;
wire wDoneEngRst;
wire wRst;
wire [C_RST_COUNT:0] wShiftRegRst;
assign DONE_TXC_RST = wTransDoneRst & wDoneEngRst;
assign wRst = wShiftRegRst[C_RST_COUNT-3];
assign wDoneEngRst = ~wShiftRegRst[C_RST_COUNT];
shiftreg
#(// Parameters
.C_DEPTH (C_RST_COUNT),
.C_WIDTH (1),
.C_VALUE (1)
/*AUTOINSTPARAM*/)
rst_shiftreg
(// Outputs
.RD_DATA (wShiftRegRst),
// Inputs
.RST_IN (RST_BUS),
.WR_DATA (wTransRstOut),
/*AUTOINST*/
// Inputs
.CLK (CLK));
txc_formatter_ultrascale
#(// Parameters
.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH))
txc_formatter_inst
(// Outputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.TX_HDR_READY (wTxHdrReady),
.RST_IN (wRst),
/*AUTOINST*/
// Outputs
.TXC_META_READY (TXC_META_READY),
// Inputs
.CLK (CLK),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP));
tx_engine
#(.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
txc_engine_inst
(// Outputs
.TX_HDR_READY (wTxHdrReady),
.TX_DATA_READY (TXC_DATA_READY),
.TX_PKT (wTxcPkt[C_DATA_WIDTH-1:0]),
.TX_PKT_START_FLAG (wTxcPktStartFlag),
.TX_PKT_START_OFFSET (wTxcPktStartOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (wTxcPktEndFlag),
.TX_PKT_END_OFFSET (wTxcPktEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_VALID (wTxcPktValid),
// Inputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_DATA_VALID (TXC_DATA_VALID),
.TX_DATA (TXC_DATA[C_DATA_WIDTH-1:0]),
.TX_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TX_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TX_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_READY (wTxcPktReady),
.RST_IN (wRst),
/*AUTOINST*/
// Inputs
.CLK (CLK));
txc_translation_layer
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT))
txc_trans_inst
(// Outputs
.TXC_PKT_READY (wTxcPktReady),
.DONE_RST (wTransDoneRst),
.RST_OUT (wTransRstOut),
// Inputs
.TXC_PKT (wTxcPkt),
.TXC_PKT_VALID (wTxcPktValid),
.TXC_PKT_START_FLAG (wTxcPktStartFlag),
.TXC_PKT_START_OFFSET (wTxcPktStartOffset),
.TXC_PKT_END_FLAG (wTxcPktEndFlag),
.TXC_PKT_END_OFFSET (wTxcPktEndOffset),
/*AUTOINST*/
// Outputs
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
// Inputs
.CLK (CLK),
.RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY));
endmodule // txc_engine_ultrascale
module txc_formatter_ultrascale
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_MAX_HDR_WIDTH = `UPKT_TXC_MAXHDR_W
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXC
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
// Interface: TX HDR
output TX_HDR_VALID,
output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
output TX_HDR_NOPAYLOAD,
input TX_HDR_READY
);
wire [`UPKT_TXC_MAXHDR_W-1:0] wHdr;
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
// Generic Header Fields
// ATYPE Should be copied from the request parameters, but we only use 0
assign wHdr[`UPKT_TXC_ADDRLOW_R] = TXC_META_ADDR;
assign wHdr[`UPKT_TXC_RSVD0_R] = `UPKT_TXC_RSVD0_W'd0;
assign wHdr[`UPKT_TXC_ATYPE_R] = `UPKT_TXC_ATYPE_W'd0;
assign wHdr[`UPKT_TXC_RSVD1_R] = `UPKT_TXC_RSVD1_W'd0;
assign wHdr[`UPKT_TXC_BYTECNT_R] = {1'b0,TXC_META_BYTE_COUNT};
assign wHdr[`UPKT_TXC_LOCKED_R] = `UPKT_TXC_LOCKED_W'd0;
assign wHdr[`UPKT_TXC_RSVD2_R] = `UPKT_TXC_RSVD2_W'd0;
assign wHdr[`UPKT_TXC_LENGTH_R] = {1'b0, TXC_META_LENGTH};
assign wHdr[`UPKT_TXC_STATUS_R] = `UPKT_TXC_STATUS_W'd0;
assign wHdr[`UPKT_TXC_EP_R] = TXC_META_EP;
assign wHdr[`UPKT_TXC_RSVD3_R] = `UPKT_TXC_RSVD3_W'd0;
assign wHdr[`UPKT_TXC_REQID_R] = TXC_META_REQUESTER_ID;
assign wHdr[`UPKT_TXC_TAG_R] = TXC_META_TAG;
assign wHdr[`UPKT_TXC_CPLID_R] = CONFIG_COMPLETER_ID;
assign wHdr[`UPKT_TXC_CPLIDEN_R] = 1'b0;
assign wHdr[`UPKT_TXC_TC_R] = TXC_META_TC;
assign wHdr[`UPKT_TXC_ATTR_R] = TXC_META_ATTR;
assign wHdr[`UPKT_TXC_TD_R] = `UPKT_TXC_TD_W'd0;
assign wTxHdrNopayload = ~wTxType[`TRLS_TYPE_PAY_I];
assign wTxHdrNonpayLen = 3;
assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`UPKT_TXC_LENGTH_I +: `SIG_LEN_W];
assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_TYPE_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(
// Outputs
.WR_DATA_READY (TXC_META_READY),
.RD_DATA ({wTxHdr,wTxType}),
.RD_DATA_VALID (wTxHdrValid),
// Inputs
.WR_DATA ({32'b0,wHdr,TXC_META_TYPE}),
.WR_DATA_VALID (TXC_META_VALID),
.RD_DATA_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wTxHdrReady),
.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
.RD_DATA_VALID (TX_HDR_VALID),
// Inputs
.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
.WR_DATA_VALID (wTxHdrValid),
.RD_DATA_READY (TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
module txc_translation_layer
#(parameter C_PCI_DATA_WIDTH = 10'd128,
parameter C_PIPELINE_INPUT = 1)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
output RST_OUT,
// Interface: TXC Classic
output TXC_PKT_READY,
input [C_PCI_DATA_WIDTH-1:0] TXC_PKT,
input TXC_PKT_VALID,
input TXC_PKT_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_START_OFFSET,
input TXC_PKT_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_END_OFFSET,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER
);
localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0;
localparam C_OUTPUT_STAGES = 1;
localparam C_RST_COUNT = 10;
wire wTxcPktReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxcPkt;
wire wTxcPktValid;
wire wTxcPktStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktStartOffset;
wire wTxcPktEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktEndOffset;
wire wSAxisCcTReady;
wire wSAxisCcTValid;
wire wSAxisCcTLast;
wire [C_PCI_DATA_WIDTH-1:0] wSAxisCcTData;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wSAxisCcTKeep;
wire [`SIG_CC_TUSER_W-1:0] wSAxisCcTUser;
wire wRst;
wire wRstWaiting;
/*ASSIGN TXC -> CC*/
assign wTxcPktReady = wSAxisCcTReady;
assign wSAxisCcTValid = wTxcPktValid;
assign wSAxisCcTLast = wTxcPktEndFlag;
assign wSAxisCcTData = wTxcPkt;
// Do not enable parity bits, and no discontinues
assign S_AXIS_CC_TUSER = `SIG_CC_TUSER_W'd0;
assign RST_OUT = wRst;
// This reset controller assumes there is always an output stage
reset_controller
#(/*AUTOINSTPARAM*/
// Parameters
.C_RST_COUNT (C_RST_COUNT))
rc
(// Outputs
.RST_OUT (wRst),
.WAITING_RESET (wRstWaiting),
// Inputs
.RST_IN (RST_BUS),
.SIGNAL_RST (RST_LOGIC),
.WAIT_RST (S_AXIS_CC_TVALID),
.NEXT_CYC_RST (S_AXIS_CC_TREADY & S_AXIS_CC_TLAST),
/*AUTOINST*/
// Outputs
.DONE_RST (DONE_RST),
// Inputs
.CLK (CLK));
pipeline
#(// Parameters
.C_DEPTH (C_INPUT_STAGES),
.C_WIDTH (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(// Outputs
.WR_DATA_READY (TXC_PKT_READY),
.RD_DATA ({wTxcPkt,wTxcPktStartFlag,wTxcPktStartOffset,wTxcPktEndFlag,wTxcPktEndOffset}),
.RD_DATA_VALID (wTxcPktValid),
// Inputs
.WR_DATA ({TXC_PKT,TXC_PKT_START_FLAG,TXC_PKT_START_OFFSET,
TXC_PKT_END_FLAG,TXC_PKT_END_OFFSET}),
.WR_DATA_VALID (TXC_PKT_VALID),
.RD_DATA_READY (wTxcPktReady),
.RST_IN (wRst),
/*AUTOINST*/
// Inputs
.CLK (CLK));
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
otom_inst
(// Outputs
.MASK (wSAxisCcTKeep),
// Inputs
.OFFSET_ENABLE (wTxcPktEndFlag),
.OFFSET (wTxcPktEndOffset)
/*AUTOINST*/);
pipeline
#(// Parameters
.C_DEPTH (C_OUTPUT_STAGES),
.C_WIDTH (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wSAxisCcTReady),
.RD_DATA ({S_AXIS_CC_TDATA,S_AXIS_CC_TLAST,S_AXIS_CC_TKEEP}),
.RD_DATA_VALID (S_AXIS_CC_TVALID),
// Inputs
.WR_DATA ({wSAxisCcTData,wSAxisCcTLast,wSAxisCcTKeep}),
.WR_DATA_VALID (wSAxisCcTValid & ~wRstWaiting),
.RD_DATA_READY (S_AXIS_CC_TREADY),
.RST_IN (wRst),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/" "../../common/")
// End:
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: txc_engine_ultrascale.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TXC Engine takes unformatted completions, formats
// these packets into AXI-style packets. These packets must meet max-request,
// max-payload, and payload termination requirements (see Read Completion
// Boundary). The TXC Engine does not check these requirements during operation,
// but may do so during simulation.
//
// This Engine is capable of operating at "line rate".
//
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "ultrascale.vh"
module txc_engine_ultrascale
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_PAYLOAD_DWORDS = 256)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_TXC_RST,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY
);
localparam C_VENDOR = "XILINX";
localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
localparam C_MAX_HDR_WIDTH = 128; // It's really 96... But it gets trimmed
localparam C_MAX_HDR_DWORDS = C_MAX_HDR_WIDTH/32;
localparam C_MAX_ALIGN_DWORDS = 0;
localparam C_MAX_NONPAY_DWORDS = C_MAX_HDR_DWORDS + C_MAX_ALIGN_DWORDS;
//
localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_FORMATTER_OUTPUT = 1;
localparam C_FORMATTER_DELAY = 1 + C_PIPELINE_FORMATTER_INPUT;
localparam C_RST_COUNT = 10;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire RST_OUT; // From txc_trans_inst of txc_translation_layer.v
// End of automatics
/*AUTOINPUT*/
///*AUTOOUTPUT*/
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
wire wTxDataReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxData;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
wire wTxDataStartFlag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataWordValid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataWordReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxcPkt;
wire wTxcPktEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktEndOffset;
wire wTxcPktStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktStartOffset;
wire wTxcPktValid;
wire wTxcPktReady;
wire wTransDoneRst;
wire wTransRstOut;
wire wDoneEngRst;
wire wRst;
wire [C_RST_COUNT:0] wShiftRegRst;
assign DONE_TXC_RST = wTransDoneRst & wDoneEngRst;
assign wRst = wShiftRegRst[C_RST_COUNT-3];
assign wDoneEngRst = ~wShiftRegRst[C_RST_COUNT];
shiftreg
#(// Parameters
.C_DEPTH (C_RST_COUNT),
.C_WIDTH (1),
.C_VALUE (1)
/*AUTOINSTPARAM*/)
rst_shiftreg
(// Outputs
.RD_DATA (wShiftRegRst),
// Inputs
.RST_IN (RST_BUS),
.WR_DATA (wTransRstOut),
/*AUTOINST*/
// Inputs
.CLK (CLK));
txc_formatter_ultrascale
#(// Parameters
.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH))
txc_formatter_inst
(// Outputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.TX_HDR_READY (wTxHdrReady),
.RST_IN (wRst),
/*AUTOINST*/
// Outputs
.TXC_META_READY (TXC_META_READY),
// Inputs
.CLK (CLK),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP));
tx_engine
#(.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
txc_engine_inst
(// Outputs
.TX_HDR_READY (wTxHdrReady),
.TX_DATA_READY (TXC_DATA_READY),
.TX_PKT (wTxcPkt[C_DATA_WIDTH-1:0]),
.TX_PKT_START_FLAG (wTxcPktStartFlag),
.TX_PKT_START_OFFSET (wTxcPktStartOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (wTxcPktEndFlag),
.TX_PKT_END_OFFSET (wTxcPktEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_VALID (wTxcPktValid),
// Inputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_DATA_VALID (TXC_DATA_VALID),
.TX_DATA (TXC_DATA[C_DATA_WIDTH-1:0]),
.TX_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TX_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TX_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_READY (wTxcPktReady),
.RST_IN (wRst),
/*AUTOINST*/
// Inputs
.CLK (CLK));
txc_translation_layer
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT))
txc_trans_inst
(// Outputs
.TXC_PKT_READY (wTxcPktReady),
.DONE_RST (wTransDoneRst),
.RST_OUT (wTransRstOut),
// Inputs
.TXC_PKT (wTxcPkt),
.TXC_PKT_VALID (wTxcPktValid),
.TXC_PKT_START_FLAG (wTxcPktStartFlag),
.TXC_PKT_START_OFFSET (wTxcPktStartOffset),
.TXC_PKT_END_FLAG (wTxcPktEndFlag),
.TXC_PKT_END_OFFSET (wTxcPktEndOffset),
/*AUTOINST*/
// Outputs
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
// Inputs
.CLK (CLK),
.RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY));
endmodule // txc_engine_ultrascale
module txc_formatter_ultrascale
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_MAX_HDR_WIDTH = `UPKT_TXC_MAXHDR_W
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXC
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
// Interface: TX HDR
output TX_HDR_VALID,
output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
output TX_HDR_NOPAYLOAD,
input TX_HDR_READY
);
wire [`UPKT_TXC_MAXHDR_W-1:0] wHdr;
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
// Generic Header Fields
// ATYPE Should be copied from the request parameters, but we only use 0
assign wHdr[`UPKT_TXC_ADDRLOW_R] = TXC_META_ADDR;
assign wHdr[`UPKT_TXC_RSVD0_R] = `UPKT_TXC_RSVD0_W'd0;
assign wHdr[`UPKT_TXC_ATYPE_R] = `UPKT_TXC_ATYPE_W'd0;
assign wHdr[`UPKT_TXC_RSVD1_R] = `UPKT_TXC_RSVD1_W'd0;
assign wHdr[`UPKT_TXC_BYTECNT_R] = {1'b0,TXC_META_BYTE_COUNT};
assign wHdr[`UPKT_TXC_LOCKED_R] = `UPKT_TXC_LOCKED_W'd0;
assign wHdr[`UPKT_TXC_RSVD2_R] = `UPKT_TXC_RSVD2_W'd0;
assign wHdr[`UPKT_TXC_LENGTH_R] = {1'b0, TXC_META_LENGTH};
assign wHdr[`UPKT_TXC_STATUS_R] = `UPKT_TXC_STATUS_W'd0;
assign wHdr[`UPKT_TXC_EP_R] = TXC_META_EP;
assign wHdr[`UPKT_TXC_RSVD3_R] = `UPKT_TXC_RSVD3_W'd0;
assign wHdr[`UPKT_TXC_REQID_R] = TXC_META_REQUESTER_ID;
assign wHdr[`UPKT_TXC_TAG_R] = TXC_META_TAG;
assign wHdr[`UPKT_TXC_CPLID_R] = CONFIG_COMPLETER_ID;
assign wHdr[`UPKT_TXC_CPLIDEN_R] = 1'b0;
assign wHdr[`UPKT_TXC_TC_R] = TXC_META_TC;
assign wHdr[`UPKT_TXC_ATTR_R] = TXC_META_ATTR;
assign wHdr[`UPKT_TXC_TD_R] = `UPKT_TXC_TD_W'd0;
assign wTxHdrNopayload = ~wTxType[`TRLS_TYPE_PAY_I];
assign wTxHdrNonpayLen = 3;
assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`UPKT_TXC_LENGTH_I +: `SIG_LEN_W];
assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_TYPE_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(
// Outputs
.WR_DATA_READY (TXC_META_READY),
.RD_DATA ({wTxHdr,wTxType}),
.RD_DATA_VALID (wTxHdrValid),
// Inputs
.WR_DATA ({32'b0,wHdr,TXC_META_TYPE}),
.WR_DATA_VALID (TXC_META_VALID),
.RD_DATA_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wTxHdrReady),
.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
.RD_DATA_VALID (TX_HDR_VALID),
// Inputs
.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
.WR_DATA_VALID (wTxHdrValid),
.RD_DATA_READY (TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
module txc_translation_layer
#(parameter C_PCI_DATA_WIDTH = 10'd128,
parameter C_PIPELINE_INPUT = 1)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
output RST_OUT,
// Interface: TXC Classic
output TXC_PKT_READY,
input [C_PCI_DATA_WIDTH-1:0] TXC_PKT,
input TXC_PKT_VALID,
input TXC_PKT_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_START_OFFSET,
input TXC_PKT_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_END_OFFSET,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER
);
localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0;
localparam C_OUTPUT_STAGES = 1;
localparam C_RST_COUNT = 10;
wire wTxcPktReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxcPkt;
wire wTxcPktValid;
wire wTxcPktStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktStartOffset;
wire wTxcPktEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktEndOffset;
wire wSAxisCcTReady;
wire wSAxisCcTValid;
wire wSAxisCcTLast;
wire [C_PCI_DATA_WIDTH-1:0] wSAxisCcTData;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wSAxisCcTKeep;
wire [`SIG_CC_TUSER_W-1:0] wSAxisCcTUser;
wire wRst;
wire wRstWaiting;
/*ASSIGN TXC -> CC*/
assign wTxcPktReady = wSAxisCcTReady;
assign wSAxisCcTValid = wTxcPktValid;
assign wSAxisCcTLast = wTxcPktEndFlag;
assign wSAxisCcTData = wTxcPkt;
// Do not enable parity bits, and no discontinues
assign S_AXIS_CC_TUSER = `SIG_CC_TUSER_W'd0;
assign RST_OUT = wRst;
// This reset controller assumes there is always an output stage
reset_controller
#(/*AUTOINSTPARAM*/
// Parameters
.C_RST_COUNT (C_RST_COUNT))
rc
(// Outputs
.RST_OUT (wRst),
.WAITING_RESET (wRstWaiting),
// Inputs
.RST_IN (RST_BUS),
.SIGNAL_RST (RST_LOGIC),
.WAIT_RST (S_AXIS_CC_TVALID),
.NEXT_CYC_RST (S_AXIS_CC_TREADY & S_AXIS_CC_TLAST),
/*AUTOINST*/
// Outputs
.DONE_RST (DONE_RST),
// Inputs
.CLK (CLK));
pipeline
#(// Parameters
.C_DEPTH (C_INPUT_STAGES),
.C_WIDTH (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(// Outputs
.WR_DATA_READY (TXC_PKT_READY),
.RD_DATA ({wTxcPkt,wTxcPktStartFlag,wTxcPktStartOffset,wTxcPktEndFlag,wTxcPktEndOffset}),
.RD_DATA_VALID (wTxcPktValid),
// Inputs
.WR_DATA ({TXC_PKT,TXC_PKT_START_FLAG,TXC_PKT_START_OFFSET,
TXC_PKT_END_FLAG,TXC_PKT_END_OFFSET}),
.WR_DATA_VALID (TXC_PKT_VALID),
.RD_DATA_READY (wTxcPktReady),
.RST_IN (wRst),
/*AUTOINST*/
// Inputs
.CLK (CLK));
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
otom_inst
(// Outputs
.MASK (wSAxisCcTKeep),
// Inputs
.OFFSET_ENABLE (wTxcPktEndFlag),
.OFFSET (wTxcPktEndOffset)
/*AUTOINST*/);
pipeline
#(// Parameters
.C_DEPTH (C_OUTPUT_STAGES),
.C_WIDTH (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wSAxisCcTReady),
.RD_DATA ({S_AXIS_CC_TDATA,S_AXIS_CC_TLAST,S_AXIS_CC_TKEEP}),
.RD_DATA_VALID (S_AXIS_CC_TVALID),
// Inputs
.WR_DATA ({wSAxisCcTData,wSAxisCcTLast,wSAxisCcTKeep}),
.WR_DATA_VALID (wSAxisCcTValid & ~wRstWaiting),
.RD_DATA_READY (S_AXIS_CC_TREADY),
.RST_IN (wRst),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/" "../../common/")
// End:
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: txc_engine_ultrascale.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TXC Engine takes unformatted completions, formats
// these packets into AXI-style packets. These packets must meet max-request,
// max-payload, and payload termination requirements (see Read Completion
// Boundary). The TXC Engine does not check these requirements during operation,
// but may do so during simulation.
//
// This Engine is capable of operating at "line rate".
//
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "ultrascale.vh"
module txc_engine_ultrascale
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_PAYLOAD_DWORDS = 256)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_TXC_RST,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY
);
localparam C_VENDOR = "XILINX";
localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
localparam C_MAX_HDR_WIDTH = 128; // It's really 96... But it gets trimmed
localparam C_MAX_HDR_DWORDS = C_MAX_HDR_WIDTH/32;
localparam C_MAX_ALIGN_DWORDS = 0;
localparam C_MAX_NONPAY_DWORDS = C_MAX_HDR_DWORDS + C_MAX_ALIGN_DWORDS;
//
localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_FORMATTER_OUTPUT = 1;
localparam C_FORMATTER_DELAY = 1 + C_PIPELINE_FORMATTER_INPUT;
localparam C_RST_COUNT = 10;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire RST_OUT; // From txc_trans_inst of txc_translation_layer.v
// End of automatics
/*AUTOINPUT*/
///*AUTOOUTPUT*/
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
wire wTxDataReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxData;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
wire wTxDataStartFlag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataWordValid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataWordReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxcPkt;
wire wTxcPktEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktEndOffset;
wire wTxcPktStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktStartOffset;
wire wTxcPktValid;
wire wTxcPktReady;
wire wTransDoneRst;
wire wTransRstOut;
wire wDoneEngRst;
wire wRst;
wire [C_RST_COUNT:0] wShiftRegRst;
assign DONE_TXC_RST = wTransDoneRst & wDoneEngRst;
assign wRst = wShiftRegRst[C_RST_COUNT-3];
assign wDoneEngRst = ~wShiftRegRst[C_RST_COUNT];
shiftreg
#(// Parameters
.C_DEPTH (C_RST_COUNT),
.C_WIDTH (1),
.C_VALUE (1)
/*AUTOINSTPARAM*/)
rst_shiftreg
(// Outputs
.RD_DATA (wShiftRegRst),
// Inputs
.RST_IN (RST_BUS),
.WR_DATA (wTransRstOut),
/*AUTOINST*/
// Inputs
.CLK (CLK));
txc_formatter_ultrascale
#(// Parameters
.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH))
txc_formatter_inst
(// Outputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.TX_HDR_READY (wTxHdrReady),
.RST_IN (wRst),
/*AUTOINST*/
// Outputs
.TXC_META_READY (TXC_META_READY),
// Inputs
.CLK (CLK),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP));
tx_engine
#(.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
txc_engine_inst
(// Outputs
.TX_HDR_READY (wTxHdrReady),
.TX_DATA_READY (TXC_DATA_READY),
.TX_PKT (wTxcPkt[C_DATA_WIDTH-1:0]),
.TX_PKT_START_FLAG (wTxcPktStartFlag),
.TX_PKT_START_OFFSET (wTxcPktStartOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (wTxcPktEndFlag),
.TX_PKT_END_OFFSET (wTxcPktEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_VALID (wTxcPktValid),
// Inputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_DATA_VALID (TXC_DATA_VALID),
.TX_DATA (TXC_DATA[C_DATA_WIDTH-1:0]),
.TX_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TX_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TX_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_READY (wTxcPktReady),
.RST_IN (wRst),
/*AUTOINST*/
// Inputs
.CLK (CLK));
txc_translation_layer
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT))
txc_trans_inst
(// Outputs
.TXC_PKT_READY (wTxcPktReady),
.DONE_RST (wTransDoneRst),
.RST_OUT (wTransRstOut),
// Inputs
.TXC_PKT (wTxcPkt),
.TXC_PKT_VALID (wTxcPktValid),
.TXC_PKT_START_FLAG (wTxcPktStartFlag),
.TXC_PKT_START_OFFSET (wTxcPktStartOffset),
.TXC_PKT_END_FLAG (wTxcPktEndFlag),
.TXC_PKT_END_OFFSET (wTxcPktEndOffset),
/*AUTOINST*/
// Outputs
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
// Inputs
.CLK (CLK),
.RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY));
endmodule // txc_engine_ultrascale
module txc_formatter_ultrascale
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_MAX_HDR_WIDTH = `UPKT_TXC_MAXHDR_W
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXC
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
// Interface: TX HDR
output TX_HDR_VALID,
output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
output TX_HDR_NOPAYLOAD,
input TX_HDR_READY
);
wire [`UPKT_TXC_MAXHDR_W-1:0] wHdr;
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
// Generic Header Fields
// ATYPE Should be copied from the request parameters, but we only use 0
assign wHdr[`UPKT_TXC_ADDRLOW_R] = TXC_META_ADDR;
assign wHdr[`UPKT_TXC_RSVD0_R] = `UPKT_TXC_RSVD0_W'd0;
assign wHdr[`UPKT_TXC_ATYPE_R] = `UPKT_TXC_ATYPE_W'd0;
assign wHdr[`UPKT_TXC_RSVD1_R] = `UPKT_TXC_RSVD1_W'd0;
assign wHdr[`UPKT_TXC_BYTECNT_R] = {1'b0,TXC_META_BYTE_COUNT};
assign wHdr[`UPKT_TXC_LOCKED_R] = `UPKT_TXC_LOCKED_W'd0;
assign wHdr[`UPKT_TXC_RSVD2_R] = `UPKT_TXC_RSVD2_W'd0;
assign wHdr[`UPKT_TXC_LENGTH_R] = {1'b0, TXC_META_LENGTH};
assign wHdr[`UPKT_TXC_STATUS_R] = `UPKT_TXC_STATUS_W'd0;
assign wHdr[`UPKT_TXC_EP_R] = TXC_META_EP;
assign wHdr[`UPKT_TXC_RSVD3_R] = `UPKT_TXC_RSVD3_W'd0;
assign wHdr[`UPKT_TXC_REQID_R] = TXC_META_REQUESTER_ID;
assign wHdr[`UPKT_TXC_TAG_R] = TXC_META_TAG;
assign wHdr[`UPKT_TXC_CPLID_R] = CONFIG_COMPLETER_ID;
assign wHdr[`UPKT_TXC_CPLIDEN_R] = 1'b0;
assign wHdr[`UPKT_TXC_TC_R] = TXC_META_TC;
assign wHdr[`UPKT_TXC_ATTR_R] = TXC_META_ATTR;
assign wHdr[`UPKT_TXC_TD_R] = `UPKT_TXC_TD_W'd0;
assign wTxHdrNopayload = ~wTxType[`TRLS_TYPE_PAY_I];
assign wTxHdrNonpayLen = 3;
assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`UPKT_TXC_LENGTH_I +: `SIG_LEN_W];
assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_TYPE_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(
// Outputs
.WR_DATA_READY (TXC_META_READY),
.RD_DATA ({wTxHdr,wTxType}),
.RD_DATA_VALID (wTxHdrValid),
// Inputs
.WR_DATA ({32'b0,wHdr,TXC_META_TYPE}),
.WR_DATA_VALID (TXC_META_VALID),
.RD_DATA_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wTxHdrReady),
.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
.RD_DATA_VALID (TX_HDR_VALID),
// Inputs
.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
.WR_DATA_VALID (wTxHdrValid),
.RD_DATA_READY (TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
module txc_translation_layer
#(parameter C_PCI_DATA_WIDTH = 10'd128,
parameter C_PIPELINE_INPUT = 1)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
output RST_OUT,
// Interface: TXC Classic
output TXC_PKT_READY,
input [C_PCI_DATA_WIDTH-1:0] TXC_PKT,
input TXC_PKT_VALID,
input TXC_PKT_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_START_OFFSET,
input TXC_PKT_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_END_OFFSET,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER
);
localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0;
localparam C_OUTPUT_STAGES = 1;
localparam C_RST_COUNT = 10;
wire wTxcPktReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxcPkt;
wire wTxcPktValid;
wire wTxcPktStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktStartOffset;
wire wTxcPktEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktEndOffset;
wire wSAxisCcTReady;
wire wSAxisCcTValid;
wire wSAxisCcTLast;
wire [C_PCI_DATA_WIDTH-1:0] wSAxisCcTData;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wSAxisCcTKeep;
wire [`SIG_CC_TUSER_W-1:0] wSAxisCcTUser;
wire wRst;
wire wRstWaiting;
/*ASSIGN TXC -> CC*/
assign wTxcPktReady = wSAxisCcTReady;
assign wSAxisCcTValid = wTxcPktValid;
assign wSAxisCcTLast = wTxcPktEndFlag;
assign wSAxisCcTData = wTxcPkt;
// Do not enable parity bits, and no discontinues
assign S_AXIS_CC_TUSER = `SIG_CC_TUSER_W'd0;
assign RST_OUT = wRst;
// This reset controller assumes there is always an output stage
reset_controller
#(/*AUTOINSTPARAM*/
// Parameters
.C_RST_COUNT (C_RST_COUNT))
rc
(// Outputs
.RST_OUT (wRst),
.WAITING_RESET (wRstWaiting),
// Inputs
.RST_IN (RST_BUS),
.SIGNAL_RST (RST_LOGIC),
.WAIT_RST (S_AXIS_CC_TVALID),
.NEXT_CYC_RST (S_AXIS_CC_TREADY & S_AXIS_CC_TLAST),
/*AUTOINST*/
// Outputs
.DONE_RST (DONE_RST),
// Inputs
.CLK (CLK));
pipeline
#(// Parameters
.C_DEPTH (C_INPUT_STAGES),
.C_WIDTH (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(// Outputs
.WR_DATA_READY (TXC_PKT_READY),
.RD_DATA ({wTxcPkt,wTxcPktStartFlag,wTxcPktStartOffset,wTxcPktEndFlag,wTxcPktEndOffset}),
.RD_DATA_VALID (wTxcPktValid),
// Inputs
.WR_DATA ({TXC_PKT,TXC_PKT_START_FLAG,TXC_PKT_START_OFFSET,
TXC_PKT_END_FLAG,TXC_PKT_END_OFFSET}),
.WR_DATA_VALID (TXC_PKT_VALID),
.RD_DATA_READY (wTxcPktReady),
.RST_IN (wRst),
/*AUTOINST*/
// Inputs
.CLK (CLK));
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
otom_inst
(// Outputs
.MASK (wSAxisCcTKeep),
// Inputs
.OFFSET_ENABLE (wTxcPktEndFlag),
.OFFSET (wTxcPktEndOffset)
/*AUTOINST*/);
pipeline
#(// Parameters
.C_DEPTH (C_OUTPUT_STAGES),
.C_WIDTH (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wSAxisCcTReady),
.RD_DATA ({S_AXIS_CC_TDATA,S_AXIS_CC_TLAST,S_AXIS_CC_TKEEP}),
.RD_DATA_VALID (S_AXIS_CC_TVALID),
// Inputs
.WR_DATA ({wSAxisCcTData,wSAxisCcTLast,wSAxisCcTKeep}),
.WR_DATA_VALID (wSAxisCcTValid & ~wRstWaiting),
.RD_DATA_READY (S_AXIS_CC_TREADY),
.RST_IN (wRst),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/" "../../common/")
// End:
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:13:28 07/01/2012
// Design Name:
// Module Name: Counter_8253
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Counter(input clk,
input rst,
input clk0,
input clk1,
input clk2,
input counter_we,
input [31:0] counter_val,
input [1:0] counter_ch, //Counter channel set
output counter0_OUT,
output counter1_OUT,
output counter2_OUT,
output [31:0] counter_out
);
reg [32:0] counter0,counter1,counter2;
reg [31:0] counter0_Lock,counter1_Lock,counter2_Lock;
reg [23:0] counter_Ctrl;
reg sq0,sq1,sq2,M0,M1,M2,clr0,clr1,clr2;
//Counter read or write & set counter_ch=SC1 SC0; counter_Ctrl=XX M2 M1 M0 X
always @ (posedge clk or posedge rst) begin
if (rst )
begin counter0_Lock <=0;counter1_Lock <=0;counter2_Lock <=0;counter_Ctrl<=0; end
else
if (counter_we) begin
case(counter_ch)
2'h0: begin counter0_Lock <= counter_val; M0<=1; end //f0000000: bit1 bit0 =00
2'h1: begin counter1_Lock <= counter_val; M1<=1; end //f0000000: bit1 bit0 =01
2'h2: begin counter2_Lock <= counter_val; M2<=1; end //f0000000: bit1 bit0 =10
2'h3: begin counter_Ctrl <= counter_val[23:0]; end //counter_Ctrl=XX M2 M1 M0 X
endcase
end
else begin counter0_Lock <=counter0_Lock;
counter1_Lock <=counter1_Lock;
counter2_Lock <=counter2_Lock;
counter_Ctrl<=counter_Ctrl;
if(clr0) M0<=0;
if(clr1) M1<=0;
if(clr2) M2<=0;
end
end
// Counter channel 0
always @ (posedge clk0 or posedge rst) begin
if (rst )
begin counter0<=0; sq0<=0; end
else
case(counter_Ctrl[2:1])
2'b00: begin if (M0) begin counter0 <= {1'b0,counter0_Lock}; clr0<=1; end
else if (counter0[32]==0)begin counter0 <= counter0 - 1'b1; clr0<=0; end
end
2'b01: begin if (counter0[32]==0) counter0 <= counter0 - 1'b1; else counter0 <={1'b0,counter0_Lock}; end
2'b10: begin sq0<=counter0[32];
if (sq0!=counter0[32]) counter0[31:0] <= {1'b0,counter0_Lock[31:1]}; else counter0 <= counter0 - 1'b1;end
2'b11: counter0 <= counter0 - 1'b1;
endcase
end
/*// Counter channel 1
always @ (posedge clk1 or posedge rst) begin
if (rst )
begin counter1<=0;sq1<=0; end
else
case(counter_Ctrl[10:9])
2'b00: begin if (M1) begin counter1 <= {1'b0,counter1_Lock}; clr1<=1; end
else if (counter1[32]==0)begin counter1 <= counter1 - 1'b1; clr1<=0; end
end
2'b01: begin if (counter1[32]==1) counter1 <= counter1 - 1'b1; else counter1 <={1'b1,counter1_Lock}; end
2'b10: begin sq1<=counter1[32];
if (sq1!=counter1[32]) counter1 <= {1'b0,counter1_Lock[31:1]}; else counter1 <= counter1 - 1'b1;end
2'b11: counter1 <= counter1 - 1'b1;
endcase
end
// Counter channel 2
always @ (posedge clk2 or posedge rst) begin
if (rst )
begin counter2<=0;sq2<=0; end
else
case(counter_Ctrl[18:17])
2'b00: begin if (M2) begin counter2 <= {1'b0,counter2_Lock}; clr2<=1; end
else if (counter2[32]==0) begin counter2 <= counter2 - 1'b1; clr2<=0; end
end
2'b01: begin if (counter2[32]==1) counter2 <= counter2 - 1'b1; else counter2 <={1'b1,counter2_Lock}; end
2'b10: begin sq2<=counter2[32];
if (sq2!=counter2[32]) counter2 <= {1'b0,counter2_Lock[31:1]}; else counter2 <= counter2 - 1'b1;end
2'b11: counter2 <= counter2 - 1'b1;
endcase
end
*/
assign counter0_OUT=counter0[32];
assign counter1_OUT=counter1[32];
assign counter2_OUT=counter2[32];
assign counter_out = counter0[31:0];
/* always @*
case(counter_ch)
2'h0: counter_out <= counter0[31:0];
2'h1: counter_out <= counter1[31:0];
2'h2: counter_out <= counter2[31:0];
2'h3: counter_out <= {8'h00,counter_Ctrl} ;
endcase
*/
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:13:28 07/01/2012
// Design Name:
// Module Name: Counter_8253
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Counter(input clk,
input rst,
input clk0,
input clk1,
input clk2,
input counter_we,
input [31:0] counter_val,
input [1:0] counter_ch, //Counter channel set
output counter0_OUT,
output counter1_OUT,
output counter2_OUT,
output [31:0] counter_out
);
reg [32:0] counter0,counter1,counter2;
reg [31:0] counter0_Lock,counter1_Lock,counter2_Lock;
reg [23:0] counter_Ctrl;
reg sq0,sq1,sq2,M0,M1,M2,clr0,clr1,clr2;
//Counter read or write & set counter_ch=SC1 SC0; counter_Ctrl=XX M2 M1 M0 X
always @ (posedge clk or posedge rst) begin
if (rst )
begin counter0_Lock <=0;counter1_Lock <=0;counter2_Lock <=0;counter_Ctrl<=0; end
else
if (counter_we) begin
case(counter_ch)
2'h0: begin counter0_Lock <= counter_val; M0<=1; end //f0000000: bit1 bit0 =00
2'h1: begin counter1_Lock <= counter_val; M1<=1; end //f0000000: bit1 bit0 =01
2'h2: begin counter2_Lock <= counter_val; M2<=1; end //f0000000: bit1 bit0 =10
2'h3: begin counter_Ctrl <= counter_val[23:0]; end //counter_Ctrl=XX M2 M1 M0 X
endcase
end
else begin counter0_Lock <=counter0_Lock;
counter1_Lock <=counter1_Lock;
counter2_Lock <=counter2_Lock;
counter_Ctrl<=counter_Ctrl;
if(clr0) M0<=0;
if(clr1) M1<=0;
if(clr2) M2<=0;
end
end
// Counter channel 0
always @ (posedge clk0 or posedge rst) begin
if (rst )
begin counter0<=0; sq0<=0; end
else
case(counter_Ctrl[2:1])
2'b00: begin if (M0) begin counter0 <= {1'b0,counter0_Lock}; clr0<=1; end
else if (counter0[32]==0)begin counter0 <= counter0 - 1'b1; clr0<=0; end
end
2'b01: begin if (counter0[32]==0) counter0 <= counter0 - 1'b1; else counter0 <={1'b0,counter0_Lock}; end
2'b10: begin sq0<=counter0[32];
if (sq0!=counter0[32]) counter0[31:0] <= {1'b0,counter0_Lock[31:1]}; else counter0 <= counter0 - 1'b1;end
2'b11: counter0 <= counter0 - 1'b1;
endcase
end
/*// Counter channel 1
always @ (posedge clk1 or posedge rst) begin
if (rst )
begin counter1<=0;sq1<=0; end
else
case(counter_Ctrl[10:9])
2'b00: begin if (M1) begin counter1 <= {1'b0,counter1_Lock}; clr1<=1; end
else if (counter1[32]==0)begin counter1 <= counter1 - 1'b1; clr1<=0; end
end
2'b01: begin if (counter1[32]==1) counter1 <= counter1 - 1'b1; else counter1 <={1'b1,counter1_Lock}; end
2'b10: begin sq1<=counter1[32];
if (sq1!=counter1[32]) counter1 <= {1'b0,counter1_Lock[31:1]}; else counter1 <= counter1 - 1'b1;end
2'b11: counter1 <= counter1 - 1'b1;
endcase
end
// Counter channel 2
always @ (posedge clk2 or posedge rst) begin
if (rst )
begin counter2<=0;sq2<=0; end
else
case(counter_Ctrl[18:17])
2'b00: begin if (M2) begin counter2 <= {1'b0,counter2_Lock}; clr2<=1; end
else if (counter2[32]==0) begin counter2 <= counter2 - 1'b1; clr2<=0; end
end
2'b01: begin if (counter2[32]==1) counter2 <= counter2 - 1'b1; else counter2 <={1'b1,counter2_Lock}; end
2'b10: begin sq2<=counter2[32];
if (sq2!=counter2[32]) counter2 <= {1'b0,counter2_Lock[31:1]}; else counter2 <= counter2 - 1'b1;end
2'b11: counter2 <= counter2 - 1'b1;
endcase
end
*/
assign counter0_OUT=counter0[32];
assign counter1_OUT=counter1[32];
assign counter2_OUT=counter2[32];
assign counter_out = counter0[31:0];
/* always @*
case(counter_ch)
2'h0: counter_out <= counter0[31:0];
2'h1: counter_out <= counter1[31:0];
2'h2: counter_out <= counter2[31:0];
2'h3: counter_out <= {8'h00,counter_Ctrl} ;
endcase
*/
endmodule
|
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_encoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_encoder_32.v
// Megafunction Name(s):
// altecc_encoder
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Internal Build 257 07/26/2010 SP 1 PN Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_encoder device_family="Stratix III" lpm_pipeline=0 width_codeword=39 width_dataword=32 data q
//VERSION_BEGIN 10.0SP1 cbx_altecc_encoder 2010:07:26:21:21:15:PN cbx_mgl 2010:07:26:21:25:47:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_encoder_32_altecc_encoder #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
) /* synthesis synthesis_clearbox=1 */;
input clk;
input reset_n;
input [31:0] data;
output [38:0] q;
wire [31:0] data_wire;
wire [17:0] parity_01_wire;
wire [9:0] parity_02_wire;
wire [4:0] parity_03_wire;
wire [1:0] parity_04_wire;
wire [0:0] parity_05_wire;
wire [5:0] parity_06_wire;
wire [37:0] parity_final;
wire [37:0] parity_final_wire;
reg [37:0] parity_final_reg;
wire [37:0] q_wire;
reg [37:0] q_reg;
assign
data_wire = data,
parity_01_wire = {
(data_wire[30] ^ parity_01_wire[16]),
(data_wire[28] ^ parity_01_wire[15]),
(data_wire[26] ^ parity_01_wire[14]),
(data_wire[25] ^ parity_01_wire[13]),
(data_wire[23] ^ parity_01_wire[12]),
(data_wire[21] ^ parity_01_wire[11]),
(data_wire[19] ^ parity_01_wire[10]),
(data_wire[17] ^ parity_01_wire[9]),
(data_wire[15] ^ parity_01_wire[8]),
(data_wire[13] ^ parity_01_wire[7]),
(data_wire[11] ^ parity_01_wire[6]),
(data_wire[10] ^ parity_01_wire[5]),
(data_wire[8] ^ parity_01_wire[4]),
(data_wire[6] ^ parity_01_wire[3]),
(data_wire[4] ^ parity_01_wire[2]),
(data_wire[3] ^ parity_01_wire[1]),
(data_wire[1] ^ parity_01_wire[0]),
data_wire[0]
},
parity_02_wire = {
(data_wire[31] ^ parity_02_wire[8]),
((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]),
((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]),
((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]),
((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]),
((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]),
((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]),
((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]),
((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]),
data_wire[0]
},
parity_03_wire = {
(((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ parity_03_wire[3]),
((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]),
((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]),
((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]),
((data_wire[1] ^ data_wire[2]) ^ data_wire[3])
},
parity_04_wire = {
((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]),
((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])
},
parity_05_wire = {
((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])
},
parity_06_wire = {
(data_wire[31] ^ parity_06_wire[4]),
(data_wire[30] ^ parity_06_wire[3]),
(data_wire[29] ^ parity_06_wire[2]),
(data_wire[28] ^ parity_06_wire[1]),
(data_wire[27] ^ parity_06_wire[0]),
data_wire[26]
},
parity_final_wire = {
(q_wire[37] ^ parity_final_wire[36]),
(q_wire[36] ^ parity_final_wire[35]),
(q_wire[35] ^ parity_final_wire[34]),
(q_wire[34] ^ parity_final_wire[33]),
(q_wire[33] ^ parity_final_wire[32]),
(q_wire[32] ^ parity_final_wire[31]),
(q_wire[31] ^ parity_final_wire[30]),
(q_wire[30] ^ parity_final_wire[29]),
(q_wire[29] ^ parity_final_wire[28]),
(q_wire[28] ^ parity_final_wire[27]),
(q_wire[27] ^ parity_final_wire[26]),
(q_wire[26] ^ parity_final_wire[25]),
(q_wire[25] ^ parity_final_wire[24]),
(q_wire[24] ^ parity_final_wire[23]),
(q_wire[23] ^ parity_final_wire[22]),
(q_wire[22] ^ parity_final_wire[21]),
(q_wire[21] ^ parity_final_wire[20]),
(q_wire[20] ^ parity_final_wire[19]),
(q_wire[19] ^ parity_final_wire[18]),
(q_wire[18] ^ parity_final_wire[17]),
(q_wire[17] ^ parity_final_wire[16]),
(q_wire[16] ^ parity_final_wire[15]),
(q_wire[15] ^ parity_final_wire[14]),
(q_wire[14] ^ parity_final_wire[13]),
(q_wire[13] ^ parity_final_wire[12]),
(q_wire[12] ^ parity_final_wire[11]),
(q_wire[11] ^ parity_final_wire[10]),
(q_wire[10] ^ parity_final_wire[9]),
(q_wire[9] ^ parity_final_wire[8]),
(q_wire[8] ^ parity_final_wire[7]),
(q_wire[7] ^ parity_final_wire[6]),
(q_wire[6] ^ parity_final_wire[5]),
(q_wire[5] ^ parity_final_wire[4]),
(q_wire[4] ^ parity_final_wire[3]),
(q_wire[3] ^ parity_final_wire[2]),
(q_wire[2] ^ parity_final_wire[1]),
(q_wire[1] ^ parity_final_wire[0]),
q_wire[0]
},
parity_final = {
(q_reg[37] ^ parity_final[36]),
(q_reg[36] ^ parity_final[35]),
(q_reg[35] ^ parity_final[34]),
(q_reg[34] ^ parity_final[33]),
(q_reg[33] ^ parity_final[32]),
(q_reg[32] ^ parity_final[31]),
parity_final_reg[31 : 0]
},
q = {parity_final[37], q_reg},
q_wire = {parity_06_wire[5], parity_05_wire[0], parity_04_wire[1], parity_03_wire[4], parity_02_wire[9], parity_01_wire[17], data_wire};
generate
if (CFG_ECC_ENC_REG)
begin
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
q_reg <= 0;
parity_final_reg <= 0;
end
else
begin
q_reg <= q_wire;
parity_final_reg <= parity_final_wire;
end
end
end
else
begin
always @ (*)
begin
q_reg = q_wire;
parity_final_reg = parity_final_wire;
end
end
endgenerate
endmodule //alt_mem_ddrx_ecc_encoder_32_altecc_encoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_encoder_32 #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
)/* synthesis synthesis_clearbox = 1 */;
input clk;
input reset_n;
input [31:0] data;
output [38:0] q;
wire [38:0] sub_wire0;
wire [38:0] q = sub_wire0[38:0];
alt_mem_ddrx_ecc_encoder_32_altecc_encoder #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
alt_mem_ddrx_ecc_encoder_32_altecc_encoder_component
(
.clk (clk),
.reset_n (reset_n),
.data (data),
.q (sub_wire0)
);
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "39"
// Retrieval info: CONSTANT: width_dataword NUMERIC "32"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 39 0 OUTPUT NODEFVAL "q[38..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 39 0 @q 0 0 39 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_syn.v TRUE
|
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_encoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_encoder_32.v
// Megafunction Name(s):
// altecc_encoder
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Internal Build 257 07/26/2010 SP 1 PN Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_encoder device_family="Stratix III" lpm_pipeline=0 width_codeword=39 width_dataword=32 data q
//VERSION_BEGIN 10.0SP1 cbx_altecc_encoder 2010:07:26:21:21:15:PN cbx_mgl 2010:07:26:21:25:47:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_encoder_32_altecc_encoder #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
) /* synthesis synthesis_clearbox=1 */;
input clk;
input reset_n;
input [31:0] data;
output [38:0] q;
wire [31:0] data_wire;
wire [17:0] parity_01_wire;
wire [9:0] parity_02_wire;
wire [4:0] parity_03_wire;
wire [1:0] parity_04_wire;
wire [0:0] parity_05_wire;
wire [5:0] parity_06_wire;
wire [37:0] parity_final;
wire [37:0] parity_final_wire;
reg [37:0] parity_final_reg;
wire [37:0] q_wire;
reg [37:0] q_reg;
assign
data_wire = data,
parity_01_wire = {
(data_wire[30] ^ parity_01_wire[16]),
(data_wire[28] ^ parity_01_wire[15]),
(data_wire[26] ^ parity_01_wire[14]),
(data_wire[25] ^ parity_01_wire[13]),
(data_wire[23] ^ parity_01_wire[12]),
(data_wire[21] ^ parity_01_wire[11]),
(data_wire[19] ^ parity_01_wire[10]),
(data_wire[17] ^ parity_01_wire[9]),
(data_wire[15] ^ parity_01_wire[8]),
(data_wire[13] ^ parity_01_wire[7]),
(data_wire[11] ^ parity_01_wire[6]),
(data_wire[10] ^ parity_01_wire[5]),
(data_wire[8] ^ parity_01_wire[4]),
(data_wire[6] ^ parity_01_wire[3]),
(data_wire[4] ^ parity_01_wire[2]),
(data_wire[3] ^ parity_01_wire[1]),
(data_wire[1] ^ parity_01_wire[0]),
data_wire[0]
},
parity_02_wire = {
(data_wire[31] ^ parity_02_wire[8]),
((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]),
((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]),
((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]),
((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]),
((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]),
((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]),
((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]),
((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]),
data_wire[0]
},
parity_03_wire = {
(((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ parity_03_wire[3]),
((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]),
((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]),
((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]),
((data_wire[1] ^ data_wire[2]) ^ data_wire[3])
},
parity_04_wire = {
((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]),
((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])
},
parity_05_wire = {
((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])
},
parity_06_wire = {
(data_wire[31] ^ parity_06_wire[4]),
(data_wire[30] ^ parity_06_wire[3]),
(data_wire[29] ^ parity_06_wire[2]),
(data_wire[28] ^ parity_06_wire[1]),
(data_wire[27] ^ parity_06_wire[0]),
data_wire[26]
},
parity_final_wire = {
(q_wire[37] ^ parity_final_wire[36]),
(q_wire[36] ^ parity_final_wire[35]),
(q_wire[35] ^ parity_final_wire[34]),
(q_wire[34] ^ parity_final_wire[33]),
(q_wire[33] ^ parity_final_wire[32]),
(q_wire[32] ^ parity_final_wire[31]),
(q_wire[31] ^ parity_final_wire[30]),
(q_wire[30] ^ parity_final_wire[29]),
(q_wire[29] ^ parity_final_wire[28]),
(q_wire[28] ^ parity_final_wire[27]),
(q_wire[27] ^ parity_final_wire[26]),
(q_wire[26] ^ parity_final_wire[25]),
(q_wire[25] ^ parity_final_wire[24]),
(q_wire[24] ^ parity_final_wire[23]),
(q_wire[23] ^ parity_final_wire[22]),
(q_wire[22] ^ parity_final_wire[21]),
(q_wire[21] ^ parity_final_wire[20]),
(q_wire[20] ^ parity_final_wire[19]),
(q_wire[19] ^ parity_final_wire[18]),
(q_wire[18] ^ parity_final_wire[17]),
(q_wire[17] ^ parity_final_wire[16]),
(q_wire[16] ^ parity_final_wire[15]),
(q_wire[15] ^ parity_final_wire[14]),
(q_wire[14] ^ parity_final_wire[13]),
(q_wire[13] ^ parity_final_wire[12]),
(q_wire[12] ^ parity_final_wire[11]),
(q_wire[11] ^ parity_final_wire[10]),
(q_wire[10] ^ parity_final_wire[9]),
(q_wire[9] ^ parity_final_wire[8]),
(q_wire[8] ^ parity_final_wire[7]),
(q_wire[7] ^ parity_final_wire[6]),
(q_wire[6] ^ parity_final_wire[5]),
(q_wire[5] ^ parity_final_wire[4]),
(q_wire[4] ^ parity_final_wire[3]),
(q_wire[3] ^ parity_final_wire[2]),
(q_wire[2] ^ parity_final_wire[1]),
(q_wire[1] ^ parity_final_wire[0]),
q_wire[0]
},
parity_final = {
(q_reg[37] ^ parity_final[36]),
(q_reg[36] ^ parity_final[35]),
(q_reg[35] ^ parity_final[34]),
(q_reg[34] ^ parity_final[33]),
(q_reg[33] ^ parity_final[32]),
(q_reg[32] ^ parity_final[31]),
parity_final_reg[31 : 0]
},
q = {parity_final[37], q_reg},
q_wire = {parity_06_wire[5], parity_05_wire[0], parity_04_wire[1], parity_03_wire[4], parity_02_wire[9], parity_01_wire[17], data_wire};
generate
if (CFG_ECC_ENC_REG)
begin
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
q_reg <= 0;
parity_final_reg <= 0;
end
else
begin
q_reg <= q_wire;
parity_final_reg <= parity_final_wire;
end
end
end
else
begin
always @ (*)
begin
q_reg = q_wire;
parity_final_reg = parity_final_wire;
end
end
endgenerate
endmodule //alt_mem_ddrx_ecc_encoder_32_altecc_encoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_encoder_32 #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
)/* synthesis synthesis_clearbox = 1 */;
input clk;
input reset_n;
input [31:0] data;
output [38:0] q;
wire [38:0] sub_wire0;
wire [38:0] q = sub_wire0[38:0];
alt_mem_ddrx_ecc_encoder_32_altecc_encoder #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
alt_mem_ddrx_ecc_encoder_32_altecc_encoder_component
(
.clk (clk),
.reset_n (reset_n),
.data (data),
.q (sub_wire0)
);
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "39"
// Retrieval info: CONSTANT: width_dataword NUMERIC "32"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 39 0 OUTPUT NODEFVAL "q[38..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 39 0 @q 0 0 39 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_syn.v TRUE
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ram_2clk_1w_1r.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An inferrable RAM module. Dual clocks, 1 write port, 1
// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
// LUT memory.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module ram_2clk_1w_1r
#(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
)
(
input CLKA,
input CLKB,
input WEA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
input [C_RAM_WIDTH-1:0] DINA,
output [C_RAM_WIDTH-1:0] DOUTB
);
//Local parameters
localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLKA) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
end
always @(posedge CLKB) begin
rDout <= #1 rRAM[ADDRB];
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ram_2clk_1w_1r.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An inferrable RAM module. Dual clocks, 1 write port, 1
// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
// LUT memory.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module ram_2clk_1w_1r
#(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
)
(
input CLKA,
input CLKB,
input WEA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
input [C_RAM_WIDTH-1:0] DINA,
output [C_RAM_WIDTH-1:0] DOUTB
);
//Local parameters
localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLKA) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
end
always @(posedge CLKB) begin
rDout <= #1 rRAM[ADDRB];
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_vc707.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: RIFFA wrapper for the VC707 Development board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "xilinx.vh"
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_vc707
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
// 4-Byte Name for this FPGA
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5,
parameter C_FPGA_ID = "V707")
(// Interface: Xilinx RX
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,
input M_AXIS_RX_TLAST,
input M_AXIS_RX_TVALID,
output M_AXIS_RX_TREADY,
input [`SIG_XIL_RX_TUSER_W-1:0] M_AXIS_RX_TUSER,
output RX_NP_OK,
output RX_NP_REQ,
// Interface: Xilinx TX
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,
output S_AXIS_TX_TLAST,
output S_AXIS_TX_TVALID,
input S_AXIS_TX_TREADY,
output [`SIG_XIL_TX_TUSER_W-1:0] S_AXIS_TX_TUSER,
output TX_CFG_GNT,
// Interface: Xilinx Configuration
input [`SIG_BUSID_W-1:0] CFG_BUS_NUMBER,
input [`SIG_DEVID_W-1:0] CFG_DEVICE_NUMBER,
input [`SIG_FNID_W-1:0] CFG_FUNCTION_NUMBER,
input [`SIG_CFGREG_W-1:0] CFG_COMMAND,
input [`SIG_CFGREG_W-1:0] CFG_DCOMMAND,
input [`SIG_CFGREG_W-1:0] CFG_LSTATUS,
input [`SIG_CFGREG_W-1:0] CFG_LCOMMAND,
// Interface: Xilinx Flow Control
input [`SIG_FC_CPLD_W-1:0] FC_CPLD,
input [`SIG_FC_CPLH_W-1:0] FC_CPLH,
output [`SIG_FC_SEL_W-1:0] FC_SEL,
// Interface: Xilinx Interrupt
input CFG_INTERRUPT_MSIEN,
input CFG_INTERRUPT_RDY,
output CFG_INTERRUPT,
input USER_CLK,
input USER_RESET,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
// ALTERA, XILINX or ULTRASCALE
localparam C_VENDOR = "XILINX";
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
localparam C_DEPTH_PACKETS = 4;
wire clk;
wire rst_in;
wire done_txc_rst;
wire done_txr_rst;
wire done_rxr_rst;
wire done_rxc_rst;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Classic Interface Wires
wire rx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] rx_tlp;
wire rx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_end_offset;
wire rx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_start_offset;
wire rx_tlp_valid;
wire [`SIG_BARDECODE_W-1:0] rx_tlp_bar_decode;
wire tx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] tx_tlp;
wire tx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_end_offset;
wire tx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_start_offset;
wire tx_tlp_valid;
// Unconnected Wires (Used in ultrascale interface)
// Interface: RQ (TXC)
wire s_axis_rq_tlast_nc;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata_nc;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep_nc;
wire s_axis_rq_tready_nc = 0;
wire s_axis_rq_tvalid_nc;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata_nc = 0;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser_nc = 0;
wire m_axis_rc_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep_nc = 0;
wire m_axis_rc_tvalid_nc = 0;
wire m_axis_rc_tready_nc;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata_nc = 0;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser_nc = 0;
wire m_axis_cq_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep_nc = 0;
wire m_axis_cq_tvalid_nc = 0;
wire m_axis_cq_tready_nc = 0;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata_nc;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser_nc;
wire s_axis_cc_tlast_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep_nc;
wire s_axis_cc_tvalid_nc;
wire s_axis_cc_tready_nc = 0;
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
reg rRxTlpValid;
reg rRxTlpEndFlag;
assign clk = USER_CLK;
assign rst_in = USER_RESET;
translation_xilinx
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
trans
(// Outputs
.RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]),
.TX_TLP_READY (tx_tlp_ready),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RX_TLP_READY (rx_tlp_ready),
.TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.INTR_MSI_REQUEST (intr_msi_request),
/*AUTOINST*/
// Outputs
.M_AXIS_RX_TREADY (M_AXIS_RX_TREADY),
.RX_NP_OK (RX_NP_OK),
.RX_NP_REQ (RX_NP_REQ),
.S_AXIS_TX_TDATA (S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (S_AXIS_TX_TLAST),
.S_AXIS_TX_TVALID (S_AXIS_TX_TVALID),
.S_AXIS_TX_TUSER (S_AXIS_TX_TUSER[`SIG_XIL_TX_TUSER_W-1:0]),
.TX_CFG_GNT (TX_CFG_GNT),
.FC_SEL (FC_SEL[`SIG_FC_SEL_W-1:0]),
.CFG_INTERRUPT (CFG_INTERRUPT),
// Inputs
.M_AXIS_RX_TDATA (M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (M_AXIS_RX_TLAST),
.M_AXIS_RX_TVALID (M_AXIS_RX_TVALID),
.M_AXIS_RX_TUSER (M_AXIS_RX_TUSER[`SIG_XIL_RX_TUSER_W-1:0]),
.S_AXIS_TX_TREADY (S_AXIS_TX_TREADY),
.CFG_BUS_NUMBER (CFG_BUS_NUMBER[`SIG_BUSID_W-1:0]),
.CFG_DEVICE_NUMBER (CFG_DEVICE_NUMBER[`SIG_DEVID_W-1:0]),
.CFG_FUNCTION_NUMBER (CFG_FUNCTION_NUMBER[`SIG_FNID_W-1:0]),
.CFG_COMMAND (CFG_COMMAND[`SIG_CFGREG_W-1:0]),
.CFG_DCOMMAND (CFG_DCOMMAND[`SIG_CFGREG_W-1:0]),
.CFG_LSTATUS (CFG_LSTATUS[`SIG_CFGREG_W-1:0]),
.CFG_LCOMMAND (CFG_LCOMMAND[`SIG_CFGREG_W-1:0]),
.FC_CPLD (FC_CPLD[`SIG_FC_CPLD_W-1:0]),
.FC_CPLH (FC_CPLH[`SIG_FC_CPLH_W-1:0]),
.CFG_INTERRUPT_MSIEN (CFG_INTERRUPT_MSIEN),
.CFG_INTERRUPT_RDY (CFG_INTERRUPT_RDY));
engine_layer
#(// Parameters
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.RST_LOGIC (RST_OUT),
// Unconnected Outputs
.TX_TLP (tx_tlp),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset),
.RX_TLP_READY (rx_tlp_ready),
// Inputs
.CLK_BUS (clk),
.RST_BUS (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (rx_tlp),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode),
.TX_TLP_READY (tx_tlp_ready),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.DONE_RXR_RST (done_rxc_rst),
.DONE_RXC_RST (done_rxr_rst),
// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready_nc),
.M_AXIS_RC_TREADY (m_axis_rc_tready_nc),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid_nc),
.S_AXIS_CC_TLAST (s_axis_cc_tlast_nc),
.S_AXIS_CC_TDATA (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid_nc),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast_nc),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid_nc),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast_nc),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid_nc),
.M_AXIS_RC_TLAST (m_axis_rc_tlast_nc),
.M_AXIS_RC_TDATA (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready_nc),
.S_AXIS_RQ_TREADY (s_axis_rq_tready_nc)
/*AUTOINST*/);
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME),
.C_FPGA_ID (C_FPGA_ID),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.RST_BUS (rst_in),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("../../riffa_hdl/")
// End:
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_vc707.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: RIFFA wrapper for the VC707 Development board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "xilinx.vh"
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_vc707
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
// 4-Byte Name for this FPGA
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5,
parameter C_FPGA_ID = "V707")
(// Interface: Xilinx RX
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,
input M_AXIS_RX_TLAST,
input M_AXIS_RX_TVALID,
output M_AXIS_RX_TREADY,
input [`SIG_XIL_RX_TUSER_W-1:0] M_AXIS_RX_TUSER,
output RX_NP_OK,
output RX_NP_REQ,
// Interface: Xilinx TX
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,
output S_AXIS_TX_TLAST,
output S_AXIS_TX_TVALID,
input S_AXIS_TX_TREADY,
output [`SIG_XIL_TX_TUSER_W-1:0] S_AXIS_TX_TUSER,
output TX_CFG_GNT,
// Interface: Xilinx Configuration
input [`SIG_BUSID_W-1:0] CFG_BUS_NUMBER,
input [`SIG_DEVID_W-1:0] CFG_DEVICE_NUMBER,
input [`SIG_FNID_W-1:0] CFG_FUNCTION_NUMBER,
input [`SIG_CFGREG_W-1:0] CFG_COMMAND,
input [`SIG_CFGREG_W-1:0] CFG_DCOMMAND,
input [`SIG_CFGREG_W-1:0] CFG_LSTATUS,
input [`SIG_CFGREG_W-1:0] CFG_LCOMMAND,
// Interface: Xilinx Flow Control
input [`SIG_FC_CPLD_W-1:0] FC_CPLD,
input [`SIG_FC_CPLH_W-1:0] FC_CPLH,
output [`SIG_FC_SEL_W-1:0] FC_SEL,
// Interface: Xilinx Interrupt
input CFG_INTERRUPT_MSIEN,
input CFG_INTERRUPT_RDY,
output CFG_INTERRUPT,
input USER_CLK,
input USER_RESET,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
// ALTERA, XILINX or ULTRASCALE
localparam C_VENDOR = "XILINX";
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
localparam C_DEPTH_PACKETS = 4;
wire clk;
wire rst_in;
wire done_txc_rst;
wire done_txr_rst;
wire done_rxr_rst;
wire done_rxc_rst;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Classic Interface Wires
wire rx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] rx_tlp;
wire rx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_end_offset;
wire rx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] rx_tlp_start_offset;
wire rx_tlp_valid;
wire [`SIG_BARDECODE_W-1:0] rx_tlp_bar_decode;
wire tx_tlp_ready;
wire [C_PCI_DATA_WIDTH-1:0] tx_tlp;
wire tx_tlp_end_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_end_offset;
wire tx_tlp_start_flag;
wire [`SIG_OFFSET_W-1:0] tx_tlp_start_offset;
wire tx_tlp_valid;
// Unconnected Wires (Used in ultrascale interface)
// Interface: RQ (TXC)
wire s_axis_rq_tlast_nc;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata_nc;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep_nc;
wire s_axis_rq_tready_nc = 0;
wire s_axis_rq_tvalid_nc;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata_nc = 0;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser_nc = 0;
wire m_axis_rc_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep_nc = 0;
wire m_axis_rc_tvalid_nc = 0;
wire m_axis_rc_tready_nc;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata_nc = 0;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser_nc = 0;
wire m_axis_cq_tlast_nc = 0;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep_nc = 0;
wire m_axis_cq_tvalid_nc = 0;
wire m_axis_cq_tready_nc = 0;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata_nc;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser_nc;
wire s_axis_cc_tlast_nc;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep_nc;
wire s_axis_cc_tvalid_nc;
wire s_axis_cc_tready_nc = 0;
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
reg rRxTlpValid;
reg rRxTlpEndFlag;
assign clk = USER_CLK;
assign rst_in = USER_RESET;
translation_xilinx
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
trans
(// Outputs
.RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]),
.TX_TLP_READY (tx_tlp_ready),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
// Inputs
.CLK (clk),
.RST_IN (rst_in),
.RX_TLP_READY (rx_tlp_ready),
.TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.INTR_MSI_REQUEST (intr_msi_request),
/*AUTOINST*/
// Outputs
.M_AXIS_RX_TREADY (M_AXIS_RX_TREADY),
.RX_NP_OK (RX_NP_OK),
.RX_NP_REQ (RX_NP_REQ),
.S_AXIS_TX_TDATA (S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (S_AXIS_TX_TLAST),
.S_AXIS_TX_TVALID (S_AXIS_TX_TVALID),
.S_AXIS_TX_TUSER (S_AXIS_TX_TUSER[`SIG_XIL_TX_TUSER_W-1:0]),
.TX_CFG_GNT (TX_CFG_GNT),
.FC_SEL (FC_SEL[`SIG_FC_SEL_W-1:0]),
.CFG_INTERRUPT (CFG_INTERRUPT),
// Inputs
.M_AXIS_RX_TDATA (M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (M_AXIS_RX_TLAST),
.M_AXIS_RX_TVALID (M_AXIS_RX_TVALID),
.M_AXIS_RX_TUSER (M_AXIS_RX_TUSER[`SIG_XIL_RX_TUSER_W-1:0]),
.S_AXIS_TX_TREADY (S_AXIS_TX_TREADY),
.CFG_BUS_NUMBER (CFG_BUS_NUMBER[`SIG_BUSID_W-1:0]),
.CFG_DEVICE_NUMBER (CFG_DEVICE_NUMBER[`SIG_DEVID_W-1:0]),
.CFG_FUNCTION_NUMBER (CFG_FUNCTION_NUMBER[`SIG_FNID_W-1:0]),
.CFG_COMMAND (CFG_COMMAND[`SIG_CFGREG_W-1:0]),
.CFG_DCOMMAND (CFG_DCOMMAND[`SIG_CFGREG_W-1:0]),
.CFG_LSTATUS (CFG_LSTATUS[`SIG_CFGREG_W-1:0]),
.CFG_LCOMMAND (CFG_LCOMMAND[`SIG_CFGREG_W-1:0]),
.FC_CPLD (FC_CPLD[`SIG_FC_CPLD_W-1:0]),
.FC_CPLH (FC_CPLH[`SIG_FC_CPLH_W-1:0]),
.CFG_INTERRUPT_MSIEN (CFG_INTERRUPT_MSIEN),
.CFG_INTERRUPT_RDY (CFG_INTERRUPT_RDY));
engine_layer
#(// Parameters
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.RST_LOGIC (RST_OUT),
// Unconnected Outputs
.TX_TLP (tx_tlp),
.TX_TLP_VALID (tx_tlp_valid),
.TX_TLP_START_FLAG (tx_tlp_start_flag),
.TX_TLP_START_OFFSET (tx_tlp_start_offset),
.TX_TLP_END_FLAG (tx_tlp_end_flag),
.TX_TLP_END_OFFSET (tx_tlp_end_offset),
.RX_TLP_READY (rx_tlp_ready),
// Inputs
.CLK_BUS (clk),
.RST_BUS (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (rx_tlp),
.RX_TLP_VALID (rx_tlp_valid),
.RX_TLP_START_FLAG (rx_tlp_start_flag),
.RX_TLP_START_OFFSET (rx_tlp_start_offset),
.RX_TLP_END_FLAG (rx_tlp_end_flag),
.RX_TLP_END_OFFSET (rx_tlp_end_offset),
.RX_TLP_BAR_DECODE (rx_tlp_bar_decode),
.TX_TLP_READY (tx_tlp_ready),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.DONE_RXR_RST (done_rxc_rst),
.DONE_RXC_RST (done_rxr_rst),
// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready_nc),
.M_AXIS_RC_TREADY (m_axis_rc_tready_nc),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid_nc),
.S_AXIS_CC_TLAST (s_axis_cc_tlast_nc),
.S_AXIS_CC_TDATA (s_axis_cc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser_nc[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid_nc),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast_nc),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser_nc[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid_nc),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast_nc),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser_nc[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid_nc),
.M_AXIS_RC_TLAST (m_axis_rc_tlast_nc),
.M_AXIS_RC_TDATA (m_axis_rc_tdata_nc[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep_nc[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser_nc[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready_nc),
.S_AXIS_RQ_TREADY (s_axis_rq_tready_nc)
/*AUTOINST*/);
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME),
.C_FPGA_ID (C_FPGA_ID),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.RST_BUS (rst_in),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("../../riffa_hdl/")
// End:
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: txc_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TXR Engine takes unformatted completions, formats
// these packets into "TLP's" or Transaction Layer Packets. These packets must
// meet max-request, max-payload, and payload termination requirements (see Read
// Completion Boundary). The TXR Engine does not check these requirements during
// operation, but may do so during simulation. This Engine is capable of
// operating at "line rate". This file also contains the txr_formatter module,
// which formats request headers.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
`include "tlp.vh" // Defines the endpoint-facing field widths in a TLP
module txr_engine_classic
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_DEPTH_PACKETS = 10,
parameter C_VENDOR = "ALTERA")
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN, // Addition for RIFFA_RST
output DONE_TXR_RST,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXR Classic
input TXR_TLP_READY,
output [C_PCI_DATA_WIDTH-1:0] TXR_TLP,
output TXR_TLP_VALID,
output TXR_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_START_OFFSET,
output TXR_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_END_OFFSET,
// Interface: TXR Engine
input TXR_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
input TXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
input TXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
output TXR_DATA_READY,
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY
);
localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
localparam C_MAX_HDR_WIDTH = `TLP_MAXHDR_W;
localparam C_MAX_ALIGN_WIDTH = (C_VENDOR == "ALTERA") ? 32:
(C_VENDOR == "XILINX") ? 0 :
0;
localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
/*AUTOWIRE*/
/*AUTOINPUT*/
///*AUTOOUTPUT*/
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
assign DONE_TXR_RST = ~RST_IN;
txr_formatter_classic
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_ALIGN_WIDTH (C_MAX_ALIGN_WIDTH),
.C_VENDOR (C_VENDOR))
txr_formatter_inst
(
// Outputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
.TXR_META_READY (TXR_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP));
tx_engine
#(
.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
txr_engine_inst
(
// Outputs
.TX_HDR_READY (wTxHdrReady),
.TX_DATA_READY (TXR_DATA_READY),
.TX_PKT (TXR_TLP[C_DATA_WIDTH-1:0]),
.TX_PKT_START_FLAG (TXR_TLP_START_FLAG),
.TX_PKT_START_OFFSET (TXR_TLP_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (TXR_TLP_END_FLAG),
.TX_PKT_END_OFFSET (TXR_TLP_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_VALID (TXR_TLP_VALID),
// Inputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_DATA_VALID (TXR_DATA_VALID),
.TX_DATA (TXR_DATA[C_DATA_WIDTH-1:0]),
.TX_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TX_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TX_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_READY (TXR_TLP_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
module txr_formatter_classic
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,
parameter C_MAX_ALIGN_WIDTH = 32,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXR
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY,
// Interface: TX HDR
output TX_HDR_VALID,
output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
output TX_HDR_NOPAYLOAD,
input TX_HDR_READY
);
wire wWrReq;
wire [`TLP_FMT_W-1:0] wHdrLoFmt;
wire [63:0] wHdrLo;
wire [63:0] _wTxHdr;
wire wTxHdrReady;
wire wTxHdrValid;
wire [(`TLP_REQADDR_W/2)-1:0] wTxHdrAddr[1:0];
wire [(`TLP_REQADDR_W/2)-1:0] wTxHdrAddrDW0;
wire wTxHdr4DW;
wire wTxHdrAlignmentNeeded;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
assign wHdrLoFmt = {1'b0, TXR_META_TYPE[`TRLS_TYPE_PAY_I],1'bx};
// Reserved Fields
assign wHdrLo[`TLP_RSVD0_R] = `TLP_RSVD0_V;
assign wHdrLo[`TLP_ADDRTYPE_R] = `TLP_ADDRTYPE_W'b0;
assign wHdrLo[`TLP_TH_R] = `TLP_TH_W'b0;
assign wHdrLo[`TLP_RSVD1_R] = `TLP_RSVD1_V;
assign wHdrLo[`TLP_RSVD2_R] = `TLP_RSVD2_V;
// Generic Header Fields
assign wHdrLo[`TLP_LEN_R] = TXR_META_LENGTH;
assign wHdrLo[`TLP_EP_R] = TXR_META_EP;
assign wHdrLo[`TLP_TD_R] = `TLP_NODIGEST_V;
assign wHdrLo[`TLP_ATTR0_R] = TXR_META_ATTR[1:0];
assign wHdrLo[`TLP_ATTR1_R] = TXR_META_ATTR[2];
assign wHdrLo[`TLP_TYPE_R] = TXR_META_TYPE; // WORKAROUND
assign wHdrLo[`TLP_TC_R] = TXR_META_TC;
assign wHdrLo[`TLP_FMT_R] = wHdrLoFmt;
// Request Specific Fields
assign wHdrLo[`TLP_REQFBE_R] = TXR_META_FDWBE;
assign wHdrLo[`TLP_REQLBE_R] = TXR_META_LDWBE;
assign wHdrLo[`TLP_REQTAG_R] = TXR_META_TAG;
assign wHdrLo[`TLP_REQREQID_R] = CONFIG_COMPLETER_ID;
// Second header formatting stage
assign wTxHdr4DW = wTxHdrAddr[1] != 32'b0;
assign {wTxHdr[`TLP_FMT_R],wTxHdr[`TLP_TYPE_R]} = trellis_to_tlp_type(_wTxHdr[`TLP_TYPE_I +: `SIG_TYPE_W],wTxHdr4DW);
assign wTxHdr[`TLP_TYPE_I-1:0] = _wTxHdr[`TLP_TYPE_I-1:0];
assign wTxHdr[63:32] = _wTxHdr[63:32];
assign wTxHdr[127:64] = {wTxHdrAddr[~wTxHdr4DW],wTxHdrAddr[wTxHdr4DW]};
// Metadata, to the aligner
assign wTxHdrNopayload = ~wTxHdr[`TLP_PAYBIT_I];
assign wTxHdrAddrDW0 = wTxHdrAddr[0];
assign wTxHdrAlignmentNeeded = (wTxHdrAddrDW0[2] == wTxHdr4DW);
assign wTxHdrNonpayLen = {1'b0,{wTxHdr4DW,~wTxHdr4DW,~wTxHdr4DW}} + ((C_VENDOR == "ALTERA") ? {3'b0,(wTxHdrAlignmentNeeded & ~wTxHdrNopayload)}:0);
assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`TLP_LEN_R];
assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
pipeline
#(// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(// Outputs
.WR_DATA_READY (TXR_META_READY),
.RD_DATA ({wTxHdrAddr[1],wTxHdrAddr[0],_wTxHdr[63:0]}),
.RD_DATA_VALID (wTxHdrValid),
// Inputs
.WR_DATA ({TXR_META_ADDR, wHdrLo}),
.WR_DATA_VALID (TXR_META_VALID),
.RD_DATA_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wTxHdrReady),
.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
.RD_DATA_VALID (TX_HDR_VALID),
// Inputs
.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
.WR_DATA_VALID (wTxHdrValid),
.RD_DATA_READY (TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/" "../../common/")
// End:
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_monitor_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Detects transaction open/close events from the stream
// of data from the tx_port_channel_gate. Filters out events and passes data
// onto the tx_port_buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTMON32_NEXT 6'b00_0001
`define S_TXPORTMON32_EVT_2 6'b00_0010
`define S_TXPORTMON32_TXN 6'b00_0100
`define S_TXPORTMON32_READ 6'b00_1000
`define S_TXPORTMON32_END_0 6'b01_0000
`define S_TXPORTMON32_END_1 6'b10_0000
`timescale 1ns/1ns
module tx_port_monitor_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_VALID_HIST = 1
)
(
input RST,
input CLK,
input [C_DATA_WIDTH:0] EVT_DATA, // Event data from tx_port_channel_gate
input EVT_DATA_EMPTY, // Event data FIFO is empty
output EVT_DATA_RD_EN, // Event data FIFO read enable
output [C_DATA_WIDTH-1:0] WR_DATA, // Output data
output WR_EN, // Write enable for output data
input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Output FIFO count
output TXN, // Transaction parameters are valid
input ACK, // Transaction parameter read, continue
output LAST, // Channel last write
output [31:0] LEN, // Channel write length (in 32 bit words)
output [30:0] OFF, // Channel write offset
output [31:0] WORDS_RECVD, // Count of data words received in transaction
output DONE, // Transaction is closed
input TX_ERR // Transaction encountered an error
);
`include "functions.vh"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [5:0] rState=`S_TXPORTMON32_NEXT, _rState=`S_TXPORTMON32_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
reg [31:0] rReadOffLast=0, _rReadOffLast=0;
reg [31:0] rReadLen=0, _rReadLen=0;
reg rReadCount=0, _rReadCount=0;
reg [31:0] rWordsRecvd=0, _rWordsRecvd=0;
reg [31:0] rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
reg rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
reg rAlmostFull=0, _rAlmostFull=0;
reg rLenEQ0Hi=0, _rLenEQ0Hi=0;
reg rLenEQ0Lo=0, _rLenEQ0Lo=0;
reg rLenLE1Lo=0, _rLenLE1Lo=0;
reg rTxErr=0, _rTxErr=0;
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[3]); // S_TXPORTMON32_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE1Lo)) & wPayloadData);
assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData;
assign TXN = rState[2]; // S_TXPORTMON32_TXN
assign LAST = rReadOffLast[0];
assign OFF = rReadOffLast[31:1];
assign LEN = rReadLen;
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[3]; // !S_TXPORTMON32_READ
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
end
always @ (*) begin
_rTxErr = TX_ERR;
end
// Transaction monitoring FSM.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXPORTMON32_NEXT : _rState);
end
always @ (*) begin
_rState = rState;
case (rState)
`S_TXPORTMON32_NEXT: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_TXN;
end
`S_TXPORTMON32_EVT_2: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_TXN;
end
`S_TXPORTMON32_TXN: begin // Don't read, wait until transaction has been acknowledged
if (ACK)
_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON32_END_0 : `S_TXPORTMON32_READ);
end
`S_TXPORTMON32_READ: begin // Continue reading, wait for end of transaction event or all expected data
if (rEvent)
_rState = `S_TXPORTMON32_END_1;
else if (wAllWordsRecvd | rTxErr)
_rState = `S_TXPORTMON32_END_0;
end
`S_TXPORTMON32_END_0: begin // Continue reading, wait for first end of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_END_1;
end
`S_TXPORTMON32_END_1: begin // Continue reading, wait for second end of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_NEXT;
end
default: begin
_rState = `S_TXPORTMON32_NEXT;
end
endcase
end
// Manage reading from the FIFO and tracking amounts read.
always @ (posedge CLK) begin
rRead <= #1 (RST ? 1'd0 : _rRead);
rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
rEvent <= #1 (RST ? 1'd0 : _rEvent);
rReadOffLast <= #1 _rReadOffLast;
rReadLen <= #1 _rReadLen;
rReadCount <= #1 (RST ? 1'd0 : _rReadCount);
rWordsRecvd <= #1 _rWordsRecvd;
rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
rAlmostFull <= #1 _rAlmostFull;
rLenEQ0Hi <= #1 _rLenEQ0Hi;
rLenEQ0Lo <= #1 _rLenEQ0Lo;
rLenLE1Lo <= #1 _rLenLE1Lo;
end
always @ (*) begin
// Don't get to the full point in the output FIFO
_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
// Track read history so we know when data is valid
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON32_TXN
// Track detected events
_rEvent = wEventData;
// Save event data when valid
if (wEventData) begin
_rReadOffLast = (rReadCount ? EVT_DATA[C_DATA_WIDTH-1:0] : rReadOffLast);
_rReadLen = (!rReadCount ? EVT_DATA[C_DATA_WIDTH-1:0] : rReadLen);
_rReadCount = rReadCount + 1'd1;
end
else begin
_rReadOffLast = rReadOffLast;
_rReadLen = rReadLen;
_rReadCount = rReadCount;
end
// If LEN == 0, we don't want to send any data to the output
_rLenEQ0Hi = (LEN[31:16] == 16'd0);
_rLenEQ0Lo = (LEN[15:0] == 16'd0);
// If LEN <= 1, we want to trigger the almost all received flag
_rLenLE1Lo = (LEN[15:0] <= 16'd1);
// Count received non-event data
_rWordsRecvd = (ACK ? 0 : rWordsRecvd + wPayloadData);
_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + wPayloadData);
_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({TXN, wPayloadData, wEventData, rState}),
.DATA({297'd0,
WR_COUNT, // 10
wPayloadData, // 1
EVT_DATA_RD_EN, // 1
RST, // 1
rTxErr, // 1
wEventData, // 1
rReadData, // 64
OFF, // 31
LEN, // 32
LAST, // 1
TXN, // 1
EVT_DATA_EMPTY, // 1
EVT_DATA, // 65
rState}) // 5
);
*/
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_monitor_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Detects transaction open/close events from the stream
// of data from the tx_port_channel_gate. Filters out events and passes data
// onto the tx_port_buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTMON32_NEXT 6'b00_0001
`define S_TXPORTMON32_EVT_2 6'b00_0010
`define S_TXPORTMON32_TXN 6'b00_0100
`define S_TXPORTMON32_READ 6'b00_1000
`define S_TXPORTMON32_END_0 6'b01_0000
`define S_TXPORTMON32_END_1 6'b10_0000
`timescale 1ns/1ns
module tx_port_monitor_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_VALID_HIST = 1
)
(
input RST,
input CLK,
input [C_DATA_WIDTH:0] EVT_DATA, // Event data from tx_port_channel_gate
input EVT_DATA_EMPTY, // Event data FIFO is empty
output EVT_DATA_RD_EN, // Event data FIFO read enable
output [C_DATA_WIDTH-1:0] WR_DATA, // Output data
output WR_EN, // Write enable for output data
input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Output FIFO count
output TXN, // Transaction parameters are valid
input ACK, // Transaction parameter read, continue
output LAST, // Channel last write
output [31:0] LEN, // Channel write length (in 32 bit words)
output [30:0] OFF, // Channel write offset
output [31:0] WORDS_RECVD, // Count of data words received in transaction
output DONE, // Transaction is closed
input TX_ERR // Transaction encountered an error
);
`include "functions.vh"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [5:0] rState=`S_TXPORTMON32_NEXT, _rState=`S_TXPORTMON32_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
reg [31:0] rReadOffLast=0, _rReadOffLast=0;
reg [31:0] rReadLen=0, _rReadLen=0;
reg rReadCount=0, _rReadCount=0;
reg [31:0] rWordsRecvd=0, _rWordsRecvd=0;
reg [31:0] rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
reg rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
reg rAlmostFull=0, _rAlmostFull=0;
reg rLenEQ0Hi=0, _rLenEQ0Hi=0;
reg rLenEQ0Lo=0, _rLenEQ0Lo=0;
reg rLenLE1Lo=0, _rLenLE1Lo=0;
reg rTxErr=0, _rTxErr=0;
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[3]); // S_TXPORTMON32_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE1Lo)) & wPayloadData);
assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData;
assign TXN = rState[2]; // S_TXPORTMON32_TXN
assign LAST = rReadOffLast[0];
assign OFF = rReadOffLast[31:1];
assign LEN = rReadLen;
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[3]; // !S_TXPORTMON32_READ
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
end
always @ (*) begin
_rTxErr = TX_ERR;
end
// Transaction monitoring FSM.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXPORTMON32_NEXT : _rState);
end
always @ (*) begin
_rState = rState;
case (rState)
`S_TXPORTMON32_NEXT: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_TXN;
end
`S_TXPORTMON32_EVT_2: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_TXN;
end
`S_TXPORTMON32_TXN: begin // Don't read, wait until transaction has been acknowledged
if (ACK)
_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON32_END_0 : `S_TXPORTMON32_READ);
end
`S_TXPORTMON32_READ: begin // Continue reading, wait for end of transaction event or all expected data
if (rEvent)
_rState = `S_TXPORTMON32_END_1;
else if (wAllWordsRecvd | rTxErr)
_rState = `S_TXPORTMON32_END_0;
end
`S_TXPORTMON32_END_0: begin // Continue reading, wait for first end of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_END_1;
end
`S_TXPORTMON32_END_1: begin // Continue reading, wait for second end of transaction event
if (rEvent)
_rState = `S_TXPORTMON32_NEXT;
end
default: begin
_rState = `S_TXPORTMON32_NEXT;
end
endcase
end
// Manage reading from the FIFO and tracking amounts read.
always @ (posedge CLK) begin
rRead <= #1 (RST ? 1'd0 : _rRead);
rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
rEvent <= #1 (RST ? 1'd0 : _rEvent);
rReadOffLast <= #1 _rReadOffLast;
rReadLen <= #1 _rReadLen;
rReadCount <= #1 (RST ? 1'd0 : _rReadCount);
rWordsRecvd <= #1 _rWordsRecvd;
rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
rAlmostFull <= #1 _rAlmostFull;
rLenEQ0Hi <= #1 _rLenEQ0Hi;
rLenEQ0Lo <= #1 _rLenEQ0Lo;
rLenLE1Lo <= #1 _rLenLE1Lo;
end
always @ (*) begin
// Don't get to the full point in the output FIFO
_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
// Track read history so we know when data is valid
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON32_TXN
// Track detected events
_rEvent = wEventData;
// Save event data when valid
if (wEventData) begin
_rReadOffLast = (rReadCount ? EVT_DATA[C_DATA_WIDTH-1:0] : rReadOffLast);
_rReadLen = (!rReadCount ? EVT_DATA[C_DATA_WIDTH-1:0] : rReadLen);
_rReadCount = rReadCount + 1'd1;
end
else begin
_rReadOffLast = rReadOffLast;
_rReadLen = rReadLen;
_rReadCount = rReadCount;
end
// If LEN == 0, we don't want to send any data to the output
_rLenEQ0Hi = (LEN[31:16] == 16'd0);
_rLenEQ0Lo = (LEN[15:0] == 16'd0);
// If LEN <= 1, we want to trigger the almost all received flag
_rLenLE1Lo = (LEN[15:0] <= 16'd1);
// Count received non-event data
_rWordsRecvd = (ACK ? 0 : rWordsRecvd + wPayloadData);
_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + wPayloadData);
_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({TXN, wPayloadData, wEventData, rState}),
.DATA({297'd0,
WR_COUNT, // 10
wPayloadData, // 1
EVT_DATA_RD_EN, // 1
RST, // 1
rTxErr, // 1
wEventData, // 1
rReadData, // 64
OFF, // 31
LEN, // 32
LAST, // 1
TXN, // 1
EVT_DATA_EMPTY, // 1
EVT_DATA, // 65
rState}) // 5
);
*/
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_wrcal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Write calibration logic to align DQS to correct CK edge
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $
**$Date: 2011/06/02 08:35:09 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_wrcal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 2500,
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps
)
(
input clk,
input rst,
// Calibration status, control signals
input wrcal_start,
input wrcal_rd_wait,
input wrcal_sanity_chk,
input dqsfound_retry_done,
input phy_rddata_en,
output dqsfound_retry,
output wrcal_read_req,
output reg wrcal_act_req,
output reg wrcal_done,
output reg wrcal_pat_err,
output reg wrcal_prech_req,
output reg temp_wrcal_done,
output reg wrcal_sanity_chk_done,
input prech_done,
// Captured data in resync clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Write level values of Phaser_Out coarse and fine
// delay taps required to load Phaser_Out register
input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
input wrlvl_byte_done,
output reg wrlvl_byte_redo,
output reg early1_data,
output reg early2_data,
// DQ IDELAY
output reg idelay_ld,
output reg wrcal_pat_resume, // to phy_init for write
output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt,
output phy_if_reset,
// Debug Port
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [99:0] dbg_phy_wrcal
);
// Length of calibration sequence (in # of words)
//localparam CAL_PAT_LEN = 8;
// Read data shift register length
localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2;
// # of reads for reliable read capture
localparam NUM_READS = 2;
// # of cycles to wait after changing RDEN count value
localparam RDEN_WAIT_CNT = 12;
localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6;
localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44;
localparam CAL2_IDLE = 4'h0;
localparam CAL2_READ_WAIT = 4'h1;
localparam CAL2_NEXT_DQS = 4'h2;
localparam CAL2_WRLVL_WAIT = 4'h3;
localparam CAL2_IFIFO_RESET = 4'h4;
localparam CAL2_DQ_IDEL_DEC = 4'h5;
localparam CAL2_DONE = 4'h6;
localparam CAL2_SANITY_WAIT = 4'h7;
localparam CAL2_ERR = 4'h8;
integer i,j,k,l,m,p,q,d;
reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1];
reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w;
reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1];
reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w;
(* keep = "true", max_fanout = 10 *) reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */;
reg [4:0] not_empty_wait_cnt;
reg [3:0] tap_inc_wait_cnt;
reg cal2_done_r;
reg cal2_done_r1;
reg cal2_prech_req_r;
reg [3:0] cal2_state_r;
reg [3:0] cal2_state_r1;
reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1];
reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1];
reg cal2_if_reset;
reg wrcal_pat_resume_r;
reg wrcal_pat_resume_r1;
reg wrcal_pat_resume_r2;
reg wrcal_pat_resume_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r;
reg pat_data_match_r;
reg pat1_data_match_r;
reg pat1_data_match_r1;
reg pat2_data_match_r;
reg pat_data_match_valid_r;
wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0];
reg [DRAM_WIDTH-1:0] pat_match_fall0_r;
reg pat_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall1_r;
reg pat_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall2_r;
reg pat_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall3_r;
reg pat_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise0_r;
reg pat_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise1_r;
reg pat_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise2_r;
reg pat_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise3_r;
reg pat_match_rise3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall1_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall1_r;
reg pat1_match_rise0_and_r;
reg pat1_match_rise1_and_r;
reg pat1_match_fall0_and_r;
reg pat1_match_fall1_and_r;
reg pat2_match_rise0_and_r;
reg pat2_match_rise1_and_r;
reg pat2_match_fall0_and_r;
reg pat2_match_fall1_and_r;
reg early1_data_match_r;
reg early1_data_match_r1;
reg [DRAM_WIDTH-1:0] early1_match_fall0_r;
reg early1_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall1_r;
reg early1_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall2_r;
reg early1_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall3_r;
reg early1_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise0_r;
reg early1_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise1_r;
reg early1_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise2_r;
reg early1_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise3_r;
reg early1_match_rise3_and_r;
reg early2_data_match_r;
reg [DRAM_WIDTH-1:0] early2_match_fall0_r;
reg early2_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall1_r;
reg early2_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall2_r;
reg early2_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall3_r;
reg early2_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise0_r;
reg early2_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise1_r;
reg early2_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise2_r;
reg early2_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise3_r;
reg early2_match_rise3_and_r;
wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0];
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;
reg rd_active_posedge_r;
reg rd_active_r;
reg rd_active_r1;
reg rd_active_r2;
reg rd_active_r3;
reg rd_active_r4;
reg rd_active_r5;
reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0];
reg wrlvl_byte_done_r;
reg idelay_ld_done;
reg pat1_detect;
reg early1_detect;
reg wrcal_sanity_chk_r;
reg wrcal_sanity_chk_err;
//***************************************************************************
// Debug
//***************************************************************************
always @(*) begin
for (d = 0; d < DQS_WIDTH; d = d + 1) begin
po_fine_tap_cnt_w[(6*d)+:6] <= #TCQ po_fine_tap_cnt[d];
po_coarse_tap_cnt_w[(3*d)+:3] <= #TCQ po_coarse_tap_cnt[d];
end
end
assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w;
assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w;
assign dbg_phy_wrcal[0] = pat_data_match_r;
assign dbg_phy_wrcal[4:1] = cal2_state_r1[2:0];
assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err;
assign dbg_phy_wrcal[6] = wrcal_start;
assign dbg_phy_wrcal[7] = wrcal_done;
assign dbg_phy_wrcal[8] = pat_data_match_valid_r;
assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r;
assign dbg_phy_wrcal[17+:5] = 'd0;
assign dbg_phy_wrcal[22+:5] = 'd0;
assign dbg_phy_wrcal[27] = 1'b0;
assign dbg_phy_wrcal[28+:5] = 'd0;
assign dbg_phy_wrcal[53:33] = 'b0;
assign dbg_phy_wrcal[54] = 1'b0;
assign dbg_phy_wrcal[55+:5] = 'd0;
assign dbg_phy_wrcal[60] = 1'b0;
assign dbg_phy_wrcal[61+:5] = 'd0;
assign dbg_phy_wrcal[66+:5] = not_empty_wait_cnt;
assign dbg_phy_wrcal[71] = early1_data;
assign dbg_phy_wrcal[72] = early2_data;
assign dqsfound_retry = 1'b0;
assign wrcal_read_req = 1'b0;
assign phy_if_reset = cal2_if_reset;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
always @(posedge clk) begin
po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r;
wrlvl_byte_done_r <= #TCQ wrlvl_byte_done;
wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk;
end
//***************************************************************************
// Data mux to route appropriate byte to calibration logic - i.e. calibration
// is done sequentially, one byte (or DQS group) at a time
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_rd_data_div4
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
end
endgenerate
//**************************************************************************
// Final Phaser OUT coarse and fine delay taps after write calibration
// Sum of taps used during write leveling taps and write calibration
//**************************************************************************
always @(*) begin
for (m = 0; m < DQS_WIDTH; m = m + 1) begin
wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3];
wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6];
end
end
always @(posedge clk) begin
if (rst) begin
for (p = 0; p < DQS_WIDTH; p = p + 1) begin
po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}};
po_fine_tap_cnt[p] <= #TCQ {6{1'b0}};
end
end else if (cal2_done_r && ~cal2_done_r1) begin
for (q = 0; q < DQS_WIDTH; q = q + 1) begin
po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i];
po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i];
end
end
end
always @(posedge clk) begin
rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r;
end
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
generate
genvar mux_i;
if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end
endgenerate
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
wrcal_prech_req <= #TCQ 1'b0;
else
// Combine requests from all stages here
wrcal_prech_req <= #TCQ cal2_prech_req_r;
//***************************************************************************
// Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
// NOTE: Written using discrete flops, but SRL can be used if the matching
// logic does the comparison sequentially, rather than parallel
//***************************************************************************
generate
genvar rd_i;
if (nCK_PER_CLK == 4) begin: gen_sr_div4
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];
sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];
sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];
sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_sr_div2
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
end
end
end
endgenerate
//***************************************************************************
// Write calibration:
// During write leveling DQS is aligned to the nearest CK edge that may not
// be the correct CK edge. Write calibration is required to align the DQS to
// the correct CK edge that clocks the write command.
// The Phaser_Out coarse delay line is adjusted if required to add a memory
// clock cycle of delay in order to read back the expected pattern.
//***************************************************************************
always @(posedge clk) begin
rd_active_r <= #TCQ phy_rddata_en;
rd_active_r1 <= #TCQ rd_active_r;
rd_active_r2 <= #TCQ rd_active_r1;
rd_active_r3 <= #TCQ rd_active_r2;
rd_active_r4 <= #TCQ rd_active_r3;
rd_active_r5 <= #TCQ rd_active_r4;
end
//*****************************************************************
// Expected data pattern when properly received by read capture
// logic:
// Based on pattern of ({rise,fall}) =
// 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
// Each nibble will look like:
// bit3: 1, 0, 1, 0, 0, 1, 1, 0
// bit2: 1, 0, 0, 1, 1, 0, 0, 1
// bit1: 1, 0, 1, 0, 0, 1, 0, 1
// bit0: 1, 0, 0, 1, 1, 0, 1, 0
// Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
// and the actual training pattern contents change
//*****************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_pat_div4
// FF00AA5555AA9966
assign pat_rise0[3] = 1'b1;
assign pat_fall0[3] = 1'b0;
assign pat_rise1[3] = 1'b1;
assign pat_fall1[3] = 1'b0;
assign pat_rise2[3] = 1'b0;
assign pat_fall2[3] = 1'b1;
assign pat_rise3[3] = 1'b1;
assign pat_fall3[3] = 1'b0;
assign pat_rise0[2] = 1'b1;
assign pat_fall0[2] = 1'b0;
assign pat_rise1[2] = 1'b0;
assign pat_fall1[2] = 1'b1;
assign pat_rise2[2] = 1'b1;
assign pat_fall2[2] = 1'b0;
assign pat_rise3[2] = 1'b0;
assign pat_fall3[2] = 1'b1;
assign pat_rise0[1] = 1'b1;
assign pat_fall0[1] = 1'b0;
assign pat_rise1[1] = 1'b1;
assign pat_fall1[1] = 1'b0;
assign pat_rise2[1] = 1'b0;
assign pat_fall2[1] = 1'b1;
assign pat_rise3[1] = 1'b0;
assign pat_fall3[1] = 1'b1;
assign pat_rise0[0] = 1'b1;
assign pat_fall0[0] = 1'b0;
assign pat_rise1[0] = 1'b0;
assign pat_fall1[0] = 1'b1;
assign pat_rise2[0] = 1'b1;
assign pat_fall2[0] = 1'b0;
assign pat_rise3[0] = 1'b1;
assign pat_fall3[0] = 1'b0;
// Pattern to distinguish between early write and incorrect read
// BB11EE4444EEDD88
assign early_rise0[3] = 1'b1;
assign early_fall0[3] = 1'b0;
assign early_rise1[3] = 1'b1;
assign early_fall1[3] = 1'b0;
assign early_rise2[3] = 1'b0;
assign early_fall2[3] = 1'b1;
assign early_rise3[3] = 1'b1;
assign early_fall3[3] = 1'b1;
assign early_rise0[2] = 1'b0;
assign early_fall0[2] = 1'b0;
assign early_rise1[2] = 1'b1;
assign early_fall1[2] = 1'b1;
assign early_rise2[2] = 1'b1;
assign early_fall2[2] = 1'b1;
assign early_rise3[2] = 1'b1;
assign early_fall3[2] = 1'b0;
assign early_rise0[1] = 1'b1;
assign early_fall0[1] = 1'b0;
assign early_rise1[1] = 1'b1;
assign early_fall1[1] = 1'b0;
assign early_rise2[1] = 1'b0;
assign early_fall2[1] = 1'b1;
assign early_rise3[1] = 1'b0;
assign early_fall3[1] = 1'b0;
assign early_rise0[0] = 1'b1;
assign early_fall0[0] = 1'b1;
assign early_rise1[0] = 1'b0;
assign early_fall1[0] = 1'b0;
assign early_rise2[0] = 1'b0;
assign early_fall2[0] = 1'b0;
assign early_rise3[0] = 1'b1;
assign early_fall3[0] = 1'b0;
end else if (nCK_PER_CLK == 2) begin: gen_pat_div2
// First cycle pattern FF00AA55
assign pat1_rise0[3] = 1'b1;
assign pat1_fall0[3] = 1'b0;
assign pat1_rise1[3] = 1'b1;
assign pat1_fall1[3] = 1'b0;
assign pat1_rise0[2] = 1'b1;
assign pat1_fall0[2] = 1'b0;
assign pat1_rise1[2] = 1'b0;
assign pat1_fall1[2] = 1'b1;
assign pat1_rise0[1] = 1'b1;
assign pat1_fall0[1] = 1'b0;
assign pat1_rise1[1] = 1'b1;
assign pat1_fall1[1] = 1'b0;
assign pat1_rise0[0] = 1'b1;
assign pat1_fall0[0] = 1'b0;
assign pat1_rise1[0] = 1'b0;
assign pat1_fall1[0] = 1'b1;
// Second cycle pattern 55AA9966
assign pat2_rise0[3] = 1'b0;
assign pat2_fall0[3] = 1'b1;
assign pat2_rise1[3] = 1'b1;
assign pat2_fall1[3] = 1'b0;
assign pat2_rise0[2] = 1'b1;
assign pat2_fall0[2] = 1'b0;
assign pat2_rise1[2] = 1'b0;
assign pat2_fall1[2] = 1'b1;
assign pat2_rise0[1] = 1'b0;
assign pat2_fall0[1] = 1'b1;
assign pat2_rise1[1] = 1'b0;
assign pat2_fall1[1] = 1'b1;
assign pat2_rise0[0] = 1'b1;
assign pat2_fall0[0] = 1'b0;
assign pat2_rise1[0] = 1'b1;
assign pat2_fall1[0] = 1'b0;
//Pattern to distinguish between early write and incorrect read
// First cycle pattern AA5555AA
assign early1_rise0[3] = 2'b1;
assign early1_fall0[3] = 2'b0;
assign early1_rise1[3] = 2'b0;
assign early1_fall1[3] = 2'b1;
assign early1_rise0[2] = 2'b0;
assign early1_fall0[2] = 2'b1;
assign early1_rise1[2] = 2'b1;
assign early1_fall1[2] = 2'b0;
assign early1_rise0[1] = 2'b1;
assign early1_fall0[1] = 2'b0;
assign early1_rise1[1] = 2'b0;
assign early1_fall1[1] = 2'b1;
assign early1_rise0[0] = 2'b0;
assign early1_fall0[0] = 2'b1;
assign early1_rise1[0] = 2'b1;
assign early1_fall1[0] = 2'b0;
// Second cycle pattern 9966BB11
assign early2_rise0[3] = 2'b1;
assign early2_fall0[3] = 2'b0;
assign early2_rise1[3] = 2'b1;
assign early2_fall1[3] = 2'b0;
assign early2_rise0[2] = 2'b0;
assign early2_fall0[2] = 2'b1;
assign early2_rise1[2] = 2'b0;
assign early2_fall1[2] = 2'b0;
assign early2_rise0[1] = 2'b0;
assign early2_fall0[1] = 2'b1;
assign early2_rise1[1] = 2'b1;
assign early2_fall1[1] = 2'b0;
assign early2_rise0[0] = 2'b1;
assign early2_fall0[0] = 2'b0;
assign early2_rise1[0] = 2'b1;
assign early2_fall1[0] = 2'b1;
end
endgenerate
// Each bit of each byte is compared to expected pattern.
// This was done to prevent (and "drastically decrease") the chance that
// invalid data clocked in when the DQ bus is tri-state (along with a
// combination of the correct data) will resemble the expected data
// pattern. A better fix for this is to change the training pattern and/or
// make the pattern longer.
generate
genvar pt_i;
if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4])
pat_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4])
pat_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4])
pat_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4])
pat_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4])
pat_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4])
pat_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4])
pat_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4])
pat_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4])
early1_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4])
early1_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise0[pt_i%4])
early1_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall0[pt_i%4])
early1_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == early_rise0[pt_i%4])
early2_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == early_fall0[pt_i%4])
early2_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise1[pt_i%4])
early2_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall1[pt_i%4])
early2_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r;
pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r;
pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r;
pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r;
pat_data_match_r <= #TCQ (pat_match_rise0_and_r &&
pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r &&
pat_match_rise2_and_r &&
pat_match_fall2_and_r &&
pat_match_rise3_and_r &&
pat_match_fall3_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r3;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r;
early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r;
early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r;
early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r &&
early1_match_rise2_and_r &&
early1_match_fall2_and_r &&
early1_match_rise3_and_r &&
early1_match_fall3_and_r);
end
always @(posedge clk) begin
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r;
early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r;
early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r;
early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r;
early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r &&
early2_match_rise2_and_r &&
early2_match_fall2_and_r &&
early2_match_rise3_and_r &&
early2_match_fall3_and_r);
end
end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4])
pat2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4])
pat2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4])
pat2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4])
pat2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
// early2 in this case does not mean 2 cycles early but
// the second cycle of read data in 2:1 mode
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r);
pat1_data_match_r1 <= #TCQ pat1_data_match_r;
pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3;
pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3;
pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3;
pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3;
pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r &&
pat2_match_fall0_and_r &&
pat2_match_rise1_and_r &&
pat2_match_fall1_and_r);
// For 2:1 mode, read valid is asserted for 2 clock cycles -
// here we generate a "match valid" pulse that is only 1 clock
// cycle wide that is simulatenous when the match calculation
// is complete
pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r);
early1_data_match_r1 <= #TCQ early1_data_match_r;
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r);
end
end
endgenerate
// Need to delay it by 3 cycles in order to wait for Phaser_Out
// coarse delay to take effect before issuing a write command
always @(posedge clk) begin
wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r;
wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1;
wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2;
end
always @(posedge clk) begin
if (rst)
tap_inc_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) ||
(cal2_state_r == CAL2_IFIFO_RESET) ||
(cal2_state_r == CAL2_SANITY_WAIT))
tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1;
else
tap_inc_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk) begin
if (rst)
not_empty_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait)
not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1;
else
not_empty_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk)
cal2_state_r1 <= #TCQ cal2_state_r;
//*****************************************************************
// Write Calibration state machine
//*****************************************************************
// when calibrating, check to see if the expected pattern is received.
// Otherwise delay DQS to align to correct CK edge.
// NOTES:
// 1. An error condition can occur due to two reasons:
// a. If the matching logic does not receive the expected data
// pattern. However, the error may be "recoverable" because
// the write calibration is still in progress. If an error is
// found the write calibration logic delays DQS by an additional
// clock cycle and restarts the pattern detection process.
// By design, if the write path timing is incorrect, the correct
// data pattern will never be detected.
// b. Valid data not found even after incrementing Phaser_Out
// coarse delay line.
always @(posedge clk) begin
if (rst) begin
wrcal_dqs_cnt_r <= #TCQ 'b0;
cal2_done_r <= #TCQ 1'b0;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IDLE;
wrcal_pat_err <= #TCQ 1'b0;
wrcal_pat_resume_r <= #TCQ 1'b0;
wrcal_act_req <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
temp_wrcal_done <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b0;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
idelay_ld <= #TCQ 1'b0;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
early1_detect <= #TCQ 1'b0;
wrcal_sanity_chk_done <= #TCQ 1'b0;
wrcal_sanity_chk_err <= #TCQ 1'b0;
end else begin
cal2_prech_req_r <= #TCQ 1'b0;
case (cal2_state_r)
CAL2_IDLE: begin
wrcal_pat_err <= #TCQ 1'b0;
if (wrcal_start) begin
cal2_if_reset <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "SKIP_CAL")
// If skip write calibration, then proceed to end.
cal2_state_r <= #TCQ CAL2_DONE;
else
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
// General wait state to wait for read data to be output by the
// IN_FIFO
CAL2_READ_WAIT: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
// Wait until read data is received, and pattern matching
// calculation is complete. NOTE: Need to add a timeout here
// in case for some reason data is never received (or rather
// the PHASER_IN and IN_FIFO think they never receives data)
if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin
if (pat_data_match_r)
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else begin
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
// If writes are one or two cycles early then redo
// write leveling for the byte
else if (early1_data_match_r) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early2_data_match_r) begin
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b1;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin
if ((pat1_data_match_r1 && pat2_data_match_r) ||
(pat1_detect && pat2_data_match_r))
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else if (pat1_data_match_r1 && ~pat2_data_match_r) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
pat1_detect <= #TCQ 1'b1;
end else begin
// If writes are one or two cycles early then redo
// write leveling for the byte
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
else if ((early1_data_match_r1 && early2_data_match_r) ||
(early1_detect && early2_data_match_r)) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early1_data_match_r1 && ~early2_data_match_r) begin
early1_detect <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (not_empty_wait_cnt == 'd31)
cal2_state_r <= #TCQ CAL2_ERR;
end
CAL2_WRLVL_WAIT: begin
early1_detect <= #TCQ 1'b0;
if (wrlvl_byte_done && ~wrlvl_byte_done_r)
wrlvl_byte_redo <= #TCQ 1'b0;
if (wrlvl_byte_done) begin
if (rd_active_r1 && ~rd_active_r) begin
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
end
end
end
CAL2_DQ_IDEL_DEC: begin
if (tap_inc_wait_cnt == 'd4) begin
idelay_ld <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b1;
end
end
CAL2_IFIFO_RESET: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_DONE;
else if (idelay_ld_done) begin
wrcal_pat_resume_r <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end else
cal2_state_r <= #TCQ CAL2_IDLE;
end
end
// Final processing for current DQS group. Move on to next group
CAL2_NEXT_DQS: begin
// At this point, we've just found the correct pattern for the
// current DQS group.
// Request bank/row precharge, and wait for its completion. Always
// precharge after each DQS group to avoid tRAS(max) violation
if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin
cal2_prech_req_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_SANITY_WAIT;
end else
cal2_prech_req_r <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
if (prech_done)
if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) ||
(wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin
// If either FAST_CAL is enabled and first DQS group is
// finished, or if the last DQS group was just finished,
// then end of write calibration
if (wrcal_sanity_chk_r) begin
cal2_if_reset <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
end else
cal2_state_r <= #TCQ CAL2_DONE;
end else begin
// Continue to next DQS group
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
CAL2_SANITY_WAIT: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
wrcal_pat_resume_r <= #TCQ 1'b1;
end
end
// Finished with read enable calibration
CAL2_DONE: begin
if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin
cal2_done_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ 'd0;
cal2_state_r <= #TCQ CAL2_IDLE;
end else
cal2_done_r <= #TCQ 1'b1;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_done <= #TCQ 1'b1;
end
// Assert error signal indicating that writes timing is incorrect
CAL2_ERR: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_err <= #TCQ 1'b1;
else
wrcal_pat_err <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_ERR;
end
endcase
end
end
// Delay assertion of wrcal_done for write calibration by a few cycles after
// we've reached CAL2_DONE
always @(posedge clk)
if (rst)
cal2_done_r1 <= #TCQ 1'b0;
else
cal2_done_r1 <= #TCQ cal2_done_r;
always @(posedge clk)
if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r))
wrcal_done <= #TCQ 1'b0;
else if (cal2_done_r)
wrcal_done <= #TCQ 1'b1;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// related to, arising under or in connection with these
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_wrcal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:09 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Write calibration logic to align DQS to correct CK edge
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $
**$Date: 2011/06/02 08:35:09 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_wrcal #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 2500,
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter SIM_CAL_OPTION = "NONE" // Skip various calibration steps
)
(
input clk,
input rst,
// Calibration status, control signals
input wrcal_start,
input wrcal_rd_wait,
input wrcal_sanity_chk,
input dqsfound_retry_done,
input phy_rddata_en,
output dqsfound_retry,
output wrcal_read_req,
output reg wrcal_act_req,
output reg wrcal_done,
output reg wrcal_pat_err,
output reg wrcal_prech_req,
output reg temp_wrcal_done,
output reg wrcal_sanity_chk_done,
input prech_done,
// Captured data in resync clock domain
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Write level values of Phaser_Out coarse and fine
// delay taps required to load Phaser_Out register
input [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,
input [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
input wrlvl_byte_done,
output reg wrlvl_byte_redo,
output reg early1_data,
output reg early2_data,
// DQ IDELAY
output reg idelay_ld,
output reg wrcal_pat_resume, // to phy_init for write
output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt,
output phy_if_reset,
// Debug Port
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [99:0] dbg_phy_wrcal
);
// Length of calibration sequence (in # of words)
//localparam CAL_PAT_LEN = 8;
// Read data shift register length
localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2;
// # of reads for reliable read capture
localparam NUM_READS = 2;
// # of cycles to wait after changing RDEN count value
localparam RDEN_WAIT_CNT = 12;
localparam COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6;
localparam FINE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44;
localparam CAL2_IDLE = 4'h0;
localparam CAL2_READ_WAIT = 4'h1;
localparam CAL2_NEXT_DQS = 4'h2;
localparam CAL2_WRLVL_WAIT = 4'h3;
localparam CAL2_IFIFO_RESET = 4'h4;
localparam CAL2_DQ_IDEL_DEC = 4'h5;
localparam CAL2_DONE = 4'h6;
localparam CAL2_SANITY_WAIT = 4'h7;
localparam CAL2_ERR = 4'h8;
integer i,j,k,l,m,p,q,d;
reg [2:0] po_coarse_tap_cnt [0:DQS_WIDTH-1];
reg [3*DQS_WIDTH-1:0] po_coarse_tap_cnt_w;
reg [5:0] po_fine_tap_cnt [0:DQS_WIDTH-1];
reg [6*DQS_WIDTH-1:0] po_fine_tap_cnt_w;
(* keep = "true", max_fanout = 10 *) reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */;
reg [4:0] not_empty_wait_cnt;
reg [3:0] tap_inc_wait_cnt;
reg cal2_done_r;
reg cal2_done_r1;
reg cal2_prech_req_r;
reg [3:0] cal2_state_r;
reg [3:0] cal2_state_r1;
reg [2:0] wl_po_coarse_cnt_w [0:DQS_WIDTH-1];
reg [5:0] wl_po_fine_cnt_w [0:DQS_WIDTH-1];
reg cal2_if_reset;
reg wrcal_pat_resume_r;
reg wrcal_pat_resume_r1;
reg wrcal_pat_resume_r2;
reg wrcal_pat_resume_r3;
reg [DRAM_WIDTH-1:0] mux_rd_fall0_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall1_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise0_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise1_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall2_r;
reg [DRAM_WIDTH-1:0] mux_rd_fall3_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise2_r;
reg [DRAM_WIDTH-1:0] mux_rd_rise3_r;
reg pat_data_match_r;
reg pat1_data_match_r;
reg pat1_data_match_r1;
reg pat2_data_match_r;
reg pat_data_match_valid_r;
wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0];
reg [DRAM_WIDTH-1:0] pat_match_fall0_r;
reg pat_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall1_r;
reg pat_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall2_r;
reg pat_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_fall3_r;
reg pat_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise0_r;
reg pat_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise1_r;
reg pat_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise2_r;
reg pat_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] pat_match_rise3_r;
reg pat_match_rise3_and_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat1_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat1_match_fall1_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise0_r;
reg [DRAM_WIDTH-1:0] pat2_match_rise1_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall0_r;
reg [DRAM_WIDTH-1:0] pat2_match_fall1_r;
reg pat1_match_rise0_and_r;
reg pat1_match_rise1_and_r;
reg pat1_match_fall0_and_r;
reg pat1_match_fall1_and_r;
reg pat2_match_rise0_and_r;
reg pat2_match_rise1_and_r;
reg pat2_match_fall0_and_r;
reg pat2_match_fall1_and_r;
reg early1_data_match_r;
reg early1_data_match_r1;
reg [DRAM_WIDTH-1:0] early1_match_fall0_r;
reg early1_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall1_r;
reg early1_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall2_r;
reg early1_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_fall3_r;
reg early1_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise0_r;
reg early1_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise1_r;
reg early1_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise2_r;
reg early1_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early1_match_rise3_r;
reg early1_match_rise3_and_r;
reg early2_data_match_r;
reg [DRAM_WIDTH-1:0] early2_match_fall0_r;
reg early2_match_fall0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall1_r;
reg early2_match_fall1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall2_r;
reg early2_match_fall2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_fall3_r;
reg early2_match_fall3_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise0_r;
reg early2_match_rise0_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise1_r;
reg early2_match_rise1_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise2_r;
reg early2_match_rise2_and_r;
reg [DRAM_WIDTH-1:0] early2_match_rise3_r;
reg early2_match_rise3_and_r;
wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0];
wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0];
wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0];
wire [DQ_WIDTH-1:0] rd_data_rise0;
wire [DQ_WIDTH-1:0] rd_data_fall0;
wire [DQ_WIDTH-1:0] rd_data_rise1;
wire [DQ_WIDTH-1:0] rd_data_fall1;
wire [DQ_WIDTH-1:0] rd_data_rise2;
wire [DQ_WIDTH-1:0] rd_data_fall2;
wire [DQ_WIDTH-1:0] rd_data_rise3;
wire [DQ_WIDTH-1:0] rd_data_fall3;
reg [DQS_CNT_WIDTH:0] rd_mux_sel_r;
reg rd_active_posedge_r;
reg rd_active_r;
reg rd_active_r1;
reg rd_active_r2;
reg rd_active_r3;
reg rd_active_r4;
reg rd_active_r5;
reg [RD_SHIFT_LEN-1:0] sr_fall0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise0_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise1_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_fall3_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise2_r [DRAM_WIDTH-1:0];
reg [RD_SHIFT_LEN-1:0] sr_rise3_r [DRAM_WIDTH-1:0];
reg wrlvl_byte_done_r;
reg idelay_ld_done;
reg pat1_detect;
reg early1_detect;
reg wrcal_sanity_chk_r;
reg wrcal_sanity_chk_err;
//***************************************************************************
// Debug
//***************************************************************************
always @(*) begin
for (d = 0; d < DQS_WIDTH; d = d + 1) begin
po_fine_tap_cnt_w[(6*d)+:6] <= #TCQ po_fine_tap_cnt[d];
po_coarse_tap_cnt_w[(3*d)+:3] <= #TCQ po_coarse_tap_cnt[d];
end
end
assign dbg_final_po_fine_tap_cnt = po_fine_tap_cnt_w;
assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w;
assign dbg_phy_wrcal[0] = pat_data_match_r;
assign dbg_phy_wrcal[4:1] = cal2_state_r1[2:0];
assign dbg_phy_wrcal[5] = wrcal_sanity_chk_err;
assign dbg_phy_wrcal[6] = wrcal_start;
assign dbg_phy_wrcal[7] = wrcal_done;
assign dbg_phy_wrcal[8] = pat_data_match_valid_r;
assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r;
assign dbg_phy_wrcal[17+:5] = 'd0;
assign dbg_phy_wrcal[22+:5] = 'd0;
assign dbg_phy_wrcal[27] = 1'b0;
assign dbg_phy_wrcal[28+:5] = 'd0;
assign dbg_phy_wrcal[53:33] = 'b0;
assign dbg_phy_wrcal[54] = 1'b0;
assign dbg_phy_wrcal[55+:5] = 'd0;
assign dbg_phy_wrcal[60] = 1'b0;
assign dbg_phy_wrcal[61+:5] = 'd0;
assign dbg_phy_wrcal[66+:5] = not_empty_wait_cnt;
assign dbg_phy_wrcal[71] = early1_data;
assign dbg_phy_wrcal[72] = early2_data;
assign dqsfound_retry = 1'b0;
assign wrcal_read_req = 1'b0;
assign phy_if_reset = cal2_if_reset;
//**************************************************************************
// DQS count to hard PHY during write calibration using Phaser_OUT Stage2
// coarse delay
//**************************************************************************
always @(posedge clk) begin
po_stg2_wrcal_cnt <= #TCQ wrcal_dqs_cnt_r;
wrlvl_byte_done_r <= #TCQ wrlvl_byte_done;
wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk;
end
//***************************************************************************
// Data mux to route appropriate byte to calibration logic - i.e. calibration
// is done sequentially, one byte (or DQS group) at a time
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_rd_data_div4
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2
assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
end
endgenerate
//**************************************************************************
// Final Phaser OUT coarse and fine delay taps after write calibration
// Sum of taps used during write leveling taps and write calibration
//**************************************************************************
always @(*) begin
for (m = 0; m < DQS_WIDTH; m = m + 1) begin
wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3];
wl_po_fine_cnt_w[m] = wl_po_fine_cnt[6*m+:6];
end
end
always @(posedge clk) begin
if (rst) begin
for (p = 0; p < DQS_WIDTH; p = p + 1) begin
po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}};
po_fine_tap_cnt[p] <= #TCQ {6{1'b0}};
end
end else if (cal2_done_r && ~cal2_done_r1) begin
for (q = 0; q < DQS_WIDTH; q = q + 1) begin
po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i];
po_fine_tap_cnt[q] <= #TCQ wl_po_fine_cnt_w[i];
end
end
end
always @(posedge clk) begin
rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r;
end
// Register outputs for improved timing.
// NOTE: Will need to change when per-bit DQ deskew is supported.
// Currenly all bits in DQS group are checked in aggregate
generate
genvar mux_i;
if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2
for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
always @(posedge clk) begin
mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
end
end
end
endgenerate
//***************************************************************************
// generate request to PHY_INIT logic to issue precharged. Required when
// calibration can take a long time (during which there are only constant
// reads present on this bus). In this case need to issue perioidic
// precharges to avoid tRAS violation. This signal must meet the following
// requirements: (1) only transition from 0->1 when prech is first needed,
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
//***************************************************************************
always @(posedge clk)
if (rst)
wrcal_prech_req <= #TCQ 1'b0;
else
// Combine requests from all stages here
wrcal_prech_req <= #TCQ cal2_prech_req_r;
//***************************************************************************
// Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
// NOTE: Written using discrete flops, but SRL can be used if the matching
// logic does the comparison sequentially, rather than parallel
//***************************************************************************
generate
genvar rd_i;
if (nCK_PER_CLK == 4) begin: gen_sr_div4
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];
sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];
sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];
sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];
end
end
end else if (nCK_PER_CLK == 2) begin: gen_sr_div2
for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
always @(posedge clk) begin
sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
end
end
end
endgenerate
//***************************************************************************
// Write calibration:
// During write leveling DQS is aligned to the nearest CK edge that may not
// be the correct CK edge. Write calibration is required to align the DQS to
// the correct CK edge that clocks the write command.
// The Phaser_Out coarse delay line is adjusted if required to add a memory
// clock cycle of delay in order to read back the expected pattern.
//***************************************************************************
always @(posedge clk) begin
rd_active_r <= #TCQ phy_rddata_en;
rd_active_r1 <= #TCQ rd_active_r;
rd_active_r2 <= #TCQ rd_active_r1;
rd_active_r3 <= #TCQ rd_active_r2;
rd_active_r4 <= #TCQ rd_active_r3;
rd_active_r5 <= #TCQ rd_active_r4;
end
//*****************************************************************
// Expected data pattern when properly received by read capture
// logic:
// Based on pattern of ({rise,fall}) =
// 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
// Each nibble will look like:
// bit3: 1, 0, 1, 0, 0, 1, 1, 0
// bit2: 1, 0, 0, 1, 1, 0, 0, 1
// bit1: 1, 0, 1, 0, 0, 1, 0, 1
// bit0: 1, 0, 0, 1, 1, 0, 1, 0
// Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
// and the actual training pattern contents change
//*****************************************************************
generate
if (nCK_PER_CLK == 4) begin: gen_pat_div4
// FF00AA5555AA9966
assign pat_rise0[3] = 1'b1;
assign pat_fall0[3] = 1'b0;
assign pat_rise1[3] = 1'b1;
assign pat_fall1[3] = 1'b0;
assign pat_rise2[3] = 1'b0;
assign pat_fall2[3] = 1'b1;
assign pat_rise3[3] = 1'b1;
assign pat_fall3[3] = 1'b0;
assign pat_rise0[2] = 1'b1;
assign pat_fall0[2] = 1'b0;
assign pat_rise1[2] = 1'b0;
assign pat_fall1[2] = 1'b1;
assign pat_rise2[2] = 1'b1;
assign pat_fall2[2] = 1'b0;
assign pat_rise3[2] = 1'b0;
assign pat_fall3[2] = 1'b1;
assign pat_rise0[1] = 1'b1;
assign pat_fall0[1] = 1'b0;
assign pat_rise1[1] = 1'b1;
assign pat_fall1[1] = 1'b0;
assign pat_rise2[1] = 1'b0;
assign pat_fall2[1] = 1'b1;
assign pat_rise3[1] = 1'b0;
assign pat_fall3[1] = 1'b1;
assign pat_rise0[0] = 1'b1;
assign pat_fall0[0] = 1'b0;
assign pat_rise1[0] = 1'b0;
assign pat_fall1[0] = 1'b1;
assign pat_rise2[0] = 1'b1;
assign pat_fall2[0] = 1'b0;
assign pat_rise3[0] = 1'b1;
assign pat_fall3[0] = 1'b0;
// Pattern to distinguish between early write and incorrect read
// BB11EE4444EEDD88
assign early_rise0[3] = 1'b1;
assign early_fall0[3] = 1'b0;
assign early_rise1[3] = 1'b1;
assign early_fall1[3] = 1'b0;
assign early_rise2[3] = 1'b0;
assign early_fall2[3] = 1'b1;
assign early_rise3[3] = 1'b1;
assign early_fall3[3] = 1'b1;
assign early_rise0[2] = 1'b0;
assign early_fall0[2] = 1'b0;
assign early_rise1[2] = 1'b1;
assign early_fall1[2] = 1'b1;
assign early_rise2[2] = 1'b1;
assign early_fall2[2] = 1'b1;
assign early_rise3[2] = 1'b1;
assign early_fall3[2] = 1'b0;
assign early_rise0[1] = 1'b1;
assign early_fall0[1] = 1'b0;
assign early_rise1[1] = 1'b1;
assign early_fall1[1] = 1'b0;
assign early_rise2[1] = 1'b0;
assign early_fall2[1] = 1'b1;
assign early_rise3[1] = 1'b0;
assign early_fall3[1] = 1'b0;
assign early_rise0[0] = 1'b1;
assign early_fall0[0] = 1'b1;
assign early_rise1[0] = 1'b0;
assign early_fall1[0] = 1'b0;
assign early_rise2[0] = 1'b0;
assign early_fall2[0] = 1'b0;
assign early_rise3[0] = 1'b1;
assign early_fall3[0] = 1'b0;
end else if (nCK_PER_CLK == 2) begin: gen_pat_div2
// First cycle pattern FF00AA55
assign pat1_rise0[3] = 1'b1;
assign pat1_fall0[3] = 1'b0;
assign pat1_rise1[3] = 1'b1;
assign pat1_fall1[3] = 1'b0;
assign pat1_rise0[2] = 1'b1;
assign pat1_fall0[2] = 1'b0;
assign pat1_rise1[2] = 1'b0;
assign pat1_fall1[2] = 1'b1;
assign pat1_rise0[1] = 1'b1;
assign pat1_fall0[1] = 1'b0;
assign pat1_rise1[1] = 1'b1;
assign pat1_fall1[1] = 1'b0;
assign pat1_rise0[0] = 1'b1;
assign pat1_fall0[0] = 1'b0;
assign pat1_rise1[0] = 1'b0;
assign pat1_fall1[0] = 1'b1;
// Second cycle pattern 55AA9966
assign pat2_rise0[3] = 1'b0;
assign pat2_fall0[3] = 1'b1;
assign pat2_rise1[3] = 1'b1;
assign pat2_fall1[3] = 1'b0;
assign pat2_rise0[2] = 1'b1;
assign pat2_fall0[2] = 1'b0;
assign pat2_rise1[2] = 1'b0;
assign pat2_fall1[2] = 1'b1;
assign pat2_rise0[1] = 1'b0;
assign pat2_fall0[1] = 1'b1;
assign pat2_rise1[1] = 1'b0;
assign pat2_fall1[1] = 1'b1;
assign pat2_rise0[0] = 1'b1;
assign pat2_fall0[0] = 1'b0;
assign pat2_rise1[0] = 1'b1;
assign pat2_fall1[0] = 1'b0;
//Pattern to distinguish between early write and incorrect read
// First cycle pattern AA5555AA
assign early1_rise0[3] = 2'b1;
assign early1_fall0[3] = 2'b0;
assign early1_rise1[3] = 2'b0;
assign early1_fall1[3] = 2'b1;
assign early1_rise0[2] = 2'b0;
assign early1_fall0[2] = 2'b1;
assign early1_rise1[2] = 2'b1;
assign early1_fall1[2] = 2'b0;
assign early1_rise0[1] = 2'b1;
assign early1_fall0[1] = 2'b0;
assign early1_rise1[1] = 2'b0;
assign early1_fall1[1] = 2'b1;
assign early1_rise0[0] = 2'b0;
assign early1_fall0[0] = 2'b1;
assign early1_rise1[0] = 2'b1;
assign early1_fall1[0] = 2'b0;
// Second cycle pattern 9966BB11
assign early2_rise0[3] = 2'b1;
assign early2_fall0[3] = 2'b0;
assign early2_rise1[3] = 2'b1;
assign early2_fall1[3] = 2'b0;
assign early2_rise0[2] = 2'b0;
assign early2_fall0[2] = 2'b1;
assign early2_rise1[2] = 2'b0;
assign early2_fall1[2] = 2'b0;
assign early2_rise0[1] = 2'b0;
assign early2_fall0[1] = 2'b1;
assign early2_rise1[1] = 2'b1;
assign early2_fall1[1] = 2'b0;
assign early2_rise0[0] = 2'b1;
assign early2_fall0[0] = 2'b0;
assign early2_rise1[0] = 2'b1;
assign early2_fall1[0] = 2'b1;
end
endgenerate
// Each bit of each byte is compared to expected pattern.
// This was done to prevent (and "drastically decrease") the chance that
// invalid data clocked in when the DQ bus is tri-state (along with a
// combination of the correct data) will resemble the expected data
// pattern. A better fix for this is to change the training pattern and/or
// make the pattern longer.
generate
genvar pt_i;
if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise0[pt_i%4])
pat_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall0[pt_i%4])
pat_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise1[pt_i%4])
pat_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall1[pt_i%4])
pat_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise2[pt_i%4])
pat_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall2[pt_i%4])
pat_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == pat_rise3[pt_i%4])
pat_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == pat_fall3[pt_i%4])
pat_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
pat_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise1[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall1[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise2[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall2[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == pat_rise3[pt_i%4])
early1_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == pat_fall3[pt_i%4])
early1_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise0[pt_i%4])
early1_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall0[pt_i%4])
early1_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat_rise2[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat_fall2[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat_rise3[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat_fall3[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
if (sr_rise2_r[pt_i] == early_rise0[pt_i%4])
early2_match_rise2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise2_r[pt_i] <= #TCQ 1'b0;
if (sr_fall2_r[pt_i] == early_fall0[pt_i%4])
early2_match_fall2_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall2_r[pt_i] <= #TCQ 1'b0;
if (sr_rise3_r[pt_i] == early_rise1[pt_i%4])
early2_match_rise3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise3_r[pt_i] <= #TCQ 1'b0;
if (sr_fall3_r[pt_i] == early_fall1[pt_i%4])
early2_match_fall3_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall3_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat_match_rise0_and_r <= #TCQ &pat_match_rise0_r;
pat_match_fall0_and_r <= #TCQ &pat_match_fall0_r;
pat_match_rise1_and_r <= #TCQ &pat_match_rise1_r;
pat_match_fall1_and_r <= #TCQ &pat_match_fall1_r;
pat_match_rise2_and_r <= #TCQ &pat_match_rise2_r;
pat_match_fall2_and_r <= #TCQ &pat_match_fall2_r;
pat_match_rise3_and_r <= #TCQ &pat_match_rise3_r;
pat_match_fall3_and_r <= #TCQ &pat_match_fall3_r;
pat_data_match_r <= #TCQ (pat_match_rise0_and_r &&
pat_match_fall0_and_r &&
pat_match_rise1_and_r &&
pat_match_fall1_and_r &&
pat_match_rise2_and_r &&
pat_match_fall2_and_r &&
pat_match_rise3_and_r &&
pat_match_fall3_and_r);
pat_data_match_valid_r <= #TCQ rd_active_r3;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_match_rise2_and_r <= #TCQ &early1_match_rise2_r;
early1_match_fall2_and_r <= #TCQ &early1_match_fall2_r;
early1_match_rise3_and_r <= #TCQ &early1_match_rise3_r;
early1_match_fall3_and_r <= #TCQ &early1_match_fall3_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r &&
early1_match_rise2_and_r &&
early1_match_fall2_and_r &&
early1_match_rise3_and_r &&
early1_match_fall3_and_r);
end
always @(posedge clk) begin
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r;
early2_match_rise2_and_r <= #TCQ &early2_match_rise2_r;
early2_match_fall2_and_r <= #TCQ &early2_match_fall2_r;
early2_match_rise3_and_r <= #TCQ &early2_match_rise3_r;
early2_match_fall3_and_r <= #TCQ &early2_match_fall3_r;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r &&
early2_match_rise2_and_r &&
early2_match_fall2_and_r &&
early2_match_rise3_and_r &&
early2_match_fall3_and_r);
end
end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == pat2_rise0[pt_i%4])
pat2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == pat2_fall0[pt_i%4])
pat2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == pat2_rise1[pt_i%4])
pat2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == pat2_fall1[pt_i%4])
pat2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
pat2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early1_rise0[pt_i%4])
early1_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early1_fall0[pt_i%4])
early1_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early1_rise1[pt_i%4])
early1_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early1_fall1[pt_i%4])
early1_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early1_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
// early2 in this case does not mean 2 cycles early but
// the second cycle of read data in 2:1 mode
always @(posedge clk) begin
if (sr_rise0_r[pt_i] == early2_rise0[pt_i%4])
early2_match_rise0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise0_r[pt_i] <= #TCQ 1'b0;
if (sr_fall0_r[pt_i] == early2_fall0[pt_i%4])
early2_match_fall0_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall0_r[pt_i] <= #TCQ 1'b0;
if (sr_rise1_r[pt_i] == early2_rise1[pt_i%4])
early2_match_rise1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_rise1_r[pt_i] <= #TCQ 1'b0;
if (sr_fall1_r[pt_i] == early2_fall1[pt_i%4])
early2_match_fall1_r[pt_i] <= #TCQ 1'b1;
else
early2_match_fall1_r[pt_i] <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
pat1_match_fall0_and_r &&
pat1_match_rise1_and_r &&
pat1_match_fall1_and_r);
pat1_data_match_r1 <= #TCQ pat1_data_match_r;
pat2_match_rise0_and_r <= #TCQ &pat2_match_rise0_r && rd_active_r3;
pat2_match_fall0_and_r <= #TCQ &pat2_match_fall0_r && rd_active_r3;
pat2_match_rise1_and_r <= #TCQ &pat2_match_rise1_r && rd_active_r3;
pat2_match_fall1_and_r <= #TCQ &pat2_match_fall1_r && rd_active_r3;
pat2_data_match_r <= #TCQ (pat2_match_rise0_and_r &&
pat2_match_fall0_and_r &&
pat2_match_rise1_and_r &&
pat2_match_fall1_and_r);
// For 2:1 mode, read valid is asserted for 2 clock cycles -
// here we generate a "match valid" pulse that is only 1 clock
// cycle wide that is simulatenous when the match calculation
// is complete
pat_data_match_valid_r <= #TCQ rd_active_r4 & ~rd_active_r5;
end
always @(posedge clk) begin
early1_match_rise0_and_r <= #TCQ &early1_match_rise0_r;
early1_match_fall0_and_r <= #TCQ &early1_match_fall0_r;
early1_match_rise1_and_r <= #TCQ &early1_match_rise1_r;
early1_match_fall1_and_r <= #TCQ &early1_match_fall1_r;
early1_data_match_r <= #TCQ (early1_match_rise0_and_r &&
early1_match_fall0_and_r &&
early1_match_rise1_and_r &&
early1_match_fall1_and_r);
early1_data_match_r1 <= #TCQ early1_data_match_r;
early2_match_rise0_and_r <= #TCQ &early2_match_rise0_r && rd_active_r3;
early2_match_fall0_and_r <= #TCQ &early2_match_fall0_r && rd_active_r3;
early2_match_rise1_and_r <= #TCQ &early2_match_rise1_r && rd_active_r3;
early2_match_fall1_and_r <= #TCQ &early2_match_fall1_r && rd_active_r3;
early2_data_match_r <= #TCQ (early2_match_rise0_and_r &&
early2_match_fall0_and_r &&
early2_match_rise1_and_r &&
early2_match_fall1_and_r);
end
end
endgenerate
// Need to delay it by 3 cycles in order to wait for Phaser_Out
// coarse delay to take effect before issuing a write command
always @(posedge clk) begin
wrcal_pat_resume_r1 <= #TCQ wrcal_pat_resume_r;
wrcal_pat_resume_r2 <= #TCQ wrcal_pat_resume_r1;
wrcal_pat_resume <= #TCQ wrcal_pat_resume_r2;
end
always @(posedge clk) begin
if (rst)
tap_inc_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_DQ_IDEL_DEC) ||
(cal2_state_r == CAL2_IFIFO_RESET) ||
(cal2_state_r == CAL2_SANITY_WAIT))
tap_inc_wait_cnt <= #TCQ tap_inc_wait_cnt + 1;
else
tap_inc_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk) begin
if (rst)
not_empty_wait_cnt <= #TCQ 'd0;
else if ((cal2_state_r == CAL2_READ_WAIT) && wrcal_rd_wait)
not_empty_wait_cnt <= #TCQ not_empty_wait_cnt + 1;
else
not_empty_wait_cnt <= #TCQ 'd0;
end
always @(posedge clk)
cal2_state_r1 <= #TCQ cal2_state_r;
//*****************************************************************
// Write Calibration state machine
//*****************************************************************
// when calibrating, check to see if the expected pattern is received.
// Otherwise delay DQS to align to correct CK edge.
// NOTES:
// 1. An error condition can occur due to two reasons:
// a. If the matching logic does not receive the expected data
// pattern. However, the error may be "recoverable" because
// the write calibration is still in progress. If an error is
// found the write calibration logic delays DQS by an additional
// clock cycle and restarts the pattern detection process.
// By design, if the write path timing is incorrect, the correct
// data pattern will never be detected.
// b. Valid data not found even after incrementing Phaser_Out
// coarse delay line.
always @(posedge clk) begin
if (rst) begin
wrcal_dqs_cnt_r <= #TCQ 'b0;
cal2_done_r <= #TCQ 1'b0;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IDLE;
wrcal_pat_err <= #TCQ 1'b0;
wrcal_pat_resume_r <= #TCQ 1'b0;
wrcal_act_req <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
temp_wrcal_done <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b0;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
idelay_ld <= #TCQ 1'b0;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
early1_detect <= #TCQ 1'b0;
wrcal_sanity_chk_done <= #TCQ 1'b0;
wrcal_sanity_chk_err <= #TCQ 1'b0;
end else begin
cal2_prech_req_r <= #TCQ 1'b0;
case (cal2_state_r)
CAL2_IDLE: begin
wrcal_pat_err <= #TCQ 1'b0;
if (wrcal_start) begin
cal2_if_reset <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "SKIP_CAL")
// If skip write calibration, then proceed to end.
cal2_state_r <= #TCQ CAL2_DONE;
else
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
// General wait state to wait for read data to be output by the
// IN_FIFO
CAL2_READ_WAIT: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
// Wait until read data is received, and pattern matching
// calculation is complete. NOTE: Need to add a timeout here
// in case for some reason data is never received (or rather
// the PHASER_IN and IN_FIFO think they never receives data)
if (pat_data_match_valid_r && (nCK_PER_CLK == 4)) begin
if (pat_data_match_r)
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else begin
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
// If writes are one or two cycles early then redo
// write leveling for the byte
else if (early1_data_match_r) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early2_data_match_r) begin
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b1;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (pat_data_match_valid_r && (nCK_PER_CLK == 2)) begin
if ((pat1_data_match_r1 && pat2_data_match_r) ||
(pat1_detect && pat2_data_match_r))
// If found data match, then move on to next DQS group
cal2_state_r <= #TCQ CAL2_NEXT_DQS;
else if (pat1_data_match_r1 && ~pat2_data_match_r) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
pat1_detect <= #TCQ 1'b1;
end else begin
// If writes are one or two cycles early then redo
// write leveling for the byte
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_ERR;
else if ((early1_data_match_r1 && early2_data_match_r) ||
(early1_detect && early2_data_match_r)) begin
early1_data <= #TCQ 1'b1;
early2_data <= #TCQ 1'b0;
wrlvl_byte_redo <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_WRLVL_WAIT;
end else if (early1_data_match_r1 && ~early2_data_match_r) begin
early1_detect <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
// Read late due to incorrect MPR idelay value
// Decrement Idelay to '0'for the current byte
end else if (~idelay_ld_done) begin
cal2_state_r <= #TCQ CAL2_DQ_IDEL_DEC;
idelay_ld <= #TCQ 1'b1;
end else
cal2_state_r <= #TCQ CAL2_ERR;
end
end else if (not_empty_wait_cnt == 'd31)
cal2_state_r <= #TCQ CAL2_ERR;
end
CAL2_WRLVL_WAIT: begin
early1_detect <= #TCQ 1'b0;
if (wrlvl_byte_done && ~wrlvl_byte_done_r)
wrlvl_byte_redo <= #TCQ 1'b0;
if (wrlvl_byte_done) begin
if (rd_active_r1 && ~rd_active_r) begin
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
early1_data <= #TCQ 1'b0;
early2_data <= #TCQ 1'b0;
end
end
end
CAL2_DQ_IDEL_DEC: begin
if (tap_inc_wait_cnt == 'd4) begin
idelay_ld <= #TCQ 1'b0;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
cal2_if_reset <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b1;
end
end
CAL2_IFIFO_RESET: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
cal2_state_r <= #TCQ CAL2_DONE;
else if (idelay_ld_done) begin
wrcal_pat_resume_r <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end else
cal2_state_r <= #TCQ CAL2_IDLE;
end
end
// Final processing for current DQS group. Move on to next group
CAL2_NEXT_DQS: begin
// At this point, we've just found the correct pattern for the
// current DQS group.
// Request bank/row precharge, and wait for its completion. Always
// precharge after each DQS group to avoid tRAS(max) violation
if (wrcal_sanity_chk_r && (wrcal_dqs_cnt_r != DQS_WIDTH-1)) begin
cal2_prech_req_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_SANITY_WAIT;
end else
cal2_prech_req_r <= #TCQ 1'b1;
idelay_ld_done <= #TCQ 1'b0;
pat1_detect <= #TCQ 1'b0;
if (prech_done)
if (((DQS_WIDTH == 1) || (SIM_CAL_OPTION == "FAST_CAL")) ||
(wrcal_dqs_cnt_r == DQS_WIDTH-1)) begin
// If either FAST_CAL is enabled and first DQS group is
// finished, or if the last DQS group was just finished,
// then end of write calibration
if (wrcal_sanity_chk_r) begin
cal2_if_reset <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_IFIFO_RESET;
end else
cal2_state_r <= #TCQ CAL2_DONE;
end else begin
// Continue to next DQS group
wrcal_dqs_cnt_r <= #TCQ wrcal_dqs_cnt_r + 1;
cal2_state_r <= #TCQ CAL2_READ_WAIT;
end
end
CAL2_SANITY_WAIT: begin
if (tap_inc_wait_cnt == 'd15) begin
cal2_state_r <= #TCQ CAL2_READ_WAIT;
wrcal_pat_resume_r <= #TCQ 1'b1;
end
end
// Finished with read enable calibration
CAL2_DONE: begin
if (wrcal_sanity_chk && ~wrcal_sanity_chk_r) begin
cal2_done_r <= #TCQ 1'b0;
wrcal_dqs_cnt_r <= #TCQ 'd0;
cal2_state_r <= #TCQ CAL2_IDLE;
end else
cal2_done_r <= #TCQ 1'b1;
cal2_prech_req_r <= #TCQ 1'b0;
cal2_if_reset <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_done <= #TCQ 1'b1;
end
// Assert error signal indicating that writes timing is incorrect
CAL2_ERR: begin
wrcal_pat_resume_r <= #TCQ 1'b0;
if (wrcal_sanity_chk_r)
wrcal_sanity_chk_err <= #TCQ 1'b1;
else
wrcal_pat_err <= #TCQ 1'b1;
cal2_state_r <= #TCQ CAL2_ERR;
end
endcase
end
end
// Delay assertion of wrcal_done for write calibration by a few cycles after
// we've reached CAL2_DONE
always @(posedge clk)
if (rst)
cal2_done_r1 <= #TCQ 1'b0;
else
cal2_done_r1 <= #TCQ cal2_done_r;
always @(posedge clk)
if (rst || (wrcal_sanity_chk && ~wrcal_sanity_chk_r))
wrcal_done <= #TCQ 1'b0;
else if (cal2_done_r)
wrcal_done <= #TCQ 1'b1;
endmodule
|
//
// Module: DRAM16XN
//
// Description: Distributed SelectRAM example
// Dual Port 16 x N-bit
//
// Device: Spartan-3 Family
//---------------------------------------------------------------------------------------
module DRAM16XN #(parameter data_width = 20)
(
DATA_IN,
ADDRESS,
ADDRESS_DP,
WRITE_EN,
CLK,
O_DATA_OUT,
O_DATA_OUT_DP);
input [data_width-1:0]DATA_IN;
input [3:0] ADDRESS;
input [3:0] ADDRESS_DP;
input WRITE_EN;
input CLK;
output [data_width-1:0]O_DATA_OUT_DP;
output [data_width-1:0]O_DATA_OUT;
genvar i;
generate
for(i = 0 ; i < data_width ; i = i + 1) begin : dram16s
RAM16X1D i_RAM16X1D_U(
.D(DATA_IN[i]), //insert input signal
.WE(WRITE_EN), //insert Write Enable signal
.WCLK(CLK), //insert Write Clock signal
.A0(ADDRESS[0]), //insert Address 0 signal port SPO
.A1(ADDRESS[1]), //insert Address 1 signal port SPO
.A2(ADDRESS[2]), //insert Address 2 signal port SPO
.A3(ADDRESS[3]), //insert Address 3 signal port SPO
.DPRA0(ADDRESS_DP[0]), //insert Address 0 signal dual port DPO
.DPRA1(ADDRESS_DP[1]), //insert Address 1 signal dual port DPO
.DPRA2(ADDRESS_DP[2]), //insert Address 2 signal dual port DPO
.DPRA3(ADDRESS_DP[3]), //insert Address 3 signal dual port DPO
.SPO(O_DATA_OUT[i]), //insert output signal SPO
.DPO(O_DATA_OUT_DP[i]) //insert output signal DPO
);
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_common.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Common block for the bank machines. Bank_common computes various
// items that cross all of the bank machines. These values are then
// fed back to all of the bank machines. Most of these values have
// to do with a row machine figuring out where it belongs in a queue.
`timescale 1 ps / 1 ps
module mig_7series_v1_9_bank_common #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter LOW_IDLE_CNT = 1,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRFC = 44,
parameter nXSDLL = 512,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter CWL = 5,
parameter tZQCS = 64
)
(/*AUTOARG*/
// Outputs
accept_internal_r, accept_ns, accept, periodic_rd_insert,
periodic_rd_ack_r, accept_req, rb_hit_busy_cnt, idle, idle_cnt, order_cnt,
adv_order_q, bank_mach_next, op_exit_grant, low_idle_cnt_r, was_wr,
was_priority, maint_wip_r, maint_idle, insert_maint_r,
// Inputs
clk, rst, idle_ns, init_calib_complete, periodic_rd_r, use_addr,
rb_hit_busy_r, idle_r, ordered_r, ordered_issued, head_r, end_rtp,
passing_open_bank, op_exit_req, start_pre_wait, cmd, hi_priority, maint_req_r,
maint_zq_r, maint_sre_r, maint_srx_r, maint_hit, bm_end,
slot_0_present, slot_1_present
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
input [nBANK_MACHS-1:0] idle_ns;
input init_calib_complete;
wire accept_internal_ns = init_calib_complete && |idle_ns;
output reg accept_internal_r;
always @(posedge clk) accept_internal_r <= accept_internal_ns;
wire periodic_rd_ack_ns;
wire accept_ns_lcl = accept_internal_ns && ~periodic_rd_ack_ns;
output wire accept_ns;
assign accept_ns = accept_ns_lcl;
reg accept_r;
always @(posedge clk) accept_r <= #TCQ accept_ns_lcl;
// Wire to user interface informing user that the request has been accepted.
output wire accept;
assign accept = accept_r;
`ifdef MC_SVA
property none_idle;
@(posedge clk) (init_calib_complete && ~|idle_r);
endproperty
all_bank_machines_busy: cover property (none_idle);
`endif
// periodic_rd_insert tells everyone to mux in the periodic read.
input periodic_rd_r;
reg periodic_rd_ack_r_lcl;
reg periodic_rd_cntr_r ;
always @(posedge clk) begin
if (rst) periodic_rd_cntr_r <= #TCQ 1'b0;
else if (periodic_rd_r && periodic_rd_ack_r_lcl)
periodic_rd_cntr_r <= #TCQ ~periodic_rd_cntr_r;
end
wire internal_periodic_rd_ack_r_lcl = (periodic_rd_cntr_r && periodic_rd_ack_r_lcl);
// wire periodic_rd_insert_lcl = periodic_rd_r && ~periodic_rd_ack_r_lcl;
wire periodic_rd_insert_lcl = periodic_rd_r && ~internal_periodic_rd_ack_r_lcl;
output wire periodic_rd_insert;
assign periodic_rd_insert = periodic_rd_insert_lcl;
// periodic_rd_ack_r acknowledges that the read has been accepted
// into the queue.
assign periodic_rd_ack_ns = periodic_rd_insert_lcl && accept_internal_ns;
always @(posedge clk) periodic_rd_ack_r_lcl <= #TCQ periodic_rd_ack_ns;
output wire periodic_rd_ack_r;
assign periodic_rd_ack_r = periodic_rd_ack_r_lcl;
// accept_req tells all q entries that a request has been accepted.
input use_addr;
wire accept_req_lcl = periodic_rd_ack_r_lcl || (accept_r && use_addr);
output wire accept_req;
assign accept_req = accept_req_lcl;
// Count how many non idle bank machines hit on the rank and bank.
input [nBANK_MACHS-1:0] rb_hit_busy_r;
output reg [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
integer i;
always @(/*AS*/rb_hit_busy_r) begin
rb_hit_busy_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (rb_hit_busy_r[i]) rb_hit_busy_cnt = rb_hit_busy_cnt + BM_CNT_ONE;
end
// Count the number of idle bank machines.
input [nBANK_MACHS-1:0] idle_r;
output reg [BM_CNT_WIDTH-1:0] idle_cnt;
always @(/*AS*/idle_r) begin
idle_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (idle_r[i]) idle_cnt = idle_cnt + BM_CNT_ONE;
end
// Report an overall idle status
output idle;
assign idle = init_calib_complete && &idle_r;
// Count the number of bank machines in the ordering queue.
input [nBANK_MACHS-1:0] ordered_r;
output reg [BM_CNT_WIDTH-1:0] order_cnt;
always @(/*AS*/ordered_r) begin
order_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (ordered_r[i]) order_cnt = order_cnt + BM_CNT_ONE;
end
input [nBANK_MACHS-1:0] ordered_issued;
output wire adv_order_q;
assign adv_order_q = |ordered_issued;
// Figure out which bank machine is going to accept the next request.
input [nBANK_MACHS-1:0] head_r;
wire [nBANK_MACHS-1:0] next = idle_r & head_r;
output reg[BM_CNT_WIDTH-1:0] bank_mach_next;
always @(/*AS*/next) begin
bank_mach_next = BM_CNT_ZERO;
for (i = 0; i <= nBANK_MACHS-1; i = i + 1)
if (next[i]) bank_mach_next = i[BM_CNT_WIDTH-1:0];
end
input [nBANK_MACHS-1:0] end_rtp;
input [nBANK_MACHS-1:0] passing_open_bank;
input [nBANK_MACHS-1:0] op_exit_req;
output wire [nBANK_MACHS-1:0] op_exit_grant;
output reg low_idle_cnt_r = 1'b0;
input [nBANK_MACHS-1:0] start_pre_wait;
generate
// In support of open page mode, the following logic
// keeps track of how many "idle" bank machines there
// are. In this case, idle means a bank machine is on
// the idle list, or is in the process of precharging and
// will soon be idle.
if (nOP_WAIT == 0) begin : op_mode_disabled
assign op_exit_grant = {nBANK_MACHS{1'b0}};
end
else begin : op_mode_enabled
reg [BM_CNT_WIDTH:0] idle_cnt_r;
reg [BM_CNT_WIDTH:0] idle_cnt_ns;
always @(/*AS*/accept_req_lcl or idle_cnt_r or passing_open_bank
or rst or start_pre_wait)
if (rst) idle_cnt_ns = nBANK_MACHS;
else begin
idle_cnt_ns = idle_cnt_r - accept_req_lcl;
for (i = 0; i <= nBANK_MACHS-1; i = i + 1) begin
idle_cnt_ns = idle_cnt_ns + passing_open_bank[i];
end
idle_cnt_ns = idle_cnt_ns + |start_pre_wait;
end
always @(posedge clk) idle_cnt_r <= #TCQ idle_cnt_ns;
wire low_idle_cnt_ns = (idle_cnt_ns <= LOW_IDLE_CNT[0+:BM_CNT_WIDTH]);
always @(posedge clk) low_idle_cnt_r <= #TCQ low_idle_cnt_ns;
// This arbiter determines which bank machine should transition
// from open page wait to precharge. Ideally, this process
// would take the oldest waiter, but don't have any reasonable
// way to implement that. Instead, just use simple round robin
// arb with the small enhancement that the most recent bank machine
// to enter open page wait is given lowest priority in the arbiter.
wire upd_last_master = |end_rtp; // should be one bit set at most
mig_7series_v1_9_round_robin_arb #
(.WIDTH (nBANK_MACHS))
op_arb0
(.grant_ns (op_exit_grant[nBANK_MACHS-1:0]),
.grant_r (),
.upd_last_master (upd_last_master),
.current_master (end_rtp[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (op_exit_req[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
end
endgenerate
// Register some command information. This information will be used
// by the bank machines to figure out if there is something behind it
// in the queue that require hi priority.
input [2:0] cmd;
output reg was_wr;
always @(posedge clk) was_wr <= #TCQ
cmd[0] && ~(periodic_rd_r && ~periodic_rd_ack_r_lcl);
input hi_priority;
output reg was_priority;
always @(posedge clk) begin
if (hi_priority)
was_priority <= #TCQ 1'b1;
else
was_priority <= #TCQ 1'b0;
end
// DRAM maintenance (refresh and ZQ) and self-refresh controller
input maint_req_r;
reg maint_wip_r_lcl;
output wire maint_wip_r;
assign maint_wip_r = maint_wip_r_lcl;
wire maint_idle_lcl;
output wire maint_idle;
assign maint_idle = maint_idle_lcl;
input maint_zq_r;
input maint_sre_r;
input maint_srx_r;
input [nBANK_MACHS-1:0] maint_hit;
input [nBANK_MACHS-1:0] bm_end;
wire start_maint;
wire maint_end;
generate begin : maint_controller
// Idle when not (maintenance work in progress (wip), OR maintenance
// starting tick).
assign maint_idle_lcl = ~(maint_req_r || maint_wip_r_lcl);
// Maintenance work in progress starts with maint_reg_r tick, terminated
// with maint_end tick. maint_end tick is generated by the RFC/ZQ/XSDLL timer
// below.
wire maint_wip_ns =
~rst && ~maint_end && (maint_wip_r_lcl || maint_req_r);
always @(posedge clk) maint_wip_r_lcl <= #TCQ maint_wip_ns;
// Keep track of which bank machines hit on the maintenance request
// when the request is made. As bank machines complete, an assertion
// of the bm_end signal clears the correspoding bit in the
// maint_hit_busies_r vector. Eventually, all bits should clear and
// the maintenance operation will proceed. ZQ and self-refresh hit on all
// non idle banks. Refresh hits only on non idle banks with the same rank as
// the refresh request.
wire [nBANK_MACHS-1:0] clear_vector = {nBANK_MACHS{rst}} | bm_end;
wire [nBANK_MACHS-1:0] maint_zq_hits = {nBANK_MACHS{maint_idle_lcl}} &
(maint_hit | {nBANK_MACHS{maint_zq_r}}) & ~idle_ns;
wire [nBANK_MACHS-1:0] maint_sre_hits = {nBANK_MACHS{maint_idle_lcl}} &
(maint_hit | {nBANK_MACHS{maint_sre_r}}) & ~idle_ns;
reg [nBANK_MACHS-1:0] maint_hit_busies_r;
wire [nBANK_MACHS-1:0] maint_hit_busies_ns =
~clear_vector & (maint_hit_busies_r | maint_zq_hits | maint_sre_hits);
always @(posedge clk) maint_hit_busies_r <= #TCQ maint_hit_busies_ns;
// Queue is clear of requests conflicting with maintenance.
wire maint_clear = ~maint_idle_lcl && ~|maint_hit_busies_ns;
// Ready to start sending maintenance commands.
wire maint_rdy = maint_clear;
reg maint_rdy_r1;
reg maint_srx_r1;
always @(posedge clk) maint_rdy_r1 <= #TCQ maint_rdy;
always @(posedge clk) maint_srx_r1 <= #TCQ maint_srx_r;
assign start_maint = maint_rdy && ~maint_rdy_r1 || maint_srx_r && ~maint_srx_r1;
end // block: maint_controller
endgenerate
// Figure out how many maintenance commands to send, and send them.
input [7:0] slot_0_present;
input [7:0] slot_1_present;
reg insert_maint_r_lcl;
output wire insert_maint_r;
assign insert_maint_r = insert_maint_r_lcl;
generate begin : generate_maint_cmds
// Count up how many slots are occupied. This tells
// us how many ZQ, SRE or SRX commands to send out.
reg [RANK_WIDTH:0] present_count;
wire [7:0] present = slot_0_present | slot_1_present;
always @(/*AS*/present) begin
present_count = {RANK_WIDTH{1'b0}};
for (i=0; i<8; i=i+1)
present_count = present_count + {{RANK_WIDTH{1'b0}}, present[i]};
end
// For refresh, there is only a single command sent. For
// ZQ, SRE and SRX, each rank present will receive a command. The counter
// below counts down the number of ranks present.
reg [RANK_WIDTH:0] send_cnt_ns;
reg [RANK_WIDTH:0] send_cnt_r;
always @(/*AS*/maint_zq_r or maint_sre_r or maint_srx_r or present_count
or rst or send_cnt_r or start_maint)
if (rst) send_cnt_ns = 4'b0;
else begin
send_cnt_ns = send_cnt_r;
if (start_maint && (maint_zq_r || maint_sre_r || maint_srx_r)) send_cnt_ns = present_count;
if (|send_cnt_ns)
send_cnt_ns = send_cnt_ns - ONE[RANK_WIDTH-1:0];
end
always @(posedge clk) send_cnt_r <= #TCQ send_cnt_ns;
// Insert a maintenance command for start_maint, or when the sent count
// is not zero.
wire insert_maint_ns = start_maint || |send_cnt_r;
always @(posedge clk) insert_maint_r_lcl <= #TCQ insert_maint_ns;
end // block: generate_maint_cmds
endgenerate
// RFC ZQ XSDLL timer. Generates delay from refresh, self-refresh exit or ZQ
// command until the end of the maintenance operation.
// Compute values for RFC, ZQ and XSDLL periods.
localparam nRFC_CLKS = (nCK_PER_CLK == 1) ?
nRFC :
(nCK_PER_CLK == 2) ?
((nRFC/2) + (nRFC%2)) :
// (nCK_PER_CLK == 4)
((nRFC/4) + ((nRFC%4) ? 1 : 0));
localparam nZQCS_CLKS = (nCK_PER_CLK == 1) ?
tZQCS :
(nCK_PER_CLK == 2) ?
((tZQCS/2) + (tZQCS%2)) :
// (nCK_PER_CLK == 4)
((tZQCS/4) + ((tZQCS%4) ? 1 : 0));
localparam nXSDLL_CLKS = (nCK_PER_CLK == 1) ?
nXSDLL :
(nCK_PER_CLK == 2) ?
((nXSDLL/2) + (nXSDLL%2)) :
// (nCK_PER_CLK == 4)
((nXSDLL/4) + ((nXSDLL%4) ? 1 : 0));
localparam RFC_ZQ_TIMER_WIDTH = clogb2(nXSDLL_CLKS + 1);
localparam THREE = 3;
generate begin : rfc_zq_xsdll_timer
reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_ns;
reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_r;
always @(/*AS*/insert_maint_r_lcl or maint_zq_r or maint_sre_r or maint_srx_r
or rfc_zq_xsdll_timer_r or rst) begin
rfc_zq_xsdll_timer_ns = rfc_zq_xsdll_timer_r;
if (rst) rfc_zq_xsdll_timer_ns = {RFC_ZQ_TIMER_WIDTH{1'b0}};
else if (insert_maint_r_lcl) rfc_zq_xsdll_timer_ns = maint_zq_r ?
nZQCS_CLKS :
maint_sre_r ?
{RFC_ZQ_TIMER_WIDTH{1'b0}} :
maint_srx_r ?
nXSDLL_CLKS :
nRFC_CLKS;
else if (|rfc_zq_xsdll_timer_r) rfc_zq_xsdll_timer_ns =
rfc_zq_xsdll_timer_r - ONE[RFC_ZQ_TIMER_WIDTH-1:0];
end
always @(posedge clk) rfc_zq_xsdll_timer_r <= #TCQ rfc_zq_xsdll_timer_ns;
// Based on rfc_zq_xsdll_timer_r, figure out when to release any bank
// machines waiting to send an activate. Need to add two to the end count.
// One because the counter starts a state after the insert_refresh_r, and
// one more because bm_end to insert_refresh_r is one state shorter
// than bm_end to rts_row.
assign maint_end = (rfc_zq_xsdll_timer_r == THREE[RFC_ZQ_TIMER_WIDTH-1:0]);
end // block: rfc_zq_xsdll_timer
endgenerate
endmodule // bank_common
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// related to, arising under or in connection with these
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// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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// performance, such as life-support or safety devices or
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// applications related to the deployment of airbags, or any
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// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_common.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Common block for the bank machines. Bank_common computes various
// items that cross all of the bank machines. These values are then
// fed back to all of the bank machines. Most of these values have
// to do with a row machine figuring out where it belongs in a queue.
`timescale 1 ps / 1 ps
module mig_7series_v1_9_bank_common #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter LOW_IDLE_CNT = 1,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRFC = 44,
parameter nXSDLL = 512,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter CWL = 5,
parameter tZQCS = 64
)
(/*AUTOARG*/
// Outputs
accept_internal_r, accept_ns, accept, periodic_rd_insert,
periodic_rd_ack_r, accept_req, rb_hit_busy_cnt, idle, idle_cnt, order_cnt,
adv_order_q, bank_mach_next, op_exit_grant, low_idle_cnt_r, was_wr,
was_priority, maint_wip_r, maint_idle, insert_maint_r,
// Inputs
clk, rst, idle_ns, init_calib_complete, periodic_rd_r, use_addr,
rb_hit_busy_r, idle_r, ordered_r, ordered_issued, head_r, end_rtp,
passing_open_bank, op_exit_req, start_pre_wait, cmd, hi_priority, maint_req_r,
maint_zq_r, maint_sre_r, maint_srx_r, maint_hit, bm_end,
slot_0_present, slot_1_present
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
input [nBANK_MACHS-1:0] idle_ns;
input init_calib_complete;
wire accept_internal_ns = init_calib_complete && |idle_ns;
output reg accept_internal_r;
always @(posedge clk) accept_internal_r <= accept_internal_ns;
wire periodic_rd_ack_ns;
wire accept_ns_lcl = accept_internal_ns && ~periodic_rd_ack_ns;
output wire accept_ns;
assign accept_ns = accept_ns_lcl;
reg accept_r;
always @(posedge clk) accept_r <= #TCQ accept_ns_lcl;
// Wire to user interface informing user that the request has been accepted.
output wire accept;
assign accept = accept_r;
`ifdef MC_SVA
property none_idle;
@(posedge clk) (init_calib_complete && ~|idle_r);
endproperty
all_bank_machines_busy: cover property (none_idle);
`endif
// periodic_rd_insert tells everyone to mux in the periodic read.
input periodic_rd_r;
reg periodic_rd_ack_r_lcl;
reg periodic_rd_cntr_r ;
always @(posedge clk) begin
if (rst) periodic_rd_cntr_r <= #TCQ 1'b0;
else if (periodic_rd_r && periodic_rd_ack_r_lcl)
periodic_rd_cntr_r <= #TCQ ~periodic_rd_cntr_r;
end
wire internal_periodic_rd_ack_r_lcl = (periodic_rd_cntr_r && periodic_rd_ack_r_lcl);
// wire periodic_rd_insert_lcl = periodic_rd_r && ~periodic_rd_ack_r_lcl;
wire periodic_rd_insert_lcl = periodic_rd_r && ~internal_periodic_rd_ack_r_lcl;
output wire periodic_rd_insert;
assign periodic_rd_insert = periodic_rd_insert_lcl;
// periodic_rd_ack_r acknowledges that the read has been accepted
// into the queue.
assign periodic_rd_ack_ns = periodic_rd_insert_lcl && accept_internal_ns;
always @(posedge clk) periodic_rd_ack_r_lcl <= #TCQ periodic_rd_ack_ns;
output wire periodic_rd_ack_r;
assign periodic_rd_ack_r = periodic_rd_ack_r_lcl;
// accept_req tells all q entries that a request has been accepted.
input use_addr;
wire accept_req_lcl = periodic_rd_ack_r_lcl || (accept_r && use_addr);
output wire accept_req;
assign accept_req = accept_req_lcl;
// Count how many non idle bank machines hit on the rank and bank.
input [nBANK_MACHS-1:0] rb_hit_busy_r;
output reg [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
integer i;
always @(/*AS*/rb_hit_busy_r) begin
rb_hit_busy_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (rb_hit_busy_r[i]) rb_hit_busy_cnt = rb_hit_busy_cnt + BM_CNT_ONE;
end
// Count the number of idle bank machines.
input [nBANK_MACHS-1:0] idle_r;
output reg [BM_CNT_WIDTH-1:0] idle_cnt;
always @(/*AS*/idle_r) begin
idle_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (idle_r[i]) idle_cnt = idle_cnt + BM_CNT_ONE;
end
// Report an overall idle status
output idle;
assign idle = init_calib_complete && &idle_r;
// Count the number of bank machines in the ordering queue.
input [nBANK_MACHS-1:0] ordered_r;
output reg [BM_CNT_WIDTH-1:0] order_cnt;
always @(/*AS*/ordered_r) begin
order_cnt = BM_CNT_ZERO;
for (i = 0; i < nBANK_MACHS; i = i + 1)
if (ordered_r[i]) order_cnt = order_cnt + BM_CNT_ONE;
end
input [nBANK_MACHS-1:0] ordered_issued;
output wire adv_order_q;
assign adv_order_q = |ordered_issued;
// Figure out which bank machine is going to accept the next request.
input [nBANK_MACHS-1:0] head_r;
wire [nBANK_MACHS-1:0] next = idle_r & head_r;
output reg[BM_CNT_WIDTH-1:0] bank_mach_next;
always @(/*AS*/next) begin
bank_mach_next = BM_CNT_ZERO;
for (i = 0; i <= nBANK_MACHS-1; i = i + 1)
if (next[i]) bank_mach_next = i[BM_CNT_WIDTH-1:0];
end
input [nBANK_MACHS-1:0] end_rtp;
input [nBANK_MACHS-1:0] passing_open_bank;
input [nBANK_MACHS-1:0] op_exit_req;
output wire [nBANK_MACHS-1:0] op_exit_grant;
output reg low_idle_cnt_r = 1'b0;
input [nBANK_MACHS-1:0] start_pre_wait;
generate
// In support of open page mode, the following logic
// keeps track of how many "idle" bank machines there
// are. In this case, idle means a bank machine is on
// the idle list, or is in the process of precharging and
// will soon be idle.
if (nOP_WAIT == 0) begin : op_mode_disabled
assign op_exit_grant = {nBANK_MACHS{1'b0}};
end
else begin : op_mode_enabled
reg [BM_CNT_WIDTH:0] idle_cnt_r;
reg [BM_CNT_WIDTH:0] idle_cnt_ns;
always @(/*AS*/accept_req_lcl or idle_cnt_r or passing_open_bank
or rst or start_pre_wait)
if (rst) idle_cnt_ns = nBANK_MACHS;
else begin
idle_cnt_ns = idle_cnt_r - accept_req_lcl;
for (i = 0; i <= nBANK_MACHS-1; i = i + 1) begin
idle_cnt_ns = idle_cnt_ns + passing_open_bank[i];
end
idle_cnt_ns = idle_cnt_ns + |start_pre_wait;
end
always @(posedge clk) idle_cnt_r <= #TCQ idle_cnt_ns;
wire low_idle_cnt_ns = (idle_cnt_ns <= LOW_IDLE_CNT[0+:BM_CNT_WIDTH]);
always @(posedge clk) low_idle_cnt_r <= #TCQ low_idle_cnt_ns;
// This arbiter determines which bank machine should transition
// from open page wait to precharge. Ideally, this process
// would take the oldest waiter, but don't have any reasonable
// way to implement that. Instead, just use simple round robin
// arb with the small enhancement that the most recent bank machine
// to enter open page wait is given lowest priority in the arbiter.
wire upd_last_master = |end_rtp; // should be one bit set at most
mig_7series_v1_9_round_robin_arb #
(.WIDTH (nBANK_MACHS))
op_arb0
(.grant_ns (op_exit_grant[nBANK_MACHS-1:0]),
.grant_r (),
.upd_last_master (upd_last_master),
.current_master (end_rtp[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (op_exit_req[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
end
endgenerate
// Register some command information. This information will be used
// by the bank machines to figure out if there is something behind it
// in the queue that require hi priority.
input [2:0] cmd;
output reg was_wr;
always @(posedge clk) was_wr <= #TCQ
cmd[0] && ~(periodic_rd_r && ~periodic_rd_ack_r_lcl);
input hi_priority;
output reg was_priority;
always @(posedge clk) begin
if (hi_priority)
was_priority <= #TCQ 1'b1;
else
was_priority <= #TCQ 1'b0;
end
// DRAM maintenance (refresh and ZQ) and self-refresh controller
input maint_req_r;
reg maint_wip_r_lcl;
output wire maint_wip_r;
assign maint_wip_r = maint_wip_r_lcl;
wire maint_idle_lcl;
output wire maint_idle;
assign maint_idle = maint_idle_lcl;
input maint_zq_r;
input maint_sre_r;
input maint_srx_r;
input [nBANK_MACHS-1:0] maint_hit;
input [nBANK_MACHS-1:0] bm_end;
wire start_maint;
wire maint_end;
generate begin : maint_controller
// Idle when not (maintenance work in progress (wip), OR maintenance
// starting tick).
assign maint_idle_lcl = ~(maint_req_r || maint_wip_r_lcl);
// Maintenance work in progress starts with maint_reg_r tick, terminated
// with maint_end tick. maint_end tick is generated by the RFC/ZQ/XSDLL timer
// below.
wire maint_wip_ns =
~rst && ~maint_end && (maint_wip_r_lcl || maint_req_r);
always @(posedge clk) maint_wip_r_lcl <= #TCQ maint_wip_ns;
// Keep track of which bank machines hit on the maintenance request
// when the request is made. As bank machines complete, an assertion
// of the bm_end signal clears the correspoding bit in the
// maint_hit_busies_r vector. Eventually, all bits should clear and
// the maintenance operation will proceed. ZQ and self-refresh hit on all
// non idle banks. Refresh hits only on non idle banks with the same rank as
// the refresh request.
wire [nBANK_MACHS-1:0] clear_vector = {nBANK_MACHS{rst}} | bm_end;
wire [nBANK_MACHS-1:0] maint_zq_hits = {nBANK_MACHS{maint_idle_lcl}} &
(maint_hit | {nBANK_MACHS{maint_zq_r}}) & ~idle_ns;
wire [nBANK_MACHS-1:0] maint_sre_hits = {nBANK_MACHS{maint_idle_lcl}} &
(maint_hit | {nBANK_MACHS{maint_sre_r}}) & ~idle_ns;
reg [nBANK_MACHS-1:0] maint_hit_busies_r;
wire [nBANK_MACHS-1:0] maint_hit_busies_ns =
~clear_vector & (maint_hit_busies_r | maint_zq_hits | maint_sre_hits);
always @(posedge clk) maint_hit_busies_r <= #TCQ maint_hit_busies_ns;
// Queue is clear of requests conflicting with maintenance.
wire maint_clear = ~maint_idle_lcl && ~|maint_hit_busies_ns;
// Ready to start sending maintenance commands.
wire maint_rdy = maint_clear;
reg maint_rdy_r1;
reg maint_srx_r1;
always @(posedge clk) maint_rdy_r1 <= #TCQ maint_rdy;
always @(posedge clk) maint_srx_r1 <= #TCQ maint_srx_r;
assign start_maint = maint_rdy && ~maint_rdy_r1 || maint_srx_r && ~maint_srx_r1;
end // block: maint_controller
endgenerate
// Figure out how many maintenance commands to send, and send them.
input [7:0] slot_0_present;
input [7:0] slot_1_present;
reg insert_maint_r_lcl;
output wire insert_maint_r;
assign insert_maint_r = insert_maint_r_lcl;
generate begin : generate_maint_cmds
// Count up how many slots are occupied. This tells
// us how many ZQ, SRE or SRX commands to send out.
reg [RANK_WIDTH:0] present_count;
wire [7:0] present = slot_0_present | slot_1_present;
always @(/*AS*/present) begin
present_count = {RANK_WIDTH{1'b0}};
for (i=0; i<8; i=i+1)
present_count = present_count + {{RANK_WIDTH{1'b0}}, present[i]};
end
// For refresh, there is only a single command sent. For
// ZQ, SRE and SRX, each rank present will receive a command. The counter
// below counts down the number of ranks present.
reg [RANK_WIDTH:0] send_cnt_ns;
reg [RANK_WIDTH:0] send_cnt_r;
always @(/*AS*/maint_zq_r or maint_sre_r or maint_srx_r or present_count
or rst or send_cnt_r or start_maint)
if (rst) send_cnt_ns = 4'b0;
else begin
send_cnt_ns = send_cnt_r;
if (start_maint && (maint_zq_r || maint_sre_r || maint_srx_r)) send_cnt_ns = present_count;
if (|send_cnt_ns)
send_cnt_ns = send_cnt_ns - ONE[RANK_WIDTH-1:0];
end
always @(posedge clk) send_cnt_r <= #TCQ send_cnt_ns;
// Insert a maintenance command for start_maint, or when the sent count
// is not zero.
wire insert_maint_ns = start_maint || |send_cnt_r;
always @(posedge clk) insert_maint_r_lcl <= #TCQ insert_maint_ns;
end // block: generate_maint_cmds
endgenerate
// RFC ZQ XSDLL timer. Generates delay from refresh, self-refresh exit or ZQ
// command until the end of the maintenance operation.
// Compute values for RFC, ZQ and XSDLL periods.
localparam nRFC_CLKS = (nCK_PER_CLK == 1) ?
nRFC :
(nCK_PER_CLK == 2) ?
((nRFC/2) + (nRFC%2)) :
// (nCK_PER_CLK == 4)
((nRFC/4) + ((nRFC%4) ? 1 : 0));
localparam nZQCS_CLKS = (nCK_PER_CLK == 1) ?
tZQCS :
(nCK_PER_CLK == 2) ?
((tZQCS/2) + (tZQCS%2)) :
// (nCK_PER_CLK == 4)
((tZQCS/4) + ((tZQCS%4) ? 1 : 0));
localparam nXSDLL_CLKS = (nCK_PER_CLK == 1) ?
nXSDLL :
(nCK_PER_CLK == 2) ?
((nXSDLL/2) + (nXSDLL%2)) :
// (nCK_PER_CLK == 4)
((nXSDLL/4) + ((nXSDLL%4) ? 1 : 0));
localparam RFC_ZQ_TIMER_WIDTH = clogb2(nXSDLL_CLKS + 1);
localparam THREE = 3;
generate begin : rfc_zq_xsdll_timer
reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_ns;
reg [RFC_ZQ_TIMER_WIDTH-1:0] rfc_zq_xsdll_timer_r;
always @(/*AS*/insert_maint_r_lcl or maint_zq_r or maint_sre_r or maint_srx_r
or rfc_zq_xsdll_timer_r or rst) begin
rfc_zq_xsdll_timer_ns = rfc_zq_xsdll_timer_r;
if (rst) rfc_zq_xsdll_timer_ns = {RFC_ZQ_TIMER_WIDTH{1'b0}};
else if (insert_maint_r_lcl) rfc_zq_xsdll_timer_ns = maint_zq_r ?
nZQCS_CLKS :
maint_sre_r ?
{RFC_ZQ_TIMER_WIDTH{1'b0}} :
maint_srx_r ?
nXSDLL_CLKS :
nRFC_CLKS;
else if (|rfc_zq_xsdll_timer_r) rfc_zq_xsdll_timer_ns =
rfc_zq_xsdll_timer_r - ONE[RFC_ZQ_TIMER_WIDTH-1:0];
end
always @(posedge clk) rfc_zq_xsdll_timer_r <= #TCQ rfc_zq_xsdll_timer_ns;
// Based on rfc_zq_xsdll_timer_r, figure out when to release any bank
// machines waiting to send an activate. Need to add two to the end count.
// One because the counter starts a state after the insert_refresh_r, and
// one more because bm_end to insert_refresh_r is one state shorter
// than bm_end to rts_row.
assign maint_end = (rfc_zq_xsdll_timer_r == THREE[RFC_ZQ_TIMER_WIDTH-1:0]);
end // block: rfc_zq_xsdll_timer
endgenerate
endmodule // bank_common
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
/* Acceptable answer 1
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.b.gen[0].tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.b.gen[1].tag
*/
/* Acceptable answer 2
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.tag
*/
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
tag tag ();
b b ();
always @ (t.cyc) begin
if (t.cyc == 2) $display("mod a has scope = %m");
if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope);
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module b ();
genvar g;
generate
for (g=0; g<2; g++) begin : gen
tag tag ();
c c ();
end
endgenerate
always @ (t.cyc) begin
if (t.cyc == 3) $display("mod b has scope = %m");
if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope);
end
endmodule
module c ();
always @ (t.cyc) begin
if (t.cyc == 4) $display("mod c has scope = %m");
if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope);
end
endmodule
module tag ();
bit [100*8-1:0] scope;
initial begin
$sformat(scope,"%m");
$display("created tag with scope = %0s",scope);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
/* Acceptable answer 1
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.b.gen[0].tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.b.gen[1].tag
*/
/* Acceptable answer 2
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.tag
*/
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
tag tag ();
b b ();
always @ (t.cyc) begin
if (t.cyc == 2) $display("mod a has scope = %m");
if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope);
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module b ();
genvar g;
generate
for (g=0; g<2; g++) begin : gen
tag tag ();
c c ();
end
endgenerate
always @ (t.cyc) begin
if (t.cyc == 3) $display("mod b has scope = %m");
if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope);
end
endmodule
module c ();
always @ (t.cyc) begin
if (t.cyc == 4) $display("mod c has scope = %m");
if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope);
end
endmodule
module tag ();
bit [100*8-1:0] scope;
initial begin
$sformat(scope,"%m");
$display("created tag with scope = %0s",scope);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
/* Acceptable answer 1
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.b.gen[0].tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.b.gen[1].tag
*/
/* Acceptable answer 2
created tag with scope = top.t.tag
created tag with scope = top.t.b.gen[0].tag
created tag with scope = top.t.b.gen[1].tag
mod a has scope = top.t
mod a has tag = top.t.tag
mod b has scope = top.t.b
mod b has tag = top.t.tag
mod c has scope = top.t.b.gen[0].c
mod c has tag = top.t.tag
mod c has scope = top.t.b.gen[1].c
mod c has tag = top.t.tag
*/
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
tag tag ();
b b ();
always @ (t.cyc) begin
if (t.cyc == 2) $display("mod a has scope = %m");
if (t.cyc == 2) $display("mod a has tag = %0s", tag.scope);
end
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module b ();
genvar g;
generate
for (g=0; g<2; g++) begin : gen
tag tag ();
c c ();
end
endgenerate
always @ (t.cyc) begin
if (t.cyc == 3) $display("mod b has scope = %m");
if (t.cyc == 3) $display("mod b has tag = %0s", tag.scope);
end
endmodule
module c ();
always @ (t.cyc) begin
if (t.cyc == 4) $display("mod c has scope = %m");
if (t.cyc == 4) $display("mod c has tag = %0s", tag.scope);
end
endmodule
module tag ();
bit [100*8-1:0] scope;
initial begin
$sformat(scope,"%m");
$display("created tag with scope = %0s",scope);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Ted Campbell.
//With MULTI_CLK defined shows bug, without it is hidden
`define MULTI_CLK
//bug634
module t (
input i_clk_wr,
input i_clk_rd
);
wire wr$wen;
wire [7:0] wr$addr;
wire [7:0] wr$wdata;
wire [7:0] wr$rdata;
wire rd$wen;
wire [7:0] rd$addr;
wire [7:0] rd$wdata;
wire [7:0] rd$rdata;
wire clk_wr;
wire clk_rd;
`ifdef MULTI_CLK
assign clk_wr = i_clk_wr;
assign clk_rd = i_clk_rd;
`else
assign clk_wr = i_clk_wr;
assign clk_rd = i_clk_wr;
`endif
FooWr u_wr (
.i_clk ( clk_wr ),
.o_wen ( wr$wen ),
.o_addr ( wr$addr ),
.o_wdata ( wr$wdata ),
.i_rdata ( wr$rdata )
);
FooRd u_rd (
.i_clk ( clk_rd ),
.o_wen ( rd$wen ),
.o_addr ( rd$addr ),
.o_wdata ( rd$wdata ),
.i_rdata ( rd$rdata )
);
FooMem u_mem (
.iv_clk ( {clk_wr, clk_rd } ),
.iv_wen ( {wr$wen, rd$wen } ),
.iv_addr ( {wr$addr, rd$addr } ),
.iv_wdata ( {wr$wdata,rd$wdata} ),
.ov_rdata ( {wr$rdata,rd$rdata} )
);
endmodule
// Memory Writer
module FooWr(
input i_clk,
output o_wen,
output [7:0] o_addr,
output [7:0] o_wdata,
input [7:0] i_rdata
);
reg [7:0] cnt = 0;
// Count [0,200]
always @( posedge i_clk )
if ( cnt < 8'd50 )
cnt <= cnt + 8'd1;
// Write addr in (10,30) if even
assign o_wen = ( cnt > 8'd10 ) && ( cnt < 8'd30 ) && ( cnt[0] == 1'b0 );
assign o_addr = cnt;
assign o_wdata = cnt;
endmodule
// Memory Reader
module FooRd(
input i_clk,
output o_wen,
output [7:0] o_addr,
output [7:0] o_wdata,
input [7:0] i_rdata
);
reg [7:0] cnt = 0;
reg [7:0] addr_r;
reg en_r;
// Count [0,200]
always @( posedge i_clk )
if ( cnt < 8'd200 )
cnt <= cnt + 8'd1;
// Read data
assign o_wen = 0;
assign o_addr = cnt - 8'd100;
// Track issued read
always @( posedge i_clk )
begin
addr_r <= o_addr;
en_r <= ( cnt > 8'd110 ) && ( cnt < 8'd130 ) && ( cnt[0] == 1'b0 );
end
// Display to console 100 cycles after writer
always @( negedge i_clk )
if ( en_r ) begin
`ifdef TEST_VERBOSE
$display( "MEM[%x] == %x", addr_r, i_rdata );
`endif
if (addr_r != i_rdata) $stop;
end
endmodule
// Multi-port memory abstraction
module FooMem(
input [2 -1:0] iv_clk,
input [2 -1:0] iv_wen,
input [2*8-1:0] iv_addr,
input [2*8-1:0] iv_wdata,
output [2*8-1:0] ov_rdata
);
FooMemImpl u_impl (
.a_clk ( iv_clk [0*1+:1] ),
.a_wen ( iv_wen [0*1+:1] ),
.a_addr ( iv_addr [0*8+:8] ),
.a_wdata ( iv_wdata[0*8+:8] ),
.a_rdata ( ov_rdata[0*8+:8] ),
.b_clk ( iv_clk [1*1+:1] ),
.b_wen ( iv_wen [1*1+:1] ),
.b_addr ( iv_addr [1*8+:8] ),
.b_wdata ( iv_wdata[1*8+:8] ),
.b_rdata ( ov_rdata[1*8+:8] )
);
endmodule
// Dual-Port L1 Memory Implementation
module FooMemImpl(
input a_clk,
input a_wen,
input [7:0] a_addr,
input [7:0] a_wdata,
output [7:0] a_rdata,
input b_clk,
input b_wen,
input [7:0] b_addr,
input [7:0] b_wdata,
output [7:0] b_rdata
);
/* verilator lint_off MULTIDRIVEN */
reg [7:0] mem[0:255];
/* verilator lint_on MULTIDRIVEN */
always @( posedge a_clk )
if ( a_wen )
mem[a_addr] <= a_wdata;
always @( posedge b_clk )
if ( b_wen )
mem[b_addr] <= b_wdata;
always @( posedge a_clk )
a_rdata <= mem[a_addr];
always @( posedge b_clk )
b_rdata <= mem[b_addr];
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: recv_credit_flow_ctrl.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Monitors the receive completion credits for headers and
// data to make sure the rx_port modules don't request too
// much data from the root complex, as this could result in
// some data being dropped/lost.
// Author: Matt Jacobsen
// Author: Dustin Richmond
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module recv_credit_flow_ctrl
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [11:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
input [7:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
input CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 bytes)w
input RX_ENG_RD_DONE, // Read completed
input TX_ENG_RD_REQ_SENT, // Read completion request issued
output RXBUF_SPACE_AVAIL // High if enough read completion credits exist to make a read completion request
);
reg rCreditAvail=0;
reg rCplDAvail=0;
reg rCplHAvail=0;
reg [12:0] rMaxRecv=0;
reg [11:0] rCplDAmt=0;
reg [7:0] rCplHAmt=0;
reg [11:0] rCplD=0;
reg [7:0] rCplH=0;
reg rInfHCred; // TODO: Altera uses sideband signals (would have been more convenient, thanks Xilinx!)
reg rInfDCred; // TODO: Altera uses sideband signals (would have been more convenient, thanks Xilinx!)
assign RXBUF_SPACE_AVAIL = rCreditAvail;
// Determine the completions required for a max read completion request.
always @(posedge CLK) begin
rInfHCred <= (CONFIG_MAX_CPL_HDR == 0);
rInfDCred <= (CONFIG_MAX_CPL_DATA == 0);
rMaxRecv <= #1 (13'd128<<CONFIG_MAX_READ_REQUEST_SIZE);
rCplHAmt <= #1 (rMaxRecv>>({2'b11, CONFIG_CPL_BOUNDARY_SEL}));
rCplDAmt <= #1 (rMaxRecv>>4);
rCplHAvail <= #1 (rCplH <= CONFIG_MAX_CPL_HDR);
rCplDAvail <= #1 (rCplD <= CONFIG_MAX_CPL_DATA);
rCreditAvail <= #1 ((rCplHAvail|rInfHCred) & (rCplDAvail | rInfDCred));
end
// Count the number of outstanding read completion requests.
always @ (posedge CLK) begin
if (RST) begin
rCplH <= #1 0;
rCplD <= #1 0;
end
else if (RX_ENG_RD_DONE & TX_ENG_RD_REQ_SENT) begin
rCplH <= #1 rCplH;
rCplD <= #1 rCplD;
end
else if (TX_ENG_RD_REQ_SENT) begin
rCplH <= #1 rCplH + rCplHAmt;
rCplD <= #1 rCplD + rCplDAmt;
end
else if (RX_ENG_RD_DONE) begin
rCplH <= #1 rCplH - rCplHAmt;
rCplD <= #1 rCplD - rCplDAmt;
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: recv_credit_flow_ctrl.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Monitors the receive completion credits for headers and
// data to make sure the rx_port modules don't request too
// much data from the root complex, as this could result in
// some data being dropped/lost.
// Author: Matt Jacobsen
// Author: Dustin Richmond
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module recv_credit_flow_ctrl
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [11:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
input [7:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
input CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 bytes)w
input RX_ENG_RD_DONE, // Read completed
input TX_ENG_RD_REQ_SENT, // Read completion request issued
output RXBUF_SPACE_AVAIL // High if enough read completion credits exist to make a read completion request
);
reg rCreditAvail=0;
reg rCplDAvail=0;
reg rCplHAvail=0;
reg [12:0] rMaxRecv=0;
reg [11:0] rCplDAmt=0;
reg [7:0] rCplHAmt=0;
reg [11:0] rCplD=0;
reg [7:0] rCplH=0;
reg rInfHCred; // TODO: Altera uses sideband signals (would have been more convenient, thanks Xilinx!)
reg rInfDCred; // TODO: Altera uses sideband signals (would have been more convenient, thanks Xilinx!)
assign RXBUF_SPACE_AVAIL = rCreditAvail;
// Determine the completions required for a max read completion request.
always @(posedge CLK) begin
rInfHCred <= (CONFIG_MAX_CPL_HDR == 0);
rInfDCred <= (CONFIG_MAX_CPL_DATA == 0);
rMaxRecv <= #1 (13'd128<<CONFIG_MAX_READ_REQUEST_SIZE);
rCplHAmt <= #1 (rMaxRecv>>({2'b11, CONFIG_CPL_BOUNDARY_SEL}));
rCplDAmt <= #1 (rMaxRecv>>4);
rCplHAvail <= #1 (rCplH <= CONFIG_MAX_CPL_HDR);
rCplDAvail <= #1 (rCplD <= CONFIG_MAX_CPL_DATA);
rCreditAvail <= #1 ((rCplHAvail|rInfHCred) & (rCplDAvail | rInfDCred));
end
// Count the number of outstanding read completion requests.
always @ (posedge CLK) begin
if (RST) begin
rCplH <= #1 0;
rCplD <= #1 0;
end
else if (RX_ENG_RD_DONE & TX_ENG_RD_REQ_SENT) begin
rCplH <= #1 rCplH;
rCplD <= #1 rCplD;
end
else if (TX_ENG_RD_REQ_SENT) begin
rCplH <= #1 rCplH + rCplHAmt;
rCplD <= #1 rCplD + rCplDAmt;
end
else if (RX_ENG_RD_DONE) begin
rCplH <= #1 rCplH - rCplHAmt;
rCplD <= #1 rCplD - rCplDAmt;
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_rd_data.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// User interface read buffer. Re orders read data returned from the
// memory controller back to the request order.
//
// Consists of a large buffer for the data, a status RAM and two counters.
//
// The large buffer is implemented with distributed RAM in 6 bit wide,
// 1 read, 1 write mode. The status RAM is implemented with a distributed
// RAM configured as 2 bits wide 1 read/write, 1 read mode.
//
// As read requests are received from the application, the data_buf_addr
// counter supplies the data_buf_addr sent into the memory controller.
// With each read request, the counter is incremented, eventually rolling
// over. This mechanism labels each read request with an incrementing number.
//
// When the memory controller returns read data, it echos the original
// data_buf_addr with the read data.
//
// The status RAM is indexed with the same address as the data buffer
// RAM. Each word of the data buffer RAM has an associated status bit
// and "end" bit. Requests of size 1 return a data burst on two consecutive
// states. Requests of size zero return with a single assertion of rd_data_en.
//
// Upon returning data, the status and end bits are updated for each
// corresponding location in the status RAM indexed by the data_buf_addr
// echoed on the rd_data_addr field.
//
// The other side of the status and data RAMs is indexed by the rd_buf_indx.
// The rd_buf_indx constantly monitors the status bit it is currently
// pointing to. When the status becomes set to the proper state (more on
// this later) read data is returned to the application, and the rd_buf_indx
// is incremented.
//
// At rst the rd_buf_indx is initialized to zero. Data will not have been
// returned from the memory controller yet, so there is nothing to return
// to the application. Evenutally, read requests will be made, and the
// memory controller will return the corresponding data. The memory
// controller may not return this data in the request order. In which
// case, the status bit at location zero, will not indicate
// the data for request zero is ready. Eventually, the memory controller
// will return data for request zero. The data is forwarded on to the
// application, and rd_buf_indx is incremented to point to the next status
// bits and data in the buffers. The status bit will be examined, and if
// data is valid, this data will be returned as well. This process
// continues until the status bit indexed by rd_buf_indx indicates data
// is not ready. This may be because the rd_data_buf
// is empty, or that some data was returned out of order. Since rd_buf_indx
// always increments sequentially, data is always returned to the application
// in request order.
//
// Some further discussion of the status bit is in order. The rd_data_buf
// is a circular buffer. The status bit is a single bit. Distributed RAM
// supports only a single write port. The write port is consumed by
// memory controller read data updates. If a simple '1' were used to
// indicate the status, when rd_data_indx rolled over it would immediately
// encounter a one for a request that may not be ready.
//
// This problem is solved by causing read data returns to flip the
// status bit, and adding hi order bit beyond the size required to
// index the rd_data_buf. Data is considered ready when the status bit
// and this hi order bit are equal.
//
// The status RAM needs to be initialized to zero after reset. This is
// accomplished by cycling through all rd_buf_indx valus and writing a
// zero to the status bits directly following deassertion of reset. This
// mechanism is used for similar purposes
// for the wr_data_buf.
//
// When ORDERING == "STRICT", read data reordering is unnecessary. For thi
// case, most of the logic in the block is not generated.
`timescale 1 ps / 1 ps
// User interface read data.
module mig_7series_v1_9_ui_rd_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ORDERING = "NORM"
)
(/*AUTOARG*/
// Outputs
ram_init_done_r, ram_init_addr, app_rd_data_valid, app_rd_data_end,
app_rd_data, app_ecc_multiple_err, rd_buf_full, rd_data_buf_addr_r,
// Inputs
rst, clk, rd_data_en, rd_data_addr, rd_data_offset, rd_data_end,
rd_data, ecc_multiple, rd_accepted
);
input rst;
input clk;
output wire ram_init_done_r;
output wire [3:0] ram_init_addr;
// rd_buf_indx points to the status and data storage rams for
// reading data out to the app.
reg [5:0] rd_buf_indx_r;
(* keep = "true", max_fanout = 10 *) reg ram_init_done_r_lcl /* synthesis syn_maxfan = 10 */;
assign ram_init_done_r = ram_init_done_r_lcl;
wire app_rd_data_valid_ns;
wire single_data;
reg [5:0] rd_buf_indx_ns;
generate begin : rd_buf_indx
wire upd_rd_buf_indx = ~ram_init_done_r_lcl || app_rd_data_valid_ns;
// Loop through all status write addresses once after rst. Initializes
// the status and pointer RAMs.
wire ram_init_done_ns =
~rst && (ram_init_done_r_lcl || (rd_buf_indx_r[4:0] == 5'h1f));
always @(posedge clk) ram_init_done_r_lcl <= #TCQ ram_init_done_ns;
always @(/*AS*/rd_buf_indx_r or rst or single_data
or upd_rd_buf_indx) begin
rd_buf_indx_ns = rd_buf_indx_r;
if (rst) rd_buf_indx_ns = 6'b0;
else if (upd_rd_buf_indx) rd_buf_indx_ns =
// need to use every slot of RAMB32 if all address bits are used
rd_buf_indx_r + 6'h1 + (DATA_BUF_ADDR_WIDTH == 5 ? 0 : single_data);
end
always @(posedge clk) rd_buf_indx_r <= #TCQ rd_buf_indx_ns;
end
endgenerate
assign ram_init_addr = rd_buf_indx_r[3:0];
input rd_data_en;
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input rd_data_offset;
input rd_data_end;
input [APP_DATA_WIDTH-1:0] rd_data;
(* keep = "true", max_fanout = 10 *) output reg app_rd_data_valid /* synthesis syn_maxfan = 10 */;
output reg app_rd_data_end;
output reg [APP_DATA_WIDTH-1:0] app_rd_data;
input [3:0] ecc_multiple;
reg [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_r = 'b0;
output wire [2*nCK_PER_CLK-1:0] app_ecc_multiple_err;
assign app_ecc_multiple_err = app_ecc_multiple_err_r;
input rd_accepted;
output wire rd_buf_full;
output wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r;
// Compute dimensions of read data buffer. Depending on width of
// DQ bus and DRAM CK
// to fabric ratio, number of RAM32Ms is variable. RAM32Ms are used in
// single write, single read, 6 bit wide mode.
localparam RD_BUF_WIDTH = APP_DATA_WIDTH + (ECC == "OFF" ? 0 : 2*nCK_PER_CLK);
localparam FULL_RAM_CNT = (RD_BUF_WIDTH/6);
localparam REMAINDER = RD_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
if (ORDERING == "STRICT") begin : strict_mode
assign app_rd_data_valid_ns = 1'b0;
assign single_data = 1'b0;
assign rd_buf_full = 1'b0;
reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns =
rst
? 0
: rd_data_buf_addr_r_lcl + rd_accepted;
always @(posedge clk) rd_data_buf_addr_r_lcl <=
#TCQ rd_data_buf_addr_ns;
assign rd_data_buf_addr_r = rd_data_buf_addr_ns;
// app_* signals required to be registered.
if (ECC == "OFF") begin : ecc_off
always @(/*AS*/rd_data) app_rd_data = rd_data;
always @(/*AS*/rd_data_en) app_rd_data_valid = rd_data_en;
always @(/*AS*/rd_data_end) app_rd_data_end = rd_data_end;
end
else begin : ecc_on
always @(posedge clk) app_rd_data <= #TCQ rd_data;
always @(posedge clk) app_rd_data_valid <= #TCQ rd_data_en;
always @(posedge clk) app_rd_data_end <= #TCQ rd_data_end;
always @(posedge clk) app_ecc_multiple_err_r <= #TCQ ecc_multiple;
end
end
else begin : not_strict_mode
(* keep = "true", max_fanout = 10 *) wire rd_buf_we = ~ram_init_done_r_lcl || rd_data_en /* synthesis syn_maxfan = 10 */;
// In configurations where read data is returned in a single fabric cycle
// the offset is always zero and we can use the bit to get a deeper
// FIFO. The RAMB32 has 5 address bits, so when the DATA_BUF_ADDR_WIDTH
// is set to use them all, discard the offset. Otherwise, include the
// offset.
wire [4:0] rd_buf_wr_addr = DATA_BUF_ADDR_WIDTH == 5 ?
rd_data_addr :
{rd_data_addr, rd_data_offset};
wire [1:0] rd_status;
// Instantiate status RAM. One bit for status and one for "end".
begin : status_ram
// Turns out read to write back status is a timing path. Update
// the status in the ram on the state following the read. Bypass
// the write data into the status read path.
wire [4:0] status_ram_wr_addr_ns = ram_init_done_r_lcl
? rd_buf_wr_addr
: rd_buf_indx_r[4:0];
reg [4:0] status_ram_wr_addr_r;
always @(posedge clk) status_ram_wr_addr_r <=
#TCQ status_ram_wr_addr_ns;
wire [1:0] wr_status;
// Not guaranteed to write second status bit. If it is written, always
// copy in the first status bit.
reg wr_status_r1;
always @(posedge clk) wr_status_r1 <= #TCQ wr_status[0];
wire [1:0] status_ram_wr_data_ns =
ram_init_done_r_lcl
? {rd_data_end, ~(rd_data_offset
? wr_status_r1
: wr_status[0])}
: 2'b0;
reg [1:0] status_ram_wr_data_r;
always @(posedge clk) status_ram_wr_data_r <=
#TCQ status_ram_wr_data_ns;
reg rd_buf_we_r1;
always @(posedge clk) rd_buf_we_r1 <= #TCQ rd_buf_we;
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(rd_status),
.DOB(),
.DOC(wr_status),
.DOD(),
.DIA(status_ram_wr_data_r),
.DIB(2'b0),
.DIC(status_ram_wr_data_r),
.DID(status_ram_wr_data_r),
.ADDRA(rd_buf_indx_r[4:0]),
.ADDRB(5'b0),
.ADDRC(status_ram_wr_addr_ns),
.ADDRD(status_ram_wr_addr_r),
.WE(rd_buf_we_r1),
.WCLK(clk)
);
end // block: status_ram
wire [RAM_WIDTH-1:0] rd_buf_out_data;
begin : rd_buf
wire [RAM_WIDTH-1:0] rd_buf_in_data;
if (REMAINDER == 0)
if (ECC == "OFF")
assign rd_buf_in_data = rd_data;
else
assign rd_buf_in_data = {ecc_multiple, rd_data};
else
if (ECC == "OFF")
assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, rd_data};
else
assign rd_buf_in_data =
{{6-REMAINDER{1'b0}}, ecc_multiple, rd_data};
// Dedicated copy for driving distributed RAM.
(* keep = "true" *) reg [4:0] rd_buf_indx_copy_r /* synthesis syn_keep = 1 */;
always @(posedge clk) rd_buf_indx_copy_r <= #TCQ rd_buf_indx_ns[4:0];
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(rd_buf_out_data[((i*6)+4)+:2]),
.DOB(rd_buf_out_data[((i*6)+2)+:2]),
.DOC(rd_buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(rd_buf_in_data[((i*6)+4)+:2]),
.DIB(rd_buf_in_data[((i*6)+2)+:2]),
.DIC(rd_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_buf_indx_copy_r[4:0]),
.ADDRB(rd_buf_indx_copy_r[4:0]),
.ADDRC(rd_buf_indx_copy_r[4:0]),
.ADDRD(rd_buf_wr_addr),
.WE(rd_buf_we),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
wire rd_data_rdy = (rd_status[0] == rd_buf_indx_r[5]);
(* keep = "true", max_fanout = 10 *) wire bypass = rd_data_en && (rd_buf_wr_addr[4:0] == rd_buf_indx_r[4:0]) /* synthesis syn_maxfan = 10 */;
assign app_rd_data_valid_ns =
ram_init_done_r_lcl && (bypass || rd_data_rdy);
wire app_rd_data_end_ns = bypass ? rd_data_end : rd_status[1];
always @(posedge clk) app_rd_data_valid <= #TCQ app_rd_data_valid_ns;
always @(posedge clk) app_rd_data_end <= #TCQ app_rd_data_end_ns;
assign single_data =
app_rd_data_valid_ns && app_rd_data_end_ns && ~rd_buf_indx_r[0];
wire [APP_DATA_WIDTH-1:0] app_rd_data_ns =
bypass
? rd_data
: rd_buf_out_data[APP_DATA_WIDTH-1:0];
always @(posedge clk) app_rd_data <= #TCQ app_rd_data_ns;
if (ECC != "OFF") begin : assign_app_ecc_multiple
wire [3:0] app_ecc_multiple_err_ns =
bypass
? ecc_multiple
: rd_buf_out_data[APP_DATA_WIDTH+:4];
always @(posedge clk) app_ecc_multiple_err_r <=
#TCQ app_ecc_multiple_err_ns;
end
//Added to fix timing. The signal app_rd_data_valid has
//a very high fanout. So making a dedicated copy for usage
//with the occ_cnt counter.
(* equivalent_register_removal = "no" *)
reg app_rd_data_valid_copy;
always @(posedge clk) app_rd_data_valid_copy <= #TCQ app_rd_data_valid_ns;
// Keep track of how many entries in the queue hold data.
wire free_rd_buf = app_rd_data_valid_copy && app_rd_data_end; //changed to use registered version
//of the signals in ordered to fix timing
reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_r;
wire [DATA_BUF_ADDR_WIDTH:0] occ_minus_one = occ_cnt_r - 1;
wire [DATA_BUF_ADDR_WIDTH:0] occ_plus_one = occ_cnt_r + 1;
begin : occupied_counter
reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_ns;
always @(/*AS*/free_rd_buf or occ_cnt_r or rd_accepted or rst or occ_minus_one or occ_plus_one) begin
occ_cnt_ns = occ_cnt_r;
if (rst) occ_cnt_ns = 0;
else case ({rd_accepted, free_rd_buf})
2'b01 : occ_cnt_ns = occ_minus_one;
2'b10 : occ_cnt_ns = occ_plus_one;
endcase // case ({wr_data_end, new_rd_data})
end
always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
assign rd_buf_full = occ_cnt_ns[DATA_BUF_ADDR_WIDTH];
`ifdef MC_SVA
rd_data_buffer_full: cover property (@(posedge clk) (~rst && rd_buf_full));
rd_data_buffer_inc_dec_15: cover property (@(posedge clk)
(~rst && rd_accepted && free_rd_buf && (occ_cnt_r == 'hf)));
rd_data_underflow: assert property (@(posedge clk)
(rst || !((occ_cnt_r == 'b0) && (occ_cnt_ns == 'h1f))));
rd_data_overflow: assert property (@(posedge clk)
(rst || !((occ_cnt_r == 'h10) && (occ_cnt_ns == 'h11))));
`endif
end // block: occupied_counter
// Generate the data_buf_address written into the memory controller
// for reads. Increment with each accepted read, and rollover at 0xf.
reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl;
assign rd_data_buf_addr_r = rd_data_buf_addr_r_lcl;
begin : data_buf_addr
reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns;
always @(/*AS*/rd_accepted or rd_data_buf_addr_r_lcl or rst) begin
rd_data_buf_addr_ns = rd_data_buf_addr_r_lcl;
if (rst) rd_data_buf_addr_ns = 0;
else if (rd_accepted) rd_data_buf_addr_ns =
rd_data_buf_addr_r_lcl + 1;
end
always @(posedge clk) rd_data_buf_addr_r_lcl <=
#TCQ rd_data_buf_addr_ns;
end // block: data_buf_addr
end // block: not_strict_mode
endgenerate
endmodule // ui_rd_data
// Local Variables:
// verilog-library-directories:(".")
// End:
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
//
// There are two modes:
// - lf_ed_toggle_mode == 0: the output is set low (resp. high) when a low
// (resp. high) edge/peak is detected, with hysteresis
// - lf_ed_toggle_mode == 1: the output is toggling whenever an edge/peak
// is detected.
// That way you can detect two consecutive edges/peaks at the same level (L/H)
//
// Output:
// - ssp_frame (wired to TIOA1 on the arm) for the edge detection/state
// - ssp_clk: cross_lo
`include "lp20khz_1MSa_iir_filter.v"
`include "lf_edge_detect.v"
module lo_edge_detect(
input pck0, input pck_divclk,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk,
output ssp_frame, input ssp_dout, output ssp_clk,
input cross_lo,
output dbg,
input lf_field,
input lf_ed_toggle_mode, input [7:0] lf_ed_threshold
);
wire tag_modulation = ssp_dout & !lf_field;
wire reader_modulation = !ssp_dout & lf_field & pck_divclk;
// No logic, straight through.
assign pwr_oe1 = 1'b0; // not used in LF mode
assign pwr_oe3 = 1'b0; // base antenna load = 33 Ohms
// when modulating, add another 33 Ohms and 10k Ohms in parallel:
assign pwr_oe2 = tag_modulation;
assign pwr_oe4 = tag_modulation;
assign ssp_clk = cross_lo;
assign pwr_lo = reader_modulation;
assign pwr_hi = 1'b0;
// filter the ADC values
wire data_rdy;
wire [7:0] adc_filtered;
assign adc_clk = pck0;
lp20khz_1MSa_iir_filter adc_filter(pck0, adc_d, data_rdy, adc_filtered);
// detect edges
wire [7:0] high_threshold, highz_threshold, lowz_threshold, low_threshold;
wire [7:0] max, min;
wire edge_state, edge_toggle;
lf_edge_detect lf_ed(pck0, adc_filtered, lf_ed_threshold,
max, min,
high_threshold, highz_threshold, lowz_threshold, low_threshold,
edge_state, edge_toggle);
assign dbg = lf_ed_toggle_mode ? edge_toggle : edge_state;
assign ssp_frame = lf_ed_toggle_mode ? edge_toggle : edge_state;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level rank machine structural block. This block
// instantiates a configurable number of rank controller blocks.
`timescale 1ps/1ps
module mig_7series_v1_9_rank_mach #
(
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCKESR = 4,
parameter nCK_PER_CLK = 2,
parameter CL = 5,
parameter CWL = 5,
parameter DQRD2DQWR_DLY = 2,
parameter nFAW = 30,
parameter nREFRESH_BANK = 8,
parameter nRRD = 4,
parameter nWTR = 4,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r, inhbt_rd,
inhbt_wr, maint_rank_r, maint_zq_r, maint_sre_r, maint_srx_r, app_sr_active,
app_ref_ack, app_zq_ack, col_rd_wr, maint_ref_zq_wip,
// Inputs
wr_this_rank_r, slot_1_present, slot_0_present, sending_row,
sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r,
maint_wip_r, insert_maint_r1, init_calib_complete, clk, app_zq_req,
app_sr_req, app_ref_req, app_periodic_rd_req, act_this_rank_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v
input app_ref_req; // To rank_cntrl0 of rank_cntrl.v
input app_zq_req; // To rank_common0 of rank_common.v
input app_sr_req; // To rank_common0 of rank_common.v
input clk; // To rank_cntrl0 of rank_cntrl.v, ...
input col_rd_wr; // To rank_cntrl0 of rank_cntrl.v, ...
input init_calib_complete; // To rank_cntrl0 of rank_cntrl.v, ...
input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ...
input maint_wip_r; // To rank_common0 of rank_common.v
input periodic_rd_ack_r; // To rank_common0 of rank_common.v
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input rst; // To rank_cntrl0 of rank_cntrl.v, ...
input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v
input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v
input [7:0] slot_0_present; // To rank_common0 of rank_common.v
input [7:0] slot_1_present; // To rank_common0 of rank_common.v
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output maint_req_r; // From rank_common0 of rank_common.v
output periodic_rd_r; // From rank_common0 of rank_common.v
output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v
wire refresh_tick; // From rank_common0 of rank_common.v
// End of automatics
output [RANKS-1:0] inhbt_act_faw_r;
output [RANKS-1:0] inhbt_rd;
output [RANKS-1:0] inhbt_wr;
output [RANK_WIDTH-1:0] maint_rank_r;
output maint_zq_r;
output maint_sre_r;
output maint_srx_r;
output app_sr_active;
output app_ref_ack;
output app_zq_ack;
output maint_ref_zq_wip;
wire [RANKS-1:0] refresh_request;
wire [RANKS-1:0] periodic_rd_request;
wire [RANKS-1:0] clear_periodic_rd_request;
genvar ID;
generate
for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl
mig_7series_v1_9_rank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.BURST_MODE (BURST_MODE),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.CL (CL),
.CWL (CWL),
.DQRD2DQWR_DLY (DQRD2DQWR_DLY),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV))
rank_cntrl0
(.clear_periodic_rd_request (clear_periodic_rd_request[ID]),
.inhbt_act_faw_r (inhbt_act_faw_r[ID]),
.inhbt_rd (inhbt_rd[ID]),
.inhbt_wr (inhbt_wr[ID]),
.periodic_rd_request (periodic_rd_request[ID]),
.refresh_request (refresh_request[ID]),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst),
.col_rd_wr (col_rd_wr),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_ref_req (app_ref_req),
.init_calib_complete (init_calib_complete),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.refresh_tick (refresh_tick),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]));
end
endgenerate
mig_7series_v1_9_rank_common #
(/*AUTOINSTPARAM*/
// Parameters
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.nCKESR (nCKESR),
.nCK_PER_CLK (nCK_PER_CLK),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV))
rank_common0
(.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]),
/*AUTOINST*/
// Outputs
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.refresh_tick (refresh_tick),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_req_r (maint_req_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_ref_zq_wip (maint_ref_zq_wip),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.insert_maint_r1 (insert_maint_r1),
.refresh_request (refresh_request[RANKS-1:0]),
.maint_wip_r (maint_wip_r),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.periodic_rd_request (periodic_rd_request[RANKS-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r));
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level rank machine structural block. This block
// instantiates a configurable number of rank controller blocks.
`timescale 1ps/1ps
module mig_7series_v1_9_rank_mach #
(
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCKESR = 4,
parameter nCK_PER_CLK = 2,
parameter CL = 5,
parameter CWL = 5,
parameter DQRD2DQWR_DLY = 2,
parameter nFAW = 30,
parameter nREFRESH_BANK = 8,
parameter nRRD = 4,
parameter nWTR = 4,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r, inhbt_rd,
inhbt_wr, maint_rank_r, maint_zq_r, maint_sre_r, maint_srx_r, app_sr_active,
app_ref_ack, app_zq_ack, col_rd_wr, maint_ref_zq_wip,
// Inputs
wr_this_rank_r, slot_1_present, slot_0_present, sending_row,
sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r,
maint_wip_r, insert_maint_r1, init_calib_complete, clk, app_zq_req,
app_sr_req, app_ref_req, app_periodic_rd_req, act_this_rank_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v
input app_ref_req; // To rank_cntrl0 of rank_cntrl.v
input app_zq_req; // To rank_common0 of rank_common.v
input app_sr_req; // To rank_common0 of rank_common.v
input clk; // To rank_cntrl0 of rank_cntrl.v, ...
input col_rd_wr; // To rank_cntrl0 of rank_cntrl.v, ...
input init_calib_complete; // To rank_cntrl0 of rank_cntrl.v, ...
input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ...
input maint_wip_r; // To rank_common0 of rank_common.v
input periodic_rd_ack_r; // To rank_common0 of rank_common.v
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input rst; // To rank_cntrl0 of rank_cntrl.v, ...
input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v
input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v
input [7:0] slot_0_present; // To rank_common0 of rank_common.v
input [7:0] slot_1_present; // To rank_common0 of rank_common.v
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output maint_req_r; // From rank_common0 of rank_common.v
output periodic_rd_r; // From rank_common0 of rank_common.v
output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v
wire refresh_tick; // From rank_common0 of rank_common.v
// End of automatics
output [RANKS-1:0] inhbt_act_faw_r;
output [RANKS-1:0] inhbt_rd;
output [RANKS-1:0] inhbt_wr;
output [RANK_WIDTH-1:0] maint_rank_r;
output maint_zq_r;
output maint_sre_r;
output maint_srx_r;
output app_sr_active;
output app_ref_ack;
output app_zq_ack;
output maint_ref_zq_wip;
wire [RANKS-1:0] refresh_request;
wire [RANKS-1:0] periodic_rd_request;
wire [RANKS-1:0] clear_periodic_rd_request;
genvar ID;
generate
for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl
mig_7series_v1_9_rank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.BURST_MODE (BURST_MODE),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.CL (CL),
.CWL (CWL),
.DQRD2DQWR_DLY (DQRD2DQWR_DLY),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV))
rank_cntrl0
(.clear_periodic_rd_request (clear_periodic_rd_request[ID]),
.inhbt_act_faw_r (inhbt_act_faw_r[ID]),
.inhbt_rd (inhbt_rd[ID]),
.inhbt_wr (inhbt_wr[ID]),
.periodic_rd_request (periodic_rd_request[ID]),
.refresh_request (refresh_request[ID]),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst),
.col_rd_wr (col_rd_wr),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_ref_req (app_ref_req),
.init_calib_complete (init_calib_complete),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.refresh_tick (refresh_tick),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]));
end
endgenerate
mig_7series_v1_9_rank_common #
(/*AUTOINSTPARAM*/
// Parameters
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.nCKESR (nCKESR),
.nCK_PER_CLK (nCK_PER_CLK),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV))
rank_common0
(.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]),
/*AUTOINST*/
// Outputs
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.refresh_tick (refresh_tick),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_req_r (maint_req_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_ref_zq_wip (maint_ref_zq_wip),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.insert_maint_r1 (insert_maint_r1),
.refresh_request (refresh_request[RANKS-1:0]),
.maint_wip_r (maint_wip_r),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.periodic_rd_request (periodic_rd_request[RANKS-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r));
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level rank machine structural block. This block
// instantiates a configurable number of rank controller blocks.
`timescale 1ps/1ps
module mig_7series_v1_9_rank_mach #
(
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCKESR = 4,
parameter nCK_PER_CLK = 2,
parameter CL = 5,
parameter CWL = 5,
parameter DQRD2DQWR_DLY = 2,
parameter nFAW = 30,
parameter nREFRESH_BANK = 8,
parameter nRRD = 4,
parameter nWTR = 4,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_BM_BV_WIDTH = 16,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
periodic_rd_rank_r, periodic_rd_r, maint_req_r, inhbt_act_faw_r, inhbt_rd,
inhbt_wr, maint_rank_r, maint_zq_r, maint_sre_r, maint_srx_r, app_sr_active,
app_ref_ack, app_zq_ack, col_rd_wr, maint_ref_zq_wip,
// Inputs
wr_this_rank_r, slot_1_present, slot_0_present, sending_row,
sending_col, rst, rd_this_rank_r, rank_busy_r, periodic_rd_ack_r,
maint_wip_r, insert_maint_r1, init_calib_complete, clk, app_zq_req,
app_sr_req, app_ref_req, app_periodic_rd_req, act_this_rank_r
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input app_periodic_rd_req; // To rank_cntrl0 of rank_cntrl.v
input app_ref_req; // To rank_cntrl0 of rank_cntrl.v
input app_zq_req; // To rank_common0 of rank_common.v
input app_sr_req; // To rank_common0 of rank_common.v
input clk; // To rank_cntrl0 of rank_cntrl.v, ...
input col_rd_wr; // To rank_cntrl0 of rank_cntrl.v, ...
input init_calib_complete; // To rank_cntrl0 of rank_cntrl.v, ...
input insert_maint_r1; // To rank_cntrl0 of rank_cntrl.v, ...
input maint_wip_r; // To rank_common0 of rank_common.v
input periodic_rd_ack_r; // To rank_common0 of rank_common.v
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r; // To rank_cntrl0 of rank_cntrl.v
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
input rst; // To rank_cntrl0 of rank_cntrl.v, ...
input [nBANK_MACHS-1:0] sending_col; // To rank_cntrl0 of rank_cntrl.v
input [nBANK_MACHS-1:0] sending_row; // To rank_cntrl0 of rank_cntrl.v
input [7:0] slot_0_present; // To rank_common0 of rank_common.v
input [7:0] slot_1_present; // To rank_common0 of rank_common.v
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r; // To rank_cntrl0 of rank_cntrl.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output maint_req_r; // From rank_common0 of rank_common.v
output periodic_rd_r; // From rank_common0 of rank_common.v
output [RANK_WIDTH-1:0] periodic_rd_rank_r; // From rank_common0 of rank_common.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire maint_prescaler_tick_r; // From rank_common0 of rank_common.v
wire refresh_tick; // From rank_common0 of rank_common.v
// End of automatics
output [RANKS-1:0] inhbt_act_faw_r;
output [RANKS-1:0] inhbt_rd;
output [RANKS-1:0] inhbt_wr;
output [RANK_WIDTH-1:0] maint_rank_r;
output maint_zq_r;
output maint_sre_r;
output maint_srx_r;
output app_sr_active;
output app_ref_ack;
output app_zq_ack;
output maint_ref_zq_wip;
wire [RANKS-1:0] refresh_request;
wire [RANKS-1:0] periodic_rd_request;
wire [RANKS-1:0] clear_periodic_rd_request;
genvar ID;
generate
for (ID=0; ID<RANKS; ID=ID+1) begin:rank_cntrl
mig_7series_v1_9_rank_cntrl #
(/*AUTOINSTPARAM*/
// Parameters
.BURST_MODE (BURST_MODE),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.CL (CL),
.CWL (CWL),
.DQRD2DQWR_DLY (DQRD2DQWR_DLY),
.nFAW (nFAW),
.nREFRESH_BANK (nREFRESH_BANK),
.nRRD (nRRD),
.nWTR (nWTR),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_BM_BV_WIDTH (RANK_BM_BV_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV))
rank_cntrl0
(.clear_periodic_rd_request (clear_periodic_rd_request[ID]),
.inhbt_act_faw_r (inhbt_act_faw_r[ID]),
.inhbt_rd (inhbt_rd[ID]),
.inhbt_wr (inhbt_wr[ID]),
.periodic_rd_request (periodic_rd_request[ID]),
.refresh_request (refresh_request[ID]),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst),
.col_rd_wr (col_rd_wr),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.act_this_rank_r (act_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.wr_this_rank_r (wr_this_rank_r[RANK_BM_BV_WIDTH-1:0]),
.app_ref_req (app_ref_req),
.init_calib_complete (init_calib_complete),
.rank_busy_r (rank_busy_r[(RANKS*nBANK_MACHS)-1:0]),
.refresh_tick (refresh_tick),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.app_periodic_rd_req (app_periodic_rd_req),
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.rd_this_rank_r (rd_this_rank_r[RANK_BM_BV_WIDTH-1:0]));
end
endgenerate
mig_7series_v1_9_rank_common #
(/*AUTOINSTPARAM*/
// Parameters
.DRAM_TYPE (DRAM_TYPE),
.MAINT_PRESCALER_DIV (MAINT_PRESCALER_DIV),
.nBANK_MACHS (nBANK_MACHS),
.nCKESR (nCKESR),
.nCK_PER_CLK (nCK_PER_CLK),
.PERIODIC_RD_TIMER_DIV (PERIODIC_RD_TIMER_DIV),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REFRESH_TIMER_DIV (REFRESH_TIMER_DIV),
.ZQ_TIMER_DIV (ZQ_TIMER_DIV))
rank_common0
(.clear_periodic_rd_request (clear_periodic_rd_request[RANKS-1:0]),
/*AUTOINST*/
// Outputs
.maint_prescaler_tick_r (maint_prescaler_tick_r),
.refresh_tick (refresh_tick),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.maint_srx_r (maint_srx_r),
.maint_req_r (maint_req_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_ref_zq_wip (maint_ref_zq_wip),
.periodic_rd_r (periodic_rd_r),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.insert_maint_r1 (insert_maint_r1),
.refresh_request (refresh_request[RANKS-1:0]),
.maint_wip_r (maint_wip_r),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]),
.periodic_rd_request (periodic_rd_request[RANKS-1:0]),
.periodic_rd_ack_r (periodic_rd_ack_r));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] operand_a = crc[7:0];
wire [7:0] operand_b = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [6:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[6:0]),
// Inputs
.clk (clk),
.operand_a (operand_a[7:0]),
.operand_b (operand_b[7:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h8a78c2ec4946ac38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
// Inputs
input wire clk,
input wire [7:0] operand_a, // operand a
input wire [7:0] operand_b, // operand b
// Outputs
output wire [6:0] out
);
wire [6:0] clz_a;
wire [6:0] clz_b;
clz u_clz_a
(
// Inputs
.data_i (operand_a),
.out (clz_a));
clz u_clz_b
(
// Inputs
.data_i (operand_b),
.out (clz_b));
assign out = clz_a - clz_b;
`ifdef TEST_VERBOSE
always @(posedge clk)
$display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b);
`endif
endmodule
`define def_0000_001x 8'b0000_0010, 8'b0000_0011
`define def_0000_01xx 8'b0000_0100, 8'b0000_0101, 8'b0000_0110, 8'b0000_0111
`define def_0000_10xx 8'b0000_1000, 8'b0000_1001, 8'b0000_1010, 8'b0000_1011
`define def_0000_11xx 8'b0000_1100, 8'b0000_1101, 8'b0000_1110, 8'b0000_1111
`define def_0000_1xxx `def_0000_10xx, `def_0000_11xx
`define def_0001_00xx 8'b0001_0000, 8'b0001_0001, 8'b0001_0010, 8'b0001_0011
`define def_0001_01xx 8'b0001_0100, 8'b0001_0101, 8'b0001_0110, 8'b0001_0111
`define def_0001_10xx 8'b0001_1000, 8'b0001_1001, 8'b0001_1010, 8'b0001_1011
`define def_0001_11xx 8'b0001_1100, 8'b0001_1101, 8'b0001_1110, 8'b0001_1111
`define def_0010_00xx 8'b0010_0000, 8'b0010_0001, 8'b0010_0010, 8'b0010_0011
`define def_0010_01xx 8'b0010_0100, 8'b0010_0101, 8'b0010_0110, 8'b0010_0111
`define def_0010_10xx 8'b0010_1000, 8'b0010_1001, 8'b0010_1010, 8'b0010_1011
`define def_0010_11xx 8'b0010_1100, 8'b0010_1101, 8'b0010_1110, 8'b0010_1111
`define def_0011_00xx 8'b0011_0000, 8'b0011_0001, 8'b0011_0010, 8'b0011_0011
`define def_0011_01xx 8'b0011_0100, 8'b0011_0101, 8'b0011_0110, 8'b0011_0111
`define def_0011_10xx 8'b0011_1000, 8'b0011_1001, 8'b0011_1010, 8'b0011_1011
`define def_0011_11xx 8'b0011_1100, 8'b0011_1101, 8'b0011_1110, 8'b0011_1111
`define def_0100_00xx 8'b0100_0000, 8'b0100_0001, 8'b0100_0010, 8'b0100_0011
`define def_0100_01xx 8'b0100_0100, 8'b0100_0101, 8'b0100_0110, 8'b0100_0111
`define def_0100_10xx 8'b0100_1000, 8'b0100_1001, 8'b0100_1010, 8'b0100_1011
`define def_0100_11xx 8'b0100_1100, 8'b0100_1101, 8'b0100_1110, 8'b0100_1111
`define def_0101_00xx 8'b0101_0000, 8'b0101_0001, 8'b0101_0010, 8'b0101_0011
`define def_0101_01xx 8'b0101_0100, 8'b0101_0101, 8'b0101_0110, 8'b0101_0111
`define def_0101_10xx 8'b0101_1000, 8'b0101_1001, 8'b0101_1010, 8'b0101_1011
`define def_0101_11xx 8'b0101_1100, 8'b0101_1101, 8'b0101_1110, 8'b0101_1111
`define def_0110_00xx 8'b0110_0000, 8'b0110_0001, 8'b0110_0010, 8'b0110_0011
`define def_0110_01xx 8'b0110_0100, 8'b0110_0101, 8'b0110_0110, 8'b0110_0111
`define def_0110_10xx 8'b0110_1000, 8'b0110_1001, 8'b0110_1010, 8'b0110_1011
`define def_0110_11xx 8'b0110_1100, 8'b0110_1101, 8'b0110_1110, 8'b0110_1111
`define def_0111_00xx 8'b0111_0000, 8'b0111_0001, 8'b0111_0010, 8'b0111_0011
`define def_0111_01xx 8'b0111_0100, 8'b0111_0101, 8'b0111_0110, 8'b0111_0111
`define def_0111_10xx 8'b0111_1000, 8'b0111_1001, 8'b0111_1010, 8'b0111_1011
`define def_0111_11xx 8'b0111_1100, 8'b0111_1101, 8'b0111_1110, 8'b0111_1111
`define def_1000_00xx 8'b1000_0000, 8'b1000_0001, 8'b1000_0010, 8'b1000_0011
`define def_1000_01xx 8'b1000_0100, 8'b1000_0101, 8'b1000_0110, 8'b1000_0111
`define def_1000_10xx 8'b1000_1000, 8'b1000_1001, 8'b1000_1010, 8'b1000_1011
`define def_1000_11xx 8'b1000_1100, 8'b1000_1101, 8'b1000_1110, 8'b1000_1111
`define def_1001_00xx 8'b1001_0000, 8'b1001_0001, 8'b1001_0010, 8'b1001_0011
`define def_1001_01xx 8'b1001_0100, 8'b1001_0101, 8'b1001_0110, 8'b1001_0111
`define def_1001_10xx 8'b1001_1000, 8'b1001_1001, 8'b1001_1010, 8'b1001_1011
`define def_1001_11xx 8'b1001_1100, 8'b1001_1101, 8'b1001_1110, 8'b1001_1111
`define def_1010_00xx 8'b1010_0000, 8'b1010_0001, 8'b1010_0010, 8'b1010_0011
`define def_1010_01xx 8'b1010_0100, 8'b1010_0101, 8'b1010_0110, 8'b1010_0111
`define def_1010_10xx 8'b1010_1000, 8'b1010_1001, 8'b1010_1010, 8'b1010_1011
`define def_1010_11xx 8'b1010_1100, 8'b1010_1101, 8'b1010_1110, 8'b1010_1111
`define def_1011_00xx 8'b1011_0000, 8'b1011_0001, 8'b1011_0010, 8'b1011_0011
`define def_1011_01xx 8'b1011_0100, 8'b1011_0101, 8'b1011_0110, 8'b1011_0111
`define def_1011_10xx 8'b1011_1000, 8'b1011_1001, 8'b1011_1010, 8'b1011_1011
`define def_1011_11xx 8'b1011_1100, 8'b1011_1101, 8'b1011_1110, 8'b1011_1111
`define def_1100_00xx 8'b1100_0000, 8'b1100_0001, 8'b1100_0010, 8'b1100_0011
`define def_1100_01xx 8'b1100_0100, 8'b1100_0101, 8'b1100_0110, 8'b1100_0111
`define def_1100_10xx 8'b1100_1000, 8'b1100_1001, 8'b1100_1010, 8'b1100_1011
`define def_1100_11xx 8'b1100_1100, 8'b1100_1101, 8'b1100_1110, 8'b1100_1111
`define def_1101_00xx 8'b1101_0000, 8'b1101_0001, 8'b1101_0010, 8'b1101_0011
`define def_1101_01xx 8'b1101_0100, 8'b1101_0101, 8'b1101_0110, 8'b1101_0111
`define def_1101_10xx 8'b1101_1000, 8'b1101_1001, 8'b1101_1010, 8'b1101_1011
`define def_1101_11xx 8'b1101_1100, 8'b1101_1101, 8'b1101_1110, 8'b1101_1111
`define def_1110_00xx 8'b1110_0000, 8'b1110_0001, 8'b1110_0010, 8'b1110_0011
`define def_1110_01xx 8'b1110_0100, 8'b1110_0101, 8'b1110_0110, 8'b1110_0111
`define def_1110_10xx 8'b1110_1000, 8'b1110_1001, 8'b1110_1010, 8'b1110_1011
`define def_1110_11xx 8'b1110_1100, 8'b1110_1101, 8'b1110_1110, 8'b1110_1111
`define def_1111_00xx 8'b1111_0000, 8'b1111_0001, 8'b1111_0010, 8'b1111_0011
`define def_1111_01xx 8'b1111_0100, 8'b1111_0101, 8'b1111_0110, 8'b1111_0111
`define def_1111_10xx 8'b1111_1000, 8'b1111_1001, 8'b1111_1010, 8'b1111_1011
`define def_1111_11xx 8'b1111_1100, 8'b1111_1101, 8'b1111_1110, 8'b1111_1111
`define def_0001_xxxx `def_0001_00xx, `def_0001_01xx, `def_0001_10xx, `def_0001_11xx
`define def_0010_xxxx `def_0010_00xx, `def_0010_01xx, `def_0010_10xx, `def_0010_11xx
`define def_0011_xxxx `def_0011_00xx, `def_0011_01xx, `def_0011_10xx, `def_0011_11xx
`define def_0100_xxxx `def_0100_00xx, `def_0100_01xx, `def_0100_10xx, `def_0100_11xx
`define def_0101_xxxx `def_0101_00xx, `def_0101_01xx, `def_0101_10xx, `def_0101_11xx
`define def_0110_xxxx `def_0110_00xx, `def_0110_01xx, `def_0110_10xx, `def_0110_11xx
`define def_0111_xxxx `def_0111_00xx, `def_0111_01xx, `def_0111_10xx, `def_0111_11xx
`define def_1000_xxxx `def_1000_00xx, `def_1000_01xx, `def_1000_10xx, `def_1000_11xx
`define def_1001_xxxx `def_1001_00xx, `def_1001_01xx, `def_1001_10xx, `def_1001_11xx
`define def_1010_xxxx `def_1010_00xx, `def_1010_01xx, `def_1010_10xx, `def_1010_11xx
`define def_1011_xxxx `def_1011_00xx, `def_1011_01xx, `def_1011_10xx, `def_1011_11xx
`define def_1100_xxxx `def_1100_00xx, `def_1100_01xx, `def_1100_10xx, `def_1100_11xx
`define def_1101_xxxx `def_1101_00xx, `def_1101_01xx, `def_1101_10xx, `def_1101_11xx
`define def_1110_xxxx `def_1110_00xx, `def_1110_01xx, `def_1110_10xx, `def_1110_11xx
`define def_1111_xxxx `def_1111_00xx, `def_1111_01xx, `def_1111_10xx, `def_1111_11xx
`define def_1xxx_xxxx `def_1000_xxxx, `def_1001_xxxx, `def_1010_xxxx, `def_1011_xxxx, \
`def_1100_xxxx, `def_1101_xxxx, `def_1110_xxxx, `def_1111_xxxx
`define def_01xx_xxxx `def_0100_xxxx, `def_0101_xxxx, `def_0110_xxxx, `def_0111_xxxx
`define def_001x_xxxx `def_0010_xxxx, `def_0011_xxxx
module clz(
input wire [7:0] data_i,
output wire [6:0] out
);
// -----------------------------
// Reg declarations
// -----------------------------
reg [2:0] clz_byte0;
reg [2:0] clz_byte1;
reg [2:0] clz_byte2;
reg [2:0] clz_byte3;
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte0 = 3'b000;
`def_01xx_xxxx : clz_byte0 = 3'b001;
`def_001x_xxxx : clz_byte0 = 3'b010;
`def_0001_xxxx : clz_byte0 = 3'b011;
`def_0000_1xxx : clz_byte0 = 3'b100;
`def_0000_01xx : clz_byte0 = 3'b101;
`def_0000_001x : clz_byte0 = 3'b110;
8'b0000_0001 : clz_byte0 = 3'b111;
8'b0000_0000 : clz_byte0 = 3'b111;
default : clz_byte0 = 3'bxxx;
endcase
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte1 = 3'b000;
`def_01xx_xxxx : clz_byte1 = 3'b001;
`def_001x_xxxx : clz_byte1 = 3'b010;
`def_0001_xxxx : clz_byte1 = 3'b011;
`def_0000_1xxx : clz_byte1 = 3'b100;
`def_0000_01xx : clz_byte1 = 3'b101;
`def_0000_001x : clz_byte1 = 3'b110;
8'b0000_0001 : clz_byte1 = 3'b111;
8'b0000_0000 : clz_byte1 = 3'b111;
default : clz_byte1 = 3'bxxx;
endcase
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte2 = 3'b000;
`def_01xx_xxxx : clz_byte2 = 3'b001;
`def_001x_xxxx : clz_byte2 = 3'b010;
`def_0001_xxxx : clz_byte2 = 3'b011;
`def_0000_1xxx : clz_byte2 = 3'b100;
`def_0000_01xx : clz_byte2 = 3'b101;
`def_0000_001x : clz_byte2 = 3'b110;
8'b0000_0001 : clz_byte2 = 3'b111;
8'b0000_0000 : clz_byte2 = 3'b111;
default : clz_byte2 = 3'bxxx;
endcase
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte3 = 3'b000;
`def_01xx_xxxx : clz_byte3 = 3'b001;
`def_001x_xxxx : clz_byte3 = 3'b010;
`def_0001_xxxx : clz_byte3 = 3'b011;
`def_0000_1xxx : clz_byte3 = 3'b100;
`def_0000_01xx : clz_byte3 = 3'b101;
`def_0000_001x : clz_byte3 = 3'b110;
8'b0000_0001 : clz_byte3 = 3'b111;
8'b0000_0000 : clz_byte3 = 3'b111;
default : clz_byte3 = 3'bxxx;
endcase
assign out = {4'b0000, clz_byte1};
endmodule // clz
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [7:0] operand_a = crc[7:0];
wire [7:0] operand_b = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [6:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[6:0]),
// Inputs
.clk (clk),
.operand_a (operand_a[7:0]),
.operand_b (operand_b[7:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h8a78c2ec4946ac38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
// Inputs
input wire clk,
input wire [7:0] operand_a, // operand a
input wire [7:0] operand_b, // operand b
// Outputs
output wire [6:0] out
);
wire [6:0] clz_a;
wire [6:0] clz_b;
clz u_clz_a
(
// Inputs
.data_i (operand_a),
.out (clz_a));
clz u_clz_b
(
// Inputs
.data_i (operand_b),
.out (clz_b));
assign out = clz_a - clz_b;
`ifdef TEST_VERBOSE
always @(posedge clk)
$display("Out(%x) = clz_a(%x) - clz_b(%x)", out, clz_a, clz_b);
`endif
endmodule
`define def_0000_001x 8'b0000_0010, 8'b0000_0011
`define def_0000_01xx 8'b0000_0100, 8'b0000_0101, 8'b0000_0110, 8'b0000_0111
`define def_0000_10xx 8'b0000_1000, 8'b0000_1001, 8'b0000_1010, 8'b0000_1011
`define def_0000_11xx 8'b0000_1100, 8'b0000_1101, 8'b0000_1110, 8'b0000_1111
`define def_0000_1xxx `def_0000_10xx, `def_0000_11xx
`define def_0001_00xx 8'b0001_0000, 8'b0001_0001, 8'b0001_0010, 8'b0001_0011
`define def_0001_01xx 8'b0001_0100, 8'b0001_0101, 8'b0001_0110, 8'b0001_0111
`define def_0001_10xx 8'b0001_1000, 8'b0001_1001, 8'b0001_1010, 8'b0001_1011
`define def_0001_11xx 8'b0001_1100, 8'b0001_1101, 8'b0001_1110, 8'b0001_1111
`define def_0010_00xx 8'b0010_0000, 8'b0010_0001, 8'b0010_0010, 8'b0010_0011
`define def_0010_01xx 8'b0010_0100, 8'b0010_0101, 8'b0010_0110, 8'b0010_0111
`define def_0010_10xx 8'b0010_1000, 8'b0010_1001, 8'b0010_1010, 8'b0010_1011
`define def_0010_11xx 8'b0010_1100, 8'b0010_1101, 8'b0010_1110, 8'b0010_1111
`define def_0011_00xx 8'b0011_0000, 8'b0011_0001, 8'b0011_0010, 8'b0011_0011
`define def_0011_01xx 8'b0011_0100, 8'b0011_0101, 8'b0011_0110, 8'b0011_0111
`define def_0011_10xx 8'b0011_1000, 8'b0011_1001, 8'b0011_1010, 8'b0011_1011
`define def_0011_11xx 8'b0011_1100, 8'b0011_1101, 8'b0011_1110, 8'b0011_1111
`define def_0100_00xx 8'b0100_0000, 8'b0100_0001, 8'b0100_0010, 8'b0100_0011
`define def_0100_01xx 8'b0100_0100, 8'b0100_0101, 8'b0100_0110, 8'b0100_0111
`define def_0100_10xx 8'b0100_1000, 8'b0100_1001, 8'b0100_1010, 8'b0100_1011
`define def_0100_11xx 8'b0100_1100, 8'b0100_1101, 8'b0100_1110, 8'b0100_1111
`define def_0101_00xx 8'b0101_0000, 8'b0101_0001, 8'b0101_0010, 8'b0101_0011
`define def_0101_01xx 8'b0101_0100, 8'b0101_0101, 8'b0101_0110, 8'b0101_0111
`define def_0101_10xx 8'b0101_1000, 8'b0101_1001, 8'b0101_1010, 8'b0101_1011
`define def_0101_11xx 8'b0101_1100, 8'b0101_1101, 8'b0101_1110, 8'b0101_1111
`define def_0110_00xx 8'b0110_0000, 8'b0110_0001, 8'b0110_0010, 8'b0110_0011
`define def_0110_01xx 8'b0110_0100, 8'b0110_0101, 8'b0110_0110, 8'b0110_0111
`define def_0110_10xx 8'b0110_1000, 8'b0110_1001, 8'b0110_1010, 8'b0110_1011
`define def_0110_11xx 8'b0110_1100, 8'b0110_1101, 8'b0110_1110, 8'b0110_1111
`define def_0111_00xx 8'b0111_0000, 8'b0111_0001, 8'b0111_0010, 8'b0111_0011
`define def_0111_01xx 8'b0111_0100, 8'b0111_0101, 8'b0111_0110, 8'b0111_0111
`define def_0111_10xx 8'b0111_1000, 8'b0111_1001, 8'b0111_1010, 8'b0111_1011
`define def_0111_11xx 8'b0111_1100, 8'b0111_1101, 8'b0111_1110, 8'b0111_1111
`define def_1000_00xx 8'b1000_0000, 8'b1000_0001, 8'b1000_0010, 8'b1000_0011
`define def_1000_01xx 8'b1000_0100, 8'b1000_0101, 8'b1000_0110, 8'b1000_0111
`define def_1000_10xx 8'b1000_1000, 8'b1000_1001, 8'b1000_1010, 8'b1000_1011
`define def_1000_11xx 8'b1000_1100, 8'b1000_1101, 8'b1000_1110, 8'b1000_1111
`define def_1001_00xx 8'b1001_0000, 8'b1001_0001, 8'b1001_0010, 8'b1001_0011
`define def_1001_01xx 8'b1001_0100, 8'b1001_0101, 8'b1001_0110, 8'b1001_0111
`define def_1001_10xx 8'b1001_1000, 8'b1001_1001, 8'b1001_1010, 8'b1001_1011
`define def_1001_11xx 8'b1001_1100, 8'b1001_1101, 8'b1001_1110, 8'b1001_1111
`define def_1010_00xx 8'b1010_0000, 8'b1010_0001, 8'b1010_0010, 8'b1010_0011
`define def_1010_01xx 8'b1010_0100, 8'b1010_0101, 8'b1010_0110, 8'b1010_0111
`define def_1010_10xx 8'b1010_1000, 8'b1010_1001, 8'b1010_1010, 8'b1010_1011
`define def_1010_11xx 8'b1010_1100, 8'b1010_1101, 8'b1010_1110, 8'b1010_1111
`define def_1011_00xx 8'b1011_0000, 8'b1011_0001, 8'b1011_0010, 8'b1011_0011
`define def_1011_01xx 8'b1011_0100, 8'b1011_0101, 8'b1011_0110, 8'b1011_0111
`define def_1011_10xx 8'b1011_1000, 8'b1011_1001, 8'b1011_1010, 8'b1011_1011
`define def_1011_11xx 8'b1011_1100, 8'b1011_1101, 8'b1011_1110, 8'b1011_1111
`define def_1100_00xx 8'b1100_0000, 8'b1100_0001, 8'b1100_0010, 8'b1100_0011
`define def_1100_01xx 8'b1100_0100, 8'b1100_0101, 8'b1100_0110, 8'b1100_0111
`define def_1100_10xx 8'b1100_1000, 8'b1100_1001, 8'b1100_1010, 8'b1100_1011
`define def_1100_11xx 8'b1100_1100, 8'b1100_1101, 8'b1100_1110, 8'b1100_1111
`define def_1101_00xx 8'b1101_0000, 8'b1101_0001, 8'b1101_0010, 8'b1101_0011
`define def_1101_01xx 8'b1101_0100, 8'b1101_0101, 8'b1101_0110, 8'b1101_0111
`define def_1101_10xx 8'b1101_1000, 8'b1101_1001, 8'b1101_1010, 8'b1101_1011
`define def_1101_11xx 8'b1101_1100, 8'b1101_1101, 8'b1101_1110, 8'b1101_1111
`define def_1110_00xx 8'b1110_0000, 8'b1110_0001, 8'b1110_0010, 8'b1110_0011
`define def_1110_01xx 8'b1110_0100, 8'b1110_0101, 8'b1110_0110, 8'b1110_0111
`define def_1110_10xx 8'b1110_1000, 8'b1110_1001, 8'b1110_1010, 8'b1110_1011
`define def_1110_11xx 8'b1110_1100, 8'b1110_1101, 8'b1110_1110, 8'b1110_1111
`define def_1111_00xx 8'b1111_0000, 8'b1111_0001, 8'b1111_0010, 8'b1111_0011
`define def_1111_01xx 8'b1111_0100, 8'b1111_0101, 8'b1111_0110, 8'b1111_0111
`define def_1111_10xx 8'b1111_1000, 8'b1111_1001, 8'b1111_1010, 8'b1111_1011
`define def_1111_11xx 8'b1111_1100, 8'b1111_1101, 8'b1111_1110, 8'b1111_1111
`define def_0001_xxxx `def_0001_00xx, `def_0001_01xx, `def_0001_10xx, `def_0001_11xx
`define def_0010_xxxx `def_0010_00xx, `def_0010_01xx, `def_0010_10xx, `def_0010_11xx
`define def_0011_xxxx `def_0011_00xx, `def_0011_01xx, `def_0011_10xx, `def_0011_11xx
`define def_0100_xxxx `def_0100_00xx, `def_0100_01xx, `def_0100_10xx, `def_0100_11xx
`define def_0101_xxxx `def_0101_00xx, `def_0101_01xx, `def_0101_10xx, `def_0101_11xx
`define def_0110_xxxx `def_0110_00xx, `def_0110_01xx, `def_0110_10xx, `def_0110_11xx
`define def_0111_xxxx `def_0111_00xx, `def_0111_01xx, `def_0111_10xx, `def_0111_11xx
`define def_1000_xxxx `def_1000_00xx, `def_1000_01xx, `def_1000_10xx, `def_1000_11xx
`define def_1001_xxxx `def_1001_00xx, `def_1001_01xx, `def_1001_10xx, `def_1001_11xx
`define def_1010_xxxx `def_1010_00xx, `def_1010_01xx, `def_1010_10xx, `def_1010_11xx
`define def_1011_xxxx `def_1011_00xx, `def_1011_01xx, `def_1011_10xx, `def_1011_11xx
`define def_1100_xxxx `def_1100_00xx, `def_1100_01xx, `def_1100_10xx, `def_1100_11xx
`define def_1101_xxxx `def_1101_00xx, `def_1101_01xx, `def_1101_10xx, `def_1101_11xx
`define def_1110_xxxx `def_1110_00xx, `def_1110_01xx, `def_1110_10xx, `def_1110_11xx
`define def_1111_xxxx `def_1111_00xx, `def_1111_01xx, `def_1111_10xx, `def_1111_11xx
`define def_1xxx_xxxx `def_1000_xxxx, `def_1001_xxxx, `def_1010_xxxx, `def_1011_xxxx, \
`def_1100_xxxx, `def_1101_xxxx, `def_1110_xxxx, `def_1111_xxxx
`define def_01xx_xxxx `def_0100_xxxx, `def_0101_xxxx, `def_0110_xxxx, `def_0111_xxxx
`define def_001x_xxxx `def_0010_xxxx, `def_0011_xxxx
module clz(
input wire [7:0] data_i,
output wire [6:0] out
);
// -----------------------------
// Reg declarations
// -----------------------------
reg [2:0] clz_byte0;
reg [2:0] clz_byte1;
reg [2:0] clz_byte2;
reg [2:0] clz_byte3;
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte0 = 3'b000;
`def_01xx_xxxx : clz_byte0 = 3'b001;
`def_001x_xxxx : clz_byte0 = 3'b010;
`def_0001_xxxx : clz_byte0 = 3'b011;
`def_0000_1xxx : clz_byte0 = 3'b100;
`def_0000_01xx : clz_byte0 = 3'b101;
`def_0000_001x : clz_byte0 = 3'b110;
8'b0000_0001 : clz_byte0 = 3'b111;
8'b0000_0000 : clz_byte0 = 3'b111;
default : clz_byte0 = 3'bxxx;
endcase
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte1 = 3'b000;
`def_01xx_xxxx : clz_byte1 = 3'b001;
`def_001x_xxxx : clz_byte1 = 3'b010;
`def_0001_xxxx : clz_byte1 = 3'b011;
`def_0000_1xxx : clz_byte1 = 3'b100;
`def_0000_01xx : clz_byte1 = 3'b101;
`def_0000_001x : clz_byte1 = 3'b110;
8'b0000_0001 : clz_byte1 = 3'b111;
8'b0000_0000 : clz_byte1 = 3'b111;
default : clz_byte1 = 3'bxxx;
endcase
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte2 = 3'b000;
`def_01xx_xxxx : clz_byte2 = 3'b001;
`def_001x_xxxx : clz_byte2 = 3'b010;
`def_0001_xxxx : clz_byte2 = 3'b011;
`def_0000_1xxx : clz_byte2 = 3'b100;
`def_0000_01xx : clz_byte2 = 3'b101;
`def_0000_001x : clz_byte2 = 3'b110;
8'b0000_0001 : clz_byte2 = 3'b111;
8'b0000_0000 : clz_byte2 = 3'b111;
default : clz_byte2 = 3'bxxx;
endcase
always @*
case (data_i)
`def_1xxx_xxxx : clz_byte3 = 3'b000;
`def_01xx_xxxx : clz_byte3 = 3'b001;
`def_001x_xxxx : clz_byte3 = 3'b010;
`def_0001_xxxx : clz_byte3 = 3'b011;
`def_0000_1xxx : clz_byte3 = 3'b100;
`def_0000_01xx : clz_byte3 = 3'b101;
`def_0000_001x : clz_byte3 = 3'b110;
8'b0000_0001 : clz_byte3 = 3'b111;
8'b0000_0000 : clz_byte3 = 3'b111;
default : clz_byte3 = 3'bxxx;
endcase
assign out = {4'b0000, clz_byte1};
endmodule // clz
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_buffer_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Wraps a FIFO for saving channel data and provides a
// registered read output. Retains unread words from reads that are a length
// which is not a multiple of the data bus width (C_FIFO_DATA_WIDTH). Data is
// available 5 cycles after RD_EN is asserted (not 1, like a traditional FIFO).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_buffer_128 #(
parameter C_FIFO_DATA_WIDTH = 9'd128,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_RD_EN_HIST = 2,
parameter C_FIFO_RD_EN_HIST = 2,
parameter C_CONSUME_HIST = 3,
parameter C_COUNT_HIST = 3,
parameter C_LEN_LAST_HIST = 1
)
(
input RST,
input CLK,
input LEN_VALID, // Transfer length is valid
input [1:0] LEN_LSB, // LSBs of transfer length
input LEN_LAST, // Last transfer in transaction
input [C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
input WR_EN, // Input data write enable
output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Input data write count
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // Output data
input RD_EN // Output data read enable
);
`include "functions.vh"
reg [1:0] rRdPtr=0, _rRdPtr=0;
reg [1:0] rWrPtr=0, _rWrPtr=0;
reg [3:0] rLenLSB0=0, _rLenLSB0=0;
reg [3:0] rLenLSB1=0, _rLenLSB1=0;
reg [3:0] rLenLast=0, _rLenLast=0;
reg rLenValid=0, _rLenValid=0;
reg rRen=0, _rRen=0;
reg [2:0] rCount=0, _rCount=0;
reg [(C_COUNT_HIST*3)-1:0] rCountHist={C_COUNT_HIST{3'd0}}, _rCountHist={C_COUNT_HIST{3'd0}};
reg [C_LEN_LAST_HIST-1:0] rLenLastHist={C_LEN_LAST_HIST{1'd0}}, _rLenLastHist={C_LEN_LAST_HIST{1'd0}};
reg [C_RD_EN_HIST-1:0] rRdEnHist={C_RD_EN_HIST{1'd0}}, _rRdEnHist={C_RD_EN_HIST{1'd0}};
reg rFifoRdEn=0, _rFifoRdEn=0;
reg [C_FIFO_RD_EN_HIST-1:0] rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}}, _rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}};
reg [(C_CONSUME_HIST*3)-1:0] rConsumedHist={C_CONSUME_HIST{3'd0}}, _rConsumedHist={C_CONSUME_HIST{3'd0}};
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
reg [223:0] rData=224'd0, _rData=224'd0;
wire [C_FIFO_DATA_WIDTH-1:0] wFifoData;
assign RD_DATA = rData[0 +:C_FIFO_DATA_WIDTH];
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rLenValid <= #1 (RST ? 1'd0 : _rLenValid);
rRen <= #1 (RST ? 1'd0 : _rRen);
end
always @ (*) begin
_rLenValid = LEN_VALID;
_rRen = RD_EN;
end
// FIFO for storing data from the channel.
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
.CLK(CLK),
.RST(RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.FULL(),
.COUNT(WR_COUNT),
.RD_EN(rFifoRdEn),
.RD_DATA(wFifoData),
.EMPTY()
);
// Manage shifting of data in from the FIFO and shifting of data out once
// it is consumed. We'll keep 7 words of output registers to hold an input
// packet with up to 3 extra words of unread data.
wire [1:0] wLenLSB = {rLenLSB1[rRdPtr], rLenLSB0[rRdPtr]};
wire wLenLast = rLenLast[rRdPtr];
wire wAfterEnd = (!rRen & rRdEnHist[0]);
// consumed = 4 if RD+2
// consumed = remainder if EOP on RD+1 (~rRen & rRdEnHist[0])
// consumed = 4 if EOP on RD+3 and LAST on RD+3
wire [2:0] wConsumed = ({(rRdEnHist[0] | (!rRdEnHist[0] & rRdEnHist[1] & rLenLastHist[0])),2'd0}) - ({2{wAfterEnd}} & wLenLSB);
always @ (posedge CLK) begin
rCount <= #1 (RST ? 2'd0 : _rCount);
rCountHist <= #1 _rCountHist;
rRdEnHist <= #1 (RST ? {C_RD_EN_HIST{1'd0}} : _rRdEnHist);
rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
rFifoRdEnHist <= #1 (RST ? {C_FIFO_RD_EN_HIST{1'd0}} : _rFifoRdEnHist);
rConsumedHist <= #1 _rConsumedHist;
rLenLastHist <= #1 (RST ? {C_LEN_LAST_HIST{1'd0}} : _rLenLastHist);
rFifoData <= #1 _rFifoData;
rData <= #1 _rData;
end
always @ (*) begin
// Keep track of words in our buffer. Subtract 4 when we reach 4 on RD_EN.
// Add wLenLSB when we finish a sequence of RD_EN that read 1, 2, or 3 words.
// rCount + remainder
_rCount = rCount + ({2{(wAfterEnd & !wLenLast)}} & wLenLSB) - ({(rRen & rCount[2]), 2'd0}) - ({3{(wAfterEnd & wLenLast)}} & rCount);
_rCountHist = ((rCountHist<<3) | rCount);
// Track read enables in the pipeline.
_rRdEnHist = ((rRdEnHist<<1) | rRen);
_rFifoRdEnHist = ((rFifoRdEnHist<<1) | rFifoRdEn);
// Track delayed length last value
_rLenLastHist = ((rLenLastHist<<1) | wLenLast);
// Calculate the amount to shift out each RD_EN. This is always 4 unless it's
// the last RD_EN in the sequence and the read words length is 1, 2, or 3.
_rConsumedHist = ((rConsumedHist<<3) | wConsumed);
// Read from the FIFO unless we have 4 words cached.
_rFifoRdEn = (!rCount[2] & rRen);
// Buffer the FIFO data.
_rFifoData = wFifoData;
// Shift the buffered FIFO data into and the consumed data out of the output register.
if (rFifoRdEnHist[1])
_rData = ((rData>>({rConsumedHist[8:6], 5'd0})) | (rFifoData<<({rCountHist[7:6], 5'd0})));
else
_rData = (rData>>({rConsumedHist[8:6], 5'd0}));
end
// Buffer up to 4 length LSB values for use to detect unread data that was
// part of a consumed packet. Should only need 2. This is basically a FIFO.
always @ (posedge CLK) begin
rRdPtr <= #1 (RST ? 2'd0 : _rRdPtr);
rWrPtr <= #1 (RST ? 2'd0 : _rWrPtr);
rLenLSB0 <= #1 _rLenLSB0;
rLenLSB1 <= #1 _rLenLSB1;
rLenLast <= #1 _rLenLast;
end
always @ (*) begin
_rRdPtr = (wAfterEnd ? rRdPtr + 1'd1 : rRdPtr);
_rWrPtr = (rLenValid ? rWrPtr + 1'd1 : rWrPtr);
_rLenLSB0 = rLenLSB0;
_rLenLSB1 = rLenLSB1;
if(rLenValid)
{_rLenLSB1[rWrPtr], _rLenLSB0[rWrPtr]} = (~LEN_LSB + 1);
_rLenLast = rLenLast;
if(rLenValid)
_rLenLast[rWrPtr] = LEN_LAST;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_buffer_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Wraps a FIFO for saving channel data and provides a
// registered read output. Retains unread words from reads that are a length
// which is not a multiple of the data bus width (C_FIFO_DATA_WIDTH). Data is
// available 5 cycles after RD_EN is asserted (not 1, like a traditional FIFO).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_buffer_128 #(
parameter C_FIFO_DATA_WIDTH = 9'd128,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_RD_EN_HIST = 2,
parameter C_FIFO_RD_EN_HIST = 2,
parameter C_CONSUME_HIST = 3,
parameter C_COUNT_HIST = 3,
parameter C_LEN_LAST_HIST = 1
)
(
input RST,
input CLK,
input LEN_VALID, // Transfer length is valid
input [1:0] LEN_LSB, // LSBs of transfer length
input LEN_LAST, // Last transfer in transaction
input [C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
input WR_EN, // Input data write enable
output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Input data write count
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // Output data
input RD_EN // Output data read enable
);
`include "functions.vh"
reg [1:0] rRdPtr=0, _rRdPtr=0;
reg [1:0] rWrPtr=0, _rWrPtr=0;
reg [3:0] rLenLSB0=0, _rLenLSB0=0;
reg [3:0] rLenLSB1=0, _rLenLSB1=0;
reg [3:0] rLenLast=0, _rLenLast=0;
reg rLenValid=0, _rLenValid=0;
reg rRen=0, _rRen=0;
reg [2:0] rCount=0, _rCount=0;
reg [(C_COUNT_HIST*3)-1:0] rCountHist={C_COUNT_HIST{3'd0}}, _rCountHist={C_COUNT_HIST{3'd0}};
reg [C_LEN_LAST_HIST-1:0] rLenLastHist={C_LEN_LAST_HIST{1'd0}}, _rLenLastHist={C_LEN_LAST_HIST{1'd0}};
reg [C_RD_EN_HIST-1:0] rRdEnHist={C_RD_EN_HIST{1'd0}}, _rRdEnHist={C_RD_EN_HIST{1'd0}};
reg rFifoRdEn=0, _rFifoRdEn=0;
reg [C_FIFO_RD_EN_HIST-1:0] rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}}, _rFifoRdEnHist={C_FIFO_RD_EN_HIST{1'd0}};
reg [(C_CONSUME_HIST*3)-1:0] rConsumedHist={C_CONSUME_HIST{3'd0}}, _rConsumedHist={C_CONSUME_HIST{3'd0}};
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
reg [223:0] rData=224'd0, _rData=224'd0;
wire [C_FIFO_DATA_WIDTH-1:0] wFifoData;
assign RD_DATA = rData[0 +:C_FIFO_DATA_WIDTH];
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rLenValid <= #1 (RST ? 1'd0 : _rLenValid);
rRen <= #1 (RST ? 1'd0 : _rRen);
end
always @ (*) begin
_rLenValid = LEN_VALID;
_rRen = RD_EN;
end
// FIFO for storing data from the channel.
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
.CLK(CLK),
.RST(RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.FULL(),
.COUNT(WR_COUNT),
.RD_EN(rFifoRdEn),
.RD_DATA(wFifoData),
.EMPTY()
);
// Manage shifting of data in from the FIFO and shifting of data out once
// it is consumed. We'll keep 7 words of output registers to hold an input
// packet with up to 3 extra words of unread data.
wire [1:0] wLenLSB = {rLenLSB1[rRdPtr], rLenLSB0[rRdPtr]};
wire wLenLast = rLenLast[rRdPtr];
wire wAfterEnd = (!rRen & rRdEnHist[0]);
// consumed = 4 if RD+2
// consumed = remainder if EOP on RD+1 (~rRen & rRdEnHist[0])
// consumed = 4 if EOP on RD+3 and LAST on RD+3
wire [2:0] wConsumed = ({(rRdEnHist[0] | (!rRdEnHist[0] & rRdEnHist[1] & rLenLastHist[0])),2'd0}) - ({2{wAfterEnd}} & wLenLSB);
always @ (posedge CLK) begin
rCount <= #1 (RST ? 2'd0 : _rCount);
rCountHist <= #1 _rCountHist;
rRdEnHist <= #1 (RST ? {C_RD_EN_HIST{1'd0}} : _rRdEnHist);
rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
rFifoRdEnHist <= #1 (RST ? {C_FIFO_RD_EN_HIST{1'd0}} : _rFifoRdEnHist);
rConsumedHist <= #1 _rConsumedHist;
rLenLastHist <= #1 (RST ? {C_LEN_LAST_HIST{1'd0}} : _rLenLastHist);
rFifoData <= #1 _rFifoData;
rData <= #1 _rData;
end
always @ (*) begin
// Keep track of words in our buffer. Subtract 4 when we reach 4 on RD_EN.
// Add wLenLSB when we finish a sequence of RD_EN that read 1, 2, or 3 words.
// rCount + remainder
_rCount = rCount + ({2{(wAfterEnd & !wLenLast)}} & wLenLSB) - ({(rRen & rCount[2]), 2'd0}) - ({3{(wAfterEnd & wLenLast)}} & rCount);
_rCountHist = ((rCountHist<<3) | rCount);
// Track read enables in the pipeline.
_rRdEnHist = ((rRdEnHist<<1) | rRen);
_rFifoRdEnHist = ((rFifoRdEnHist<<1) | rFifoRdEn);
// Track delayed length last value
_rLenLastHist = ((rLenLastHist<<1) | wLenLast);
// Calculate the amount to shift out each RD_EN. This is always 4 unless it's
// the last RD_EN in the sequence and the read words length is 1, 2, or 3.
_rConsumedHist = ((rConsumedHist<<3) | wConsumed);
// Read from the FIFO unless we have 4 words cached.
_rFifoRdEn = (!rCount[2] & rRen);
// Buffer the FIFO data.
_rFifoData = wFifoData;
// Shift the buffered FIFO data into and the consumed data out of the output register.
if (rFifoRdEnHist[1])
_rData = ((rData>>({rConsumedHist[8:6], 5'd0})) | (rFifoData<<({rCountHist[7:6], 5'd0})));
else
_rData = (rData>>({rConsumedHist[8:6], 5'd0}));
end
// Buffer up to 4 length LSB values for use to detect unread data that was
// part of a consumed packet. Should only need 2. This is basically a FIFO.
always @ (posedge CLK) begin
rRdPtr <= #1 (RST ? 2'd0 : _rRdPtr);
rWrPtr <= #1 (RST ? 2'd0 : _rWrPtr);
rLenLSB0 <= #1 _rLenLSB0;
rLenLSB1 <= #1 _rLenLSB1;
rLenLast <= #1 _rLenLast;
end
always @ (*) begin
_rRdPtr = (wAfterEnd ? rRdPtr + 1'd1 : rRdPtr);
_rWrPtr = (rLenValid ? rWrPtr + 1'd1 : rWrPtr);
_rLenLSB0 = rLenLSB0;
_rLenLSB1 = rLenLSB1;
if(rLenValid)
{_rLenLSB1[rWrPtr], _rLenLSB0[rWrPtr]} = (~LEN_LSB + 1);
_rLenLast = rLenLast;
if(rLenValid)
_rLenLast[rWrPtr] = LEN_LAST;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/18/2016 03:28:31 PM
// Design Name:
// Module Name: Round_Sgf_Dec
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dep encies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Round_Sgf_Dec(
input wire [1:0] Data_i,
input wire [1:0] Round_Type_i,
input wire Sign_Result_i,
output reg Round_Flag_o
);
always @*
case ({Sign_Result_i,Round_Type_i,Data_i})
//Round type=00; Towards zero / No round
//Round type=01; Towards - infinity
//Round type=10; Towards + infinity
//Op=0;Round type=00
/*5'b00000: Round_Flag_o <=0;
5'b00001: Round_Flag_o <=0;
5'b00010: Round_Flag_o <=0;
5'b00011: Round_Flag_o <=0;*/
//Op=1;Round type=00
/*5'b10000: Round_Flag_o <=0;
5'b10001: Round_Flag_o <=0;
5'b10010: Round_Flag_o <=0;
5'b10011: Round_Flag_o <=0; */
//Op=0;Round type=01
/*5'b00100: Round_Flag_o <=0;
5'b00101: Round_Flag_o <=0;
5'b00110: Round_Flag_o <=0;
5'b00111: Round_Flag_o <=0; */
//Op=1;Round type=01
//5'b10100: Round_Flag_o <=0;
5'b10101: Round_Flag_o <=1;
5'b10110: Round_Flag_o <=1;
5'b10111: Round_Flag_o <=1;
//Op=0;Round type=10
//5'b01000: Round_Flag_o <=0;
5'b01001: Round_Flag_o <=1;
5'b01010: Round_Flag_o <=1;
5'b01011: Round_Flag_o <=1;
//Op=1;Round type=10
/*5'b11000: Round_Flag_o <=0;
5'b11001: Round_Flag_o <=0;
5'b11010: Round_Flag_o <=0;
5'b11011: Round_Flag_o <=0; */
default: Round_Flag_o <=0;
endcase
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:
// \ \ Application: MIG
// / / Filename: ddr_phy_dqs_found_cal.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:08 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Read leveling calibration logic
// NOTES:
// 1. Phaser_In DQSFOUND calibration
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_dqs_found_cal.v,v 1.1 2011/06/02 08:35:08 mishra Exp $
**$Date: 2011/06/02 08:35:08 $
**$Author:
**$Revision:
**$Source:
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_phy_dqs_found_cal_hr #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter nCL = 5, // Read CAS latency
parameter AL = "0",
parameter nCWL = 5, // Write CAS latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RANKS = 1, // # of memory ranks in the system
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter NUM_DQSFOUND_CAL = 3, // Number of times to iterate
parameter N_CTL_LANES = 3, // Number of control byte lanes
parameter HIGHEST_LANE = 12, // Sum of byte lanes (Data + Ctrl)
parameter HIGHEST_BANK = 3, // Sum of I/O Banks
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf
)
(
input clk,
input rst,
input dqsfound_retry,
// From phy_init
input pi_dqs_found_start,
input detect_pi_found_dqs,
input prech_done,
// DQSFOUND per Phaser_IN
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
// To phy_init
output [5:0] rd_data_offset_0,
output [5:0] rd_data_offset_1,
output [5:0] rd_data_offset_2,
output pi_dqs_found_rank_done,
output pi_dqs_found_done,
output reg pi_dqs_found_err,
output [6*RANKS-1:0] rd_data_offset_ranks_0,
output [6*RANKS-1:0] rd_data_offset_ranks_1,
output [6*RANKS-1:0] rd_data_offset_ranks_2,
output reg dqsfound_retry_done,
output reg dqs_found_prech_req,
//To MC
output [6*RANKS-1:0] rd_data_offset_ranks_mc_0,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_1,
output [6*RANKS-1:0] rd_data_offset_ranks_mc_2,
input [8:0] po_counter_read_val,
output rd_data_offset_cal_done,
output fine_adjust_done,
output [N_CTL_LANES-1:0] fine_adjust_lane_cnt,
output reg ck_po_stg2_f_indec,
output reg ck_po_stg2_f_en,
output [255:0] dbg_dqs_found_cal
);
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Added to reduce simulation time
localparam LATENCY_FACTOR = 13;
localparam NUM_READS = (SIM_CAL_OPTION == "NONE") ? 7 : 1;
localparam [19:0] DATA_PRESENT = {(DATA_CTL_B4[3] & BYTE_LANES_B4[3]),
(DATA_CTL_B4[2] & BYTE_LANES_B4[2]),
(DATA_CTL_B4[1] & BYTE_LANES_B4[1]),
(DATA_CTL_B4[0] & BYTE_LANES_B4[0]),
(DATA_CTL_B3[3] & BYTE_LANES_B3[3]),
(DATA_CTL_B3[2] & BYTE_LANES_B3[2]),
(DATA_CTL_B3[1] & BYTE_LANES_B3[1]),
(DATA_CTL_B3[0] & BYTE_LANES_B3[0]),
(DATA_CTL_B2[3] & BYTE_LANES_B2[3]),
(DATA_CTL_B2[2] & BYTE_LANES_B2[2]),
(DATA_CTL_B2[1] & BYTE_LANES_B2[1]),
(DATA_CTL_B2[0] & BYTE_LANES_B2[0]),
(DATA_CTL_B1[3] & BYTE_LANES_B1[3]),
(DATA_CTL_B1[2] & BYTE_LANES_B1[2]),
(DATA_CTL_B1[1] & BYTE_LANES_B1[1]),
(DATA_CTL_B1[0] & BYTE_LANES_B1[0]),
(DATA_CTL_B0[3] & BYTE_LANES_B0[3]),
(DATA_CTL_B0[2] & BYTE_LANES_B0[2]),
(DATA_CTL_B0[1] & BYTE_LANES_B0[1]),
(DATA_CTL_B0[0] & BYTE_LANES_B0[0])};
localparam FINE_ADJ_IDLE = 4'h0;
localparam RST_POSTWAIT = 4'h1;
localparam RST_POSTWAIT1 = 4'h2;
localparam RST_WAIT = 4'h3;
localparam FINE_ADJ_INIT = 4'h4;
localparam FINE_INC = 4'h5;
localparam FINE_INC_WAIT = 4'h6;
localparam FINE_INC_PREWAIT = 4'h7;
localparam DETECT_PREWAIT = 4'h8;
localparam DETECT_DQSFOUND = 4'h9;
localparam PRECH_WAIT = 4'hA;
localparam FINE_DEC = 4'hB;
localparam FINE_DEC_WAIT = 4'hC;
localparam FINE_DEC_PREWAIT = 4'hD;
localparam FINAL_WAIT = 4'hE;
localparam FINE_ADJ_DONE = 4'hF;
integer k,l,m,n,p,q,r,s;
reg dqs_found_start_r;
reg [6*HIGHEST_BANK-1:0] rd_byte_data_offset[0:RANKS-1];
reg rank_done_r;
reg rank_done_r1;
reg dqs_found_done_r;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r1;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r2;
(* ASYNC_REG = "TRUE" *) reg [HIGHEST_LANE-1:0] pi_dqs_found_lanes_r3;
reg init_dqsfound_done_r;
reg init_dqsfound_done_r1;
reg init_dqsfound_done_r2;
reg init_dqsfound_done_r3;
reg init_dqsfound_done_r4;
reg init_dqsfound_done_r5;
reg [1:0] rnk_cnt_r;
reg [2:0 ] final_do_index[0:RANKS-1];
reg [5:0 ] final_do_max[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset[0:RANKS-1];
reg [6*HIGHEST_BANK-1:0] final_data_offset_mc[0:RANKS-1];
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r;
reg [HIGHEST_BANK-1:0] pi_rst_stg1_cal_r1;
reg [10*HIGHEST_BANK-1:0] retry_cnt;
reg dqsfound_retry_r1;
wire [4*HIGHEST_BANK-1:0] pi_dqs_found_lanes_int;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_all_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank;
reg [HIGHEST_BANK-1:0] pi_dqs_found_any_bank_r;
reg [HIGHEST_BANK-1:0] pi_dqs_found_err_r;
// CK/Control byte lanes fine adjust stage
reg fine_adjust;
reg [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [3:0] fine_adj_state_r;
reg fine_adjust_done_r;
reg rst_dqs_find;
reg rst_dqs_find_r1;
reg rst_dqs_find_r2;
reg [5:0] init_dec_cnt;
reg [5:0] dec_cnt;
reg [5:0] inc_cnt;
reg final_dec_done;
reg init_dec_done;
reg first_fail_detect;
reg second_fail_detect;
reg [5:0] first_fail_taps;
reg [5:0] second_fail_taps;
reg [5:0] stable_pass_cnt;
reg [3:0] detect_rd_cnt;
//***************************************************************************
// Debug signals
//
//***************************************************************************
assign dbg_dqs_found_cal[5:0] = first_fail_taps;
assign dbg_dqs_found_cal[11:6] = second_fail_taps;
assign dbg_dqs_found_cal[12] = first_fail_detect;
assign dbg_dqs_found_cal[13] = second_fail_detect;
assign dbg_dqs_found_cal[14] = fine_adjust_done_r;
assign pi_dqs_found_rank_done = rank_done_r;
assign pi_dqs_found_done = dqs_found_done_r;
generate
genvar rnk_cnt;
if (HIGHEST_BANK == 3) begin // Three Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][17:12];
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][17:12];
end
end else if (HIGHEST_BANK == 2) begin // Two Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][11:6];
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][11:6];
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end else begin // Single Bank Interface
for (rnk_cnt = 0; rnk_cnt < RANKS; rnk_cnt = rnk_cnt + 1) begin: rnk_loop
assign rd_data_offset_ranks_0[6*rnk_cnt+:6] = final_data_offset[rnk_cnt][5:0];
assign rd_data_offset_ranks_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_2[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_0[6*rnk_cnt+:6] = final_data_offset_mc[rnk_cnt][5:0];
assign rd_data_offset_ranks_mc_1[6*rnk_cnt+:6] = 'd0;
assign rd_data_offset_ranks_mc_2[6*rnk_cnt+:6] = 'd0;
end
end
endgenerate
// final_data_offset is used during write calibration and during
// normal operation. One rd_data_offset value per rank for entire
// interface
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][12+:6] :
final_data_offset[rnk_cnt_r][12+:6];
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][6+:6] :
final_data_offset[rnk_cnt_r][6+:6];
assign rd_data_offset_2 = 'd0;
end else begin
assign rd_data_offset_0 = (~init_dqsfound_done_r2) ? rd_byte_data_offset[rnk_cnt_r][0+:6] :
final_data_offset[rnk_cnt_r][0+:6];
assign rd_data_offset_1 = 'd0;
assign rd_data_offset_2 = 'd0;
end
endgenerate
assign rd_data_offset_cal_done = init_dqsfound_done_r;
assign fine_adjust_lane_cnt = ctl_lane_cnt;
//**************************************************************************
// DQSFOUND all and any generation
// pi_dqs_found_all_bank[x] asserted when all Phaser_INs in Bankx are
// asserted
// pi_dqs_found_any_bank[x] asserted when at least one Phaser_IN in Bankx
// is asserted
//**************************************************************************
generate
if ((HIGHEST_LANE == 4) || (HIGHEST_LANE == 8) || (HIGHEST_LANE == 12))
assign pi_dqs_found_lanes_int = pi_dqs_found_lanes_r3;
else if ((HIGHEST_LANE == 7) || (HIGHEST_LANE == 11))
assign pi_dqs_found_lanes_int = {1'b0, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 6) || (HIGHEST_LANE == 10))
assign pi_dqs_found_lanes_int = {2'b00, pi_dqs_found_lanes_r3};
else if ((HIGHEST_LANE == 5) || (HIGHEST_LANE == 9))
assign pi_dqs_found_lanes_int = {3'b000, pi_dqs_found_lanes_r3};
endgenerate
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < HIGHEST_BANK; k = k + 1) begin: rst_pi_dqs_found
pi_dqs_found_all_bank[k] <= #TCQ 'b0;
pi_dqs_found_any_bank[k] <= #TCQ 'b0;
end
end else if (pi_dqs_found_start) begin
for (p = 0; p < HIGHEST_BANK; p = p +1) begin: assign_pi_dqs_found
pi_dqs_found_all_bank[p] <= #TCQ (!DATA_PRESENT[4*p+0] | pi_dqs_found_lanes_int[4*p+0]) &
(!DATA_PRESENT[4*p+1] | pi_dqs_found_lanes_int[4*p+1]) &
(!DATA_PRESENT[4*p+2] | pi_dqs_found_lanes_int[4*p+2]) &
(!DATA_PRESENT[4*p+3] | pi_dqs_found_lanes_int[4*p+3]);
pi_dqs_found_any_bank[p] <= #TCQ (DATA_PRESENT[4*p+0] & pi_dqs_found_lanes_int[4*p+0]) |
(DATA_PRESENT[4*p+1] & pi_dqs_found_lanes_int[4*p+1]) |
(DATA_PRESENT[4*p+2] & pi_dqs_found_lanes_int[4*p+2]) |
(DATA_PRESENT[4*p+3] & pi_dqs_found_lanes_int[4*p+3]);
end
end
end
always @(posedge clk) begin
pi_dqs_found_all_bank_r <= #TCQ pi_dqs_found_all_bank;
pi_dqs_found_any_bank_r <= #TCQ pi_dqs_found_any_bank;
end
//*****************************************************************************
// Counter to increase number of 4 back-to-back reads per rd_data_offset and
// per CK/A/C tap value
//*****************************************************************************
always @(posedge clk) begin
if (rst || (detect_rd_cnt == 'd0))
detect_rd_cnt <= #TCQ NUM_READS;
else if (detect_pi_found_dqs && (detect_rd_cnt > 'd0))
detect_rd_cnt <= #TCQ detect_rd_cnt - 1;
end
//**************************************************************************
// Adjust Phaser_Out stage 2 taps on CK/Address/Command/Controls
//
//**************************************************************************
assign fine_adjust_done = fine_adjust_done_r;
always @(posedge clk) begin
rst_dqs_find_r1 <= #TCQ rst_dqs_find;
rst_dqs_find_r2 <= #TCQ rst_dqs_find_r1;
end
always @(posedge clk) begin
if(rst)begin
fine_adjust <= #TCQ 1'b0;
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ FINE_ADJ_IDLE;
fine_adjust_done_r <= #TCQ 1'b0;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b0;
init_dec_cnt <= #TCQ 'd31;
dec_cnt <= #TCQ 'd0;
inc_cnt <= #TCQ 'd0;
init_dec_done <= #TCQ 1'b0;
final_dec_done <= #TCQ 1'b0;
first_fail_detect <= #TCQ 1'b0;
second_fail_detect <= #TCQ 1'b0;
first_fail_taps <= #TCQ 'd0;
second_fail_taps <= #TCQ 'd0;
stable_pass_cnt <= #TCQ 'd0;
dqs_found_prech_req<= #TCQ 1'b0;
end else begin
case (fine_adj_state_r)
FINE_ADJ_IDLE: begin
if (init_dqsfound_done_r5) begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
rst_dqs_find <= #TCQ 1'b0;
end else begin
fine_adjust <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
rst_dqs_find <= #TCQ 1'b1;
end
end
end
RST_WAIT: begin
if (~(|pi_dqs_found_any_bank) && rst_dqs_find_r2) begin
rst_dqs_find <= #TCQ 1'b0;
if (|init_dec_cnt)
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else if (final_dec_done)
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
else
fine_adj_state_r <= #TCQ RST_POSTWAIT;
end
end
RST_POSTWAIT: begin
fine_adj_state_r <= #TCQ RST_POSTWAIT1;
end
RST_POSTWAIT1: begin
fine_adj_state_r <= #TCQ FINE_ADJ_INIT;
end
FINE_ADJ_INIT: begin
//if (detect_pi_found_dqs && (inc_cnt < 'd63))
fine_adj_state_r <= #TCQ FINE_INC;
end
FINE_INC: begin
fine_adj_state_r <= #TCQ FINE_INC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b1;
ck_po_stg2_f_en <= #TCQ 1'b1;
if (ctl_lane_cnt == N_CTL_LANES-1)
inc_cnt <= #TCQ inc_cnt + 1;
end
FINE_INC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_INC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
end
FINE_INC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_INC;
end
DETECT_PREWAIT: begin
if (detect_pi_found_dqs && (detect_rd_cnt == 'd1))
fine_adj_state_r <= #TCQ DETECT_DQSFOUND;
else
fine_adj_state_r <= #TCQ DETECT_PREWAIT;
end
DETECT_DQSFOUND: begin
if (detect_pi_found_dqs && ~(&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ 'd0;
if (~first_fail_detect && (inc_cnt == 'd63)) begin
// First failing tap detected at 63 taps
// then decrement to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else if (~first_fail_detect && (inc_cnt > 'd30) && (stable_pass_cnt > 'd29)) begin
// First failing tap detected at greater than 30 taps
// then stop looking for second edge and decrement
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ (inc_cnt>>1) + 1;
end else if (~first_fail_detect || (first_fail_detect && (stable_pass_cnt < 'd30) && (inc_cnt <= 'd32))) begin
// First failing tap detected, continue incrementing
// until either second failing tap detected or 63
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt > 'd32) && (inc_cnt < 'd63) && (stable_pass_cnt < 'd30)) begin
// Consecutive 30 taps of passing region was not found
// continue incrementing
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
rst_dqs_find <= #TCQ 1'b1;
if ((inc_cnt == 'd36) || (inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else
fine_adj_state_r <= #TCQ RST_WAIT;
end else if (first_fail_detect && (inc_cnt == 'd63)) begin
if (stable_pass_cnt < 'd30) begin
// Consecutive 30 taps of passing region was not found
// from tap 0 to 63 so decrement back to 31
first_fail_detect <= #TCQ 1'b1;
first_fail_taps <= #TCQ inc_cnt;
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ 'd32;
end else begin
// Consecutive 30 taps of passing region was found
// between first_fail_taps and 63
fine_adj_state_r <= #TCQ FINE_DEC;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end else begin
// Second failing tap detected, decrement to center of
// failing taps
second_fail_detect <= #TCQ 1'b1;
second_fail_taps <= #TCQ inc_cnt;
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
fine_adj_state_r <= #TCQ FINE_DEC;
end
end else if (detect_pi_found_dqs && (&pi_dqs_found_all_bank)) begin
stable_pass_cnt <= #TCQ stable_pass_cnt + 1;
if ((inc_cnt == 'd12) || (inc_cnt == 'd24) || (inc_cnt == 'd36) ||
(inc_cnt == 'd48) || (inc_cnt == 'd60)) begin
dqs_found_prech_req <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ PRECH_WAIT;
end else if (inc_cnt < 'd63) begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end else begin
fine_adj_state_r <= #TCQ FINE_DEC;
if (~first_fail_detect || (first_fail_taps > 'd33))
// No failing taps detected, decrement by 31
dec_cnt <= #TCQ 'd32;
//else if (first_fail_detect && (stable_pass_cnt > 'd28))
// // First failing tap detected between 0 and 34
// // decrement midpoint between 63 and failing tap
// dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
else
// First failing tap detected
// decrement to midpoint between 63 and failing tap
dec_cnt <= #TCQ ((inc_cnt - first_fail_taps)>>1);
end
end
end
PRECH_WAIT: begin
if (prech_done) begin
dqs_found_prech_req <= #TCQ 1'b0;
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
end
FINE_DEC: begin
fine_adj_state_r <= #TCQ FINE_DEC_WAIT;
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b1;
if ((ctl_lane_cnt == N_CTL_LANES-1) && (init_dec_cnt > 'd0))
init_dec_cnt <= #TCQ init_dec_cnt - 1;
else if ((ctl_lane_cnt == N_CTL_LANES-1) && (dec_cnt > 'd0))
dec_cnt <= #TCQ dec_cnt - 1;
end
FINE_DEC_WAIT: begin
ck_po_stg2_f_indec <= #TCQ 1'b0;
ck_po_stg2_f_en <= #TCQ 1'b0;
if (ctl_lane_cnt != N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ ctl_lane_cnt + 1;
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
end else if (ctl_lane_cnt == N_CTL_LANES-1) begin
ctl_lane_cnt <= #TCQ 'd0;
if ((dec_cnt > 'd0) || (init_dec_cnt > 'd0))
fine_adj_state_r <= #TCQ FINE_DEC_PREWAIT;
else begin
fine_adj_state_r <= #TCQ FINAL_WAIT;
if ((init_dec_cnt == 'd0) && ~init_dec_done)
init_dec_done <= #TCQ 1'b1;
else
final_dec_done <= #TCQ 1'b1;
end
end
end
FINE_DEC_PREWAIT: begin
fine_adj_state_r <= #TCQ FINE_DEC;
end
FINAL_WAIT: begin
rst_dqs_find <= #TCQ 1'b1;
fine_adj_state_r <= #TCQ RST_WAIT;
end
FINE_ADJ_DONE: begin
if (&pi_dqs_found_all_bank) begin
fine_adjust_done_r <= #TCQ 1'b1;
rst_dqs_find <= #TCQ 1'b0;
fine_adj_state_r <= #TCQ FINE_ADJ_DONE;
end
end
endcase
end
end
//*****************************************************************************
always@(posedge clk)
dqs_found_start_r <= #TCQ pi_dqs_found_start;
always @(posedge clk) begin
if (rst)
rnk_cnt_r <= #TCQ 2'b00;
else if (init_dqsfound_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r;
else if (rank_done_r)
rnk_cnt_r <= #TCQ rnk_cnt_r + 1;
end
//*****************************************************************
// Read data_offset calibration done signal
//*****************************************************************
always @(posedge clk) begin
if (rst || (|pi_rst_stg1_cal_r))
init_dqsfound_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank) begin
if (rnk_cnt_r == RANKS-1)
init_dqsfound_done_r <= #TCQ 1'b1;
else
init_dqsfound_done_r <= #TCQ 1'b0;
end
end
always @(posedge clk) begin
if (rst ||
(init_dqsfound_done_r && (rnk_cnt_r == RANKS-1)))
rank_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && ~(&pi_dqs_found_all_bank_r))
rank_done_r <= #TCQ 1'b1;
else
rank_done_r <= #TCQ 1'b0;
end
always @(posedge clk) begin
pi_dqs_found_lanes_r1 <= #TCQ pi_dqs_found_lanes;
pi_dqs_found_lanes_r2 <= #TCQ pi_dqs_found_lanes_r1;
pi_dqs_found_lanes_r3 <= #TCQ pi_dqs_found_lanes_r2;
init_dqsfound_done_r1 <= #TCQ init_dqsfound_done_r;
init_dqsfound_done_r2 <= #TCQ init_dqsfound_done_r1;
init_dqsfound_done_r3 <= #TCQ init_dqsfound_done_r2;
init_dqsfound_done_r4 <= #TCQ init_dqsfound_done_r3;
init_dqsfound_done_r5 <= #TCQ init_dqsfound_done_r4;
rank_done_r1 <= #TCQ rank_done_r;
dqsfound_retry_r1 <= #TCQ dqsfound_retry;
end
always @(posedge clk) begin
if (rst)
dqs_found_done_r <= #TCQ 1'b0;
else if (&pi_dqs_found_all_bank && (rnk_cnt_r == RANKS-1) && init_dqsfound_done_r1 &&
(fine_adj_state_r == FINE_ADJ_DONE))
dqs_found_done_r <= #TCQ 1'b1;
else
dqs_found_done_r <= #TCQ 1'b0;
end
generate
if (HIGHEST_BANK == 3) begin // Three I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[2] || fine_adjust)
pi_rst_stg1_cal_r[2] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[2]) ||
(pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2]) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[2] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[2] && ~pi_dqs_found_all_bank[2])
pi_rst_stg1_cal_r1[2] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[20+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[2])
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10] + 1;
else
retry_cnt[20+:10] <= #TCQ retry_cnt[20+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[2] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[2] && (retry_cnt[20+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[2] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: three_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: three_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (s = 0; s < RANKS; s = s + 1) begin: three_bank2_rst_loop
rd_byte_data_offset[s][12+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][12+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][12+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[2] &&
//(rd_byte_data_offset[rnk_cnt_r][12+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][12+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][12+:6] + 1;
end
//*****************************************************************************
// Two I/O Bank Interface
//*****************************************************************************
end else if (HIGHEST_BANK == 2) begin // Two I/O Bank interface
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[1] || fine_adjust)
pi_rst_stg1_cal_r[1] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[1]) ||
(pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1]) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[1] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[1] && ~pi_dqs_found_all_bank[1])
pi_rst_stg1_cal_r1[1] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[10+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[1])
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10] + 1;
else
retry_cnt[10+:10] <= #TCQ retry_cnt[10+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[1] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[1] && (retry_cnt[10+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[1] <= #TCQ 1'b1;
end
// Read data offset value for all DQS in a Bank
always @(posedge clk) begin
if (rst) begin
for (q = 0; q < RANKS; q = q + 1) begin: two_bank0_rst_loop
rd_byte_data_offset[q][0+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][0+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r][0+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][0+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][0+:6] + 1;
end
always @(posedge clk) begin
if (rst) begin
for (r = 0; r < RANKS; r = r + 1) begin: two_bank1_rst_loop
rd_byte_data_offset[r][6+:6] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r][6+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r][6+:6] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[1] &&
//(rd_byte_data_offset[rnk_cnt_r][6+:6] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r][6+:6]
<= #TCQ rd_byte_data_offset[rnk_cnt_r][6+:6] + 1;
end
//*****************************************************************************
// One I/O Bank Interface
//*****************************************************************************
end else begin // One I/O Bank Interface
// Read data offset value for all DQS in Bank0
always @(posedge clk) begin
if (rst) begin
for (l = 0; l < RANKS; l = l + 1) begin: bank_rst_loop
rd_byte_data_offset[l] <= #TCQ nCL + nAL - 2;
end
end else if ((rank_done_r1 && ~init_dqsfound_done_r) ||
(rd_byte_data_offset[rnk_cnt_r] > (nCL + nAL + LATENCY_FACTOR - 1)))
rd_byte_data_offset[rnk_cnt_r] <= #TCQ nCL + nAL - 2;
else if (dqs_found_start_r && ~pi_dqs_found_all_bank[0] &&
//(rd_byte_data_offset[rnk_cnt_r] < (nCL + nAL + LATENCY_FACTOR)) &&
(detect_pi_found_dqs && (detect_rd_cnt == 'd1)) && ~init_dqsfound_done_r && ~fine_adjust)
rd_byte_data_offset[rnk_cnt_r]
<= #TCQ rd_byte_data_offset[rnk_cnt_r] + 1;
end
// Reset read data offset calibration in all DQS Phaser_INs
// in a Bank after the read data offset value for a rank is determined
// or if within a Bank DQSFOUND is not asserted for all DQSs
always @(posedge clk) begin
if (rst || pi_rst_stg1_cal_r1[0] || fine_adjust)
pi_rst_stg1_cal_r[0] <= #TCQ 1'b0;
else if ((pi_dqs_found_start && ~dqs_found_start_r) ||
//(dqsfound_retry[0]) ||
(pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0]) ||
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_rst_stg1_cal_r[0] <= #TCQ 1'b1;
end
always @(posedge clk) begin
if (rst || fine_adjust)
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
else if (pi_rst_stg1_cal_r[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b1;
else if (~pi_dqs_found_any_bank_r[0] && ~pi_dqs_found_all_bank[0])
pi_rst_stg1_cal_r1[0] <= #TCQ 1'b0;
end
//*****************************************************************************
// Retry counter to track number of DQSFOUND retries
//*****************************************************************************
always @(posedge clk) begin
if (rst || rank_done_r)
retry_cnt[0+:10] <= #TCQ 'b0;
else if ((rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)) &&
~pi_dqs_found_all_bank[0])
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10] + 1;
else
retry_cnt[0+:10] <= #TCQ retry_cnt[0+:10];
end
// Error generation in case pi_dqs_found_all_bank
// is not asserted even with 3 dqfound retries
always @(posedge clk) begin
if (rst)
pi_dqs_found_err_r[0] <= #TCQ 1'b0;
else if (~pi_dqs_found_all_bank[0] && (retry_cnt[0+:10] == NUM_DQSFOUND_CAL) &&
(rd_byte_data_offset[rnk_cnt_r][0+:6] > (nCL + nAL + LATENCY_FACTOR - 1)))
pi_dqs_found_err_r[0] <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk) begin
if (rst)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b0}};
else if (rst_dqs_find)
pi_rst_stg1_cal <= #TCQ {HIGHEST_BANK{1'b1}};
else
pi_rst_stg1_cal <= #TCQ pi_rst_stg1_cal_r;
end
// Final read data offset value to be used during write calibration and
// normal operation
generate
genvar i;
genvar j;
for (i = 0; i < RANKS; i = i + 1) begin: rank_final_loop
reg [5:0] final_do_cand [RANKS-1:0];
// combinatorially select the candidate offset for the bank
// indexed by final_do_index
if (HIGHEST_BANK == 3) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = final_data_offset[i][17:12];
default: final_do_cand[i] = 'd0;
endcase
end
end else if (HIGHEST_BANK == 2) begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = final_data_offset[i][11:6];
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end else begin
always @(*) begin
case (final_do_index[i])
3'b000: final_do_cand[i] = final_data_offset[i][5:0];
3'b001: final_do_cand[i] = 'd0;
3'b010: final_do_cand[i] = 'd0;
default: final_do_cand[i] = 'd0;
endcase
end
end
always @(posedge clk or posedge rst) begin
if (rst)
final_do_max[i] <= #TCQ 0;
else begin
final_do_max[i] <= #TCQ final_do_max[i]; // default
case (final_do_index[i])
3'b000: if ( | DATA_PRESENT[3:0])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b001: if ( | DATA_PRESENT[7:4])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
3'b010: if ( | DATA_PRESENT[11:8])
if (final_do_max[i] < final_do_cand[i])
if (CWL_M % 2) // odd latency CAS slot 1
final_do_max[i] <= #TCQ final_do_cand[i] - 1;
else
final_do_max[i] <= #TCQ final_do_cand[i];
default:
final_do_max[i] <= #TCQ final_do_max[i];
endcase
end
end
always @(posedge clk)
if (rst) begin
final_do_index[i] <= #TCQ 0;
end
else begin
final_do_index[i] <= #TCQ final_do_index[i] + 1;
end
for (j = 0; j < HIGHEST_BANK; j = j + 1) begin: bank_final_loop
always @(posedge clk) begin
if (rst) begin
final_data_offset[i][6*j+:6] <= #TCQ 'b0;
end
else begin
//if (dqsfound_retry[j])
// final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
//else
if (init_dqsfound_done_r && ~init_dqsfound_done_r1) begin
if ( DATA_PRESENT [ j*4+:4] != 0) begin // has a data lane
final_data_offset[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
if (CWL_M % 2) // odd latency CAS slot 1
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6] - 1;
else // even latency CAS slot 0
final_data_offset_mc[i][6*j+:6] <= #TCQ rd_byte_data_offset[i][6*j+:6];
end
end
else if (init_dqsfound_done_r5 ) begin
if ( DATA_PRESENT [ j*4+:4] == 0) begin // all control lanes
final_data_offset[i][6*j+:6] <= #TCQ final_do_max[i];
final_data_offset_mc[i][6*j+:6] <= #TCQ final_do_max[i];
end
end
end
end
end
end
endgenerate
// Error generation in case pi_found_dqs signal from Phaser_IN
// is not asserted when a common rddata_offset value is used
always @(posedge clk) begin
pi_dqs_found_err <= #TCQ |pi_dqs_found_err_r;
end
endmodule
|
/***********************************************************
-- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable wrapper instantiating
// up to 5 memory banks of 4-lane phy primitives. There
// There are always 2 control banks leaving 18 lanes for data.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_mc_phy
#(
// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter RCLK_SELECT_BANK = 0,
parameter RCLK_SELECT_LANE = "B",
parameter RCLK_SELECT_EDGE = 4'b1111,
parameter GENERATE_DDR_CK_MAP = "0B",
parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002,
parameter USE_PRE_POST_FIFO = "TRUE",
parameter SYNTHESIS = "FALSE",
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PI_SEL_CLK_OFFSET = 6,
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio
// common to all i/o banks
parameter PHY_FOUR_WINDOW_CLOCKS = 63,
parameter PHY_EVENTS_DELAY = 18,
parameter PHY_COUNT_EN = "TRUE",
parameter PHY_SYNC_MODE = "TRUE",
parameter PHY_DISABLE_SEQ_MATCH = "FALSE",
parameter MASTER_PHY_CTL = 0,
// common to instance 0
parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff,
parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_0_LANE_REMAP = 16'h3210,
parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_0_IODELAY_GRP = "IODELAY_MIG",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter NUM_DDR_CK = 1,
parameter PHY_0_DATA_CTL = DATA_CTL_B0,
parameter PHY_0_CMD_OFFSET = 0,
parameter PHY_0_RD_CMD_OFFSET_0 = 0,
parameter PHY_0_RD_CMD_OFFSET_1 = 0,
parameter PHY_0_RD_CMD_OFFSET_2 = 0,
parameter PHY_0_RD_CMD_OFFSET_3 = 0,
parameter PHY_0_RD_DURATION_0 = 0,
parameter PHY_0_RD_DURATION_1 = 0,
parameter PHY_0_RD_DURATION_2 = 0,
parameter PHY_0_RD_DURATION_3 = 0,
parameter PHY_0_WR_CMD_OFFSET_0 = 0,
parameter PHY_0_WR_CMD_OFFSET_1 = 0,
parameter PHY_0_WR_CMD_OFFSET_2 = 0,
parameter PHY_0_WR_CMD_OFFSET_3 = 0,
parameter PHY_0_WR_DURATION_0 = 0,
parameter PHY_0_WR_DURATION_1 = 0,
parameter PHY_0_WR_DURATION_2 = 0,
parameter PHY_0_WR_DURATION_3 = 0,
parameter PHY_0_AO_WRLVL_EN = 0,
parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PHY_0_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE",
parameter PHY_0_A_PI_CLKOUT_DIV = 2,
parameter PHY_0_A_PO_CLKOUT_DIV = 2,
parameter PHY_0_A_BURST_MODE = "TRUE",
parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OCLK_DELAY = 25,
parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE",
parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED",
parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED",
parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00,
parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
// common to instance 1
parameter PHY_1_BITLANES = PHY_0_BITLANES,
parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_1_LANE_REMAP = 16'h3210,
parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_1_DATA_CTL = DATA_CTL_B1,
parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_1_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV,
parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE,
parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC ,
parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
// common to instance 2
parameter PHY_2_BITLANES = PHY_0_BITLANES,
parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_2_LANE_REMAP = 16'h3210,
parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_2_DATA_CTL = DATA_CTL_B2,
parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_2_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV ,
parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE ,
parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC,
parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE",
parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter TCK = 2500,
// local computational use, do not pass down
parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3])
+ (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3])
, // must not delete comma for syntax
parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))),
parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B3 = 0,
parameter HIGHEST_LANE_B4 = 0,
parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))),
parameter LP_DDR_CK_WIDTH = 2,
parameter GENERATE_SIGNAL_SPLIT = "FALSE"
,parameter CKE_ODT_AUX = "FALSE"
)
(
input rst,
input ddr_rst_in_n ,
input phy_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input auxout_clk,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [31:0] phy_ctl_wd,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input phy_ctl_wr,
input if_rst,
input if_empty_def,
input cke_in,
input idelay_ce,
input idelay_ld,
input idelay_inc,
input phyGo,
input input_sink,
output if_a_empty,
(* keep = "true", max_fanout = 3 *) output if_empty /* synthesis syn_maxfan = 3 */,
output if_empty_or,
output if_empty_and,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output pre_data_a_full,
output [HIGHEST_LANE*80-1:0] phy_din,
output phy_ctl_a_full,
(* keep = "true", max_fanout = 3 *) output wire [3:0] phy_ctl_full,
output [HIGHEST_LANE*12-1:0] mem_dq_out,
output [HIGHEST_LANE*12-1:0] mem_dq_ts,
input [HIGHEST_LANE*10-1:0] mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
(* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller
output phy_ctl_ready, // to fabric
output reg rst_out, // to memory
output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
// output rclk,
output mcGo,
output ref_dll_lock,
// calibration signals
input phy_write_calib,
input phy_read_calib,
input [5:0] calib_sel,
input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank
input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs
input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane
input calib_in_common,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input po_counter_read_en,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_phase_locked,
output pi_phase_locked_all,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg pi_dqs_out_of_range
);
wire [7:0] calib_zero_inputs_int ;
wire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ;
//Added the temporary variable for concadination operation
wire [2:0] calib_sel_byte0 ;
wire [2:0] calib_sel_byte1 ;
wire [2:0] calib_sel_byte2 ;
wire [4:0] po_coarse_overflow_w;
wire [4:0] po_fine_overflow_w;
wire [8:0] po_counter_read_val_w[4:0];
wire [4:0] pi_fine_overflow_w;
wire [5:0] pi_counter_read_val_w[4:0];
wire [4:0] pi_dqs_found_w;
wire [4:0] pi_dqs_found_all_w;
wire [4:0] pi_dqs_found_any_w;
wire [4:0] pi_dqs_out_of_range_w;
wire [4:0] pi_phase_locked_w;
wire [4:0] pi_phase_locked_all_w;
wire [4:0] rclk_w;
wire [HIGHEST_BANK-1:0] phy_ctl_ready_w;
wire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0];
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_;
wire [3:0] if_q0;
wire [3:0] if_q1;
wire [3:0] if_q2;
wire [3:0] if_q3;
wire [3:0] if_q4;
wire [7:0] if_q5;
wire [7:0] if_q6;
wire [3:0] if_q7;
wire [3:0] if_q8;
wire [3:0] if_q9;
wire [31:0] _phy_ctl_wd;
wire [3:0] aux_in_[4:1];
wire [3:0] rst_out_w;
wire freq_refclk_split;
wire mem_refclk_split;
wire mem_refclk_div4_split;
wire sync_pulse_split;
wire phy_clk_split0;
wire phy_ctl_clk_split0;
wire [31:0] phy_ctl_wd_split0;
wire phy_ctl_wr_split0;
wire phy_ctl_clk_split1;
wire phy_clk_split1;
wire [31:0] phy_ctl_wd_split1;
wire phy_ctl_wr_split1;
wire [5:0] phy_data_offset_1_split1;
wire phy_ctl_clk_split2;
wire phy_clk_split2;
wire [31:0] phy_ctl_wd_split2;
wire phy_ctl_wr_split2;
wire [5:0] phy_data_offset_2_split2;
wire [HIGHEST_LANE*80-1:0] phy_dout_split0;
wire phy_cmd_wr_en_split0;
wire phy_data_wr_en_split0;
wire phy_rd_en_split0;
wire [HIGHEST_LANE*80-1:0] phy_dout_split1;
wire phy_cmd_wr_en_split1;
wire phy_data_wr_en_split1;
wire phy_rd_en_split1;
wire [HIGHEST_LANE*80-1:0] phy_dout_split2;
wire phy_cmd_wr_en_split2;
wire phy_data_wr_en_split2;
wire phy_rd_en_split2;
wire phy_ctl_mstr_empty;
wire [HIGHEST_BANK-1:0] phy_ctl_empty;
wire _phy_ctl_a_full_f;
wire _phy_ctl_a_empty_f;
wire _phy_ctl_full_f;
wire _phy_ctl_empty_f;
wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p;
wire [HIGHEST_BANK-1:0] _phy_ctl_full_p;
wire [HIGHEST_BANK-1:0] of_ctl_a_full_v;
wire [HIGHEST_BANK-1:0] of_ctl_full_v;
wire [HIGHEST_BANK-1:0] of_data_a_full_v;
wire [HIGHEST_BANK-1:0] of_data_full_v;
wire [HIGHEST_BANK-1:0] pre_data_a_full_v;
wire [HIGHEST_BANK-1:0] if_empty_v;
wire [HIGHEST_BANK-1:0] byte_rd_en_v;
wire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks;
wire [HIGHEST_BANK-1:0] if_empty_or_v;
wire [HIGHEST_BANK-1:0] if_empty_and_v;
wire [HIGHEST_BANK-1:0] if_a_empty_v;
localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4";
localparam IF_SYNCHRONOUS_MODE = "FALSE";
localparam IF_SLOW_WR_CLK = "FALSE";
localparam IF_SLOW_RD_CLK = "FALSE";
localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE";
localparam RCLK_NEG_EDGE = 3'b000;
localparam RCLK_POS_EDGE = 3'b111;
localparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF;
localparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF;
localparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF;
// hi, lo positions for data offset field, MIG doesn't allow defines
localparam PC_DATA_OFFSET_RANGE_HI = 22;
localparam PC_DATA_OFFSET_RANGE_LO = 17;
/* Phaser_In Output source coding table
"PHASE_REF" : 4'b0000;
"DELAYED_MEM_REF" : 4'b0101;
"DELAYED_PHASE_REF" : 4'b0011;
"DELAYED_REF" : 4'b0001;
"FREQ_REF" : 4'b1000;
"MEM_REF" : 4'b0010;
*/
localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF";
localparam DDR_TCK = TCK;
localparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
localparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0;
localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line
localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line
localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta
/*
Intrinsic delay of Phaser In Stage 1
@3300ps - 1.939ns - 58.8%
@2500ps - 1.657ns - 66.3%
@1875ps - 1.263ns - 67.4%
@1500ps - 1.021ns - 68.1%
@1250ps - 0.868ns - 69.4%
@1072ps - 0.752ns - 70.1%
@938ps - 0.667ns - 71.1%
*/
// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0
// Fraction of a full DDR_TCK period
localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 :
((DDR_TCK < 1005) ? 0.667 :
(DDR_TCK < 1160) ? 0.752 :
(DDR_TCK < 1375) ? 0.868 :
(DDR_TCK < 1685) ? 1.021 :
(DDR_TCK < 2185) ? 1.263 :
(DDR_TCK < 2900) ? 1.657 :
(DDR_TCK < 3100) ? 1.771 : 1.939)*1000;
/*
Intrinsic delay of Phaser In Stage 2
@3300ps - 0.912ns - 27.6% - single tap - 13ps
@3000ps - 0.848ns - 28.3% - single tap - 11ps
@2500ps - 1.264ns - 50.6% - single tap - 19ps
@1875ps - 1.000ns - 53.3% - single tap - 15ps
@1500ps - 0.848ns - 56.5% - single tap - 11ps
@1250ps - 0.736ns - 58.9% - single tap - 9ps
@1072ps - 0.664ns - 61.9% - single tap - 8ps
@938ps - 0.608ns - 64.8% - single tap - 7ps
*/
// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps)
localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor
/*
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1
@3300ps - 1.294ns - 39.2%
@2500ps - 1.294ns - 51.8%
@1875ps - 1.030ns - 54.9%
@1500ps - 0.878ns - 58.5%
@1250ps - 0.766ns - 61.3%
@1072ps - 0.694ns - 64.7%
@938ps - 0.638ns - 68.0%
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0
@3300ps - 2.084ns - 63.2% - single tap - 20ps
@2500ps - 2.084ns - 81.9% - single tap - 19ps
@1875ps - 1.676ns - 89.4% - single tap - 15ps
@1500ps - 1.444ns - 96.3% - single tap - 11ps
@1250ps - 1.276ns - 102.1% - single tap - 9ps
@1072ps - 1.164ns - 108.6% - single tap - 8ps
@938ps - 1.076ns - 114.7% - single tap - 7ps
*/
// Fraction of a full DDR_TCK period
localparam real PO_STG1_INTRINSIC_DELAY = 0;
localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor
localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor
localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY +
(PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY);
// When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can
// go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this,
// a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments
// to the stage 2 delay can be made after reset is removed.
localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PO_CIRC_BUF_META_ZONE = 200.0;
localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0;
localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK;
// If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold
// If it is not more than the threshold than we must push the delay after the clock period plus a guardband.
//A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated.
localparam integer PO_CIRC_BUF_DELAY = 60;
//localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 :
// (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE :
// (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE;
localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE;
localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY;
localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY;
localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE);
localparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi
// The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path
// of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the
// oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment
// is within the range of the stage 2 delay line in the Phaser_In.
localparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY);
localparam integer PO_DELAY_INT = PO_DELAY;
localparam real PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK);
// if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is
// if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge.
// note that in this case PI_OFFSET is negative so invert before subtracting.
localparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0
? PI_OFFSET
: ((-PI_OFFSET) < DDR_TCK/2) ?
(DDR_TCK/2 - (- PI_OFFSET)) :
(DDR_TCK - (- PI_OFFSET)) ;
localparam real PI_STG2_DELAY =
(PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ?
PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND);
localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE;
localparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE));
localparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
wire _phy_clk;
wire [2:0] mcGo_w;
wire [HIGHEST_BANK-1:0] ref_dll_lock_w;
reg [15:0] mcGo_r;
assign ref_dll_lock = & ref_dll_lock_w;
initial begin
if ( SYNTHESIS == "FALSE" ) begin
$display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1);
$display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1);
$display("%m : HIGHEST_BANK = %d", HIGHEST_BANK);
$display("%m : FREQ_REF_PERIOD = %0.2f ", FREQ_REF_PERIOD);
$display("%m : DDR_TCK = %0d ", DDR_TCK);
$display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE);
$display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY);
$display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET);
$display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE);
$display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY);
$display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY);
$display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY);
$display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY);
$display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY);
$display("%m : PO_DELAY = %0.2f ", PO_DELAY);
$display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY);
$display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY);
$display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY);
$display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY);
$display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY);
$display("%m : PI_MAX_STG2_DELAY = %0.2f ", PI_MAX_STG2_DELAY);
$display("%m : PI_OFFSET = %0.2f ", PI_OFFSET);
if ( PI_OFFSET < 0) $display("%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used.");
$display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY);
$display("%m :PI_STG2_DELAY_CAND = %0.2f ",PI_STG2_DELAY_CAND);
$display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY);
$display("%m : RCLK_SELECT_EDGE = %0b ", LP_RCLK_SELECT_EDGE);
end // SYNTHESIS
if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display("WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY);
end
assign sync_pulse_split = sync_pulse;
assign mem_refclk_split = mem_refclk;
assign freq_refclk_split = freq_refclk;
assign mem_refclk_div4_split = mem_refclk_div4;
assign phy_ctl_clk_split0 = _phy_clk;
assign phy_ctl_wd_split0 = phy_ctl_wd;
assign phy_ctl_wr_split0 = phy_ctl_wr;
assign phy_clk_split0 = phy_clk;
assign phy_cmd_wr_en_split0 = phy_cmd_wr_en;
assign phy_data_wr_en_split0 = phy_data_wr_en;
assign phy_rd_en_split0 = phy_rd_en;
assign phy_dout_split0 = phy_dout;
assign phy_ctl_clk_split1 = phy_clk;
assign phy_ctl_wd_split1 = phy_ctl_wd;
assign phy_data_offset_1_split1 = data_offset_1;
assign phy_ctl_wr_split1 = phy_ctl_wr;
assign phy_clk_split1 = phy_clk;
assign phy_cmd_wr_en_split1 = phy_cmd_wr_en;
assign phy_data_wr_en_split1 = phy_data_wr_en;
assign phy_rd_en_split1 = phy_rd_en;
assign phy_dout_split1 = phy_dout;
assign phy_ctl_clk_split2 = phy_clk;
assign phy_ctl_wd_split2 = phy_ctl_wd;
assign phy_data_offset_2_split2 = data_offset_2;
assign phy_ctl_wr_split2 = phy_ctl_wr;
assign phy_clk_split2 = phy_clk;
assign phy_cmd_wr_en_split2 = phy_cmd_wr_en;
assign phy_data_wr_en_split2 = phy_data_wr_en;
assign phy_rd_en_split2 = phy_rd_en;
assign phy_dout_split2 = phy_dout;
// these wires are needed to coerce correct synthesis
// the synthesizer did not always see the widths of the
// parameters as 4 bits.
wire [3:0] blb0 = BYTE_LANES_B0;
wire [3:0] blb1 = BYTE_LANES_B1;
wire [3:0] blb2 = BYTE_LANES_B2;
wire [3:0] dcb0 = DATA_CTL_B0;
wire [3:0] dcb1 = DATA_CTL_B1;
wire [3:0] dcb2 = DATA_CTL_B2;
assign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0});
assign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0});
assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0];
assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs};
//Added to remove concadination in the instantiation
assign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ;
assign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ;
assign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ;
assign calib_zero_lanes_int = calib_zero_lanes;
assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0];
assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL];
assign of_ctl_a_full = |of_ctl_a_full_v;
assign of_ctl_full = |of_ctl_full_v;
assign of_data_a_full = |of_data_a_full_v;
assign of_data_full = |of_data_full_v;
assign pre_data_a_full= |pre_data_a_full_v;
// if if_empty_def == 1, empty is asserted only if all are empty;
// this allows the user to detect a skewed fifo depth and self-clear
// if desired. It avoids a reset to clear the flags.
assign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v;
assign if_empty_or = |if_empty_or_v;
assign if_empty_and = &if_empty_and_v;
assign if_a_empty = |if_a_empty_v;
generate
genvar i;
for (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen
case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff)
16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
default : initial $display("ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) ", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff ));
endcase
end
endgenerate
//assign rclk = rclk_w[RCLK_SELECT_BANK];
reg rst_auxout;
reg rst_auxout_r;
reg rst_auxout_rr;
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout_r <= #(1) 1'b1;
rst_auxout_rr <= #(1) 1'b1;
end
else begin
rst_auxout_r <= #(1) rst;
rst_auxout_rr <= #(1) rst_auxout_r;
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
else begin
always @(negedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
localparam L_RESET_SELECT_BANK =
(BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK;
always @(*) begin
rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n;
end
always @(posedge phy_clk or posedge rst) begin
if ( rst)
mcGo_r <= #(1) 0;
else
mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w;
end
assign mcGo = mcGo_r[15];
generate
// this is an optional 1 clock delay to add latency to the phy_control programming path
if (PHYCTL_CMD_FIFO == "TRUE") begin : cmd_fifo_soft
reg [31:0] phy_wd_reg = 0;
reg [3:0] aux_in1_reg = 0;
reg [3:0] aux_in2_reg = 0;
reg sfifo_ready = 0;
assign _phy_ctl_wd = phy_wd_reg;
assign aux_in_[1] = aux_in1_reg;
assign aux_in_[2] = aux_in2_reg;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[1] = |_phy_ctl_full_p;
assign phy_ctl_full[2] = |_phy_ctl_full_p;
assign phy_ctl_full[3] = |_phy_ctl_full_p;
assign _phy_clk = phy_clk;
always @(posedge phy_clk) begin
phy_wd_reg <= #1 phy_ctl_wd;
aux_in1_reg <= #1 aux_in_1;
aux_in2_reg <= #1 aux_in_2;
sfifo_ready <= #1 phy_ctl_wr;
end
end
else if (PHYCTL_CMD_FIFO == "FALSE") begin
assign _phy_ctl_wd = phy_ctl_wd;
assign aux_in_[1] = aux_in_1;
assign aux_in_[2] = aux_in_2;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[3:1] = 3'b000;
assign _phy_clk = phy_clk;
end
endgenerate
// instance of four-lane phy
generate
if (HIGHEST_BANK == 3) begin : banks_3
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]};
end
else if (HIGHEST_BANK == 2) begin : banks_2
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1};
end
else begin : banks_1
assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1};
end
if ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */
.DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY),
.BITLANES (PHY_0_BITLANES),
.BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK),
.LAST_BANK (PHY_0_IS_LAST_BANK),
.LANE_REMAP (PHY_0_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_0_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_0_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_0_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_0_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_0_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_0_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_0_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_0_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_0_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split0),
.phy_ctl_clk (phy_ctl_clk_split0),
.phy_ctl_wd (phy_ctl_wd_split0),
.data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]),
.phy_ctl_wr (phy_ctl_wr_split0),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]),
.phy_cmd_wr_en (phy_cmd_wr_en_split0),
.phy_data_wr_en (phy_data_wr_en_split0),
.phy_rd_en (phy_rd_en_split0),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[0]),
.rclk (),
.rst_out (rst_out_w[0]),
.mcGo (mcGo_w[0]),
.ref_dll_lock (ref_dll_lock_w[0]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]),
.if_a_empty (if_a_empty_v[0]),
.if_empty (if_empty_v[0]),
.byte_rd_en (byte_rd_en_v[0]),
.if_empty_or (if_empty_or_v[0]),
.if_empty_and (if_empty_and_v[0]),
.of_ctl_a_full (of_ctl_a_full_v[0]),
.of_data_a_full (of_data_a_full_v[0]),
.of_ctl_full (of_ctl_full_v[0]),
.of_data_full (of_data_full_v[0]),
.pre_data_a_full (pre_data_a_full_v[0]),
.phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]),
.phy_ctl_a_full (_phy_ctl_a_full_p[0]),
.phy_ctl_full (_phy_ctl_full_p[0]),
.phy_ctl_empty (phy_ctl_empty[0]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]),
.aux_out (aux_out_[3:0]),
.phy_ctl_ready (phy_ctl_ready_w[0]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte0),
.calib_zero_ctrl (calib_zero_ctrl[0]),
.calib_zero_lanes (calib_zero_lanes_int[3:0]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[0]),
.po_fine_enable (po_fine_enable[0]),
.po_fine_inc (po_fine_inc[0]),
.po_coarse_inc (po_coarse_inc[0]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[0]),
.po_fine_overflow (po_fine_overflow_w[0]),
.po_counter_read_val (po_counter_read_val_w[0]),
.pi_rst_dqs_find (pi_rst_dqs_find[0]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[0]),
.pi_counter_read_val (pi_counter_read_val_w[0]),
.pi_dqs_found (pi_dqs_found_w[0]),
.pi_dqs_found_all (pi_dqs_found_all_w[0]),
.pi_dqs_found_any (pi_dqs_found_any_w[0]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]),
.pi_phase_locked (pi_phase_locked_w[0]),
.pi_phase_locked_all (pi_phase_locked_all_w[0])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[0] <= #100 0;
aux_out[2] <= #100 0;
end
else begin
aux_out[0] <= #100 aux_out_[0];
aux_out[2] <= #100 aux_out_[2];
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
end
else begin
if ( HIGHEST_BANK > 0) begin
assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0;
assign _phy_ctl_a_full_p[0] = 0;
assign of_ctl_a_full_v[0] = 0;
assign of_ctl_full_v[0] = 0;
assign of_data_a_full_v[0] = 0;
assign of_data_full_v[0] = 0;
assign pre_data_a_full_v[0] = 0;
assign if_empty_v[0] = 0;
assign byte_rd_en_v[0] = 1;
always @(*)
aux_out[3:0] = 0;
end
assign pi_dqs_found_w[0] = 1;
assign pi_dqs_found_all_w[0] = 1;
assign pi_dqs_found_any_w[0] = 0;
assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_out_of_range_w[0] = 0;
assign pi_phase_locked_w[0] = 1;
assign po_fine_overflow_w[0] = 0;
assign po_coarse_overflow_w[0] = 0;
assign po_fine_overflow_w[0] = 0;
assign pi_fine_overflow_w[0] = 0;
assign po_counter_read_val_w[0] = 0;
assign pi_counter_read_val_w[0] = 0;
assign mcGo_w[0] = 1;
if ( RCLK_SELECT_BANK == 0)
always @(*)
aux_out[3:0] = 0;
end
if ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */
.DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY),
.BITLANES (PHY_1_BITLANES),
.BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK),
.LAST_BANK (PHY_1_IS_LAST_BANK ),
.LANE_REMAP (PHY_1_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_1_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_1_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_1_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_1_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_1_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_1_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_1_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_1_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_1_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_1_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_1_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_1_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_1_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split1),
.phy_ctl_clk (phy_ctl_clk_split1),
.phy_ctl_wd (phy_ctl_wd_split1),
.data_offset (phy_data_offset_1_split1),
.phy_ctl_wr (phy_ctl_wr_split1),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]),
.phy_cmd_wr_en (phy_cmd_wr_en_split1),
.phy_data_wr_en (phy_data_wr_en_split1),
.phy_rd_en (phy_rd_en_split1),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[1]),
.rclk (),
.rst_out (rst_out_w[1]),
.mcGo (mcGo_w[1]),
.ref_dll_lock (ref_dll_lock_w[1]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]),
.if_a_empty (if_a_empty_v[1]),
.if_empty (if_empty_v[1]),
.byte_rd_en (byte_rd_en_v[1]),
.if_empty_or (if_empty_or_v[1]),
.if_empty_and (if_empty_and_v[1]),
.of_ctl_a_full (of_ctl_a_full_v[1]),
.of_data_a_full (of_data_a_full_v[1]),
.of_ctl_full (of_ctl_full_v[1]),
.of_data_full (of_data_full_v[1]),
.pre_data_a_full (pre_data_a_full_v[1]),
.phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]),
.phy_ctl_a_full (_phy_ctl_a_full_p[1]),
.phy_ctl_full (_phy_ctl_full_p[1]),
.phy_ctl_empty (phy_ctl_empty[1]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]),
.aux_out (aux_out_[7:4]),
.phy_ctl_ready (phy_ctl_ready_w[1]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte1),
.calib_zero_ctrl (calib_zero_ctrl[1]),
.calib_zero_lanes (calib_zero_lanes_int[7:4]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[1]),
.po_fine_enable (po_fine_enable[1]),
.po_fine_inc (po_fine_inc[1]),
.po_coarse_inc (po_coarse_inc[1]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[1]),
.po_fine_overflow (po_fine_overflow_w[1]),
.po_counter_read_val (po_counter_read_val_w[1]),
.pi_rst_dqs_find (pi_rst_dqs_find[1]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[1]),
.pi_counter_read_val (pi_counter_read_val_w[1]),
.pi_dqs_found (pi_dqs_found_w[1]),
.pi_dqs_found_all (pi_dqs_found_all_w[1]),
.pi_dqs_found_any (pi_dqs_found_any_w[1]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]),
.pi_phase_locked (pi_phase_locked_w[1]),
.pi_phase_locked_all (pi_phase_locked_all_w[1])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[4] <= #100 0;
aux_out[6] <= #100 0;
end
else begin
aux_out[4] <= #100 aux_out_[4];
aux_out[6] <= #100 aux_out_[6];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
end
else begin
if ( HIGHEST_BANK > 1) begin
assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0;
assign _phy_ctl_a_full_p[1] = 0;
assign of_ctl_a_full_v[1] = 0;
assign of_ctl_full_v[1] = 0;
assign of_data_a_full_v[1] = 0;
assign of_data_full_v[1] = 0;
assign pre_data_a_full_v[1] = 0;
assign if_empty_v[1] = 0;
assign byte_rd_en_v[1] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
always @(*)
aux_out[7:4] = 0;
end
assign pi_dqs_found_w[1] = 1;
assign pi_dqs_found_all_w[1] = 1;
assign pi_dqs_found_any_w[1] = 0;
assign pi_dqs_out_of_range_w[1] = 0;
assign pi_phase_locked_w[1] = 1;
assign po_coarse_overflow_w[1] = 0;
assign po_fine_overflow_w[1] = 0;
assign pi_fine_overflow_w[1] = 0;
assign po_counter_read_val_w[1] = 0;
assign pi_counter_read_val_w[1] = 0;
assign mcGo_w[1] = 1;
end
if ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */
.DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY),
.BITLANES (PHY_2_BITLANES),
.BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK),
.LAST_BANK (PHY_2_IS_LAST_BANK ),
.LANE_REMAP (PHY_2_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_2_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_2_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_2_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_2_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_2_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_2_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_2_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_2_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_2_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_2_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_2_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_2_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_2_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split2),
.phy_ctl_clk (phy_ctl_clk_split2),
.phy_ctl_wd (phy_ctl_wd_split2),
.data_offset (phy_data_offset_2_split2),
.phy_ctl_wr (phy_ctl_wr_split2),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]),
.phy_cmd_wr_en (phy_cmd_wr_en_split2),
.phy_data_wr_en (phy_data_wr_en_split2),
.phy_rd_en (phy_rd_en_split2),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[2]),
.rclk (),
.rst_out (rst_out_w[2]),
.mcGo (mcGo_w[2]),
.ref_dll_lock (ref_dll_lock_w[2]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]),
.if_a_empty (if_a_empty_v[2]),
.if_empty (if_empty_v[2]),
.byte_rd_en (byte_rd_en_v[2]),
.if_empty_or (if_empty_or_v[2]),
.if_empty_and (if_empty_and_v[2]),
.of_ctl_a_full (of_ctl_a_full_v[2]),
.of_data_a_full (of_data_a_full_v[2]),
.of_ctl_full (of_ctl_full_v[2]),
.of_data_full (of_data_full_v[2]),
.pre_data_a_full (pre_data_a_full_v[2]),
.phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]),
.phy_ctl_a_full (_phy_ctl_a_full_p[2]),
.phy_ctl_full (_phy_ctl_full_p[2]),
.phy_ctl_empty (phy_ctl_empty[2]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]),
.aux_out (aux_out_[11:8]),
.phy_ctl_ready (phy_ctl_ready_w[2]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte2),
.calib_zero_ctrl (calib_zero_ctrl[2]),
.calib_zero_lanes (calib_zero_lanes_int[11:8]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[2]),
.po_fine_enable (po_fine_enable[2]),
.po_fine_inc (po_fine_inc[2]),
.po_coarse_inc (po_coarse_inc[2]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[2]),
.po_fine_overflow (po_fine_overflow_w[2]),
.po_counter_read_val (po_counter_read_val_w[2]),
.pi_rst_dqs_find (pi_rst_dqs_find[2]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[2]),
.pi_counter_read_val (pi_counter_read_val_w[2]),
.pi_dqs_found (pi_dqs_found_w[2]),
.pi_dqs_found_all (pi_dqs_found_all_w[2]),
.pi_dqs_found_any (pi_dqs_found_any_w[2]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]),
.pi_phase_locked (pi_phase_locked_w[2]),
.pi_phase_locked_all (pi_phase_locked_all_w[2])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[8] <= #100 0;
aux_out[10] <= #100 0;
end
else begin
aux_out[8] <= #100 aux_out_[8];
aux_out[10] <= #100 aux_out_[10];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
end
else begin
if ( HIGHEST_BANK > 2) begin
assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0;
assign _phy_ctl_a_full_p[2] = 0;
assign of_ctl_a_full_v[2] = 0;
assign of_ctl_full_v[2] = 0;
assign of_data_a_full_v[2] = 0;
assign of_data_full_v[2] = 0;
assign pre_data_a_full_v[2] = 0;
assign if_empty_v[2] = 0;
assign byte_rd_en_v[2] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
always @(*)
aux_out[11:8] = 0;
end
assign pi_dqs_found_w[2] = 1;
assign pi_dqs_found_all_w[2] = 1;
assign pi_dqs_found_any_w[2] = 0;
assign pi_dqs_out_of_range_w[2] = 0;
assign pi_phase_locked_w[2] = 1;
assign po_coarse_overflow_w[2] = 0;
assign po_fine_overflow_w[2] = 0;
assign po_counter_read_val_w[2] = 0;
assign pi_counter_read_val_w[2] = 0;
assign mcGo_w[2] = 1;
end
endgenerate
generate
// for single bank , emit an extra phaser_in to generate rclk
// so that auxout can be placed in another region
// if desired
if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0)
begin : phaser_in_rclk
localparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY;
PHASER_IN_PHY #(
.BURST_MODE ( PHY_0_A_BURST_MODE),
.CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV),
.FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.FINE_DELAY ( L_EXTRA_PI_FINE_DELAY),
.OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC)
) phaser_in_rclk (
.DQSFOUND (),
.DQSOUTOFRANGE (),
.FINEOVERFLOW (),
.PHASELOCKED (),
.ISERDESRST (),
.ICLKDIV (),
.ICLK (),
.COUNTERREADVAL (),
.RCLK (),
.WRENABLE (),
.BURSTPENDINGPHY (),
.ENCALIBPHY (),
.FINEENABLE (0),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (0),
.PHASEREFCLK (),
.RSTDQSFIND (0),
.RST (rst),
.FINEINC (),
.COUNTERLOADEN (),
.COUNTERREADEN (),
.COUNTERLOADVAL (),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
end
endgenerate
always @(*) begin
case (calib_sel[5:3])
3'b000: begin
po_coarse_overflow = po_coarse_overflow_w[0];
po_fine_overflow = po_fine_overflow_w[0];
po_counter_read_val = po_counter_read_val_w[0];
pi_fine_overflow = pi_fine_overflow_w[0];
pi_counter_read_val = pi_counter_read_val_w[0];
pi_phase_locked = pi_phase_locked_w[0];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[0];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[0];
end
3'b001: begin
po_coarse_overflow = po_coarse_overflow_w[1];
po_fine_overflow = po_fine_overflow_w[1];
po_counter_read_val = po_counter_read_val_w[1];
pi_fine_overflow = pi_fine_overflow_w[1];
pi_counter_read_val = pi_counter_read_val_w[1];
pi_phase_locked = pi_phase_locked_w[1];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[1];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[1];
end
3'b010: begin
po_coarse_overflow = po_coarse_overflow_w[2];
po_fine_overflow = po_fine_overflow_w[2];
po_counter_read_val = po_counter_read_val_w[2];
pi_fine_overflow = pi_fine_overflow_w[2];
pi_counter_read_val = pi_counter_read_val_w[2];
pi_phase_locked = pi_phase_locked_w[2];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[2];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[2];
end
default: begin
po_coarse_overflow = 0;
po_fine_overflow = 0;
po_counter_read_val = 0;
pi_fine_overflow = 0;
pi_counter_read_val = 0;
pi_phase_locked = 0;
pi_dqs_found = 0;
pi_dqs_out_of_range = 0;
end
endcase
end
endmodule // mc_phy
|
/***********************************************************
-- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable wrapper instantiating
// up to 5 memory banks of 4-lane phy primitives. There
// There are always 2 control banks leaving 18 lanes for data.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_mc_phy
#(
// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter RCLK_SELECT_BANK = 0,
parameter RCLK_SELECT_LANE = "B",
parameter RCLK_SELECT_EDGE = 4'b1111,
parameter GENERATE_DDR_CK_MAP = "0B",
parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002,
parameter USE_PRE_POST_FIFO = "TRUE",
parameter SYNTHESIS = "FALSE",
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PI_SEL_CLK_OFFSET = 6,
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio
// common to all i/o banks
parameter PHY_FOUR_WINDOW_CLOCKS = 63,
parameter PHY_EVENTS_DELAY = 18,
parameter PHY_COUNT_EN = "TRUE",
parameter PHY_SYNC_MODE = "TRUE",
parameter PHY_DISABLE_SEQ_MATCH = "FALSE",
parameter MASTER_PHY_CTL = 0,
// common to instance 0
parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff,
parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_0_LANE_REMAP = 16'h3210,
parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_0_IODELAY_GRP = "IODELAY_MIG",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter NUM_DDR_CK = 1,
parameter PHY_0_DATA_CTL = DATA_CTL_B0,
parameter PHY_0_CMD_OFFSET = 0,
parameter PHY_0_RD_CMD_OFFSET_0 = 0,
parameter PHY_0_RD_CMD_OFFSET_1 = 0,
parameter PHY_0_RD_CMD_OFFSET_2 = 0,
parameter PHY_0_RD_CMD_OFFSET_3 = 0,
parameter PHY_0_RD_DURATION_0 = 0,
parameter PHY_0_RD_DURATION_1 = 0,
parameter PHY_0_RD_DURATION_2 = 0,
parameter PHY_0_RD_DURATION_3 = 0,
parameter PHY_0_WR_CMD_OFFSET_0 = 0,
parameter PHY_0_WR_CMD_OFFSET_1 = 0,
parameter PHY_0_WR_CMD_OFFSET_2 = 0,
parameter PHY_0_WR_CMD_OFFSET_3 = 0,
parameter PHY_0_WR_DURATION_0 = 0,
parameter PHY_0_WR_DURATION_1 = 0,
parameter PHY_0_WR_DURATION_2 = 0,
parameter PHY_0_WR_DURATION_3 = 0,
parameter PHY_0_AO_WRLVL_EN = 0,
parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PHY_0_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE",
parameter PHY_0_A_PI_CLKOUT_DIV = 2,
parameter PHY_0_A_PO_CLKOUT_DIV = 2,
parameter PHY_0_A_BURST_MODE = "TRUE",
parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OCLK_DELAY = 25,
parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE",
parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED",
parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED",
parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00,
parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
// common to instance 1
parameter PHY_1_BITLANES = PHY_0_BITLANES,
parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_1_LANE_REMAP = 16'h3210,
parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_1_DATA_CTL = DATA_CTL_B1,
parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_1_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV,
parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE,
parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC ,
parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
// common to instance 2
parameter PHY_2_BITLANES = PHY_0_BITLANES,
parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_2_LANE_REMAP = 16'h3210,
parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_2_DATA_CTL = DATA_CTL_B2,
parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_2_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV ,
parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE ,
parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC,
parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE",
parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter TCK = 2500,
// local computational use, do not pass down
parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3])
+ (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3])
, // must not delete comma for syntax
parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))),
parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B3 = 0,
parameter HIGHEST_LANE_B4 = 0,
parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))),
parameter LP_DDR_CK_WIDTH = 2,
parameter GENERATE_SIGNAL_SPLIT = "FALSE"
,parameter CKE_ODT_AUX = "FALSE"
)
(
input rst,
input ddr_rst_in_n ,
input phy_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input auxout_clk,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [31:0] phy_ctl_wd,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input phy_ctl_wr,
input if_rst,
input if_empty_def,
input cke_in,
input idelay_ce,
input idelay_ld,
input idelay_inc,
input phyGo,
input input_sink,
output if_a_empty,
(* keep = "true", max_fanout = 3 *) output if_empty /* synthesis syn_maxfan = 3 */,
output if_empty_or,
output if_empty_and,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output pre_data_a_full,
output [HIGHEST_LANE*80-1:0] phy_din,
output phy_ctl_a_full,
(* keep = "true", max_fanout = 3 *) output wire [3:0] phy_ctl_full,
output [HIGHEST_LANE*12-1:0] mem_dq_out,
output [HIGHEST_LANE*12-1:0] mem_dq_ts,
input [HIGHEST_LANE*10-1:0] mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
(* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller
output phy_ctl_ready, // to fabric
output reg rst_out, // to memory
output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
// output rclk,
output mcGo,
output ref_dll_lock,
// calibration signals
input phy_write_calib,
input phy_read_calib,
input [5:0] calib_sel,
input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank
input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs
input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane
input calib_in_common,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input po_counter_read_en,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_phase_locked,
output pi_phase_locked_all,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg pi_dqs_out_of_range
);
wire [7:0] calib_zero_inputs_int ;
wire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ;
//Added the temporary variable for concadination operation
wire [2:0] calib_sel_byte0 ;
wire [2:0] calib_sel_byte1 ;
wire [2:0] calib_sel_byte2 ;
wire [4:0] po_coarse_overflow_w;
wire [4:0] po_fine_overflow_w;
wire [8:0] po_counter_read_val_w[4:0];
wire [4:0] pi_fine_overflow_w;
wire [5:0] pi_counter_read_val_w[4:0];
wire [4:0] pi_dqs_found_w;
wire [4:0] pi_dqs_found_all_w;
wire [4:0] pi_dqs_found_any_w;
wire [4:0] pi_dqs_out_of_range_w;
wire [4:0] pi_phase_locked_w;
wire [4:0] pi_phase_locked_all_w;
wire [4:0] rclk_w;
wire [HIGHEST_BANK-1:0] phy_ctl_ready_w;
wire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0];
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_;
wire [3:0] if_q0;
wire [3:0] if_q1;
wire [3:0] if_q2;
wire [3:0] if_q3;
wire [3:0] if_q4;
wire [7:0] if_q5;
wire [7:0] if_q6;
wire [3:0] if_q7;
wire [3:0] if_q8;
wire [3:0] if_q9;
wire [31:0] _phy_ctl_wd;
wire [3:0] aux_in_[4:1];
wire [3:0] rst_out_w;
wire freq_refclk_split;
wire mem_refclk_split;
wire mem_refclk_div4_split;
wire sync_pulse_split;
wire phy_clk_split0;
wire phy_ctl_clk_split0;
wire [31:0] phy_ctl_wd_split0;
wire phy_ctl_wr_split0;
wire phy_ctl_clk_split1;
wire phy_clk_split1;
wire [31:0] phy_ctl_wd_split1;
wire phy_ctl_wr_split1;
wire [5:0] phy_data_offset_1_split1;
wire phy_ctl_clk_split2;
wire phy_clk_split2;
wire [31:0] phy_ctl_wd_split2;
wire phy_ctl_wr_split2;
wire [5:0] phy_data_offset_2_split2;
wire [HIGHEST_LANE*80-1:0] phy_dout_split0;
wire phy_cmd_wr_en_split0;
wire phy_data_wr_en_split0;
wire phy_rd_en_split0;
wire [HIGHEST_LANE*80-1:0] phy_dout_split1;
wire phy_cmd_wr_en_split1;
wire phy_data_wr_en_split1;
wire phy_rd_en_split1;
wire [HIGHEST_LANE*80-1:0] phy_dout_split2;
wire phy_cmd_wr_en_split2;
wire phy_data_wr_en_split2;
wire phy_rd_en_split2;
wire phy_ctl_mstr_empty;
wire [HIGHEST_BANK-1:0] phy_ctl_empty;
wire _phy_ctl_a_full_f;
wire _phy_ctl_a_empty_f;
wire _phy_ctl_full_f;
wire _phy_ctl_empty_f;
wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p;
wire [HIGHEST_BANK-1:0] _phy_ctl_full_p;
wire [HIGHEST_BANK-1:0] of_ctl_a_full_v;
wire [HIGHEST_BANK-1:0] of_ctl_full_v;
wire [HIGHEST_BANK-1:0] of_data_a_full_v;
wire [HIGHEST_BANK-1:0] of_data_full_v;
wire [HIGHEST_BANK-1:0] pre_data_a_full_v;
wire [HIGHEST_BANK-1:0] if_empty_v;
wire [HIGHEST_BANK-1:0] byte_rd_en_v;
wire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks;
wire [HIGHEST_BANK-1:0] if_empty_or_v;
wire [HIGHEST_BANK-1:0] if_empty_and_v;
wire [HIGHEST_BANK-1:0] if_a_empty_v;
localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4";
localparam IF_SYNCHRONOUS_MODE = "FALSE";
localparam IF_SLOW_WR_CLK = "FALSE";
localparam IF_SLOW_RD_CLK = "FALSE";
localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE";
localparam RCLK_NEG_EDGE = 3'b000;
localparam RCLK_POS_EDGE = 3'b111;
localparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF;
localparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF;
localparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF;
// hi, lo positions for data offset field, MIG doesn't allow defines
localparam PC_DATA_OFFSET_RANGE_HI = 22;
localparam PC_DATA_OFFSET_RANGE_LO = 17;
/* Phaser_In Output source coding table
"PHASE_REF" : 4'b0000;
"DELAYED_MEM_REF" : 4'b0101;
"DELAYED_PHASE_REF" : 4'b0011;
"DELAYED_REF" : 4'b0001;
"FREQ_REF" : 4'b1000;
"MEM_REF" : 4'b0010;
*/
localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF";
localparam DDR_TCK = TCK;
localparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
localparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0;
localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line
localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line
localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta
/*
Intrinsic delay of Phaser In Stage 1
@3300ps - 1.939ns - 58.8%
@2500ps - 1.657ns - 66.3%
@1875ps - 1.263ns - 67.4%
@1500ps - 1.021ns - 68.1%
@1250ps - 0.868ns - 69.4%
@1072ps - 0.752ns - 70.1%
@938ps - 0.667ns - 71.1%
*/
// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0
// Fraction of a full DDR_TCK period
localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 :
((DDR_TCK < 1005) ? 0.667 :
(DDR_TCK < 1160) ? 0.752 :
(DDR_TCK < 1375) ? 0.868 :
(DDR_TCK < 1685) ? 1.021 :
(DDR_TCK < 2185) ? 1.263 :
(DDR_TCK < 2900) ? 1.657 :
(DDR_TCK < 3100) ? 1.771 : 1.939)*1000;
/*
Intrinsic delay of Phaser In Stage 2
@3300ps - 0.912ns - 27.6% - single tap - 13ps
@3000ps - 0.848ns - 28.3% - single tap - 11ps
@2500ps - 1.264ns - 50.6% - single tap - 19ps
@1875ps - 1.000ns - 53.3% - single tap - 15ps
@1500ps - 0.848ns - 56.5% - single tap - 11ps
@1250ps - 0.736ns - 58.9% - single tap - 9ps
@1072ps - 0.664ns - 61.9% - single tap - 8ps
@938ps - 0.608ns - 64.8% - single tap - 7ps
*/
// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps)
localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor
/*
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1
@3300ps - 1.294ns - 39.2%
@2500ps - 1.294ns - 51.8%
@1875ps - 1.030ns - 54.9%
@1500ps - 0.878ns - 58.5%
@1250ps - 0.766ns - 61.3%
@1072ps - 0.694ns - 64.7%
@938ps - 0.638ns - 68.0%
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0
@3300ps - 2.084ns - 63.2% - single tap - 20ps
@2500ps - 2.084ns - 81.9% - single tap - 19ps
@1875ps - 1.676ns - 89.4% - single tap - 15ps
@1500ps - 1.444ns - 96.3% - single tap - 11ps
@1250ps - 1.276ns - 102.1% - single tap - 9ps
@1072ps - 1.164ns - 108.6% - single tap - 8ps
@938ps - 1.076ns - 114.7% - single tap - 7ps
*/
// Fraction of a full DDR_TCK period
localparam real PO_STG1_INTRINSIC_DELAY = 0;
localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor
localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor
localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY +
(PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY);
// When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can
// go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this,
// a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments
// to the stage 2 delay can be made after reset is removed.
localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PO_CIRC_BUF_META_ZONE = 200.0;
localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0;
localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK;
// If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold
// If it is not more than the threshold than we must push the delay after the clock period plus a guardband.
//A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated.
localparam integer PO_CIRC_BUF_DELAY = 60;
//localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 :
// (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE :
// (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE;
localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE;
localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY;
localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY;
localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE);
localparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi
// The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path
// of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the
// oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment
// is within the range of the stage 2 delay line in the Phaser_In.
localparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY);
localparam integer PO_DELAY_INT = PO_DELAY;
localparam real PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK);
// if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is
// if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge.
// note that in this case PI_OFFSET is negative so invert before subtracting.
localparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0
? PI_OFFSET
: ((-PI_OFFSET) < DDR_TCK/2) ?
(DDR_TCK/2 - (- PI_OFFSET)) :
(DDR_TCK - (- PI_OFFSET)) ;
localparam real PI_STG2_DELAY =
(PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ?
PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND);
localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE;
localparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE));
localparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
wire _phy_clk;
wire [2:0] mcGo_w;
wire [HIGHEST_BANK-1:0] ref_dll_lock_w;
reg [15:0] mcGo_r;
assign ref_dll_lock = & ref_dll_lock_w;
initial begin
if ( SYNTHESIS == "FALSE" ) begin
$display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1);
$display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1);
$display("%m : HIGHEST_BANK = %d", HIGHEST_BANK);
$display("%m : FREQ_REF_PERIOD = %0.2f ", FREQ_REF_PERIOD);
$display("%m : DDR_TCK = %0d ", DDR_TCK);
$display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE);
$display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY);
$display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET);
$display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE);
$display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY);
$display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY);
$display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY);
$display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY);
$display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY);
$display("%m : PO_DELAY = %0.2f ", PO_DELAY);
$display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY);
$display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY);
$display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY);
$display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY);
$display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY);
$display("%m : PI_MAX_STG2_DELAY = %0.2f ", PI_MAX_STG2_DELAY);
$display("%m : PI_OFFSET = %0.2f ", PI_OFFSET);
if ( PI_OFFSET < 0) $display("%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used.");
$display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY);
$display("%m :PI_STG2_DELAY_CAND = %0.2f ",PI_STG2_DELAY_CAND);
$display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY);
$display("%m : RCLK_SELECT_EDGE = %0b ", LP_RCLK_SELECT_EDGE);
end // SYNTHESIS
if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display("WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY);
end
assign sync_pulse_split = sync_pulse;
assign mem_refclk_split = mem_refclk;
assign freq_refclk_split = freq_refclk;
assign mem_refclk_div4_split = mem_refclk_div4;
assign phy_ctl_clk_split0 = _phy_clk;
assign phy_ctl_wd_split0 = phy_ctl_wd;
assign phy_ctl_wr_split0 = phy_ctl_wr;
assign phy_clk_split0 = phy_clk;
assign phy_cmd_wr_en_split0 = phy_cmd_wr_en;
assign phy_data_wr_en_split0 = phy_data_wr_en;
assign phy_rd_en_split0 = phy_rd_en;
assign phy_dout_split0 = phy_dout;
assign phy_ctl_clk_split1 = phy_clk;
assign phy_ctl_wd_split1 = phy_ctl_wd;
assign phy_data_offset_1_split1 = data_offset_1;
assign phy_ctl_wr_split1 = phy_ctl_wr;
assign phy_clk_split1 = phy_clk;
assign phy_cmd_wr_en_split1 = phy_cmd_wr_en;
assign phy_data_wr_en_split1 = phy_data_wr_en;
assign phy_rd_en_split1 = phy_rd_en;
assign phy_dout_split1 = phy_dout;
assign phy_ctl_clk_split2 = phy_clk;
assign phy_ctl_wd_split2 = phy_ctl_wd;
assign phy_data_offset_2_split2 = data_offset_2;
assign phy_ctl_wr_split2 = phy_ctl_wr;
assign phy_clk_split2 = phy_clk;
assign phy_cmd_wr_en_split2 = phy_cmd_wr_en;
assign phy_data_wr_en_split2 = phy_data_wr_en;
assign phy_rd_en_split2 = phy_rd_en;
assign phy_dout_split2 = phy_dout;
// these wires are needed to coerce correct synthesis
// the synthesizer did not always see the widths of the
// parameters as 4 bits.
wire [3:0] blb0 = BYTE_LANES_B0;
wire [3:0] blb1 = BYTE_LANES_B1;
wire [3:0] blb2 = BYTE_LANES_B2;
wire [3:0] dcb0 = DATA_CTL_B0;
wire [3:0] dcb1 = DATA_CTL_B1;
wire [3:0] dcb2 = DATA_CTL_B2;
assign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0});
assign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0});
assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0];
assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs};
//Added to remove concadination in the instantiation
assign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ;
assign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ;
assign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ;
assign calib_zero_lanes_int = calib_zero_lanes;
assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0];
assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL];
assign of_ctl_a_full = |of_ctl_a_full_v;
assign of_ctl_full = |of_ctl_full_v;
assign of_data_a_full = |of_data_a_full_v;
assign of_data_full = |of_data_full_v;
assign pre_data_a_full= |pre_data_a_full_v;
// if if_empty_def == 1, empty is asserted only if all are empty;
// this allows the user to detect a skewed fifo depth and self-clear
// if desired. It avoids a reset to clear the flags.
assign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v;
assign if_empty_or = |if_empty_or_v;
assign if_empty_and = &if_empty_and_v;
assign if_a_empty = |if_a_empty_v;
generate
genvar i;
for (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen
case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff)
16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
default : initial $display("ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) ", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff ));
endcase
end
endgenerate
//assign rclk = rclk_w[RCLK_SELECT_BANK];
reg rst_auxout;
reg rst_auxout_r;
reg rst_auxout_rr;
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout_r <= #(1) 1'b1;
rst_auxout_rr <= #(1) 1'b1;
end
else begin
rst_auxout_r <= #(1) rst;
rst_auxout_rr <= #(1) rst_auxout_r;
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
else begin
always @(negedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
localparam L_RESET_SELECT_BANK =
(BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK;
always @(*) begin
rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n;
end
always @(posedge phy_clk or posedge rst) begin
if ( rst)
mcGo_r <= #(1) 0;
else
mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w;
end
assign mcGo = mcGo_r[15];
generate
// this is an optional 1 clock delay to add latency to the phy_control programming path
if (PHYCTL_CMD_FIFO == "TRUE") begin : cmd_fifo_soft
reg [31:0] phy_wd_reg = 0;
reg [3:0] aux_in1_reg = 0;
reg [3:0] aux_in2_reg = 0;
reg sfifo_ready = 0;
assign _phy_ctl_wd = phy_wd_reg;
assign aux_in_[1] = aux_in1_reg;
assign aux_in_[2] = aux_in2_reg;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[1] = |_phy_ctl_full_p;
assign phy_ctl_full[2] = |_phy_ctl_full_p;
assign phy_ctl_full[3] = |_phy_ctl_full_p;
assign _phy_clk = phy_clk;
always @(posedge phy_clk) begin
phy_wd_reg <= #1 phy_ctl_wd;
aux_in1_reg <= #1 aux_in_1;
aux_in2_reg <= #1 aux_in_2;
sfifo_ready <= #1 phy_ctl_wr;
end
end
else if (PHYCTL_CMD_FIFO == "FALSE") begin
assign _phy_ctl_wd = phy_ctl_wd;
assign aux_in_[1] = aux_in_1;
assign aux_in_[2] = aux_in_2;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[3:1] = 3'b000;
assign _phy_clk = phy_clk;
end
endgenerate
// instance of four-lane phy
generate
if (HIGHEST_BANK == 3) begin : banks_3
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]};
end
else if (HIGHEST_BANK == 2) begin : banks_2
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1};
end
else begin : banks_1
assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1};
end
if ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */
.DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY),
.BITLANES (PHY_0_BITLANES),
.BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK),
.LAST_BANK (PHY_0_IS_LAST_BANK),
.LANE_REMAP (PHY_0_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_0_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_0_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_0_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_0_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_0_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_0_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_0_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_0_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_0_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split0),
.phy_ctl_clk (phy_ctl_clk_split0),
.phy_ctl_wd (phy_ctl_wd_split0),
.data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]),
.phy_ctl_wr (phy_ctl_wr_split0),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]),
.phy_cmd_wr_en (phy_cmd_wr_en_split0),
.phy_data_wr_en (phy_data_wr_en_split0),
.phy_rd_en (phy_rd_en_split0),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[0]),
.rclk (),
.rst_out (rst_out_w[0]),
.mcGo (mcGo_w[0]),
.ref_dll_lock (ref_dll_lock_w[0]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]),
.if_a_empty (if_a_empty_v[0]),
.if_empty (if_empty_v[0]),
.byte_rd_en (byte_rd_en_v[0]),
.if_empty_or (if_empty_or_v[0]),
.if_empty_and (if_empty_and_v[0]),
.of_ctl_a_full (of_ctl_a_full_v[0]),
.of_data_a_full (of_data_a_full_v[0]),
.of_ctl_full (of_ctl_full_v[0]),
.of_data_full (of_data_full_v[0]),
.pre_data_a_full (pre_data_a_full_v[0]),
.phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]),
.phy_ctl_a_full (_phy_ctl_a_full_p[0]),
.phy_ctl_full (_phy_ctl_full_p[0]),
.phy_ctl_empty (phy_ctl_empty[0]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]),
.aux_out (aux_out_[3:0]),
.phy_ctl_ready (phy_ctl_ready_w[0]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte0),
.calib_zero_ctrl (calib_zero_ctrl[0]),
.calib_zero_lanes (calib_zero_lanes_int[3:0]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[0]),
.po_fine_enable (po_fine_enable[0]),
.po_fine_inc (po_fine_inc[0]),
.po_coarse_inc (po_coarse_inc[0]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[0]),
.po_fine_overflow (po_fine_overflow_w[0]),
.po_counter_read_val (po_counter_read_val_w[0]),
.pi_rst_dqs_find (pi_rst_dqs_find[0]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[0]),
.pi_counter_read_val (pi_counter_read_val_w[0]),
.pi_dqs_found (pi_dqs_found_w[0]),
.pi_dqs_found_all (pi_dqs_found_all_w[0]),
.pi_dqs_found_any (pi_dqs_found_any_w[0]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]),
.pi_phase_locked (pi_phase_locked_w[0]),
.pi_phase_locked_all (pi_phase_locked_all_w[0])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[0] <= #100 0;
aux_out[2] <= #100 0;
end
else begin
aux_out[0] <= #100 aux_out_[0];
aux_out[2] <= #100 aux_out_[2];
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
end
else begin
if ( HIGHEST_BANK > 0) begin
assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0;
assign _phy_ctl_a_full_p[0] = 0;
assign of_ctl_a_full_v[0] = 0;
assign of_ctl_full_v[0] = 0;
assign of_data_a_full_v[0] = 0;
assign of_data_full_v[0] = 0;
assign pre_data_a_full_v[0] = 0;
assign if_empty_v[0] = 0;
assign byte_rd_en_v[0] = 1;
always @(*)
aux_out[3:0] = 0;
end
assign pi_dqs_found_w[0] = 1;
assign pi_dqs_found_all_w[0] = 1;
assign pi_dqs_found_any_w[0] = 0;
assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_out_of_range_w[0] = 0;
assign pi_phase_locked_w[0] = 1;
assign po_fine_overflow_w[0] = 0;
assign po_coarse_overflow_w[0] = 0;
assign po_fine_overflow_w[0] = 0;
assign pi_fine_overflow_w[0] = 0;
assign po_counter_read_val_w[0] = 0;
assign pi_counter_read_val_w[0] = 0;
assign mcGo_w[0] = 1;
if ( RCLK_SELECT_BANK == 0)
always @(*)
aux_out[3:0] = 0;
end
if ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */
.DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY),
.BITLANES (PHY_1_BITLANES),
.BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK),
.LAST_BANK (PHY_1_IS_LAST_BANK ),
.LANE_REMAP (PHY_1_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_1_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_1_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_1_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_1_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_1_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_1_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_1_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_1_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_1_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_1_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_1_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_1_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_1_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split1),
.phy_ctl_clk (phy_ctl_clk_split1),
.phy_ctl_wd (phy_ctl_wd_split1),
.data_offset (phy_data_offset_1_split1),
.phy_ctl_wr (phy_ctl_wr_split1),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]),
.phy_cmd_wr_en (phy_cmd_wr_en_split1),
.phy_data_wr_en (phy_data_wr_en_split1),
.phy_rd_en (phy_rd_en_split1),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[1]),
.rclk (),
.rst_out (rst_out_w[1]),
.mcGo (mcGo_w[1]),
.ref_dll_lock (ref_dll_lock_w[1]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]),
.if_a_empty (if_a_empty_v[1]),
.if_empty (if_empty_v[1]),
.byte_rd_en (byte_rd_en_v[1]),
.if_empty_or (if_empty_or_v[1]),
.if_empty_and (if_empty_and_v[1]),
.of_ctl_a_full (of_ctl_a_full_v[1]),
.of_data_a_full (of_data_a_full_v[1]),
.of_ctl_full (of_ctl_full_v[1]),
.of_data_full (of_data_full_v[1]),
.pre_data_a_full (pre_data_a_full_v[1]),
.phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]),
.phy_ctl_a_full (_phy_ctl_a_full_p[1]),
.phy_ctl_full (_phy_ctl_full_p[1]),
.phy_ctl_empty (phy_ctl_empty[1]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]),
.aux_out (aux_out_[7:4]),
.phy_ctl_ready (phy_ctl_ready_w[1]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte1),
.calib_zero_ctrl (calib_zero_ctrl[1]),
.calib_zero_lanes (calib_zero_lanes_int[7:4]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[1]),
.po_fine_enable (po_fine_enable[1]),
.po_fine_inc (po_fine_inc[1]),
.po_coarse_inc (po_coarse_inc[1]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[1]),
.po_fine_overflow (po_fine_overflow_w[1]),
.po_counter_read_val (po_counter_read_val_w[1]),
.pi_rst_dqs_find (pi_rst_dqs_find[1]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[1]),
.pi_counter_read_val (pi_counter_read_val_w[1]),
.pi_dqs_found (pi_dqs_found_w[1]),
.pi_dqs_found_all (pi_dqs_found_all_w[1]),
.pi_dqs_found_any (pi_dqs_found_any_w[1]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]),
.pi_phase_locked (pi_phase_locked_w[1]),
.pi_phase_locked_all (pi_phase_locked_all_w[1])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[4] <= #100 0;
aux_out[6] <= #100 0;
end
else begin
aux_out[4] <= #100 aux_out_[4];
aux_out[6] <= #100 aux_out_[6];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
end
else begin
if ( HIGHEST_BANK > 1) begin
assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0;
assign _phy_ctl_a_full_p[1] = 0;
assign of_ctl_a_full_v[1] = 0;
assign of_ctl_full_v[1] = 0;
assign of_data_a_full_v[1] = 0;
assign of_data_full_v[1] = 0;
assign pre_data_a_full_v[1] = 0;
assign if_empty_v[1] = 0;
assign byte_rd_en_v[1] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
always @(*)
aux_out[7:4] = 0;
end
assign pi_dqs_found_w[1] = 1;
assign pi_dqs_found_all_w[1] = 1;
assign pi_dqs_found_any_w[1] = 0;
assign pi_dqs_out_of_range_w[1] = 0;
assign pi_phase_locked_w[1] = 1;
assign po_coarse_overflow_w[1] = 0;
assign po_fine_overflow_w[1] = 0;
assign pi_fine_overflow_w[1] = 0;
assign po_counter_read_val_w[1] = 0;
assign pi_counter_read_val_w[1] = 0;
assign mcGo_w[1] = 1;
end
if ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */
.DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY),
.BITLANES (PHY_2_BITLANES),
.BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK),
.LAST_BANK (PHY_2_IS_LAST_BANK ),
.LANE_REMAP (PHY_2_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_2_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_2_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_2_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_2_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_2_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_2_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_2_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_2_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_2_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_2_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_2_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_2_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_2_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split2),
.phy_ctl_clk (phy_ctl_clk_split2),
.phy_ctl_wd (phy_ctl_wd_split2),
.data_offset (phy_data_offset_2_split2),
.phy_ctl_wr (phy_ctl_wr_split2),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]),
.phy_cmd_wr_en (phy_cmd_wr_en_split2),
.phy_data_wr_en (phy_data_wr_en_split2),
.phy_rd_en (phy_rd_en_split2),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[2]),
.rclk (),
.rst_out (rst_out_w[2]),
.mcGo (mcGo_w[2]),
.ref_dll_lock (ref_dll_lock_w[2]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]),
.if_a_empty (if_a_empty_v[2]),
.if_empty (if_empty_v[2]),
.byte_rd_en (byte_rd_en_v[2]),
.if_empty_or (if_empty_or_v[2]),
.if_empty_and (if_empty_and_v[2]),
.of_ctl_a_full (of_ctl_a_full_v[2]),
.of_data_a_full (of_data_a_full_v[2]),
.of_ctl_full (of_ctl_full_v[2]),
.of_data_full (of_data_full_v[2]),
.pre_data_a_full (pre_data_a_full_v[2]),
.phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]),
.phy_ctl_a_full (_phy_ctl_a_full_p[2]),
.phy_ctl_full (_phy_ctl_full_p[2]),
.phy_ctl_empty (phy_ctl_empty[2]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]),
.aux_out (aux_out_[11:8]),
.phy_ctl_ready (phy_ctl_ready_w[2]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte2),
.calib_zero_ctrl (calib_zero_ctrl[2]),
.calib_zero_lanes (calib_zero_lanes_int[11:8]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[2]),
.po_fine_enable (po_fine_enable[2]),
.po_fine_inc (po_fine_inc[2]),
.po_coarse_inc (po_coarse_inc[2]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[2]),
.po_fine_overflow (po_fine_overflow_w[2]),
.po_counter_read_val (po_counter_read_val_w[2]),
.pi_rst_dqs_find (pi_rst_dqs_find[2]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[2]),
.pi_counter_read_val (pi_counter_read_val_w[2]),
.pi_dqs_found (pi_dqs_found_w[2]),
.pi_dqs_found_all (pi_dqs_found_all_w[2]),
.pi_dqs_found_any (pi_dqs_found_any_w[2]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]),
.pi_phase_locked (pi_phase_locked_w[2]),
.pi_phase_locked_all (pi_phase_locked_all_w[2])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[8] <= #100 0;
aux_out[10] <= #100 0;
end
else begin
aux_out[8] <= #100 aux_out_[8];
aux_out[10] <= #100 aux_out_[10];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
end
else begin
if ( HIGHEST_BANK > 2) begin
assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0;
assign _phy_ctl_a_full_p[2] = 0;
assign of_ctl_a_full_v[2] = 0;
assign of_ctl_full_v[2] = 0;
assign of_data_a_full_v[2] = 0;
assign of_data_full_v[2] = 0;
assign pre_data_a_full_v[2] = 0;
assign if_empty_v[2] = 0;
assign byte_rd_en_v[2] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
always @(*)
aux_out[11:8] = 0;
end
assign pi_dqs_found_w[2] = 1;
assign pi_dqs_found_all_w[2] = 1;
assign pi_dqs_found_any_w[2] = 0;
assign pi_dqs_out_of_range_w[2] = 0;
assign pi_phase_locked_w[2] = 1;
assign po_coarse_overflow_w[2] = 0;
assign po_fine_overflow_w[2] = 0;
assign po_counter_read_val_w[2] = 0;
assign pi_counter_read_val_w[2] = 0;
assign mcGo_w[2] = 1;
end
endgenerate
generate
// for single bank , emit an extra phaser_in to generate rclk
// so that auxout can be placed in another region
// if desired
if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0)
begin : phaser_in_rclk
localparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY;
PHASER_IN_PHY #(
.BURST_MODE ( PHY_0_A_BURST_MODE),
.CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV),
.FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.FINE_DELAY ( L_EXTRA_PI_FINE_DELAY),
.OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC)
) phaser_in_rclk (
.DQSFOUND (),
.DQSOUTOFRANGE (),
.FINEOVERFLOW (),
.PHASELOCKED (),
.ISERDESRST (),
.ICLKDIV (),
.ICLK (),
.COUNTERREADVAL (),
.RCLK (),
.WRENABLE (),
.BURSTPENDINGPHY (),
.ENCALIBPHY (),
.FINEENABLE (0),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (0),
.PHASEREFCLK (),
.RSTDQSFIND (0),
.RST (rst),
.FINEINC (),
.COUNTERLOADEN (),
.COUNTERREADEN (),
.COUNTERLOADVAL (),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
end
endgenerate
always @(*) begin
case (calib_sel[5:3])
3'b000: begin
po_coarse_overflow = po_coarse_overflow_w[0];
po_fine_overflow = po_fine_overflow_w[0];
po_counter_read_val = po_counter_read_val_w[0];
pi_fine_overflow = pi_fine_overflow_w[0];
pi_counter_read_val = pi_counter_read_val_w[0];
pi_phase_locked = pi_phase_locked_w[0];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[0];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[0];
end
3'b001: begin
po_coarse_overflow = po_coarse_overflow_w[1];
po_fine_overflow = po_fine_overflow_w[1];
po_counter_read_val = po_counter_read_val_w[1];
pi_fine_overflow = pi_fine_overflow_w[1];
pi_counter_read_val = pi_counter_read_val_w[1];
pi_phase_locked = pi_phase_locked_w[1];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[1];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[1];
end
3'b010: begin
po_coarse_overflow = po_coarse_overflow_w[2];
po_fine_overflow = po_fine_overflow_w[2];
po_counter_read_val = po_counter_read_val_w[2];
pi_fine_overflow = pi_fine_overflow_w[2];
pi_counter_read_val = pi_counter_read_val_w[2];
pi_phase_locked = pi_phase_locked_w[2];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[2];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[2];
end
default: begin
po_coarse_overflow = 0;
po_fine_overflow = 0;
po_counter_read_val = 0;
pi_fine_overflow = 0;
pi_counter_read_val = 0;
pi_phase_locked = 0;
pi_dqs_found = 0;
pi_dqs_out_of_range = 0;
end
endcase
end
endmodule // mc_phy
|
/***********************************************************
-- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable wrapper instantiating
// up to 5 memory banks of 4-lane phy primitives. There
// There are always 2 control banks leaving 18 lanes for data.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_mc_phy
#(
// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter RCLK_SELECT_BANK = 0,
parameter RCLK_SELECT_LANE = "B",
parameter RCLK_SELECT_EDGE = 4'b1111,
parameter GENERATE_DDR_CK_MAP = "0B",
parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002,
parameter USE_PRE_POST_FIFO = "TRUE",
parameter SYNTHESIS = "FALSE",
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PI_SEL_CLK_OFFSET = 6,
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio
// common to all i/o banks
parameter PHY_FOUR_WINDOW_CLOCKS = 63,
parameter PHY_EVENTS_DELAY = 18,
parameter PHY_COUNT_EN = "TRUE",
parameter PHY_SYNC_MODE = "TRUE",
parameter PHY_DISABLE_SEQ_MATCH = "FALSE",
parameter MASTER_PHY_CTL = 0,
// common to instance 0
parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff,
parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_0_LANE_REMAP = 16'h3210,
parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_0_IODELAY_GRP = "IODELAY_MIG",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter NUM_DDR_CK = 1,
parameter PHY_0_DATA_CTL = DATA_CTL_B0,
parameter PHY_0_CMD_OFFSET = 0,
parameter PHY_0_RD_CMD_OFFSET_0 = 0,
parameter PHY_0_RD_CMD_OFFSET_1 = 0,
parameter PHY_0_RD_CMD_OFFSET_2 = 0,
parameter PHY_0_RD_CMD_OFFSET_3 = 0,
parameter PHY_0_RD_DURATION_0 = 0,
parameter PHY_0_RD_DURATION_1 = 0,
parameter PHY_0_RD_DURATION_2 = 0,
parameter PHY_0_RD_DURATION_3 = 0,
parameter PHY_0_WR_CMD_OFFSET_0 = 0,
parameter PHY_0_WR_CMD_OFFSET_1 = 0,
parameter PHY_0_WR_CMD_OFFSET_2 = 0,
parameter PHY_0_WR_CMD_OFFSET_3 = 0,
parameter PHY_0_WR_DURATION_0 = 0,
parameter PHY_0_WR_DURATION_1 = 0,
parameter PHY_0_WR_DURATION_2 = 0,
parameter PHY_0_WR_DURATION_3 = 0,
parameter PHY_0_AO_WRLVL_EN = 0,
parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PHY_0_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE",
parameter PHY_0_A_PI_CLKOUT_DIV = 2,
parameter PHY_0_A_PO_CLKOUT_DIV = 2,
parameter PHY_0_A_BURST_MODE = "TRUE",
parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OCLK_DELAY = 25,
parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE",
parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED",
parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED",
parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00,
parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
// common to instance 1
parameter PHY_1_BITLANES = PHY_0_BITLANES,
parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_1_LANE_REMAP = 16'h3210,
parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_1_DATA_CTL = DATA_CTL_B1,
parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_1_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV,
parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE,
parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC ,
parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
// common to instance 2
parameter PHY_2_BITLANES = PHY_0_BITLANES,
parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_2_LANE_REMAP = 16'h3210,
parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_2_DATA_CTL = DATA_CTL_B2,
parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_2_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV ,
parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE ,
parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC,
parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE",
parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter TCK = 2500,
// local computational use, do not pass down
parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3])
+ (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3])
, // must not delete comma for syntax
parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))),
parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B3 = 0,
parameter HIGHEST_LANE_B4 = 0,
parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))),
parameter LP_DDR_CK_WIDTH = 2,
parameter GENERATE_SIGNAL_SPLIT = "FALSE"
,parameter CKE_ODT_AUX = "FALSE"
)
(
input rst,
input ddr_rst_in_n ,
input phy_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input auxout_clk,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [31:0] phy_ctl_wd,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input phy_ctl_wr,
input if_rst,
input if_empty_def,
input cke_in,
input idelay_ce,
input idelay_ld,
input idelay_inc,
input phyGo,
input input_sink,
output if_a_empty,
(* keep = "true", max_fanout = 3 *) output if_empty /* synthesis syn_maxfan = 3 */,
output if_empty_or,
output if_empty_and,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output pre_data_a_full,
output [HIGHEST_LANE*80-1:0] phy_din,
output phy_ctl_a_full,
(* keep = "true", max_fanout = 3 *) output wire [3:0] phy_ctl_full,
output [HIGHEST_LANE*12-1:0] mem_dq_out,
output [HIGHEST_LANE*12-1:0] mem_dq_ts,
input [HIGHEST_LANE*10-1:0] mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
(* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller
output phy_ctl_ready, // to fabric
output reg rst_out, // to memory
output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
// output rclk,
output mcGo,
output ref_dll_lock,
// calibration signals
input phy_write_calib,
input phy_read_calib,
input [5:0] calib_sel,
input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank
input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs
input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane
input calib_in_common,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input po_counter_read_en,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_phase_locked,
output pi_phase_locked_all,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg pi_dqs_out_of_range
);
wire [7:0] calib_zero_inputs_int ;
wire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ;
//Added the temporary variable for concadination operation
wire [2:0] calib_sel_byte0 ;
wire [2:0] calib_sel_byte1 ;
wire [2:0] calib_sel_byte2 ;
wire [4:0] po_coarse_overflow_w;
wire [4:0] po_fine_overflow_w;
wire [8:0] po_counter_read_val_w[4:0];
wire [4:0] pi_fine_overflow_w;
wire [5:0] pi_counter_read_val_w[4:0];
wire [4:0] pi_dqs_found_w;
wire [4:0] pi_dqs_found_all_w;
wire [4:0] pi_dqs_found_any_w;
wire [4:0] pi_dqs_out_of_range_w;
wire [4:0] pi_phase_locked_w;
wire [4:0] pi_phase_locked_all_w;
wire [4:0] rclk_w;
wire [HIGHEST_BANK-1:0] phy_ctl_ready_w;
wire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0];
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_;
wire [3:0] if_q0;
wire [3:0] if_q1;
wire [3:0] if_q2;
wire [3:0] if_q3;
wire [3:0] if_q4;
wire [7:0] if_q5;
wire [7:0] if_q6;
wire [3:0] if_q7;
wire [3:0] if_q8;
wire [3:0] if_q9;
wire [31:0] _phy_ctl_wd;
wire [3:0] aux_in_[4:1];
wire [3:0] rst_out_w;
wire freq_refclk_split;
wire mem_refclk_split;
wire mem_refclk_div4_split;
wire sync_pulse_split;
wire phy_clk_split0;
wire phy_ctl_clk_split0;
wire [31:0] phy_ctl_wd_split0;
wire phy_ctl_wr_split0;
wire phy_ctl_clk_split1;
wire phy_clk_split1;
wire [31:0] phy_ctl_wd_split1;
wire phy_ctl_wr_split1;
wire [5:0] phy_data_offset_1_split1;
wire phy_ctl_clk_split2;
wire phy_clk_split2;
wire [31:0] phy_ctl_wd_split2;
wire phy_ctl_wr_split2;
wire [5:0] phy_data_offset_2_split2;
wire [HIGHEST_LANE*80-1:0] phy_dout_split0;
wire phy_cmd_wr_en_split0;
wire phy_data_wr_en_split0;
wire phy_rd_en_split0;
wire [HIGHEST_LANE*80-1:0] phy_dout_split1;
wire phy_cmd_wr_en_split1;
wire phy_data_wr_en_split1;
wire phy_rd_en_split1;
wire [HIGHEST_LANE*80-1:0] phy_dout_split2;
wire phy_cmd_wr_en_split2;
wire phy_data_wr_en_split2;
wire phy_rd_en_split2;
wire phy_ctl_mstr_empty;
wire [HIGHEST_BANK-1:0] phy_ctl_empty;
wire _phy_ctl_a_full_f;
wire _phy_ctl_a_empty_f;
wire _phy_ctl_full_f;
wire _phy_ctl_empty_f;
wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p;
wire [HIGHEST_BANK-1:0] _phy_ctl_full_p;
wire [HIGHEST_BANK-1:0] of_ctl_a_full_v;
wire [HIGHEST_BANK-1:0] of_ctl_full_v;
wire [HIGHEST_BANK-1:0] of_data_a_full_v;
wire [HIGHEST_BANK-1:0] of_data_full_v;
wire [HIGHEST_BANK-1:0] pre_data_a_full_v;
wire [HIGHEST_BANK-1:0] if_empty_v;
wire [HIGHEST_BANK-1:0] byte_rd_en_v;
wire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks;
wire [HIGHEST_BANK-1:0] if_empty_or_v;
wire [HIGHEST_BANK-1:0] if_empty_and_v;
wire [HIGHEST_BANK-1:0] if_a_empty_v;
localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4";
localparam IF_SYNCHRONOUS_MODE = "FALSE";
localparam IF_SLOW_WR_CLK = "FALSE";
localparam IF_SLOW_RD_CLK = "FALSE";
localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE";
localparam RCLK_NEG_EDGE = 3'b000;
localparam RCLK_POS_EDGE = 3'b111;
localparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF;
localparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF;
localparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF;
// hi, lo positions for data offset field, MIG doesn't allow defines
localparam PC_DATA_OFFSET_RANGE_HI = 22;
localparam PC_DATA_OFFSET_RANGE_LO = 17;
/* Phaser_In Output source coding table
"PHASE_REF" : 4'b0000;
"DELAYED_MEM_REF" : 4'b0101;
"DELAYED_PHASE_REF" : 4'b0011;
"DELAYED_REF" : 4'b0001;
"FREQ_REF" : 4'b1000;
"MEM_REF" : 4'b0010;
*/
localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF";
localparam DDR_TCK = TCK;
localparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
localparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0;
localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line
localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line
localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta
/*
Intrinsic delay of Phaser In Stage 1
@3300ps - 1.939ns - 58.8%
@2500ps - 1.657ns - 66.3%
@1875ps - 1.263ns - 67.4%
@1500ps - 1.021ns - 68.1%
@1250ps - 0.868ns - 69.4%
@1072ps - 0.752ns - 70.1%
@938ps - 0.667ns - 71.1%
*/
// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0
// Fraction of a full DDR_TCK period
localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 :
((DDR_TCK < 1005) ? 0.667 :
(DDR_TCK < 1160) ? 0.752 :
(DDR_TCK < 1375) ? 0.868 :
(DDR_TCK < 1685) ? 1.021 :
(DDR_TCK < 2185) ? 1.263 :
(DDR_TCK < 2900) ? 1.657 :
(DDR_TCK < 3100) ? 1.771 : 1.939)*1000;
/*
Intrinsic delay of Phaser In Stage 2
@3300ps - 0.912ns - 27.6% - single tap - 13ps
@3000ps - 0.848ns - 28.3% - single tap - 11ps
@2500ps - 1.264ns - 50.6% - single tap - 19ps
@1875ps - 1.000ns - 53.3% - single tap - 15ps
@1500ps - 0.848ns - 56.5% - single tap - 11ps
@1250ps - 0.736ns - 58.9% - single tap - 9ps
@1072ps - 0.664ns - 61.9% - single tap - 8ps
@938ps - 0.608ns - 64.8% - single tap - 7ps
*/
// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps)
localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor
/*
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1
@3300ps - 1.294ns - 39.2%
@2500ps - 1.294ns - 51.8%
@1875ps - 1.030ns - 54.9%
@1500ps - 0.878ns - 58.5%
@1250ps - 0.766ns - 61.3%
@1072ps - 0.694ns - 64.7%
@938ps - 0.638ns - 68.0%
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0
@3300ps - 2.084ns - 63.2% - single tap - 20ps
@2500ps - 2.084ns - 81.9% - single tap - 19ps
@1875ps - 1.676ns - 89.4% - single tap - 15ps
@1500ps - 1.444ns - 96.3% - single tap - 11ps
@1250ps - 1.276ns - 102.1% - single tap - 9ps
@1072ps - 1.164ns - 108.6% - single tap - 8ps
@938ps - 1.076ns - 114.7% - single tap - 7ps
*/
// Fraction of a full DDR_TCK period
localparam real PO_STG1_INTRINSIC_DELAY = 0;
localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor
localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor
localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY +
(PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY);
// When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can
// go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this,
// a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments
// to the stage 2 delay can be made after reset is removed.
localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PO_CIRC_BUF_META_ZONE = 200.0;
localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0;
localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK;
// If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold
// If it is not more than the threshold than we must push the delay after the clock period plus a guardband.
//A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated.
localparam integer PO_CIRC_BUF_DELAY = 60;
//localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 :
// (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE :
// (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE;
localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE;
localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY;
localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY;
localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE);
localparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi
// The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path
// of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the
// oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment
// is within the range of the stage 2 delay line in the Phaser_In.
localparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY);
localparam integer PO_DELAY_INT = PO_DELAY;
localparam real PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK);
// if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is
// if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge.
// note that in this case PI_OFFSET is negative so invert before subtracting.
localparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0
? PI_OFFSET
: ((-PI_OFFSET) < DDR_TCK/2) ?
(DDR_TCK/2 - (- PI_OFFSET)) :
(DDR_TCK - (- PI_OFFSET)) ;
localparam real PI_STG2_DELAY =
(PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ?
PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND);
localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE;
localparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE));
localparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
wire _phy_clk;
wire [2:0] mcGo_w;
wire [HIGHEST_BANK-1:0] ref_dll_lock_w;
reg [15:0] mcGo_r;
assign ref_dll_lock = & ref_dll_lock_w;
initial begin
if ( SYNTHESIS == "FALSE" ) begin
$display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1);
$display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1);
$display("%m : HIGHEST_BANK = %d", HIGHEST_BANK);
$display("%m : FREQ_REF_PERIOD = %0.2f ", FREQ_REF_PERIOD);
$display("%m : DDR_TCK = %0d ", DDR_TCK);
$display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE);
$display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY);
$display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET);
$display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE);
$display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY);
$display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY);
$display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY);
$display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY);
$display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY);
$display("%m : PO_DELAY = %0.2f ", PO_DELAY);
$display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY);
$display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY);
$display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY);
$display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY);
$display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY);
$display("%m : PI_MAX_STG2_DELAY = %0.2f ", PI_MAX_STG2_DELAY);
$display("%m : PI_OFFSET = %0.2f ", PI_OFFSET);
if ( PI_OFFSET < 0) $display("%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used.");
$display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY);
$display("%m :PI_STG2_DELAY_CAND = %0.2f ",PI_STG2_DELAY_CAND);
$display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY);
$display("%m : RCLK_SELECT_EDGE = %0b ", LP_RCLK_SELECT_EDGE);
end // SYNTHESIS
if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display("WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY);
end
assign sync_pulse_split = sync_pulse;
assign mem_refclk_split = mem_refclk;
assign freq_refclk_split = freq_refclk;
assign mem_refclk_div4_split = mem_refclk_div4;
assign phy_ctl_clk_split0 = _phy_clk;
assign phy_ctl_wd_split0 = phy_ctl_wd;
assign phy_ctl_wr_split0 = phy_ctl_wr;
assign phy_clk_split0 = phy_clk;
assign phy_cmd_wr_en_split0 = phy_cmd_wr_en;
assign phy_data_wr_en_split0 = phy_data_wr_en;
assign phy_rd_en_split0 = phy_rd_en;
assign phy_dout_split0 = phy_dout;
assign phy_ctl_clk_split1 = phy_clk;
assign phy_ctl_wd_split1 = phy_ctl_wd;
assign phy_data_offset_1_split1 = data_offset_1;
assign phy_ctl_wr_split1 = phy_ctl_wr;
assign phy_clk_split1 = phy_clk;
assign phy_cmd_wr_en_split1 = phy_cmd_wr_en;
assign phy_data_wr_en_split1 = phy_data_wr_en;
assign phy_rd_en_split1 = phy_rd_en;
assign phy_dout_split1 = phy_dout;
assign phy_ctl_clk_split2 = phy_clk;
assign phy_ctl_wd_split2 = phy_ctl_wd;
assign phy_data_offset_2_split2 = data_offset_2;
assign phy_ctl_wr_split2 = phy_ctl_wr;
assign phy_clk_split2 = phy_clk;
assign phy_cmd_wr_en_split2 = phy_cmd_wr_en;
assign phy_data_wr_en_split2 = phy_data_wr_en;
assign phy_rd_en_split2 = phy_rd_en;
assign phy_dout_split2 = phy_dout;
// these wires are needed to coerce correct synthesis
// the synthesizer did not always see the widths of the
// parameters as 4 bits.
wire [3:0] blb0 = BYTE_LANES_B0;
wire [3:0] blb1 = BYTE_LANES_B1;
wire [3:0] blb2 = BYTE_LANES_B2;
wire [3:0] dcb0 = DATA_CTL_B0;
wire [3:0] dcb1 = DATA_CTL_B1;
wire [3:0] dcb2 = DATA_CTL_B2;
assign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0});
assign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0});
assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0];
assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs};
//Added to remove concadination in the instantiation
assign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ;
assign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ;
assign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ;
assign calib_zero_lanes_int = calib_zero_lanes;
assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0];
assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL];
assign of_ctl_a_full = |of_ctl_a_full_v;
assign of_ctl_full = |of_ctl_full_v;
assign of_data_a_full = |of_data_a_full_v;
assign of_data_full = |of_data_full_v;
assign pre_data_a_full= |pre_data_a_full_v;
// if if_empty_def == 1, empty is asserted only if all are empty;
// this allows the user to detect a skewed fifo depth and self-clear
// if desired. It avoids a reset to clear the flags.
assign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v;
assign if_empty_or = |if_empty_or_v;
assign if_empty_and = &if_empty_and_v;
assign if_a_empty = |if_a_empty_v;
generate
genvar i;
for (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen
case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff)
16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
default : initial $display("ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) ", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff ));
endcase
end
endgenerate
//assign rclk = rclk_w[RCLK_SELECT_BANK];
reg rst_auxout;
reg rst_auxout_r;
reg rst_auxout_rr;
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout_r <= #(1) 1'b1;
rst_auxout_rr <= #(1) 1'b1;
end
else begin
rst_auxout_r <= #(1) rst;
rst_auxout_rr <= #(1) rst_auxout_r;
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
else begin
always @(negedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
localparam L_RESET_SELECT_BANK =
(BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK;
always @(*) begin
rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n;
end
always @(posedge phy_clk or posedge rst) begin
if ( rst)
mcGo_r <= #(1) 0;
else
mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w;
end
assign mcGo = mcGo_r[15];
generate
// this is an optional 1 clock delay to add latency to the phy_control programming path
if (PHYCTL_CMD_FIFO == "TRUE") begin : cmd_fifo_soft
reg [31:0] phy_wd_reg = 0;
reg [3:0] aux_in1_reg = 0;
reg [3:0] aux_in2_reg = 0;
reg sfifo_ready = 0;
assign _phy_ctl_wd = phy_wd_reg;
assign aux_in_[1] = aux_in1_reg;
assign aux_in_[2] = aux_in2_reg;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[1] = |_phy_ctl_full_p;
assign phy_ctl_full[2] = |_phy_ctl_full_p;
assign phy_ctl_full[3] = |_phy_ctl_full_p;
assign _phy_clk = phy_clk;
always @(posedge phy_clk) begin
phy_wd_reg <= #1 phy_ctl_wd;
aux_in1_reg <= #1 aux_in_1;
aux_in2_reg <= #1 aux_in_2;
sfifo_ready <= #1 phy_ctl_wr;
end
end
else if (PHYCTL_CMD_FIFO == "FALSE") begin
assign _phy_ctl_wd = phy_ctl_wd;
assign aux_in_[1] = aux_in_1;
assign aux_in_[2] = aux_in_2;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[3:1] = 3'b000;
assign _phy_clk = phy_clk;
end
endgenerate
// instance of four-lane phy
generate
if (HIGHEST_BANK == 3) begin : banks_3
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]};
end
else if (HIGHEST_BANK == 2) begin : banks_2
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1};
end
else begin : banks_1
assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1};
end
if ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */
.DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY),
.BITLANES (PHY_0_BITLANES),
.BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK),
.LAST_BANK (PHY_0_IS_LAST_BANK),
.LANE_REMAP (PHY_0_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_0_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_0_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_0_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_0_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_0_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_0_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_0_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_0_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_0_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split0),
.phy_ctl_clk (phy_ctl_clk_split0),
.phy_ctl_wd (phy_ctl_wd_split0),
.data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]),
.phy_ctl_wr (phy_ctl_wr_split0),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]),
.phy_cmd_wr_en (phy_cmd_wr_en_split0),
.phy_data_wr_en (phy_data_wr_en_split0),
.phy_rd_en (phy_rd_en_split0),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[0]),
.rclk (),
.rst_out (rst_out_w[0]),
.mcGo (mcGo_w[0]),
.ref_dll_lock (ref_dll_lock_w[0]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]),
.if_a_empty (if_a_empty_v[0]),
.if_empty (if_empty_v[0]),
.byte_rd_en (byte_rd_en_v[0]),
.if_empty_or (if_empty_or_v[0]),
.if_empty_and (if_empty_and_v[0]),
.of_ctl_a_full (of_ctl_a_full_v[0]),
.of_data_a_full (of_data_a_full_v[0]),
.of_ctl_full (of_ctl_full_v[0]),
.of_data_full (of_data_full_v[0]),
.pre_data_a_full (pre_data_a_full_v[0]),
.phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]),
.phy_ctl_a_full (_phy_ctl_a_full_p[0]),
.phy_ctl_full (_phy_ctl_full_p[0]),
.phy_ctl_empty (phy_ctl_empty[0]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]),
.aux_out (aux_out_[3:0]),
.phy_ctl_ready (phy_ctl_ready_w[0]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte0),
.calib_zero_ctrl (calib_zero_ctrl[0]),
.calib_zero_lanes (calib_zero_lanes_int[3:0]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[0]),
.po_fine_enable (po_fine_enable[0]),
.po_fine_inc (po_fine_inc[0]),
.po_coarse_inc (po_coarse_inc[0]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[0]),
.po_fine_overflow (po_fine_overflow_w[0]),
.po_counter_read_val (po_counter_read_val_w[0]),
.pi_rst_dqs_find (pi_rst_dqs_find[0]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[0]),
.pi_counter_read_val (pi_counter_read_val_w[0]),
.pi_dqs_found (pi_dqs_found_w[0]),
.pi_dqs_found_all (pi_dqs_found_all_w[0]),
.pi_dqs_found_any (pi_dqs_found_any_w[0]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]),
.pi_phase_locked (pi_phase_locked_w[0]),
.pi_phase_locked_all (pi_phase_locked_all_w[0])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[0] <= #100 0;
aux_out[2] <= #100 0;
end
else begin
aux_out[0] <= #100 aux_out_[0];
aux_out[2] <= #100 aux_out_[2];
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
end
else begin
if ( HIGHEST_BANK > 0) begin
assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0;
assign _phy_ctl_a_full_p[0] = 0;
assign of_ctl_a_full_v[0] = 0;
assign of_ctl_full_v[0] = 0;
assign of_data_a_full_v[0] = 0;
assign of_data_full_v[0] = 0;
assign pre_data_a_full_v[0] = 0;
assign if_empty_v[0] = 0;
assign byte_rd_en_v[0] = 1;
always @(*)
aux_out[3:0] = 0;
end
assign pi_dqs_found_w[0] = 1;
assign pi_dqs_found_all_w[0] = 1;
assign pi_dqs_found_any_w[0] = 0;
assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_out_of_range_w[0] = 0;
assign pi_phase_locked_w[0] = 1;
assign po_fine_overflow_w[0] = 0;
assign po_coarse_overflow_w[0] = 0;
assign po_fine_overflow_w[0] = 0;
assign pi_fine_overflow_w[0] = 0;
assign po_counter_read_val_w[0] = 0;
assign pi_counter_read_val_w[0] = 0;
assign mcGo_w[0] = 1;
if ( RCLK_SELECT_BANK == 0)
always @(*)
aux_out[3:0] = 0;
end
if ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */
.DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY),
.BITLANES (PHY_1_BITLANES),
.BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK),
.LAST_BANK (PHY_1_IS_LAST_BANK ),
.LANE_REMAP (PHY_1_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_1_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_1_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_1_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_1_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_1_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_1_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_1_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_1_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_1_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_1_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_1_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_1_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_1_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split1),
.phy_ctl_clk (phy_ctl_clk_split1),
.phy_ctl_wd (phy_ctl_wd_split1),
.data_offset (phy_data_offset_1_split1),
.phy_ctl_wr (phy_ctl_wr_split1),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]),
.phy_cmd_wr_en (phy_cmd_wr_en_split1),
.phy_data_wr_en (phy_data_wr_en_split1),
.phy_rd_en (phy_rd_en_split1),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[1]),
.rclk (),
.rst_out (rst_out_w[1]),
.mcGo (mcGo_w[1]),
.ref_dll_lock (ref_dll_lock_w[1]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]),
.if_a_empty (if_a_empty_v[1]),
.if_empty (if_empty_v[1]),
.byte_rd_en (byte_rd_en_v[1]),
.if_empty_or (if_empty_or_v[1]),
.if_empty_and (if_empty_and_v[1]),
.of_ctl_a_full (of_ctl_a_full_v[1]),
.of_data_a_full (of_data_a_full_v[1]),
.of_ctl_full (of_ctl_full_v[1]),
.of_data_full (of_data_full_v[1]),
.pre_data_a_full (pre_data_a_full_v[1]),
.phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]),
.phy_ctl_a_full (_phy_ctl_a_full_p[1]),
.phy_ctl_full (_phy_ctl_full_p[1]),
.phy_ctl_empty (phy_ctl_empty[1]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]),
.aux_out (aux_out_[7:4]),
.phy_ctl_ready (phy_ctl_ready_w[1]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte1),
.calib_zero_ctrl (calib_zero_ctrl[1]),
.calib_zero_lanes (calib_zero_lanes_int[7:4]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[1]),
.po_fine_enable (po_fine_enable[1]),
.po_fine_inc (po_fine_inc[1]),
.po_coarse_inc (po_coarse_inc[1]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[1]),
.po_fine_overflow (po_fine_overflow_w[1]),
.po_counter_read_val (po_counter_read_val_w[1]),
.pi_rst_dqs_find (pi_rst_dqs_find[1]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[1]),
.pi_counter_read_val (pi_counter_read_val_w[1]),
.pi_dqs_found (pi_dqs_found_w[1]),
.pi_dqs_found_all (pi_dqs_found_all_w[1]),
.pi_dqs_found_any (pi_dqs_found_any_w[1]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]),
.pi_phase_locked (pi_phase_locked_w[1]),
.pi_phase_locked_all (pi_phase_locked_all_w[1])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[4] <= #100 0;
aux_out[6] <= #100 0;
end
else begin
aux_out[4] <= #100 aux_out_[4];
aux_out[6] <= #100 aux_out_[6];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
end
else begin
if ( HIGHEST_BANK > 1) begin
assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0;
assign _phy_ctl_a_full_p[1] = 0;
assign of_ctl_a_full_v[1] = 0;
assign of_ctl_full_v[1] = 0;
assign of_data_a_full_v[1] = 0;
assign of_data_full_v[1] = 0;
assign pre_data_a_full_v[1] = 0;
assign if_empty_v[1] = 0;
assign byte_rd_en_v[1] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
always @(*)
aux_out[7:4] = 0;
end
assign pi_dqs_found_w[1] = 1;
assign pi_dqs_found_all_w[1] = 1;
assign pi_dqs_found_any_w[1] = 0;
assign pi_dqs_out_of_range_w[1] = 0;
assign pi_phase_locked_w[1] = 1;
assign po_coarse_overflow_w[1] = 0;
assign po_fine_overflow_w[1] = 0;
assign pi_fine_overflow_w[1] = 0;
assign po_counter_read_val_w[1] = 0;
assign pi_counter_read_val_w[1] = 0;
assign mcGo_w[1] = 1;
end
if ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2
mig_7series_v1_9_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */
.DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY),
.BITLANES (PHY_2_BITLANES),
.BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK),
.LAST_BANK (PHY_2_IS_LAST_BANK ),
.LANE_REMAP (PHY_2_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_2_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_2_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_2_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_2_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_2_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_2_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_2_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_2_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_2_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_2_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_2_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_2_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_2_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split2),
.phy_ctl_clk (phy_ctl_clk_split2),
.phy_ctl_wd (phy_ctl_wd_split2),
.data_offset (phy_data_offset_2_split2),
.phy_ctl_wr (phy_ctl_wr_split2),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]),
.phy_cmd_wr_en (phy_cmd_wr_en_split2),
.phy_data_wr_en (phy_data_wr_en_split2),
.phy_rd_en (phy_rd_en_split2),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[2]),
.rclk (),
.rst_out (rst_out_w[2]),
.mcGo (mcGo_w[2]),
.ref_dll_lock (ref_dll_lock_w[2]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]),
.if_a_empty (if_a_empty_v[2]),
.if_empty (if_empty_v[2]),
.byte_rd_en (byte_rd_en_v[2]),
.if_empty_or (if_empty_or_v[2]),
.if_empty_and (if_empty_and_v[2]),
.of_ctl_a_full (of_ctl_a_full_v[2]),
.of_data_a_full (of_data_a_full_v[2]),
.of_ctl_full (of_ctl_full_v[2]),
.of_data_full (of_data_full_v[2]),
.pre_data_a_full (pre_data_a_full_v[2]),
.phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]),
.phy_ctl_a_full (_phy_ctl_a_full_p[2]),
.phy_ctl_full (_phy_ctl_full_p[2]),
.phy_ctl_empty (phy_ctl_empty[2]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]),
.aux_out (aux_out_[11:8]),
.phy_ctl_ready (phy_ctl_ready_w[2]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte2),
.calib_zero_ctrl (calib_zero_ctrl[2]),
.calib_zero_lanes (calib_zero_lanes_int[11:8]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[2]),
.po_fine_enable (po_fine_enable[2]),
.po_fine_inc (po_fine_inc[2]),
.po_coarse_inc (po_coarse_inc[2]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[2]),
.po_fine_overflow (po_fine_overflow_w[2]),
.po_counter_read_val (po_counter_read_val_w[2]),
.pi_rst_dqs_find (pi_rst_dqs_find[2]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[2]),
.pi_counter_read_val (pi_counter_read_val_w[2]),
.pi_dqs_found (pi_dqs_found_w[2]),
.pi_dqs_found_all (pi_dqs_found_all_w[2]),
.pi_dqs_found_any (pi_dqs_found_any_w[2]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]),
.pi_phase_locked (pi_phase_locked_w[2]),
.pi_phase_locked_all (pi_phase_locked_all_w[2])
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[8] <= #100 0;
aux_out[10] <= #100 0;
end
else begin
aux_out[8] <= #100 aux_out_[8];
aux_out[10] <= #100 aux_out_[10];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
end
else begin
if ( HIGHEST_BANK > 2) begin
assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0;
assign _phy_ctl_a_full_p[2] = 0;
assign of_ctl_a_full_v[2] = 0;
assign of_ctl_full_v[2] = 0;
assign of_data_a_full_v[2] = 0;
assign of_data_full_v[2] = 0;
assign pre_data_a_full_v[2] = 0;
assign if_empty_v[2] = 0;
assign byte_rd_en_v[2] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
always @(*)
aux_out[11:8] = 0;
end
assign pi_dqs_found_w[2] = 1;
assign pi_dqs_found_all_w[2] = 1;
assign pi_dqs_found_any_w[2] = 0;
assign pi_dqs_out_of_range_w[2] = 0;
assign pi_phase_locked_w[2] = 1;
assign po_coarse_overflow_w[2] = 0;
assign po_fine_overflow_w[2] = 0;
assign po_counter_read_val_w[2] = 0;
assign pi_counter_read_val_w[2] = 0;
assign mcGo_w[2] = 1;
end
endgenerate
generate
// for single bank , emit an extra phaser_in to generate rclk
// so that auxout can be placed in another region
// if desired
if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0)
begin : phaser_in_rclk
localparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY;
PHASER_IN_PHY #(
.BURST_MODE ( PHY_0_A_BURST_MODE),
.CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV),
.FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.FINE_DELAY ( L_EXTRA_PI_FINE_DELAY),
.OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC)
) phaser_in_rclk (
.DQSFOUND (),
.DQSOUTOFRANGE (),
.FINEOVERFLOW (),
.PHASELOCKED (),
.ISERDESRST (),
.ICLKDIV (),
.ICLK (),
.COUNTERREADVAL (),
.RCLK (),
.WRENABLE (),
.BURSTPENDINGPHY (),
.ENCALIBPHY (),
.FINEENABLE (0),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (0),
.PHASEREFCLK (),
.RSTDQSFIND (0),
.RST (rst),
.FINEINC (),
.COUNTERLOADEN (),
.COUNTERREADEN (),
.COUNTERLOADVAL (),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
end
endgenerate
always @(*) begin
case (calib_sel[5:3])
3'b000: begin
po_coarse_overflow = po_coarse_overflow_w[0];
po_fine_overflow = po_fine_overflow_w[0];
po_counter_read_val = po_counter_read_val_w[0];
pi_fine_overflow = pi_fine_overflow_w[0];
pi_counter_read_val = pi_counter_read_val_w[0];
pi_phase_locked = pi_phase_locked_w[0];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[0];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[0];
end
3'b001: begin
po_coarse_overflow = po_coarse_overflow_w[1];
po_fine_overflow = po_fine_overflow_w[1];
po_counter_read_val = po_counter_read_val_w[1];
pi_fine_overflow = pi_fine_overflow_w[1];
pi_counter_read_val = pi_counter_read_val_w[1];
pi_phase_locked = pi_phase_locked_w[1];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[1];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[1];
end
3'b010: begin
po_coarse_overflow = po_coarse_overflow_w[2];
po_fine_overflow = po_fine_overflow_w[2];
po_counter_read_val = po_counter_read_val_w[2];
pi_fine_overflow = pi_fine_overflow_w[2];
pi_counter_read_val = pi_counter_read_val_w[2];
pi_phase_locked = pi_phase_locked_w[2];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[2];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[2];
end
default: begin
po_coarse_overflow = 0;
po_fine_overflow = 0;
po_counter_read_val = 0;
pi_fine_overflow = 0;
pi_counter_read_val = 0;
pi_phase_locked = 0;
pi_dqs_found = 0;
pi_dqs_out_of_range = 0;
end
endcase
end
endmodule // mc_phy
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Properties of decidable propositions *)
Definition decidable (P:Prop) := P \/ ~ P.
Theorem dec_not_not : forall P:Prop, decidable P -> (~ P -> False) -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_True : decidable True.
Proof.
unfold decidable; auto.
Qed.
Theorem dec_False : decidable False.
Proof.
unfold decidable, not; auto.
Qed.
Theorem dec_or :
forall A B:Prop, decidable A -> decidable B -> decidable (A \/ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_and :
forall A B:Prop, decidable A -> decidable B -> decidable (A /\ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_not : forall A:Prop, decidable A -> decidable (~ A).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_imp :
forall A B:Prop, decidable A -> decidable B -> decidable (A -> B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_iff :
forall A B:Prop, decidable A -> decidable B -> decidable (A<->B).
Proof.
unfold decidable; tauto.
Qed.
Theorem not_not : forall P:Prop, decidable P -> ~ ~ P -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_or : forall A B:Prop, ~ (A \/ B) -> ~ A /\ ~ B.
Proof.
tauto.
Qed.
Theorem not_and : forall A B:Prop, decidable A -> ~ (A /\ B) -> ~ A \/ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_imp : forall A B:Prop, decidable A -> ~ (A -> B) -> A /\ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem imp_simp : forall A B:Prop, decidable A -> (A -> B) -> ~ A \/ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_iff :
forall A B:Prop, decidable A -> decidable B ->
~ (A <-> B) -> (A /\ ~ B) \/ (~ A /\ B).
Proof.
unfold decidable; tauto.
Qed.
(** Results formulated with iff, used in FSetDecide.
Negation are expanded since it is unclear whether setoid rewrite
will always perform conversion. *)
(** We begin with lemmas that, when read from left to right,
can be understood as ways to eliminate uses of [not]. *)
Theorem not_true_iff : (True -> False) <-> False.
Proof.
tauto.
Qed.
Theorem not_false_iff : (False -> False) <-> True.
Proof.
tauto.
Qed.
Theorem not_not_iff : forall A:Prop, decidable A ->
(((A -> False) -> False) <-> A).
Proof.
unfold decidable; tauto.
Qed.
Theorem contrapositive : forall A B:Prop, decidable A ->
(((A -> False) -> (B -> False)) <-> (B -> A)).
Proof.
unfold decidable; tauto.
Qed.
Lemma or_not_l_iff_1 : forall A B: Prop, decidable A ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_l_iff_2 : forall A B: Prop, decidable B ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_1 : forall A B: Prop, decidable A ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_2 : forall A B: Prop, decidable B ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma imp_not_l : forall A B: Prop, decidable A ->
(((A -> False) -> B) <-> (A \/ B)).
Proof.
unfold decidable. tauto.
Qed.
(** Moving Negations Around:
We have four lemmas that, when read from left to right,
describe how to push negations toward the leaves of a
proposition and, when read from right to left, describe
how to pull negations toward the top of a proposition. *)
Theorem not_or_iff : forall A B:Prop,
(A \/ B -> False) <-> (A -> False) /\ (B -> False).
Proof.
tauto.
Qed.
Lemma not_and_iff : forall A B:Prop,
(A /\ B -> False) <-> (A -> B -> False).
Proof.
tauto.
Qed.
Lemma not_imp_iff : forall A B:Prop, decidable A ->
(((A -> B) -> False) <-> A /\ (B -> False)).
Proof.
unfold decidable. tauto.
Qed.
Lemma not_imp_rev_iff : forall A B : Prop, decidable A ->
(((A -> B) -> False) <-> (B -> False) /\ A).
Proof.
unfold decidable. tauto.
Qed.
(* Functional relations on decidable co-domains are decidable *)
Theorem dec_functional_relation :
forall (X Y : Type) (A:X->Y->Prop), (forall y y' : Y, decidable (y=y')) ->
(forall x, exists! y, A x y) -> forall x y, decidable (A x y).
Proof.
intros X Y A Hdec H x y.
destruct (H x) as (y',(Hex,Huniq)).
destruct (Hdec y y') as [->|Hnot]; firstorder.
Qed.
(** With the following hint database, we can leverage [auto] to check
decidability of propositions. *)
Hint Resolve dec_True dec_False dec_or dec_and dec_imp dec_not dec_iff
: decidable_prop.
(** [solve_decidable using lib] will solve goals about the
decidability of a proposition, assisted by an auxiliary
database of lemmas. The database is intended to contain
lemmas stating the decidability of base propositions,
(e.g., the decidability of equality on a particular
inductive type). *)
Tactic Notation "solve_decidable" "using" ident(db) :=
match goal with
| |- decidable _ =>
solve [ auto 100 with decidable_prop db ]
end.
Tactic Notation "solve_decidable" :=
solve_decidable using core.
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Properties of decidable propositions *)
Definition decidable (P:Prop) := P \/ ~ P.
Theorem dec_not_not : forall P:Prop, decidable P -> (~ P -> False) -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_True : decidable True.
Proof.
unfold decidable; auto.
Qed.
Theorem dec_False : decidable False.
Proof.
unfold decidable, not; auto.
Qed.
Theorem dec_or :
forall A B:Prop, decidable A -> decidable B -> decidable (A \/ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_and :
forall A B:Prop, decidable A -> decidable B -> decidable (A /\ B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_not : forall A:Prop, decidable A -> decidable (~ A).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_imp :
forall A B:Prop, decidable A -> decidable B -> decidable (A -> B).
Proof.
unfold decidable; tauto.
Qed.
Theorem dec_iff :
forall A B:Prop, decidable A -> decidable B -> decidable (A<->B).
Proof.
unfold decidable; tauto.
Qed.
Theorem not_not : forall P:Prop, decidable P -> ~ ~ P -> P.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_or : forall A B:Prop, ~ (A \/ B) -> ~ A /\ ~ B.
Proof.
tauto.
Qed.
Theorem not_and : forall A B:Prop, decidable A -> ~ (A /\ B) -> ~ A \/ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_imp : forall A B:Prop, decidable A -> ~ (A -> B) -> A /\ ~ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem imp_simp : forall A B:Prop, decidable A -> (A -> B) -> ~ A \/ B.
Proof.
unfold decidable; tauto.
Qed.
Theorem not_iff :
forall A B:Prop, decidable A -> decidable B ->
~ (A <-> B) -> (A /\ ~ B) \/ (~ A /\ B).
Proof.
unfold decidable; tauto.
Qed.
(** Results formulated with iff, used in FSetDecide.
Negation are expanded since it is unclear whether setoid rewrite
will always perform conversion. *)
(** We begin with lemmas that, when read from left to right,
can be understood as ways to eliminate uses of [not]. *)
Theorem not_true_iff : (True -> False) <-> False.
Proof.
tauto.
Qed.
Theorem not_false_iff : (False -> False) <-> True.
Proof.
tauto.
Qed.
Theorem not_not_iff : forall A:Prop, decidable A ->
(((A -> False) -> False) <-> A).
Proof.
unfold decidable; tauto.
Qed.
Theorem contrapositive : forall A B:Prop, decidable A ->
(((A -> False) -> (B -> False)) <-> (B -> A)).
Proof.
unfold decidable; tauto.
Qed.
Lemma or_not_l_iff_1 : forall A B: Prop, decidable A ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_l_iff_2 : forall A B: Prop, decidable B ->
((A -> False) \/ B <-> (A -> B)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_1 : forall A B: Prop, decidable A ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma or_not_r_iff_2 : forall A B: Prop, decidable B ->
(A \/ (B -> False) <-> (B -> A)).
Proof.
unfold decidable. tauto.
Qed.
Lemma imp_not_l : forall A B: Prop, decidable A ->
(((A -> False) -> B) <-> (A \/ B)).
Proof.
unfold decidable. tauto.
Qed.
(** Moving Negations Around:
We have four lemmas that, when read from left to right,
describe how to push negations toward the leaves of a
proposition and, when read from right to left, describe
how to pull negations toward the top of a proposition. *)
Theorem not_or_iff : forall A B:Prop,
(A \/ B -> False) <-> (A -> False) /\ (B -> False).
Proof.
tauto.
Qed.
Lemma not_and_iff : forall A B:Prop,
(A /\ B -> False) <-> (A -> B -> False).
Proof.
tauto.
Qed.
Lemma not_imp_iff : forall A B:Prop, decidable A ->
(((A -> B) -> False) <-> A /\ (B -> False)).
Proof.
unfold decidable. tauto.
Qed.
Lemma not_imp_rev_iff : forall A B : Prop, decidable A ->
(((A -> B) -> False) <-> (B -> False) /\ A).
Proof.
unfold decidable. tauto.
Qed.
(* Functional relations on decidable co-domains are decidable *)
Theorem dec_functional_relation :
forall (X Y : Type) (A:X->Y->Prop), (forall y y' : Y, decidable (y=y')) ->
(forall x, exists! y, A x y) -> forall x y, decidable (A x y).
Proof.
intros X Y A Hdec H x y.
destruct (H x) as (y',(Hex,Huniq)).
destruct (Hdec y y') as [->|Hnot]; firstorder.
Qed.
(** With the following hint database, we can leverage [auto] to check
decidability of propositions. *)
Hint Resolve dec_True dec_False dec_or dec_and dec_imp dec_not dec_iff
: decidable_prop.
(** [solve_decidable using lib] will solve goals about the
decidability of a proposition, assisted by an auxiliary
database of lemmas. The database is intended to contain
lemmas stating the decidability of base propositions,
(e.g., the decidability of equality on a particular
inductive type). *)
Tactic Notation "solve_decidable" "using" ident(db) :=
match goal with
| |- decidable _ =>
solve [ auto 100 with decidable_prop db ]
end.
Tactic Notation "solve_decidable" :=
solve_decidable using core.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test case for parameterized module.
//
// When a module is instantiatied with parameter, there will be two modules in
// the tree and eventually one will be removed after param and deadifyModules.
//
// This test is to check that the removal of dead module will not cause
// compilation error. Possible error was/is seen as:
//
// pure virtual method called
// terminate called without an active exception
// %Error: Verilator aborted. Consider trying --debug --gdbbt
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jie Xu.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [71:0] ctrl;
wire [7:0] cl; // this line is added
memory #(.words(72)) i_memory (.clk (clk));
assign ctrl = i_memory.mem[0];
assign cl = i_memory.mem[0][7:0]; // and this line
endmodule
// memory module, which is used with parameter
module memory (clk);
input clk;
parameter words = 16384, bits = 72;
reg [bits-1 :0] mem[words-1 : 0];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test case for parameterized module.
//
// When a module is instantiatied with parameter, there will be two modules in
// the tree and eventually one will be removed after param and deadifyModules.
//
// This test is to check that the removal of dead module will not cause
// compilation error. Possible error was/is seen as:
//
// pure virtual method called
// terminate called without an active exception
// %Error: Verilator aborted. Consider trying --debug --gdbbt
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jie Xu.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [71:0] ctrl;
wire [7:0] cl; // this line is added
memory #(.words(72)) i_memory (.clk (clk));
assign ctrl = i_memory.mem[0];
assign cl = i_memory.mem[0][7:0]; // and this line
endmodule
// memory module, which is used with parameter
module memory (clk);
input clk;
parameter words = 16384, bits = 72;
reg [bits-1 :0] mem[words-1 : 0];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test case for parameterized module.
//
// When a module is instantiatied with parameter, there will be two modules in
// the tree and eventually one will be removed after param and deadifyModules.
//
// This test is to check that the removal of dead module will not cause
// compilation error. Possible error was/is seen as:
//
// pure virtual method called
// terminate called without an active exception
// %Error: Verilator aborted. Consider trying --debug --gdbbt
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jie Xu.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [71:0] ctrl;
wire [7:0] cl; // this line is added
memory #(.words(72)) i_memory (.clk (clk));
assign ctrl = i_memory.mem[0];
assign cl = i_memory.mem[0][7:0]; // and this line
endmodule
// memory module, which is used with parameter
module memory (clk);
input clk;
parameter words = 16384, bits = 72;
reg [bits-1 :0] mem[words-1 : 0];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// A test case for parameterized module.
//
// When a module is instantiatied with parameter, there will be two modules in
// the tree and eventually one will be removed after param and deadifyModules.
//
// This test is to check that the removal of dead module will not cause
// compilation error. Possible error was/is seen as:
//
// pure virtual method called
// terminate called without an active exception
// %Error: Verilator aborted. Consider trying --debug --gdbbt
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jie Xu.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [71:0] ctrl;
wire [7:0] cl; // this line is added
memory #(.words(72)) i_memory (.clk (clk));
assign ctrl = i_memory.mem[0];
assign cl = i_memory.mem[0][7:0]; // and this line
endmodule
// memory module, which is used with parameter
module memory (clk);
input clk;
parameter words = 16384, bits = 72;
reg [bits-1 :0] mem[words-1 : 0];
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_common.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Block for logic common to all rank machines. Contains
// a clock prescaler, and arbiters for refresh and periodic
// read functions.
`timescale 1 ps / 1 ps
module mig_7series_v1_9_rank_common #
(
parameter TCQ = 100,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCKESR = 4,
parameter nCK_PER_CLK = 2,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
maint_prescaler_tick_r, refresh_tick, maint_zq_r, maint_sre_r, maint_srx_r,
maint_req_r, maint_rank_r, clear_periodic_rd_request, periodic_rd_r,
periodic_rd_rank_r, app_ref_ack, app_zq_ack, app_sr_active, maint_ref_zq_wip,
// Inputs
clk, rst, init_calib_complete, app_ref_req, app_zq_req, app_sr_req,
insert_maint_r1, refresh_request, maint_wip_r, slot_0_present, slot_1_present,
periodic_rd_request, periodic_rd_ack_r
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input clk;
input rst;
// Maintenance and periodic read prescaler. Nominally 200 nS.
localparam ONE = 1;
localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1);
input init_calib_complete;
reg maint_prescaler_tick_r_lcl;
generate
begin : maint_prescaler
reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r;
reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns;
wire maint_prescaler_tick_ns =
(maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]);
always @(/*AS*/init_calib_complete or maint_prescaler_r
or maint_prescaler_tick_ns) begin
maint_prescaler_ns = maint_prescaler_r;
if (~init_calib_complete || maint_prescaler_tick_ns)
maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0];
else if (|maint_prescaler_r)
maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0];
end
always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns;
always @(posedge clk) maint_prescaler_tick_r_lcl <=
#TCQ maint_prescaler_tick_ns;
end
endgenerate
output wire maint_prescaler_tick_r;
assign maint_prescaler_tick_r = maint_prescaler_tick_r_lcl;
// Refresh timebase. Nominically 7800 nS.
localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER_DIV + /*idle*/ 1);
wire refresh_tick_lcl;
generate
begin : refresh_timer
reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_r;
reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl
or refresh_tick_lcl or refresh_timer_r) begin
refresh_timer_ns = refresh_timer_r;
if (~init_calib_complete || refresh_tick_lcl)
refresh_timer_ns = REFRESH_TIMER_DIV[REFRESH_TIMER_WIDTH-1:0];
else if (|refresh_timer_r && maint_prescaler_tick_r_lcl)
refresh_timer_ns =
refresh_timer_r - ONE[REFRESH_TIMER_WIDTH-1:0];
end
always @(posedge clk) refresh_timer_r <= #TCQ refresh_timer_ns;
assign refresh_tick_lcl = (refresh_timer_r ==
ONE[REFRESH_TIMER_WIDTH-1:0]) && maint_prescaler_tick_r_lcl;
end
endgenerate
output wire refresh_tick;
assign refresh_tick = refresh_tick_lcl;
// ZQ timebase. Nominally 128 mS
localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1);
input app_zq_req;
input insert_maint_r1;
reg maint_zq_r_lcl;
reg zq_request = 1'b0;
generate
if (DRAM_TYPE == "DDR3") begin : zq_cntrl
reg zq_tick = 1'b0;
if (ZQ_TIMER_DIV !=0) begin : zq_timer
reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r;
reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl
or zq_tick or zq_timer_r) begin
zq_timer_ns = zq_timer_r;
if (~init_calib_complete || zq_tick)
zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0];
else if (|zq_timer_r && maint_prescaler_tick_r_lcl)
zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0];
end
always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns;
always @(/*AS*/maint_prescaler_tick_r_lcl or zq_timer_r)
zq_tick = (zq_timer_r ==
ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick_r_lcl);
end // zq_timer
// ZQ request. Set request with timer tick, and when exiting PHY init. Never
// request if ZQ_TIMER_DIV == 0.
begin : zq_request_logic
wire zq_clears_zq_request = insert_maint_r1 && maint_zq_r_lcl;
reg zq_request_r;
wire zq_request_ns = ~rst && (DRAM_TYPE == "DDR3") &&
((~init_calib_complete && (ZQ_TIMER_DIV != 0)) ||
(zq_request_r && ~zq_clears_zq_request) ||
zq_tick ||
(app_zq_req && init_calib_complete));
always @(posedge clk) zq_request_r <= #TCQ zq_request_ns;
always @(/*AS*/init_calib_complete or zq_request_r)
zq_request = init_calib_complete && zq_request_r;
end // zq_request_logic
end
endgenerate
// Self-refresh control
localparam nCKESR_CLKS = (nCKESR / nCK_PER_CLK) + (nCKESR % nCK_PER_CLK ? 1 : 0);
localparam CKESR_TIMER_WIDTH = clogb2(nCKESR_CLKS + 1);
input app_sr_req;
reg maint_sre_r_lcl;
reg maint_srx_r_lcl;
reg sre_request = 1'b0;
wire inhbt_srx;
generate begin : sr_cntrl
// SRE request. Set request with user request.
begin : sre_request_logic
reg sre_request_r;
wire sre_clears_sre_request = insert_maint_r1 && maint_sre_r_lcl;
wire sre_request_ns = ~rst && ((sre_request_r && ~sre_clears_sre_request)
|| (app_sr_req && init_calib_complete && ~maint_sre_r_lcl));
always @(posedge clk) sre_request_r <= #TCQ sre_request_ns;
always @(init_calib_complete or sre_request_r)
sre_request = init_calib_complete && sre_request_r;
end // sre_request_logic
// CKESR timer: Self-Refresh must be maintained for a minimum of tCKESR
begin : ckesr_timer
reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_r = {CKESR_TIMER_WIDTH{1'b0}};
reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_ns = {CKESR_TIMER_WIDTH{1'b0}};
always @(insert_maint_r1 or ckesr_timer_r or maint_sre_r_lcl) begin
ckesr_timer_ns = ckesr_timer_r;
if (insert_maint_r1 && maint_sre_r_lcl)
ckesr_timer_ns = nCKESR_CLKS[CKESR_TIMER_WIDTH-1:0];
else if(|ckesr_timer_r)
ckesr_timer_ns = ckesr_timer_r - ONE[CKESR_TIMER_WIDTH-1:0];
end
always @(posedge clk) ckesr_timer_r <= #TCQ ckesr_timer_ns;
assign inhbt_srx = |ckesr_timer_r;
end // ckesr_timer
end
endgenerate
// DRAM maintenance operations of refresh and ZQ calibration, and self-refresh
// DRAM maintenance operations and self-refresh have their own channel in the
// queue. There is also a single, very simple bank machine
// dedicated to these operations. Its assumed that the
// maintenance operations can be completed quickly enough
// to avoid any queuing.
//
// ZQ, refresh and self-refresh requests share a channel into controller.
// Self-refresh is appended to the uppermost bit of the request bus and ZQ is
// appended just below that.
input[RANKS-1:0] refresh_request;
input maint_wip_r;
reg maint_req_r_lcl;
reg [RANK_WIDTH-1:0] maint_rank_r_lcl;
input [7:0] slot_0_present;
input [7:0] slot_1_present;
generate
begin : maintenance_request
// Maintenance request pipeline.
reg upd_last_master_r;
reg new_maint_rank_r;
wire maint_busy = upd_last_master_r || new_maint_rank_r ||
maint_req_r_lcl || maint_wip_r;
wire [RANKS+1:0] maint_request = {sre_request, zq_request, refresh_request[RANKS-1:0]};
wire upd_last_master_ns = |maint_request && ~maint_busy;
always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns;
always @(posedge clk) new_maint_rank_r <= #TCQ upd_last_master_r;
always @(posedge clk) maint_req_r_lcl <= #TCQ new_maint_rank_r;
// Arbitrate maintenance requests.
wire [RANKS+1:0] maint_grant_ns;
wire [RANKS+1:0] maint_grant_r;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (RANKS+2))
maint_arb0
(.grant_ns (maint_grant_ns),
.grant_r (maint_grant_r),
.upd_last_master (upd_last_master_r),
.current_master (maint_grant_r),
.req (maint_request),
.disable_grant (1'b0),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
// Look at arbitration results. Decide if ZQ, refresh or self-refresh.
// If refresh select the maintenance rank from the winning rank controller.
// If ZQ or self-refresh, generate a sequence of rank numbers corresponding to
// slots populated maint_rank_r is not used for comparisons in the queue for ZQ
// or self-refresh requests. The bank machine will enable CS for the number of
// states equal to the the number of occupied slots. This will produce a
// command to every occupied slot, but not in any particular order.
wire [7:0] present = slot_0_present | slot_1_present;
integer i;
reg [RANK_WIDTH-1:0] maint_rank_ns;
wire maint_zq_ns = ~rst && (upd_last_master_r
? maint_grant_r[RANKS]
: maint_zq_r_lcl);
wire maint_srx_ns = ~rst && (maint_sre_r_lcl
? ~app_sr_req & ~inhbt_srx
: maint_srx_r_lcl && upd_last_master_r
? maint_grant_r[RANKS+1]
: maint_srx_r_lcl);
wire maint_sre_ns = ~rst && (upd_last_master_r
? maint_grant_r[RANKS+1]
: maint_sre_r_lcl && ~maint_srx_ns);
always @(/*AS*/maint_grant_r or maint_rank_r_lcl or maint_zq_ns
or maint_sre_ns or maint_srx_ns or present or rst
or upd_last_master_r) begin
if (rst) maint_rank_ns = {RANK_WIDTH{1'b0}};
else begin
maint_rank_ns = maint_rank_r_lcl;
if (maint_zq_ns || maint_sre_ns || maint_srx_ns) begin
maint_rank_ns = maint_rank_r_lcl + ONE[RANK_WIDTH-1:0];
for (i=0; i<8; i=i+1)
if (~present[maint_rank_ns])
maint_rank_ns = maint_rank_ns + ONE[RANK_WIDTH-1:0];
end
else
if (upd_last_master_r)
for (i=0; i<RANKS; i=i+1)
if (maint_grant_r[i]) maint_rank_ns = i[RANK_WIDTH-1:0];
end
end
always @(posedge clk) maint_rank_r_lcl <= #TCQ maint_rank_ns;
always @(posedge clk) maint_zq_r_lcl <= #TCQ maint_zq_ns;
always @(posedge clk) maint_sre_r_lcl <= #TCQ maint_sre_ns;
always @(posedge clk) maint_srx_r_lcl <= #TCQ maint_srx_ns;
end // block: maintenance_request
endgenerate
output wire maint_zq_r;
assign maint_zq_r = maint_zq_r_lcl;
output wire maint_sre_r;
assign maint_sre_r = maint_sre_r_lcl;
output wire maint_srx_r;
assign maint_srx_r = maint_srx_r_lcl;
output wire maint_req_r;
assign maint_req_r = maint_req_r_lcl;
output wire [RANK_WIDTH-1:0] maint_rank_r;
assign maint_rank_r = maint_rank_r_lcl;
// Indicate whether self-refresh is active or not.
output app_sr_active;
reg app_sr_active_r;
wire app_sr_active_ns =
insert_maint_r1 ? maint_sre_r && ~maint_srx_r : app_sr_active_r;
always @(posedge clk) app_sr_active_r <= #TCQ app_sr_active_ns;
assign app_sr_active = app_sr_active_r;
// Acknowledge user REF and ZQ Requests
input app_ref_req;
output app_ref_ack;
wire app_ref_ack_ns;
wire app_ref_ns;
reg app_ref_ack_r = 1'b0;
reg app_ref_r = 1'b0;
assign app_ref_ns = init_calib_complete && (app_ref_req || app_ref_r && |refresh_request);
assign app_ref_ack_ns = app_ref_r && ~|refresh_request;
always @(posedge clk) app_ref_r <= #TCQ app_ref_ns;
always @(posedge clk) app_ref_ack_r <= #TCQ app_ref_ack_ns;
assign app_ref_ack = app_ref_ack_r;
output app_zq_ack;
wire app_zq_ack_ns;
wire app_zq_ns;
reg app_zq_ack_r = 1'b0;
reg app_zq_r = 1'b0;
assign app_zq_ns = init_calib_complete && (app_zq_req || app_zq_r && zq_request);
assign app_zq_ack_ns = app_zq_r && ~zq_request;
always @(posedge clk) app_zq_r <= #TCQ app_zq_ns;
always @(posedge clk) app_zq_ack_r <= #TCQ app_zq_ack_ns;
assign app_zq_ack = app_zq_ack_r;
// Periodic reads to maintain PHY alignment.
// Demand insertion of periodic read as soon as
// possible. Since the is a single rank, bank compare mechanism
// must be used, periodic reads must be forced in at the
// expense of not accepting a normal request.
input [RANKS-1:0] periodic_rd_request;
reg periodic_rd_r_lcl;
reg [RANK_WIDTH-1:0] periodic_rd_rank_r_lcl;
input periodic_rd_ack_r;
output wire [RANKS-1:0] clear_periodic_rd_request;
output wire periodic_rd_r;
output wire [RANK_WIDTH-1:0] periodic_rd_rank_r;
generate
// This is not needed in 7-Series and should remain disabled
if ( PERIODIC_RD_TIMER_DIV != 0 ) begin : periodic_read_request
// Maintenance request pipeline.
reg periodic_rd_r_cnt;
wire int_periodic_rd_ack_r = (periodic_rd_ack_r && periodic_rd_r_cnt);
reg upd_last_master_r;
wire periodic_rd_busy = upd_last_master_r || periodic_rd_r_lcl;
wire upd_last_master_ns =
init_calib_complete && (|periodic_rd_request && ~periodic_rd_busy);
always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns;
wire periodic_rd_ns = init_calib_complete &&
(upd_last_master_r || (periodic_rd_r_lcl && ~int_periodic_rd_ack_r));
always @(posedge clk) periodic_rd_r_lcl <= #TCQ periodic_rd_ns;
always @(posedge clk) begin
if (rst) periodic_rd_r_cnt <= #TCQ 1'b0;
else if (periodic_rd_r_lcl && periodic_rd_ack_r)
periodic_rd_r_cnt <= ~periodic_rd_r_cnt;
end
// Arbitrate periodic read requests.
wire [RANKS-1:0] periodic_rd_grant_ns;
reg [RANKS-1:0] periodic_rd_grant_r;
mig_7series_v1_9_round_robin_arb #
(.WIDTH (RANKS))
periodic_rd_arb0
(.grant_ns (periodic_rd_grant_ns[RANKS-1:0]),
.grant_r (),
.upd_last_master (upd_last_master_r),
.current_master (periodic_rd_grant_r[RANKS-1:0]),
.req (periodic_rd_request[RANKS-1:0]),
.disable_grant (1'b0),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
always @(posedge clk) periodic_rd_grant_r = upd_last_master_ns
? periodic_rd_grant_ns
: periodic_rd_grant_r;
// Encode and set periodic read rank into periodic_rd_rank_r.
integer i;
reg [RANK_WIDTH-1:0] periodic_rd_rank_ns;
always @(/*AS*/periodic_rd_grant_r or periodic_rd_rank_r_lcl
or upd_last_master_r) begin
periodic_rd_rank_ns = periodic_rd_rank_r_lcl;
if (upd_last_master_r)
for (i=0; i<RANKS; i=i+1)
if (periodic_rd_grant_r[i])
periodic_rd_rank_ns = i[RANK_WIDTH-1:0];
end
always @(posedge clk) periodic_rd_rank_r_lcl <=
#TCQ periodic_rd_rank_ns;
// Once the request is dropped in the queue, it might be a while before it
// emerges. Can't clear the request based on seeing the read issued.
// Need to clear the request as soon as its made it into the queue.
assign clear_periodic_rd_request =
periodic_rd_grant_r & {RANKS{periodic_rd_ack_r}};
assign periodic_rd_r = periodic_rd_r_lcl;
assign periodic_rd_rank_r = periodic_rd_rank_r_lcl;
end else begin
// Disable periodic reads
assign clear_periodic_rd_request = {RANKS{1'b0}};
assign periodic_rd_r = 1'b0;
assign periodic_rd_rank_r = {RANK_WIDTH{1'b0}};
end // block: periodic_read_request
endgenerate
// Indicate that a refresh is in progress. The PHY will use this to schedule
// tap adjustments during idle bus time
reg maint_ref_zq_wip_r = 1'b0;
output maint_ref_zq_wip;
always @(posedge clk)
if(rst)
maint_ref_zq_wip_r <= #TCQ 1'b0;
else if((zq_request || |refresh_request) && insert_maint_r1)
maint_ref_zq_wip_r <= #TCQ 1'b1;
else if(~maint_wip_r)
maint_ref_zq_wip_r <= #TCQ 1'b0;
assign maint_ref_zq_wip = maint_ref_zq_wip_r;
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_in_deserializer (
// Inputs
clk,
reset,
serial_data_in,
receive_data_en,
// Bidirectionals
// Outputs
fifo_read_available,
received_data_valid,
received_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input serial_data_in;
input receive_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_read_available;
output received_data_valid;
output [DW: 0] received_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_received;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
// Internal Registers
reg receiving_data;
reg [(TDW-1):0] data_in_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_read_available <= 8'h00;
else
fifo_read_available <= {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
receiving_data <= 1'b0;
else if (all_bits_received)
receiving_data <= 1'b0;
else if (serial_data_in == 1'b0)
receiving_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_in_shift_reg <= {TDW{1'b0}};
else if (shift_data_reg_en)
data_in_shift_reg <=
{serial_data_in, data_in_shift_reg[(TDW - 1):1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign received_data_valid = ~fifo_is_empty;
// Input assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_In_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~receiving_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (),
.baud_clock_falling_edge (shift_data_reg_en),
.all_bits_transmitted (all_bits_received)
);
defparam
RS232_In_Counters.CW = CW,
RS232_In_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Counters.TDW = TDW;
altera_up_sync_fifo RS232_In_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (all_bits_received & ~fifo_is_full),
.write_data (data_in_shift_reg[(DW + 1):1]),
.read_en (receive_data_en & ~fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (received_data)
);
defparam
RS232_In_FIFO.DW = DW,
RS232_In_FIFO.DATA_DEPTH = 128,
RS232_In_FIFO.AW = 6;
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module reads data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_in_deserializer (
// Inputs
clk,
reset,
serial_data_in,
receive_data_en,
// Bidirectionals
// Outputs
fifo_read_available,
received_data_valid,
received_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input serial_data_in;
input receive_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_read_available;
output received_data_valid;
output [DW: 0] received_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_received;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
// Internal Registers
reg receiving_data;
reg [(TDW-1):0] data_in_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_read_available <= 8'h00;
else
fifo_read_available <= {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
receiving_data <= 1'b0;
else if (all_bits_received)
receiving_data <= 1'b0;
else if (serial_data_in == 1'b0)
receiving_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_in_shift_reg <= {TDW{1'b0}};
else if (shift_data_reg_en)
data_in_shift_reg <=
{serial_data_in, data_in_shift_reg[(TDW - 1):1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign received_data_valid = ~fifo_is_empty;
// Input assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_In_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~receiving_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (),
.baud_clock_falling_edge (shift_data_reg_en),
.all_bits_transmitted (all_bits_received)
);
defparam
RS232_In_Counters.CW = CW,
RS232_In_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Counters.TDW = TDW;
altera_up_sync_fifo RS232_In_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (all_bits_received & ~fifo_is_full),
.write_data (data_in_shift_reg[(DW + 1):1]),
.read_en (receive_data_en & ~fifo_is_empty),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (received_data)
);
defparam
RS232_In_FIFO.DW = DW,
RS232_In_FIFO.DATA_DEPTH = 128,
RS232_In_FIFO.AW = 6;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: syncff.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A back to back FF design to mitigate metastable issues
// when crossing clock domains.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module syncff
(
input CLK,
input IN_ASYNC,
output OUT_SYNC
);
wire wSyncFFQ;
ff
syncFF
(
.CLK(CLK),
.D(IN_ASYNC),
.Q(wSyncFFQ)
);
ff metaFF (
.CLK(CLK),
.D(wSyncFFQ),
.Q(OUT_SYNC)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_compare.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block stores the request for this bank machine.
//
// All possible new requests are compared against the request stored
// here. The compare results are shared with the bank machines and
// is used to determine where to enqueue a new request.
`timescale 1ps/1ps
module mig_7series_v1_9_bank_compare #
(parameter BANK_WIDTH = 3,
parameter TCQ = 100,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter ECC = "OFF",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16)
(/*AUTOARG*/
// Outputs
req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r,
req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r,
rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr,
req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r,
// Inputs
clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd,
sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority,
maint_rank_r, maint_zq_r, maint_sre_r, auto_pre_r, rd_half_rmw, act_wait_r
);
input clk;
input idle_ns;
input idle_r;
input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;
output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns =
idle_r
? data_buf_addr
: req_data_buf_addr_r;
always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns;
input periodic_rd_insert;
reg req_periodic_rd_r_lcl;
wire req_periodic_rd_ns = idle_ns
? periodic_rd_insert
: req_periodic_rd_r_lcl;
always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns;
output wire req_periodic_rd_r;
assign req_periodic_rd_r = req_periodic_rd_r_lcl;
input size;
wire req_size_r_lcl;
generate
if (BURST_MODE == "4") begin : burst_mode_4
assign req_size_r_lcl = 1'b0;
end
else
if (BURST_MODE == "8") begin : burst_mode_8
assign req_size_r_lcl = 1'b1;
end
else
if (BURST_MODE == "OTF") begin : burst_mode_otf
reg req_size;
wire req_size_ns = idle_ns
? (periodic_rd_insert || size)
: req_size;
always @(posedge clk) req_size <= #TCQ req_size_ns;
assign req_size_r_lcl = req_size;
end
endgenerate
output wire req_size_r;
assign req_size_r = req_size_r_lcl;
input [2:0] cmd;
reg [2:0] req_cmd_r;
wire [2:0] req_cmd_ns = idle_ns
? (periodic_rd_insert ? 3'b001 : cmd)
: req_cmd_r;
always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns;
`ifdef MC_SVA
rd_wr_only_wo_ecc: assert property
(@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1]));
`endif
input sending_col;
reg rd_wr_r_lcl;
wire rd_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0])
: ~sending_col && rd_wr_r_lcl;
always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns;
output wire rd_wr_r;
assign rd_wr_r = rd_wr_r_lcl;
input [RANK_WIDTH-1:0] rank;
input [RANK_WIDTH-1:0] periodic_rd_rank_r;
reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}};
reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}};
generate
if (RANKS != 1) begin
always @(/*AS*/idle_ns or periodic_rd_insert
or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns
? periodic_rd_insert
? periodic_rd_rank_r
: rank
: req_rank_r_lcl;
always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns;
end
endgenerate
output wire [RANK_WIDTH-1:0] req_rank_r;
assign req_rank_r = req_rank_r_lcl;
input [BANK_WIDTH-1:0] bank;
reg [BANK_WIDTH-1:0] req_bank_r_lcl;
wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl;
always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns;
output wire[BANK_WIDTH-1:0] req_bank_r;
assign req_bank_r = req_bank_r_lcl;
input [ROW_WIDTH-1:0] row;
reg [ROW_WIDTH-1:0] req_row_r_lcl;
wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl;
always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns;
output wire [ROW_WIDTH-1:0] req_row_r;
assign req_row_r = req_row_r_lcl;
// Make req_col_r as wide as the max row address. This
// makes it easier to deal with indexing different column widths.
input [COL_WIDTH-1:0] col;
reg [15:0] req_col_r = 16'b0;
wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0];
always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns;
reg req_wr_r_lcl;
wire req_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0])
: req_wr_r_lcl;
always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns;
output wire req_wr_r;
assign req_wr_r = req_wr_r_lcl;
input hi_priority;
output reg req_priority_r;
wire req_priority_ns = idle_ns ? hi_priority : req_priority_r;
always @(posedge clk) req_priority_r <= #TCQ req_priority_ns;
wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert
? periodic_rd_rank_r
: rank));
wire bank_hit = (req_bank_r_lcl == bank);
wire rank_bank_hit = rank_hit && bank_hit;
output reg rb_hit_busy_r; // rank-bank hit on non idle row machine
wire rb_hit_busy_ns_lcl;
assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns;
output wire rb_hit_busy_ns;
assign rb_hit_busy_ns = rb_hit_busy_ns_lcl;
wire row_hit_ns = (req_row_r_lcl == row);
output reg row_hit_r;
always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl;
always @(posedge clk) row_hit_r <= #TCQ row_hit_ns;
input [RANK_WIDTH-1:0] maint_rank_r;
input maint_zq_r;
input maint_sre_r;
output wire maint_hit;
assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r || maint_sre_r;
// Assemble column address. Structure to be the same
// width as the row address. This makes it easier
// for the downstream muxing. Depending on the sizes
// of the row and column addresses, fill in as appropriate.
input auto_pre_r;
input rd_half_rmw;
reg [15:0] col_addr_template = 16'b0;
always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r
or req_size_r_lcl) begin
col_addr_template = req_col_r;
col_addr_template[10] = auto_pre_r && ~rd_half_rmw;
col_addr_template[11] = req_col_r[10];
col_addr_template[12] = req_size_r_lcl;
col_addr_template[13] = req_col_r[11];
end
output wire [ROW_WIDTH-1:0] col_addr;
assign col_addr = col_addr_template[ROW_WIDTH-1:0];
output wire req_ras;
output wire req_cas;
output wire row_cmd_wr;
input act_wait_r;
assign req_ras = 1'b0;
assign req_cas = 1'b1;
assign row_cmd_wr = act_wait_r;
output reg [ROW_WIDTH-1:0] row_addr;
always @(/*AS*/act_wait_r or req_row_r_lcl) begin
row_addr = req_row_r_lcl;
// This causes all precharges to be precharge single bank command.
if (~act_wait_r) row_addr[10] = 1'b0;
end
// Indicate which, if any, rank this bank machine is busy with.
// Not registering the result would probably be more accurate, but
// would create timing issues. This is used for refresh banking, perfect
// accuracy is not required.
localparam ONE = 1;
output reg [RANKS-1:0] rank_busy_r;
wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns);
always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns;
endmodule // bank_compare
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: interrupt_controller.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Signals an interrupt on the Xilnx PCIe Endpoint
// interface. Supports single vector MSI or legacy based
// interrupts.
// When INTR is pulsed high, the interrupt will be issued
// as soon as possible. If using legacy interrupts, the
// initial interrupt must be cleared by another request
// (typically a PIO read or write request to the
// endpoint at some predetermined BAR address). Receipt of
// the "clear" acknowledgment should cause INTR_LEGACY_CLR
// input to pulse high. Thus completing the legacy
// interrupt cycle. If using MSI interrupts, no such
// acknowldegment is necessary.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_INTRCTLR_IDLE 3'd0
`define S_INTRCLTR_WORKING 3'd1
`define S_INTRCLTR_COMPLETE 3'd2
`define S_INTRCLTR_CLEAR_LEGACY 3'd3
`define S_INTRCLTR_CLEARING_LEGACY 3'd4
`define S_INTRCLTR_DONE 3'd5
`timescale 1ns/1ns
module interrupt_controller (
input CLK, // System clock
input RST, // Async reset
input INTR, // Pulsed high to request an interrupt
input INTR_LEGACY_CLR, // Pulsed high to ack the legacy interrupt and clear it
output INTR_DONE, // Pulsed high to signal interrupt sent
input CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
output CFG_INTERRUPT_ASSERT, // Legacy interrupt message type
input INTR_MSI_RDY, // High when interrupt is able to be sent
output INTR_MSI_REQUEST // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent
);
reg [2:0] rState=`S_INTRCTLR_IDLE;
reg [2:0] rStateNext=`S_INTRCTLR_IDLE;
reg rIntr=0;
reg rIntrAssert=0;
assign INTR_DONE = (rState == `S_INTRCLTR_DONE);
assign INTR_MSI_REQUEST = rIntr;
assign CFG_INTERRUPT_ASSERT = rIntrAssert;
// Control sending interrupts.
always @(*) begin
case (rState)
`S_INTRCTLR_IDLE : begin
if (INTR) begin
rIntr = 1;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
end
else begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
end
`S_INTRCLTR_WORKING : begin
rIntr = 1;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_COMPLETE : `S_INTRCLTR_WORKING);
end
`S_INTRCLTR_COMPLETE : begin
rIntr = 0;
rIntrAssert = !CONFIG_INTERRUPT_MSIENABLE;
rStateNext = (CONFIG_INTERRUPT_MSIENABLE ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEAR_LEGACY);
end
`S_INTRCLTR_CLEAR_LEGACY : begin
if (INTR_LEGACY_CLR) begin
rIntr = 1;
rIntrAssert = 0;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
end
else begin
rIntr = 0;
rIntrAssert = 1;
rStateNext = `S_INTRCLTR_CLEAR_LEGACY;
end
end
`S_INTRCLTR_CLEARING_LEGACY : begin
rIntr = 1;
rIntrAssert = 0;
rStateNext = (INTR_MSI_RDY ? `S_INTRCLTR_DONE : `S_INTRCLTR_CLEARING_LEGACY);
end
`S_INTRCLTR_DONE : begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
default: begin
rIntr = 0;
rIntrAssert = 0;
rStateNext = `S_INTRCTLR_IDLE;
end
endcase
end
// Update the state.
always @(posedge CLK) begin
if (RST)
rState <= #1 `S_INTRCTLR_IDLE;
else
rState <= #1 rStateNext;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v1_9_tempmon.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Jul 25 2012
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Monitors chip temperature via the XADC and adjusts the
// stage 2 tap values as appropriate.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v1_9_tempmon #
(
parameter TCQ = 100, // Register delay (sim only)
parameter TEMP_MON_CONTROL = "INTERNAL", // XADC or user temperature source
parameter XADC_CLK_PERIOD = 5000, // pS (default to 200 MHz refclk)
parameter tTEMPSAMPLE = 10000000 // ps (10 us)
)
(
input clk, // Fabric clock
input xadc_clk,
input rst, // System reset
input [11:0] device_temp_i, // User device temperature
output [11:0] device_temp // Sampled temperature
);
//***************************************************************************
// Function cdiv
// Description:
// This function performs ceiling division (divide and round-up)
// Inputs:
// num: integer to be divided
// div: divisor
// Outputs:
// cdiv: result of ceiling division (num/div, rounded up)
//***************************************************************************
function integer cdiv (input integer num, input integer div);
begin
// perform division, then add 1 if and only if remainder is non-zero
cdiv = (num/div) + (((num%div)>0) ? 1 : 0);
end
endfunction // cdiv
//***************************************************************************
// Function clogb2
// Description:
// This function performs binary logarithm and rounds up
// Inputs:
// size: integer to perform binary log upon
// Outputs:
// clogb2: result of binary logarithm, rounded up
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
// increment clogb2 from 1 for each bit in size
for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1)
size = size >> 1;
end
endfunction // clogb2
// Synchronization registers
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r1;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r2;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r3 /* synthesis syn_srlstyle="registers" */;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r4;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r5;
// Output register
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_r;
wire [11:0] device_temp_lcl;
reg [3:0] sync_cntr = 4'b0000;
reg device_temp_sync_r4_neq_r3;
// (* ASYNC_REG = "TRUE" *) reg rst_r1;
// (* ASYNC_REG = "TRUE" *) reg rst_r2;
// // Synchronization rst to XADC clock domain
// always @(posedge xadc_clk) begin
// rst_r1 <= rst;
// rst_r2 <= rst_r1;
// end
// Synchronization counter
always @(posedge clk) begin
device_temp_sync_r1 <= #TCQ device_temp_lcl;
device_temp_sync_r2 <= #TCQ device_temp_sync_r1;
device_temp_sync_r3 <= #TCQ device_temp_sync_r2;
device_temp_sync_r4 <= #TCQ device_temp_sync_r3;
device_temp_sync_r5 <= #TCQ device_temp_sync_r4;
device_temp_sync_r4_neq_r3 <= #TCQ (device_temp_sync_r4 != device_temp_sync_r3) ? 1'b1 : 1'b0;
end
always @(posedge clk)
if(rst || (device_temp_sync_r4_neq_r3))
sync_cntr <= #TCQ 4'b0000;
else if(~&sync_cntr)
sync_cntr <= #TCQ sync_cntr + 4'b0001;
always @(posedge clk)
if(&sync_cntr)
device_temp_r <= #TCQ device_temp_sync_r5;
assign device_temp = device_temp_r;
generate
if(TEMP_MON_CONTROL == "EXTERNAL") begin : user_supplied_temperature
assign device_temp_lcl = device_temp_i;
end else begin : xadc_supplied_temperature
// calculate polling timer width and limit
localparam nTEMPSAMP = cdiv(tTEMPSAMPLE, XADC_CLK_PERIOD);
localparam nTEMPSAMP_CLKS = nTEMPSAMP;
localparam nTEMPSAMP_CLKS_M6 = nTEMPSAMP - 6;
localparam nTEMPSAMP_CNTR_WIDTH = clogb2(nTEMPSAMP_CLKS);
// Temperature sampler FSM encoding
localparam INIT_IDLE = 2'b00;
localparam REQUEST_READ_TEMP = 2'b01;
localparam WAIT_FOR_READ = 2'b10;
localparam READ = 2'b11;
// polling timer and tick
reg [nTEMPSAMP_CNTR_WIDTH-1:0] sample_timer = {nTEMPSAMP_CNTR_WIDTH{1'b0}};
reg sample_timer_en = 1'b0;
reg sample_timer_clr = 1'b0;
reg sample_en = 1'b0;
// Temperature sampler state
reg [2:0] tempmon_state = INIT_IDLE;
reg [2:0] tempmon_next_state = INIT_IDLE;
// XADC interfacing
reg xadc_den = 1'b0;
wire xadc_drdy;
wire [15:0] xadc_do;
reg xadc_drdy_r = 1'b0;
reg [15:0] xadc_do_r = 1'b0;
// Temperature storage
reg [11:0] temperature = 12'b0;
// Reset sync
(* ASYNC_REG = "TRUE" *) reg rst_r1;
(* ASYNC_REG = "TRUE" *) reg rst_r2;
// Synchronization rst to XADC clock domain
always @(posedge xadc_clk) begin
rst_r1 <= rst;
rst_r2 <= rst_r1;
end
// XADC polling interval timer
always @ (posedge xadc_clk)
if(rst_r2 || sample_timer_clr)
sample_timer <= #TCQ {nTEMPSAMP_CNTR_WIDTH{1'b0}};
else if(sample_timer_en)
sample_timer <= #TCQ sample_timer + 1'b1;
// XADC sampler state transition
always @(posedge xadc_clk)
if(rst_r2)
tempmon_state <= #TCQ INIT_IDLE;
else
tempmon_state <= #TCQ tempmon_next_state;
// Sample enable
always @(posedge xadc_clk)
sample_en <= #TCQ (sample_timer == nTEMPSAMP_CLKS_M6) ? 1'b1 : 1'b0;
// XADC sampler next state transition
always @(tempmon_state or sample_en or xadc_drdy_r) begin
tempmon_next_state = tempmon_state;
case(tempmon_state)
INIT_IDLE:
if(sample_en)
tempmon_next_state = REQUEST_READ_TEMP;
REQUEST_READ_TEMP:
tempmon_next_state = WAIT_FOR_READ;
WAIT_FOR_READ:
if(xadc_drdy_r)
tempmon_next_state = READ;
READ:
tempmon_next_state = INIT_IDLE;
default:
tempmon_next_state = INIT_IDLE;
endcase
end
// Sample timer clear
always @(posedge xadc_clk)
if(rst_r2 || (tempmon_state == WAIT_FOR_READ))
sample_timer_clr <= #TCQ 1'b0;
else if(tempmon_state == REQUEST_READ_TEMP)
sample_timer_clr <= #TCQ 1'b1;
// Sample timer enable
always @(posedge xadc_clk)
if(rst_r2 || (tempmon_state == REQUEST_READ_TEMP))
sample_timer_en <= #TCQ 1'b0;
else if((tempmon_state == INIT_IDLE) || (tempmon_state == READ))
sample_timer_en <= #TCQ 1'b1;
// XADC enable
always @(posedge xadc_clk)
if(rst_r2 || (tempmon_state == WAIT_FOR_READ))
xadc_den <= #TCQ 1'b0;
else if(tempmon_state == REQUEST_READ_TEMP)
xadc_den <= #TCQ 1'b1;
// Register XADC outputs
always @(posedge xadc_clk)
if(rst_r2) begin
xadc_drdy_r <= #TCQ 1'b0;
xadc_do_r <= #TCQ 16'b0;
end
else begin
xadc_drdy_r <= #TCQ xadc_drdy;
xadc_do_r <= #TCQ xadc_do;
end
// Store current read value
always @(posedge xadc_clk)
if(rst_r2)
temperature <= #TCQ 12'b0;
else if(tempmon_state == READ)
temperature <= #TCQ xadc_do_r[15:4];
assign device_temp_lcl = temperature;
// XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter
// 7 Series
// Xilinx HDL Libraries Guide, version 14.1
XADC #(
// INIT_40 - INIT_42: XADC configuration registers
.INIT_40(16'h8000), // config reg 0
.INIT_41(16'h3f0f), // config reg 1
.INIT_42(16'h0400), // config reg 2
// INIT_48 - INIT_4F: Sequence Registers
.INIT_48(16'h0100), // Sequencer channel selection
.INIT_49(16'h0000), // Sequencer channel selection
.INIT_4A(16'h0000), // Sequencer Average selection
.INIT_4B(16'h0000), // Sequencer Average selection
.INIT_4C(16'h0000), // Sequencer Bipolar selection
.INIT_4D(16'h0000), // Sequencer Bipolar selection
.INIT_4E(16'h0000), // Sequencer Acq time selection
.INIT_4F(16'h0000), // Sequencer Acq time selection
// INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
.INIT_50(16'hb5ed), // Temp alarm trigger
.INIT_51(16'h57e4), // Vccint upper alarm limit
.INIT_52(16'ha147), // Vccaux upper alarm limit
.INIT_53(16'hca33), // Temp alarm OT upper
.INIT_54(16'ha93a), // Temp alarm reset
.INIT_55(16'h52c6), // Vccint lower alarm limit
.INIT_56(16'h9555), // Vccaux lower alarm limit
.INIT_57(16'hae4e), // Temp alarm OT reset
.INIT_58(16'h5999), // VBRAM upper alarm limit
.INIT_5C(16'h5111), // VBRAM lower alarm limit
// Simulation attributes: Set for proepr simulation behavior
.SIM_DEVICE("7SERIES") // Select target device (values)
)
XADC_inst (
// ALARMS: 8-bit (each) output: ALM, OT
.ALM(), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
.OT(), // 1-bit output: Over-Temperature alarm
// Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports
.DO(xadc_do), // 16-bit output: DRP output data bus
.DRDY(xadc_drdy), // 1-bit output: DRP data ready
// STATUS: 1-bit (each) output: XADC status ports
.BUSY(), // 1-bit output: ADC busy output
.CHANNEL(), // 5-bit output: Channel selection outputs
.EOC(), // 1-bit output: End of Conversion
.EOS(), // 1-bit output: End of Sequence
.JTAGBUSY(), // 1-bit output: JTAG DRP transaction in progress output
.JTAGLOCKED(), // 1-bit output: JTAG requested DRP port lock
.JTAGMODIFIED(), // 1-bit output: JTAG Write to the DRP has occurred
.MUXADDR(), // 5-bit output: External MUX channel decode
// Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
.VAUXN(16'b0), // 16-bit input: N-side auxiliary analog input
.VAUXP(16'b0), // 16-bit input: P-side auxiliary analog input
// CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs
.CONVST(1'b0), // 1-bit input: Convert start input
.CONVSTCLK(1'b0), // 1-bit input: Convert start input
.RESET(1'b0), // 1-bit input: Active-high reset
// Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
.VN(1'b0), // 1-bit input: N-side analog input
.VP(1'b0), // 1-bit input: P-side analog input
// Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports
.DADDR(7'b0), // 7-bit input: DRP address bus
.DCLK(xadc_clk), // 1-bit input: DRP clock
.DEN(xadc_den), // 1-bit input: DRP enable signal
.DI(16'b0), // 16-bit input: DRP input data bus
.DWE(1'b0) // 1-bit input: DRP write enable
);
// End of XADC_inst instantiation
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_wr_data.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// User interface write data buffer. Consists of four counters,
// a pointer RAM and the write data storage RAM.
//
// All RAMs are implemented with distributed RAM.
//
// Whe ordering is set to STRICT or NORM, data moves through
// the write data buffer in strictly FIFO order. In RELAXED
// mode, data may be retired from the write data RAM in any
// order relative to the input order. This implementation
// supports all ordering modes.
//
// The pointer RAM stores a list of pointers to the write data storage RAM.
// This is a list of vacant entries. As data is written into the RAM, a
// pointer is pulled from the pointer RAM and used to index the write
// operation. In a semi autonomously manner, pointers are also pulled, in
// the same order, and provided to the command port as the data_buf_addr.
//
// When the MC reads data from the write data buffer, it uses the
// data_buf_addr provided with the command to extract the data from the
// write data buffer. It also writes this pointer into the end
// of the pointer RAM.
//
// The occupancy counter keeps track of how many entries are valid
// in the write data storage RAM. app_wdf_rdy and app_rdy will be
// de-asserted when there is no more storage in the write data buffer.
//
// Three sequentially incrementing counters/indexes are used to maintain
// and use the contents of the pointer RAM.
//
// The write buffer write data address index generates the pointer
// used to extract the write data address from the pointer RAM. It
// is incremented with each buffer write. The counter is actually one
// ahead of the current write address so that the actual data buffer
// write address can be registered to give a full state to propagate to
// the write data distributed RAMs.
//
// The data_buf_addr counter is used to extract the data_buf_addr for
// the command port. It is incremented as each command is written
// into the MC.
//
// The read data index points to the end of the list of free
// buffers. When the MC fetches data from the write data buffer, it
// provides the buffer address. The buffer address is used to fetch
// the data, but is also written into the pointer at the location indicated
// by the read data index.
//
// Enter and exiting a buffer full condition generates corner cases. Upon
// entering a full condition, incrementing the write buffer write data
// address index must be inhibited. When exiting the full condition,
// the just arrived pointer must propagate through the pointer RAM, then
// indexed by the current value of the write buffer write data
// address counter, the value is registered in the write buffer write
// data address register, then the counter can be advanced.
//
// The pointer RAM must be initialized with valid data after reset. This is
// accomplished by stepping through each pointer RAM entry and writing
// the locations address into the pointer RAM. For the FIFO modes, this means
// that buffer address will always proceed in a sequential order. In the
// RELAXED mode, the original write traversal will be in sequential
// order, but once the MC begins to retire out of order, the entries in
// the pointer RAM will become randomized. The ui_rd_data module provides
// the control information for the initialization process.
`timescale 1 ps / 1 ps
module mig_7series_v1_9_ui_wr_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ECC_TEST = "OFF",
parameter CWL = 5
)
(/*AUTOARG*/
// Outputs
app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask,
raw_not_ecc,
// Inputs
rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren,
app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted,
ram_init_done_r, ram_init_addr
);
input rst;
input clk;
input [APP_DATA_WIDTH-1:0] app_wdf_data;
input [APP_MASK_WIDTH-1:0] app_wdf_mask;
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc;
input app_wdf_wren;
input app_wdf_end;
reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1;
reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1;
reg [2*nCK_PER_CLK-1:0] app_raw_not_ecc_r1 = 4'b0;
reg app_wdf_wren_r1;
reg app_wdf_end_r1;
reg app_wdf_rdy_r;
//Adding few copies of the app_wdf_rdy_r signal in order to meet
//timing. This is signal has a very high fanout. So grouped into
//few functional groups and alloted one copy per group.
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy1;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy2;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy3;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy4;
wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask;
wire app_wdf_wren_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren);
wire app_wdf_end_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end);
generate
if (ECC_TEST != "OFF") begin : ecc_on
always @(app_raw_not_ecc) app_raw_not_ecc_r1 = app_raw_not_ecc;
end
endgenerate
// Be explicit about the latch enable on these registers.
always @(posedge clk) begin
app_wdf_data_r1 <= #TCQ app_wdf_data_ns1;
app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1;
app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1;
app_wdf_end_r1 <= #TCQ app_wdf_end_ns1;
end
// The signals wr_data_addr and wr_data_offset come at different
// times depending on ECC and the value of CWL. The data portion
// always needs to look a the raw wires, the control portion needs
// to look at a delayed version when ECC is on and CWL != 8. The
// currently supported write data delays do not require this
// functionality, but preserve for future use.
input wr_data_offset;
input [3:0] wr_data_addr;
reg wr_data_offset_r;
reg [3:0] wr_data_addr_r;
generate
if (ECC == "OFF" || CWL >= 0) begin : pass_wr_addr
always @(wr_data_offset) wr_data_offset_r = wr_data_offset;
always @(wr_data_addr) wr_data_addr_r = wr_data_addr;
end
else begin : delay_wr_addr
always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset;
always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr;
end
endgenerate
// rd_data_cnt is the pointer RAM index for data read from the write data
// buffer. Ie, its the data on its way out to the DRAM.
input wr_data_en;
wire new_rd_data = wr_data_en && ~wr_data_offset_r;
reg [3:0] rd_data_indx_r;
reg rd_data_upd_indx_r;
generate begin : read_data_indx
reg [3:0] rd_data_indx_ns;
always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin
rd_data_indx_ns = rd_data_indx_r;
if (rst) rd_data_indx_ns = 5'b0;
else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1;
end
always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns;
always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data;
end
endgenerate
// data_buf_addr_cnt generates the pointer for the pointer RAM on behalf
// of data buf address that comes with the wr_data_en.
// The data buf address is written into the memory
// controller along with the command and address.
input wr_accepted;
reg [3:0] data_buf_addr_cnt_r;
generate begin : data_buf_address_counter
reg [3:0] data_buf_addr_cnt_ns;
always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin
data_buf_addr_cnt_ns = data_buf_addr_cnt_r;
if (rst) data_buf_addr_cnt_ns = 4'b0;
else if (wr_accepted) data_buf_addr_cnt_ns =
data_buf_addr_cnt_r + 4'h1;
end
always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns;
end
endgenerate
// Control writing data into the write data buffer.
wire wdf_rdy_ns;
always @( posedge clk ) begin
app_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns;
end
wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1;
wire [3:0] wr_data_pntr;
wire [4:0] wb_wr_data_addr;
wire [4:0] wb_wr_data_addr_w;
reg [3:0] wr_data_indx_r;
generate begin : write_data_control
wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) ||
(rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1);
// For pointer RAM. Initialize to one since this is one ahead of
// what's being registered in wb_wr_data_addr. Assumes pointer RAM
// has been initialized such that address equals contents.
reg [3:0] wr_data_indx_ns;
always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin
wr_data_indx_ns = wr_data_indx_r;
if (rst) wr_data_indx_ns = 4'b1;
else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1;
end
always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns;
// Take pointer from pointer RAM and set into the write data address.
// Needs to be split into zeroth bit and everything else because synthesis
// tools don't always allow assigning bit vectors seperately. Bit zero of the
// address is computed via an entirely different algorithm.
reg [4:1] wb_wr_data_addr_ns;
reg [4:1] wb_wr_data_addr_r;
always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le
or wr_data_pntr) begin
wb_wr_data_addr_ns = wb_wr_data_addr_r;
if (rst) wb_wr_data_addr_ns = 4'b0;
else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr;
end
always @(posedge clk) wb_wr_data_addr_r <= #TCQ wb_wr_data_addr_ns;
// If we see the first getting accepted, then
// second half is unconditionally accepted.
reg wb_wr_data_addr0_r;
wire wb_wr_data_addr0_ns = ~rst &&
((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) ||
(wb_wr_data_addr0_r && ~app_wdf_wren_r1));
always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns;
assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r};
assign wb_wr_data_addr_w = {wb_wr_data_addr_ns, wb_wr_data_addr0_ns};
end
endgenerate
// Keep track of how many entries in the queue hold data.
input ram_init_done_r;
output wire app_wdf_rdy;
generate begin : occupied_counter
//reg [4:0] occ_cnt_ns;
//reg [4:0] occ_cnt_r;
//always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst
// or wr_data_end) begin
// occ_cnt_ns = occ_cnt_r;
// if (rst) occ_cnt_ns = 5'b0;
// else case ({wr_data_end, rd_data_upd_indx_r})
// 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1;
// 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1;
// endcase // case ({wr_data_end, rd_data_upd_indx_r})
//end
//always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
//assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]);
//always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
//assign app_wdf_rdy = app_wdf_rdy_r;
reg [15:0] occ_cnt;
always @(posedge clk) begin
if ( rst )
occ_cnt <= #TCQ 16'h0000;
else case ({wr_data_end, rd_data_upd_indx_r})
2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]};
2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1};
endcase // case ({wr_data_end, rd_data_upd_indx_r})
end
assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r));
always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
assign app_wdf_rdy = app_wdf_rdy_r;
`ifdef MC_SVA
wr_data_buffer_full: cover property (@(posedge clk)
(~rst && ~app_wdf_rdy_r));
// wr_data_buffer_inc_dec_15: cover property (@(posedge clk)
// (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf)));
// wr_data_underflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f))));
// wr_data_overflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11))));
`endif
end // block: occupied_counter
endgenerate
// Keep track of how many write requests are in the memory controller. We
// must limit this to 16 because we only have that many data_buf_addrs to
// hand out. Since the memory controller queue and the write data buffer
// queue are distinct, the number of valid entries can be different.
// Throttle request acceptance once there are sixteen write requests in
// the memory controller. Note that there is still a requirement
// for a write reqeusts corresponding write data to be written into the
// write data queue with two states of the request.
output wire wr_req_16;
generate begin : wr_req_counter
reg [4:0] wr_req_cnt_ns;
reg [4:0] wr_req_cnt_r;
always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted
or wr_req_cnt_r) begin
wr_req_cnt_ns = wr_req_cnt_r;
if (rst) wr_req_cnt_ns = 5'b0;
else case ({wr_accepted, rd_data_upd_indx_r})
2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1;
2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1;
endcase // case ({wr_accepted, rd_data_upd_indx_r})
end
always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns;
assign wr_req_16 = (wr_req_cnt_ns == 5'h10);
`ifdef MC_SVA
wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16));
wr_req_mc_full_inc_dec_15: cover property (@(posedge clk)
(~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf)));
wr_req_underflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f))));
wr_req_overflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11))));
`endif
end // block: wr_req_counter
endgenerate
// Instantiate pointer RAM. Made up of RAM32M in single write, two read
// port mode, 2 bit wide mode.
input [3:0] ram_init_addr;
output wire [3:0] wr_data_buf_addr;
localparam PNTR_RAM_CNT = 2;
generate begin : pointer_ram
wire pointer_we = new_rd_data || ~ram_init_done_r;
wire [3:0] pointer_wr_data = ram_init_done_r
? wr_data_addr_r
: ram_init_addr;
wire [3:0] pointer_wr_addr = ram_init_done_r
? rd_data_indx_r
: ram_init_addr;
genvar i;
for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(),
.DOB(wr_data_buf_addr[i*2+:2]),
.DOC(wr_data_pntr[i*2+:2]),
.DOD(),
.DIA(2'b0),
.DIB(pointer_wr_data[i*2+:2]),
.DIC(pointer_wr_data[i*2+:2]),
.DID(2'b0),
.ADDRA(5'b0),
.ADDRB({1'b0, data_buf_addr_cnt_r}),
.ADDRC({1'b0, wr_data_indx_r}),
.ADDRD({1'b0, pointer_wr_addr}),
.WE(pointer_we),
.WCLK(clk)
);
end // block : rams
end // block: pointer_ram
endgenerate
// Instantiate write data buffer. Depending on width of DQ bus and
// DRAM CK to fabric ratio, number of RAM32Ms is variable. RAM32Ms are
// used in single write, single read, 6 bit wide mode.
localparam WR_BUF_WIDTH =
APP_DATA_WIDTH + APP_MASK_WIDTH + (ECC_TEST == "OFF" ? 0 : 2*nCK_PER_CLK);
localparam FULL_RAM_CNT = (WR_BUF_WIDTH/6);
localparam REMAINDER = WR_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] wr_buf_out_data_w;
reg [RAM_WIDTH-1:0] wr_buf_out_data;
generate
begin : write_buffer
wire [RAM_WIDTH-1:0] wr_buf_in_data;
if (REMAINDER == 0)
if (ECC_TEST == "OFF")
assign wr_buf_in_data = {app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data =
{app_raw_not_ecc_r1, app_wdf_mask_ns1, app_wdf_data_ns1};
else
if (ECC_TEST == "OFF")
assign wr_buf_in_data =
{{6-REMAINDER{1'b0}}, app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data = {{6-REMAINDER{1'b0}}, app_raw_not_ecc_r1,//app_raw_not_ecc_r1 is not ff
app_wdf_mask_ns1, app_wdf_data_ns1};
wire [4:0] rd_addr_w;
assign rd_addr_w = {wr_data_addr, wr_data_offset};
always @(posedge clk) wr_buf_out_data <= #TCQ wr_buf_out_data_w;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : wr_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(wr_buf_out_data_w[((i*6)+4)+:2]),
.DOB(wr_buf_out_data_w[((i*6)+2)+:2]),
.DOC(wr_buf_out_data_w[((i*6)+0)+:2]),
.DOD(),
.DIA(wr_buf_in_data[((i*6)+4)+:2]),
.DIB(wr_buf_in_data[((i*6)+2)+:2]),
.DIC(wr_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_addr_w),
.ADDRB(rd_addr_w),
.ADDRC(rd_addr_w),
.ADDRD(wb_wr_data_addr_w),
.WE(wdf_rdy_ns),
.WCLK(clk)
);
end // block: wr_buffer_ram
end
endgenerate
output [APP_DATA_WIDTH-1:0] wr_data;
output [APP_MASK_WIDTH-1:0] wr_data_mask;
assign {wr_data_mask, wr_data} = wr_buf_out_data[WR_BUF_WIDTH-1:0];
output [2*nCK_PER_CLK-1:0] raw_not_ecc;
generate
if (ECC_TEST == "OFF") assign raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
else assign raw_not_ecc = wr_buf_out_data[WR_BUF_WIDTH-1-:4];
endgenerate
endmodule // ui_wr_data
// Local Variables:
// verilog-library-directories:(".")
// End:
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
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// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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// applications related to the deployment of airbags, or any
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// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_wr_data.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// User interface write data buffer. Consists of four counters,
// a pointer RAM and the write data storage RAM.
//
// All RAMs are implemented with distributed RAM.
//
// Whe ordering is set to STRICT or NORM, data moves through
// the write data buffer in strictly FIFO order. In RELAXED
// mode, data may be retired from the write data RAM in any
// order relative to the input order. This implementation
// supports all ordering modes.
//
// The pointer RAM stores a list of pointers to the write data storage RAM.
// This is a list of vacant entries. As data is written into the RAM, a
// pointer is pulled from the pointer RAM and used to index the write
// operation. In a semi autonomously manner, pointers are also pulled, in
// the same order, and provided to the command port as the data_buf_addr.
//
// When the MC reads data from the write data buffer, it uses the
// data_buf_addr provided with the command to extract the data from the
// write data buffer. It also writes this pointer into the end
// of the pointer RAM.
//
// The occupancy counter keeps track of how many entries are valid
// in the write data storage RAM. app_wdf_rdy and app_rdy will be
// de-asserted when there is no more storage in the write data buffer.
//
// Three sequentially incrementing counters/indexes are used to maintain
// and use the contents of the pointer RAM.
//
// The write buffer write data address index generates the pointer
// used to extract the write data address from the pointer RAM. It
// is incremented with each buffer write. The counter is actually one
// ahead of the current write address so that the actual data buffer
// write address can be registered to give a full state to propagate to
// the write data distributed RAMs.
//
// The data_buf_addr counter is used to extract the data_buf_addr for
// the command port. It is incremented as each command is written
// into the MC.
//
// The read data index points to the end of the list of free
// buffers. When the MC fetches data from the write data buffer, it
// provides the buffer address. The buffer address is used to fetch
// the data, but is also written into the pointer at the location indicated
// by the read data index.
//
// Enter and exiting a buffer full condition generates corner cases. Upon
// entering a full condition, incrementing the write buffer write data
// address index must be inhibited. When exiting the full condition,
// the just arrived pointer must propagate through the pointer RAM, then
// indexed by the current value of the write buffer write data
// address counter, the value is registered in the write buffer write
// data address register, then the counter can be advanced.
//
// The pointer RAM must be initialized with valid data after reset. This is
// accomplished by stepping through each pointer RAM entry and writing
// the locations address into the pointer RAM. For the FIFO modes, this means
// that buffer address will always proceed in a sequential order. In the
// RELAXED mode, the original write traversal will be in sequential
// order, but once the MC begins to retire out of order, the entries in
// the pointer RAM will become randomized. The ui_rd_data module provides
// the control information for the initialization process.
`timescale 1 ps / 1 ps
module mig_7series_v1_9_ui_wr_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ECC_TEST = "OFF",
parameter CWL = 5
)
(/*AUTOARG*/
// Outputs
app_wdf_rdy, wr_req_16, wr_data_buf_addr, wr_data, wr_data_mask,
raw_not_ecc,
// Inputs
rst, clk, app_wdf_data, app_wdf_mask, app_raw_not_ecc, app_wdf_wren,
app_wdf_end, wr_data_offset, wr_data_addr, wr_data_en, wr_accepted,
ram_init_done_r, ram_init_addr
);
input rst;
input clk;
input [APP_DATA_WIDTH-1:0] app_wdf_data;
input [APP_MASK_WIDTH-1:0] app_wdf_mask;
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc;
input app_wdf_wren;
input app_wdf_end;
reg [APP_DATA_WIDTH-1:0] app_wdf_data_r1;
reg [APP_MASK_WIDTH-1:0] app_wdf_mask_r1;
reg [2*nCK_PER_CLK-1:0] app_raw_not_ecc_r1 = 4'b0;
reg app_wdf_wren_r1;
reg app_wdf_end_r1;
reg app_wdf_rdy_r;
//Adding few copies of the app_wdf_rdy_r signal in order to meet
//timing. This is signal has a very high fanout. So grouped into
//few functional groups and alloted one copy per group.
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy1;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy2;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy3;
(* equivalent_register_removal = "no" *)
reg app_wdf_rdy_r_copy4;
wire [APP_DATA_WIDTH-1:0] app_wdf_data_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_data_r1 : app_wdf_data;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask_ns1 =
~app_wdf_rdy_r_copy2 ? app_wdf_mask_r1 : app_wdf_mask;
wire app_wdf_wren_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_wren_r1 : app_wdf_wren);
wire app_wdf_end_ns1 =
~rst && (~app_wdf_rdy_r_copy2 ? app_wdf_end_r1 : app_wdf_end);
generate
if (ECC_TEST != "OFF") begin : ecc_on
always @(app_raw_not_ecc) app_raw_not_ecc_r1 = app_raw_not_ecc;
end
endgenerate
// Be explicit about the latch enable on these registers.
always @(posedge clk) begin
app_wdf_data_r1 <= #TCQ app_wdf_data_ns1;
app_wdf_mask_r1 <= #TCQ app_wdf_mask_ns1;
app_wdf_wren_r1 <= #TCQ app_wdf_wren_ns1;
app_wdf_end_r1 <= #TCQ app_wdf_end_ns1;
end
// The signals wr_data_addr and wr_data_offset come at different
// times depending on ECC and the value of CWL. The data portion
// always needs to look a the raw wires, the control portion needs
// to look at a delayed version when ECC is on and CWL != 8. The
// currently supported write data delays do not require this
// functionality, but preserve for future use.
input wr_data_offset;
input [3:0] wr_data_addr;
reg wr_data_offset_r;
reg [3:0] wr_data_addr_r;
generate
if (ECC == "OFF" || CWL >= 0) begin : pass_wr_addr
always @(wr_data_offset) wr_data_offset_r = wr_data_offset;
always @(wr_data_addr) wr_data_addr_r = wr_data_addr;
end
else begin : delay_wr_addr
always @(posedge clk) wr_data_offset_r <= #TCQ wr_data_offset;
always @(posedge clk) wr_data_addr_r <= #TCQ wr_data_addr;
end
endgenerate
// rd_data_cnt is the pointer RAM index for data read from the write data
// buffer. Ie, its the data on its way out to the DRAM.
input wr_data_en;
wire new_rd_data = wr_data_en && ~wr_data_offset_r;
reg [3:0] rd_data_indx_r;
reg rd_data_upd_indx_r;
generate begin : read_data_indx
reg [3:0] rd_data_indx_ns;
always @(/*AS*/new_rd_data or rd_data_indx_r or rst) begin
rd_data_indx_ns = rd_data_indx_r;
if (rst) rd_data_indx_ns = 5'b0;
else if (new_rd_data) rd_data_indx_ns = rd_data_indx_r + 5'h1;
end
always @(posedge clk) rd_data_indx_r <= #TCQ rd_data_indx_ns;
always @(posedge clk) rd_data_upd_indx_r <= #TCQ new_rd_data;
end
endgenerate
// data_buf_addr_cnt generates the pointer for the pointer RAM on behalf
// of data buf address that comes with the wr_data_en.
// The data buf address is written into the memory
// controller along with the command and address.
input wr_accepted;
reg [3:0] data_buf_addr_cnt_r;
generate begin : data_buf_address_counter
reg [3:0] data_buf_addr_cnt_ns;
always @(/*AS*/data_buf_addr_cnt_r or rst or wr_accepted) begin
data_buf_addr_cnt_ns = data_buf_addr_cnt_r;
if (rst) data_buf_addr_cnt_ns = 4'b0;
else if (wr_accepted) data_buf_addr_cnt_ns =
data_buf_addr_cnt_r + 4'h1;
end
always @(posedge clk) data_buf_addr_cnt_r <= #TCQ data_buf_addr_cnt_ns;
end
endgenerate
// Control writing data into the write data buffer.
wire wdf_rdy_ns;
always @( posedge clk ) begin
app_wdf_rdy_r_copy1 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy2 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy3 <= #TCQ wdf_rdy_ns;
app_wdf_rdy_r_copy4 <= #TCQ wdf_rdy_ns;
end
wire wr_data_end = app_wdf_end_r1 && app_wdf_rdy_r_copy1 && app_wdf_wren_r1;
wire [3:0] wr_data_pntr;
wire [4:0] wb_wr_data_addr;
wire [4:0] wb_wr_data_addr_w;
reg [3:0] wr_data_indx_r;
generate begin : write_data_control
wire wr_data_addr_le = (wr_data_end && wdf_rdy_ns) ||
(rd_data_upd_indx_r && ~app_wdf_rdy_r_copy1);
// For pointer RAM. Initialize to one since this is one ahead of
// what's being registered in wb_wr_data_addr. Assumes pointer RAM
// has been initialized such that address equals contents.
reg [3:0] wr_data_indx_ns;
always @(/*AS*/rst or wr_data_addr_le or wr_data_indx_r) begin
wr_data_indx_ns = wr_data_indx_r;
if (rst) wr_data_indx_ns = 4'b1;
else if (wr_data_addr_le) wr_data_indx_ns = wr_data_indx_r + 4'h1;
end
always @(posedge clk) wr_data_indx_r <= #TCQ wr_data_indx_ns;
// Take pointer from pointer RAM and set into the write data address.
// Needs to be split into zeroth bit and everything else because synthesis
// tools don't always allow assigning bit vectors seperately. Bit zero of the
// address is computed via an entirely different algorithm.
reg [4:1] wb_wr_data_addr_ns;
reg [4:1] wb_wr_data_addr_r;
always @(/*AS*/rst or wb_wr_data_addr_r or wr_data_addr_le
or wr_data_pntr) begin
wb_wr_data_addr_ns = wb_wr_data_addr_r;
if (rst) wb_wr_data_addr_ns = 4'b0;
else if (wr_data_addr_le) wb_wr_data_addr_ns = wr_data_pntr;
end
always @(posedge clk) wb_wr_data_addr_r <= #TCQ wb_wr_data_addr_ns;
// If we see the first getting accepted, then
// second half is unconditionally accepted.
reg wb_wr_data_addr0_r;
wire wb_wr_data_addr0_ns = ~rst &&
((app_wdf_rdy_r_copy3 && app_wdf_wren_r1 && ~app_wdf_end_r1) ||
(wb_wr_data_addr0_r && ~app_wdf_wren_r1));
always @(posedge clk) wb_wr_data_addr0_r <= #TCQ wb_wr_data_addr0_ns;
assign wb_wr_data_addr = {wb_wr_data_addr_r, wb_wr_data_addr0_r};
assign wb_wr_data_addr_w = {wb_wr_data_addr_ns, wb_wr_data_addr0_ns};
end
endgenerate
// Keep track of how many entries in the queue hold data.
input ram_init_done_r;
output wire app_wdf_rdy;
generate begin : occupied_counter
//reg [4:0] occ_cnt_ns;
//reg [4:0] occ_cnt_r;
//always @(/*AS*/occ_cnt_r or rd_data_upd_indx_r or rst
// or wr_data_end) begin
// occ_cnt_ns = occ_cnt_r;
// if (rst) occ_cnt_ns = 5'b0;
// else case ({wr_data_end, rd_data_upd_indx_r})
// 2'b01 : occ_cnt_ns = occ_cnt_r - 5'b1;
// 2'b10 : occ_cnt_ns = occ_cnt_r + 5'b1;
// endcase // case ({wr_data_end, rd_data_upd_indx_r})
//end
//always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
//assign wdf_rdy_ns = !(rst || ~ram_init_done_r || occ_cnt_ns[4]);
//always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
//assign app_wdf_rdy = app_wdf_rdy_r;
reg [15:0] occ_cnt;
always @(posedge clk) begin
if ( rst )
occ_cnt <= #TCQ 16'h0000;
else case ({wr_data_end, rd_data_upd_indx_r})
2'b01 : occ_cnt <= #TCQ {1'b0,occ_cnt[15:1]};
2'b10 : occ_cnt <= #TCQ {occ_cnt[14:0],1'b1};
endcase // case ({wr_data_end, rd_data_upd_indx_r})
end
assign wdf_rdy_ns = !(rst || ~ram_init_done_r || (occ_cnt[14] && wr_data_end && ~rd_data_upd_indx_r) || (occ_cnt[15] && ~rd_data_upd_indx_r));
always @(posedge clk) app_wdf_rdy_r <= #TCQ wdf_rdy_ns;
assign app_wdf_rdy = app_wdf_rdy_r;
`ifdef MC_SVA
wr_data_buffer_full: cover property (@(posedge clk)
(~rst && ~app_wdf_rdy_r));
// wr_data_buffer_inc_dec_15: cover property (@(posedge clk)
// (~rst && wr_data_end && rd_data_upd_indx_r && (occ_cnt_r == 5'hf)));
// wr_data_underflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'b0) && (occ_cnt_ns == 5'h1f))));
// wr_data_overflow: assert property (@(posedge clk)
// (rst || !((occ_cnt_r == 5'h10) && (occ_cnt_ns == 5'h11))));
`endif
end // block: occupied_counter
endgenerate
// Keep track of how many write requests are in the memory controller. We
// must limit this to 16 because we only have that many data_buf_addrs to
// hand out. Since the memory controller queue and the write data buffer
// queue are distinct, the number of valid entries can be different.
// Throttle request acceptance once there are sixteen write requests in
// the memory controller. Note that there is still a requirement
// for a write reqeusts corresponding write data to be written into the
// write data queue with two states of the request.
output wire wr_req_16;
generate begin : wr_req_counter
reg [4:0] wr_req_cnt_ns;
reg [4:0] wr_req_cnt_r;
always @(/*AS*/rd_data_upd_indx_r or rst or wr_accepted
or wr_req_cnt_r) begin
wr_req_cnt_ns = wr_req_cnt_r;
if (rst) wr_req_cnt_ns = 5'b0;
else case ({wr_accepted, rd_data_upd_indx_r})
2'b01 : wr_req_cnt_ns = wr_req_cnt_r - 5'b1;
2'b10 : wr_req_cnt_ns = wr_req_cnt_r + 5'b1;
endcase // case ({wr_accepted, rd_data_upd_indx_r})
end
always @(posedge clk) wr_req_cnt_r <= #TCQ wr_req_cnt_ns;
assign wr_req_16 = (wr_req_cnt_ns == 5'h10);
`ifdef MC_SVA
wr_req_mc_full: cover property (@(posedge clk) (~rst && wr_req_16));
wr_req_mc_full_inc_dec_15: cover property (@(posedge clk)
(~rst && wr_accepted && rd_data_upd_indx_r && (wr_req_cnt_r == 5'hf)));
wr_req_underflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'b0) && (wr_req_cnt_ns == 5'h1f))));
wr_req_overflow: assert property (@(posedge clk)
(rst || !((wr_req_cnt_r == 5'h10) && (wr_req_cnt_ns == 5'h11))));
`endif
end // block: wr_req_counter
endgenerate
// Instantiate pointer RAM. Made up of RAM32M in single write, two read
// port mode, 2 bit wide mode.
input [3:0] ram_init_addr;
output wire [3:0] wr_data_buf_addr;
localparam PNTR_RAM_CNT = 2;
generate begin : pointer_ram
wire pointer_we = new_rd_data || ~ram_init_done_r;
wire [3:0] pointer_wr_data = ram_init_done_r
? wr_data_addr_r
: ram_init_addr;
wire [3:0] pointer_wr_addr = ram_init_done_r
? rd_data_indx_r
: ram_init_addr;
genvar i;
for (i=0; i<PNTR_RAM_CNT; i=i+1) begin : rams
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(),
.DOB(wr_data_buf_addr[i*2+:2]),
.DOC(wr_data_pntr[i*2+:2]),
.DOD(),
.DIA(2'b0),
.DIB(pointer_wr_data[i*2+:2]),
.DIC(pointer_wr_data[i*2+:2]),
.DID(2'b0),
.ADDRA(5'b0),
.ADDRB({1'b0, data_buf_addr_cnt_r}),
.ADDRC({1'b0, wr_data_indx_r}),
.ADDRD({1'b0, pointer_wr_addr}),
.WE(pointer_we),
.WCLK(clk)
);
end // block : rams
end // block: pointer_ram
endgenerate
// Instantiate write data buffer. Depending on width of DQ bus and
// DRAM CK to fabric ratio, number of RAM32Ms is variable. RAM32Ms are
// used in single write, single read, 6 bit wide mode.
localparam WR_BUF_WIDTH =
APP_DATA_WIDTH + APP_MASK_WIDTH + (ECC_TEST == "OFF" ? 0 : 2*nCK_PER_CLK);
localparam FULL_RAM_CNT = (WR_BUF_WIDTH/6);
localparam REMAINDER = WR_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] wr_buf_out_data_w;
reg [RAM_WIDTH-1:0] wr_buf_out_data;
generate
begin : write_buffer
wire [RAM_WIDTH-1:0] wr_buf_in_data;
if (REMAINDER == 0)
if (ECC_TEST == "OFF")
assign wr_buf_in_data = {app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data =
{app_raw_not_ecc_r1, app_wdf_mask_ns1, app_wdf_data_ns1};
else
if (ECC_TEST == "OFF")
assign wr_buf_in_data =
{{6-REMAINDER{1'b0}}, app_wdf_mask_ns1, app_wdf_data_ns1};
else
assign wr_buf_in_data = {{6-REMAINDER{1'b0}}, app_raw_not_ecc_r1,//app_raw_not_ecc_r1 is not ff
app_wdf_mask_ns1, app_wdf_data_ns1};
wire [4:0] rd_addr_w;
assign rd_addr_w = {wr_data_addr, wr_data_offset};
always @(posedge clk) wr_buf_out_data <= #TCQ wr_buf_out_data_w;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : wr_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(wr_buf_out_data_w[((i*6)+4)+:2]),
.DOB(wr_buf_out_data_w[((i*6)+2)+:2]),
.DOC(wr_buf_out_data_w[((i*6)+0)+:2]),
.DOD(),
.DIA(wr_buf_in_data[((i*6)+4)+:2]),
.DIB(wr_buf_in_data[((i*6)+2)+:2]),
.DIC(wr_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_addr_w),
.ADDRB(rd_addr_w),
.ADDRC(rd_addr_w),
.ADDRD(wb_wr_data_addr_w),
.WE(wdf_rdy_ns),
.WCLK(clk)
);
end // block: wr_buffer_ram
end
endgenerate
output [APP_DATA_WIDTH-1:0] wr_data;
output [APP_MASK_WIDTH-1:0] wr_data_mask;
assign {wr_data_mask, wr_data} = wr_buf_out_data[WR_BUF_WIDTH-1:0];
output [2*nCK_PER_CLK-1:0] raw_not_ecc;
generate
if (ECC_TEST == "OFF") assign raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
else assign raw_not_ecc = wr_buf_out_data[WR_BUF_WIDTH-1-:4];
endgenerate
endmodule // ui_wr_data
// Local Variables:
// verilog-library-directories:(".")
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
// verilator lint_off LITENDIAN
reg [5:0] binary_nostart [2:15];
reg [5:0] binary_start [0:15];
reg [175:0] hex [0:15];
// verilator lint_on LITENDIAN
integer i;
initial begin
begin
$readmemb("t/t_sys_readmem_b.mem", binary_nostart);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_nostart[i]);
`endif
if (binary_nostart['h2] != 6'h02) $stop;
if (binary_nostart['h3] != 6'h03) $stop;
if (binary_nostart['h4] != 6'h04) $stop;
if (binary_nostart['h5] != 6'h05) $stop;
if (binary_nostart['h6] != 6'h06) $stop;
if (binary_nostart['h7] != 6'h07) $stop;
if (binary_nostart['h8] != 6'h10) $stop;
if (binary_nostart['hc] != 6'h14) $stop;
if (binary_nostart['hd] != 6'h15) $stop;
end
begin
$readmemb("t/t_sys_readmem_b_8.mem", binary_start, 4, 4+7);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_start[i]);
`endif
if (binary_start['h04] != 6'h10) $stop;
if (binary_start['h05] != 6'h11) $stop;
if (binary_start['h06] != 6'h12) $stop;
if (binary_start['h07] != 6'h13) $stop;
if (binary_start['h08] != 6'h14) $stop;
if (binary_start['h09] != 6'h15) $stop;
if (binary_start['h0a] != 6'h16) $stop;
if (binary_start['h0b] != 6'h17) $stop;
end
begin
$readmemh("t/t_sys_readmem_h.mem", hex, 0);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex[i]);
`endif
if (hex['h04] != 176'h400437654321276543211765432107654321abcdef10) $stop;
if (hex['h0a] != 176'h400a37654321276543211765432107654321abcdef11) $stop;
if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop;
if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
// verilator lint_off LITENDIAN
reg [5:0] binary_nostart [2:15];
reg [5:0] binary_start [0:15];
reg [175:0] hex [0:15];
// verilator lint_on LITENDIAN
integer i;
initial begin
begin
$readmemb("t/t_sys_readmem_b.mem", binary_nostart);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_nostart[i]);
`endif
if (binary_nostart['h2] != 6'h02) $stop;
if (binary_nostart['h3] != 6'h03) $stop;
if (binary_nostart['h4] != 6'h04) $stop;
if (binary_nostart['h5] != 6'h05) $stop;
if (binary_nostart['h6] != 6'h06) $stop;
if (binary_nostart['h7] != 6'h07) $stop;
if (binary_nostart['h8] != 6'h10) $stop;
if (binary_nostart['hc] != 6'h14) $stop;
if (binary_nostart['hd] != 6'h15) $stop;
end
begin
$readmemb("t/t_sys_readmem_b_8.mem", binary_start, 4, 4+7);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, binary_start[i]);
`endif
if (binary_start['h04] != 6'h10) $stop;
if (binary_start['h05] != 6'h11) $stop;
if (binary_start['h06] != 6'h12) $stop;
if (binary_start['h07] != 6'h13) $stop;
if (binary_start['h08] != 6'h14) $stop;
if (binary_start['h09] != 6'h15) $stop;
if (binary_start['h0a] != 6'h16) $stop;
if (binary_start['h0b] != 6'h17) $stop;
end
begin
$readmemh("t/t_sys_readmem_h.mem", hex, 0);
`ifdef TEST_VERBOSE
for (i=0; i<16; i=i+1) $write(" @%x = %x\n", i, hex[i]);
`endif
if (hex['h04] != 176'h400437654321276543211765432107654321abcdef10) $stop;
if (hex['h0a] != 176'h400a37654321276543211765432107654321abcdef11) $stop;
if (hex['h0b] != 176'h400b37654321276543211765432107654321abcdef12) $stop;
if (hex['h0c] != 176'h400c37654321276543211765432107654321abcdef13) $stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mem_intfc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Aug 03 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose : Top level memory interface block. Instantiates a clock
// and reset generator, the memory controller, the phy and
// the user interface blocks.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v1_9_mem_intfc #
(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "1T",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane
// data=1/ctl=0
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
// defines the byte lanes in I/O banks being used in the interface
// 1- Used, 0- Unused
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
// defines the bit lanes in I/O banks being used in the interface. Each
// parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
parameter nCK_PER_CLK = 4, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter ORDERING = "NORM",
parameter PHASE_DETECT = "OFF" , // to phy_top
parameter IBUF_LPWR_MODE = "OFF", // to phy_top
parameter IODELAY_HP_MODE = "ON", // to phy_top
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG", //to phy_top
parameter OUTPUT_DRV = "HIGH" , // to phy_top
parameter REG_CTRL = "OFF" , // to phy_top
parameter RTT_NOM = "60" , // to phy_top
parameter RTT_WR = "120" , // to phy_top
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tCKE = 10000, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter WRLVL = "OFF" , // to phy_top
parameter DEBUG_PORT = "OFF" , // to phy_top
parameter CAL_WIDTH = "HALF" , // to phy_top
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter nDQS_COL0 = DQS_WIDTH,
parameter nDQS_COL1 = 0,
parameter nDQS_COL2 = 0,
parameter nDQS_COL3 = 0,
parameter DQS_LOC_COL0 = 144'h11100F0E0D0C0B0A09080706050403020100,
parameter DQS_LOC_COL1 = 0,
parameter DQS_LOC_COL2 = 0,
parameter DQS_LOC_COL3 = 0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter USER_REFRESH = "OFF", // Choose whether MC or User manages REF
parameter TEMP_MON_EN = "ON" // Enable/disable temperature monitoring
)
(
input clk_ref,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input error,
input reset,
output rst_tg_mc,
input [BANK_WIDTH-1:0] bank, // To mc0 of mc.v
input clk ,
input [2:0] cmd, // To mc0 of mc.v
input [COL_WIDTH-1:0] col, // To mc0 of mc.v
input correct_en,
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr, // To mc0 of mc.v
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input hi_priority, // To mc0 of mc.v
input [RANK_WIDTH-1:0] rank, // To mc0 of mc.v
input [2*nCK_PER_CLK-1:0] raw_not_ecc,
input [ROW_WIDTH-1:0] row, // To mc0 of mc.v
input rst, // To mc0 of mc.v, ...
input size, // To mc0 of mc.v
input [7:0] slot_0_present, // To mc0 of mc.v
input [7:0] slot_1_present, // To mc0 of mc.v
input use_addr, // To mc0 of mc.v
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data,
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask,
output accept, // From mc0 of mc.v
output accept_ns, // From mc0 of mc.v
output [BM_CNT_WIDTH-1:0] bank_mach_next, // From mc0 of mc.v
input app_sr_req,
output app_sr_active,
input app_ref_req,
output app_ref_ack,
input app_zq_req,
output app_zq_ack,
output [255:0] dbg_calib_top,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [ROW_WIDTH-1:0] ddr_addr, // From phy_top0 of phy_top.v
output [BANK_WIDTH-1:0] ddr_ba, // From phy_top0 of phy_top.v
output ddr_cas_n, // From phy_top0 of phy_top.v
output [CK_WIDTH-1:0] ddr_ck_n, // From phy_top0 of phy_top.v
output [CK_WIDTH-1:0] ddr_ck , // From phy_top0 of phy_top.v
output [CKE_WIDTH-1:0] ddr_cke, // From phy_top0 of phy_top.v
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, // From phy_top0 of phy_top.v
output [DM_WIDTH-1:0] ddr_dm, // From phy_top0 of phy_top.v
output [ODT_WIDTH-1:0] ddr_odt, // From phy_top0 of phy_top.v
output ddr_ras_n, // From phy_top0 of phy_top.v
output ddr_reset_n, // From phy_top0 of phy_top.v
output ddr_parity,
output ddr_we_n, // From phy_top0 of phy_top.v
output init_calib_complete,
output init_wrcal_complete,
output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr,
output [2*nCK_PER_CLK-1:0] ecc_multiple,
output [2*nCK_PER_CLK-1:0] ecc_single,
output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data,
output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr,
// From mc0 of mc.v
output rd_data_en, // From mc0 of mc.v
output rd_data_end, // From mc0 of mc.v
output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset, // From mc0 of mc.v
output [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr, // From mc0 of mc.v
output wr_data_en, // From mc0 of mc.v
output [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset, // From mc0 of mc.v
inout [DQ_WIDTH-1:0] ddr_dq, // To/From phy_top0 of phy_top.v
inout [DQS_WIDTH-1:0] ddr_dqs_n, // To/From phy_top0 of phy_top.v
inout [DQS_WIDTH-1:0] ddr_dqs // To/From phy_top0 of phy_top.v
,input [11:0] device_temp
,input dbg_sel_pi_incdec
,input dbg_sel_po_incdec
,input [DQS_CNT_WIDTH:0] dbg_byte_sel
,input dbg_pi_f_inc
,input dbg_pi_f_dec
,input dbg_po_f_inc
,input dbg_po_f_stg23_sel
,input dbg_po_f_dec
,output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt
,output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt
,output dbg_rddata_valid
,output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt
,output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt
,output [255:0] dbg_phy_wrlvl
,output [5:0] dbg_pi_counter_read_val
,output [8:0] dbg_po_counter_read_val
,output ref_dll_lock
,input rst_phaser_ref
,output [6*RANKS-1:0] dbg_rd_data_offset
,output [255:0] dbg_phy_init
,output [255:0] dbg_prbs_rdlvl
,output [255:0] dbg_dqs_found_cal
,output dbg_pi_phaselock_start
,output dbg_pi_phaselocked_done
,output dbg_pi_phaselock_err
,output dbg_pi_dqsfound_start
,output dbg_pi_dqsfound_done
,output dbg_pi_dqsfound_err
,output dbg_wrcal_start
,output dbg_wrcal_done
,output dbg_wrcal_err
,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes
,output [11:0] dbg_pi_phase_locked_phy4lanes
,output [6*RANKS-1:0] dbg_calib_rd_data_offset_1
,output [6*RANKS-1:0] dbg_calib_rd_data_offset_2
,output [5:0] dbg_data_offset
,output [5:0] dbg_data_offset_1
,output [5:0] dbg_data_offset_2
,output dbg_oclkdelay_calib_start
,output dbg_oclkdelay_calib_done
,output [255:0] dbg_phy_oclkdelay_cal
,output [DRAM_WIDTH*16 -1:0]dbg_oclkdelay_rd_data
);
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
localparam SLOT_0_CONFIG_MC = (nSLOTS == 2)? 8'b0000_0101 : 8'b0000_1111;
localparam SLOT_1_CONFIG_MC = (nSLOTS == 2)? 8'b0000_1010 : 8'b0000_0000;
reg [7:0] slot_0_present_mc;
reg [7:0] slot_1_present_mc;
reg user_periodic_rd_req = 1'b0;
reg user_ref_req = 1'b0;
reg user_zq_req = 1'b0;
// MC/PHY interface
wire [nCK_PER_CLK-1:0] mc_ras_n;
wire [nCK_PER_CLK-1:0] mc_cas_n;
wire [nCK_PER_CLK-1:0] mc_we_n;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank;
wire [nCK_PER_CLK-1 :0] mc_cke ;
wire [1:0] mc_odt ;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n;
wire mc_reset_n;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
wire mc_wrdata_en;
wire mc_ref_zq_wip;
wire tempmon_sample_en;
wire idle;
wire mc_cmd_wren;
wire mc_ctl_wren;
wire [2:0] mc_cmd;
wire [1:0] mc_cas_slot;
wire [5:0] mc_data_offset;
wire [5:0] mc_data_offset_1;
wire [5:0] mc_data_offset_2;
wire [3:0] mc_aux_out0;
wire [3:0] mc_aux_out1;
wire [1:0] mc_rank_cnt;
wire phy_mc_ctl_full;
wire phy_mc_cmd_full;
wire phy_mc_data_full;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data;
wire phy_rddata_valid;
wire [6*RANKS-1:0] calib_rd_data_offset_0;
wire [6*RANKS-1:0] calib_rd_data_offset_1;
wire [6*RANKS-1:0] calib_rd_data_offset_2;
wire init_calib_complete_w;
wire init_wrcal_complete_w;
wire mux_rst;
// assigning CWL = CL -1 for DDR2. DDR2 customers will not know anything
// about CWL. There is also nCWL parameter. Need to clean it up.
localparam CWL_T = (DRAM_TYPE == "DDR3") ? CWL : CL-1;
assign init_calib_complete = init_calib_complete_w;
assign init_wrcal_complete = init_wrcal_complete_w;
assign mux_calib_complete = (PRE_REV3ES == "OFF") ? init_calib_complete_w :
(init_calib_complete_w | init_wrcal_complete_w);
assign mux_rst = (PRE_REV3ES == "OFF") ? rst : reset;
assign dbg_calib_rd_data_offset_1 = calib_rd_data_offset_1;
assign dbg_calib_rd_data_offset_2 = calib_rd_data_offset_2;
assign dbg_data_offset = mc_data_offset;
assign dbg_data_offset_1 = mc_data_offset_1;
assign dbg_data_offset_2 = mc_data_offset_2;
// Enable / disable temperature monitoring
assign tempmon_sample_en = TEMP_MON_EN == "OFF" ? 1'b0 : mc_ref_zq_wip;
generate
if (nSLOTS == 1) begin: gen_single_slot_odt
always @ (slot_0_present or slot_1_present) begin
slot_0_present_mc = slot_0_present;
slot_1_present_mc = slot_1_present;
end
end else if (nSLOTS == 2) begin: gen_dual_slot_odt
always @ (slot_0_present[0] or slot_0_present[1]
or slot_1_present[0] or slot_1_present[1]) begin
case ({slot_0_present[0],slot_0_present[1],
slot_1_present[0],slot_1_present[1]})
//Two slot configuration, one slot present, single rank
4'b1000: begin
slot_0_present_mc = 8'b0000_0001;
slot_1_present_mc = 8'b0000_0000;
end
4'b0010: begin
slot_0_present_mc = 8'b0000_0000;
slot_1_present_mc = 8'b0000_0010;
end
// Two slot configuration, one slot present, dual rank
4'b1100: begin
slot_0_present_mc = 8'b0000_0101;
slot_1_present_mc = 8'b0000_0000;
end
4'b0011: begin
slot_0_present_mc = 8'b0000_0000;
slot_1_present_mc = 8'b0000_1010;
end
// Two slot configuration, one rank per slot
4'b1010: begin
slot_0_present_mc = 8'b0000_0001;
slot_1_present_mc = 8'b0000_0010;
end
// Two Slots - One slot with dual rank and the other with single rank
4'b1011: begin
slot_0_present_mc = 8'b0000_0001;
slot_1_present_mc = 8'b0000_1010;
end
4'b1110: begin
slot_0_present_mc = 8'b0000_0101;
slot_1_present_mc = 8'b0000_0010;
end
// Two Slots - two ranks per slot
4'b1111: begin
slot_0_present_mc = 8'b0000_0101;
slot_1_present_mc = 8'b0000_1010;
end
endcase
end
end
endgenerate
mig_7series_v1_9_mc #
(
.TCQ (TCQ),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.CKE_ODT_AUX (CKE_ODT_AUX),
.DQS_WIDTH (DQS_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nSLOTS (nSLOTS),
.CL (CL),
.nCS_PER_RANK (nCS_PER_RANK),
.CWL (CWL_T),
.ORDERING (ORDERING),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REG_CTRL (REG_CTRL),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.STARVE_LIMIT (STARVE_LIMIT),
.SLOT_0_CONFIG (SLOT_0_CONFIG_MC),
.SLOT_1_CONFIG (SLOT_1_CONFIG_MC),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.tPRDI (tPRDI),
.USER_REFRESH (USER_REFRESH))
mc0
(.app_periodic_rd_req (1'b0),
.app_sr_req (app_sr_req),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.app_zq_ack (app_zq_ack),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.mc_address (mc_address),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_bank (mc_bank),
.mc_cke (mc_cke),
.mc_odt (mc_odt),
.mc_cas_n (mc_cas_n),
.mc_cmd (mc_cmd),
.mc_cmd_wren (mc_cmd_wren),
.mc_cs_n (mc_cs_n),
.mc_ctl_wren (mc_ctl_wren),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.mc_cas_slot (mc_cas_slot),
.mc_rank_cnt (mc_rank_cnt),
.mc_ras_n (mc_ras_n),
.mc_reset_n (mc_reset_n),
.mc_we_n (mc_we_n),
.mc_wrdata (mc_wrdata),
.mc_wrdata_en (mc_wrdata_en),
.mc_wrdata_mask (mc_wrdata_mask),
// Outputs
.accept (accept),
.accept_ns (accept_ns),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.rd_data (rd_data),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.mc_read_idle (idle),
.mc_ref_zq_wip (mc_ref_zq_wip),
// Inputs
.init_calib_complete (mux_calib_complete),
.calib_rd_data_offset (calib_rd_data_offset_0),
.calib_rd_data_offset_1 (calib_rd_data_offset_1),
.calib_rd_data_offset_2 (calib_rd_data_offset_2),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_data_full (phy_mc_data_full),
.phy_rd_data (phy_rd_data),
.phy_rddata_valid (phy_rddata_valid),
.correct_en (correct_en),
.bank (bank[BANK_WIDTH-1:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.hi_priority (hi_priority),
.rank (rank[RANK_WIDTH-1:0]),
.raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1 :0]),
.row (row[ROW_WIDTH-1:0]),
.rst (mux_rst),
.size (size),
.slot_0_present (slot_0_present_mc[7:0]),
.slot_1_present (slot_1_present_mc[7:0]),
.use_addr (use_addr));
// following calculations should be moved inside PHY
// odt bus should be added to PHY.
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
localparam nCL = CL;
localparam nCWL = CWL_T;
`ifdef MC_SVA
ddr2_improper_CL: assert property
(@(posedge clk) (~((DRAM_TYPE == "DDR2") && ((CL > 6) || (CL < 3)))));
// Not needed after the CWL fix for DDR2
// ddr2_improper_CWL: assert property
// (@(posedge clk) (~((DRAM_TYPE == "DDR2") && ((CL - CWL) != 1))));
`endif
mig_7series_v1_9_ddr_phy_top #
(
.TCQ (TCQ),
.REFCLK_FREQ (REFCLK_FREQ),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CA_MIRROR (CA_MIRROR),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.nCS_PER_RANK (nCS_PER_RANK),
.CS_WIDTH (CS_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.PRE_REV3ES (PRE_REV3ES),
.CKE_WIDTH (CKE_WIDTH),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DRAM_TYPE (DRAM_TYPE),
.BANK_WIDTH (BANK_WIDTH),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO),
.ROW_WIDTH (ROW_WIDTH),
.AL (AL),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CL (nCL),
.CWL (nCWL),
.tRFC (tRFC),
.tCK (tCK),
.OUTPUT_DRV (OUTPUT_DRV),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.WRLVL (WRLVL),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
// Prevent the following simulation-related parameters from
// being overridden for synthesis - for synthesis only the
// default values of these parameters should be used
// synthesis translate_off
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
// synthesis translate_on
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DEBUG_PORT (DEBUG_PORT)
)
ddr_phy_top0
(
// Outputs
.calib_rd_data_offset_0 (calib_rd_data_offset_0),
.calib_rd_data_offset_1 (calib_rd_data_offset_1),
.calib_rd_data_offset_2 (calib_rd_data_offset_2),
.ddr_ck (ddr_ck),
.ddr_ck_n (ddr_ck_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_ras_n (ddr_ras_n),
.ddr_cas_n (ddr_cas_n),
.ddr_we_n (ddr_we_n),
.ddr_cs_n (ddr_cs_n),
.ddr_cke (ddr_cke),
.ddr_odt (ddr_odt),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_dm (ddr_dm),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.init_calib_complete (init_calib_complete_w),
.init_wrcal_complete (init_wrcal_complete_w),
.mc_address (mc_address),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_bank (mc_bank),
.mc_cke (mc_cke),
.mc_odt (mc_odt),
.mc_cas_n (mc_cas_n),
.mc_cmd (mc_cmd),
.mc_cmd_wren (mc_cmd_wren),
.mc_cas_slot (mc_cas_slot),
.mc_cs_n (mc_cs_n),
.mc_ctl_wren (mc_ctl_wren),
.mc_data_offset (mc_data_offset),
.mc_data_offset_1 (mc_data_offset_1),
.mc_data_offset_2 (mc_data_offset_2),
.mc_rank_cnt (mc_rank_cnt),
.mc_ras_n (mc_ras_n),
.mc_reset_n (mc_reset_n),
.mc_we_n (mc_we_n),
.mc_wrdata (mc_wrdata),
.mc_wrdata_en (mc_wrdata_en),
.mc_wrdata_mask (mc_wrdata_mask),
.idle (idle),
.mem_refclk (mem_refclk),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_data_full (phy_mc_data_full),
.phy_rd_data (phy_rd_data),
.phy_rddata_valid (phy_rddata_valid),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
// Inouts
.ddr_dqs (ddr_dqs),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dq (ddr_dq),
// Inputs
.clk_ref (clk_ref),
.freq_refclk (freq_refclk),
.clk (clk),
.rst (rst),
.error (error),
.rst_tg_mc (rst_tg_mc),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt)
,.device_temp (device_temp)
,.tempmon_sample_en (tempmon_sample_en)
,.dbg_sel_pi_incdec (dbg_sel_pi_incdec)
,.dbg_sel_po_incdec (dbg_sel_po_incdec)
,.dbg_byte_sel (dbg_byte_sel)
,.dbg_pi_f_inc (dbg_pi_f_inc)
,.dbg_po_f_inc (dbg_po_f_inc)
,.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel)
,.dbg_pi_f_dec (dbg_pi_f_dec)
,.dbg_po_f_dec (dbg_po_f_dec)
,.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt)
,.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt)
,.dbg_rddata_valid (dbg_rddata_valid)
,.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt)
,.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt)
,.dbg_phy_wrlvl (dbg_phy_wrlvl)
,.ref_dll_lock (ref_dll_lock)
,.rst_phaser_ref (rst_phaser_ref)
,.dbg_rd_data_offset (dbg_rd_data_offset)
,.dbg_phy_init (dbg_phy_init)
,.dbg_prbs_rdlvl (dbg_prbs_rdlvl)
,.dbg_dqs_found_cal (dbg_dqs_found_cal)
,.dbg_po_counter_read_val (dbg_po_counter_read_val)
,.dbg_pi_counter_read_val (dbg_pi_counter_read_val)
,.dbg_pi_phaselock_start (dbg_pi_phaselock_start)
,.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done)
,.dbg_pi_phaselock_err (dbg_pi_phaselock_err)
,.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start)
,.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done)
,.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err)
,.dbg_wrcal_start (dbg_wrcal_start)
,.dbg_wrcal_done (dbg_wrcal_done)
,.dbg_wrcal_err (dbg_wrcal_err)
,.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal)
,.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data)
,.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start)
,.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sg_list_requester.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives scatter gather address/length info and requests
// the scatter gather data from the RX engine. Monitors the state of the scatter
// gather FIFO to make sure it can accommodate the requested data. Also signals
// when the entire scatter gather data has been received so the buffer can be
// overwritten with new data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_SGREQ_IDLE 8'b0000_0001
`define S_SGREQ_WAIT_0 8'b0000_0010
`define S_SGREQ_WAIT_1 8'b0000_0100
`define S_SGREQ_CHECK 8'b0000_1000
`define S_SGREQ_ISSUE 8'b0001_0000
`define S_SGREQ_UPDATE 8'b0010_0000
`define S_SGREQ_COUNT 8'b0100_0000
`define S_SGREQ_FLUSH 8'b1000_0000
`timescale 1ns/1ns
module sg_list_requester #(
parameter C_FIFO_DATA_WIDTH = 9'd64,
parameter C_FIFO_DEPTH = 1024,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_WORDS_PER_ELEM = 4,
parameter C_MAX_ELEMS = 200,
parameter C_MAX_ENTRIES = (C_MAX_ELEMS*C_WORDS_PER_ELEM),
parameter C_FIFO_COUNT_THRESH = C_FIFO_DEPTH - C_MAX_ENTRIES
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input USER_RST, // User reset, should clear FIFO data too
output BUF_RECVD, // Signals when scatter gather buffer received
input [31:0] BUF_DATA, // Buffer data
input BUF_LEN_VALID, // Buffer length valid
input BUF_ADDR_HI_VALID, // Buffer high address valid
input BUF_ADDR_LO_VALID, // Buffer low address valid
input [C_FIFO_DEPTH_WIDTH-1:0] FIFO_COUNT, // Scatter gather FIFO count
output FIFO_FLUSH, // Scatter gather FIFO flush request
input FIFO_FLUSHED, // Scatter gather FIFO flushed
output FIFO_RST, // Scatter gather FIFO data reset request
output RX_REQ, // Issue a read request
output [63:0] RX_ADDR, // Request address
output [9:0] RX_LEN, // Request length
input RX_REQ_ACK, // Request has been issued
input RX_DONE // Request has completed (data received)
);
`include "functions.vh"
reg [31:0] rData=0, _rData=0;
reg rAddrHiValid=0, _rAddrHiValid=0;
reg rAddrLoValid=0, _rAddrLoValid=0;
reg rLenValid=0, _rLenValid=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [7:0] rState=`S_SGREQ_IDLE, _rState=`S_SGREQ_IDLE;
reg rDone=0, _rDone=0;
reg rDelay=0, _rDelay=0;
reg [2:0] rCarry=0, _rCarry=0;
reg [3:0] rValsProp=0, _rValsProp=0;
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rBufWords=0, _rBufWords=0;
reg [10:0] rPageRem=0, _rPageRem=0;
reg rPageSpill=0, _rPageSpill=0;
reg [10:0] rPreLen=0, _rPreLen=0;
reg [2:0] rMaxPayloadTrain=0, _rMaxPayloadTrain=0;
reg [2:0] rMaxPayloadShift=0, _rMaxPayloadShift=0;
reg [9:0] rMaxPayload=0, _rMaxPayload=0;
reg rPayloadSpill=0, _rPayloadSpill=0;
reg [9:0] rLen=0, _rLen=0;
reg rBufWordsEQ0Hi=0, _rBufWordsEQ0Hi=0;
reg rBufWordsEQ0Lo=0, _rBufWordsEQ0Lo=0;
reg rUserRst=0, _rUserRst=0;
reg rRecvdAll=0, _rRecvdAll=0;
reg [10:0] rAckCount=0, _rAckCount=0;
assign BUF_RECVD = rDone;
assign FIFO_FLUSH = rState[7]; // S_SGREQ_FLUSH
assign FIFO_RST = (rUserRst & rState[0]); // S_SGREQ_IDLE
assign RX_ADDR = rAddr;
assign RX_LEN = rLen;
assign RX_REQ = rState[4]; // S_SGREQ_ISSUE
// Buffer signals coming from outside the rx_port.
always @ (posedge CLK) begin
rData <= #1 _rData;
rAddrHiValid <= #1 _rAddrHiValid;
rAddrLoValid <= #1 _rAddrLoValid;
rLenValid <= #1 _rLenValid;
end
always @ (*) begin
_rData = BUF_DATA;
_rAddrHiValid = BUF_ADDR_HI_VALID;
_rAddrLoValid = BUF_ADDR_LO_VALID;
_rLenValid = BUF_LEN_VALID;
end
// Handle requesting the next scatter gather buffer data.
wire [9:0] wAddrLoInv = ~rAddr[11:2];
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_SGREQ_IDLE : _rState);
rDone <= #1 (RST ? 1'd0 : _rDone);
rDelay <= #1 _rDelay;
rAddr <= #1 _rAddr;
rCarry <= #1 _rCarry;
rBufWords <= #1 _rBufWords;
rValsProp <= #1 _rValsProp;
rPageRem <= #1 _rPageRem;
rPageSpill <= #1 _rPageSpill;
rPreLen <= #1 _rPreLen;
rMaxPayloadTrain <= #1 _rMaxPayloadTrain;
rMaxPayloadShift <= #1 _rMaxPayloadShift;
rMaxPayload <= #1 _rMaxPayload;
rPayloadSpill <= #1 _rPayloadSpill;
rLen <= #1 _rLen;
rBufWordsEQ0Hi <= #1 _rBufWordsEQ0Hi;
rBufWordsEQ0Lo <= #1 _rBufWordsEQ0Lo;
rUserRst <= #1 (RST ? 1'd0 : _rUserRst);
end
always @ (*) begin
_rState = rState;
_rDone = rDone;
_rDelay = rDelay;
_rUserRst = ((rUserRst & !rState[0]) | USER_RST);
_rValsProp = ((rValsProp<<1) | RX_REQ_ACK);
{_rCarry[0], _rAddr[15:0]} = (rAddrLoValid ? rData[15:0] : (rAddr[15:0] + ({12{RX_REQ_ACK}} & {2'b0,rLen}<<2)));
{_rCarry[1], _rAddr[31:16]} = (rAddrLoValid ? rData[31:16] : (rAddr[31:16] + rCarry[0]));
{_rCarry[2], _rAddr[47:32]} = (rAddrHiValid ? rData[15:0] : (rAddr[47:32] + rCarry[1]));
_rAddr[63:48] = (rAddrHiValid ? rData[31:16] : (rAddr[63:48] + rCarry[2]));
_rBufWords = (rLenValid ? rData : rBufWords) - ({10{RX_REQ_ACK}} & rLen);
_rPageRem = (wAddrLoInv + 1'd1);
_rPageSpill = (rBufWords > rPageRem);
_rPreLen = (rPageSpill ? rPageRem : rBufWords[10:0]);
_rMaxPayloadTrain = (CONFIG_MAX_READ_REQUEST_SIZE > 3'd4 ? 3'd4 : CONFIG_MAX_READ_REQUEST_SIZE);
_rMaxPayloadShift = (C_MAX_READ_REQ[2:0] < rMaxPayloadTrain ? C_MAX_READ_REQ[2:0] : rMaxPayloadTrain);
_rMaxPayload = (6'd32<<rMaxPayloadShift);
_rPayloadSpill = (rPreLen > rMaxPayload);
_rLen = (rPayloadSpill ? rMaxPayload : rPreLen[9:0]);
_rBufWordsEQ0Hi = (16'd0 == rBufWords[31:16]);
_rBufWordsEQ0Lo = (16'd0 == rBufWords[15:0]);
case (rState)
`S_SGREQ_IDLE: begin // Wait for addr & length
_rDone = 0;
if (rLenValid)
_rState = `S_SGREQ_WAIT_0;
end
`S_SGREQ_WAIT_0: begin // Wait 1 cycle for values to propagate
_rDelay = 0;
_rState = `S_SGREQ_WAIT_1;
end
`S_SGREQ_WAIT_1: begin // Wait 2 cycles for values to propagate
_rDelay = 1;
if (rDelay)
_rState = `S_SGREQ_CHECK;
end
`S_SGREQ_CHECK: begin // Wait for space to be made available
if (FIFO_COUNT < C_FIFO_COUNT_THRESH)
_rState = `S_SGREQ_ISSUE;
else if (rUserRst)
_rState = `S_SGREQ_COUNT;
end
`S_SGREQ_ISSUE: begin // Wait for read request to be serviced
if (RX_REQ_ACK)
_rState = `S_SGREQ_UPDATE;
end
`S_SGREQ_UPDATE: begin // Update the address and length
if (rUserRst | (rBufWordsEQ0Hi & rBufWordsEQ0Lo))
_rState = `S_SGREQ_COUNT;
else if (rValsProp[3])
_rState = `S_SGREQ_ISSUE;
end
`S_SGREQ_COUNT: begin // Wait for read data to arrive
if (rRecvdAll)
_rState = `S_SGREQ_FLUSH;
end
`S_SGREQ_FLUSH: begin // Wait for read data to arrive
if (FIFO_FLUSHED) begin
_rDone = !rUserRst;
_rState = `S_SGREQ_IDLE;
end
end
default: begin
_rState = `S_SGREQ_IDLE;
end
endcase
end
// Keep track of requests made and requests completed so we know when all
// the outstanding data has been received.
always @ (posedge CLK) begin
rAckCount <= #1 (RST ? 10'd0 : _rAckCount);
rRecvdAll <= #1 _rRecvdAll;
end
always @ (*) begin
// Track REQ_DONE and SG_DONE to maintain an outstanding request count.
_rRecvdAll = (rAckCount == 10'd0);
if (rState[0]) // S_SGREQ_IDLE
_rAckCount = 0;
else
_rAckCount = rAckCount + RX_REQ_ACK - RX_DONE;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sg_list_requester.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives scatter gather address/length info and requests
// the scatter gather data from the RX engine. Monitors the state of the scatter
// gather FIFO to make sure it can accommodate the requested data. Also signals
// when the entire scatter gather data has been received so the buffer can be
// overwritten with new data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_SGREQ_IDLE 8'b0000_0001
`define S_SGREQ_WAIT_0 8'b0000_0010
`define S_SGREQ_WAIT_1 8'b0000_0100
`define S_SGREQ_CHECK 8'b0000_1000
`define S_SGREQ_ISSUE 8'b0001_0000
`define S_SGREQ_UPDATE 8'b0010_0000
`define S_SGREQ_COUNT 8'b0100_0000
`define S_SGREQ_FLUSH 8'b1000_0000
`timescale 1ns/1ns
module sg_list_requester #(
parameter C_FIFO_DATA_WIDTH = 9'd64,
parameter C_FIFO_DEPTH = 1024,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_WORDS_PER_ELEM = 4,
parameter C_MAX_ELEMS = 200,
parameter C_MAX_ENTRIES = (C_MAX_ELEMS*C_WORDS_PER_ELEM),
parameter C_FIFO_COUNT_THRESH = C_FIFO_DEPTH - C_MAX_ENTRIES
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input USER_RST, // User reset, should clear FIFO data too
output BUF_RECVD, // Signals when scatter gather buffer received
input [31:0] BUF_DATA, // Buffer data
input BUF_LEN_VALID, // Buffer length valid
input BUF_ADDR_HI_VALID, // Buffer high address valid
input BUF_ADDR_LO_VALID, // Buffer low address valid
input [C_FIFO_DEPTH_WIDTH-1:0] FIFO_COUNT, // Scatter gather FIFO count
output FIFO_FLUSH, // Scatter gather FIFO flush request
input FIFO_FLUSHED, // Scatter gather FIFO flushed
output FIFO_RST, // Scatter gather FIFO data reset request
output RX_REQ, // Issue a read request
output [63:0] RX_ADDR, // Request address
output [9:0] RX_LEN, // Request length
input RX_REQ_ACK, // Request has been issued
input RX_DONE // Request has completed (data received)
);
`include "functions.vh"
reg [31:0] rData=0, _rData=0;
reg rAddrHiValid=0, _rAddrHiValid=0;
reg rAddrLoValid=0, _rAddrLoValid=0;
reg rLenValid=0, _rLenValid=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [7:0] rState=`S_SGREQ_IDLE, _rState=`S_SGREQ_IDLE;
reg rDone=0, _rDone=0;
reg rDelay=0, _rDelay=0;
reg [2:0] rCarry=0, _rCarry=0;
reg [3:0] rValsProp=0, _rValsProp=0;
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rBufWords=0, _rBufWords=0;
reg [10:0] rPageRem=0, _rPageRem=0;
reg rPageSpill=0, _rPageSpill=0;
reg [10:0] rPreLen=0, _rPreLen=0;
reg [2:0] rMaxPayloadTrain=0, _rMaxPayloadTrain=0;
reg [2:0] rMaxPayloadShift=0, _rMaxPayloadShift=0;
reg [9:0] rMaxPayload=0, _rMaxPayload=0;
reg rPayloadSpill=0, _rPayloadSpill=0;
reg [9:0] rLen=0, _rLen=0;
reg rBufWordsEQ0Hi=0, _rBufWordsEQ0Hi=0;
reg rBufWordsEQ0Lo=0, _rBufWordsEQ0Lo=0;
reg rUserRst=0, _rUserRst=0;
reg rRecvdAll=0, _rRecvdAll=0;
reg [10:0] rAckCount=0, _rAckCount=0;
assign BUF_RECVD = rDone;
assign FIFO_FLUSH = rState[7]; // S_SGREQ_FLUSH
assign FIFO_RST = (rUserRst & rState[0]); // S_SGREQ_IDLE
assign RX_ADDR = rAddr;
assign RX_LEN = rLen;
assign RX_REQ = rState[4]; // S_SGREQ_ISSUE
// Buffer signals coming from outside the rx_port.
always @ (posedge CLK) begin
rData <= #1 _rData;
rAddrHiValid <= #1 _rAddrHiValid;
rAddrLoValid <= #1 _rAddrLoValid;
rLenValid <= #1 _rLenValid;
end
always @ (*) begin
_rData = BUF_DATA;
_rAddrHiValid = BUF_ADDR_HI_VALID;
_rAddrLoValid = BUF_ADDR_LO_VALID;
_rLenValid = BUF_LEN_VALID;
end
// Handle requesting the next scatter gather buffer data.
wire [9:0] wAddrLoInv = ~rAddr[11:2];
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_SGREQ_IDLE : _rState);
rDone <= #1 (RST ? 1'd0 : _rDone);
rDelay <= #1 _rDelay;
rAddr <= #1 _rAddr;
rCarry <= #1 _rCarry;
rBufWords <= #1 _rBufWords;
rValsProp <= #1 _rValsProp;
rPageRem <= #1 _rPageRem;
rPageSpill <= #1 _rPageSpill;
rPreLen <= #1 _rPreLen;
rMaxPayloadTrain <= #1 _rMaxPayloadTrain;
rMaxPayloadShift <= #1 _rMaxPayloadShift;
rMaxPayload <= #1 _rMaxPayload;
rPayloadSpill <= #1 _rPayloadSpill;
rLen <= #1 _rLen;
rBufWordsEQ0Hi <= #1 _rBufWordsEQ0Hi;
rBufWordsEQ0Lo <= #1 _rBufWordsEQ0Lo;
rUserRst <= #1 (RST ? 1'd0 : _rUserRst);
end
always @ (*) begin
_rState = rState;
_rDone = rDone;
_rDelay = rDelay;
_rUserRst = ((rUserRst & !rState[0]) | USER_RST);
_rValsProp = ((rValsProp<<1) | RX_REQ_ACK);
{_rCarry[0], _rAddr[15:0]} = (rAddrLoValid ? rData[15:0] : (rAddr[15:0] + ({12{RX_REQ_ACK}} & {2'b0,rLen}<<2)));
{_rCarry[1], _rAddr[31:16]} = (rAddrLoValid ? rData[31:16] : (rAddr[31:16] + rCarry[0]));
{_rCarry[2], _rAddr[47:32]} = (rAddrHiValid ? rData[15:0] : (rAddr[47:32] + rCarry[1]));
_rAddr[63:48] = (rAddrHiValid ? rData[31:16] : (rAddr[63:48] + rCarry[2]));
_rBufWords = (rLenValid ? rData : rBufWords) - ({10{RX_REQ_ACK}} & rLen);
_rPageRem = (wAddrLoInv + 1'd1);
_rPageSpill = (rBufWords > rPageRem);
_rPreLen = (rPageSpill ? rPageRem : rBufWords[10:0]);
_rMaxPayloadTrain = (CONFIG_MAX_READ_REQUEST_SIZE > 3'd4 ? 3'd4 : CONFIG_MAX_READ_REQUEST_SIZE);
_rMaxPayloadShift = (C_MAX_READ_REQ[2:0] < rMaxPayloadTrain ? C_MAX_READ_REQ[2:0] : rMaxPayloadTrain);
_rMaxPayload = (6'd32<<rMaxPayloadShift);
_rPayloadSpill = (rPreLen > rMaxPayload);
_rLen = (rPayloadSpill ? rMaxPayload : rPreLen[9:0]);
_rBufWordsEQ0Hi = (16'd0 == rBufWords[31:16]);
_rBufWordsEQ0Lo = (16'd0 == rBufWords[15:0]);
case (rState)
`S_SGREQ_IDLE: begin // Wait for addr & length
_rDone = 0;
if (rLenValid)
_rState = `S_SGREQ_WAIT_0;
end
`S_SGREQ_WAIT_0: begin // Wait 1 cycle for values to propagate
_rDelay = 0;
_rState = `S_SGREQ_WAIT_1;
end
`S_SGREQ_WAIT_1: begin // Wait 2 cycles for values to propagate
_rDelay = 1;
if (rDelay)
_rState = `S_SGREQ_CHECK;
end
`S_SGREQ_CHECK: begin // Wait for space to be made available
if (FIFO_COUNT < C_FIFO_COUNT_THRESH)
_rState = `S_SGREQ_ISSUE;
else if (rUserRst)
_rState = `S_SGREQ_COUNT;
end
`S_SGREQ_ISSUE: begin // Wait for read request to be serviced
if (RX_REQ_ACK)
_rState = `S_SGREQ_UPDATE;
end
`S_SGREQ_UPDATE: begin // Update the address and length
if (rUserRst | (rBufWordsEQ0Hi & rBufWordsEQ0Lo))
_rState = `S_SGREQ_COUNT;
else if (rValsProp[3])
_rState = `S_SGREQ_ISSUE;
end
`S_SGREQ_COUNT: begin // Wait for read data to arrive
if (rRecvdAll)
_rState = `S_SGREQ_FLUSH;
end
`S_SGREQ_FLUSH: begin // Wait for read data to arrive
if (FIFO_FLUSHED) begin
_rDone = !rUserRst;
_rState = `S_SGREQ_IDLE;
end
end
default: begin
_rState = `S_SGREQ_IDLE;
end
endcase
end
// Keep track of requests made and requests completed so we know when all
// the outstanding data has been received.
always @ (posedge CLK) begin
rAckCount <= #1 (RST ? 10'd0 : _rAckCount);
rRecvdAll <= #1 _rRecvdAll;
end
always @ (*) begin
// Track REQ_DONE and SG_DONE to maintain an outstanding request count.
_rRecvdAll = (rAckCount == 10'd0);
if (rState[0]) // S_SGREQ_IDLE
_rAckCount = 0;
else
_rAckCount = rAckCount + RX_REQ_ACK - RX_DONE;
end
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31; // Data width
parameter DATA_DEPTH = 128;
parameter AW = 6; // Address width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data),
// Unused
// synopsys translate_off
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31; // Data width
parameter DATA_DEPTH = 128;
parameter AW = 6; // Address width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data),
// Unused
// synopsys translate_off
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31; // Data width
parameter DATA_DEPTH = 128;
parameter AW = 6; // Address width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data),
// Unused
// synopsys translate_off
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
Set Universe Polymorphism.
Definition crelation (A : Type) := A -> A -> Type.
Definition arrow (A B : Type) := A -> B.
Definition flip {A B C : Type} (f : A -> B -> C) := fun x y => f y x.
Definition iffT (A B : Type) := ((A -> B) * (B -> A))%type.
(** We allow to unfold the [crelation] definition while doing morphism search. *)
Section Defs.
Context {A : Type}.
(** We rebind crelational properties in separate classes to be able to overload each proof. *)
Class Reflexive (R : crelation A) :=
reflexivity : forall x : A, R x x.
Definition complement (R : crelation A) : crelation A :=
fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement iffT.
(** These are convertible. *)
Lemma complement_inverse R : complement (flip R) = flip (complement R).
Proof. reflexivity. Qed.
Class Irreflexive (R : crelation A) :=
irreflexivity : Reflexive (complement R).
Class Symmetric (R : crelation A) :=
symmetry : forall {x y}, R x y -> R y x.
Class Asymmetric (R : crelation A) :=
asymmetry : forall {x y}, R x y -> (complement R y x : Type).
Class Transitive (R : crelation A) :=
transitivity : forall {x y z}, R x y -> R y z -> R x z.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder (R : crelation A) := {
PreOrder_Reflexive :> Reflexive R | 2 ;
PreOrder_Transitive :> Transitive R | 2 }.
(** A [StrictOrder] is both Irreflexive and Transitive. *)
Class StrictOrder (R : crelation A) := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R }.
(** By definition, a strict order is also asymmetric *)
Global Instance StrictOrder_Asymmetric `(StrictOrder R) : Asymmetric R.
Proof. firstorder. Qed.
(** A partial equivalence crelation is Symmetric and Transitive. *)
Class PER (R : crelation A) := {
PER_Symmetric :> Symmetric R | 3 ;
PER_Transitive :> Transitive R | 3 }.
(** Equivalence crelations. *)
Class Equivalence (R : crelation A) := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Global Instance Equivalence_PER {R} `(Equivalence R) : PER R | 10 :=
{ PER_Symmetric := Equivalence_Symmetric ;
PER_Transitive := Equivalence_Transitive }.
(** We can now define antisymmetry w.r.t. an equivalence crelation on the carrier. *)
Class Antisymmetric eqA `{equ : Equivalence eqA} (R : crelation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Class subrelation (R R' : crelation A) :=
is_subrelation : forall {x y}, R x y -> R' x y.
(** Any symmetric crelation is equal to its inverse. *)
Lemma subrelation_symmetric R `(Symmetric R) : subrelation (flip R) R.
Proof. hnf. intros x y H'. red in H'. apply symmetry. assumption. Qed.
Section flip.
Lemma flip_Reflexive `{Reflexive R} : Reflexive (flip R).
Proof. tauto. Qed.
Program Definition flip_Irreflexive `(Irreflexive R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Program Definition flip_Antisymmetric `(Antisymmetric eqA R) :
Antisymmetric eqA (flip R).
Proof. firstorder. Qed.
(** Inversing the larger structures *)
Lemma flip_PreOrder `(PreOrder R) : PreOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_StrictOrder `(StrictOrder R) : StrictOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_PER `(PER R) : PER (flip R).
Proof. firstorder. Qed.
Lemma flip_Equivalence `(Equivalence R) : Equivalence (flip R).
Proof. firstorder. Qed.
End flip.
Section complement.
Definition complement_Irreflexive `(Reflexive R)
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric R) : Symmetric (complement R).
Proof. firstorder. Qed.
End complement.
(** Rewrite crelation on a given support: declares a crelation as a rewrite
crelation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
crelations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation (RA : crelation A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite crelation. *)
Global Instance equivalence_rewrite_crelation `(Equivalence eqA) : RewriteRelation eqA.
(** Leibniz equality. *)
Section Leibniz.
Global Instance eq_Reflexive : Reflexive (@eq A) := @eq_refl A.
Global Instance eq_Symmetric : Symmetric (@eq A) := @eq_sym A.
Global Instance eq_Transitive : Transitive (@eq A) := @eq_trans A.
(** Leibinz equality [eq] is an equivalence crelation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Global Program Instance eq_equivalence : Equivalence (@eq A) | 10.
End Leibniz.
End Defs.
(** Default rewrite crelations handled by [setoid_rewrite]. *)
Instance: RewriteRelation impl.
Instance: RewriteRelation iff.
(** Hints to drive the typeclass resolution avoiding loops
due to the use of full unification. *)
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
Hint Extern 3 (Irreflexive (complement _)) => class_apply complement_Irreflexive : typeclass_instances.
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
Hint Extern 3 (Antisymmetric (flip _)) => class_apply flip_Antisymmetric : typeclass_instances.
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
Hint Extern 3 (StrictOrder (flip _)) => class_apply flip_StrictOrder : typeclass_instances.
Hint Extern 3 (PreOrder (flip _)) => class_apply flip_PreOrder : typeclass_instances.
Hint Extern 4 (subrelation (flip _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
Hint Resolve irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for crelations. *)
Ltac solve_crelation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_crelation : crelations.
(** We can already dualize all these properties. *)
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_crelation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ dintuition ]).
Local Obligation Tactic := simpl_crelation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Instance iff_Reflexive : Reflexive iff := iff_refl.
Instance iff_Symmetric : Symmetric iff := iff_sym.
Instance iff_Transitive : Transitive iff := iff_trans.
(** Logical equivalence [iff] is an equivalence crelation. *)
Program Instance iff_equivalence : Equivalence iff.
Program Instance arrow_Reflexive : Reflexive arrow.
Program Instance arrow_Transitive : Transitive arrow.
Instance iffT_Reflexive : Reflexive iffT.
Proof. firstorder. Defined.
Instance iffT_Symmetric : Symmetric iffT.
Proof. firstorder. Defined.
Instance iffT_Transitive : Transitive iffT.
Proof. firstorder. Defined.
(** We now develop a generalization of results on crelations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary crelations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
(** We define the various operations which define the algebra on binary crelations *)
Section Binary.
Context {A : Type}.
Definition relation_equivalence : crelation (crelation A) :=
fun R R' => forall x y, iffT (R x y) (R' x y).
Global Instance: RewriteRelation relation_equivalence.
Definition relation_conjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => prod (R x y) (R' x y).
Definition relation_disjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => sum (R x y) (R' x y).
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Set Automatic Introduction.
Global Instance relation_equivalence_equivalence :
Equivalence relation_equivalence.
Proof. split; red; unfold relation_equivalence, iffT. firstorder.
firstorder.
intros. specialize (X x0 y0). specialize (X0 x0 y0). firstorder.
Qed.
Global Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. firstorder. Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence crelation
on the carrier. *)
Class PartialOrder eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (flip R)).
(** The equivalence proof is sufficient for proving that [R] must be a
morphism for equivalence (see Morphisms). It is also sufficient to
show that [R] is antisymmetric w.r.t. [eqA] *)
Global Instance partial_order_antisym `(PartialOrder eqA R) : ! Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
apply H. firstorder.
Qed.
Lemma PartialOrder_inverse `(PartialOrder eqA R) : PartialOrder eqA (flip R).
Proof. unfold flip; constructor; unfold flip. intros. apply H. apply symmetry. apply X.
unfold relation_conjunction. intros [H1 H2]. apply H. constructor; assumption. Qed.
End Binary.
Hint Extern 3 (PartialOrder (flip _)) => class_apply PartialOrder_inverse : typeclass_instances.
(** The partial order defined by subrelation and crelation equivalence. *)
(* Program Instance subrelation_partial_order : *)
(* ! PartialOrder (crelation A) relation_equivalence subrelation. *)
(* Obligation Tactic := idtac. *)
(* Next Obligation. *)
(* Proof. *)
(* intros x. refine (fun x => x). *)
(* Qed. *)
Typeclasses Opaque relation_equivalence.
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
Set Universe Polymorphism.
Definition crelation (A : Type) := A -> A -> Type.
Definition arrow (A B : Type) := A -> B.
Definition flip {A B C : Type} (f : A -> B -> C) := fun x y => f y x.
Definition iffT (A B : Type) := ((A -> B) * (B -> A))%type.
(** We allow to unfold the [crelation] definition while doing morphism search. *)
Section Defs.
Context {A : Type}.
(** We rebind crelational properties in separate classes to be able to overload each proof. *)
Class Reflexive (R : crelation A) :=
reflexivity : forall x : A, R x x.
Definition complement (R : crelation A) : crelation A :=
fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement iffT.
(** These are convertible. *)
Lemma complement_inverse R : complement (flip R) = flip (complement R).
Proof. reflexivity. Qed.
Class Irreflexive (R : crelation A) :=
irreflexivity : Reflexive (complement R).
Class Symmetric (R : crelation A) :=
symmetry : forall {x y}, R x y -> R y x.
Class Asymmetric (R : crelation A) :=
asymmetry : forall {x y}, R x y -> (complement R y x : Type).
Class Transitive (R : crelation A) :=
transitivity : forall {x y z}, R x y -> R y z -> R x z.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder (R : crelation A) := {
PreOrder_Reflexive :> Reflexive R | 2 ;
PreOrder_Transitive :> Transitive R | 2 }.
(** A [StrictOrder] is both Irreflexive and Transitive. *)
Class StrictOrder (R : crelation A) := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R }.
(** By definition, a strict order is also asymmetric *)
Global Instance StrictOrder_Asymmetric `(StrictOrder R) : Asymmetric R.
Proof. firstorder. Qed.
(** A partial equivalence crelation is Symmetric and Transitive. *)
Class PER (R : crelation A) := {
PER_Symmetric :> Symmetric R | 3 ;
PER_Transitive :> Transitive R | 3 }.
(** Equivalence crelations. *)
Class Equivalence (R : crelation A) := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Global Instance Equivalence_PER {R} `(Equivalence R) : PER R | 10 :=
{ PER_Symmetric := Equivalence_Symmetric ;
PER_Transitive := Equivalence_Transitive }.
(** We can now define antisymmetry w.r.t. an equivalence crelation on the carrier. *)
Class Antisymmetric eqA `{equ : Equivalence eqA} (R : crelation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Class subrelation (R R' : crelation A) :=
is_subrelation : forall {x y}, R x y -> R' x y.
(** Any symmetric crelation is equal to its inverse. *)
Lemma subrelation_symmetric R `(Symmetric R) : subrelation (flip R) R.
Proof. hnf. intros x y H'. red in H'. apply symmetry. assumption. Qed.
Section flip.
Lemma flip_Reflexive `{Reflexive R} : Reflexive (flip R).
Proof. tauto. Qed.
Program Definition flip_Irreflexive `(Irreflexive R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Program Definition flip_Antisymmetric `(Antisymmetric eqA R) :
Antisymmetric eqA (flip R).
Proof. firstorder. Qed.
(** Inversing the larger structures *)
Lemma flip_PreOrder `(PreOrder R) : PreOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_StrictOrder `(StrictOrder R) : StrictOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_PER `(PER R) : PER (flip R).
Proof. firstorder. Qed.
Lemma flip_Equivalence `(Equivalence R) : Equivalence (flip R).
Proof. firstorder. Qed.
End flip.
Section complement.
Definition complement_Irreflexive `(Reflexive R)
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric R) : Symmetric (complement R).
Proof. firstorder. Qed.
End complement.
(** Rewrite crelation on a given support: declares a crelation as a rewrite
crelation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
crelations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation (RA : crelation A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite crelation. *)
Global Instance equivalence_rewrite_crelation `(Equivalence eqA) : RewriteRelation eqA.
(** Leibniz equality. *)
Section Leibniz.
Global Instance eq_Reflexive : Reflexive (@eq A) := @eq_refl A.
Global Instance eq_Symmetric : Symmetric (@eq A) := @eq_sym A.
Global Instance eq_Transitive : Transitive (@eq A) := @eq_trans A.
(** Leibinz equality [eq] is an equivalence crelation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Global Program Instance eq_equivalence : Equivalence (@eq A) | 10.
End Leibniz.
End Defs.
(** Default rewrite crelations handled by [setoid_rewrite]. *)
Instance: RewriteRelation impl.
Instance: RewriteRelation iff.
(** Hints to drive the typeclass resolution avoiding loops
due to the use of full unification. *)
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
Hint Extern 3 (Irreflexive (complement _)) => class_apply complement_Irreflexive : typeclass_instances.
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
Hint Extern 3 (Antisymmetric (flip _)) => class_apply flip_Antisymmetric : typeclass_instances.
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
Hint Extern 3 (StrictOrder (flip _)) => class_apply flip_StrictOrder : typeclass_instances.
Hint Extern 3 (PreOrder (flip _)) => class_apply flip_PreOrder : typeclass_instances.
Hint Extern 4 (subrelation (flip _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
Hint Resolve irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for crelations. *)
Ltac solve_crelation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_crelation : crelations.
(** We can already dualize all these properties. *)
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_crelation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ dintuition ]).
Local Obligation Tactic := simpl_crelation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Instance iff_Reflexive : Reflexive iff := iff_refl.
Instance iff_Symmetric : Symmetric iff := iff_sym.
Instance iff_Transitive : Transitive iff := iff_trans.
(** Logical equivalence [iff] is an equivalence crelation. *)
Program Instance iff_equivalence : Equivalence iff.
Program Instance arrow_Reflexive : Reflexive arrow.
Program Instance arrow_Transitive : Transitive arrow.
Instance iffT_Reflexive : Reflexive iffT.
Proof. firstorder. Defined.
Instance iffT_Symmetric : Symmetric iffT.
Proof. firstorder. Defined.
Instance iffT_Transitive : Transitive iffT.
Proof. firstorder. Defined.
(** We now develop a generalization of results on crelations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary crelations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
(** We define the various operations which define the algebra on binary crelations *)
Section Binary.
Context {A : Type}.
Definition relation_equivalence : crelation (crelation A) :=
fun R R' => forall x y, iffT (R x y) (R' x y).
Global Instance: RewriteRelation relation_equivalence.
Definition relation_conjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => prod (R x y) (R' x y).
Definition relation_disjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => sum (R x y) (R' x y).
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Set Automatic Introduction.
Global Instance relation_equivalence_equivalence :
Equivalence relation_equivalence.
Proof. split; red; unfold relation_equivalence, iffT. firstorder.
firstorder.
intros. specialize (X x0 y0). specialize (X0 x0 y0). firstorder.
Qed.
Global Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. firstorder. Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence crelation
on the carrier. *)
Class PartialOrder eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (flip R)).
(** The equivalence proof is sufficient for proving that [R] must be a
morphism for equivalence (see Morphisms). It is also sufficient to
show that [R] is antisymmetric w.r.t. [eqA] *)
Global Instance partial_order_antisym `(PartialOrder eqA R) : ! Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
apply H. firstorder.
Qed.
Lemma PartialOrder_inverse `(PartialOrder eqA R) : PartialOrder eqA (flip R).
Proof. unfold flip; constructor; unfold flip. intros. apply H. apply symmetry. apply X.
unfold relation_conjunction. intros [H1 H2]. apply H. constructor; assumption. Qed.
End Binary.
Hint Extern 3 (PartialOrder (flip _)) => class_apply PartialOrder_inverse : typeclass_instances.
(** The partial order defined by subrelation and crelation equivalence. *)
(* Program Instance subrelation_partial_order : *)
(* ! PartialOrder (crelation A) relation_equivalence subrelation. *)
(* Obligation Tactic := idtac. *)
(* Next Obligation. *)
(* Proof. *)
(* intros x. refine (fun x => x). *)
(* Qed. *)
Typeclasses Opaque relation_equivalence.
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
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// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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// DISCLAIMER
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
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// possibility of the same.
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// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_top.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level of simple user interface.
`timescale 1 ps / 1 ps
module mig_7series_v1_9_ui_top #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter BANK_WIDTH = 3,
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
parameter ORDERING = "NORM",
parameter nCK_PER_CLK = 2,
parameter RANKS = 4,
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
)
(/*AUTOARG*/
// Outputs
wr_data_mask, wr_data, use_addr, size, row, raw_not_ecc, rank,
hi_priority, data_buf_addr, col, cmd, bank, app_wdf_rdy, app_rdy,
app_rd_data_valid, app_rd_data_end, app_rd_data,
app_ecc_multiple_err, correct_en, sr_req, app_sr_active, ref_req, app_ref_ack,
zq_req, app_zq_ack,
// Inputs
wr_data_offset, wr_data_en, wr_data_addr, rst, rd_data_offset,
rd_data_end, rd_data_en, rd_data_addr, rd_data, ecc_multiple, clk,
app_wdf_wren, app_wdf_mask, app_wdf_end, app_wdf_data, app_sz,
app_raw_not_ecc, app_hi_pri, app_en, app_cmd, app_addr, accept_ns,
accept, app_correct_en, app_sr_req, sr_active, app_ref_req, ref_ack,
app_zq_req, zq_ack
);
input accept;
localparam ADDR_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
// Add a cycle to CWL for the register in RDIMM devices
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
input app_correct_en;
output wire correct_en;
assign correct_en = app_correct_en;
input app_sr_req;
output wire sr_req;
assign sr_req = app_sr_req;
input sr_active;
output wire app_sr_active;
assign app_sr_active = sr_active;
input app_ref_req;
output wire ref_req;
assign ref_req = app_ref_req;
input ref_ack;
output wire app_ref_ack;
assign app_ref_ack = ref_ack;
input app_zq_req;
output wire zq_req;
assign zq_req = app_zq_req;
input zq_ack;
output wire app_zq_ack;
assign app_zq_ack = zq_ack;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_ns; // To ui_cmd0 of ui_cmd.v
input [ADDR_WIDTH-1:0] app_addr; // To ui_cmd0 of ui_cmd.v
input [2:0] app_cmd; // To ui_cmd0 of ui_cmd.v
input app_en; // To ui_cmd0 of ui_cmd.v
input app_hi_pri; // To ui_cmd0 of ui_cmd.v
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; // To ui_wr_data0 of ui_wr_data.v
input app_sz; // To ui_cmd0 of ui_cmd.v
input [APP_DATA_WIDTH-1:0] app_wdf_data; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_end; // To ui_wr_data0 of ui_wr_data.v
input [APP_MASK_WIDTH-1:0] app_wdf_mask; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_wren; // To ui_wr_data0 of ui_wr_data.v
input clk; // To ui_cmd0 of ui_cmd.v, ...
input [2*nCK_PER_CLK-1:0] ecc_multiple; // To ui_rd_data0 of ui_rd_data.v
input [APP_DATA_WIDTH-1:0] rd_data; // To ui_rd_data0 of ui_rd_data.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To ui_rd_data0 of ui_rd_data.v
input rd_data_en; // To ui_rd_data0 of ui_rd_data.v
input rd_data_end; // To ui_rd_data0 of ui_rd_data.v
input rd_data_offset; // To ui_rd_data0 of ui_rd_data.v
input rst; // To ui_cmd0 of ui_cmd.v, ...
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; // To ui_wr_data0 of ui_wr_data.v
input wr_data_en; // To ui_wr_data0 of ui_wr_data.v
input wr_data_offset; // To ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; // From ui_rd_data0 of ui_rd_data.v
output [APP_DATA_WIDTH-1:0] app_rd_data; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_end; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_valid; // From ui_rd_data0 of ui_rd_data.v
output app_rdy; // From ui_cmd0 of ui_cmd.v
output app_wdf_rdy; // From ui_wr_data0 of ui_wr_data.v
output [BANK_WIDTH-1:0] bank; // From ui_cmd0 of ui_cmd.v
output [2:0] cmd; // From ui_cmd0 of ui_cmd.v
output [COL_WIDTH-1:0] col; // From ui_cmd0 of ui_cmd.v
output [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;// From ui_cmd0 of ui_cmd.v
output hi_priority; // From ui_cmd0 of ui_cmd.v
output [RANK_WIDTH-1:0] rank; // From ui_cmd0 of ui_cmd.v
output [2*nCK_PER_CLK-1:0] raw_not_ecc; // From ui_wr_data0 of ui_wr_data.v
output [ROW_WIDTH-1:0] row; // From ui_cmd0 of ui_cmd.v
output size; // From ui_cmd0 of ui_cmd.v
output use_addr; // From ui_cmd0 of ui_cmd.v
output [APP_DATA_WIDTH-1:0] wr_data; // From ui_wr_data0 of ui_wr_data.v
output [APP_MASK_WIDTH-1:0] wr_data_mask; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ram_init_addr; // From ui_rd_data0 of ui_rd_data.v
wire ram_init_done_r; // From ui_rd_data0 of ui_rd_data.v
wire rd_accepted; // From ui_cmd0 of ui_cmd.v
wire rd_buf_full; // From ui_rd_data0 of ui_rd_data.v
wire [DATA_BUF_ADDR_WIDTH-1:0]rd_data_buf_addr_r;// From ui_rd_data0 of ui_rd_data.v
wire wr_accepted; // From ui_cmd0 of ui_cmd.v
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;// From ui_wr_data0 of ui_wr_data.v
wire wr_req_16; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
// In the UI, the read and write buffers are allowed to be asymmetric to
// to maximize read performance, but the MC's native interface requires
// symmetry, so we zero-fill the write pointer
generate
if(DATA_BUF_ADDR_WIDTH > 4) begin
assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0;
end
endgenerate
mig_7series_v1_9_ui_cmd #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_WIDTH (ADDR_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANKS (RANKS),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER))
ui_cmd0
(/*AUTOINST*/
// Outputs
.app_rdy (app_rdy),
.use_addr (use_addr),
.rank (rank[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.size (size),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.rd_accepted (rd_accepted),
.wr_accepted (wr_accepted),
.data_buf_addr (data_buf_addr),
// Inputs
.rst (rst),
.clk (clk),
.accept_ns (accept_ns),
.rd_buf_full (rd_buf_full),
.wr_req_16 (wr_req_16),
.app_addr (app_addr[ADDR_WIDTH-1:0]),
.app_cmd (app_cmd[2:0]),
.app_sz (app_sz),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.wr_data_buf_addr (wr_data_buf_addr),
.rd_data_buf_addr_r (rd_data_buf_addr_r));
mig_7series_v1_9_ui_wr_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.CWL (CWL_M))
ui_wr_data0
(/*AUTOINST*/
// Outputs
.app_wdf_rdy (app_wdf_rdy),
.wr_req_16 (wr_req_16),
.wr_data_buf_addr (wr_data_buf_addr[3:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]),
// Inputs
.rst (rst),
.clk (clk),
.app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]),
.app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]),
.app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]),
.app_wdf_wren (app_wdf_wren),
.app_wdf_end (app_wdf_end),
.wr_data_offset (wr_data_offset),
.wr_data_addr (wr_data_addr[3:0]),
.wr_data_en (wr_data_en),
.wr_accepted (wr_accepted),
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr));
mig_7series_v1_9_ui_rd_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ORDERING (ORDERING))
ui_rd_data0
(/*AUTOINST*/
// Outputs
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]),
.app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]),
.rd_buf_full (rd_buf_full),
.rd_data_buf_addr_r (rd_data_buf_addr_r),
// Inputs
.rst (rst),
.clk (clk),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple[3:0]),
.rd_accepted (rd_accepted));
endmodule // ui_top
// Local Variables:
// verilog-library-directories:("." "../mc")
// End:
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Structural block instantiating the three sub blocks that make up
// a bank machine.
`timescale 1ps/1ps
module mig_7series_v1_9_bank_cntrl #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 4,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRCD = 5,
parameter nRTP = 4,
parameter nRP = 10,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter ROW_WIDTH = 16,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
wr_this_rank_r, start_rcd, start_pre_wait, rts_row, rts_col, rts_pre, rtc,
row_cmd_wr, row_addr, req_size_r, req_row_r, req_ras,
req_periodic_rd_r, req_cas, req_bank_r, rd_this_rank_r,
rb_hit_busy_ns, ras_timer_ns, rank_busy_r, ordered_r,
ordered_issued, op_exit_req, end_rtp, demand_priority,
demand_act_priority, col_rdy_wr, col_addr, act_this_rank_r, idle_ns,
req_wr_r, rd_wr_r, bm_end, idle_r, head_r, req_rank_r,
rb_hit_busy_r, passing_open_bank, maint_hit, req_data_buf_addr_r,
// Inputs
was_wr, was_priority, use_addr, start_rcd_in,
size, sent_row, sent_col, sending_row, sending_pre, sending_col, rst, row,
req_rank_r_in, rd_rmw, rd_data_addr, rb_hit_busy_ns_in,
rb_hit_busy_cnt, ras_timer_ns_in, rank, periodic_rd_rank_r,
periodic_rd_insert, periodic_rd_ack_r, passing_open_bank_in,
order_cnt, op_exit_grant, maint_zq_r, maint_sre_r, maint_req_r, maint_rank_r,
maint_idle, low_idle_cnt_r, rnk_config_valid_r, inhbt_rd, inhbt_wr,
rnk_config_strobe, rnk_config, inhbt_act_faw_r, idle_cnt, hi_priority,
dq_busy_data, phy_rddata_valid, demand_priority_in, demand_act_priority_in,
data_buf_addr, col, cmd, clk, bm_end_in, bank, adv_order_q,
accept_req, accept_internal_r, rnk_config_kill_rts_col, phy_mc_ctl_full,
phy_mc_cmd_full, phy_mc_data_full
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_internal_r; // To bank_queue0 of bank_queue.v
input accept_req; // To bank_queue0 of bank_queue.v
input adv_order_q; // To bank_queue0 of bank_queue.v
input [BANK_WIDTH-1:0] bank; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] bm_end_in; // To bank_queue0 of bank_queue.v
input clk; // To bank_compare0 of bank_compare.v, ...
input [2:0] cmd; // To bank_compare0 of bank_compare.v
input [COL_WIDTH-1:0] col; // To bank_compare0 of bank_compare.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;// To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;// To bank_state0 of bank_state.v
input [(nBANK_MACHS*2)-1:0] demand_priority_in;// To bank_state0 of bank_state.v
input phy_rddata_valid; // To bank_state0 of bank_state.v
input dq_busy_data; // To bank_state0 of bank_state.v
input hi_priority; // To bank_compare0 of bank_compare.v
input [BM_CNT_WIDTH-1:0] idle_cnt; // To bank_queue0 of bank_queue.v
input [RANKS-1:0] inhbt_act_faw_r; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_rd; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_wr; // To bank_state0 of bank_state.v
input [RANK_WIDTH-1:0]rnk_config; // To bank_state0 of bank_state.v
input rnk_config_strobe; // To bank_state0 of bank_state.v
input rnk_config_kill_rts_col;// To bank_state0 of bank_state.v
input rnk_config_valid_r; // To bank_state0 of bank_state.v
input low_idle_cnt_r; // To bank_state0 of bank_state.v
input maint_idle; // To bank_queue0 of bank_queue.v
input [RANK_WIDTH-1:0] maint_rank_r; // To bank_compare0 of bank_compare.v
input maint_req_r; // To bank_queue0 of bank_queue.v
input maint_zq_r; // To bank_compare0 of bank_compare.v
input maint_sre_r; // To bank_compare0 of bank_compare.v
input op_exit_grant; // To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] order_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;// To bank_queue0 of bank_queue.v
input periodic_rd_ack_r; // To bank_queue0 of bank_queue.v
input periodic_rd_insert; // To bank_compare0 of bank_compare.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r; // To bank_compare0 of bank_compare.v
input phy_mc_ctl_full;
input phy_mc_cmd_full;
input phy_mc_data_full;
input [RANK_WIDTH-1:0] rank; // To bank_compare0 of bank_compare.v
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;// To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;// To bank_queue0 of bank_queue.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To bank_state0 of bank_state.v
input rd_rmw; // To bank_state0 of bank_state.v
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;// To bank_state0 of bank_state.v
input [ROW_WIDTH-1:0] row; // To bank_compare0 of bank_compare.v
input rst; // To bank_state0 of bank_state.v, ...
input sending_col; // To bank_compare0 of bank_compare.v, ...
input sending_row; // To bank_state0 of bank_state.v
input sending_pre;
input sent_col; // To bank_state0 of bank_state.v
input sent_row; // To bank_state0 of bank_state.v
input size; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] start_rcd_in; // To bank_state0 of bank_state.v
input use_addr; // To bank_queue0 of bank_queue.v
input was_priority; // To bank_queue0 of bank_queue.v
input was_wr; // To bank_queue0 of bank_queue.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [RANKS-1:0] act_this_rank_r; // From bank_state0 of bank_state.v
output [ROW_WIDTH-1:0] col_addr; // From bank_compare0 of bank_compare.v
output col_rdy_wr; // From bank_state0 of bank_state.v
output demand_act_priority; // From bank_state0 of bank_state.v
output demand_priority; // From bank_state0 of bank_state.v
output end_rtp; // From bank_state0 of bank_state.v
output op_exit_req; // From bank_state0 of bank_state.v
output ordered_issued; // From bank_queue0 of bank_queue.v
output ordered_r; // From bank_queue0 of bank_queue.v
output [RANKS-1:0] rank_busy_r; // From bank_compare0 of bank_compare.v
output [RAS_TIMER_WIDTH-1:0] ras_timer_ns; // From bank_state0 of bank_state.v
output rb_hit_busy_ns; // From bank_compare0 of bank_compare.v
output [RANKS-1:0] rd_this_rank_r; // From bank_state0 of bank_state.v
output [BANK_WIDTH-1:0] req_bank_r; // From bank_compare0 of bank_compare.v
output req_cas; // From bank_compare0 of bank_compare.v
output req_periodic_rd_r; // From bank_compare0 of bank_compare.v
output req_ras; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] req_row_r; // From bank_compare0 of bank_compare.v
output req_size_r; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] row_addr; // From bank_compare0 of bank_compare.v
output row_cmd_wr; // From bank_compare0 of bank_compare.v
output rtc; // From bank_state0 of bank_state.v
output rts_col; // From bank_state0 of bank_state.v
output rts_row; // From bank_state0 of bank_state.v
output rts_pre;
output start_pre_wait; // From bank_state0 of bank_state.v
output start_rcd; // From bank_state0 of bank_state.v
output [RANKS-1:0] wr_this_rank_r; // From bank_state0 of bank_state.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire act_wait_r; // From bank_state0 of bank_state.v
wire allow_auto_pre; // From bank_state0 of bank_state.v
wire auto_pre_r; // From bank_queue0 of bank_queue.v
wire bank_wait_in_progress; // From bank_state0 of bank_state.v
wire order_q_zero; // From bank_queue0 of bank_queue.v
wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v
wire pass_open_bank_r; // From bank_queue0 of bank_queue.v
wire pre_wait_r; // From bank_state0 of bank_state.v
wire precharge_bm_end; // From bank_state0 of bank_state.v
wire q_has_priority; // From bank_queue0 of bank_queue.v
wire q_has_rd; // From bank_queue0 of bank_queue.v
wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v
wire rcv_open_bank; // From bank_queue0 of bank_queue.v
wire rd_half_rmw; // From bank_state0 of bank_state.v
wire req_priority_r; // From bank_compare0 of bank_compare.v
wire row_hit_r; // From bank_compare0 of bank_compare.v
wire tail_r; // From bank_queue0 of bank_queue.v
wire wait_for_maint_r; // From bank_queue0 of bank_queue.v
// End of automatics
output idle_ns;
output req_wr_r;
output rd_wr_r;
output bm_end;
output idle_r;
output head_r;
output [RANK_WIDTH-1:0] req_rank_r;
output rb_hit_busy_r;
output passing_open_bank;
output maint_hit;
output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
mig_7series_v1_9_bank_compare #
(/*AUTOINSTPARAM*/
// Parameters
.BANK_WIDTH (BANK_WIDTH),
.TCQ (TCQ),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH))
bank_compare0
(/*AUTOINST*/
// Outputs
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r),
.req_size_r (req_size_r),
.rd_wr_r (rd_wr_r),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_bank_r (req_bank_r[BANK_WIDTH-1:0]),
.req_row_r (req_row_r[ROW_WIDTH-1:0]),
.req_wr_r (req_wr_r),
.req_priority_r (req_priority_r),
.rb_hit_busy_r (rb_hit_busy_r),
.rb_hit_busy_ns (rb_hit_busy_ns),
.row_hit_r (row_hit_r),
.maint_hit (maint_hit),
.col_addr (col_addr[ROW_WIDTH-1:0]),
.req_ras (req_ras),
.req_cas (req_cas),
.row_cmd_wr (row_cmd_wr),
.row_addr (row_addr[ROW_WIDTH-1:0]),
.rank_busy_r (rank_busy_r[RANKS-1:0]),
// Inputs
.clk (clk),
.idle_ns (idle_ns),
.idle_r (idle_r),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.periodic_rd_insert (periodic_rd_insert),
.size (size),
.cmd (cmd[2:0]),
.sending_col (sending_col),
.rank (rank[RANK_WIDTH-1:0]),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.hi_priority (hi_priority),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.auto_pre_r (auto_pre_r),
.rd_half_rmw (rd_half_rmw),
.act_wait_r (act_wait_r));
mig_7series_v1_9_bank_state #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRP (nRP),
.nRTP (nRTP),
.nRCD (nRCD),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank_state0
(/*AUTOINST*/
// Outputs
.start_rcd (start_rcd),
.act_wait_r (act_wait_r),
.rd_half_rmw (rd_half_rmw),
.ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]),
.end_rtp (end_rtp),
.bank_wait_in_progress (bank_wait_in_progress),
.start_pre_wait (start_pre_wait),
.op_exit_req (op_exit_req),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.precharge_bm_end (precharge_bm_end),
.demand_act_priority (demand_act_priority),
.rts_row (rts_row),
.rts_pre (rts_pre),
.act_this_rank_r (act_this_rank_r[RANKS-1:0]),
.demand_priority (demand_priority),
.col_rdy_wr (col_rdy_wr),
.rts_col (rts_col),
.wr_this_rank_r (wr_this_rank_r[RANKS-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANKS-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.bm_end (bm_end),
.pass_open_bank_r (pass_open_bank_r),
.sending_row (sending_row),
.sending_pre (sending_pre),
.rcv_open_bank (rcv_open_bank),
.sending_col (sending_col),
.rd_wr_r (rd_wr_r),
.req_wr_r (req_wr_r),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.rd_rmw (rd_rmw),
.ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]),
.rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]),
.idle_r (idle_r),
.passing_open_bank (passing_open_bank),
.low_idle_cnt_r (low_idle_cnt_r),
.op_exit_grant (op_exit_grant),
.tail_r (tail_r),
.auto_pre_r (auto_pre_r),
.pass_open_bank_ns (pass_open_bank_ns),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.rtc (rtc),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]),
.start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.wait_for_maint_r (wait_for_maint_r),
.head_r (head_r),
.sent_row (sent_row),
.demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]),
.order_q_zero (order_q_zero),
.sent_col (sent_col),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.req_priority_r (req_priority_r),
.idle_ns (idle_ns),
.demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.dq_busy_data (dq_busy_data));
mig_7series_v1_9_bank_queue #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.ORDERING (ORDERING),
.ID (ID))
bank_queue0
(/*AUTOINST*/
// Outputs
.head_r (head_r),
.tail_r (tail_r),
.idle_ns (idle_ns),
.idle_r (idle_r),
.pass_open_bank_ns (pass_open_bank_ns),
.pass_open_bank_r (pass_open_bank_r),
.auto_pre_r (auto_pre_r),
.bm_end (bm_end),
.passing_open_bank (passing_open_bank),
.ordered_issued (ordered_issued),
.ordered_r (ordered_r),
.order_q_zero (order_q_zero),
.rcv_open_bank (rcv_open_bank),
.rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.wait_for_maint_r (wait_for_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.accept_internal_r (accept_internal_r),
.use_addr (use_addr),
.periodic_rd_ack_r (periodic_rd_ack_r),
.bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.accept_req (accept_req),
.rb_hit_busy_r (rb_hit_busy_r),
.maint_idle (maint_idle),
.maint_hit (maint_hit),
.row_hit_r (row_hit_r),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.sending_col (sending_col),
.req_wr_r (req_wr_r),
.rd_wr_r (rd_wr_r),
.bank_wait_in_progress (bank_wait_in_progress),
.precharge_bm_end (precharge_bm_end),
.adv_order_q (adv_order_q),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]),
.passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]),
.was_wr (was_wr),
.maint_req_r (maint_req_r),
.was_priority (was_priority));
endmodule // bank_cntrl
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the tx_engine and buffers the input
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
input TXN_DONE_ACK, // Write transaction actual transfer length read
input [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather data
input SG_DATA_EMPTY, // Scatter gather buffer empty
output SG_DATA_REN, // Scatter gather data read enable
output SG_RST, // Scatter gather reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire wGateRen;
wire wGateEmpty;
wire [C_DATA_WIDTH:0] wGateData;
wire wBufWen;
wire [C_FIFO_DEPTH_WIDTH-1:0] wBufCount;
wire [C_DATA_WIDTH-1:0] wBufData;
wire wTxn;
wire wTxnAck;
wire wTxnLast;
wire [31:0] wTxnLen;
wire [30:0] wTxnOff;
wire [31:0] wTxnWordsRecvd;
wire wTxnDone;
wire wTxnErr;
wire wSgElemRen;
wire wSgElemRdy;
wire wSgElemEmpty;
wire [31:0] wSgElemLen;
wire [63:0] wSgElemAddr;
wire wTxLast;
reg [4:0] rWideRst=0;
reg rRst=0;
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Capture channel transaction open/close events as well as channel data.
tx_port_channel_gate_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.RD_CLK(CLK),
.RD_DATA(wGateData),
.RD_EMPTY(wGateEmpty),
.RD_EN(wGateRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
// Filter transaction events from channel data. Use the events to put only
// the requested amount of data into the port buffer.
tx_port_monitor_64 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
.RST(rRst),
.CLK(CLK),
.EVT_DATA(wGateData),
.EVT_DATA_EMPTY(wGateEmpty),
.EVT_DATA_RD_EN(wGateRen),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount),
.TXN(wTxn),
.ACK(wTxnAck),
.LAST(wTxnLast),
.LEN(wTxnLen),
.OFF(wTxnOff),
.WORDS_RECVD(wTxnWordsRecvd),
.DONE(wTxnDone),
.TX_ERR(SG_ERR)
);
// Buffer the incoming channel data. Also make sure to discard only as
// much data as is needed for a transfer (which may involve non-integral
// packets (i.e. reading only 1 word out of the packet).
tx_port_buffer_64 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
.CLK(CLK),
.RST(rRst | (TXN_DONE & wTxnErr)),
.RD_DATA(TX_DATA),
.RD_EN(TX_DATA_REN),
.LEN_VALID(TX_REQ_ACK),
.LEN_LSB(TX_LEN[0]),
.LEN_LAST(wTxLast),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | SG_RST),
.BUF_DATA(SG_DATA),
.BUF_DATA_EMPTY(SG_DATA_EMPTY),
.BUF_DATA_REN(SG_DATA_REN),
.VALID(wSgElemRdy),
.EMPTY(wSgElemEmpty),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Controls the flow of request to the tx engine for transfers in a transaction.
tx_port_writer writer (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN),
.TXN_ACK(TXN_ACK),
.TXN_LEN(TXN_LEN),
.TXN_OFF_LAST(TXN_OFF_LAST),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.NEW_TXN(wTxn),
.NEW_TXN_ACK(wTxnAck),
.NEW_TXN_LAST(wTxnLast),
.NEW_TXN_LEN(wTxnLen),
.NEW_TXN_OFF(wTxnOff),
.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
.NEW_TXN_DONE(wTxnDone),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_EMPTY(wSgElemEmpty),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(SG_RST),
.SG_ERR(SG_ERR),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_LAST(wTxLast),
.TX_SENT(TX_SENT)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
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// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_queue.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Bank machine queue controller.
//
// Bank machines are always associated with a queue. When the system is
// idle, all bank machines are in the idle queue. As requests are
// received, the bank machine at the head of the idle queue accepts
// the request, removes itself from the idle queue and places itself
// in a queue associated with the rank-bank of the new request.
//
// If the new request is to an idle rank-bank, a new queue is created
// for that rank-bank. If the rank-bank is not idle, then the new
// request is added to the end of the existing rank-bank queue.
//
// When the head of the idle queue accepts a new request, all other
// bank machines move down one in the idle queue. When the idle queue
// is empty, the memory interface deasserts its accept signal.
//
// When new requests are received, the first step is to classify them
// as to whether the request targets an already open rank-bank, and if
// so, does the new request also hit on the already open page? As mentioned
// above, a new request places itself in the existing queue for a
// rank-bank hit. If it is also detected that the last entry in the
// existing rank-bank queue has the same page, then the current tail
// sets a bit telling itself to pass the open row when the column
// command is issued. The "passee" knows its in the head minus one
// position and hence takes control of the rank-bank.
//
// Requests are retired out of order to optimize DRAM array resources.
// However it is required that the user cannot "observe" this out of
// order processing as a data corruption. An ordering queue is
// used to enforce some ordering rules. As controlled by a paramter,
// there can be no ordering (RELAXED), ordering of writes only (NORM), and
// strict (STRICT) ordering whereby input request ordering is
// strictly adhered to.
//
// Note that ordering applies only to column commands. Row commands
// such as activate and precharge are allowed to proceed in any order
// with the proviso that within a rank-bank row commands are processed in
// the request order.
//
// When a bank machine accepts a new request, it looks at the ordering
// mode. If no ordering, nothing is done. If strict ordering, then
// it always places itself at the end of the ordering queue. If "normal"
// or write ordering, the row machine places itself in the ordering
// queue only if the new request is a write. The bank state machine
// looks at the ordering queue, and will only issue a column
// command when it sees itself at the head of the ordering queue.
//
// When a bank machine has completed its request, it must re-enter the
// idle queue. This is done by setting the idle_r bit, and setting q_entry_r
// to the idle count.
//
// There are several situations where more than one bank machine
// will enter the idle queue simultaneously. If two or more
// simply use the idle count to place themselves in the idle queue, multiple
// bank machines will end up at the same location in the idle queue, which
// is illegal.
//
// Based on the bank machine instance numbers, a count is made of
// the number of bank machines entering idle "below" this instance. This
// number is added to the idle count to compute the location in
// idle queue.
//
// There is also a single bit computed that says there were bank machines
// entering the idle queue "above" this instance. This is used to
// compute the tail bit.
//
// The word "queue" is used frequently to describe the behavior of the
// bank_queue block. In reality, there are no queues in the ordinary sense.
// As instantiated in this block, each bank machine has a q_entry_r number.
// This number represents the position of the bank machine in its current
// queue. At any given time, a bank machine may be in the idle queue,
// one of the dynamic rank-bank queues, or a single entry manitenance queue.
// A complete description of which queue a bank machine is currently in is
// given by idle_r, its rank-bank, mainteance status and its q_entry_r number.
//
// DRAM refresh and ZQ have a private single entry queue/channel. However,
// when a refresh request is made, it must be injected into the main queue
// properly. At the time of injection, the refresh rank is compared against
// all entryies in the queue. For those that match, if timing allows, and
// they are the tail of the rank-bank queue, then the auto_pre bit is set.
// Otherwise precharge is in progress. This results in a fully precharged
// rank.
//
// At the time of injection, the refresh channel builds a bit
// vector of queue entries that hit on the refresh rank. Once all
// of these entries finish, the refresh is forced in at the row arbiter.
//
// New requests that come after the refresh request will notice that
// a refresh is in progress for their rank and wait for the refresh
// to finish before attempting to arbitrate to send an activate.
//
// Injection of a refresh sets the q_has_rd bit for all queues hitting
// on the refresh rank. This insures a starved write request will not
// indefinitely hold off a refresh.
//
// Periodic reads are required to compare themselves against requests
// that are in progress. Adding a unique compare channel for this
// is not worthwhile. Periodic read requests inhibit the accept
// signal and override any new request that might be trying to
// enter the queue.
//
// Once a periodic read has entered the queue it is nearly indistinguishable
// from a normal read request. The req_periodic_rd_r bit is set for
// queue entry. This signal is used to inhibit the rd_data_en signal.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v1_9_bank_queue #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter nBANK_MACHS = 4,
parameter ORDERING = "NORM",
parameter ID = 0
)
(/*AUTOARG*/
// Outputs
head_r, tail_r, idle_ns, idle_r, pass_open_bank_ns,
pass_open_bank_r, auto_pre_r, bm_end, passing_open_bank,
ordered_issued, ordered_r, order_q_zero, rcv_open_bank,
rb_hit_busies_r, q_has_rd, q_has_priority, wait_for_maint_r,
// Inputs
clk, rst, accept_internal_r, use_addr, periodic_rd_ack_r, bm_end_in,
idle_cnt, rb_hit_busy_cnt, accept_req, rb_hit_busy_r, maint_idle,
maint_hit, row_hit_r, pre_wait_r, allow_auto_pre, sending_col,
bank_wait_in_progress, precharge_bm_end, req_wr_r, rd_wr_r,
adv_order_q, order_cnt, rb_hit_busy_ns_in, passing_open_bank_in,
was_wr, maint_req_r, was_priority
);
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
// Decide if this bank machine should accept a new request.
reg idle_r_lcl;
reg head_r_lcl;
input accept_internal_r;
wire bm_ready = idle_r_lcl && head_r_lcl && accept_internal_r;
// Accept request in this bank machine. Could be maintenance or
// regular request.
input use_addr;
input periodic_rd_ack_r;
wire accept_this_bm = bm_ready && (use_addr || periodic_rd_ack_r);
// Multiple machines may enter the idle queue in a single state.
// Based on bank machine instance number, compute how many
// bank machines with lower instance numbers are entering
// the idle queue.
input [(nBANK_MACHS*2)-1:0] bm_end_in;
reg [BM_CNT_WIDTH-1:0] idlers_below;
integer i;
always @(/*AS*/bm_end_in) begin
idlers_below = BM_CNT_ZERO;
for (i=0; i<ID; i=i+1)
idlers_below = idlers_below + bm_end_in[i];
end
reg idlers_above;
always @(/*AS*/bm_end_in) begin
idlers_above = 1'b0;
for (i=ID+1; i<ID+nBANK_MACHS; i=i+1)
idlers_above = idlers_above || bm_end_in[i];
end
`ifdef MC_SVA
bm_end_and_idlers_above: cover property (@(posedge clk)
(~rst && bm_end && idlers_above));
bm_end_and_idlers_below: cover property (@(posedge clk)
(~rst && bm_end && |idlers_below));
`endif
// Compute the q_entry number.
input [BM_CNT_WIDTH-1:0] idle_cnt;
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
input accept_req;
wire bm_end_lcl;
reg adv_queue = 1'b0;
reg [BM_CNT_WIDTH-1:0] q_entry_r;
reg [BM_CNT_WIDTH-1:0] q_entry_ns;
wire [BM_CNT_WIDTH-1:0] temp;
// always @(/*AS*/accept_req or accept_this_bm or adv_queue
// or bm_end_lcl or idle_cnt or idle_r_lcl or idlers_below
// or q_entry_r or rb_hit_busy_cnt /*or rst*/) begin
//// if (rst) q_entry_ns = ID[BM_CNT_WIDTH-1:0];
//// else begin
// q_entry_ns = q_entry_r;
// if ((~idle_r_lcl && adv_queue) ||
// (idle_r_lcl && accept_req && ~accept_this_bm))
// q_entry_ns = q_entry_r - BM_CNT_ONE;
// if (accept_this_bm)
//// q_entry_ns = rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO);
// q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
// if (bm_end_lcl) begin
// q_entry_ns = idle_cnt + idlers_below;
// if (accept_req) q_entry_ns = q_entry_ns - BM_CNT_ONE;
//// end
// end
// end
assign temp = idle_cnt + idlers_below;
always @ (*)
begin
if (accept_req & bm_end_lcl)
q_entry_ns = temp - BM_CNT_ONE;
else if (bm_end_lcl)
q_entry_ns = temp;
else if (accept_this_bm)
q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
else if ((!idle_r_lcl & adv_queue) |
(idle_r_lcl & accept_req & !accept_this_bm))
q_entry_ns = q_entry_r - BM_CNT_ONE;
else
q_entry_ns = q_entry_r;
end
always @(posedge clk)
if (rst)
q_entry_r <= #TCQ ID[BM_CNT_WIDTH-1:0];
else
q_entry_r <= #TCQ q_entry_ns;
// Determine if this entry is the head of its queue.
reg head_ns;
always @(/*AS*/accept_req or accept_this_bm or adv_queue
or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl
or idlers_below or q_entry_r or rb_hit_busy_cnt or rst) begin
if (rst) head_ns = ~|ID[BM_CNT_WIDTH-1:0];
else begin
head_ns = head_r_lcl;
if (accept_this_bm)
head_ns = ~|(rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO));
if ((~idle_r_lcl && adv_queue) ||
(idle_r_lcl && accept_req && ~accept_this_bm))
head_ns = ~|(q_entry_r - BM_CNT_ONE);
if (bm_end_lcl) begin
head_ns = ~|(idle_cnt - (accept_req ? BM_CNT_ONE : BM_CNT_ZERO)) &&
~|idlers_below;
end
end
end
always @(posedge clk) head_r_lcl <= #TCQ head_ns;
output wire head_r;
assign head_r = head_r_lcl;
// Determine if this entry is the tail of its queue. Note that
// an entry can be both head and tail.
input rb_hit_busy_r;
reg tail_r_lcl = 1'b1;
generate
if (nBANK_MACHS > 1) begin : compute_tail
reg tail_ns;
always @(accept_req or accept_this_bm
or bm_end_in or bm_end_lcl or idle_r_lcl
or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin
if (rst) tail_ns = (ID == nBANK_MACHS);
// The order of the statements below is important in the case where
// another bank machine is retiring and this bank machine is accepting.
else begin
tail_ns = tail_r_lcl;
if ((accept_req && rb_hit_busy_r) ||
(|bm_end_in[`BM_SHARED_BV] && idle_r_lcl))
tail_ns = 1'b0;
if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1;
end
end
always @(posedge clk) tail_r_lcl <= #TCQ tail_ns;
end // if (nBANK_MACHS > 1)
endgenerate
output wire tail_r;
assign tail_r = tail_r_lcl;
wire clear_req = bm_end_lcl || rst;
// Is this entry in the idle queue?
reg idle_ns_lcl;
always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin
idle_ns_lcl = idle_r_lcl;
if (accept_this_bm) idle_ns_lcl = 1'b0;
if (clear_req) idle_ns_lcl = 1'b1;
end
always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl;
output wire idle_ns;
assign idle_ns = idle_ns_lcl;
output wire idle_r;
assign idle_r = idle_r_lcl;
// Maintenance hitting on this active bank machine is in progress.
input maint_idle;
input maint_hit;
wire maint_hit_this_bm = ~maint_idle && maint_hit;
// Does new request hit on this bank machine while it is able to pass the
// open bank?
input row_hit_r;
input pre_wait_r;
wire pass_open_bank_eligible =
tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r;
// Set pass open bank bit, but not if request preceded active maintenance.
reg wait_for_maint_r_lcl;
reg pass_open_bank_r_lcl;
wire pass_open_bank_ns_lcl = ~clear_req &&
(pass_open_bank_r_lcl ||
(accept_req && pass_open_bank_eligible &&
(~maint_hit_this_bm || wait_for_maint_r_lcl)));
always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl;
output wire pass_open_bank_ns;
assign pass_open_bank_ns = pass_open_bank_ns_lcl;
output wire pass_open_bank_r;
assign pass_open_bank_r = pass_open_bank_r_lcl;
`ifdef MC_SVA
pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns));
pass_open_bank_killed_by_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && ~wait_for_maint_r_lcl));
pass_open_bank_following_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && wait_for_maint_r_lcl));
`endif
// Should the column command be sent with the auto precharge bit set? This
// will happen when it is detected that next request is to a different row,
// or the next reqest is the next request is refresh to this rank.
reg auto_pre_r_lcl;
reg auto_pre_ns;
input allow_auto_pre;
always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl
or clear_req or maint_hit_this_bm or rb_hit_busy_r
or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin
auto_pre_ns = auto_pre_r_lcl;
if (clear_req) auto_pre_ns = 1'b0;
else
if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r &&
(~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl)))
auto_pre_ns = 1'b1;
end
always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns;
output wire auto_pre_r;
assign auto_pre_r = auto_pre_r_lcl;
`ifdef MC_SVA
auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns));
maint_triggers_auto_precharge: cover property (@(posedge clk)
(~rst && auto_pre_ns && ~auto_pre_r && row_hit_r));
`endif
// Determine when the current request is finished.
input sending_col;
input req_wr_r;
input rd_wr_r;
wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r);
input bank_wait_in_progress;
input precharge_bm_end;
reg pre_bm_end_r;
wire pre_bm_end_ns = precharge_bm_end ||
(bank_wait_in_progress && pass_open_bank_ns_lcl);
always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns;
assign bm_end_lcl =
pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
output wire bm_end;
assign bm_end = bm_end_lcl;
// Determine that the open bank should be passed to the successor bank machine.
reg pre_passing_open_bank_r;
wire pre_passing_open_bank_ns =
bank_wait_in_progress && pass_open_bank_ns_lcl;
always @(posedge clk) pre_passing_open_bank_r <= #TCQ
pre_passing_open_bank_ns;
output wire passing_open_bank;
assign passing_open_bank =
pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
reg ordered_ns;
wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") &&
req_wr_r)) && accept_this_bm;
wire ordered_issued_lcl =
sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) &&
((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r));
output wire ordered_issued;
assign ordered_issued = ordered_issued_lcl;
reg ordered_r_lcl;
always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst
or set_order_q) begin
if (rst) ordered_ns = 1'b0;
else begin
ordered_ns = ordered_r_lcl;
// Should never see accept_this_bm and adv_order_q at the same time.
if (set_order_q) ordered_ns = 1'b1;
if (ordered_issued_lcl) ordered_ns = 1'b0;
end
end
always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns;
output wire ordered_r;
assign ordered_r = ordered_r_lcl;
// Figure out when to advance the ordering queue.
input adv_order_q;
input [BM_CNT_WIDTH-1:0] order_cnt;
reg [BM_CNT_WIDTH-1:0] order_q_r;
reg [BM_CNT_WIDTH-1:0] order_q_ns;
always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst
or set_order_q) begin
order_q_ns = order_q_r;
if (rst) order_q_ns = BM_CNT_ZERO;
if (set_order_q)
if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE;
else order_q_ns = order_cnt;
if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE;
end
always @(posedge clk) order_q_r <= #TCQ order_q_ns;
output wire order_q_zero;
assign order_q_zero = ~|order_q_r ||
(adv_order_q && (order_q_r == BM_CNT_ONE)) ||
((ORDERING == "NORM") && rd_wr_r);
// Keep track of which other bank machine are ahead of this one in a
// rank-bank queue. This is necessary to know when to advance this bank
// machine in the queue, and when to update bank state machine counter upon
// passing a bank.
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;
reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}};
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;
output reg rcv_open_bank = 1'b0;
generate
if (nBANK_MACHS > 1) begin : rb_hit_busies
// The clear_vector resets bits in the rb_hit_busies vector as bank machines
// completes requests. rst also resets all the bits.
wire [nBANK_MACHS-2:0] clear_vector =
({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]);
// As this bank machine takes on a new request, capture the vector of
// which other bank machines are in the same queue.
wire [`BM_SHARED_BV] rb_hit_busies_ns =
~clear_vector &
(idle_ns_lcl
? rb_hit_busy_ns_in[`BM_SHARED_BV]
: rb_hit_busies_r_lcl[`BM_SHARED_BV]);
always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <=
#TCQ rb_hit_busies_ns;
// Compute when to advance this queue entry based on seeing other bank machines
// in the same queue finish.
always @(bm_end_in or rb_hit_busies_r_lcl)
adv_queue =
|(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]);
// Decide when to receive an open bank based on knowing this bank machine is
// one entry from the head, and a passing_open_bank hits on the
// rb_hit_busies vector.
always @(idle_r_lcl
or passing_open_bank_in or q_entry_r
or rb_hit_busies_r_lcl) rcv_open_bank =
|(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV])
&& (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl;
end
endgenerate
output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r;
assign rb_hit_busies_r = rb_hit_busies_r_lcl;
// Keep track if the queue this entry is in has priority content.
input was_wr;
input maint_req_r;
reg q_has_rd_r;
wire q_has_rd_ns = ~clear_req &&
(q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) ||
(maint_req_r && maint_hit && ~idle_r_lcl));
always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns;
output wire q_has_rd;
assign q_has_rd = q_has_rd_r;
input was_priority;
reg q_has_priority_r;
wire q_has_priority_ns = ~clear_req &&
(q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority));
always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns;
output wire q_has_priority;
assign q_has_priority = q_has_priority_r;
// Figure out if this entry should wait for maintenance to end.
wire wait_for_maint_ns = ~rst && ~maint_idle &&
(wait_for_maint_r_lcl || (maint_hit && accept_this_bm));
always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns;
output wire wait_for_maint_r;
assign wait_for_maint_r = wait_for_maint_r_lcl;
endmodule // bank_queue
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_buffer_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Wraps a FIFO for saving channel data and provides a
// registered read output. Data is available 3 cycles after RD_EN is asserted
// (not 1, like a traditional FIFO).
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_buffer_32 #(
parameter C_FIFO_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input RST,
input CLK,
input [C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
input WR_EN, // Input data write enable
output [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Input data FIFO is full
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // Output data
input RD_EN // Output data read enable
);
`include "functions.vh"
reg rFifoRdEn=0, _rFifoRdEn=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData={C_FIFO_DATA_WIDTH{1'd0}}, _rFifoData={C_FIFO_DATA_WIDTH{1'd0}};
wire [C_FIFO_DATA_WIDTH-1:0] wFifoData;
assign RD_DATA = rFifoData;
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rFifoRdEn <= #1 (RST ? 1'd0 : _rFifoRdEn);
end
always @ (*) begin
_rFifoRdEn = RD_EN;
end
// FIFO for storing data from the channel.
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
.CLK(CLK),
.RST(RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.FULL(),
.COUNT(WR_COUNT),
.RD_EN(rFifoRdEn),
.RD_DATA(wFifoData),
.EMPTY()
);
// Buffer data from the FIFO.
always @ (posedge CLK) begin
rFifoData <= #1 _rFifoData;
end
always @ (*) begin
_rFifoData = wFifoData;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Allowed import return types:
// void, byte, shortint, int, longint, real, shortreal, chandle, and string
// Scalar bit and logic
//
// Allowed argument types:
// Same as above plus packed arrays
import "DPI-C" pure function bit dpii_f_bit (input bit i);
import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i);
import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i);
import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i);
import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i);
import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i);
// Illegal to return > 32 bits, so we use longint
import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i);
import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i);
import "DPI-C" pure function int dpii_f_int (input int i);
import "DPI-C" pure function byte dpii_f_byte (input byte i);
import "DPI-C" pure function shortint dpii_f_shortint (input shortint i);
import "DPI-C" pure function longint dpii_f_longint (input longint i);
import "DPI-C" pure function chandle dpii_f_chandle (input chandle i);
import "DPI-C" pure function string dpii_f_string (input string i);
import "DPI-C" pure function real dpii_f_real (input real i);
`ifndef NO_SHORTREAL
import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i);
`endif
import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o);
import "DPI-C" pure function void dpii_v_int (input int i, output int o);
import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o);
import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o);
import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o);
import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o);
import "DPI-C" pure function void dpii_v_string (input string i, output string o);
import "DPI-C" pure function void dpii_v_real (input real i, output real o);
import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o);
import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o);
import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o);
`ifndef NO_SHORTREAL
import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o);
`endif
import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o);
import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o);
import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o);
import "DPI-C" pure function int dpii_f_strlen (input string i);
import "DPI-C" function void dpii_f_void ();
// Try a task
import "DPI-C" task dpii_t_void ();
import "DPI-C" context task dpii_t_void_context ();
import "DPI-C" task dpii_t_int (input int i, output int o);
// Try non-pure, aliasing with name
import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i);
import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i);
bit i_b, o_b;
bit [7:0] i_b8;
bit [8:0] i_b9;
bit [15:0] i_b16;
bit [16:0] i_b17;
bit [31:0] i_b32;
bit [32:0] i_b33, o_b33;
bit [63:0] i_b64, o_b64;
bit [94:0] i_b95, o_b95;
bit [95:0] i_b96, o_b96;
int i_i, o_i;
byte i_y, o_y;
shortint i_s, o_s;
longint i_l, o_l;
int unsigned i_iu, o_iu;
shortint unsigned i_su, o_su;
longint unsigned i_lu, o_lu;
// verilator lint_off UNDRIVEN
chandle i_c, o_c;
string i_n, o_n;
// verilator lint_on UNDRIVEN
real i_d, o_d;
`ifndef NO_SHORTREAL
shortreal i_f, o_f;
`endif
bit [94:0] wide;
bit [6*8:1] string6;
initial begin
wide = 95'h15caff7a73c48afee4ffcb57;
i_b = 1'b1;
i_b8 = {1'b1,wide[8-2:0]};
i_b9 = {1'b1,wide[9-2:0]};
i_b16 = {1'b1,wide[16-2:0]};
i_b17 = {1'b1,wide[17-2:0]};
i_b32 = {1'b1,wide[32-2:0]};
i_b33 = {1'b1,wide[33-2:0]};
i_b64 = {1'b1,wide[64-2:0]};
i_b95 = {1'b1,wide[95-2:0]};
i_b96 = {1'b1,wide[96-2:0]};
i_i = {1'b1,wide[32-2:0]};
i_iu= {1'b1,wide[32-2:0]};
i_y = {1'b1,wide[8-2:0]};
i_s = {1'b1,wide[16-2:0]};
i_su= {1'b1,wide[16-2:0]};
i_l = {1'b1,wide[64-2:0]};
i_lu= {1'b1,wide[64-2:0]};
i_d = 32.1;
`ifndef NO_SHORTREAL
i_f = 30.2;
`endif
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop;
if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop;
if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop;
if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop;
if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop;
// These return different sizes, so we need to truncate
// verilator lint_off WIDTH
o_b33 = dpii_f_bit33 (i_b33);
o_b64 = dpii_f_bit64 (i_b64);
// verilator lint_on WIDTH
if (o_b33 !== ~i_b33) $stop;
if (o_b64 !== ~i_b64) $stop;
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_int (i_i) !== ~i_i) $stop;
if (dpii_f_byte (i_y) !== ~i_y) $stop;
if (dpii_f_shortint (i_s) !== ~i_s) $stop;
if (dpii_f_longint (i_l) !== ~i_l) $stop;
if (dpii_f_chandle (i_c) !== i_c) $stop;
if (dpii_f_string (i_n) != i_n) $stop;
if (dpii_f_real (i_d) != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
if (dpii_f_shortreal(i_f) != i_f+1.5) $stop;
`endif
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop;
dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop;
dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop;
dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop;
dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop;
dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop;
dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop;
dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop;
dpii_v_string (i_n,o_n); if (o_n != i_n) $stop;
dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop;
`endif
dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop;
dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop;
dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop;
if (dpii_f_strlen ("")!=0) $stop;
if (dpii_f_strlen ("s")!=1) $stop;
if (dpii_f_strlen ("st")!=2) $stop;
if (dpii_f_strlen ("str")!=3) $stop;
if (dpii_f_strlen ("stri")!=4) $stop;
if (dpii_f_strlen ("string_l")!=8) $stop;
if (dpii_f_strlen ("string_len")!=10) $stop;
string6 = "hello6";
`ifdef VERILATOR
string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function
`endif
if (dpii_f_strlen (string6) != 6) $stop;
dpii_f_void();
dpii_t_void();
dpii_t_void_context();
i_i = 32'h456789ab;
dpii_t_int (i_i,o_i); if (o_b !== ~i_b) $stop;
// Check alias
if (oth_f_int1(32'd123) !== ~32'd123) $stop;
if (oth_f_int2(32'd124) !== ~32'd124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
i_b <= ~i_b;
// This once mis-threw a BLKSEQ warning
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Allowed import return types:
// void, byte, shortint, int, longint, real, shortreal, chandle, and string
// Scalar bit and logic
//
// Allowed argument types:
// Same as above plus packed arrays
import "DPI-C" pure function bit dpii_f_bit (input bit i);
import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i);
import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i);
import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i);
import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i);
import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i);
// Illegal to return > 32 bits, so we use longint
import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i);
import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i);
import "DPI-C" pure function int dpii_f_int (input int i);
import "DPI-C" pure function byte dpii_f_byte (input byte i);
import "DPI-C" pure function shortint dpii_f_shortint (input shortint i);
import "DPI-C" pure function longint dpii_f_longint (input longint i);
import "DPI-C" pure function chandle dpii_f_chandle (input chandle i);
import "DPI-C" pure function string dpii_f_string (input string i);
import "DPI-C" pure function real dpii_f_real (input real i);
`ifndef NO_SHORTREAL
import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i);
`endif
import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o);
import "DPI-C" pure function void dpii_v_int (input int i, output int o);
import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o);
import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o);
import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o);
import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o);
import "DPI-C" pure function void dpii_v_string (input string i, output string o);
import "DPI-C" pure function void dpii_v_real (input real i, output real o);
import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o);
import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o);
import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o);
`ifndef NO_SHORTREAL
import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o);
`endif
import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o);
import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o);
import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o);
import "DPI-C" pure function int dpii_f_strlen (input string i);
import "DPI-C" function void dpii_f_void ();
// Try a task
import "DPI-C" task dpii_t_void ();
import "DPI-C" context task dpii_t_void_context ();
import "DPI-C" task dpii_t_int (input int i, output int o);
// Try non-pure, aliasing with name
import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i);
import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i);
bit i_b, o_b;
bit [7:0] i_b8;
bit [8:0] i_b9;
bit [15:0] i_b16;
bit [16:0] i_b17;
bit [31:0] i_b32;
bit [32:0] i_b33, o_b33;
bit [63:0] i_b64, o_b64;
bit [94:0] i_b95, o_b95;
bit [95:0] i_b96, o_b96;
int i_i, o_i;
byte i_y, o_y;
shortint i_s, o_s;
longint i_l, o_l;
int unsigned i_iu, o_iu;
shortint unsigned i_su, o_su;
longint unsigned i_lu, o_lu;
// verilator lint_off UNDRIVEN
chandle i_c, o_c;
string i_n, o_n;
// verilator lint_on UNDRIVEN
real i_d, o_d;
`ifndef NO_SHORTREAL
shortreal i_f, o_f;
`endif
bit [94:0] wide;
bit [6*8:1] string6;
initial begin
wide = 95'h15caff7a73c48afee4ffcb57;
i_b = 1'b1;
i_b8 = {1'b1,wide[8-2:0]};
i_b9 = {1'b1,wide[9-2:0]};
i_b16 = {1'b1,wide[16-2:0]};
i_b17 = {1'b1,wide[17-2:0]};
i_b32 = {1'b1,wide[32-2:0]};
i_b33 = {1'b1,wide[33-2:0]};
i_b64 = {1'b1,wide[64-2:0]};
i_b95 = {1'b1,wide[95-2:0]};
i_b96 = {1'b1,wide[96-2:0]};
i_i = {1'b1,wide[32-2:0]};
i_iu= {1'b1,wide[32-2:0]};
i_y = {1'b1,wide[8-2:0]};
i_s = {1'b1,wide[16-2:0]};
i_su= {1'b1,wide[16-2:0]};
i_l = {1'b1,wide[64-2:0]};
i_lu= {1'b1,wide[64-2:0]};
i_d = 32.1;
`ifndef NO_SHORTREAL
i_f = 30.2;
`endif
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop;
if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop;
if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop;
if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop;
if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop;
// These return different sizes, so we need to truncate
// verilator lint_off WIDTH
o_b33 = dpii_f_bit33 (i_b33);
o_b64 = dpii_f_bit64 (i_b64);
// verilator lint_on WIDTH
if (o_b33 !== ~i_b33) $stop;
if (o_b64 !== ~i_b64) $stop;
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_int (i_i) !== ~i_i) $stop;
if (dpii_f_byte (i_y) !== ~i_y) $stop;
if (dpii_f_shortint (i_s) !== ~i_s) $stop;
if (dpii_f_longint (i_l) !== ~i_l) $stop;
if (dpii_f_chandle (i_c) !== i_c) $stop;
if (dpii_f_string (i_n) != i_n) $stop;
if (dpii_f_real (i_d) != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
if (dpii_f_shortreal(i_f) != i_f+1.5) $stop;
`endif
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop;
dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop;
dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop;
dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop;
dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop;
dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop;
dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop;
dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop;
dpii_v_string (i_n,o_n); if (o_n != i_n) $stop;
dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop;
`endif
dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop;
dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop;
dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop;
if (dpii_f_strlen ("")!=0) $stop;
if (dpii_f_strlen ("s")!=1) $stop;
if (dpii_f_strlen ("st")!=2) $stop;
if (dpii_f_strlen ("str")!=3) $stop;
if (dpii_f_strlen ("stri")!=4) $stop;
if (dpii_f_strlen ("string_l")!=8) $stop;
if (dpii_f_strlen ("string_len")!=10) $stop;
string6 = "hello6";
`ifdef VERILATOR
string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function
`endif
if (dpii_f_strlen (string6) != 6) $stop;
dpii_f_void();
dpii_t_void();
dpii_t_void_context();
i_i = 32'h456789ab;
dpii_t_int (i_i,o_i); if (o_b !== ~i_b) $stop;
// Check alias
if (oth_f_int1(32'd123) !== ~32'd123) $stop;
if (oth_f_int2(32'd124) !== ~32'd124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
i_b <= ~i_b;
// This once mis-threw a BLKSEQ warning
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Allowed import return types:
// void, byte, shortint, int, longint, real, shortreal, chandle, and string
// Scalar bit and logic
//
// Allowed argument types:
// Same as above plus packed arrays
import "DPI-C" pure function bit dpii_f_bit (input bit i);
import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i);
import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i);
import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i);
import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i);
import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i);
// Illegal to return > 32 bits, so we use longint
import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i);
import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i);
import "DPI-C" pure function int dpii_f_int (input int i);
import "DPI-C" pure function byte dpii_f_byte (input byte i);
import "DPI-C" pure function shortint dpii_f_shortint (input shortint i);
import "DPI-C" pure function longint dpii_f_longint (input longint i);
import "DPI-C" pure function chandle dpii_f_chandle (input chandle i);
import "DPI-C" pure function string dpii_f_string (input string i);
import "DPI-C" pure function real dpii_f_real (input real i);
`ifndef NO_SHORTREAL
import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i);
`endif
import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o);
import "DPI-C" pure function void dpii_v_int (input int i, output int o);
import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o);
import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o);
import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o);
import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o);
import "DPI-C" pure function void dpii_v_string (input string i, output string o);
import "DPI-C" pure function void dpii_v_real (input real i, output real o);
import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o);
import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o);
import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o);
`ifndef NO_SHORTREAL
import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o);
`endif
import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o);
import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o);
import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o);
import "DPI-C" pure function int dpii_f_strlen (input string i);
import "DPI-C" function void dpii_f_void ();
// Try a task
import "DPI-C" task dpii_t_void ();
import "DPI-C" context task dpii_t_void_context ();
import "DPI-C" task dpii_t_int (input int i, output int o);
// Try non-pure, aliasing with name
import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i);
import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i);
bit i_b, o_b;
bit [7:0] i_b8;
bit [8:0] i_b9;
bit [15:0] i_b16;
bit [16:0] i_b17;
bit [31:0] i_b32;
bit [32:0] i_b33, o_b33;
bit [63:0] i_b64, o_b64;
bit [94:0] i_b95, o_b95;
bit [95:0] i_b96, o_b96;
int i_i, o_i;
byte i_y, o_y;
shortint i_s, o_s;
longint i_l, o_l;
int unsigned i_iu, o_iu;
shortint unsigned i_su, o_su;
longint unsigned i_lu, o_lu;
// verilator lint_off UNDRIVEN
chandle i_c, o_c;
string i_n, o_n;
// verilator lint_on UNDRIVEN
real i_d, o_d;
`ifndef NO_SHORTREAL
shortreal i_f, o_f;
`endif
bit [94:0] wide;
bit [6*8:1] string6;
initial begin
wide = 95'h15caff7a73c48afee4ffcb57;
i_b = 1'b1;
i_b8 = {1'b1,wide[8-2:0]};
i_b9 = {1'b1,wide[9-2:0]};
i_b16 = {1'b1,wide[16-2:0]};
i_b17 = {1'b1,wide[17-2:0]};
i_b32 = {1'b1,wide[32-2:0]};
i_b33 = {1'b1,wide[33-2:0]};
i_b64 = {1'b1,wide[64-2:0]};
i_b95 = {1'b1,wide[95-2:0]};
i_b96 = {1'b1,wide[96-2:0]};
i_i = {1'b1,wide[32-2:0]};
i_iu= {1'b1,wide[32-2:0]};
i_y = {1'b1,wide[8-2:0]};
i_s = {1'b1,wide[16-2:0]};
i_su= {1'b1,wide[16-2:0]};
i_l = {1'b1,wide[64-2:0]};
i_lu= {1'b1,wide[64-2:0]};
i_d = 32.1;
`ifndef NO_SHORTREAL
i_f = 30.2;
`endif
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop;
if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop;
if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop;
if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop;
if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop;
// These return different sizes, so we need to truncate
// verilator lint_off WIDTH
o_b33 = dpii_f_bit33 (i_b33);
o_b64 = dpii_f_bit64 (i_b64);
// verilator lint_on WIDTH
if (o_b33 !== ~i_b33) $stop;
if (o_b64 !== ~i_b64) $stop;
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_int (i_i) !== ~i_i) $stop;
if (dpii_f_byte (i_y) !== ~i_y) $stop;
if (dpii_f_shortint (i_s) !== ~i_s) $stop;
if (dpii_f_longint (i_l) !== ~i_l) $stop;
if (dpii_f_chandle (i_c) !== i_c) $stop;
if (dpii_f_string (i_n) != i_n) $stop;
if (dpii_f_real (i_d) != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
if (dpii_f_shortreal(i_f) != i_f+1.5) $stop;
`endif
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop;
dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop;
dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop;
dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop;
dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop;
dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop;
dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop;
dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop;
dpii_v_string (i_n,o_n); if (o_n != i_n) $stop;
dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop;
`endif
dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop;
dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop;
dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop;
if (dpii_f_strlen ("")!=0) $stop;
if (dpii_f_strlen ("s")!=1) $stop;
if (dpii_f_strlen ("st")!=2) $stop;
if (dpii_f_strlen ("str")!=3) $stop;
if (dpii_f_strlen ("stri")!=4) $stop;
if (dpii_f_strlen ("string_l")!=8) $stop;
if (dpii_f_strlen ("string_len")!=10) $stop;
string6 = "hello6";
`ifdef VERILATOR
string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function
`endif
if (dpii_f_strlen (string6) != 6) $stop;
dpii_f_void();
dpii_t_void();
dpii_t_void_context();
i_i = 32'h456789ab;
dpii_t_int (i_i,o_i); if (o_b !== ~i_b) $stop;
// Check alias
if (oth_f_int1(32'd123) !== ~32'd123) $stop;
if (oth_f_int2(32'd124) !== ~32'd124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
i_b <= ~i_b;
// This once mis-threw a BLKSEQ warning
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Allowed import return types:
// void, byte, shortint, int, longint, real, shortreal, chandle, and string
// Scalar bit and logic
//
// Allowed argument types:
// Same as above plus packed arrays
import "DPI-C" pure function bit dpii_f_bit (input bit i);
import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i);
import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i);
import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i);
import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i);
import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i);
// Illegal to return > 32 bits, so we use longint
import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i);
import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i);
import "DPI-C" pure function int dpii_f_int (input int i);
import "DPI-C" pure function byte dpii_f_byte (input byte i);
import "DPI-C" pure function shortint dpii_f_shortint (input shortint i);
import "DPI-C" pure function longint dpii_f_longint (input longint i);
import "DPI-C" pure function chandle dpii_f_chandle (input chandle i);
import "DPI-C" pure function string dpii_f_string (input string i);
import "DPI-C" pure function real dpii_f_real (input real i);
`ifndef NO_SHORTREAL
import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i);
`endif
import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o);
import "DPI-C" pure function void dpii_v_int (input int i, output int o);
import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o);
import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o);
import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o);
import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o);
import "DPI-C" pure function void dpii_v_string (input string i, output string o);
import "DPI-C" pure function void dpii_v_real (input real i, output real o);
import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o);
import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o);
import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o);
`ifndef NO_SHORTREAL
import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o);
`endif
import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o);
import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o);
import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o);
import "DPI-C" pure function int dpii_f_strlen (input string i);
import "DPI-C" function void dpii_f_void ();
// Try a task
import "DPI-C" task dpii_t_void ();
import "DPI-C" context task dpii_t_void_context ();
import "DPI-C" task dpii_t_int (input int i, output int o);
// Try non-pure, aliasing with name
import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i);
import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i);
bit i_b, o_b;
bit [7:0] i_b8;
bit [8:0] i_b9;
bit [15:0] i_b16;
bit [16:0] i_b17;
bit [31:0] i_b32;
bit [32:0] i_b33, o_b33;
bit [63:0] i_b64, o_b64;
bit [94:0] i_b95, o_b95;
bit [95:0] i_b96, o_b96;
int i_i, o_i;
byte i_y, o_y;
shortint i_s, o_s;
longint i_l, o_l;
int unsigned i_iu, o_iu;
shortint unsigned i_su, o_su;
longint unsigned i_lu, o_lu;
// verilator lint_off UNDRIVEN
chandle i_c, o_c;
string i_n, o_n;
// verilator lint_on UNDRIVEN
real i_d, o_d;
`ifndef NO_SHORTREAL
shortreal i_f, o_f;
`endif
bit [94:0] wide;
bit [6*8:1] string6;
initial begin
wide = 95'h15caff7a73c48afee4ffcb57;
i_b = 1'b1;
i_b8 = {1'b1,wide[8-2:0]};
i_b9 = {1'b1,wide[9-2:0]};
i_b16 = {1'b1,wide[16-2:0]};
i_b17 = {1'b1,wide[17-2:0]};
i_b32 = {1'b1,wide[32-2:0]};
i_b33 = {1'b1,wide[33-2:0]};
i_b64 = {1'b1,wide[64-2:0]};
i_b95 = {1'b1,wide[95-2:0]};
i_b96 = {1'b1,wide[96-2:0]};
i_i = {1'b1,wide[32-2:0]};
i_iu= {1'b1,wide[32-2:0]};
i_y = {1'b1,wide[8-2:0]};
i_s = {1'b1,wide[16-2:0]};
i_su= {1'b1,wide[16-2:0]};
i_l = {1'b1,wide[64-2:0]};
i_lu= {1'b1,wide[64-2:0]};
i_d = 32.1;
`ifndef NO_SHORTREAL
i_f = 30.2;
`endif
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop;
if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop;
if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop;
if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop;
if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop;
// These return different sizes, so we need to truncate
// verilator lint_off WIDTH
o_b33 = dpii_f_bit33 (i_b33);
o_b64 = dpii_f_bit64 (i_b64);
// verilator lint_on WIDTH
if (o_b33 !== ~i_b33) $stop;
if (o_b64 !== ~i_b64) $stop;
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_int (i_i) !== ~i_i) $stop;
if (dpii_f_byte (i_y) !== ~i_y) $stop;
if (dpii_f_shortint (i_s) !== ~i_s) $stop;
if (dpii_f_longint (i_l) !== ~i_l) $stop;
if (dpii_f_chandle (i_c) !== i_c) $stop;
if (dpii_f_string (i_n) != i_n) $stop;
if (dpii_f_real (i_d) != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
if (dpii_f_shortreal(i_f) != i_f+1.5) $stop;
`endif
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop;
dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop;
dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop;
dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop;
dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop;
dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop;
dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop;
dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop;
dpii_v_string (i_n,o_n); if (o_n != i_n) $stop;
dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop;
`endif
dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop;
dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop;
dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop;
if (dpii_f_strlen ("")!=0) $stop;
if (dpii_f_strlen ("s")!=1) $stop;
if (dpii_f_strlen ("st")!=2) $stop;
if (dpii_f_strlen ("str")!=3) $stop;
if (dpii_f_strlen ("stri")!=4) $stop;
if (dpii_f_strlen ("string_l")!=8) $stop;
if (dpii_f_strlen ("string_len")!=10) $stop;
string6 = "hello6";
`ifdef VERILATOR
string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function
`endif
if (dpii_f_strlen (string6) != 6) $stop;
dpii_f_void();
dpii_t_void();
dpii_t_void_context();
i_i = 32'h456789ab;
dpii_t_int (i_i,o_i); if (o_b !== ~i_b) $stop;
// Check alias
if (oth_f_int1(32'd123) !== ~32'd123) $stop;
if (oth_f_int2(32'd124) !== ~32'd124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
i_b <= ~i_b;
// This once mis-threw a BLKSEQ warning
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef int unit_type_t;
function [3:0] unit_plusone(input [3:0] i);
unit_plusone = i+1;
endfunction
package p;
typedef int package_type_t;
integer pi = 123;
function [3:0] plusone(input [3:0] i);
plusone = i+1;
endfunction
endpackage
package p2;
typedef int package2_type_t;
function [3:0] plustwo(input [3:0] i);
plustwo = i+2;
endfunction
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
unit_type_t vu;
$unit::unit_type_t vdu;
p::package_type_t vp;
t2 t2 ();
initial begin
if (unit_plusone(1) !== 2) $stop;
if ($unit::unit_plusone(1) !== 2) $stop;
if (p::plusone(1) !== 2) $stop;
p::pi = 124;
if (p::pi !== 124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
p::pi += 1;
if (p::pi < 124) $stop;
end
endmodule
module t2;
import p::*;
import p2::plustwo;
import p2::package2_type_t;
package_type_t vp;
package2_type_t vp2;
initial begin
if (plusone(1) !== 2) $stop;
if (plustwo(1) !== 3) $stop;
if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef int unit_type_t;
function [3:0] unit_plusone(input [3:0] i);
unit_plusone = i+1;
endfunction
package p;
typedef int package_type_t;
integer pi = 123;
function [3:0] plusone(input [3:0] i);
plusone = i+1;
endfunction
endpackage
package p2;
typedef int package2_type_t;
function [3:0] plustwo(input [3:0] i);
plustwo = i+2;
endfunction
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
unit_type_t vu;
$unit::unit_type_t vdu;
p::package_type_t vp;
t2 t2 ();
initial begin
if (unit_plusone(1) !== 2) $stop;
if ($unit::unit_plusone(1) !== 2) $stop;
if (p::plusone(1) !== 2) $stop;
p::pi = 124;
if (p::pi !== 124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
p::pi += 1;
if (p::pi < 124) $stop;
end
endmodule
module t2;
import p::*;
import p2::plustwo;
import p2::package2_type_t;
package_type_t vp;
package2_type_t vp2;
initial begin
if (plusone(1) !== 2) $stop;
if (plustwo(1) !== 3) $stop;
if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef int unit_type_t;
function [3:0] unit_plusone(input [3:0] i);
unit_plusone = i+1;
endfunction
package p;
typedef int package_type_t;
integer pi = 123;
function [3:0] plusone(input [3:0] i);
plusone = i+1;
endfunction
endpackage
package p2;
typedef int package2_type_t;
function [3:0] plustwo(input [3:0] i);
plustwo = i+2;
endfunction
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
unit_type_t vu;
$unit::unit_type_t vdu;
p::package_type_t vp;
t2 t2 ();
initial begin
if (unit_plusone(1) !== 2) $stop;
if ($unit::unit_plusone(1) !== 2) $stop;
if (p::plusone(1) !== 2) $stop;
p::pi = 124;
if (p::pi !== 124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
p::pi += 1;
if (p::pi < 124) $stop;
end
endmodule
module t2;
import p::*;
import p2::plustwo;
import p2::package2_type_t;
package_type_t vp;
package2_type_t vp2;
initial begin
if (plusone(1) !== 2) $stop;
if (plustwo(1) !== 3) $stop;
if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [19:10] bitout;
wire [29:24] short_bitout;
wire [7:0] allbits;
wire [15:0] twobits;
sub
i_sub1 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14])),
i_sub2 [3:0] (.allbits (allbits),
.twobits (twobits[7:0]),
.bitout (bitout[13:10]));
sub
i_sub3 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14]));
sub
i_sub4 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (short_bitout[27:24]));
sub
i_sub5 [7:0] (.allbits (allbits),
.twobits (twobits),
.bitout (bitout[17:10]));
sub
i_sub6 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout ({bitout[18+:2],short_bitout[28+:2]}));
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Signals under test
assign allbits = crc[7:0];
assign twobits = crc[15:0];
wire [63:0] result = {48'h0, short_bitout, bitout};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha1da9ff8082a4ff6
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule // t
module sub
( input wire [7:0] allbits,
input wire [1:0] twobits,
output wire bitout);
assign bitout = (^ twobits) ^ (^ allbits);
endmodule // sub
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_calib_top.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:06 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
//Purpose:
// Top-level for memory physical layer (PHY) interface
// NOTES:
// 1. Need to support multiple copies of CS outputs
// 2. DFI_DRAM_CKE_DISABLE not supported
//
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $
**$Date: 2011/06/02 08:35:06 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_calib_top #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter tCK = 2500, // DDR3 SDRAM clock period
parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter PRBS_WIDTH = 8, // The PRBS sequence is 2^PRBS_WIDTH
parameter HIGHEST_LANE = 4,
parameter HIGHEST_BANK = 3,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
// five fields, one per possible I/O bank, 4 bits in each field,
// 1 per lane data=1/ctl=0
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
// defines the byte lanes in I/O banks being used in the interface
// 1- Used, 0- Unused
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter CTL_BYTE_LANE = 8'hE4, // Control byte lane map
parameter CTL_BANK = 3'b000, // Bank used for control byte lanes
// Slot Conifg parameters
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
// DRAM bus widths
parameter BANK_WIDTH = 2, // # of bank bits
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter COL_WIDTH = 10, // column address width
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ROW_WIDTH = 14, // DRAM address bus width
parameter RANKS = 1, // # of memory ranks in the interface
parameter CS_WIDTH = 1, // # of CS# signals in the interface
parameter CKE_WIDTH = 1, // # of cke outputs
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter PER_BIT_DESKEW = "ON",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter NUM_DQSFOUND_CAL = 1020, // # of iteration of DQSFOUND calib
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// DRAM mode settings
parameter AL = "0", // Additive Latency option
parameter TEST_AL = "0", // Additive Latency for internal use
parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T"
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter nCL = 5, // Read CAS latency (in clk cyc)
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter tRFC = 110000, // Refresh-to-command delay
parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RTT_NOM = "60", // ODT Nominal termination value
parameter RTT_WR = "60", // ODT Write termination value
parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA
// 1 - ODT output from FPGA
parameter WRLVL = "OFF", // Enable write leveling
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
// Simulation /debug options
parameter SIM_INIT_OPTION = "NONE", // Performs all initialization steps
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter CKE_ODT_AUX = "FALSE",
parameter DEBUG_PORT = "OFF" // Enable debug port
)
(
input clk, // Internal (logic) clock
input rst, // Reset sync'ed to CLK
// Slot present inputs
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// Hard PHY signals
// From PHY Ctrl Block
input phy_ctl_ready,
input phy_ctl_full,
input phy_cmd_full,
input phy_data_full,
// To PHY Ctrl Block
output write_calib,
output read_calib,
output calib_ctl_wren,
output calib_cmd_wren,
output [1:0] calib_seq,
output [3:0] calib_aux_out,
output [nCK_PER_CLK -1:0] calib_cke,
output [1:0] calib_odt,
output [2:0] calib_cmd,
output calib_wrdata_en,
output [1:0] calib_rank_cnt,
output [1:0] calib_cas_slot,
output [5:0] calib_data_offset_0,
output [5:0] calib_data_offset_1,
output [5:0] calib_data_offset_2,
output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,
output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,
output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,
output [nCK_PER_CLK-1:0] phy_ras_n,
output [nCK_PER_CLK-1:0] phy_cas_n,
output [nCK_PER_CLK-1:0] phy_we_n,
output phy_reset_n,
// To hard PHY wrapper
(* keep = "true", max_fanout = 10 *) output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 */,
(* keep = "true", max_fanout = 10 *) output reg calib_in_common/* synthesis syn_maxfan = 10 */,
(* keep = "true", max_fanout = 10 *) output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 */,
output reg [HIGHEST_BANK-1:0] calib_zero_ctrl,
output phy_if_empty_def,
output reg phy_if_reset,
// output reg ck_addr_ctl_delay_done,
// From DQS Phaser_In
input pi_phaselocked,
input pi_phase_locked_all,
input pi_found_dqs,
input pi_dqs_found_all,
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
input [5:0] pi_counter_read_val,
// To DQS Phaser_In
output [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
output pi_en_stg2_f,
output pi_stg2_f_incdec,
output pi_stg2_load,
output [5:0] pi_stg2_reg_l,
// To DQ IDELAY
output idelay_ce,
output idelay_inc,
output idelay_ld,
// To DQS Phaser_Out
(* keep = "true", max_fanout = 3 *) output [2:0] po_sel_stg2stg3 /* synthesis syn_maxfan = 3 */,
(* keep = "true", max_fanout = 3 *) output [2:0] po_stg2_c_incdec /* synthesis syn_maxfan = 3 */,
(* keep = "true", max_fanout = 3 *) output [2:0] po_en_stg2_c /* synthesis syn_maxfan = 3 */,
(* keep = "true", max_fanout = 3 *) output [2:0] po_stg2_f_incdec /* synthesis syn_maxfan = 3 */,
(* keep = "true", max_fanout = 3 *) output [2:0] po_en_stg2_f /* synthesis syn_maxfan = 3 */,
output po_counter_load_en,
input [8:0] po_counter_read_val,
// To command Phaser_Out
input phy_if_empty,
input [4:0] idelaye2_init_val,
input [5:0] oclkdelay_init_val,
input tg_err,
output rst_tg_mc,
// Write data to OUT_FIFO
output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata,
// To CNTVALUEIN input of DQ IDELAYs for perbit de-skew
output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,
// IN_FIFO read enable during write leveling, write calibration,
// and read leveling
// Read data from hard PHY fans out to mc and calib logic
input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata,
// To MC
output [6*RANKS-1:0] calib_rd_data_offset_0,
output [6*RANKS-1:0] calib_rd_data_offset_1,
output [6*RANKS-1:0] calib_rd_data_offset_2,
output phy_rddata_valid,
output calib_writes,
(* keep = "true", max_fanout = 10 *) output reg init_calib_complete/* synthesis syn_maxfan = 10 */,
output init_wrcal_complete,
output pi_phase_locked_err,
output pi_dqsfound_err,
output wrcal_err,
// Debug Port
output dbg_pi_phaselock_start,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrlvl_start,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output [255:0] dbg_phy_wrlvl,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
// Write Calibration Logic
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [99:0] dbg_phy_wrcal,
// Read leveling logic
output [1:0] dbg_rdlvl_start,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
// Delay control
input [11:0] device_temp,
input tempmon_sample_en,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_cpt,
input dbg_idel_down_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input dbg_sel_all_idel_cpt,
output [255:0] dbg_phy_rdlvl, // Read leveling calibration
output [255:0] dbg_calib_top, // General PHY debug
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal
);
// Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center
// align DQ and DQS on writes. Round (up or down) value to nearest integer
// localparam integer SHIFT_TBY4_TAP
// = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) /
// (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4);
// Calculate number of slots in the system
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
localparam OCAL_EN = ((SIM_CAL_OPTION == "FAST_CAL") || (tCK > 2500)) ? "OFF" : "ON";
// Different CTL_LANES value for DDR2. In DDR2 during DQS found all
// the add,ctl & data phaser out fine delays will be adjusted.
// In DDR3 only the add/ctrl lane delays will be adjusted
localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == "DDR3") ? N_CTL_LANES : 1;
localparam DQSFOUND_CAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && tCK > 2500)) ? "LEFT" : "RIGHT"; // IO Bank used for Memory I/F: "LEFT", "RIGHT"
wire [2*8*nCK_PER_CLK-1:0] prbs_seed;
wire [2*8*nCK_PER_CLK-1:0] prbs_out;
wire [7:0] prbs_rise0;
wire [7:0] prbs_fall0;
wire [7:0] prbs_rise1;
wire [7:0] prbs_fall1;
wire [7:0] prbs_rise2;
wire [7:0] prbs_fall2;
wire [7:0] prbs_rise3;
wire [7:0] prbs_fall3;
wire [2*8*nCK_PER_CLK-1:0] prbs_o;
wire dqsfound_retry;
wire dqsfound_retry_done;
wire phy_rddata_en;
wire prech_done;
wire rdlvl_stg1_done;
reg rdlvl_stg1_done_r1;
wire pi_dqs_found_done;
wire rdlvl_stg1_err;
wire pi_dqs_found_err;
wire wrcal_pat_resume;
wire wrcal_resume_w;
wire rdlvl_prech_req;
wire rdlvl_last_byte_done;
wire rdlvl_stg1_start;
wire rdlvl_stg1_rank_done;
wire rdlvl_assrt_common;
wire pi_dqs_found_start;
wire pi_dqs_found_rank_done;
wire wl_sm_start;
wire wrcal_start;
wire wrcal_rd_wait;
wire wrcal_prech_req;
wire wrcal_pat_err;
wire wrcal_done;
wire wrlvl_done;
wire wrlvl_err;
wire wrlvl_start;
wire ck_addr_cmd_delay_done;
wire po_ck_addr_cmd_delay_done;
wire pi_calib_done;
wire detect_pi_found_dqs;
wire [5:0] rd_data_offset_0;
wire [5:0] rd_data_offset_1;
wire [5:0] rd_data_offset_2;
wire [6*RANKS-1:0] rd_data_offset_ranks_0;
wire [6*RANKS-1:0] rd_data_offset_ranks_1;
wire [6*RANKS-1:0] rd_data_offset_ranks_2;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_0;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_1;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_2;
wire cmd_po_stg2_f_incdec;
wire cmd_po_stg2_incdec_ddr2_c;
wire cmd_po_en_stg2_f;
wire cmd_po_en_stg2_ddr2_c;
wire cmd_po_stg2_c_incdec;
wire cmd_po_en_stg2_c;
wire po_stg2_ddr2_incdec;
wire po_en_stg2_ddr2;
wire dqs_po_stg2_f_incdec;
wire dqs_po_en_stg2_f;
wire dqs_wl_po_stg2_c_incdec;
wire wrcal_po_stg2_c_incdec;
wire dqs_wl_po_en_stg2_c;
wire wrcal_po_en_stg2_c;
wire [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [N_CTL_LANES-1:0] ctl_lane_sel;
wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt;
wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt;
wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt;
wire [8:0] dqs_wl_po_stg2_reg_l;
wire dqs_wl_po_stg2_load;
wire [8:0] dqs_po_stg2_reg_l;
wire dqs_po_stg2_load;
wire dqs_po_dec_done;
wire pi_fine_dly_dec_done;
wire rdlvl_pi_stg2_f_incdec;
wire rdlvl_pi_stg2_f_en;
wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt;
reg [DQS_CNT_WIDTH:0] byte_sel_cnt;
wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt;
wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt;
wire phase_locked_err;
wire phy_ctl_rdy_dly;
wire idelay_ce_int;
wire idelay_inc_int;
reg idelay_ce_r1;
reg idelay_ce_r2;
reg idelay_inc_r1;
(* keep = "true", max_fanout = 30 *) reg idelay_inc_r2 /* synthesis syn_maxfan = 30 */;
reg po_dly_req_r;
wire wrcal_read_req;
wire wrcal_act_req;
wire temp_wrcal_done;
wire tg_timer_done;
wire no_rst_tg_mc;
wire calib_complete;
reg reset_if_r1;
reg reset_if_r2;
reg reset_if_r3;
reg reset_if_r4;
reg reset_if_r5;
reg reset_if_r6;
reg reset_if_r7;
reg reset_if_r8;
reg reset_if_r9;
reg reset_if;
wire phy_if_reset_w;
wire pi_phaselock_start;
reg dbg_pi_f_inc_r;
reg dbg_pi_f_en_r;
reg dbg_sel_pi_incdec_r;
reg dbg_po_f_inc_r;
reg dbg_po_f_stg23_sel_r;
reg dbg_po_f_en_r;
reg dbg_sel_po_incdec_r;
reg tempmon_pi_f_inc_r;
reg tempmon_pi_f_en_r;
reg tempmon_sel_pi_incdec_r;
reg ck_addr_cmd_delay_done_r1;
reg ck_addr_cmd_delay_done_r2;
reg ck_addr_cmd_delay_done_r3;
reg ck_addr_cmd_delay_done_r4;
reg ck_addr_cmd_delay_done_r5;
reg ck_addr_cmd_delay_done_r6;
wire oclk_init_delay_start;
wire oclk_prech_req;
wire oclk_calib_resume;
wire oclk_init_delay_done;
wire [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
wire oclkdelay_calib_start;
wire oclkdelay_calib_done;
wire oclkdelay_calib_done_temp;
wire wrlvl_final;
wire wrlvl_final_if_rst;
wire wrlvl_byte_redo;
wire wrlvl_byte_done;
wire early1_data;
wire early2_data;
wire po_stg3_incdec;
wire po_en_stg3;
wire po_stg23_sel;
wire po_stg23_incdec;
wire po_en_stg23;
wire mpr_rdlvl_done;
wire mpr_rdlvl_start;
wire mpr_last_byte_done;
wire mpr_rnk_done;
wire mpr_end_if_reset;
wire mpr_rdlvl_err;
wire rdlvl_err;
wire prbs_rdlvl_start;
wire prbs_rdlvl_done;
reg prbs_rdlvl_done_r1;
wire prbs_last_byte_done;
wire prbs_rdlvl_prech_req;
wire prbs_pi_stg2_f_incdec;
wire prbs_pi_stg2_f_en;
wire [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt;
wire prbs_gen_clk_en;
wire rd_data_offset_cal_done;
wire fine_adjust_done;
wire [N_CTL_LANES-1:0] fine_adjust_lane_cnt;
wire ck_po_stg2_f_indec;
wire ck_po_stg2_f_en;
wire dqs_found_prech_req;
wire tempmon_pi_f_inc;
wire tempmon_pi_f_dec;
wire tempmon_sel_pi_incdec;
wire wrcal_sanity_chk;
wire wrcal_sanity_chk_done;
//*****************************************************************************
// Assertions to check correctness of parameter values
//*****************************************************************************
// synthesis translate_off
initial
begin
if (RANKS == 0) begin
$display ("Error: Invalid RANKS parameter. Must be 1 or greater");
$finish;
end
if (phy_ctl_full == 1'b1) begin
$display ("Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode");
$finish;
end
end
// synthesis translate_on
//***************************************************************************
// Debug
//***************************************************************************
assign dbg_pi_phaselock_start = pi_phaselock_start;
assign dbg_pi_dqsfound_start = pi_dqs_found_start;
assign dbg_pi_dqsfound_done = pi_dqs_found_done;
assign dbg_wrcal_start = wrcal_start;
assign dbg_wrcal_done = wrcal_done;
// Unused for now - use these as needed to bring up lower level signals
assign dbg_calib_top = 256'd0;
// Write Level and write calibration debug observation ports
assign dbg_wrlvl_start = wrlvl_start;
assign dbg_wrlvl_done = wrlvl_done;
assign dbg_wrlvl_err = wrlvl_err;
// Read Level debug observation ports
assign dbg_rdlvl_start = {mpr_rdlvl_start, rdlvl_stg1_start};
assign dbg_rdlvl_done = {mpr_rdlvl_done, rdlvl_stg1_done};
assign dbg_rdlvl_err = {mpr_rdlvl_err, rdlvl_err};
assign dbg_oclkdelay_calib_done = oclkdelay_calib_done;
assign dbg_oclkdelay_calib_start = oclkdelay_calib_start;
//***************************************************************************
// Write leveling dependent signals
//***************************************************************************
assign wrcal_resume_w = (WRLVL == "ON") ? wrcal_pat_resume : 1'b0;
assign wrlvl_done_w = (WRLVL == "ON") ? wrlvl_done : 1'b1;
assign ck_addr_cmd_delay_done = (WRLVL == "ON") ? po_ck_addr_cmd_delay_done :
(po_ck_addr_cmd_delay_done
&& pi_fine_dly_dec_done) ;
generate
genvar i;
for (i = 0; i <= 2; i = i+1) begin : bankwise_signal
assign po_sel_stg2stg3[i] = ((~oclk_init_delay_done && ck_addr_cmd_delay_done &&
(DRAM_TYPE=="DDR3")) ? 1'b1 :
~oclkdelay_calib_done ? po_stg23_sel : 1'b0
) | dbg_po_f_stg23_sel_r;
assign po_stg2_c_incdec[i] = cmd_po_stg2_c_incdec ||
cmd_po_stg2_incdec_ddr2_c ||
dqs_wl_po_stg2_c_incdec;
assign po_en_stg2_c[i] = cmd_po_en_stg2_c ||
cmd_po_en_stg2_ddr2_c ||
dqs_wl_po_en_stg2_c;
assign po_stg2_f_incdec[i] = dqs_po_stg2_f_incdec ||
cmd_po_stg2_f_incdec ||
po_stg3_incdec ||
ck_po_stg2_f_indec ||
po_stg23_incdec ||
dbg_po_f_inc_r;
assign po_en_stg2_f[i] = dqs_po_en_stg2_f ||
cmd_po_en_stg2_f ||
po_en_stg3 ||
ck_po_stg2_f_en ||
po_en_stg23 ||
dbg_po_f_en_r;
end
endgenerate
assign pi_stg2_f_incdec = (dbg_pi_f_inc_r | rdlvl_pi_stg2_f_incdec | prbs_pi_stg2_f_incdec | tempmon_pi_f_inc_r);
assign pi_en_stg2_f = (dbg_pi_f_en_r | rdlvl_pi_stg2_f_en | prbs_pi_stg2_f_en | tempmon_pi_f_en_r);
assign idelay_ce = idelay_ce_r2;
assign idelay_inc = idelay_inc_r2;
assign po_counter_load_en = 1'b0;
// Added single stage flop to meet timing
always @(posedge clk)
init_calib_complete <= calib_complete;
assign calib_rd_data_offset_0 = rd_data_offset_ranks_mc_0;
assign calib_rd_data_offset_1 = rd_data_offset_ranks_mc_1;
assign calib_rd_data_offset_2 = rd_data_offset_ranks_mc_2;
//***************************************************************************
// Hard PHY signals
//***************************************************************************
assign pi_phase_locked_err = phase_locked_err;
assign pi_dqsfound_err = pi_dqs_found_err;
assign wrcal_err = wrcal_pat_err;
assign rst_tg_mc = 1'b0;
always @(posedge clk)
phy_if_reset <= #TCQ (phy_if_reset_w | mpr_end_if_reset |
reset_if | wrlvl_final_if_rst);
//***************************************************************************
// Phaser_IN inc dec control for debug
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
dbg_pi_f_inc_r <= #TCQ 1'b0;
dbg_pi_f_en_r <= #TCQ 1'b0;
dbg_sel_pi_incdec_r <= #TCQ 1'b0;
end else begin
dbg_pi_f_inc_r <= #TCQ dbg_pi_f_inc;
dbg_pi_f_en_r <= #TCQ (dbg_pi_f_inc | dbg_pi_f_dec);
dbg_sel_pi_incdec_r <= #TCQ dbg_sel_pi_incdec;
end
end
//***************************************************************************
// Phaser_OUT inc dec control for debug
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
dbg_po_f_inc_r <= #TCQ 1'b0;
dbg_po_f_stg23_sel_r<= #TCQ 1'b0;
dbg_po_f_en_r <= #TCQ 1'b0;
dbg_sel_po_incdec_r <= #TCQ 1'b0;
end else begin
dbg_po_f_inc_r <= #TCQ dbg_po_f_inc;
dbg_po_f_stg23_sel_r<= #TCQ dbg_po_f_stg23_sel;
dbg_po_f_en_r <= #TCQ (dbg_po_f_inc | dbg_po_f_dec);
dbg_sel_po_incdec_r <= #TCQ dbg_sel_po_incdec;
end
end
//***************************************************************************
// Phaser_IN inc dec control for temperature tracking
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
tempmon_pi_f_inc_r <= #TCQ 1'b0;
tempmon_pi_f_en_r <= #TCQ 1'b0;
tempmon_sel_pi_incdec_r <= #TCQ 1'b0;
end else begin
tempmon_pi_f_inc_r <= #TCQ tempmon_pi_f_inc;
tempmon_pi_f_en_r <= #TCQ (tempmon_pi_f_inc | tempmon_pi_f_dec);
tempmon_sel_pi_incdec_r <= #TCQ tempmon_sel_pi_incdec;
end
end
//***************************************************************************
// OCLKDELAY calibration signals
//***************************************************************************
// Minimum of 5 'clk' cycles required between assertion of po_sel_stg2stg3
// and increment/decrement of Phaser_Out stage 3 delay
always @(posedge clk) begin
ck_addr_cmd_delay_done_r1 <= #TCQ ck_addr_cmd_delay_done;
ck_addr_cmd_delay_done_r2 <= #TCQ ck_addr_cmd_delay_done_r1;
ck_addr_cmd_delay_done_r3 <= #TCQ ck_addr_cmd_delay_done_r2;
ck_addr_cmd_delay_done_r4 <= #TCQ ck_addr_cmd_delay_done_r3;
ck_addr_cmd_delay_done_r5 <= #TCQ ck_addr_cmd_delay_done_r4;
ck_addr_cmd_delay_done_r6 <= #TCQ ck_addr_cmd_delay_done_r5;
end
assign oclk_init_delay_start = ck_addr_cmd_delay_done_r6 && (DRAM_TYPE=="DDR3"); // && (SIM_CAL_OPTION == "NONE")
//***************************************************************************
// MUX select logic to select current byte undergoing calibration
// Use DQS_CAL_MAP to determine the correlation between the physical
// byte numbering, and the byte numbering within the hard PHY
//***************************************************************************
generate
if (tCK > 2500) begin: gen_byte_sel_div2
always @(posedge clk) begin
if (rst) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done) begin
ctl_lane_sel <= #TCQ ctl_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~oclk_init_delay_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_calib_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_dqs_found_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~wrlvl_done_w) begin
if (SIM_CAL_OPTION != "FAST_CAL") begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b0;
end else begin
// Special case for FAST_CAL simulation only to ensure that
// calib_in_common isn't asserted too soon
if (!phy_ctl_rdy_dly) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b1;
end
end
end else if (~mpr_rdlvl_done) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~oclkdelay_calib_done) begin
byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~rdlvl_stg1_done && pi_calib_done) begin
if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~wrcal_done) begin
byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
byte_sel_cnt <= #TCQ dbg_byte_sel;
calib_in_common <= #TCQ 1'b0;
end else if (tempmon_sel_pi_incdec) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end
end
end else begin: gen_byte_sel_div1
always @(posedge clk) begin
if (rst) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done) begin
ctl_lane_sel <= #TCQ ctl_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~oclk_init_delay_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_calib_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_dqs_found_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~wrlvl_done_w) begin
if (SIM_CAL_OPTION != "FAST_CAL") begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b0;
end else begin
// Special case for FAST_CAL simulation only to ensure that
// calib_in_common isn't asserted too soon
if (!phy_ctl_rdy_dly) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b1;
end
end
end else if (~mpr_rdlvl_done) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~oclkdelay_calib_done) begin
byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if ((~wrcal_done)&& (DRAM_TYPE == "DDR3")) begin
byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~rdlvl_stg1_done && pi_calib_done) begin
if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
byte_sel_cnt <= #TCQ dbg_byte_sel;
calib_in_common <= #TCQ 1'b0;
end else if (tempmon_sel_pi_incdec) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end
end
end
endgenerate
always @(posedge clk) begin
if (rst || (calib_complete && ~ (dbg_sel_pi_incdec_r|dbg_sel_po_incdec_r|tempmon_sel_pi_incdec) )) begin
calib_sel <= #TCQ 6'b000100;
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
if (~dqs_po_dec_done && (WRLVL != "ON"))
//if (~dqs_po_dec_done && ((SIM_CAL_OPTION == "FAST_CAL") ||(WRLVL != "ON")))
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
else
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~ck_addr_cmd_delay_done || (~fine_adjust_done && rd_data_offset_cal_done)) begin
if(WRLVL =="ON") begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ CTL_BYTE_LANE[(ctl_lane_sel*2)+:2];
calib_sel[5:3] <= #TCQ CTL_BANK;
if (|pi_rst_stg1_cal) begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
end else begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_inputs[1*CTL_BANK] <= #TCQ 1'b0;
end
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else begin // if (WRLVL =="ON")
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
if(~ck_addr_cmd_delay_done)
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
else
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
end // else: !if(WRLVL =="ON")
end else if (~oclk_init_delay_done) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == "FAST_CAL")) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~rdlvl_stg1_done && (SIM_CAL_OPTION == "FAST_CAL") &&
rdlvl_assrt_common) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (tempmon_sel_pi_incdec) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
if (~calib_in_common) begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0;
end else
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
end
end
// Logic to reset IN_FIFO flags to account for the possibility that
// one or more PHASER_IN's have not correctly found the DQS preamble
// If this happens, we can still complete read leveling, but the # of
// words written into the IN_FIFO's may be an odd #, so that if the
// IN_FIFO is used in 2:1 mode ("8:4 mode"), there may be a "half" word
// of data left that can only be flushed out by reseting the IN_FIFO
always @(posedge clk) begin
rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done;
prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done;
reset_if_r1 <= #TCQ reset_if;
reset_if_r2 <= #TCQ reset_if_r1;
reset_if_r3 <= #TCQ reset_if_r2;
reset_if_r4 <= #TCQ reset_if_r3;
reset_if_r5 <= #TCQ reset_if_r4;
reset_if_r6 <= #TCQ reset_if_r5;
reset_if_r7 <= #TCQ reset_if_r6;
reset_if_r8 <= #TCQ reset_if_r7;
reset_if_r9 <= #TCQ reset_if_r8;
end
always @(posedge clk) begin
if (rst || reset_if_r9)
reset_if <= #TCQ 1'b0;
else if ((rdlvl_stg1_done && ~rdlvl_stg1_done_r1) ||
(prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
reset_if <= #TCQ 1'b1;
end
assign phy_if_empty_def = 1'b0;
// DQ IDELAY tap inc and ce signals registered to control calib_in_common
// signal during read leveling in FAST_CAL mode. The calib_in_common signal
// is only asserted for IDELAY tap increments not Phaser_IN tap increments
// in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load
// inputs are used.
always @(posedge clk) begin
if (rst) begin
idelay_ce_r1 <= #TCQ 1'b0;
idelay_ce_r2 <= #TCQ 1'b0;
idelay_inc_r1 <= #TCQ 1'b0;
idelay_inc_r2 <= #TCQ 1'b0;
end else begin
idelay_ce_r1 <= #TCQ idelay_ce_int;
idelay_ce_r2 <= #TCQ idelay_ce_r1;
idelay_inc_r1 <= #TCQ idelay_inc_int;
idelay_inc_r2 <= #TCQ idelay_inc_r1;
end
end
//***************************************************************************
// Delay all Outputs using Phaser_Out fine taps
//***************************************************************************
assign init_wrcal_complete = 1'b0;
//***************************************************************************
// PRBS Generator for Read Leveling Stage 1 - read window detection and
// DQS Centering
//***************************************************************************
// Assign initial seed (used for 1st data word in 8-burst sequence); use alternating 1/0 pat
assign prbs_seed = 64'h9966aa559966aa55;
// A single PRBS generator
// writes 64-bits every 4to1 fabric clock cycle and
// write 32-bits every 2to1 fabric clock cycle
mig_7series_v1_9_ddr_prbs_gen #
(
.TCQ (TCQ),
.PRBS_WIDTH (2*8*nCK_PER_CLK)
)
u_ddr_prbs_gen
(
.clk_i (clk),
.clk_en_i (prbs_gen_clk_en),
.rst_i (rst),
.prbs_o (prbs_out),
.prbs_seed_i (prbs_seed),
.phy_if_empty (phy_if_empty),
.prbs_rdlvl_start (prbs_rdlvl_start)
);
// PRBS data slice that decides the Rise0, Fall0, Rise1, Fall1,
// Rise2, Fall2, Rise3, Fall3 data
generate
if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
assign prbs_rise0 = prbs_out[7:0];
assign prbs_fall0 = prbs_out[15:8];
assign prbs_rise1 = prbs_out[23:16];
assign prbs_fall1 = prbs_out[31:24];
assign prbs_rise2 = prbs_out[39:32];
assign prbs_fall2 = prbs_out[47:40];
assign prbs_rise3 = prbs_out[55:48];
assign prbs_fall3 = prbs_out[63:56];
assign prbs_o = {prbs_fall3, prbs_rise3, prbs_fall2, prbs_rise2,
prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};
end else begin :gen_ck_per_clk2
assign prbs_rise0 = prbs_out[7:0];
assign prbs_fall0 = prbs_out[15:8];
assign prbs_rise1 = prbs_out[23:16];
assign prbs_fall1 = prbs_out[31:24];
assign prbs_o = {prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};
end
endgenerate
//***************************************************************************
// Initialization / Master PHY state logic (overall control during memory
// init, timing leveling)
//***************************************************************************
mig_7series_v1_9_ddr_phy_init #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DRAM_TYPE (DRAM_TYPE),
.PRBS_WIDTH (PRBS_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.CA_MIRROR (CA_MIRROR),
.COL_WIDTH (COL_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.CS_WIDTH (CS_WIDTH),
.RANKS (RANKS),
.CKE_WIDTH (CKE_WIDTH),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.AL (AL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.nCL (nCL),
.nCWL (nCWL),
.tRFC (tRFC),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.WRLVL (WRLVL),
.USE_ODT_PORT (USE_ODT_PORT),
.DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE),
.nSLOTS (nSLOTS),
.SIM_INIT_OPTION (SIM_INIT_OPTION),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.CKE_ODT_AUX (CKE_ODT_AUX),
.PRE_REV3ES (PRE_REV3ES),
.TEST_AL (TEST_AL)
)
u_ddr_phy_init
(
.clk (clk),
.rst (rst),
.prbs_o (prbs_o),
.ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
.delay_incdec_done (ck_addr_cmd_delay_done & oclk_init_delay_done),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_phaselock_start (pi_phaselock_start),
.pi_phase_locked_err (phase_locked_err),
.pi_calib_done (pi_calib_done),
.phy_if_empty (phy_if_empty),
.phy_ctl_ready (phy_ctl_ready),
.phy_ctl_full (phy_ctl_full),
.phy_cmd_full (phy_cmd_full),
.phy_data_full (phy_data_full),
.calib_ctl_wren (calib_ctl_wren),
.calib_cmd_wren (calib_cmd_wren),
.calib_wrdata_en (calib_wrdata_en),
.calib_seq (calib_seq),
.calib_aux_out (calib_aux_out),
.calib_rank_cnt (calib_rank_cnt),
.calib_cas_slot (calib_cas_slot),
.calib_data_offset_0 (calib_data_offset_0),
.calib_data_offset_1 (calib_data_offset_1),
.calib_data_offset_2 (calib_data_offset_2),
.calib_cmd (calib_cmd),
.calib_cke (calib_cke),
.calib_odt (calib_odt),
.write_calib (write_calib),
.read_calib (read_calib),
.wrlvl_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.wrlvl_byte_done (wrlvl_byte_done),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrlvl_final (wrlvl_final),
.wrlvl_final_if_rst (wrlvl_final_if_rst),
.oclkdelay_calib_start (oclkdelay_calib_start),
.oclkdelay_calib_done (oclkdelay_calib_done),
.oclk_prech_req (oclk_prech_req),
.oclk_calib_resume (oclk_calib_resume),
.done_dqs_tap_inc (done_dqs_tap_inc),
.wl_sm_start (wl_sm_start),
.wr_lvl_start (wrlvl_start),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
.mpr_rdlvl_done (mpr_rdlvl_done),
.mpr_rdlvl_start (mpr_rdlvl_start),
.mpr_last_byte_done (mpr_last_byte_done),
.mpr_rnk_done (mpr_rnk_done),
.mpr_end_if_reset (mpr_end_if_reset),
.rdlvl_stg1_done (rdlvl_stg1_done),
.rdlvl_stg1_rank_done (rdlvl_stg1_rank_done),
.rdlvl_stg1_start (rdlvl_stg1_start),
.rdlvl_prech_req (rdlvl_prech_req),
.rdlvl_last_byte_done (rdlvl_last_byte_done),
.prbs_rdlvl_start (prbs_rdlvl_start),
.prbs_rdlvl_done (prbs_rdlvl_done),
.prbs_last_byte_done (prbs_last_byte_done),
.prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
.prbs_gen_clk_en (prbs_gen_clk_en),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_rank_done(pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.detect_pi_found_dqs (detect_pi_found_dqs),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.rd_data_offset_ranks_0(rd_data_offset_ranks_0),
.rd_data_offset_ranks_1(rd_data_offset_ranks_1),
.rd_data_offset_ranks_2(rd_data_offset_ranks_2),
.wrcal_start (wrcal_start),
.wrcal_rd_wait (wrcal_rd_wait),
.wrcal_prech_req (wrcal_prech_req),
.wrcal_resume (wrcal_resume_w),
.wrcal_read_req (wrcal_read_req),
.wrcal_act_req (wrcal_act_req),
.wrcal_sanity_chk (wrcal_sanity_chk),
.temp_wrcal_done (temp_wrcal_done),
.wrcal_sanity_chk_done (wrcal_sanity_chk_done),
.tg_timer_done (tg_timer_done),
.no_rst_tg_mc (no_rst_tg_mc),
.wrcal_done (wrcal_done),
.prech_done (prech_done),
.calib_writes (calib_writes),
.init_calib_complete (calib_complete),
.phy_address (phy_address),
.phy_bank (phy_bank),
.phy_cas_n (phy_cas_n),
.phy_cs_n (phy_cs_n),
.phy_ras_n (phy_ras_n),
.phy_reset_n (phy_reset_n),
.phy_we_n (phy_we_n),
.phy_wrdata (phy_wrdata),
.phy_rddata_en (phy_rddata_en),
.phy_rddata_valid (phy_rddata_valid),
.dbg_phy_init (dbg_phy_init)
);
//*****************************************************************
// Write Calibration
//*****************************************************************
mig_7series_v1_9_ddr_phy_wrcal #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.SIM_CAL_OPTION (SIM_CAL_OPTION)
)
u_ddr_phy_wrcal
(
.clk (clk),
.rst (rst),
.wrcal_start (wrcal_start),
.wrcal_rd_wait (wrcal_rd_wait),
.wrcal_sanity_chk (wrcal_sanity_chk),
.dqsfound_retry_done (pi_dqs_found_done),
.dqsfound_retry (dqsfound_retry),
.wrcal_read_req (wrcal_read_req),
.wrcal_act_req (wrcal_act_req),
.phy_rddata_en (phy_rddata_en),
.wrcal_done (wrcal_done),
.wrcal_pat_err (wrcal_pat_err),
.wrcal_prech_req (wrcal_prech_req),
.temp_wrcal_done (temp_wrcal_done),
.wrcal_sanity_chk_done (wrcal_sanity_chk_done),
.prech_done (prech_done),
.rd_data (phy_rddata),
.wrcal_pat_resume (wrcal_pat_resume),
.po_stg2_wrcal_cnt (po_stg2_wrcal_cnt),
.phy_if_reset (phy_if_reset_w),
.wl_po_coarse_cnt (wl_po_coarse_cnt),
.wl_po_fine_cnt (wl_po_fine_cnt),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrlvl_byte_done (wrlvl_byte_done),
.early1_data (early1_data),
.early2_data (early2_data),
.idelay_ld (idelay_ld),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt)
);
//***************************************************************************
// Write-leveling calibration logic
//***************************************************************************
generate
if (WRLVL == "ON") begin: mb_wrlvl_inst
mig_7series_v1_9_ddr_phy_wrlvl #
(
.TCQ (TCQ),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.CLK_PERIOD (CLK_PERIOD),
.nCK_PER_CLK (nCK_PER_CLK),
.SIM_CAL_OPTION (SIM_CAL_OPTION)
)
u_ddr_phy_wrlvl
(
.clk (clk),
.rst (rst),
.phy_ctl_ready (phy_ctl_ready),
.wr_level_start (wrlvl_start),
.wl_sm_start (wl_sm_start),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrcal_cnt (po_stg2_wrcal_cnt),
.early1_data (early1_data),
.early2_data (early2_data),
.wrlvl_final (wrlvl_final),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt),
.wrlvl_byte_done (wrlvl_byte_done),
.oclkdelay_calib_done (oclkdelay_calib_done),
.rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]),
.dqs_po_dec_done (dqs_po_dec_done),
.phy_ctl_rdy_dly (phy_ctl_rdy_dly),
.wr_level_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.done_dqs_tap_inc (done_dqs_tap_inc),
.dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec),
.dqs_po_en_stg2_f (dqs_po_en_stg2_f),
.dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec),
.dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c),
.po_counter_read_val (po_counter_read_val),
.po_stg2_wl_cnt (po_stg2_wl_cnt),
.wrlvl_err (wrlvl_err),
.wl_po_coarse_cnt (wl_po_coarse_cnt),
.wl_po_fine_cnt (wl_po_fine_cnt),
.dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_dqs_count (),
.dbg_wl_state (),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl)
);
mig_7series_v1_9_ddr_phy_ck_addr_cmd_delay #
(
.TCQ (TCQ),
.tCK (tCK),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.N_CTL_LANES (N_CTL_LANES),
.SIM_CAL_OPTION(SIM_CAL_OPTION)
)
u_ddr_phy_ck_addr_cmd_delay
(
.clk (clk),
.rst (rst),
.cmd_delay_start (dqs_po_dec_done & pi_fine_dly_dec_done),
.ctl_lane_cnt (ctl_lane_cnt),
.po_stg2_f_incdec (cmd_po_stg2_f_incdec),
.po_en_stg2_f (cmd_po_en_stg2_f),
.po_stg2_c_incdec (cmd_po_stg2_c_incdec),
.po_en_stg2_c (cmd_po_en_stg2_c),
.po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done)
);
assign cmd_po_stg2_incdec_ddr2_c = 1'b0;
assign cmd_po_en_stg2_ddr2_c = 1'b0;
end else begin: mb_wrlvl_off
mig_7series_v1_9_ddr_phy_wrlvl_off_delay #
(
.TCQ (TCQ),
.tCK (tCK),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.PO_INITIAL_DLY(60),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.N_CTL_LANES (N_CTL_LANES)
)
u_phy_wrlvl_off_delay
(
.clk (clk),
.rst (rst),
.pi_fine_dly_dec_done (pi_fine_dly_dec_done),
.cmd_delay_start (phy_ctl_ready),
.ctl_lane_cnt (ctl_lane_cnt),
.po_s2_incdec_f (cmd_po_stg2_f_incdec),
.po_en_s2_f (cmd_po_en_stg2_f),
.po_s2_incdec_c (cmd_po_stg2_incdec_ddr2_c),
.po_en_s2_c (cmd_po_en_stg2_ddr2_c),
.po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done),
.po_dec_done (dqs_po_dec_done),
.phy_ctl_rdy_dly (phy_ctl_rdy_dly)
);
assign wrlvl_done = 1'b1;
assign wrlvl_err = 1'b0;
assign dqs_po_stg2_f_incdec = 1'b0;
assign dqs_po_en_stg2_f = 1'b0;
assign dqs_wl_po_en_stg2_c = 1'b0;
assign cmd_po_stg2_c_incdec = 1'b0;
assign dqs_wl_po_stg2_c_incdec = 1'b0;
assign cmd_po_en_stg2_c = 1'b0;
end
endgenerate
generate
if(WRLVL == "ON") begin: oclk_calib
mig_7series_v1_9_ddr_phy_oclkdelay_cal #
(
.TCQ (TCQ),
.tCK (tCK),
.nCK_PER_CLK (nCK_PER_CLK),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.OCAL_EN (OCAL_EN)
)
u_ddr_phy_oclkdelay_cal
(
.clk (clk),
.rst (rst),
.oclk_init_delay_start (oclk_init_delay_start),
.oclkdelay_calib_start (oclkdelay_calib_start),
.oclkdelay_init_val (oclkdelay_init_val),
.phy_rddata_en (phy_rddata_en),
.rd_data (phy_rddata),
.prech_done (prech_done),
.wl_po_fine_cnt (wl_po_fine_cnt),
.po_stg3_incdec (po_stg3_incdec),
.po_en_stg3 (po_en_stg3),
.po_stg23_sel (po_stg23_sel),
.po_stg23_incdec (po_stg23_incdec),
.po_en_stg23 (po_en_stg23),
.wrlvl_final (wrlvl_final),
.oclk_prech_req (oclk_prech_req),
.oclk_calib_resume (oclk_calib_resume),
.oclk_init_delay_done (oclk_init_delay_done),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt),
.oclkdelay_calib_done (oclkdelay_calib_done),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data)
);
end else begin : oclk_calib_disabled
assign wrlvl_final = 'b0;
assign po_stg3_incdec = 'b0;
assign po_en_stg3 = 'b0;
assign po_stg23_sel = 'b0;
assign po_stg23_incdec = 'b0;
assign po_en_stg23 = 'b0;
assign oclk_init_delay_done = 1'b1;
assign oclkdelay_calib_cnt = 'b0;
assign oclk_prech_req = 'b0;
assign oclk_calib_resume = 'b0;
assign oclkdelay_calib_done = 1'b1;
end
endgenerate
//***************************************************************************
// Read data-offset calibration required for Phaser_In
//***************************************************************************
generate
if(DQSFOUND_CAL == "RIGHT") begin: dqsfind_calib_right
mig_7series_v1_9_ddr_phy_dqs_found_cal #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.nCL (nCL),
.AL (AL),
.nCWL (nCWL),
//.RANKS (RANKS),
.RANKS (1),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.REG_CTRL (REG_CTRL),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DRAM_TYPE (DRAM_TYPE),
.NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
.N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
.HIGHEST_LANE (HIGHEST_LANE),
.HIGHEST_BANK (HIGHEST_BANK),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4)
)
u_ddr_phy_dqs_found_cal
(
.clk (clk),
.rst (rst),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.detect_pi_found_dqs (detect_pi_found_dqs),
.prech_done (prech_done),
.pi_dqs_found_lanes (pi_dqs_found_lanes),
.pi_rst_stg1_cal (pi_rst_stg1_cal),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.pi_dqs_found_rank_done (pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.dqsfound_retry_done (dqsfound_retry_done),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_err (pi_dqs_found_err),
.rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
.rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
.rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
.rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
.rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
.rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
.po_counter_read_val (po_counter_read_val),
.rd_data_offset_cal_done (rd_data_offset_cal_done),
.fine_adjust_done (fine_adjust_done),
.fine_adjust_lane_cnt (fine_adjust_lane_cnt),
.ck_po_stg2_f_indec (ck_po_stg2_f_indec),
.ck_po_stg2_f_en (ck_po_stg2_f_en),
.dbg_dqs_found_cal (dbg_dqs_found_cal)
);
end else begin: dqsfind_calib_left
mig_7series_v1_9_ddr_phy_dqs_found_cal_hr #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.nCL (nCL),
.AL (AL),
.nCWL (nCWL),
//.RANKS (RANKS),
.RANKS (1),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.REG_CTRL (REG_CTRL),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DRAM_TYPE (DRAM_TYPE),
.NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
.N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
.HIGHEST_LANE (HIGHEST_LANE),
.HIGHEST_BANK (HIGHEST_BANK),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4)
)
u_ddr_phy_dqs_found_cal_hr
(
.clk (clk),
.rst (rst),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.detect_pi_found_dqs (detect_pi_found_dqs),
.prech_done (prech_done),
.pi_dqs_found_lanes (pi_dqs_found_lanes),
.pi_rst_stg1_cal (pi_rst_stg1_cal),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.pi_dqs_found_rank_done (pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.dqsfound_retry_done (dqsfound_retry_done),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_err (pi_dqs_found_err),
.rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
.rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
.rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
.rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
.rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
.rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
.po_counter_read_val (po_counter_read_val),
.rd_data_offset_cal_done (rd_data_offset_cal_done),
.fine_adjust_done (fine_adjust_done),
.fine_adjust_lane_cnt (fine_adjust_lane_cnt),
.ck_po_stg2_f_indec (ck_po_stg2_f_indec),
.ck_po_stg2_f_en (ck_po_stg2_f_en),
.dbg_dqs_found_cal (dbg_dqs_found_cal)
);
end
endgenerate
//***************************************************************************
// Read-leveling calibration logic
//***************************************************************************
mig_7series_v1_9_ddr_phy_rdlvl #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.PER_BIT_DESKEW (PER_BIT_DESKEW),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DEBUG_PORT (DEBUG_PORT),
.DRAM_TYPE (DRAM_TYPE),
.OCAL_EN (OCAL_EN)
)
u_ddr_phy_rdlvl
(
.clk (clk),
.rst (rst),
.mpr_rdlvl_done (mpr_rdlvl_done),
.mpr_rdlvl_start (mpr_rdlvl_start),
.mpr_last_byte_done (mpr_last_byte_done),
.mpr_rnk_done (mpr_rnk_done),
.rdlvl_stg1_start (rdlvl_stg1_start),
.rdlvl_stg1_done (rdlvl_stg1_done),
.rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done),
.rdlvl_stg1_err (rdlvl_stg1_err),
.mpr_rdlvl_err (mpr_rdlvl_err),
.rdlvl_err (rdlvl_err),
.rdlvl_prech_req (rdlvl_prech_req),
.rdlvl_last_byte_done (rdlvl_last_byte_done),
.rdlvl_assrt_common (rdlvl_assrt_common),
.prech_done (prech_done),
.phy_if_empty (phy_if_empty),
.idelaye2_init_val (idelaye2_init_val),
.rd_data (phy_rddata),
.pi_en_stg2_f (rdlvl_pi_stg2_f_en),
.pi_stg2_f_incdec (rdlvl_pi_stg2_f_incdec),
.pi_stg2_load (pi_stg2_load),
.pi_stg2_reg_l (pi_stg2_reg_l),
.dqs_po_dec_done (dqs_po_dec_done),
.pi_counter_read_val (pi_counter_read_val),
.pi_fine_dly_dec_done (pi_fine_dly_dec_done),
.idelay_ce (idelay_ce_int),
.idelay_inc (idelay_inc_int),
.idelay_ld (idelay_ld),
.wrcal_cnt (po_stg2_wrcal_cnt),
.pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt),
.dlyval_dq (dlyval_dq),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_phy_rdlvl (dbg_phy_rdlvl)
);
generate
if(DRAM_TYPE == "DDR3") begin:ddr_phy_prbs_rdlvl_gen
mig_7series_v1_9_ddr_phy_prbs_rdlvl #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.PRBS_WIDTH (PRBS_WIDTH)
)
u_ddr_phy_prbs_rdlvl
(
.clk (clk),
.rst (rst),
.prbs_rdlvl_start (prbs_rdlvl_start),
.prbs_rdlvl_done (prbs_rdlvl_done),
.prbs_last_byte_done (prbs_last_byte_done),
.prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
.prech_done (prech_done),
.phy_if_empty (phy_if_empty),
.rd_data (phy_rddata),
.compare_data (prbs_o),
.pi_counter_read_val (pi_counter_read_val),
.pi_en_stg2_f (prbs_pi_stg2_f_en),
.pi_stg2_f_incdec (prbs_pi_stg2_f_incdec),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.pi_stg2_prbs_rdlvl_cnt (pi_stg2_prbs_rdlvl_cnt)
);
end else begin:ddr_phy_prbs_rdlvl_off
assign prbs_rdlvl_done = rdlvl_stg1_done ;
assign prbs_last_byte_done = rdlvl_stg1_rank_done ;
assign prbs_rdlvl_prech_req = 1'b0 ;
assign prbs_pi_stg2_f_en = 1'b0 ;
assign prbs_pi_stg2_f_incdec = 1'b0 ;
assign pi_stg2_prbs_rdlvl_cnt = 'b0 ;
end
endgenerate
//***************************************************************************
// Temperature induced PI tap adjustment logic
//***************************************************************************
mig_7series_v1_9_ddr_phy_tempmon #
(
.TCQ (TCQ)
)
ddr_phy_tempmon_0
(
.rst (rst),
.clk (clk),
.calib_complete (calib_complete),
.tempmon_pi_f_inc (tempmon_pi_f_inc),
.tempmon_pi_f_dec (tempmon_pi_f_dec),
.tempmon_sel_pi_incdec (tempmon_sel_pi_incdec),
.device_temp (device_temp),
.tempmon_sample_en (tempmon_sample_en)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_calib_top.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:06 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
//Purpose:
// Top-level for memory physical layer (PHY) interface
// NOTES:
// 1. Need to support multiple copies of CS outputs
// 2. DFI_DRAM_CKE_DISABLE not supported
//
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $
**$Date: 2011/06/02 08:35:06 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_calib_top #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter tCK = 2500, // DDR3 SDRAM clock period
parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter PRBS_WIDTH = 8, // The PRBS sequence is 2^PRBS_WIDTH
parameter HIGHEST_LANE = 4,
parameter HIGHEST_BANK = 3,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
// five fields, one per possible I/O bank, 4 bits in each field,
// 1 per lane data=1/ctl=0
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
// defines the byte lanes in I/O banks being used in the interface
// 1- Used, 0- Unused
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter CTL_BYTE_LANE = 8'hE4, // Control byte lane map
parameter CTL_BANK = 3'b000, // Bank used for control byte lanes
// Slot Conifg parameters
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
// DRAM bus widths
parameter BANK_WIDTH = 2, // # of bank bits
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter COL_WIDTH = 10, // column address width
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ROW_WIDTH = 14, // DRAM address bus width
parameter RANKS = 1, // # of memory ranks in the interface
parameter CS_WIDTH = 1, // # of CS# signals in the interface
parameter CKE_WIDTH = 1, // # of cke outputs
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter PER_BIT_DESKEW = "ON",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter NUM_DQSFOUND_CAL = 1020, // # of iteration of DQSFOUND calib
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// DRAM mode settings
parameter AL = "0", // Additive Latency option
parameter TEST_AL = "0", // Additive Latency for internal use
parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T"
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter nCL = 5, // Read CAS latency (in clk cyc)
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter tRFC = 110000, // Refresh-to-command delay
parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RTT_NOM = "60", // ODT Nominal termination value
parameter RTT_WR = "60", // ODT Write termination value
parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA
// 1 - ODT output from FPGA
parameter WRLVL = "OFF", // Enable write leveling
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
// Simulation /debug options
parameter SIM_INIT_OPTION = "NONE", // Performs all initialization steps
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter CKE_ODT_AUX = "FALSE",
parameter DEBUG_PORT = "OFF" // Enable debug port
)
(
input clk, // Internal (logic) clock
input rst, // Reset sync'ed to CLK
// Slot present inputs
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// Hard PHY signals
// From PHY Ctrl Block
input phy_ctl_ready,
input phy_ctl_full,
input phy_cmd_full,
input phy_data_full,
// To PHY Ctrl Block
output write_calib,
output read_calib,
output calib_ctl_wren,
output calib_cmd_wren,
output [1:0] calib_seq,
output [3:0] calib_aux_out,
output [nCK_PER_CLK -1:0] calib_cke,
output [1:0] calib_odt,
output [2:0] calib_cmd,
output calib_wrdata_en,
output [1:0] calib_rank_cnt,
output [1:0] calib_cas_slot,
output [5:0] calib_data_offset_0,
output [5:0] calib_data_offset_1,
output [5:0] calib_data_offset_2,
output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,
output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,
output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,
output [nCK_PER_CLK-1:0] phy_ras_n,
output [nCK_PER_CLK-1:0] phy_cas_n,
output [nCK_PER_CLK-1:0] phy_we_n,
output phy_reset_n,
// To hard PHY wrapper
(* keep = "true", max_fanout = 10 *) output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 */,
(* keep = "true", max_fanout = 10 *) output reg calib_in_common/* synthesis syn_maxfan = 10 */,
(* keep = "true", max_fanout = 10 *) output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 */,
output reg [HIGHEST_BANK-1:0] calib_zero_ctrl,
output phy_if_empty_def,
output reg phy_if_reset,
// output reg ck_addr_ctl_delay_done,
// From DQS Phaser_In
input pi_phaselocked,
input pi_phase_locked_all,
input pi_found_dqs,
input pi_dqs_found_all,
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
input [5:0] pi_counter_read_val,
// To DQS Phaser_In
output [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
output pi_en_stg2_f,
output pi_stg2_f_incdec,
output pi_stg2_load,
output [5:0] pi_stg2_reg_l,
// To DQ IDELAY
output idelay_ce,
output idelay_inc,
output idelay_ld,
// To DQS Phaser_Out
(* keep = "true", max_fanout = 3 *) output [2:0] po_sel_stg2stg3 /* synthesis syn_maxfan = 3 */,
(* keep = "true", max_fanout = 3 *) output [2:0] po_stg2_c_incdec /* synthesis syn_maxfan = 3 */,
(* keep = "true", max_fanout = 3 *) output [2:0] po_en_stg2_c /* synthesis syn_maxfan = 3 */,
(* keep = "true", max_fanout = 3 *) output [2:0] po_stg2_f_incdec /* synthesis syn_maxfan = 3 */,
(* keep = "true", max_fanout = 3 *) output [2:0] po_en_stg2_f /* synthesis syn_maxfan = 3 */,
output po_counter_load_en,
input [8:0] po_counter_read_val,
// To command Phaser_Out
input phy_if_empty,
input [4:0] idelaye2_init_val,
input [5:0] oclkdelay_init_val,
input tg_err,
output rst_tg_mc,
// Write data to OUT_FIFO
output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata,
// To CNTVALUEIN input of DQ IDELAYs for perbit de-skew
output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,
// IN_FIFO read enable during write leveling, write calibration,
// and read leveling
// Read data from hard PHY fans out to mc and calib logic
input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata,
// To MC
output [6*RANKS-1:0] calib_rd_data_offset_0,
output [6*RANKS-1:0] calib_rd_data_offset_1,
output [6*RANKS-1:0] calib_rd_data_offset_2,
output phy_rddata_valid,
output calib_writes,
(* keep = "true", max_fanout = 10 *) output reg init_calib_complete/* synthesis syn_maxfan = 10 */,
output init_wrcal_complete,
output pi_phase_locked_err,
output pi_dqsfound_err,
output wrcal_err,
// Debug Port
output dbg_pi_phaselock_start,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrlvl_start,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output [255:0] dbg_phy_wrlvl,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
// Write Calibration Logic
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [99:0] dbg_phy_wrcal,
// Read leveling logic
output [1:0] dbg_rdlvl_start,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
// Delay control
input [11:0] device_temp,
input tempmon_sample_en,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_cpt,
input dbg_idel_down_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input dbg_sel_all_idel_cpt,
output [255:0] dbg_phy_rdlvl, // Read leveling calibration
output [255:0] dbg_calib_top, // General PHY debug
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal
);
// Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center
// align DQ and DQS on writes. Round (up or down) value to nearest integer
// localparam integer SHIFT_TBY4_TAP
// = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) /
// (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4);
// Calculate number of slots in the system
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
localparam OCAL_EN = ((SIM_CAL_OPTION == "FAST_CAL") || (tCK > 2500)) ? "OFF" : "ON";
// Different CTL_LANES value for DDR2. In DDR2 during DQS found all
// the add,ctl & data phaser out fine delays will be adjusted.
// In DDR3 only the add/ctrl lane delays will be adjusted
localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == "DDR3") ? N_CTL_LANES : 1;
localparam DQSFOUND_CAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && tCK > 2500)) ? "LEFT" : "RIGHT"; // IO Bank used for Memory I/F: "LEFT", "RIGHT"
wire [2*8*nCK_PER_CLK-1:0] prbs_seed;
wire [2*8*nCK_PER_CLK-1:0] prbs_out;
wire [7:0] prbs_rise0;
wire [7:0] prbs_fall0;
wire [7:0] prbs_rise1;
wire [7:0] prbs_fall1;
wire [7:0] prbs_rise2;
wire [7:0] prbs_fall2;
wire [7:0] prbs_rise3;
wire [7:0] prbs_fall3;
wire [2*8*nCK_PER_CLK-1:0] prbs_o;
wire dqsfound_retry;
wire dqsfound_retry_done;
wire phy_rddata_en;
wire prech_done;
wire rdlvl_stg1_done;
reg rdlvl_stg1_done_r1;
wire pi_dqs_found_done;
wire rdlvl_stg1_err;
wire pi_dqs_found_err;
wire wrcal_pat_resume;
wire wrcal_resume_w;
wire rdlvl_prech_req;
wire rdlvl_last_byte_done;
wire rdlvl_stg1_start;
wire rdlvl_stg1_rank_done;
wire rdlvl_assrt_common;
wire pi_dqs_found_start;
wire pi_dqs_found_rank_done;
wire wl_sm_start;
wire wrcal_start;
wire wrcal_rd_wait;
wire wrcal_prech_req;
wire wrcal_pat_err;
wire wrcal_done;
wire wrlvl_done;
wire wrlvl_err;
wire wrlvl_start;
wire ck_addr_cmd_delay_done;
wire po_ck_addr_cmd_delay_done;
wire pi_calib_done;
wire detect_pi_found_dqs;
wire [5:0] rd_data_offset_0;
wire [5:0] rd_data_offset_1;
wire [5:0] rd_data_offset_2;
wire [6*RANKS-1:0] rd_data_offset_ranks_0;
wire [6*RANKS-1:0] rd_data_offset_ranks_1;
wire [6*RANKS-1:0] rd_data_offset_ranks_2;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_0;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_1;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_2;
wire cmd_po_stg2_f_incdec;
wire cmd_po_stg2_incdec_ddr2_c;
wire cmd_po_en_stg2_f;
wire cmd_po_en_stg2_ddr2_c;
wire cmd_po_stg2_c_incdec;
wire cmd_po_en_stg2_c;
wire po_stg2_ddr2_incdec;
wire po_en_stg2_ddr2;
wire dqs_po_stg2_f_incdec;
wire dqs_po_en_stg2_f;
wire dqs_wl_po_stg2_c_incdec;
wire wrcal_po_stg2_c_incdec;
wire dqs_wl_po_en_stg2_c;
wire wrcal_po_en_stg2_c;
wire [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [N_CTL_LANES-1:0] ctl_lane_sel;
wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt;
wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt;
wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt;
wire [8:0] dqs_wl_po_stg2_reg_l;
wire dqs_wl_po_stg2_load;
wire [8:0] dqs_po_stg2_reg_l;
wire dqs_po_stg2_load;
wire dqs_po_dec_done;
wire pi_fine_dly_dec_done;
wire rdlvl_pi_stg2_f_incdec;
wire rdlvl_pi_stg2_f_en;
wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt;
reg [DQS_CNT_WIDTH:0] byte_sel_cnt;
wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt;
wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt;
wire phase_locked_err;
wire phy_ctl_rdy_dly;
wire idelay_ce_int;
wire idelay_inc_int;
reg idelay_ce_r1;
reg idelay_ce_r2;
reg idelay_inc_r1;
(* keep = "true", max_fanout = 30 *) reg idelay_inc_r2 /* synthesis syn_maxfan = 30 */;
reg po_dly_req_r;
wire wrcal_read_req;
wire wrcal_act_req;
wire temp_wrcal_done;
wire tg_timer_done;
wire no_rst_tg_mc;
wire calib_complete;
reg reset_if_r1;
reg reset_if_r2;
reg reset_if_r3;
reg reset_if_r4;
reg reset_if_r5;
reg reset_if_r6;
reg reset_if_r7;
reg reset_if_r8;
reg reset_if_r9;
reg reset_if;
wire phy_if_reset_w;
wire pi_phaselock_start;
reg dbg_pi_f_inc_r;
reg dbg_pi_f_en_r;
reg dbg_sel_pi_incdec_r;
reg dbg_po_f_inc_r;
reg dbg_po_f_stg23_sel_r;
reg dbg_po_f_en_r;
reg dbg_sel_po_incdec_r;
reg tempmon_pi_f_inc_r;
reg tempmon_pi_f_en_r;
reg tempmon_sel_pi_incdec_r;
reg ck_addr_cmd_delay_done_r1;
reg ck_addr_cmd_delay_done_r2;
reg ck_addr_cmd_delay_done_r3;
reg ck_addr_cmd_delay_done_r4;
reg ck_addr_cmd_delay_done_r5;
reg ck_addr_cmd_delay_done_r6;
wire oclk_init_delay_start;
wire oclk_prech_req;
wire oclk_calib_resume;
wire oclk_init_delay_done;
wire [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
wire oclkdelay_calib_start;
wire oclkdelay_calib_done;
wire oclkdelay_calib_done_temp;
wire wrlvl_final;
wire wrlvl_final_if_rst;
wire wrlvl_byte_redo;
wire wrlvl_byte_done;
wire early1_data;
wire early2_data;
wire po_stg3_incdec;
wire po_en_stg3;
wire po_stg23_sel;
wire po_stg23_incdec;
wire po_en_stg23;
wire mpr_rdlvl_done;
wire mpr_rdlvl_start;
wire mpr_last_byte_done;
wire mpr_rnk_done;
wire mpr_end_if_reset;
wire mpr_rdlvl_err;
wire rdlvl_err;
wire prbs_rdlvl_start;
wire prbs_rdlvl_done;
reg prbs_rdlvl_done_r1;
wire prbs_last_byte_done;
wire prbs_rdlvl_prech_req;
wire prbs_pi_stg2_f_incdec;
wire prbs_pi_stg2_f_en;
wire [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt;
wire prbs_gen_clk_en;
wire rd_data_offset_cal_done;
wire fine_adjust_done;
wire [N_CTL_LANES-1:0] fine_adjust_lane_cnt;
wire ck_po_stg2_f_indec;
wire ck_po_stg2_f_en;
wire dqs_found_prech_req;
wire tempmon_pi_f_inc;
wire tempmon_pi_f_dec;
wire tempmon_sel_pi_incdec;
wire wrcal_sanity_chk;
wire wrcal_sanity_chk_done;
//*****************************************************************************
// Assertions to check correctness of parameter values
//*****************************************************************************
// synthesis translate_off
initial
begin
if (RANKS == 0) begin
$display ("Error: Invalid RANKS parameter. Must be 1 or greater");
$finish;
end
if (phy_ctl_full == 1'b1) begin
$display ("Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode");
$finish;
end
end
// synthesis translate_on
//***************************************************************************
// Debug
//***************************************************************************
assign dbg_pi_phaselock_start = pi_phaselock_start;
assign dbg_pi_dqsfound_start = pi_dqs_found_start;
assign dbg_pi_dqsfound_done = pi_dqs_found_done;
assign dbg_wrcal_start = wrcal_start;
assign dbg_wrcal_done = wrcal_done;
// Unused for now - use these as needed to bring up lower level signals
assign dbg_calib_top = 256'd0;
// Write Level and write calibration debug observation ports
assign dbg_wrlvl_start = wrlvl_start;
assign dbg_wrlvl_done = wrlvl_done;
assign dbg_wrlvl_err = wrlvl_err;
// Read Level debug observation ports
assign dbg_rdlvl_start = {mpr_rdlvl_start, rdlvl_stg1_start};
assign dbg_rdlvl_done = {mpr_rdlvl_done, rdlvl_stg1_done};
assign dbg_rdlvl_err = {mpr_rdlvl_err, rdlvl_err};
assign dbg_oclkdelay_calib_done = oclkdelay_calib_done;
assign dbg_oclkdelay_calib_start = oclkdelay_calib_start;
//***************************************************************************
// Write leveling dependent signals
//***************************************************************************
assign wrcal_resume_w = (WRLVL == "ON") ? wrcal_pat_resume : 1'b0;
assign wrlvl_done_w = (WRLVL == "ON") ? wrlvl_done : 1'b1;
assign ck_addr_cmd_delay_done = (WRLVL == "ON") ? po_ck_addr_cmd_delay_done :
(po_ck_addr_cmd_delay_done
&& pi_fine_dly_dec_done) ;
generate
genvar i;
for (i = 0; i <= 2; i = i+1) begin : bankwise_signal
assign po_sel_stg2stg3[i] = ((~oclk_init_delay_done && ck_addr_cmd_delay_done &&
(DRAM_TYPE=="DDR3")) ? 1'b1 :
~oclkdelay_calib_done ? po_stg23_sel : 1'b0
) | dbg_po_f_stg23_sel_r;
assign po_stg2_c_incdec[i] = cmd_po_stg2_c_incdec ||
cmd_po_stg2_incdec_ddr2_c ||
dqs_wl_po_stg2_c_incdec;
assign po_en_stg2_c[i] = cmd_po_en_stg2_c ||
cmd_po_en_stg2_ddr2_c ||
dqs_wl_po_en_stg2_c;
assign po_stg2_f_incdec[i] = dqs_po_stg2_f_incdec ||
cmd_po_stg2_f_incdec ||
po_stg3_incdec ||
ck_po_stg2_f_indec ||
po_stg23_incdec ||
dbg_po_f_inc_r;
assign po_en_stg2_f[i] = dqs_po_en_stg2_f ||
cmd_po_en_stg2_f ||
po_en_stg3 ||
ck_po_stg2_f_en ||
po_en_stg23 ||
dbg_po_f_en_r;
end
endgenerate
assign pi_stg2_f_incdec = (dbg_pi_f_inc_r | rdlvl_pi_stg2_f_incdec | prbs_pi_stg2_f_incdec | tempmon_pi_f_inc_r);
assign pi_en_stg2_f = (dbg_pi_f_en_r | rdlvl_pi_stg2_f_en | prbs_pi_stg2_f_en | tempmon_pi_f_en_r);
assign idelay_ce = idelay_ce_r2;
assign idelay_inc = idelay_inc_r2;
assign po_counter_load_en = 1'b0;
// Added single stage flop to meet timing
always @(posedge clk)
init_calib_complete <= calib_complete;
assign calib_rd_data_offset_0 = rd_data_offset_ranks_mc_0;
assign calib_rd_data_offset_1 = rd_data_offset_ranks_mc_1;
assign calib_rd_data_offset_2 = rd_data_offset_ranks_mc_2;
//***************************************************************************
// Hard PHY signals
//***************************************************************************
assign pi_phase_locked_err = phase_locked_err;
assign pi_dqsfound_err = pi_dqs_found_err;
assign wrcal_err = wrcal_pat_err;
assign rst_tg_mc = 1'b0;
always @(posedge clk)
phy_if_reset <= #TCQ (phy_if_reset_w | mpr_end_if_reset |
reset_if | wrlvl_final_if_rst);
//***************************************************************************
// Phaser_IN inc dec control for debug
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
dbg_pi_f_inc_r <= #TCQ 1'b0;
dbg_pi_f_en_r <= #TCQ 1'b0;
dbg_sel_pi_incdec_r <= #TCQ 1'b0;
end else begin
dbg_pi_f_inc_r <= #TCQ dbg_pi_f_inc;
dbg_pi_f_en_r <= #TCQ (dbg_pi_f_inc | dbg_pi_f_dec);
dbg_sel_pi_incdec_r <= #TCQ dbg_sel_pi_incdec;
end
end
//***************************************************************************
// Phaser_OUT inc dec control for debug
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
dbg_po_f_inc_r <= #TCQ 1'b0;
dbg_po_f_stg23_sel_r<= #TCQ 1'b0;
dbg_po_f_en_r <= #TCQ 1'b0;
dbg_sel_po_incdec_r <= #TCQ 1'b0;
end else begin
dbg_po_f_inc_r <= #TCQ dbg_po_f_inc;
dbg_po_f_stg23_sel_r<= #TCQ dbg_po_f_stg23_sel;
dbg_po_f_en_r <= #TCQ (dbg_po_f_inc | dbg_po_f_dec);
dbg_sel_po_incdec_r <= #TCQ dbg_sel_po_incdec;
end
end
//***************************************************************************
// Phaser_IN inc dec control for temperature tracking
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
tempmon_pi_f_inc_r <= #TCQ 1'b0;
tempmon_pi_f_en_r <= #TCQ 1'b0;
tempmon_sel_pi_incdec_r <= #TCQ 1'b0;
end else begin
tempmon_pi_f_inc_r <= #TCQ tempmon_pi_f_inc;
tempmon_pi_f_en_r <= #TCQ (tempmon_pi_f_inc | tempmon_pi_f_dec);
tempmon_sel_pi_incdec_r <= #TCQ tempmon_sel_pi_incdec;
end
end
//***************************************************************************
// OCLKDELAY calibration signals
//***************************************************************************
// Minimum of 5 'clk' cycles required between assertion of po_sel_stg2stg3
// and increment/decrement of Phaser_Out stage 3 delay
always @(posedge clk) begin
ck_addr_cmd_delay_done_r1 <= #TCQ ck_addr_cmd_delay_done;
ck_addr_cmd_delay_done_r2 <= #TCQ ck_addr_cmd_delay_done_r1;
ck_addr_cmd_delay_done_r3 <= #TCQ ck_addr_cmd_delay_done_r2;
ck_addr_cmd_delay_done_r4 <= #TCQ ck_addr_cmd_delay_done_r3;
ck_addr_cmd_delay_done_r5 <= #TCQ ck_addr_cmd_delay_done_r4;
ck_addr_cmd_delay_done_r6 <= #TCQ ck_addr_cmd_delay_done_r5;
end
assign oclk_init_delay_start = ck_addr_cmd_delay_done_r6 && (DRAM_TYPE=="DDR3"); // && (SIM_CAL_OPTION == "NONE")
//***************************************************************************
// MUX select logic to select current byte undergoing calibration
// Use DQS_CAL_MAP to determine the correlation between the physical
// byte numbering, and the byte numbering within the hard PHY
//***************************************************************************
generate
if (tCK > 2500) begin: gen_byte_sel_div2
always @(posedge clk) begin
if (rst) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done) begin
ctl_lane_sel <= #TCQ ctl_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~oclk_init_delay_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_calib_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_dqs_found_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~wrlvl_done_w) begin
if (SIM_CAL_OPTION != "FAST_CAL") begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b0;
end else begin
// Special case for FAST_CAL simulation only to ensure that
// calib_in_common isn't asserted too soon
if (!phy_ctl_rdy_dly) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b1;
end
end
end else if (~mpr_rdlvl_done) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~oclkdelay_calib_done) begin
byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~rdlvl_stg1_done && pi_calib_done) begin
if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~wrcal_done) begin
byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
byte_sel_cnt <= #TCQ dbg_byte_sel;
calib_in_common <= #TCQ 1'b0;
end else if (tempmon_sel_pi_incdec) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end
end
end else begin: gen_byte_sel_div1
always @(posedge clk) begin
if (rst) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done) begin
ctl_lane_sel <= #TCQ ctl_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~oclk_init_delay_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_calib_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_dqs_found_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~wrlvl_done_w) begin
if (SIM_CAL_OPTION != "FAST_CAL") begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b0;
end else begin
// Special case for FAST_CAL simulation only to ensure that
// calib_in_common isn't asserted too soon
if (!phy_ctl_rdy_dly) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b1;
end
end
end else if (~mpr_rdlvl_done) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~oclkdelay_calib_done) begin
byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if ((~wrcal_done)&& (DRAM_TYPE == "DDR3")) begin
byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~rdlvl_stg1_done && pi_calib_done) begin
if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
byte_sel_cnt <= #TCQ dbg_byte_sel;
calib_in_common <= #TCQ 1'b0;
end else if (tempmon_sel_pi_incdec) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end
end
end
endgenerate
always @(posedge clk) begin
if (rst || (calib_complete && ~ (dbg_sel_pi_incdec_r|dbg_sel_po_incdec_r|tempmon_sel_pi_incdec) )) begin
calib_sel <= #TCQ 6'b000100;
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
if (~dqs_po_dec_done && (WRLVL != "ON"))
//if (~dqs_po_dec_done && ((SIM_CAL_OPTION == "FAST_CAL") ||(WRLVL != "ON")))
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
else
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~ck_addr_cmd_delay_done || (~fine_adjust_done && rd_data_offset_cal_done)) begin
if(WRLVL =="ON") begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ CTL_BYTE_LANE[(ctl_lane_sel*2)+:2];
calib_sel[5:3] <= #TCQ CTL_BANK;
if (|pi_rst_stg1_cal) begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
end else begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_inputs[1*CTL_BANK] <= #TCQ 1'b0;
end
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else begin // if (WRLVL =="ON")
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
if(~ck_addr_cmd_delay_done)
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
else
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
end // else: !if(WRLVL =="ON")
end else if (~oclk_init_delay_done) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == "FAST_CAL")) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~rdlvl_stg1_done && (SIM_CAL_OPTION == "FAST_CAL") &&
rdlvl_assrt_common) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (tempmon_sel_pi_incdec) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
if (~calib_in_common) begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0;
end else
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
end
end
// Logic to reset IN_FIFO flags to account for the possibility that
// one or more PHASER_IN's have not correctly found the DQS preamble
// If this happens, we can still complete read leveling, but the # of
// words written into the IN_FIFO's may be an odd #, so that if the
// IN_FIFO is used in 2:1 mode ("8:4 mode"), there may be a "half" word
// of data left that can only be flushed out by reseting the IN_FIFO
always @(posedge clk) begin
rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done;
prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done;
reset_if_r1 <= #TCQ reset_if;
reset_if_r2 <= #TCQ reset_if_r1;
reset_if_r3 <= #TCQ reset_if_r2;
reset_if_r4 <= #TCQ reset_if_r3;
reset_if_r5 <= #TCQ reset_if_r4;
reset_if_r6 <= #TCQ reset_if_r5;
reset_if_r7 <= #TCQ reset_if_r6;
reset_if_r8 <= #TCQ reset_if_r7;
reset_if_r9 <= #TCQ reset_if_r8;
end
always @(posedge clk) begin
if (rst || reset_if_r9)
reset_if <= #TCQ 1'b0;
else if ((rdlvl_stg1_done && ~rdlvl_stg1_done_r1) ||
(prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
reset_if <= #TCQ 1'b1;
end
assign phy_if_empty_def = 1'b0;
// DQ IDELAY tap inc and ce signals registered to control calib_in_common
// signal during read leveling in FAST_CAL mode. The calib_in_common signal
// is only asserted for IDELAY tap increments not Phaser_IN tap increments
// in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load
// inputs are used.
always @(posedge clk) begin
if (rst) begin
idelay_ce_r1 <= #TCQ 1'b0;
idelay_ce_r2 <= #TCQ 1'b0;
idelay_inc_r1 <= #TCQ 1'b0;
idelay_inc_r2 <= #TCQ 1'b0;
end else begin
idelay_ce_r1 <= #TCQ idelay_ce_int;
idelay_ce_r2 <= #TCQ idelay_ce_r1;
idelay_inc_r1 <= #TCQ idelay_inc_int;
idelay_inc_r2 <= #TCQ idelay_inc_r1;
end
end
//***************************************************************************
// Delay all Outputs using Phaser_Out fine taps
//***************************************************************************
assign init_wrcal_complete = 1'b0;
//***************************************************************************
// PRBS Generator for Read Leveling Stage 1 - read window detection and
// DQS Centering
//***************************************************************************
// Assign initial seed (used for 1st data word in 8-burst sequence); use alternating 1/0 pat
assign prbs_seed = 64'h9966aa559966aa55;
// A single PRBS generator
// writes 64-bits every 4to1 fabric clock cycle and
// write 32-bits every 2to1 fabric clock cycle
mig_7series_v1_9_ddr_prbs_gen #
(
.TCQ (TCQ),
.PRBS_WIDTH (2*8*nCK_PER_CLK)
)
u_ddr_prbs_gen
(
.clk_i (clk),
.clk_en_i (prbs_gen_clk_en),
.rst_i (rst),
.prbs_o (prbs_out),
.prbs_seed_i (prbs_seed),
.phy_if_empty (phy_if_empty),
.prbs_rdlvl_start (prbs_rdlvl_start)
);
// PRBS data slice that decides the Rise0, Fall0, Rise1, Fall1,
// Rise2, Fall2, Rise3, Fall3 data
generate
if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
assign prbs_rise0 = prbs_out[7:0];
assign prbs_fall0 = prbs_out[15:8];
assign prbs_rise1 = prbs_out[23:16];
assign prbs_fall1 = prbs_out[31:24];
assign prbs_rise2 = prbs_out[39:32];
assign prbs_fall2 = prbs_out[47:40];
assign prbs_rise3 = prbs_out[55:48];
assign prbs_fall3 = prbs_out[63:56];
assign prbs_o = {prbs_fall3, prbs_rise3, prbs_fall2, prbs_rise2,
prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};
end else begin :gen_ck_per_clk2
assign prbs_rise0 = prbs_out[7:0];
assign prbs_fall0 = prbs_out[15:8];
assign prbs_rise1 = prbs_out[23:16];
assign prbs_fall1 = prbs_out[31:24];
assign prbs_o = {prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};
end
endgenerate
//***************************************************************************
// Initialization / Master PHY state logic (overall control during memory
// init, timing leveling)
//***************************************************************************
mig_7series_v1_9_ddr_phy_init #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DRAM_TYPE (DRAM_TYPE),
.PRBS_WIDTH (PRBS_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.CA_MIRROR (CA_MIRROR),
.COL_WIDTH (COL_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.CS_WIDTH (CS_WIDTH),
.RANKS (RANKS),
.CKE_WIDTH (CKE_WIDTH),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.AL (AL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.nCL (nCL),
.nCWL (nCWL),
.tRFC (tRFC),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.WRLVL (WRLVL),
.USE_ODT_PORT (USE_ODT_PORT),
.DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE),
.nSLOTS (nSLOTS),
.SIM_INIT_OPTION (SIM_INIT_OPTION),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.CKE_ODT_AUX (CKE_ODT_AUX),
.PRE_REV3ES (PRE_REV3ES),
.TEST_AL (TEST_AL)
)
u_ddr_phy_init
(
.clk (clk),
.rst (rst),
.prbs_o (prbs_o),
.ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
.delay_incdec_done (ck_addr_cmd_delay_done & oclk_init_delay_done),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_phaselock_start (pi_phaselock_start),
.pi_phase_locked_err (phase_locked_err),
.pi_calib_done (pi_calib_done),
.phy_if_empty (phy_if_empty),
.phy_ctl_ready (phy_ctl_ready),
.phy_ctl_full (phy_ctl_full),
.phy_cmd_full (phy_cmd_full),
.phy_data_full (phy_data_full),
.calib_ctl_wren (calib_ctl_wren),
.calib_cmd_wren (calib_cmd_wren),
.calib_wrdata_en (calib_wrdata_en),
.calib_seq (calib_seq),
.calib_aux_out (calib_aux_out),
.calib_rank_cnt (calib_rank_cnt),
.calib_cas_slot (calib_cas_slot),
.calib_data_offset_0 (calib_data_offset_0),
.calib_data_offset_1 (calib_data_offset_1),
.calib_data_offset_2 (calib_data_offset_2),
.calib_cmd (calib_cmd),
.calib_cke (calib_cke),
.calib_odt (calib_odt),
.write_calib (write_calib),
.read_calib (read_calib),
.wrlvl_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.wrlvl_byte_done (wrlvl_byte_done),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrlvl_final (wrlvl_final),
.wrlvl_final_if_rst (wrlvl_final_if_rst),
.oclkdelay_calib_start (oclkdelay_calib_start),
.oclkdelay_calib_done (oclkdelay_calib_done),
.oclk_prech_req (oclk_prech_req),
.oclk_calib_resume (oclk_calib_resume),
.done_dqs_tap_inc (done_dqs_tap_inc),
.wl_sm_start (wl_sm_start),
.wr_lvl_start (wrlvl_start),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
.mpr_rdlvl_done (mpr_rdlvl_done),
.mpr_rdlvl_start (mpr_rdlvl_start),
.mpr_last_byte_done (mpr_last_byte_done),
.mpr_rnk_done (mpr_rnk_done),
.mpr_end_if_reset (mpr_end_if_reset),
.rdlvl_stg1_done (rdlvl_stg1_done),
.rdlvl_stg1_rank_done (rdlvl_stg1_rank_done),
.rdlvl_stg1_start (rdlvl_stg1_start),
.rdlvl_prech_req (rdlvl_prech_req),
.rdlvl_last_byte_done (rdlvl_last_byte_done),
.prbs_rdlvl_start (prbs_rdlvl_start),
.prbs_rdlvl_done (prbs_rdlvl_done),
.prbs_last_byte_done (prbs_last_byte_done),
.prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
.prbs_gen_clk_en (prbs_gen_clk_en),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_rank_done(pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.detect_pi_found_dqs (detect_pi_found_dqs),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.rd_data_offset_ranks_0(rd_data_offset_ranks_0),
.rd_data_offset_ranks_1(rd_data_offset_ranks_1),
.rd_data_offset_ranks_2(rd_data_offset_ranks_2),
.wrcal_start (wrcal_start),
.wrcal_rd_wait (wrcal_rd_wait),
.wrcal_prech_req (wrcal_prech_req),
.wrcal_resume (wrcal_resume_w),
.wrcal_read_req (wrcal_read_req),
.wrcal_act_req (wrcal_act_req),
.wrcal_sanity_chk (wrcal_sanity_chk),
.temp_wrcal_done (temp_wrcal_done),
.wrcal_sanity_chk_done (wrcal_sanity_chk_done),
.tg_timer_done (tg_timer_done),
.no_rst_tg_mc (no_rst_tg_mc),
.wrcal_done (wrcal_done),
.prech_done (prech_done),
.calib_writes (calib_writes),
.init_calib_complete (calib_complete),
.phy_address (phy_address),
.phy_bank (phy_bank),
.phy_cas_n (phy_cas_n),
.phy_cs_n (phy_cs_n),
.phy_ras_n (phy_ras_n),
.phy_reset_n (phy_reset_n),
.phy_we_n (phy_we_n),
.phy_wrdata (phy_wrdata),
.phy_rddata_en (phy_rddata_en),
.phy_rddata_valid (phy_rddata_valid),
.dbg_phy_init (dbg_phy_init)
);
//*****************************************************************
// Write Calibration
//*****************************************************************
mig_7series_v1_9_ddr_phy_wrcal #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.SIM_CAL_OPTION (SIM_CAL_OPTION)
)
u_ddr_phy_wrcal
(
.clk (clk),
.rst (rst),
.wrcal_start (wrcal_start),
.wrcal_rd_wait (wrcal_rd_wait),
.wrcal_sanity_chk (wrcal_sanity_chk),
.dqsfound_retry_done (pi_dqs_found_done),
.dqsfound_retry (dqsfound_retry),
.wrcal_read_req (wrcal_read_req),
.wrcal_act_req (wrcal_act_req),
.phy_rddata_en (phy_rddata_en),
.wrcal_done (wrcal_done),
.wrcal_pat_err (wrcal_pat_err),
.wrcal_prech_req (wrcal_prech_req),
.temp_wrcal_done (temp_wrcal_done),
.wrcal_sanity_chk_done (wrcal_sanity_chk_done),
.prech_done (prech_done),
.rd_data (phy_rddata),
.wrcal_pat_resume (wrcal_pat_resume),
.po_stg2_wrcal_cnt (po_stg2_wrcal_cnt),
.phy_if_reset (phy_if_reset_w),
.wl_po_coarse_cnt (wl_po_coarse_cnt),
.wl_po_fine_cnt (wl_po_fine_cnt),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrlvl_byte_done (wrlvl_byte_done),
.early1_data (early1_data),
.early2_data (early2_data),
.idelay_ld (idelay_ld),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt)
);
//***************************************************************************
// Write-leveling calibration logic
//***************************************************************************
generate
if (WRLVL == "ON") begin: mb_wrlvl_inst
mig_7series_v1_9_ddr_phy_wrlvl #
(
.TCQ (TCQ),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.CLK_PERIOD (CLK_PERIOD),
.nCK_PER_CLK (nCK_PER_CLK),
.SIM_CAL_OPTION (SIM_CAL_OPTION)
)
u_ddr_phy_wrlvl
(
.clk (clk),
.rst (rst),
.phy_ctl_ready (phy_ctl_ready),
.wr_level_start (wrlvl_start),
.wl_sm_start (wl_sm_start),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrcal_cnt (po_stg2_wrcal_cnt),
.early1_data (early1_data),
.early2_data (early2_data),
.wrlvl_final (wrlvl_final),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt),
.wrlvl_byte_done (wrlvl_byte_done),
.oclkdelay_calib_done (oclkdelay_calib_done),
.rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]),
.dqs_po_dec_done (dqs_po_dec_done),
.phy_ctl_rdy_dly (phy_ctl_rdy_dly),
.wr_level_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.done_dqs_tap_inc (done_dqs_tap_inc),
.dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec),
.dqs_po_en_stg2_f (dqs_po_en_stg2_f),
.dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec),
.dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c),
.po_counter_read_val (po_counter_read_val),
.po_stg2_wl_cnt (po_stg2_wl_cnt),
.wrlvl_err (wrlvl_err),
.wl_po_coarse_cnt (wl_po_coarse_cnt),
.wl_po_fine_cnt (wl_po_fine_cnt),
.dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_dqs_count (),
.dbg_wl_state (),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl)
);
mig_7series_v1_9_ddr_phy_ck_addr_cmd_delay #
(
.TCQ (TCQ),
.tCK (tCK),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.N_CTL_LANES (N_CTL_LANES),
.SIM_CAL_OPTION(SIM_CAL_OPTION)
)
u_ddr_phy_ck_addr_cmd_delay
(
.clk (clk),
.rst (rst),
.cmd_delay_start (dqs_po_dec_done & pi_fine_dly_dec_done),
.ctl_lane_cnt (ctl_lane_cnt),
.po_stg2_f_incdec (cmd_po_stg2_f_incdec),
.po_en_stg2_f (cmd_po_en_stg2_f),
.po_stg2_c_incdec (cmd_po_stg2_c_incdec),
.po_en_stg2_c (cmd_po_en_stg2_c),
.po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done)
);
assign cmd_po_stg2_incdec_ddr2_c = 1'b0;
assign cmd_po_en_stg2_ddr2_c = 1'b0;
end else begin: mb_wrlvl_off
mig_7series_v1_9_ddr_phy_wrlvl_off_delay #
(
.TCQ (TCQ),
.tCK (tCK),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.PO_INITIAL_DLY(60),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.N_CTL_LANES (N_CTL_LANES)
)
u_phy_wrlvl_off_delay
(
.clk (clk),
.rst (rst),
.pi_fine_dly_dec_done (pi_fine_dly_dec_done),
.cmd_delay_start (phy_ctl_ready),
.ctl_lane_cnt (ctl_lane_cnt),
.po_s2_incdec_f (cmd_po_stg2_f_incdec),
.po_en_s2_f (cmd_po_en_stg2_f),
.po_s2_incdec_c (cmd_po_stg2_incdec_ddr2_c),
.po_en_s2_c (cmd_po_en_stg2_ddr2_c),
.po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done),
.po_dec_done (dqs_po_dec_done),
.phy_ctl_rdy_dly (phy_ctl_rdy_dly)
);
assign wrlvl_done = 1'b1;
assign wrlvl_err = 1'b0;
assign dqs_po_stg2_f_incdec = 1'b0;
assign dqs_po_en_stg2_f = 1'b0;
assign dqs_wl_po_en_stg2_c = 1'b0;
assign cmd_po_stg2_c_incdec = 1'b0;
assign dqs_wl_po_stg2_c_incdec = 1'b0;
assign cmd_po_en_stg2_c = 1'b0;
end
endgenerate
generate
if(WRLVL == "ON") begin: oclk_calib
mig_7series_v1_9_ddr_phy_oclkdelay_cal #
(
.TCQ (TCQ),
.tCK (tCK),
.nCK_PER_CLK (nCK_PER_CLK),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.OCAL_EN (OCAL_EN)
)
u_ddr_phy_oclkdelay_cal
(
.clk (clk),
.rst (rst),
.oclk_init_delay_start (oclk_init_delay_start),
.oclkdelay_calib_start (oclkdelay_calib_start),
.oclkdelay_init_val (oclkdelay_init_val),
.phy_rddata_en (phy_rddata_en),
.rd_data (phy_rddata),
.prech_done (prech_done),
.wl_po_fine_cnt (wl_po_fine_cnt),
.po_stg3_incdec (po_stg3_incdec),
.po_en_stg3 (po_en_stg3),
.po_stg23_sel (po_stg23_sel),
.po_stg23_incdec (po_stg23_incdec),
.po_en_stg23 (po_en_stg23),
.wrlvl_final (wrlvl_final),
.oclk_prech_req (oclk_prech_req),
.oclk_calib_resume (oclk_calib_resume),
.oclk_init_delay_done (oclk_init_delay_done),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt),
.oclkdelay_calib_done (oclkdelay_calib_done),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data)
);
end else begin : oclk_calib_disabled
assign wrlvl_final = 'b0;
assign po_stg3_incdec = 'b0;
assign po_en_stg3 = 'b0;
assign po_stg23_sel = 'b0;
assign po_stg23_incdec = 'b0;
assign po_en_stg23 = 'b0;
assign oclk_init_delay_done = 1'b1;
assign oclkdelay_calib_cnt = 'b0;
assign oclk_prech_req = 'b0;
assign oclk_calib_resume = 'b0;
assign oclkdelay_calib_done = 1'b1;
end
endgenerate
//***************************************************************************
// Read data-offset calibration required for Phaser_In
//***************************************************************************
generate
if(DQSFOUND_CAL == "RIGHT") begin: dqsfind_calib_right
mig_7series_v1_9_ddr_phy_dqs_found_cal #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.nCL (nCL),
.AL (AL),
.nCWL (nCWL),
//.RANKS (RANKS),
.RANKS (1),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.REG_CTRL (REG_CTRL),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DRAM_TYPE (DRAM_TYPE),
.NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
.N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
.HIGHEST_LANE (HIGHEST_LANE),
.HIGHEST_BANK (HIGHEST_BANK),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4)
)
u_ddr_phy_dqs_found_cal
(
.clk (clk),
.rst (rst),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.detect_pi_found_dqs (detect_pi_found_dqs),
.prech_done (prech_done),
.pi_dqs_found_lanes (pi_dqs_found_lanes),
.pi_rst_stg1_cal (pi_rst_stg1_cal),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.pi_dqs_found_rank_done (pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.dqsfound_retry_done (dqsfound_retry_done),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_err (pi_dqs_found_err),
.rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
.rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
.rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
.rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
.rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
.rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
.po_counter_read_val (po_counter_read_val),
.rd_data_offset_cal_done (rd_data_offset_cal_done),
.fine_adjust_done (fine_adjust_done),
.fine_adjust_lane_cnt (fine_adjust_lane_cnt),
.ck_po_stg2_f_indec (ck_po_stg2_f_indec),
.ck_po_stg2_f_en (ck_po_stg2_f_en),
.dbg_dqs_found_cal (dbg_dqs_found_cal)
);
end else begin: dqsfind_calib_left
mig_7series_v1_9_ddr_phy_dqs_found_cal_hr #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.nCL (nCL),
.AL (AL),
.nCWL (nCWL),
//.RANKS (RANKS),
.RANKS (1),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.REG_CTRL (REG_CTRL),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DRAM_TYPE (DRAM_TYPE),
.NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
.N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
.HIGHEST_LANE (HIGHEST_LANE),
.HIGHEST_BANK (HIGHEST_BANK),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4)
)
u_ddr_phy_dqs_found_cal_hr
(
.clk (clk),
.rst (rst),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.detect_pi_found_dqs (detect_pi_found_dqs),
.prech_done (prech_done),
.pi_dqs_found_lanes (pi_dqs_found_lanes),
.pi_rst_stg1_cal (pi_rst_stg1_cal),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.pi_dqs_found_rank_done (pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.dqsfound_retry_done (dqsfound_retry_done),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_err (pi_dqs_found_err),
.rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
.rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
.rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
.rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
.rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
.rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
.po_counter_read_val (po_counter_read_val),
.rd_data_offset_cal_done (rd_data_offset_cal_done),
.fine_adjust_done (fine_adjust_done),
.fine_adjust_lane_cnt (fine_adjust_lane_cnt),
.ck_po_stg2_f_indec (ck_po_stg2_f_indec),
.ck_po_stg2_f_en (ck_po_stg2_f_en),
.dbg_dqs_found_cal (dbg_dqs_found_cal)
);
end
endgenerate
//***************************************************************************
// Read-leveling calibration logic
//***************************************************************************
mig_7series_v1_9_ddr_phy_rdlvl #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.PER_BIT_DESKEW (PER_BIT_DESKEW),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DEBUG_PORT (DEBUG_PORT),
.DRAM_TYPE (DRAM_TYPE),
.OCAL_EN (OCAL_EN)
)
u_ddr_phy_rdlvl
(
.clk (clk),
.rst (rst),
.mpr_rdlvl_done (mpr_rdlvl_done),
.mpr_rdlvl_start (mpr_rdlvl_start),
.mpr_last_byte_done (mpr_last_byte_done),
.mpr_rnk_done (mpr_rnk_done),
.rdlvl_stg1_start (rdlvl_stg1_start),
.rdlvl_stg1_done (rdlvl_stg1_done),
.rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done),
.rdlvl_stg1_err (rdlvl_stg1_err),
.mpr_rdlvl_err (mpr_rdlvl_err),
.rdlvl_err (rdlvl_err),
.rdlvl_prech_req (rdlvl_prech_req),
.rdlvl_last_byte_done (rdlvl_last_byte_done),
.rdlvl_assrt_common (rdlvl_assrt_common),
.prech_done (prech_done),
.phy_if_empty (phy_if_empty),
.idelaye2_init_val (idelaye2_init_val),
.rd_data (phy_rddata),
.pi_en_stg2_f (rdlvl_pi_stg2_f_en),
.pi_stg2_f_incdec (rdlvl_pi_stg2_f_incdec),
.pi_stg2_load (pi_stg2_load),
.pi_stg2_reg_l (pi_stg2_reg_l),
.dqs_po_dec_done (dqs_po_dec_done),
.pi_counter_read_val (pi_counter_read_val),
.pi_fine_dly_dec_done (pi_fine_dly_dec_done),
.idelay_ce (idelay_ce_int),
.idelay_inc (idelay_inc_int),
.idelay_ld (idelay_ld),
.wrcal_cnt (po_stg2_wrcal_cnt),
.pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt),
.dlyval_dq (dlyval_dq),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_phy_rdlvl (dbg_phy_rdlvl)
);
generate
if(DRAM_TYPE == "DDR3") begin:ddr_phy_prbs_rdlvl_gen
mig_7series_v1_9_ddr_phy_prbs_rdlvl #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.PRBS_WIDTH (PRBS_WIDTH)
)
u_ddr_phy_prbs_rdlvl
(
.clk (clk),
.rst (rst),
.prbs_rdlvl_start (prbs_rdlvl_start),
.prbs_rdlvl_done (prbs_rdlvl_done),
.prbs_last_byte_done (prbs_last_byte_done),
.prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
.prech_done (prech_done),
.phy_if_empty (phy_if_empty),
.rd_data (phy_rddata),
.compare_data (prbs_o),
.pi_counter_read_val (pi_counter_read_val),
.pi_en_stg2_f (prbs_pi_stg2_f_en),
.pi_stg2_f_incdec (prbs_pi_stg2_f_incdec),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.pi_stg2_prbs_rdlvl_cnt (pi_stg2_prbs_rdlvl_cnt)
);
end else begin:ddr_phy_prbs_rdlvl_off
assign prbs_rdlvl_done = rdlvl_stg1_done ;
assign prbs_last_byte_done = rdlvl_stg1_rank_done ;
assign prbs_rdlvl_prech_req = 1'b0 ;
assign prbs_pi_stg2_f_en = 1'b0 ;
assign prbs_pi_stg2_f_incdec = 1'b0 ;
assign pi_stg2_prbs_rdlvl_cnt = 'b0 ;
end
endgenerate
//***************************************************************************
// Temperature induced PI tap adjustment logic
//***************************************************************************
mig_7series_v1_9_ddr_phy_tempmon #
(
.TCQ (TCQ)
)
ddr_phy_tempmon_0
(
.rst (rst),
.clk (clk),
.calib_complete (calib_complete),
.tempmon_pi_f_inc (tempmon_pi_f_inc),
.tempmon_pi_f_dec (tempmon_pi_f_dec),
.tempmon_sel_pi_incdec (tempmon_sel_pi_incdec),
.device_temp (device_temp),
.tempmon_sample_en (tempmon_sample_en)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_calib_top.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:06 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
//Purpose:
// Top-level for memory physical layer (PHY) interface
// NOTES:
// 1. Need to support multiple copies of CS outputs
// 2. DFI_DRAM_CKE_DISABLE not supported
//
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $
**$Date: 2011/06/02 08:35:06 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_ddr_calib_top #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter tCK = 2500, // DDR3 SDRAM clock period
parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
parameter N_CTL_LANES = 3, // # of control byte lanes in the PHY
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter PRBS_WIDTH = 8, // The PRBS sequence is 2^PRBS_WIDTH
parameter HIGHEST_LANE = 4,
parameter HIGHEST_BANK = 3,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
// five fields, one per possible I/O bank, 4 bits in each field,
// 1 per lane data=1/ctl=0
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
// defines the byte lanes in I/O banks being used in the interface
// 1- Used, 0- Unused
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter CTL_BYTE_LANE = 8'hE4, // Control byte lane map
parameter CTL_BANK = 3'b000, // Bank used for control byte lanes
// Slot Conifg parameters
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
// DRAM bus widths
parameter BANK_WIDTH = 2, // # of bank bits
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter COL_WIDTH = 10, // column address width
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ROW_WIDTH = 14, // DRAM address bus width
parameter RANKS = 1, // # of memory ranks in the interface
parameter CS_WIDTH = 1, // # of CS# signals in the interface
parameter CKE_WIDTH = 1, // # of cke outputs
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter PER_BIT_DESKEW = "ON",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter NUM_DQSFOUND_CAL = 1020, // # of iteration of DQSFOUND calib
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// DRAM mode settings
parameter AL = "0", // Additive Latency option
parameter TEST_AL = "0", // Additive Latency for internal use
parameter ADDR_CMD_MODE = "1T", // ADDR/CTRL timing: "2T", "1T"
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter nCL = 5, // Read CAS latency (in clk cyc)
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter tRFC = 110000, // Refresh-to-command delay
parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RTT_NOM = "60", // ODT Nominal termination value
parameter RTT_WR = "60", // ODT Write termination value
parameter USE_ODT_PORT = 0, // 0 - No ODT output from FPGA
// 1 - ODT output from FPGA
parameter WRLVL = "OFF", // Enable write leveling
parameter PRE_REV3ES = "OFF", // Delay O/Ps using Phaser_Out fine dly
// Simulation /debug options
parameter SIM_INIT_OPTION = "NONE", // Performs all initialization steps
parameter SIM_CAL_OPTION = "NONE", // Performs all calibration steps
parameter CKE_ODT_AUX = "FALSE",
parameter DEBUG_PORT = "OFF" // Enable debug port
)
(
input clk, // Internal (logic) clock
input rst, // Reset sync'ed to CLK
// Slot present inputs
input [7:0] slot_0_present,
input [7:0] slot_1_present,
// Hard PHY signals
// From PHY Ctrl Block
input phy_ctl_ready,
input phy_ctl_full,
input phy_cmd_full,
input phy_data_full,
// To PHY Ctrl Block
output write_calib,
output read_calib,
output calib_ctl_wren,
output calib_cmd_wren,
output [1:0] calib_seq,
output [3:0] calib_aux_out,
output [nCK_PER_CLK -1:0] calib_cke,
output [1:0] calib_odt,
output [2:0] calib_cmd,
output calib_wrdata_en,
output [1:0] calib_rank_cnt,
output [1:0] calib_cas_slot,
output [5:0] calib_data_offset_0,
output [5:0] calib_data_offset_1,
output [5:0] calib_data_offset_2,
output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,
output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,
output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,
output [nCK_PER_CLK-1:0] phy_ras_n,
output [nCK_PER_CLK-1:0] phy_cas_n,
output [nCK_PER_CLK-1:0] phy_we_n,
output phy_reset_n,
// To hard PHY wrapper
(* keep = "true", max_fanout = 10 *) output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 */,
(* keep = "true", max_fanout = 10 *) output reg calib_in_common/* synthesis syn_maxfan = 10 */,
(* keep = "true", max_fanout = 10 *) output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 */,
output reg [HIGHEST_BANK-1:0] calib_zero_ctrl,
output phy_if_empty_def,
output reg phy_if_reset,
// output reg ck_addr_ctl_delay_done,
// From DQS Phaser_In
input pi_phaselocked,
input pi_phase_locked_all,
input pi_found_dqs,
input pi_dqs_found_all,
input [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
input [5:0] pi_counter_read_val,
// To DQS Phaser_In
output [HIGHEST_BANK-1:0] pi_rst_stg1_cal,
output pi_en_stg2_f,
output pi_stg2_f_incdec,
output pi_stg2_load,
output [5:0] pi_stg2_reg_l,
// To DQ IDELAY
output idelay_ce,
output idelay_inc,
output idelay_ld,
// To DQS Phaser_Out
(* keep = "true", max_fanout = 3 *) output [2:0] po_sel_stg2stg3 /* synthesis syn_maxfan = 3 */,
(* keep = "true", max_fanout = 3 *) output [2:0] po_stg2_c_incdec /* synthesis syn_maxfan = 3 */,
(* keep = "true", max_fanout = 3 *) output [2:0] po_en_stg2_c /* synthesis syn_maxfan = 3 */,
(* keep = "true", max_fanout = 3 *) output [2:0] po_stg2_f_incdec /* synthesis syn_maxfan = 3 */,
(* keep = "true", max_fanout = 3 *) output [2:0] po_en_stg2_f /* synthesis syn_maxfan = 3 */,
output po_counter_load_en,
input [8:0] po_counter_read_val,
// To command Phaser_Out
input phy_if_empty,
input [4:0] idelaye2_init_val,
input [5:0] oclkdelay_init_val,
input tg_err,
output rst_tg_mc,
// Write data to OUT_FIFO
output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata,
// To CNTVALUEIN input of DQ IDELAYs for perbit de-skew
output [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,
// IN_FIFO read enable during write leveling, write calibration,
// and read leveling
// Read data from hard PHY fans out to mc and calib logic
input[2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata,
// To MC
output [6*RANKS-1:0] calib_rd_data_offset_0,
output [6*RANKS-1:0] calib_rd_data_offset_1,
output [6*RANKS-1:0] calib_rd_data_offset_2,
output phy_rddata_valid,
output calib_writes,
(* keep = "true", max_fanout = 10 *) output reg init_calib_complete/* synthesis syn_maxfan = 10 */,
output init_wrcal_complete,
output pi_phase_locked_err,
output pi_dqsfound_err,
output wrcal_err,
// Debug Port
output dbg_pi_phaselock_start,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrlvl_start,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output [255:0] dbg_phy_wrlvl,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
// Write Calibration Logic
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output [99:0] dbg_phy_wrcal,
// Read leveling logic
output [1:0] dbg_rdlvl_start,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
// Delay control
input [11:0] device_temp,
input tempmon_sample_en,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_cpt,
input dbg_idel_down_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input dbg_sel_all_idel_cpt,
output [255:0] dbg_phy_rdlvl, // Read leveling calibration
output [255:0] dbg_calib_top, // General PHY debug
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal
);
// Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center
// align DQ and DQS on writes. Round (up or down) value to nearest integer
// localparam integer SHIFT_TBY4_TAP
// = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) /
// (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4);
// Calculate number of slots in the system
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
localparam OCAL_EN = ((SIM_CAL_OPTION == "FAST_CAL") || (tCK > 2500)) ? "OFF" : "ON";
// Different CTL_LANES value for DDR2. In DDR2 during DQS found all
// the add,ctl & data phaser out fine delays will be adjusted.
// In DDR3 only the add/ctrl lane delays will be adjusted
localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == "DDR3") ? N_CTL_LANES : 1;
localparam DQSFOUND_CAL = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && tCK > 2500)) ? "LEFT" : "RIGHT"; // IO Bank used for Memory I/F: "LEFT", "RIGHT"
wire [2*8*nCK_PER_CLK-1:0] prbs_seed;
wire [2*8*nCK_PER_CLK-1:0] prbs_out;
wire [7:0] prbs_rise0;
wire [7:0] prbs_fall0;
wire [7:0] prbs_rise1;
wire [7:0] prbs_fall1;
wire [7:0] prbs_rise2;
wire [7:0] prbs_fall2;
wire [7:0] prbs_rise3;
wire [7:0] prbs_fall3;
wire [2*8*nCK_PER_CLK-1:0] prbs_o;
wire dqsfound_retry;
wire dqsfound_retry_done;
wire phy_rddata_en;
wire prech_done;
wire rdlvl_stg1_done;
reg rdlvl_stg1_done_r1;
wire pi_dqs_found_done;
wire rdlvl_stg1_err;
wire pi_dqs_found_err;
wire wrcal_pat_resume;
wire wrcal_resume_w;
wire rdlvl_prech_req;
wire rdlvl_last_byte_done;
wire rdlvl_stg1_start;
wire rdlvl_stg1_rank_done;
wire rdlvl_assrt_common;
wire pi_dqs_found_start;
wire pi_dqs_found_rank_done;
wire wl_sm_start;
wire wrcal_start;
wire wrcal_rd_wait;
wire wrcal_prech_req;
wire wrcal_pat_err;
wire wrcal_done;
wire wrlvl_done;
wire wrlvl_err;
wire wrlvl_start;
wire ck_addr_cmd_delay_done;
wire po_ck_addr_cmd_delay_done;
wire pi_calib_done;
wire detect_pi_found_dqs;
wire [5:0] rd_data_offset_0;
wire [5:0] rd_data_offset_1;
wire [5:0] rd_data_offset_2;
wire [6*RANKS-1:0] rd_data_offset_ranks_0;
wire [6*RANKS-1:0] rd_data_offset_ranks_1;
wire [6*RANKS-1:0] rd_data_offset_ranks_2;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_0;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_1;
wire [6*RANKS-1:0] rd_data_offset_ranks_mc_2;
wire cmd_po_stg2_f_incdec;
wire cmd_po_stg2_incdec_ddr2_c;
wire cmd_po_en_stg2_f;
wire cmd_po_en_stg2_ddr2_c;
wire cmd_po_stg2_c_incdec;
wire cmd_po_en_stg2_c;
wire po_stg2_ddr2_incdec;
wire po_en_stg2_ddr2;
wire dqs_po_stg2_f_incdec;
wire dqs_po_en_stg2_f;
wire dqs_wl_po_stg2_c_incdec;
wire wrcal_po_stg2_c_incdec;
wire dqs_wl_po_en_stg2_c;
wire wrcal_po_en_stg2_c;
wire [N_CTL_LANES-1:0] ctl_lane_cnt;
reg [N_CTL_LANES-1:0] ctl_lane_sel;
wire [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt;
wire [DQS_CNT_WIDTH:0] po_stg2_wl_cnt;
wire [DQS_CNT_WIDTH:0] po_stg2_ddr2_cnt;
wire [8:0] dqs_wl_po_stg2_reg_l;
wire dqs_wl_po_stg2_load;
wire [8:0] dqs_po_stg2_reg_l;
wire dqs_po_stg2_load;
wire dqs_po_dec_done;
wire pi_fine_dly_dec_done;
wire rdlvl_pi_stg2_f_incdec;
wire rdlvl_pi_stg2_f_en;
wire [DQS_CNT_WIDTH:0] pi_stg2_rdlvl_cnt;
reg [DQS_CNT_WIDTH:0] byte_sel_cnt;
wire [3*DQS_WIDTH-1:0] wl_po_coarse_cnt;
wire [6*DQS_WIDTH-1:0] wl_po_fine_cnt;
wire phase_locked_err;
wire phy_ctl_rdy_dly;
wire idelay_ce_int;
wire idelay_inc_int;
reg idelay_ce_r1;
reg idelay_ce_r2;
reg idelay_inc_r1;
(* keep = "true", max_fanout = 30 *) reg idelay_inc_r2 /* synthesis syn_maxfan = 30 */;
reg po_dly_req_r;
wire wrcal_read_req;
wire wrcal_act_req;
wire temp_wrcal_done;
wire tg_timer_done;
wire no_rst_tg_mc;
wire calib_complete;
reg reset_if_r1;
reg reset_if_r2;
reg reset_if_r3;
reg reset_if_r4;
reg reset_if_r5;
reg reset_if_r6;
reg reset_if_r7;
reg reset_if_r8;
reg reset_if_r9;
reg reset_if;
wire phy_if_reset_w;
wire pi_phaselock_start;
reg dbg_pi_f_inc_r;
reg dbg_pi_f_en_r;
reg dbg_sel_pi_incdec_r;
reg dbg_po_f_inc_r;
reg dbg_po_f_stg23_sel_r;
reg dbg_po_f_en_r;
reg dbg_sel_po_incdec_r;
reg tempmon_pi_f_inc_r;
reg tempmon_pi_f_en_r;
reg tempmon_sel_pi_incdec_r;
reg ck_addr_cmd_delay_done_r1;
reg ck_addr_cmd_delay_done_r2;
reg ck_addr_cmd_delay_done_r3;
reg ck_addr_cmd_delay_done_r4;
reg ck_addr_cmd_delay_done_r5;
reg ck_addr_cmd_delay_done_r6;
wire oclk_init_delay_start;
wire oclk_prech_req;
wire oclk_calib_resume;
wire oclk_init_delay_done;
wire [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
wire oclkdelay_calib_start;
wire oclkdelay_calib_done;
wire oclkdelay_calib_done_temp;
wire wrlvl_final;
wire wrlvl_final_if_rst;
wire wrlvl_byte_redo;
wire wrlvl_byte_done;
wire early1_data;
wire early2_data;
wire po_stg3_incdec;
wire po_en_stg3;
wire po_stg23_sel;
wire po_stg23_incdec;
wire po_en_stg23;
wire mpr_rdlvl_done;
wire mpr_rdlvl_start;
wire mpr_last_byte_done;
wire mpr_rnk_done;
wire mpr_end_if_reset;
wire mpr_rdlvl_err;
wire rdlvl_err;
wire prbs_rdlvl_start;
wire prbs_rdlvl_done;
reg prbs_rdlvl_done_r1;
wire prbs_last_byte_done;
wire prbs_rdlvl_prech_req;
wire prbs_pi_stg2_f_incdec;
wire prbs_pi_stg2_f_en;
wire [DQS_CNT_WIDTH:0] pi_stg2_prbs_rdlvl_cnt;
wire prbs_gen_clk_en;
wire rd_data_offset_cal_done;
wire fine_adjust_done;
wire [N_CTL_LANES-1:0] fine_adjust_lane_cnt;
wire ck_po_stg2_f_indec;
wire ck_po_stg2_f_en;
wire dqs_found_prech_req;
wire tempmon_pi_f_inc;
wire tempmon_pi_f_dec;
wire tempmon_sel_pi_incdec;
wire wrcal_sanity_chk;
wire wrcal_sanity_chk_done;
//*****************************************************************************
// Assertions to check correctness of parameter values
//*****************************************************************************
// synthesis translate_off
initial
begin
if (RANKS == 0) begin
$display ("Error: Invalid RANKS parameter. Must be 1 or greater");
$finish;
end
if (phy_ctl_full == 1'b1) begin
$display ("Error: Incorrect phy_ctl_full input value in 2:1 or 4:1 mode");
$finish;
end
end
// synthesis translate_on
//***************************************************************************
// Debug
//***************************************************************************
assign dbg_pi_phaselock_start = pi_phaselock_start;
assign dbg_pi_dqsfound_start = pi_dqs_found_start;
assign dbg_pi_dqsfound_done = pi_dqs_found_done;
assign dbg_wrcal_start = wrcal_start;
assign dbg_wrcal_done = wrcal_done;
// Unused for now - use these as needed to bring up lower level signals
assign dbg_calib_top = 256'd0;
// Write Level and write calibration debug observation ports
assign dbg_wrlvl_start = wrlvl_start;
assign dbg_wrlvl_done = wrlvl_done;
assign dbg_wrlvl_err = wrlvl_err;
// Read Level debug observation ports
assign dbg_rdlvl_start = {mpr_rdlvl_start, rdlvl_stg1_start};
assign dbg_rdlvl_done = {mpr_rdlvl_done, rdlvl_stg1_done};
assign dbg_rdlvl_err = {mpr_rdlvl_err, rdlvl_err};
assign dbg_oclkdelay_calib_done = oclkdelay_calib_done;
assign dbg_oclkdelay_calib_start = oclkdelay_calib_start;
//***************************************************************************
// Write leveling dependent signals
//***************************************************************************
assign wrcal_resume_w = (WRLVL == "ON") ? wrcal_pat_resume : 1'b0;
assign wrlvl_done_w = (WRLVL == "ON") ? wrlvl_done : 1'b1;
assign ck_addr_cmd_delay_done = (WRLVL == "ON") ? po_ck_addr_cmd_delay_done :
(po_ck_addr_cmd_delay_done
&& pi_fine_dly_dec_done) ;
generate
genvar i;
for (i = 0; i <= 2; i = i+1) begin : bankwise_signal
assign po_sel_stg2stg3[i] = ((~oclk_init_delay_done && ck_addr_cmd_delay_done &&
(DRAM_TYPE=="DDR3")) ? 1'b1 :
~oclkdelay_calib_done ? po_stg23_sel : 1'b0
) | dbg_po_f_stg23_sel_r;
assign po_stg2_c_incdec[i] = cmd_po_stg2_c_incdec ||
cmd_po_stg2_incdec_ddr2_c ||
dqs_wl_po_stg2_c_incdec;
assign po_en_stg2_c[i] = cmd_po_en_stg2_c ||
cmd_po_en_stg2_ddr2_c ||
dqs_wl_po_en_stg2_c;
assign po_stg2_f_incdec[i] = dqs_po_stg2_f_incdec ||
cmd_po_stg2_f_incdec ||
po_stg3_incdec ||
ck_po_stg2_f_indec ||
po_stg23_incdec ||
dbg_po_f_inc_r;
assign po_en_stg2_f[i] = dqs_po_en_stg2_f ||
cmd_po_en_stg2_f ||
po_en_stg3 ||
ck_po_stg2_f_en ||
po_en_stg23 ||
dbg_po_f_en_r;
end
endgenerate
assign pi_stg2_f_incdec = (dbg_pi_f_inc_r | rdlvl_pi_stg2_f_incdec | prbs_pi_stg2_f_incdec | tempmon_pi_f_inc_r);
assign pi_en_stg2_f = (dbg_pi_f_en_r | rdlvl_pi_stg2_f_en | prbs_pi_stg2_f_en | tempmon_pi_f_en_r);
assign idelay_ce = idelay_ce_r2;
assign idelay_inc = idelay_inc_r2;
assign po_counter_load_en = 1'b0;
// Added single stage flop to meet timing
always @(posedge clk)
init_calib_complete <= calib_complete;
assign calib_rd_data_offset_0 = rd_data_offset_ranks_mc_0;
assign calib_rd_data_offset_1 = rd_data_offset_ranks_mc_1;
assign calib_rd_data_offset_2 = rd_data_offset_ranks_mc_2;
//***************************************************************************
// Hard PHY signals
//***************************************************************************
assign pi_phase_locked_err = phase_locked_err;
assign pi_dqsfound_err = pi_dqs_found_err;
assign wrcal_err = wrcal_pat_err;
assign rst_tg_mc = 1'b0;
always @(posedge clk)
phy_if_reset <= #TCQ (phy_if_reset_w | mpr_end_if_reset |
reset_if | wrlvl_final_if_rst);
//***************************************************************************
// Phaser_IN inc dec control for debug
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
dbg_pi_f_inc_r <= #TCQ 1'b0;
dbg_pi_f_en_r <= #TCQ 1'b0;
dbg_sel_pi_incdec_r <= #TCQ 1'b0;
end else begin
dbg_pi_f_inc_r <= #TCQ dbg_pi_f_inc;
dbg_pi_f_en_r <= #TCQ (dbg_pi_f_inc | dbg_pi_f_dec);
dbg_sel_pi_incdec_r <= #TCQ dbg_sel_pi_incdec;
end
end
//***************************************************************************
// Phaser_OUT inc dec control for debug
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
dbg_po_f_inc_r <= #TCQ 1'b0;
dbg_po_f_stg23_sel_r<= #TCQ 1'b0;
dbg_po_f_en_r <= #TCQ 1'b0;
dbg_sel_po_incdec_r <= #TCQ 1'b0;
end else begin
dbg_po_f_inc_r <= #TCQ dbg_po_f_inc;
dbg_po_f_stg23_sel_r<= #TCQ dbg_po_f_stg23_sel;
dbg_po_f_en_r <= #TCQ (dbg_po_f_inc | dbg_po_f_dec);
dbg_sel_po_incdec_r <= #TCQ dbg_sel_po_incdec;
end
end
//***************************************************************************
// Phaser_IN inc dec control for temperature tracking
//***************************************************************************
always @(posedge clk) begin
if (rst) begin
tempmon_pi_f_inc_r <= #TCQ 1'b0;
tempmon_pi_f_en_r <= #TCQ 1'b0;
tempmon_sel_pi_incdec_r <= #TCQ 1'b0;
end else begin
tempmon_pi_f_inc_r <= #TCQ tempmon_pi_f_inc;
tempmon_pi_f_en_r <= #TCQ (tempmon_pi_f_inc | tempmon_pi_f_dec);
tempmon_sel_pi_incdec_r <= #TCQ tempmon_sel_pi_incdec;
end
end
//***************************************************************************
// OCLKDELAY calibration signals
//***************************************************************************
// Minimum of 5 'clk' cycles required between assertion of po_sel_stg2stg3
// and increment/decrement of Phaser_Out stage 3 delay
always @(posedge clk) begin
ck_addr_cmd_delay_done_r1 <= #TCQ ck_addr_cmd_delay_done;
ck_addr_cmd_delay_done_r2 <= #TCQ ck_addr_cmd_delay_done_r1;
ck_addr_cmd_delay_done_r3 <= #TCQ ck_addr_cmd_delay_done_r2;
ck_addr_cmd_delay_done_r4 <= #TCQ ck_addr_cmd_delay_done_r3;
ck_addr_cmd_delay_done_r5 <= #TCQ ck_addr_cmd_delay_done_r4;
ck_addr_cmd_delay_done_r6 <= #TCQ ck_addr_cmd_delay_done_r5;
end
assign oclk_init_delay_start = ck_addr_cmd_delay_done_r6 && (DRAM_TYPE=="DDR3"); // && (SIM_CAL_OPTION == "NONE")
//***************************************************************************
// MUX select logic to select current byte undergoing calibration
// Use DQS_CAL_MAP to determine the correlation between the physical
// byte numbering, and the byte numbering within the hard PHY
//***************************************************************************
generate
if (tCK > 2500) begin: gen_byte_sel_div2
always @(posedge clk) begin
if (rst) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done) begin
ctl_lane_sel <= #TCQ ctl_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~oclk_init_delay_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_calib_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_dqs_found_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~wrlvl_done_w) begin
if (SIM_CAL_OPTION != "FAST_CAL") begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b0;
end else begin
// Special case for FAST_CAL simulation only to ensure that
// calib_in_common isn't asserted too soon
if (!phy_ctl_rdy_dly) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b1;
end
end
end else if (~mpr_rdlvl_done) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~oclkdelay_calib_done) begin
byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~rdlvl_stg1_done && pi_calib_done) begin
if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~wrcal_done) begin
byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
byte_sel_cnt <= #TCQ dbg_byte_sel;
calib_in_common <= #TCQ 1'b0;
end else if (tempmon_sel_pi_incdec) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end
end
end else begin: gen_byte_sel_div1
always @(posedge clk) begin
if (rst) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done && (WRLVL !="ON")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~ck_addr_cmd_delay_done) begin
ctl_lane_sel <= #TCQ ctl_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~fine_adjust_done && rd_data_offset_cal_done) begin
if ((|pi_rst_stg1_cal) || (DRAM_TYPE == "DDR2")) begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ 'd0;
ctl_lane_sel <= #TCQ fine_adjust_lane_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~oclk_init_delay_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_calib_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~pi_dqs_found_done) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end else if (~wrlvl_done_w) begin
if (SIM_CAL_OPTION != "FAST_CAL") begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b0;
end else begin
// Special case for FAST_CAL simulation only to ensure that
// calib_in_common isn't asserted too soon
if (!phy_ctl_rdy_dly) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b0;
end else begin
byte_sel_cnt <= #TCQ po_stg2_wl_cnt;
calib_in_common <= #TCQ 1'b1;
end
end
end else if (~mpr_rdlvl_done) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~oclkdelay_calib_done) begin
byte_sel_cnt <= #TCQ oclkdelay_calib_cnt;
calib_in_common <= #TCQ 1'b0;
end else if ((~wrcal_done)&& (DRAM_TYPE == "DDR3")) begin
byte_sel_cnt <= #TCQ po_stg2_wrcal_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (~rdlvl_stg1_done && pi_calib_done) begin
if ((SIM_CAL_OPTION == "FAST_CAL") && rdlvl_assrt_common) begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b1;
end else begin
byte_sel_cnt <= #TCQ pi_stg2_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end
end else if (~prbs_rdlvl_done && rdlvl_stg1_done) begin
byte_sel_cnt <= #TCQ pi_stg2_prbs_rdlvl_cnt;
calib_in_common <= #TCQ 1'b0;
end else if (dbg_sel_pi_incdec_r | dbg_sel_po_incdec_r) begin
byte_sel_cnt <= #TCQ dbg_byte_sel;
calib_in_common <= #TCQ 1'b0;
end else if (tempmon_sel_pi_incdec) begin
byte_sel_cnt <= #TCQ 'd0;
calib_in_common <= #TCQ 1'b1;
end
end
end
endgenerate
always @(posedge clk) begin
if (rst || (calib_complete && ~ (dbg_sel_pi_incdec_r|dbg_sel_po_incdec_r|tempmon_sel_pi_incdec) )) begin
calib_sel <= #TCQ 6'b000100;
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~(dqs_po_dec_done && pi_fine_dly_dec_done)) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
if (~dqs_po_dec_done && (WRLVL != "ON"))
//if (~dqs_po_dec_done && ((SIM_CAL_OPTION == "FAST_CAL") ||(WRLVL != "ON")))
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
else
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~ck_addr_cmd_delay_done || (~fine_adjust_done && rd_data_offset_cal_done)) begin
if(WRLVL =="ON") begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ CTL_BYTE_LANE[(ctl_lane_sel*2)+:2];
calib_sel[5:3] <= #TCQ CTL_BANK;
if (|pi_rst_stg1_cal) begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
end else begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_inputs[1*CTL_BANK] <= #TCQ 1'b0;
end
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else begin // if (WRLVL =="ON")
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
if(~ck_addr_cmd_delay_done)
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
else
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b0}};
end // else: !if(WRLVL =="ON")
end else if (~oclk_init_delay_done) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if ((~wrlvl_done_w) && (SIM_CAL_OPTION == "FAST_CAL")) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (~rdlvl_stg1_done && (SIM_CAL_OPTION == "FAST_CAL") &&
rdlvl_assrt_common) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else if (tempmon_sel_pi_incdec) begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
end else begin
calib_sel[2] <= #TCQ 1'b0;
calib_sel[1:0] <= #TCQ DQS_BYTE_MAP[(byte_sel_cnt*8)+:2];
calib_sel[5:3] <= #TCQ DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3];
calib_zero_ctrl <= #TCQ {HIGHEST_BANK{1'b1}};
if (~calib_in_common) begin
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b1}};
calib_zero_inputs[(1*DQS_BYTE_MAP[((byte_sel_cnt*8)+4)+:3])] <= #TCQ 1'b0;
end else
calib_zero_inputs <= #TCQ {HIGHEST_BANK{1'b0}};
end
end
// Logic to reset IN_FIFO flags to account for the possibility that
// one or more PHASER_IN's have not correctly found the DQS preamble
// If this happens, we can still complete read leveling, but the # of
// words written into the IN_FIFO's may be an odd #, so that if the
// IN_FIFO is used in 2:1 mode ("8:4 mode"), there may be a "half" word
// of data left that can only be flushed out by reseting the IN_FIFO
always @(posedge clk) begin
rdlvl_stg1_done_r1 <= #TCQ rdlvl_stg1_done;
prbs_rdlvl_done_r1 <= #TCQ prbs_rdlvl_done;
reset_if_r1 <= #TCQ reset_if;
reset_if_r2 <= #TCQ reset_if_r1;
reset_if_r3 <= #TCQ reset_if_r2;
reset_if_r4 <= #TCQ reset_if_r3;
reset_if_r5 <= #TCQ reset_if_r4;
reset_if_r6 <= #TCQ reset_if_r5;
reset_if_r7 <= #TCQ reset_if_r6;
reset_if_r8 <= #TCQ reset_if_r7;
reset_if_r9 <= #TCQ reset_if_r8;
end
always @(posedge clk) begin
if (rst || reset_if_r9)
reset_if <= #TCQ 1'b0;
else if ((rdlvl_stg1_done && ~rdlvl_stg1_done_r1) ||
(prbs_rdlvl_done && ~prbs_rdlvl_done_r1))
reset_if <= #TCQ 1'b1;
end
assign phy_if_empty_def = 1'b0;
// DQ IDELAY tap inc and ce signals registered to control calib_in_common
// signal during read leveling in FAST_CAL mode. The calib_in_common signal
// is only asserted for IDELAY tap increments not Phaser_IN tap increments
// in FAST_CAL mode. For Phaser_IN tap increments the Phaser_IN counter load
// inputs are used.
always @(posedge clk) begin
if (rst) begin
idelay_ce_r1 <= #TCQ 1'b0;
idelay_ce_r2 <= #TCQ 1'b0;
idelay_inc_r1 <= #TCQ 1'b0;
idelay_inc_r2 <= #TCQ 1'b0;
end else begin
idelay_ce_r1 <= #TCQ idelay_ce_int;
idelay_ce_r2 <= #TCQ idelay_ce_r1;
idelay_inc_r1 <= #TCQ idelay_inc_int;
idelay_inc_r2 <= #TCQ idelay_inc_r1;
end
end
//***************************************************************************
// Delay all Outputs using Phaser_Out fine taps
//***************************************************************************
assign init_wrcal_complete = 1'b0;
//***************************************************************************
// PRBS Generator for Read Leveling Stage 1 - read window detection and
// DQS Centering
//***************************************************************************
// Assign initial seed (used for 1st data word in 8-burst sequence); use alternating 1/0 pat
assign prbs_seed = 64'h9966aa559966aa55;
// A single PRBS generator
// writes 64-bits every 4to1 fabric clock cycle and
// write 32-bits every 2to1 fabric clock cycle
mig_7series_v1_9_ddr_prbs_gen #
(
.TCQ (TCQ),
.PRBS_WIDTH (2*8*nCK_PER_CLK)
)
u_ddr_prbs_gen
(
.clk_i (clk),
.clk_en_i (prbs_gen_clk_en),
.rst_i (rst),
.prbs_o (prbs_out),
.prbs_seed_i (prbs_seed),
.phy_if_empty (phy_if_empty),
.prbs_rdlvl_start (prbs_rdlvl_start)
);
// PRBS data slice that decides the Rise0, Fall0, Rise1, Fall1,
// Rise2, Fall2, Rise3, Fall3 data
generate
if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
assign prbs_rise0 = prbs_out[7:0];
assign prbs_fall0 = prbs_out[15:8];
assign prbs_rise1 = prbs_out[23:16];
assign prbs_fall1 = prbs_out[31:24];
assign prbs_rise2 = prbs_out[39:32];
assign prbs_fall2 = prbs_out[47:40];
assign prbs_rise3 = prbs_out[55:48];
assign prbs_fall3 = prbs_out[63:56];
assign prbs_o = {prbs_fall3, prbs_rise3, prbs_fall2, prbs_rise2,
prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};
end else begin :gen_ck_per_clk2
assign prbs_rise0 = prbs_out[7:0];
assign prbs_fall0 = prbs_out[15:8];
assign prbs_rise1 = prbs_out[23:16];
assign prbs_fall1 = prbs_out[31:24];
assign prbs_o = {prbs_fall1, prbs_rise1, prbs_fall0, prbs_rise0};
end
endgenerate
//***************************************************************************
// Initialization / Master PHY state logic (overall control during memory
// init, timing leveling)
//***************************************************************************
mig_7series_v1_9_ddr_phy_init #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DRAM_TYPE (DRAM_TYPE),
.PRBS_WIDTH (PRBS_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.CA_MIRROR (CA_MIRROR),
.COL_WIDTH (COL_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.CS_WIDTH (CS_WIDTH),
.RANKS (RANKS),
.CKE_WIDTH (CKE_WIDTH),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.AL (AL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.nCL (nCL),
.nCWL (nCWL),
.tRFC (tRFC),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.WRLVL (WRLVL),
.USE_ODT_PORT (USE_ODT_PORT),
.DDR2_DQSN_ENABLE(DDR2_DQSN_ENABLE),
.nSLOTS (nSLOTS),
.SIM_INIT_OPTION (SIM_INIT_OPTION),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.CKE_ODT_AUX (CKE_ODT_AUX),
.PRE_REV3ES (PRE_REV3ES),
.TEST_AL (TEST_AL)
)
u_ddr_phy_init
(
.clk (clk),
.rst (rst),
.prbs_o (prbs_o),
.ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
.delay_incdec_done (ck_addr_cmd_delay_done & oclk_init_delay_done),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_phaselock_start (pi_phaselock_start),
.pi_phase_locked_err (phase_locked_err),
.pi_calib_done (pi_calib_done),
.phy_if_empty (phy_if_empty),
.phy_ctl_ready (phy_ctl_ready),
.phy_ctl_full (phy_ctl_full),
.phy_cmd_full (phy_cmd_full),
.phy_data_full (phy_data_full),
.calib_ctl_wren (calib_ctl_wren),
.calib_cmd_wren (calib_cmd_wren),
.calib_wrdata_en (calib_wrdata_en),
.calib_seq (calib_seq),
.calib_aux_out (calib_aux_out),
.calib_rank_cnt (calib_rank_cnt),
.calib_cas_slot (calib_cas_slot),
.calib_data_offset_0 (calib_data_offset_0),
.calib_data_offset_1 (calib_data_offset_1),
.calib_data_offset_2 (calib_data_offset_2),
.calib_cmd (calib_cmd),
.calib_cke (calib_cke),
.calib_odt (calib_odt),
.write_calib (write_calib),
.read_calib (read_calib),
.wrlvl_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.wrlvl_byte_done (wrlvl_byte_done),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrlvl_final (wrlvl_final),
.wrlvl_final_if_rst (wrlvl_final_if_rst),
.oclkdelay_calib_start (oclkdelay_calib_start),
.oclkdelay_calib_done (oclkdelay_calib_done),
.oclk_prech_req (oclk_prech_req),
.oclk_calib_resume (oclk_calib_resume),
.done_dqs_tap_inc (done_dqs_tap_inc),
.wl_sm_start (wl_sm_start),
.wr_lvl_start (wrlvl_start),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
.mpr_rdlvl_done (mpr_rdlvl_done),
.mpr_rdlvl_start (mpr_rdlvl_start),
.mpr_last_byte_done (mpr_last_byte_done),
.mpr_rnk_done (mpr_rnk_done),
.mpr_end_if_reset (mpr_end_if_reset),
.rdlvl_stg1_done (rdlvl_stg1_done),
.rdlvl_stg1_rank_done (rdlvl_stg1_rank_done),
.rdlvl_stg1_start (rdlvl_stg1_start),
.rdlvl_prech_req (rdlvl_prech_req),
.rdlvl_last_byte_done (rdlvl_last_byte_done),
.prbs_rdlvl_start (prbs_rdlvl_start),
.prbs_rdlvl_done (prbs_rdlvl_done),
.prbs_last_byte_done (prbs_last_byte_done),
.prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
.prbs_gen_clk_en (prbs_gen_clk_en),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_rank_done(pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.detect_pi_found_dqs (detect_pi_found_dqs),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.rd_data_offset_ranks_0(rd_data_offset_ranks_0),
.rd_data_offset_ranks_1(rd_data_offset_ranks_1),
.rd_data_offset_ranks_2(rd_data_offset_ranks_2),
.wrcal_start (wrcal_start),
.wrcal_rd_wait (wrcal_rd_wait),
.wrcal_prech_req (wrcal_prech_req),
.wrcal_resume (wrcal_resume_w),
.wrcal_read_req (wrcal_read_req),
.wrcal_act_req (wrcal_act_req),
.wrcal_sanity_chk (wrcal_sanity_chk),
.temp_wrcal_done (temp_wrcal_done),
.wrcal_sanity_chk_done (wrcal_sanity_chk_done),
.tg_timer_done (tg_timer_done),
.no_rst_tg_mc (no_rst_tg_mc),
.wrcal_done (wrcal_done),
.prech_done (prech_done),
.calib_writes (calib_writes),
.init_calib_complete (calib_complete),
.phy_address (phy_address),
.phy_bank (phy_bank),
.phy_cas_n (phy_cas_n),
.phy_cs_n (phy_cs_n),
.phy_ras_n (phy_ras_n),
.phy_reset_n (phy_reset_n),
.phy_we_n (phy_we_n),
.phy_wrdata (phy_wrdata),
.phy_rddata_en (phy_rddata_en),
.phy_rddata_valid (phy_rddata_valid),
.dbg_phy_init (dbg_phy_init)
);
//*****************************************************************
// Write Calibration
//*****************************************************************
mig_7series_v1_9_ddr_phy_wrcal #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.SIM_CAL_OPTION (SIM_CAL_OPTION)
)
u_ddr_phy_wrcal
(
.clk (clk),
.rst (rst),
.wrcal_start (wrcal_start),
.wrcal_rd_wait (wrcal_rd_wait),
.wrcal_sanity_chk (wrcal_sanity_chk),
.dqsfound_retry_done (pi_dqs_found_done),
.dqsfound_retry (dqsfound_retry),
.wrcal_read_req (wrcal_read_req),
.wrcal_act_req (wrcal_act_req),
.phy_rddata_en (phy_rddata_en),
.wrcal_done (wrcal_done),
.wrcal_pat_err (wrcal_pat_err),
.wrcal_prech_req (wrcal_prech_req),
.temp_wrcal_done (temp_wrcal_done),
.wrcal_sanity_chk_done (wrcal_sanity_chk_done),
.prech_done (prech_done),
.rd_data (phy_rddata),
.wrcal_pat_resume (wrcal_pat_resume),
.po_stg2_wrcal_cnt (po_stg2_wrcal_cnt),
.phy_if_reset (phy_if_reset_w),
.wl_po_coarse_cnt (wl_po_coarse_cnt),
.wl_po_fine_cnt (wl_po_fine_cnt),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrlvl_byte_done (wrlvl_byte_done),
.early1_data (early1_data),
.early2_data (early2_data),
.idelay_ld (idelay_ld),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt)
);
//***************************************************************************
// Write-leveling calibration logic
//***************************************************************************
generate
if (WRLVL == "ON") begin: mb_wrlvl_inst
mig_7series_v1_9_ddr_phy_wrlvl #
(
.TCQ (TCQ),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.CLK_PERIOD (CLK_PERIOD),
.nCK_PER_CLK (nCK_PER_CLK),
.SIM_CAL_OPTION (SIM_CAL_OPTION)
)
u_ddr_phy_wrlvl
(
.clk (clk),
.rst (rst),
.phy_ctl_ready (phy_ctl_ready),
.wr_level_start (wrlvl_start),
.wl_sm_start (wl_sm_start),
.wrlvl_byte_redo (wrlvl_byte_redo),
.wrcal_cnt (po_stg2_wrcal_cnt),
.early1_data (early1_data),
.early2_data (early2_data),
.wrlvl_final (wrlvl_final),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt),
.wrlvl_byte_done (wrlvl_byte_done),
.oclkdelay_calib_done (oclkdelay_calib_done),
.rd_data_rise0 (phy_rddata[DQ_WIDTH-1:0]),
.dqs_po_dec_done (dqs_po_dec_done),
.phy_ctl_rdy_dly (phy_ctl_rdy_dly),
.wr_level_done (wrlvl_done),
.wrlvl_rank_done (wrlvl_rank_done),
.done_dqs_tap_inc (done_dqs_tap_inc),
.dqs_po_stg2_f_incdec (dqs_po_stg2_f_incdec),
.dqs_po_en_stg2_f (dqs_po_en_stg2_f),
.dqs_wl_po_stg2_c_incdec (dqs_wl_po_stg2_c_incdec),
.dqs_wl_po_en_stg2_c (dqs_wl_po_en_stg2_c),
.po_counter_read_val (po_counter_read_val),
.po_stg2_wl_cnt (po_stg2_wl_cnt),
.wrlvl_err (wrlvl_err),
.wl_po_coarse_cnt (wl_po_coarse_cnt),
.wl_po_fine_cnt (wl_po_fine_cnt),
.dbg_wl_tap_cnt (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_dqs_count (),
.dbg_wl_state (),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl)
);
mig_7series_v1_9_ddr_phy_ck_addr_cmd_delay #
(
.TCQ (TCQ),
.tCK (tCK),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.N_CTL_LANES (N_CTL_LANES),
.SIM_CAL_OPTION(SIM_CAL_OPTION)
)
u_ddr_phy_ck_addr_cmd_delay
(
.clk (clk),
.rst (rst),
.cmd_delay_start (dqs_po_dec_done & pi_fine_dly_dec_done),
.ctl_lane_cnt (ctl_lane_cnt),
.po_stg2_f_incdec (cmd_po_stg2_f_incdec),
.po_en_stg2_f (cmd_po_en_stg2_f),
.po_stg2_c_incdec (cmd_po_stg2_c_incdec),
.po_en_stg2_c (cmd_po_en_stg2_c),
.po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done)
);
assign cmd_po_stg2_incdec_ddr2_c = 1'b0;
assign cmd_po_en_stg2_ddr2_c = 1'b0;
end else begin: mb_wrlvl_off
mig_7series_v1_9_ddr_phy_wrlvl_off_delay #
(
.TCQ (TCQ),
.tCK (tCK),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.PO_INITIAL_DLY(60),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.N_CTL_LANES (N_CTL_LANES)
)
u_phy_wrlvl_off_delay
(
.clk (clk),
.rst (rst),
.pi_fine_dly_dec_done (pi_fine_dly_dec_done),
.cmd_delay_start (phy_ctl_ready),
.ctl_lane_cnt (ctl_lane_cnt),
.po_s2_incdec_f (cmd_po_stg2_f_incdec),
.po_en_s2_f (cmd_po_en_stg2_f),
.po_s2_incdec_c (cmd_po_stg2_incdec_ddr2_c),
.po_en_s2_c (cmd_po_en_stg2_ddr2_c),
.po_ck_addr_cmd_delay_done (po_ck_addr_cmd_delay_done),
.po_dec_done (dqs_po_dec_done),
.phy_ctl_rdy_dly (phy_ctl_rdy_dly)
);
assign wrlvl_done = 1'b1;
assign wrlvl_err = 1'b0;
assign dqs_po_stg2_f_incdec = 1'b0;
assign dqs_po_en_stg2_f = 1'b0;
assign dqs_wl_po_en_stg2_c = 1'b0;
assign cmd_po_stg2_c_incdec = 1'b0;
assign dqs_wl_po_stg2_c_incdec = 1'b0;
assign cmd_po_en_stg2_c = 1'b0;
end
endgenerate
generate
if(WRLVL == "ON") begin: oclk_calib
mig_7series_v1_9_ddr_phy_oclkdelay_cal #
(
.TCQ (TCQ),
.tCK (tCK),
.nCK_PER_CLK (nCK_PER_CLK),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.OCAL_EN (OCAL_EN)
)
u_ddr_phy_oclkdelay_cal
(
.clk (clk),
.rst (rst),
.oclk_init_delay_start (oclk_init_delay_start),
.oclkdelay_calib_start (oclkdelay_calib_start),
.oclkdelay_init_val (oclkdelay_init_val),
.phy_rddata_en (phy_rddata_en),
.rd_data (phy_rddata),
.prech_done (prech_done),
.wl_po_fine_cnt (wl_po_fine_cnt),
.po_stg3_incdec (po_stg3_incdec),
.po_en_stg3 (po_en_stg3),
.po_stg23_sel (po_stg23_sel),
.po_stg23_incdec (po_stg23_incdec),
.po_en_stg23 (po_en_stg23),
.wrlvl_final (wrlvl_final),
.oclk_prech_req (oclk_prech_req),
.oclk_calib_resume (oclk_calib_resume),
.oclk_init_delay_done (oclk_init_delay_done),
.oclkdelay_calib_cnt (oclkdelay_calib_cnt),
.oclkdelay_calib_done (oclkdelay_calib_done),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data)
);
end else begin : oclk_calib_disabled
assign wrlvl_final = 'b0;
assign po_stg3_incdec = 'b0;
assign po_en_stg3 = 'b0;
assign po_stg23_sel = 'b0;
assign po_stg23_incdec = 'b0;
assign po_en_stg23 = 'b0;
assign oclk_init_delay_done = 1'b1;
assign oclkdelay_calib_cnt = 'b0;
assign oclk_prech_req = 'b0;
assign oclk_calib_resume = 'b0;
assign oclkdelay_calib_done = 1'b1;
end
endgenerate
//***************************************************************************
// Read data-offset calibration required for Phaser_In
//***************************************************************************
generate
if(DQSFOUND_CAL == "RIGHT") begin: dqsfind_calib_right
mig_7series_v1_9_ddr_phy_dqs_found_cal #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.nCL (nCL),
.AL (AL),
.nCWL (nCWL),
//.RANKS (RANKS),
.RANKS (1),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.REG_CTRL (REG_CTRL),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DRAM_TYPE (DRAM_TYPE),
.NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
.N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
.HIGHEST_LANE (HIGHEST_LANE),
.HIGHEST_BANK (HIGHEST_BANK),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4)
)
u_ddr_phy_dqs_found_cal
(
.clk (clk),
.rst (rst),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.detect_pi_found_dqs (detect_pi_found_dqs),
.prech_done (prech_done),
.pi_dqs_found_lanes (pi_dqs_found_lanes),
.pi_rst_stg1_cal (pi_rst_stg1_cal),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.pi_dqs_found_rank_done (pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.dqsfound_retry_done (dqsfound_retry_done),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_err (pi_dqs_found_err),
.rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
.rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
.rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
.rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
.rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
.rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
.po_counter_read_val (po_counter_read_val),
.rd_data_offset_cal_done (rd_data_offset_cal_done),
.fine_adjust_done (fine_adjust_done),
.fine_adjust_lane_cnt (fine_adjust_lane_cnt),
.ck_po_stg2_f_indec (ck_po_stg2_f_indec),
.ck_po_stg2_f_en (ck_po_stg2_f_en),
.dbg_dqs_found_cal (dbg_dqs_found_cal)
);
end else begin: dqsfind_calib_left
mig_7series_v1_9_ddr_phy_dqs_found_cal_hr #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.nCL (nCL),
.AL (AL),
.nCWL (nCWL),
//.RANKS (RANKS),
.RANKS (1),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.REG_CTRL (REG_CTRL),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DRAM_TYPE (DRAM_TYPE),
.NUM_DQSFOUND_CAL (NUM_DQSFOUND_CAL),
.N_CTL_LANES (DQS_FOUND_N_CTL_LANES),
.HIGHEST_LANE (HIGHEST_LANE),
.HIGHEST_BANK (HIGHEST_BANK),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4)
)
u_ddr_phy_dqs_found_cal_hr
(
.clk (clk),
.rst (rst),
.pi_dqs_found_start (pi_dqs_found_start),
.dqsfound_retry (dqsfound_retry),
.detect_pi_found_dqs (detect_pi_found_dqs),
.prech_done (prech_done),
.pi_dqs_found_lanes (pi_dqs_found_lanes),
.pi_rst_stg1_cal (pi_rst_stg1_cal),
.rd_data_offset_0 (rd_data_offset_0),
.rd_data_offset_1 (rd_data_offset_1),
.rd_data_offset_2 (rd_data_offset_2),
.pi_dqs_found_rank_done (pi_dqs_found_rank_done),
.pi_dqs_found_done (pi_dqs_found_done),
.dqsfound_retry_done (dqsfound_retry_done),
.dqs_found_prech_req (dqs_found_prech_req),
.pi_dqs_found_err (pi_dqs_found_err),
.rd_data_offset_ranks_0 (rd_data_offset_ranks_0),
.rd_data_offset_ranks_1 (rd_data_offset_ranks_1),
.rd_data_offset_ranks_2 (rd_data_offset_ranks_2),
.rd_data_offset_ranks_mc_0 (rd_data_offset_ranks_mc_0),
.rd_data_offset_ranks_mc_1 (rd_data_offset_ranks_mc_1),
.rd_data_offset_ranks_mc_2 (rd_data_offset_ranks_mc_2),
.po_counter_read_val (po_counter_read_val),
.rd_data_offset_cal_done (rd_data_offset_cal_done),
.fine_adjust_done (fine_adjust_done),
.fine_adjust_lane_cnt (fine_adjust_lane_cnt),
.ck_po_stg2_f_indec (ck_po_stg2_f_indec),
.ck_po_stg2_f_en (ck_po_stg2_f_en),
.dbg_dqs_found_cal (dbg_dqs_found_cal)
);
end
endgenerate
//***************************************************************************
// Read-leveling calibration logic
//***************************************************************************
mig_7series_v1_9_ddr_phy_rdlvl #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.PER_BIT_DESKEW (PER_BIT_DESKEW),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.DEBUG_PORT (DEBUG_PORT),
.DRAM_TYPE (DRAM_TYPE),
.OCAL_EN (OCAL_EN)
)
u_ddr_phy_rdlvl
(
.clk (clk),
.rst (rst),
.mpr_rdlvl_done (mpr_rdlvl_done),
.mpr_rdlvl_start (mpr_rdlvl_start),
.mpr_last_byte_done (mpr_last_byte_done),
.mpr_rnk_done (mpr_rnk_done),
.rdlvl_stg1_start (rdlvl_stg1_start),
.rdlvl_stg1_done (rdlvl_stg1_done),
.rdlvl_stg1_rnk_done (rdlvl_stg1_rank_done),
.rdlvl_stg1_err (rdlvl_stg1_err),
.mpr_rdlvl_err (mpr_rdlvl_err),
.rdlvl_err (rdlvl_err),
.rdlvl_prech_req (rdlvl_prech_req),
.rdlvl_last_byte_done (rdlvl_last_byte_done),
.rdlvl_assrt_common (rdlvl_assrt_common),
.prech_done (prech_done),
.phy_if_empty (phy_if_empty),
.idelaye2_init_val (idelaye2_init_val),
.rd_data (phy_rddata),
.pi_en_stg2_f (rdlvl_pi_stg2_f_en),
.pi_stg2_f_incdec (rdlvl_pi_stg2_f_incdec),
.pi_stg2_load (pi_stg2_load),
.pi_stg2_reg_l (pi_stg2_reg_l),
.dqs_po_dec_done (dqs_po_dec_done),
.pi_counter_read_val (pi_counter_read_val),
.pi_fine_dly_dec_done (pi_fine_dly_dec_done),
.idelay_ce (idelay_ce_int),
.idelay_inc (idelay_inc_int),
.idelay_ld (idelay_ld),
.wrcal_cnt (po_stg2_wrcal_cnt),
.pi_stg2_rdlvl_cnt (pi_stg2_rdlvl_cnt),
.dlyval_dq (dlyval_dq),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_phy_rdlvl (dbg_phy_rdlvl)
);
generate
if(DRAM_TYPE == "DDR3") begin:ddr_phy_prbs_rdlvl_gen
mig_7series_v1_9_ddr_phy_prbs_rdlvl #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.RANKS (1),
.SIM_CAL_OPTION (SIM_CAL_OPTION),
.PRBS_WIDTH (PRBS_WIDTH)
)
u_ddr_phy_prbs_rdlvl
(
.clk (clk),
.rst (rst),
.prbs_rdlvl_start (prbs_rdlvl_start),
.prbs_rdlvl_done (prbs_rdlvl_done),
.prbs_last_byte_done (prbs_last_byte_done),
.prbs_rdlvl_prech_req (prbs_rdlvl_prech_req),
.prech_done (prech_done),
.phy_if_empty (phy_if_empty),
.rd_data (phy_rddata),
.compare_data (prbs_o),
.pi_counter_read_val (pi_counter_read_val),
.pi_en_stg2_f (prbs_pi_stg2_f_en),
.pi_stg2_f_incdec (prbs_pi_stg2_f_incdec),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.pi_stg2_prbs_rdlvl_cnt (pi_stg2_prbs_rdlvl_cnt)
);
end else begin:ddr_phy_prbs_rdlvl_off
assign prbs_rdlvl_done = rdlvl_stg1_done ;
assign prbs_last_byte_done = rdlvl_stg1_rank_done ;
assign prbs_rdlvl_prech_req = 1'b0 ;
assign prbs_pi_stg2_f_en = 1'b0 ;
assign prbs_pi_stg2_f_incdec = 1'b0 ;
assign pi_stg2_prbs_rdlvl_cnt = 'b0 ;
end
endgenerate
//***************************************************************************
// Temperature induced PI tap adjustment logic
//***************************************************************************
mig_7series_v1_9_ddr_phy_tempmon #
(
.TCQ (TCQ)
)
ddr_phy_tempmon_0
(
.rst (rst),
.clk (clk),
.calib_complete (calib_complete),
.tempmon_pi_f_inc (tempmon_pi_f_inc),
.tempmon_pi_f_dec (tempmon_pi_f_dec),
.tempmon_sel_pi_incdec (tempmon_sel_pi_incdec),
.device_temp (device_temp),
.tempmon_sample_en (tempmon_sample_en)
);
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Ltac f_equiv' := repeat (repeat f_equiv; try intros ? ? ?; auto).
Module NStrongRecProp (Import N : NAxiomsRecSig').
Include NSubProp N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows defining a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0; f_equiv'.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt; f_equiv'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
f_equiv.
rewrite recursion_succ; f_equiv'.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ; f_equiv'.
rewrite strong_rec0_0. reflexivity.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
f_equiv.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Arguments strong_rec [A] a f n.
End NStrongRecProp.
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Ltac f_equiv' := repeat (repeat f_equiv; try intros ? ? ?; auto).
Module NStrongRecProp (Import N : NAxiomsRecSig').
Include NSubProp N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows defining a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0; f_equiv'.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt; f_equiv'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
f_equiv.
rewrite recursion_succ; f_equiv'.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ; f_equiv'.
rewrite strong_rec0_0. reflexivity.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
f_equiv.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Arguments strong_rec [A] a f n.
End NStrongRecProp.
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_engine_selector.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Searches for read and write requests.
// PCIe Endpoint core.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
// Additional Comments:
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_engine_selector
#(
parameter C_NUM_CHNL = 4'd12
)
(
input CLK,
input RST,
input [C_NUM_CHNL-1:0] REQ_ALL, // Write requests
output REQ, // Write request
output [3:0] CHNL// Write channel
);
reg [3:0] rReqChnl=0, _rReqChnl=0;
reg [3:0] rReqChnlNext=0, _rReqChnlNext=0;
reg rReqChnlsSame=0, _rReqChnlsSame=0;
reg [3:0] rChnlNext=0, _rChnlNext=0;
reg [3:0] rChnlNextNext=0, _rChnlNextNext=0;
reg rChnlNextDfrnt=0, _rChnlNextDfrnt=0;
reg rChnlNextNextOn=0, _rChnlNextNextOn=0;
wire wChnlNextNextOn;
reg rReq=0, _rReq=0;
wire wReq;// = (REQ_ALL>>(rReqChnl));
reg rReqChnlNextUpdated=0, _rReqChnlNextUpdated=0;
assign wReq = REQ_ALL[rReqChnl];
assign wChnlNextNextOn = REQ_ALL[rChnlNextNext];
assign REQ = rReq;
assign CHNL = rReqChnl;
// Search for the next request so that we can move onto it immediately after
// the current channel has released its request.
always @ (posedge CLK) begin
rReq <= #1 (RST ? 1'd0 : _rReq);
rReqChnl <= #1 (RST ? 4'd0 : _rReqChnl);
rReqChnlNext <= #1 (RST ? 4'd0 : _rReqChnlNext);
rChnlNext <= #1 (RST ? 4'd0 : _rChnlNext);
rChnlNextNext <= #1 (RST ? 4'd0 : _rChnlNextNext);
rChnlNextDfrnt <= #1 (RST ? 1'd0 : _rChnlNextDfrnt);
rChnlNextNextOn <= #1 (RST ? 1'd0 : _rChnlNextNextOn);
rReqChnlsSame <= #1 (RST ? 1'd0 : _rReqChnlsSame);
rReqChnlNextUpdated <= #1 (RST ? 1'd1 : _rReqChnlNextUpdated);
end
always @ (*) begin
// Go through each channel (RR), looking for requests
_rChnlNextNextOn = wChnlNextNextOn;
_rChnlNext = rChnlNextNext;
_rChnlNextNext = (rChnlNextNext == C_NUM_CHNL - 1 ? 4'd0 : rChnlNextNext + 1'd1);
_rChnlNextDfrnt = (rChnlNextNext != rReqChnl);
_rReqChnlsSame = (rReqChnlNext == rReqChnl);
// Save ready channel if it is not the same channel we're currently on
if (rChnlNextNextOn & rChnlNextDfrnt & rReqChnlsSame & !rReqChnlNextUpdated) begin
_rReqChnlNextUpdated = 1;
_rReqChnlNext = rChnlNext;
end
else begin
_rReqChnlNextUpdated = 0;
_rReqChnlNext = rReqChnlNext;
end
// Assign the new channel
_rReq = wReq;
_rReqChnl = (!rReq ? rReqChnlNext : rReqChnl);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef struct packed {
bit b9;
byte b1;
bit b0;
} pack_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
pack_t in;
always @* in = crc[9:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
pack_t out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out),
// Inputs
.in (in));
// Aggregate outputs into a single result vector
wire [63:0] result = {54'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x in=%x result=%x\n",$time, cyc, crc, in, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h99c434d9b08c2a8a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input pack_t in,
output pack_t out);
always @* begin
out = in;
out.b1 = in.b1 + 1;
out.b0 = 1'b1;
end
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fir_shift_reg_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 32;
parameter AWIDTH = 4;
parameter MEM_SIZE = 11;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./fir_shift_reg_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module fir_shift_reg(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd11;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
fir_shift_reg_ram fir_shift_reg_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fir_shift_reg_ram (addr0, ce0, d0, we0, q0, clk);
parameter DWIDTH = 32;
parameter AWIDTH = 4;
parameter MEM_SIZE = 11;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./fir_shift_reg_ram.dat", ram);
end
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
endmodule
`timescale 1 ns / 1 ps
module fir_shift_reg(
reset,
clk,
address0,
ce0,
we0,
d0,
q0);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd11;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
fir_shift_reg_ram fir_shift_reg_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ));
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: channel_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Represents a RIFFA channel. Contains a RX port and a
// TX port.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module channel_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_32 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's definitions ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// Defines for the OR1200 core ////
//// ////
//// To Do: ////
//// - add parameters that are missing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_defines.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Defines added, bugs fixed.
//
// Dump VCD
//
//`define OR1200_VCD_DUMP
//
// Generate debug messages during simulation
//
//`define OR1200_VERBOSE
// `define OR1200_ASIC
////////////////////////////////////////////////////////
//
// Typical configuration for an ASIC
//
`ifdef OR1200_ASIC
//
// Target ASIC memories
//
//`define OR1200_ARTISAN_SSP
//`define OR1200_ARTISAN_SDP
//`define OR1200_ARTISAN_STP
`define OR1200_VIRTUALSILICON_SSP
//`define OR1200_VIRTUALSILICON_STP_T1
//`define OR1200_VIRTUALSILICON_STP_T2
//
// Do not implement Data cache
//
//`define OR1200_NO_DC
//
// Do not implement Insn cache
//
//`define OR1200_NO_IC
//
// Do not implement Data MMU
//
//`define OR1200_NO_DMMU
//
// Do not implement Insn MMU
//
//`define OR1200_NO_IMMU
//
// Select between ASIC optimized and generic multiplier
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
//
// Size/type of insn/data cache if implemented
//
// `define OR1200_IC_1W_512B
// `define OR1200_IC_1W_4KB
`define OR1200_IC_1W_8KB
// `define OR1200_DC_1W_4KB
`define OR1200_DC_1W_8KB
`else
/////////////////////////////////////////////////////////
//
// Typical configuration for an FPGA
//
//
// Target FPGA memories
//
`define OR1200_ALTERA_LPM
//`define OR1200_XILINX_RAMB16
//`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
// Generic models should infer RAM blocks at synthesis time (not only effects
// single port ram.)
//`define OR1200_GENERIC
//
// Do not implement Data cache
//
//`define OR1200_NO_DC
//
// Do not implement Insn cache
//
//`define OR1200_NO_IC
//
// Do not implement Data MMU
//
//`define OR1200_NO_DMMU
//
// Do not implement Insn MMU
//
//`define OR1200_NO_IMMU
//
// Select between ASIC and generic multiplier
//
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
//
// Size/type of insn/data cache if implemented
// (consider available FPGA memory resources)
//
//`define OR1200_IC_1W_512B
`define OR1200_IC_1W_4KB
//`define OR1200_IC_1W_8KB
//`define OR1200_IC_1W_16KB
//`define OR1200_IC_1W_32KB
`define OR1200_DC_1W_4KB
//`define OR1200_DC_1W_8KB
//`define OR1200_DC_1W_16KB
//`define OR1200_DC_1W_32KB
`endif
//////////////////////////////////////////////////////////
//
// Do not change below unless you know what you are doing
//
//
// Reset active low
//
//`define OR1200_RST_ACT_LOW
//
// Enable RAM BIST
//
// At the moment this only works for Virtual Silicon
// single port RAMs. For other RAMs it has not effect.
// Special wrapper for VS RAMs needs to be provided
// with scan flops to facilitate bist scan.
//
//`define OR1200_BIST
//
// Register OR1200 WISHBONE outputs
// (must be defined/enabled)
//
`define OR1200_REGISTERED_OUTPUTS
//
// Register OR1200 WISHBONE inputs
//
// (must be undefined/disabled)
//
//`define OR1200_REGISTERED_INPUTS
//
// Disable bursts if they are not supported by the
// memory subsystem (only affect cache line fill)
//
//`define OR1200_NO_BURSTS
//
//
// WISHBONE retry counter range
//
// 2^value range for retry counter. Retry counter
// is activated whenever *wb_rty_i is asserted and
// until retry counter expires, corresponding
// WISHBONE interface is deactivated.
//
// To disable retry counters and *wb_rty_i all together,
// undefine this macro.
//
//`define OR1200_WB_RETRY 7
//
// WISHBONE Consecutive Address Burst
//
// This was used prior to WISHBONE B3 specification
// to identify bursts. It is no longer needed but
// remains enabled for compatibility with old designs.
//
// To remove *wb_cab_o ports undefine this macro.
//
//`define OR1200_WB_CAB
//
// WISHBONE B3 compatible interface
//
// This follows the WISHBONE B3 specification.
// It is not enabled by default because most
// designs still don't use WB b3.
//
// To enable *wb_cti_o/*wb_bte_o ports,
// define this macro.
//
`define OR1200_WB_B3
//
// LOG all WISHBONE accesses
//
`define OR1200_LOG_WB_ACCESS
//
// Enable additional synthesis directives if using
// _Synopsys_ synthesis tool
//
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
//
// Enables default statement in some case blocks
// and disables Synopsys synthesis directive full_case
//
// By default it is enabled. When disabled it
// can increase clock frequency.
//
`define OR1200_CASE_DEFAULT
//
// Operand width / register file address width
//
// (DO NOT CHANGE)
//
`define OR1200_OPERAND_WIDTH 32
`define OR1200_REGFILE_ADDR_WIDTH 5
//
// l.add/l.addi/l.and and optional l.addc/l.addic
// also set (compare) flag when result of their
// operation equals zero
//
// At the time of writing this, default or32
// C/C++ compiler doesn't generate code that
// would benefit from this optimization.
//
// By default this optimization is disabled to
// save area.
//
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
//
// Implement l.addc/l.addic instructions
//
// By default implementation of l.addc/l.addic
// instructions is enabled in case you need them.
// If you don't use them, then disable implementation
// to save area.
//
//`define OR1200_IMPL_ADDC
//
// Implement l.sub instruction
//
// By default implementation of l.sub instructions
// is enabled to be compliant with the simulator.
// If you don't use carry bit, then disable
// implementation to save area.
//
`define OR1200_IMPL_SUB
//
// Implement carry bit SR[CY]
//
//
// By default implementation of SR[CY] is enabled
// to be compliant with the simulator. However SR[CY]
// is explicitly only used by l.addc/l.addic/l.sub
// instructions and if these three insns are not
// implemented there is not much point having SR[CY].
//
//`define OR1200_IMPL_CY
//
// Implement carry bit SR[OV]
//
// Compiler doesn't use this, but other code may like
// to.
//
//`define OR1200_IMPL_OV
//
// Implement carry bit SR[OVE]
//
// Overflow interrupt indicator. When enabled, SR[OV] flag
// does not remain asserted after exception.
//
//`define OR1200_IMPL_OVE
//
// Implement rotate in the ALU
//
// At the time of writing this, or32
// C/C++ compiler doesn't generate rotate
// instructions. However or32 assembler
// can assemble code that uses rotate insn.
// This means that rotate instructions
// must be used manually inserted.
//
// By default implementation of rotate
// is disabled to save area and increase
// clock frequency.
//
//`define OR1200_IMPL_ALU_ROTATE
//
// Type of ALU compare to implement
//
// Try either one to find what yields
// higher clock frequencyin your case.
//
//`define OR1200_IMPL_ALU_COMP1
`define OR1200_IMPL_ALU_COMP2
//`define OR1200_IMPL_ALU_COMP3
//
// Implement Find First/Last '1'
//
`define OR1200_IMPL_ALU_FFL1
//
// Implement l.cust5 ALU instruction
//
//`define OR1200_IMPL_ALU_CUST5
//
// Implement l.extXs and l.extXz instructions
//
//`define OR1200_IMPL_ALU_EXT
//
// Implement multiplier
//
// By default multiplier is implemented
//
`define OR1200_MULT_IMPLEMENTED
//
// Implement multiply-and-accumulate
//
// By default MAC is implemented. To
// implement MAC, multiplier (non-serial) needs to be
// implemented.
//
//`define OR1200_MAC_IMPLEMENTED
//
// Implement optional l.div/l.divu instructions
//
// By default divide instructions are not implemented
// to save area.
//
//
`define OR1200_DIV_IMPLEMENTED
//
// Serial multiplier.
//
`define OR1200_MULT_SERIAL
//
// Serial divider.
// Uncomment to use a serial divider, otherwise will
// be a generic parallel implementation.
//
`define OR1200_DIV_SERIAL
//
// Implement HW Single Precision FPU
//
//`define OR1200_FPU_IMPLEMENTED
//
// Clock ratio RISC clock versus WB clock
//
// If you plan to run WB:RISC clock fixed to 1:1, disable
// both defines
//
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
// and use clmode to set ratio
//
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
// clmode to set ratio
//
//`define OR1200_CLKDIV_2_SUPPORTED
//`define OR1200_CLKDIV_4_SUPPORTED
//
// Type of register file RAM
//
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
//`define OR1200_RFRAM_TWOPORT
//
// Memory macro dual port (see or1200_dpram.v)
`define OR1200_RFRAM_DUALPORT
//
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
//`define OR1200_RFRAM_GENERIC
// Generic register file supports - 16 registers
`ifdef OR1200_RFRAM_GENERIC
// `define OR1200_RFRAM_16REG
`endif
//
// Type of mem2reg aligner to implement.
//
// Once OR1200_IMPL_MEM2REG2 yielded faster
// circuit, however with today tools it will
// most probably give you slower circuit.
//
`define OR1200_IMPL_MEM2REG1
//`define OR1200_IMPL_MEM2REG2
//
// Reset value and event
//
`ifdef OR1200_RST_ACT_LOW
`define OR1200_RST_VALUE (1'b0)
`define OR1200_RST_EVENT negedge
`else
`define OR1200_RST_VALUE (1'b1)
`define OR1200_RST_EVENT posedge
`endif
//
// ALUOPs
//
`define OR1200_ALUOP_WIDTH 5
`define OR1200_ALUOP_NOP 5'b0_0100
/* LS-nibble encodings correspond to bits [3:0] of instruction */
`define OR1200_ALUOP_ADD 5'b0_0000 // 0
`define OR1200_ALUOP_ADDC 5'b0_0001 // 1
`define OR1200_ALUOP_SUB 5'b0_0010 // 2
`define OR1200_ALUOP_AND 5'b0_0011 // 3
`define OR1200_ALUOP_OR 5'b0_0100 // 4
`define OR1200_ALUOP_XOR 5'b0_0101 // 5
`define OR1200_ALUOP_MUL 5'b0_0110 // 6
`define OR1200_ALUOP_RESERVED 5'b0_0111 // 7
`define OR1200_ALUOP_SHROT 5'b0_1000 // 8
`define OR1200_ALUOP_DIV 5'b0_1001 // 9
`define OR1200_ALUOP_DIVU 5'b0_1010 // a
`define OR1200_ALUOP_MULU 5'b0_1011 // b
`define OR1200_ALUOP_EXTHB 5'b0_1100 // c
`define OR1200_ALUOP_EXTW 5'b0_1101 // d
`define OR1200_ALUOP_CMOV 5'b0_1110 // e
`define OR1200_ALUOP_FFL1 5'b0_1111 // f
/* Values sent to ALU from decode unit - not defined by ISA */
`define OR1200_ALUOP_COMP 5'b1_0000 // Comparison
`define OR1200_ALUOP_MOVHI 5'b1_0001 // Move-high
`define OR1200_ALUOP_CUST5 5'b1_0010 // l.cust5
// ALU instructions second opcode field
`define OR1200_ALUOP2_POS 9:6
`define OR1200_ALUOP2_WIDTH 4
//
// MACOPs
//
`define OR1200_MACOP_WIDTH 3
`define OR1200_MACOP_NOP 3'b000
`define OR1200_MACOP_MAC 3'b001
`define OR1200_MACOP_MSB 3'b010
//
// Shift/rotate ops
//
`define OR1200_SHROTOP_WIDTH 4
`define OR1200_SHROTOP_NOP 4'd0
`define OR1200_SHROTOP_SLL 4'd0
`define OR1200_SHROTOP_SRL 4'd1
`define OR1200_SHROTOP_SRA 4'd2
`define OR1200_SHROTOP_ROR 4'd3
//
// Zero/Sign Extend ops
//
`define OR1200_EXTHBOP_WIDTH 4
`define OR1200_EXTHBOP_BS 4'h1
`define OR1200_EXTHBOP_HS 4'h0
`define OR1200_EXTHBOP_BZ 4'h3
`define OR1200_EXTHBOP_HZ 4'h2
`define OR1200_EXTWOP_WIDTH 4
`define OR1200_EXTWOP_WS 4'h0
`define OR1200_EXTWOP_WZ 4'h1
// Execution cycles per instruction
`define OR1200_MULTICYCLE_WIDTH 3
`define OR1200_ONE_CYCLE 3'd0
`define OR1200_TWO_CYCLES 3'd1
// Execution control which will "wait on" a module to finish
`define OR1200_WAIT_ON_WIDTH 2
`define OR1200_WAIT_ON_NOTHING `OR1200_WAIT_ON_WIDTH'd0
`define OR1200_WAIT_ON_MULTMAC `OR1200_WAIT_ON_WIDTH'd1
`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd2
`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd3
// Operand MUX selects
`define OR1200_SEL_WIDTH 2
`define OR1200_SEL_RF 2'd0
`define OR1200_SEL_IMM 2'd1
`define OR1200_SEL_EX_FORW 2'd2
`define OR1200_SEL_WB_FORW 2'd3
//
// BRANCHOPs
//
`define OR1200_BRANCHOP_WIDTH 3
`define OR1200_BRANCHOP_NOP 3'd0
`define OR1200_BRANCHOP_J 3'd1
`define OR1200_BRANCHOP_JR 3'd2
`define OR1200_BRANCHOP_BAL 3'd3
`define OR1200_BRANCHOP_BF 3'd4
`define OR1200_BRANCHOP_BNF 3'd5
`define OR1200_BRANCHOP_RFE 3'd6
//
// LSUOPs
//
// Bit 0: sign extend
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
// Bit 3: 0 load, 1 store
`define OR1200_LSUOP_WIDTH 4
`define OR1200_LSUOP_NOP 4'b0000
`define OR1200_LSUOP_LBZ 4'b0010
`define OR1200_LSUOP_LBS 4'b0011
`define OR1200_LSUOP_LHZ 4'b0100
`define OR1200_LSUOP_LHS 4'b0101
`define OR1200_LSUOP_LWZ 4'b0110
`define OR1200_LSUOP_LWS 4'b0111
`define OR1200_LSUOP_LD 4'b0001
`define OR1200_LSUOP_SD 4'b1000
`define OR1200_LSUOP_SB 4'b1010
`define OR1200_LSUOP_SH 4'b1100
`define OR1200_LSUOP_SW 4'b1110
// Number of bits of load/store EA precalculated in ID stage
// for balancing ID and EX stages.
//
// Valid range: 2,3,...,30,31
`define OR1200_LSUEA_PRECALC 2
// FETCHOPs
`define OR1200_FETCHOP_WIDTH 1
`define OR1200_FETCHOP_NOP 1'b0
`define OR1200_FETCHOP_LW 1'b1
//
// Register File Write-Back OPs
//
// Bit 0: register file write enable
// Bits 3-1: write-back mux selects
//
`define OR1200_RFWBOP_WIDTH 4
`define OR1200_RFWBOP_NOP 4'b0000
`define OR1200_RFWBOP_ALU 3'b000
`define OR1200_RFWBOP_LSU 3'b001
`define OR1200_RFWBOP_SPRS 3'b010
`define OR1200_RFWBOP_LR 3'b011
`define OR1200_RFWBOP_FPU 3'b100
// Compare instructions
`define OR1200_COP_SFEQ 3'b000
`define OR1200_COP_SFNE 3'b001
`define OR1200_COP_SFGT 3'b010
`define OR1200_COP_SFGE 3'b011
`define OR1200_COP_SFLT 3'b100
`define OR1200_COP_SFLE 3'b101
`define OR1200_COP_X 3'b111
`define OR1200_SIGNED_COMPARE 'd3
`define OR1200_COMPOP_WIDTH 4
//
// FP OPs
//
// MSbit indicates FPU operation valid
//
`define OR1200_FPUOP_WIDTH 8
// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
`define OR1200_FPUOP_CYCLES 3'd4
// FP instruction is double precision if bit 4 is set. We're a 32-bit
// implementation thus do not support double precision FP
`define OR1200_FPUOP_DOUBLE_BIT 4
`define OR1200_FPUOP_ADD 8'b0000_0000
`define OR1200_FPUOP_SUB 8'b0000_0001
`define OR1200_FPUOP_MUL 8'b0000_0010
`define OR1200_FPUOP_DIV 8'b0000_0011
`define OR1200_FPUOP_ITOF 8'b0000_0100
`define OR1200_FPUOP_FTOI 8'b0000_0101
`define OR1200_FPUOP_REM 8'b0000_0110
`define OR1200_FPUOP_RESERVED 8'b0000_0111
// FP Compare instructions
`define OR1200_FPCOP_SFEQ 8'b0000_1000
`define OR1200_FPCOP_SFNE 8'b0000_1001
`define OR1200_FPCOP_SFGT 8'b0000_1010
`define OR1200_FPCOP_SFGE 8'b0000_1011
`define OR1200_FPCOP_SFLT 8'b0000_1100
`define OR1200_FPCOP_SFLE 8'b0000_1101
//
// TAGs for instruction bus
//
`define OR1200_ITAG_IDLE 4'h0 // idle bus
`define OR1200_ITAG_NI 4'h1 // normal insn
`define OR1200_ITAG_BE 4'hb // Bus error exception
`define OR1200_ITAG_PE 4'hc // Page fault exception
`define OR1200_ITAG_TE 4'hd // TLB miss exception
//
// TAGs for data bus
//
`define OR1200_DTAG_IDLE 4'h0 // idle bus
`define OR1200_DTAG_ND 4'h1 // normal data
`define OR1200_DTAG_AE 4'ha // Alignment exception
`define OR1200_DTAG_BE 4'hb // Bus error exception
`define OR1200_DTAG_PE 4'hc // Page fault exception
`define OR1200_DTAG_TE 4'hd // TLB miss exception
//////////////////////////////////////////////
//
// ORBIS32 ISA specifics
//
// SHROT_OP position in machine word
`define OR1200_SHROTOP_POS 7:6
//
// Instruction opcode groups (basic)
//
`define OR1200_OR32_J 6'b000000
`define OR1200_OR32_JAL 6'b000001
`define OR1200_OR32_BNF 6'b000011
`define OR1200_OR32_BF 6'b000100
`define OR1200_OR32_NOP 6'b000101
`define OR1200_OR32_MOVHI 6'b000110
`define OR1200_OR32_MACRC 6'b000110
`define OR1200_OR32_XSYNC 6'b001000
`define OR1200_OR32_RFE 6'b001001
/* */
`define OR1200_OR32_JR 6'b010001
`define OR1200_OR32_JALR 6'b010010
`define OR1200_OR32_MACI 6'b010011
/* */
`define OR1200_OR32_LWZ 6'b100001
`define OR1200_OR32_LWS 6'b100010
`define OR1200_OR32_LBZ 6'b100011
`define OR1200_OR32_LBS 6'b100100
`define OR1200_OR32_LHZ 6'b100101
`define OR1200_OR32_LHS 6'b100110
`define OR1200_OR32_ADDI 6'b100111
`define OR1200_OR32_ADDIC 6'b101000
`define OR1200_OR32_ANDI 6'b101001
`define OR1200_OR32_ORI 6'b101010
`define OR1200_OR32_XORI 6'b101011
`define OR1200_OR32_MULI 6'b101100
`define OR1200_OR32_MFSPR 6'b101101
`define OR1200_OR32_SH_ROTI 6'b101110
`define OR1200_OR32_SFXXI 6'b101111
/* */
`define OR1200_OR32_MTSPR 6'b110000
`define OR1200_OR32_MACMSB 6'b110001
`define OR1200_OR32_FLOAT 6'b110010
/* */
`define OR1200_OR32_SW 6'b110101
`define OR1200_OR32_SB 6'b110110
`define OR1200_OR32_SH 6'b110111
`define OR1200_OR32_ALU 6'b111000
`define OR1200_OR32_SFXX 6'b111001
`define OR1200_OR32_CUST5 6'b111100
/////////////////////////////////////////////////////
//
// Exceptions
//
//
// Exception vectors per OR1K architecture:
// 0xPPPPP100 - reset
// 0xPPPPP200 - bus error
// ... etc
// where P represents exception prefix.
//
// Exception vectors can be customized as per
// the following formula:
// 0xPPPPPNVV - exception N
//
// P represents exception prefix
// N represents exception N
// VV represents length of the individual vector space,
// usually it is 8 bits wide and starts with all bits zero
//
//
// PPPPP and VV parts
//
// Sum of these two defines needs to be 28
//
`define OR1200_EXCEPT_EPH0_P 20'h00000
`define OR1200_EXCEPT_EPH1_P 20'hF0000
`define OR1200_EXCEPT_V 8'h00
//
// N part width
//
`define OR1200_EXCEPT_WIDTH 4
//
// Definition of exception vectors
//
// To avoid implementation of a certain exception,
// simply comment out corresponding line
//
`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf
`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he
`define OR1200_EXCEPT_FLOAT `OR1200_EXCEPT_WIDTH'hd
`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc
`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb
`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha
`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9
`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8
`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7
`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6
`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5
`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4
`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3
`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2
`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1
`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0
/////////////////////////////////////////////////////
//
// SPR groups
//
// Bits that define the group
`define OR1200_SPR_GROUP_BITS 15:11
// Width of the group bits
`define OR1200_SPR_GROUP_WIDTH 5
// Bits that define offset inside the group
`define OR1200_SPR_OFS_BITS 10:0
// List of groups
`define OR1200_SPR_GROUP_SYS 5'd00
`define OR1200_SPR_GROUP_DMMU 5'd01
`define OR1200_SPR_GROUP_IMMU 5'd02
`define OR1200_SPR_GROUP_DC 5'd03
`define OR1200_SPR_GROUP_IC 5'd04
`define OR1200_SPR_GROUP_MAC 5'd05
`define OR1200_SPR_GROUP_DU 5'd06
`define OR1200_SPR_GROUP_PM 5'd08
`define OR1200_SPR_GROUP_PIC 5'd09
`define OR1200_SPR_GROUP_TT 5'd10
`define OR1200_SPR_GROUP_FPU 5'd11
/////////////////////////////////////////////////////
//
// System group
//
//
// System registers
//
`define OR1200_SPR_CFGR 7'd0
`define OR1200_SPR_RF 6'd32 // 1024 >> 5
`define OR1200_SPR_NPC 11'd16
`define OR1200_SPR_SR 11'd17
`define OR1200_SPR_PPC 11'd18
`define OR1200_SPR_FPCSR 11'd20
`define OR1200_SPR_EPCR 11'd32
`define OR1200_SPR_EEAR 11'd48
`define OR1200_SPR_ESR 11'd64
//
// SR bits
//
`define OR1200_SR_WIDTH 17
`define OR1200_SR_SM 0
`define OR1200_SR_TEE 1
`define OR1200_SR_IEE 2
`define OR1200_SR_DCE 3
`define OR1200_SR_ICE 4
`define OR1200_SR_DME 5
`define OR1200_SR_IME 6
`define OR1200_SR_LEE 7
`define OR1200_SR_CE 8
`define OR1200_SR_F 9
`define OR1200_SR_CY 10 // Optional
`define OR1200_SR_OV 11 // Optional
`define OR1200_SR_OVE 12 // Optional
`define OR1200_SR_DSX 13 // Unused
`define OR1200_SR_EPH 14
`define OR1200_SR_FO 15
`define OR1200_SR_TED 16
`define OR1200_SR_CID 31:28 // Unimplemented
//
// Bits that define offset inside the group
//
`define OR1200_SPROFS_BITS 10:0
//
// Default Exception Prefix
//
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
//
`define OR1200_SR_EPH_DEF 1'b0
//
// FPCSR bits
//
`define OR1200_FPCSR_WIDTH 12
`define OR1200_FPCSR_FPEE 0
`define OR1200_FPCSR_RM 2:1
`define OR1200_FPCSR_OVF 3
`define OR1200_FPCSR_UNF 4
`define OR1200_FPCSR_SNF 5
`define OR1200_FPCSR_QNF 6
`define OR1200_FPCSR_ZF 7
`define OR1200_FPCSR_IXF 8
`define OR1200_FPCSR_IVF 9
`define OR1200_FPCSR_INF 10
`define OR1200_FPCSR_DZF 11
`define OR1200_FPCSR_RES 31:12
/////////////////////////////////////////////////////
//
// Power Management (PM)
//
// Define it if you want PM implemented
//`define OR1200_PM_IMPLEMENTED
// Bit positions inside PMR (don't change)
`define OR1200_PM_PMR_SDF 3:0
`define OR1200_PM_PMR_DME 4
`define OR1200_PM_PMR_SME 5
`define OR1200_PM_PMR_DCGE 6
`define OR1200_PM_PMR_UNUSED 31:7
// PMR offset inside PM group of registers
`define OR1200_PM_OFS_PMR 11'b0
// PM group
`define OR1200_SPRGRP_PM 5'd8
// Define if PMR can be read/written at any address inside PM group
`define OR1200_PM_PARTIAL_DECODING
// Define if reading PMR is allowed
`define OR1200_PM_READREGS
// Define if unused PMR bits should be zero
`define OR1200_PM_UNUSED_ZERO
/////////////////////////////////////////////////////
//
// Debug Unit (DU)
//
// Define it if you want DU implemented
`define OR1200_DU_IMPLEMENTED
//
// Define if you want HW Breakpoints
// (if HW breakpoints are not implemented
// only default software trapping is
// possible with l.trap insn - this is
// however already enough for use
// with or32 gdb)
//
//`define OR1200_DU_HWBKPTS
// Number of DVR/DCR pairs if HW breakpoints enabled
// Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number !
// DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS
`define OR1200_DU_DVRDCR_PAIRS 8
// Define if you want trace buffer
// (for now only available for Xilinx Virtex FPGAs)
//`define OR1200_DU_TB_IMPLEMENTED
//
// Address offsets of DU registers inside DU group
//
// To not implement a register, doq not define its address
//
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DVR0 11'd0
`define OR1200_DU_DVR1 11'd1
`define OR1200_DU_DVR2 11'd2
`define OR1200_DU_DVR3 11'd3
`define OR1200_DU_DVR4 11'd4
`define OR1200_DU_DVR5 11'd5
`define OR1200_DU_DVR6 11'd6
`define OR1200_DU_DVR7 11'd7
`define OR1200_DU_DCR0 11'd8
`define OR1200_DU_DCR1 11'd9
`define OR1200_DU_DCR2 11'd10
`define OR1200_DU_DCR3 11'd11
`define OR1200_DU_DCR4 11'd12
`define OR1200_DU_DCR5 11'd13
`define OR1200_DU_DCR6 11'd14
`define OR1200_DU_DCR7 11'd15
`endif
`define OR1200_DU_DMR1 11'd16
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DMR2 11'd17
`define OR1200_DU_DWCR0 11'd18
`define OR1200_DU_DWCR1 11'd19
`endif
`define OR1200_DU_DSR 11'd20
`define OR1200_DU_DRR 11'd21
`ifdef OR1200_DU_TB_IMPLEMENTED
`define OR1200_DU_TBADR 11'h0ff
`define OR1200_DU_TBIA 11'h1??
`define OR1200_DU_TBIM 11'h2??
`define OR1200_DU_TBAR 11'h3??
`define OR1200_DU_TBTS 11'h4??
`endif
// Position of offset bits inside SPR address
`define OR1200_DUOFS_BITS 10:0
// DCR bits
`define OR1200_DU_DCR_DP 0
`define OR1200_DU_DCR_CC 3:1
`define OR1200_DU_DCR_SC 4
`define OR1200_DU_DCR_CT 7:5
// DMR1 bits
`define OR1200_DU_DMR1_CW0 1:0
`define OR1200_DU_DMR1_CW1 3:2
`define OR1200_DU_DMR1_CW2 5:4
`define OR1200_DU_DMR1_CW3 7:6
`define OR1200_DU_DMR1_CW4 9:8
`define OR1200_DU_DMR1_CW5 11:10
`define OR1200_DU_DMR1_CW6 13:12
`define OR1200_DU_DMR1_CW7 15:14
`define OR1200_DU_DMR1_CW8 17:16
`define OR1200_DU_DMR1_CW9 19:18
`define OR1200_DU_DMR1_CW10 21:20
`define OR1200_DU_DMR1_ST 22
`define OR1200_DU_DMR1_BT 23
`define OR1200_DU_DMR1_DXFW 24
`define OR1200_DU_DMR1_ETE 25
// DMR2 bits
`define OR1200_DU_DMR2_WCE0 0
`define OR1200_DU_DMR2_WCE1 1
`define OR1200_DU_DMR2_AWTC 12:2
`define OR1200_DU_DMR2_WGB 23:13
// DWCR bits
`define OR1200_DU_DWCR_COUNT 15:0
`define OR1200_DU_DWCR_MATCH 31:16
// DSR bits
`define OR1200_DU_DSR_WIDTH 14
`define OR1200_DU_DSR_RSTE 0
`define OR1200_DU_DSR_BUSEE 1
`define OR1200_DU_DSR_DPFE 2
`define OR1200_DU_DSR_IPFE 3
`define OR1200_DU_DSR_TTE 4
`define OR1200_DU_DSR_AE 5
`define OR1200_DU_DSR_IIE 6
`define OR1200_DU_DSR_IE 7
`define OR1200_DU_DSR_DME 8
`define OR1200_DU_DSR_IME 9
`define OR1200_DU_DSR_RE 10
`define OR1200_DU_DSR_SCE 11
`define OR1200_DU_DSR_FPE 12
`define OR1200_DU_DSR_TE 13
// DRR bits
`define OR1200_DU_DRR_RSTE 0
`define OR1200_DU_DRR_BUSEE 1
`define OR1200_DU_DRR_DPFE 2
`define OR1200_DU_DRR_IPFE 3
`define OR1200_DU_DRR_TTE 4
`define OR1200_DU_DRR_AE 5
`define OR1200_DU_DRR_IIE 6
`define OR1200_DU_DRR_IE 7
`define OR1200_DU_DRR_DME 8
`define OR1200_DU_DRR_IME 9
`define OR1200_DU_DRR_RE 10
`define OR1200_DU_DRR_SCE 11
`define OR1200_DU_DRR_FPE 12
`define OR1200_DU_DRR_TE 13
// Define if reading DU regs is allowed
`define OR1200_DU_READREGS
// Define if unused DU registers bits should be zero
`define OR1200_DU_UNUSED_ZERO
// Define if IF/LSU status is not needed by devel i/f
`define OR1200_DU_STATUS_UNIMPLEMENTED
/////////////////////////////////////////////////////
//
// Programmable Interrupt Controller (PIC)
//
// Define it if you want PIC implemented
`define OR1200_PIC_IMPLEMENTED
// Define number of interrupt inputs (2-31)
`define OR1200_PIC_INTS 31
// Address offsets of PIC registers inside PIC group
`define OR1200_PIC_OFS_PICMR 2'd0
`define OR1200_PIC_OFS_PICSR 2'd2
// Position of offset bits inside SPR address
`define OR1200_PICOFS_BITS 1:0
// Define if you want these PIC registers to be implemented
`define OR1200_PIC_PICMR
`define OR1200_PIC_PICSR
// Define if reading PIC registers is allowed
`define OR1200_PIC_READREGS
// Define if unused PIC register bits should be zero
`define OR1200_PIC_UNUSED_ZERO
/////////////////////////////////////////////////////
//
// Tick Timer (TT)
//
// Define it if you want TT implemented
`define OR1200_TT_IMPLEMENTED
// Address offsets of TT registers inside TT group
`define OR1200_TT_OFS_TTMR 1'd0
`define OR1200_TT_OFS_TTCR 1'd1
// Position of offset bits inside SPR group
`define OR1200_TTOFS_BITS 0
// Define if you want these TT registers to be implemented
`define OR1200_TT_TTMR
`define OR1200_TT_TTCR
// TTMR bits
`define OR1200_TT_TTMR_TP 27:0
`define OR1200_TT_TTMR_IP 28
`define OR1200_TT_TTMR_IE 29
`define OR1200_TT_TTMR_M 31:30
// Define if reading TT registers is allowed
`define OR1200_TT_READREGS
//////////////////////////////////////////////
//
// MAC
//
`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable
//
// Shift {MACHI,MACLO} into destination register when executing l.macrc
//
// According to architecture manual there is no shift, so default value is 0.
// However the implementation has deviated in this from the arch manual and had
// hard coded shift by 28 bits which is a useful optimization for MP3 decoding
// (if using libmad fixed point library). Shifts are no longer default setup,
// but if you need to remain backward compatible, define your shift bits, which
// were normally
// dest_GPR = {MACHI,MACLO}[59:28]
`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility
//////////////////////////////////////////////
//
// Data MMU (DMMU)
//
//
// Address that selects between TLB TR and MR
//
`define OR1200_DTLB_TM_ADDR 7
//
// DTLBMR fields
//
`define OR1200_DTLBMR_V_BITS 0
`define OR1200_DTLBMR_CID_BITS 4:1
`define OR1200_DTLBMR_RES_BITS 11:5
`define OR1200_DTLBMR_VPN_BITS 31:13
//
// DTLBTR fields
//
`define OR1200_DTLBTR_CC_BITS 0
`define OR1200_DTLBTR_CI_BITS 1
`define OR1200_DTLBTR_WBC_BITS 2
`define OR1200_DTLBTR_WOM_BITS 3
`define OR1200_DTLBTR_A_BITS 4
`define OR1200_DTLBTR_D_BITS 5
`define OR1200_DTLBTR_URE_BITS 6
`define OR1200_DTLBTR_UWE_BITS 7
`define OR1200_DTLBTR_SRE_BITS 8
`define OR1200_DTLBTR_SWE_BITS 9
`define OR1200_DTLBTR_RES_BITS 11:10
`define OR1200_DTLBTR_PPN_BITS 31:13
//
// DTLB configuration
//
`define OR1200_DMMU_PS 13 // 13 for 8KB page size
`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries
`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13
`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19
`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13
`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12
`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20
`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20
`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit
`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI
//
// Cache inhibit while DMMU is not enabled/implemented
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !dcpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30]
// cache inhibited 2GB-4GB (default) dcpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_DMMU_CI dcpu_adr_i[31]
//////////////////////////////////////////////
//
// Insn MMU (IMMU)
//
//
// Address that selects between TLB TR and MR
//
`define OR1200_ITLB_TM_ADDR 7
//
// ITLBMR fields
//
`define OR1200_ITLBMR_V_BITS 0
`define OR1200_ITLBMR_CID_BITS 4:1
`define OR1200_ITLBMR_RES_BITS 11:5
`define OR1200_ITLBMR_VPN_BITS 31:13
//
// ITLBTR fields
//
`define OR1200_ITLBTR_CC_BITS 0
`define OR1200_ITLBTR_CI_BITS 1
`define OR1200_ITLBTR_WBC_BITS 2
`define OR1200_ITLBTR_WOM_BITS 3
`define OR1200_ITLBTR_A_BITS 4
`define OR1200_ITLBTR_D_BITS 5
`define OR1200_ITLBTR_SXE_BITS 6
`define OR1200_ITLBTR_UXE_BITS 7
`define OR1200_ITLBTR_RES_BITS 11:8
`define OR1200_ITLBTR_PPN_BITS 31:13
//
// ITLB configuration
//
`define OR1200_IMMU_PS 13 // 13 for 8KB page size
`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries
`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13
`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19
`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13
`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12
`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20
`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20
`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit
`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI
//
// Cache inhibit while IMMU is not enabled/implemented
// Note: all combinations that use icpu_adr_i cause async loop
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !icpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30]
// cache inhibited 2GB-4GB (default) icpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_IMMU_CI 1'b0
/////////////////////////////////////////////////
//
// Insn cache (IC)
//
// 4 for 16 byte line, 5 for 32 byte lines.
`ifdef OR1200_IC_1W_32KB
`define OR1200_ICLS 5
`else
`define OR1200_ICLS 4
`endif
//
// IC configurations
//
`ifdef OR1200_IC_1W_512B
`define OR1200_ICSIZE 9 // 512
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5
`define OR1200_ICTAG_W 24
`endif
`ifdef OR1200_IC_1W_4KB
`define OR1200_ICSIZE 12 // 4096
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8
`define OR1200_ICTAG_W 21
`endif
`ifdef OR1200_IC_1W_8KB
`define OR1200_ICSIZE 13 // 8192
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
`define OR1200_ICTAG_W 20
`endif
`ifdef OR1200_IC_1W_16KB
`define OR1200_ICSIZE 14 // 16384
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 12
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 13
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
`define OR1200_ICTAG_W 19
`endif
`ifdef OR1200_IC_1W_32KB
`define OR1200_ICSIZE 15 // 32768
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 13
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 14
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
`define OR1200_ICTAG_W 18
`endif
/////////////////////////////////////////////////
//
// Data cache (DC)
//
// 4 for 16 bytes, 5 for 32 bytes
`ifdef OR1200_DC_1W_32KB
`define OR1200_DCLS 5
`else
`define OR1200_DCLS 4
`endif
// Define to enable default behavior of cache as write through
// Turning this off enabled write back statergy
//
`define OR1200_DC_WRITETHROUGH
// Define to enable stores from the stack not doing writethrough.
// EXPERIMENTAL
//`define OR1200_DC_NOSTACKWRITETHROUGH
// Data cache SPR definitions
`define OR1200_SPRGRP_DC_ADR_WIDTH 3
// Data cache group SPR addresses
`define OR1200_SPRGRP_DC_DCCR 3'd0 // Not implemented
`define OR1200_SPRGRP_DC_DCBPR 3'd1 // Not implemented
`define OR1200_SPRGRP_DC_DCBFR 3'd2
`define OR1200_SPRGRP_DC_DCBIR 3'd3
`define OR1200_SPRGRP_DC_DCBWR 3'd4 // Not implemented
`define OR1200_SPRGRP_DC_DCBLR 3'd5 // Not implemented
//
// DC configurations
//
`ifdef OR1200_DC_1W_4KB
`define OR1200_DCSIZE 12 // 4096
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8
`define OR1200_DCTAG_W 21
`endif
`ifdef OR1200_DC_1W_8KB
`define OR1200_DCSIZE 13 // 8192
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
`define OR1200_DCTAG_W 20
`endif
`ifdef OR1200_DC_1W_16KB
`define OR1200_DCSIZE 14 // 16384
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 12
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 13
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 14
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
`define OR1200_DCTAG_W 19
`endif
`ifdef OR1200_DC_1W_32KB
`define OR1200_DCSIZE 15 // 32768
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 13
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 14
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 15
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
`define OR1200_DCTAG_W 18
`endif
/////////////////////////////////////////////////
//
// Store buffer (SB)
//
//
// Store buffer
//
// It will improve performance by "caching" CPU stores
// using store buffer. This is most important for function
// prologues because DC can only work in write though mode
// and all stores would have to complete external WB writes
// to memory.
// Store buffer is between DC and data BIU.
// All stores will be stored into store buffer and immediately
// completed by the CPU, even though actual external writes
// will be performed later. As a consequence store buffer masks
// all data bus errors related to stores (data bus errors
// related to loads are delivered normally).
// All pending CPU loads will wait until store buffer is empty to
// ensure strict memory model. Right now this is necessary because
// we don't make destinction between cached and cache inhibited
// address space, so we simply empty store buffer until loads
// can begin.
//
// It makes design a bit bigger, depending what is the number of
// entries in SB FIFO. Number of entries can be changed further
// down.
//
//`define OR1200_SB_IMPLEMENTED
//
// Number of store buffer entries
//
// Verified number of entries are 4 and 8 entries
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
// always match 2**OR1200_SB_LOG.
// To disable store buffer, undefine
// OR1200_SB_IMPLEMENTED.
//
`define OR1200_SB_LOG 2 // 2 or 3
`define OR1200_SB_ENTRIES 4 // 4 or 8
/////////////////////////////////////////////////
//
// Quick Embedded Memory (QMEM)
//
//
// Quick Embedded Memory
//
// Instantiation of dedicated insn/data memory (RAM or ROM).
// Insn fetch has effective throughput 1insn / clock cycle.
// Data load takes two clock cycles / access, data store
// takes 1 clock cycle / access (if there is no insn fetch)).
// Memory instantiation is shared between insn and data,
// meaning if insn fetch are performed, data load/store
// performance will be lower.
//
// Main reason for QMEM is to put some time critical functions
// into this memory and to have predictable and fast access
// to these functions. (soft fpu, context switch, exception
// handlers, stack, etc)
//
// It makes design a bit bigger and slower. QMEM sits behind
// IMMU/DMMU so all addresses are physical (so the MMUs can be
// used with QMEM and QMEM is seen by the CPU just like any other
// memory in the system). IC/DC are sitting behind QMEM so the
// whole design timing might be worse with QMEM implemented.
//
//`define OR1200_QMEM_IMPLEMENTED
//
// Base address and mask of QMEM
//
// Base address defines first address of QMEM. Mask defines
// QMEM range in address space. Actual size of QMEM is however
// determined with instantiated RAM/ROM. However bigger
// mask will reserve more address space for QMEM, but also
// make design faster, while more tight mask will take
// less address space but also make design slower. If
// instantiated RAM/ROM is smaller than space reserved with
// the mask, instatiated RAM/ROM will also be shadowed
// at higher addresses in reserved space.
//
`define OR1200_QMEM_IADDR 32'h0080_0000
`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB
`define OR1200_QMEM_DADDR 32'h0080_0000
`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB
//
// QMEM interface byte-select capability
//
// To enable qmem_sel* ports, define this macro.
//
//`define OR1200_QMEM_BSEL
//
// QMEM interface acknowledge
//
// To enable qmem_ack port, define this macro.
//
//`define OR1200_QMEM_ACK
/////////////////////////////////////////////////////
//
// VR, UPR and Configuration Registers
//
//
// VR, UPR and configuration registers are optional. If
// implemented, operating system can automatically figure
// out how to use the processor because it knows
// what units are available in the processor and how they
// are configured.
//
// This section must be last in or1200_defines.v file so
// that all units are already configured and thus
// configuration registers are properly set.
//
// Define if you want configuration registers implemented
`define OR1200_CFGR_IMPLEMENTED
// Define if you want full address decode inside SYS group
`define OR1200_SYS_FULL_DECODE
// Offsets of VR, UPR and CFGR registers
`define OR1200_SPRGRP_SYS_VR 4'h0
`define OR1200_SPRGRP_SYS_UPR 4'h1
`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2
`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3
`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4
`define OR1200_SPRGRP_SYS_DCCFGR 4'h5
`define OR1200_SPRGRP_SYS_ICCFGR 4'h6
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
// VR fields
`define OR1200_VR_REV_BITS 5:0
`define OR1200_VR_RES1_BITS 15:6
`define OR1200_VR_CFG_BITS 23:16
`define OR1200_VR_VER_BITS 31:24
// VR values
`define OR1200_VR_REV 6'h08
`define OR1200_VR_RES1 10'h000
`define OR1200_VR_CFG 8'h00
`define OR1200_VR_VER 8'h12
// UPR fields
`define OR1200_UPR_UP_BITS 0
`define OR1200_UPR_DCP_BITS 1
`define OR1200_UPR_ICP_BITS 2
`define OR1200_UPR_DMP_BITS 3
`define OR1200_UPR_IMP_BITS 4
`define OR1200_UPR_MP_BITS 5
`define OR1200_UPR_DUP_BITS 6
`define OR1200_UPR_PCUP_BITS 7
`define OR1200_UPR_PMP_BITS 8
`define OR1200_UPR_PICP_BITS 9
`define OR1200_UPR_TTP_BITS 10
`define OR1200_UPR_FPP_BITS 11
`define OR1200_UPR_RES1_BITS 23:12
`define OR1200_UPR_CUP_BITS 31:24
// UPR values
`define OR1200_UPR_UP 1'b1
`ifdef OR1200_NO_DC
`define OR1200_UPR_DCP 1'b0
`else
`define OR1200_UPR_DCP 1'b1
`endif
`ifdef OR1200_NO_IC
`define OR1200_UPR_ICP 1'b0
`else
`define OR1200_UPR_ICP 1'b1
`endif
`ifdef OR1200_NO_DMMU
`define OR1200_UPR_DMP 1'b0
`else
`define OR1200_UPR_DMP 1'b1
`endif
`ifdef OR1200_NO_IMMU
`define OR1200_UPR_IMP 1'b0
`else
`define OR1200_UPR_IMP 1'b1
`endif
`ifdef OR1200_MAC_IMPLEMENTED
`define OR1200_UPR_MP 1'b1
`else
`define OR1200_UPR_MP 1'b0
`endif
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_DUP 1'b1
`else
`define OR1200_UPR_DUP 1'b0
`endif
`define OR1200_UPR_PCUP 1'b0 // Performance counters not present
`ifdef OR1200_PM_IMPLEMENTED
`define OR1200_UPR_PMP 1'b1
`else
`define OR1200_UPR_PMP 1'b0
`endif
`ifdef OR1200_PIC_IMPLEMENTED
`define OR1200_UPR_PICP 1'b1
`else
`define OR1200_UPR_PICP 1'b0
`endif
`ifdef OR1200_TT_IMPLEMENTED
`define OR1200_UPR_TTP 1'b1
`else
`define OR1200_UPR_TTP 1'b0
`endif
`ifdef OR1200_FPU_IMPLEMENTED
`define OR1200_UPR_FPP 1'b1
`else
`define OR1200_UPR_FPP 1'b0
`endif
`define OR1200_UPR_RES1 12'h000
`define OR1200_UPR_CUP 8'h00
// CPUCFGR fields
`define OR1200_CPUCFGR_NSGF_BITS 3:0
`define OR1200_CPUCFGR_HGF_BITS 4
`define OR1200_CPUCFGR_OB32S_BITS 5
`define OR1200_CPUCFGR_OB64S_BITS 6
`define OR1200_CPUCFGR_OF32S_BITS 7
`define OR1200_CPUCFGR_OF64S_BITS 8
`define OR1200_CPUCFGR_OV64S_BITS 9
`define OR1200_CPUCFGR_RES1_BITS 31:10
// CPUCFGR values
`define OR1200_CPUCFGR_NSGF 4'h0
`ifdef OR1200_RFRAM_16REG
`define OR1200_CPUCFGR_HGF 1'b1
`else
`define OR1200_CPUCFGR_HGF 1'b0
`endif
`define OR1200_CPUCFGR_OB32S 1'b1
`define OR1200_CPUCFGR_OB64S 1'b0
`ifdef OR1200_FPU_IMPLEMENTED
`define OR1200_CPUCFGR_OF32S 1'b1
`else
`define OR1200_CPUCFGR_OF32S 1'b0
`endif
`define OR1200_CPUCFGR_OF64S 1'b0
`define OR1200_CPUCFGR_OV64S 1'b0
`define OR1200_CPUCFGR_RES1 22'h000000
// DMMUCFGR fields
`define OR1200_DMMUCFGR_NTW_BITS 1:0
`define OR1200_DMMUCFGR_NTS_BITS 4:2
`define OR1200_DMMUCFGR_NAE_BITS 7:5
`define OR1200_DMMUCFGR_CRI_BITS 8
`define OR1200_DMMUCFGR_PRI_BITS 9
`define OR1200_DMMUCFGR_TEIRI_BITS 10
`define OR1200_DMMUCFGR_HTR_BITS 11
`define OR1200_DMMUCFGR_RES1_BITS 31:12
// DMMUCFGR values
`ifdef OR1200_NO_DMMU
`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_RES1 20'h00000
`else
`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_DMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl.
`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_DMMUCFGR_RES1 20'h00000
`endif
// IMMUCFGR fields
`define OR1200_IMMUCFGR_NTW_BITS 1:0
`define OR1200_IMMUCFGR_NTS_BITS 4:2
`define OR1200_IMMUCFGR_NAE_BITS 7:5
`define OR1200_IMMUCFGR_CRI_BITS 8
`define OR1200_IMMUCFGR_PRI_BITS 9
`define OR1200_IMMUCFGR_TEIRI_BITS 10
`define OR1200_IMMUCFGR_HTR_BITS 11
`define OR1200_IMMUCFGR_RES1_BITS 31:12
// IMMUCFGR values
`ifdef OR1200_NO_IMMU
`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_RES1 20'h00000
`else
`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_IMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl
`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_IMMUCFGR_RES1 20'h00000
`endif
// DCCFGR fields
`define OR1200_DCCFGR_NCW_BITS 2:0
`define OR1200_DCCFGR_NCS_BITS 6:3
`define OR1200_DCCFGR_CBS_BITS 7
`define OR1200_DCCFGR_CWS_BITS 8
`define OR1200_DCCFGR_CCRI_BITS 9
`define OR1200_DCCFGR_CBIRI_BITS 10
`define OR1200_DCCFGR_CBPRI_BITS 11
`define OR1200_DCCFGR_CBLRI_BITS 12
`define OR1200_DCCFGR_CBFRI_BITS 13
`define OR1200_DCCFGR_CBWBRI_BITS 14
`define OR1200_DCCFGR_RES1_BITS 31:15
// DCCFGR values
`ifdef OR1200_NO_DC
`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant
`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant
`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CCRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBIRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBFRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_RES1 17'h00000
`else
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
`ifdef OR1200_DC_WRITETHROUGH
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
`else
`define OR1200_DCCFGR_CWS 1'b1 // Write-back strategy
`endif
`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`ifdef OR1200_DC_WRITETHROUGH
`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl.
`else
`define OR1200_DCCFGR_CBWBRI 1'b1 // Cache block WB reg impl.
`endif
`define OR1200_DCCFGR_RES1 17'h00000
`endif
// ICCFGR fields
`define OR1200_ICCFGR_NCW_BITS 2:0
`define OR1200_ICCFGR_NCS_BITS 6:3
`define OR1200_ICCFGR_CBS_BITS 7
`define OR1200_ICCFGR_CWS_BITS 8
`define OR1200_ICCFGR_CCRI_BITS 9
`define OR1200_ICCFGR_CBIRI_BITS 10
`define OR1200_ICCFGR_CBPRI_BITS 11
`define OR1200_ICCFGR_CBLRI_BITS 12
`define OR1200_ICCFGR_CBFRI_BITS 13
`define OR1200_ICCFGR_CBWBRI_BITS 14
`define OR1200_ICCFGR_RES1_BITS 31:15
// ICCFGR values
`ifdef OR1200_NO_IC
`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant
`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant
`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`else
`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1 // 16 byte cache block
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`endif
// DCFGR fields
`define OR1200_DCFGR_NDP_BITS 3:0
`define OR1200_DCFGR_WPCI_BITS 4
`define OR1200_DCFGR_RES1_BITS 31:5
// DCFGR values
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DCFGR_NDP 4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
`ifdef OR1200_DU_DWCR0
`define OR1200_DCFGR_WPCI 1'b1
`else
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`else
`define OR1200_DCFGR_NDP 4'h0 // Zero DVR/DCR pairs
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`define OR1200_DCFGR_RES1 27'd0
///////////////////////////////////////////////////////////////////////////////
// Boot Address Selection //
// //
// Allows a definable boot address, potentially different to the usual reset //
// vector to allow for power-on code to be run, if desired. //
// //
// OR1200_BOOT_ADR should be the 32-bit address of the boot location //
// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2) //
// //
// For default reset behavior uncomment the settings under the "Boot 0x100" //
// comment below. //
// //
///////////////////////////////////////////////////////////////////////////////
// Boot from 0xf0000100
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
//`define OR1200_BOOT_ADR 32'hf0000100
// Boot from 0x100
`define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
`define OR1200_BOOT_ADR 32'h00000100
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