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/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_dma # (
parameter P_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_read_req_size,
input pcie_rx_cmd_wr_en,
input [33:0] pcie_rx_cmd_wr_data,
output pcie_rx_cmd_full_n,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [P_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n
);
wire w_pcie_rx_cmd_rd_en;
wire [33:0] w_pcie_rx_cmd_rd_data;
wire w_pcie_rx_cmd_empty_n;
wire w_pcie_tag_alloc;
wire [7:0] w_pcie_alloc_tag;
wire [9:4] w_pcie_tag_alloc_len;
wire w_pcie_tag_full_n;
wire w_pcie_rx_fifo_full_n;
wire w_fifo_wr_en;
wire [8:0] w_fifo_wr_addr;
wire [127:0] w_fifo_wr_data;
wire [9:0] w_rear_full_addr;
wire [9:0] w_rear_addr;
pcie_rx_cmd_fifo
pcie_rx_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (pcie_rx_cmd_wr_en),
.wr_data (pcie_rx_cmd_wr_data),
.full_n (pcie_rx_cmd_full_n),
.rd_en (w_pcie_rx_cmd_rd_en),
.rd_data (w_pcie_rx_cmd_rd_data),
.empty_n (w_pcie_rx_cmd_empty_n)
);
pcie_rx_fifo
pcie_rx_fifo_inst0
(
.wr_clk (pcie_user_clk),
.wr_rst_n (pcie_user_rst_n),
.wr_en (w_fifo_wr_en),
.wr_addr (w_fifo_wr_addr),
.wr_data (w_fifo_wr_data),
.rear_full_addr (w_rear_full_addr),
.rear_addr (w_rear_addr),
.alloc_len (w_pcie_tag_alloc_len),
.full_n (w_pcie_rx_fifo_full_n),
.rd_clk (dma_bus_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (pcie_rx_fifo_rd_en),
.rd_data (pcie_rx_fifo_rd_data),
.free_en (pcie_rx_fifo_free_en),
.free_len (pcie_rx_fifo_free_len),
.empty_n (pcie_rx_fifo_empty_n)
);
pcie_rx_tag
pcie_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_pcie_tag_alloc),
.pcie_alloc_tag (w_pcie_alloc_tag),
.pcie_tag_alloc_len (w_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.cpld_fifo_tag (cpld_dma_fifo_tag),
.cpld_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_fifo_tag_last (cpld_dma_fifo_tag_last),
.fifo_wr_en (w_fifo_wr_en),
.fifo_wr_addr (w_fifo_wr_addr),
.fifo_wr_data (w_fifo_wr_data),
.rear_full_addr (w_rear_full_addr),
.rear_addr (w_rear_addr)
);
pcie_rx_req # (
.P_PCIE_DATA_WIDTH (P_PCIE_DATA_WIDTH),
.C_PCIE_ADDR_WIDTH (C_PCIE_ADDR_WIDTH)
)
pcie_rx_req_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_rd_en (w_pcie_rx_cmd_rd_en),
.pcie_rx_cmd_rd_data (w_pcie_rx_cmd_rd_data),
.pcie_rx_cmd_empty_n (w_pcie_rx_cmd_empty_n),
.pcie_tag_alloc (w_pcie_tag_alloc),
.pcie_alloc_tag (w_pcie_alloc_tag),
.pcie_tag_alloc_len (w_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.pcie_rx_fifo_full_n (w_pcie_rx_fifo_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_dma # (
parameter P_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_read_req_size,
input pcie_rx_cmd_wr_en,
input [33:0] pcie_rx_cmd_wr_data,
output pcie_rx_cmd_full_n,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [P_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n
);
wire w_pcie_rx_cmd_rd_en;
wire [33:0] w_pcie_rx_cmd_rd_data;
wire w_pcie_rx_cmd_empty_n;
wire w_pcie_tag_alloc;
wire [7:0] w_pcie_alloc_tag;
wire [9:4] w_pcie_tag_alloc_len;
wire w_pcie_tag_full_n;
wire w_pcie_rx_fifo_full_n;
wire w_fifo_wr_en;
wire [8:0] w_fifo_wr_addr;
wire [127:0] w_fifo_wr_data;
wire [9:0] w_rear_full_addr;
wire [9:0] w_rear_addr;
pcie_rx_cmd_fifo
pcie_rx_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (pcie_rx_cmd_wr_en),
.wr_data (pcie_rx_cmd_wr_data),
.full_n (pcie_rx_cmd_full_n),
.rd_en (w_pcie_rx_cmd_rd_en),
.rd_data (w_pcie_rx_cmd_rd_data),
.empty_n (w_pcie_rx_cmd_empty_n)
);
pcie_rx_fifo
pcie_rx_fifo_inst0
(
.wr_clk (pcie_user_clk),
.wr_rst_n (pcie_user_rst_n),
.wr_en (w_fifo_wr_en),
.wr_addr (w_fifo_wr_addr),
.wr_data (w_fifo_wr_data),
.rear_full_addr (w_rear_full_addr),
.rear_addr (w_rear_addr),
.alloc_len (w_pcie_tag_alloc_len),
.full_n (w_pcie_rx_fifo_full_n),
.rd_clk (dma_bus_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (pcie_rx_fifo_rd_en),
.rd_data (pcie_rx_fifo_rd_data),
.free_en (pcie_rx_fifo_free_en),
.free_len (pcie_rx_fifo_free_len),
.empty_n (pcie_rx_fifo_empty_n)
);
pcie_rx_tag
pcie_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_pcie_tag_alloc),
.pcie_alloc_tag (w_pcie_alloc_tag),
.pcie_tag_alloc_len (w_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.cpld_fifo_tag (cpld_dma_fifo_tag),
.cpld_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_fifo_tag_last (cpld_dma_fifo_tag_last),
.fifo_wr_en (w_fifo_wr_en),
.fifo_wr_addr (w_fifo_wr_addr),
.fifo_wr_data (w_fifo_wr_data),
.rear_full_addr (w_rear_full_addr),
.rear_addr (w_rear_addr)
);
pcie_rx_req # (
.P_PCIE_DATA_WIDTH (P_PCIE_DATA_WIDTH),
.C_PCIE_ADDR_WIDTH (C_PCIE_ADDR_WIDTH)
)
pcie_rx_req_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_rd_en (w_pcie_rx_cmd_rd_en),
.pcie_rx_cmd_rd_data (w_pcie_rx_cmd_rd_data),
.pcie_rx_cmd_empty_n (w_pcie_rx_cmd_empty_n),
.pcie_tag_alloc (w_pcie_tag_alloc),
.pcie_alloc_tag (w_pcie_alloc_tag),
.pcie_tag_alloc_len (w_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.pcie_rx_fifo_full_n (w_pcie_rx_fifo_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack)
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg check;
initial check = 1'b0;
Genit g (.clk(clk), .check(check));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
check <= 1'b0;
end
else if (cyc==1) begin
check <= 1'b1;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile("obj_dir/t_gen_intdot2/t_gen_intdot.vcd");
$dumpvars(12, t);
end
`endif
endmodule
module One;
wire one = 1'b1;
endmodule
module Genit (
input clk,
input check);
// ARRAY
One cellarray1[1:0] (); //cellarray[0..1][0..1]
always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop;
always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop;
// IF
generate
// genblk1 refers to the if's name, not the "generate" itself.
if (1'b1) // IMPLIED begin: genblk1
One ifcell1(); // genblk1.ifcell1
else
One ifcell1(); // genblk1.ifcell1
endgenerate
// On compliant simulators "Implicit name" not allowed here; IE we can't use "genblk1" etc
`ifdef verilator
always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
begin : namedif2
if (1'b1)
One ifcell2(); // namedif2.genblk1.ifcell2
end
endgenerate
`ifdef verilator
always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
if (1'b1)
begin : namedif3
One ifcell3(); // namedif3.ifcell3
end
endgenerate
always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop;
// CASE
generate
case (1'b1)
1'b1 :
One casecell10(); // genblk3.casecell10
endcase
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk3.casecell10.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
case (1'b1)
1'b1 : begin : namedcase11
One casecell11();
end
endcase
endgenerate
always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop;
genvar i;
genvar j;
// IF
generate
for (i = 0; i < 2; i = i + 1)
One cellfor20 (); // genblk4[0..1].cellfor20
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk4[0].cellfor20.one !== 1'b1) $stop;
always @ (posedge clk) if (genblk4[1].cellfor20.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
// COMBO
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor21
One cellfor21 (); // namedfor21[0..1].cellfor21
end
endgenerate
always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop;
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor30
for (j = 0; j < 2; j = j + 1)
begin : forb30
if (j == 0)
begin : forif30
One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a
end
else
`ifdef verilator
begin : forif30b
`else
begin : forif30 // forif30 seems to work on some simulators, not verilator yet
`endif
One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b
end
end
end
endgenerate
always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
`ifdef verilator
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
`else
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
`endif
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg check;
initial check = 1'b0;
Genit g (.clk(clk), .check(check));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
check <= 1'b0;
end
else if (cyc==1) begin
check <= 1'b1;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile("obj_dir/t_gen_intdot2/t_gen_intdot.vcd");
$dumpvars(12, t);
end
`endif
endmodule
module One;
wire one = 1'b1;
endmodule
module Genit (
input clk,
input check);
// ARRAY
One cellarray1[1:0] (); //cellarray[0..1][0..1]
always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop;
always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop;
// IF
generate
// genblk1 refers to the if's name, not the "generate" itself.
if (1'b1) // IMPLIED begin: genblk1
One ifcell1(); // genblk1.ifcell1
else
One ifcell1(); // genblk1.ifcell1
endgenerate
// On compliant simulators "Implicit name" not allowed here; IE we can't use "genblk1" etc
`ifdef verilator
always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
begin : namedif2
if (1'b1)
One ifcell2(); // namedif2.genblk1.ifcell2
end
endgenerate
`ifdef verilator
always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
if (1'b1)
begin : namedif3
One ifcell3(); // namedif3.ifcell3
end
endgenerate
always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop;
// CASE
generate
case (1'b1)
1'b1 :
One casecell10(); // genblk3.casecell10
endcase
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk3.casecell10.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
case (1'b1)
1'b1 : begin : namedcase11
One casecell11();
end
endcase
endgenerate
always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop;
genvar i;
genvar j;
// IF
generate
for (i = 0; i < 2; i = i + 1)
One cellfor20 (); // genblk4[0..1].cellfor20
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk4[0].cellfor20.one !== 1'b1) $stop;
always @ (posedge clk) if (genblk4[1].cellfor20.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
// COMBO
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor21
One cellfor21 (); // namedfor21[0..1].cellfor21
end
endgenerate
always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop;
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor30
for (j = 0; j < 2; j = j + 1)
begin : forb30
if (j == 0)
begin : forif30
One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a
end
else
`ifdef verilator
begin : forif30b
`else
begin : forif30 // forif30 seems to work on some simulators, not verilator yet
`endif
One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b
end
end
end
endgenerate
always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
`ifdef verilator
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
`else
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
`endif
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg check;
initial check = 1'b0;
Genit g (.clk(clk), .check(check));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
check <= 1'b0;
end
else if (cyc==1) begin
check <= 1'b1;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile("obj_dir/t_gen_intdot2/t_gen_intdot.vcd");
$dumpvars(12, t);
end
`endif
endmodule
module One;
wire one = 1'b1;
endmodule
module Genit (
input clk,
input check);
// ARRAY
One cellarray1[1:0] (); //cellarray[0..1][0..1]
always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop;
always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop;
// IF
generate
// genblk1 refers to the if's name, not the "generate" itself.
if (1'b1) // IMPLIED begin: genblk1
One ifcell1(); // genblk1.ifcell1
else
One ifcell1(); // genblk1.ifcell1
endgenerate
// On compliant simulators "Implicit name" not allowed here; IE we can't use "genblk1" etc
`ifdef verilator
always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
begin : namedif2
if (1'b1)
One ifcell2(); // namedif2.genblk1.ifcell2
end
endgenerate
`ifdef verilator
always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
if (1'b1)
begin : namedif3
One ifcell3(); // namedif3.ifcell3
end
endgenerate
always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop;
// CASE
generate
case (1'b1)
1'b1 :
One casecell10(); // genblk3.casecell10
endcase
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk3.casecell10.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
case (1'b1)
1'b1 : begin : namedcase11
One casecell11();
end
endcase
endgenerate
always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop;
genvar i;
genvar j;
// IF
generate
for (i = 0; i < 2; i = i + 1)
One cellfor20 (); // genblk4[0..1].cellfor20
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk4[0].cellfor20.one !== 1'b1) $stop;
always @ (posedge clk) if (genblk4[1].cellfor20.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
// COMBO
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor21
One cellfor21 (); // namedfor21[0..1].cellfor21
end
endgenerate
always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop;
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor30
for (j = 0; j < 2; j = j + 1)
begin : forb30
if (j == 0)
begin : forif30
One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a
end
else
`ifdef verilator
begin : forif30b
`else
begin : forif30 // forif30 seems to work on some simulators, not verilator yet
`endif
One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b
end
end
end
endgenerate
always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
`ifdef verilator
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
`else
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
`endif
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg check;
initial check = 1'b0;
Genit g (.clk(clk), .check(check));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
check <= 1'b0;
end
else if (cyc==1) begin
check <= 1'b1;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile("obj_dir/t_gen_intdot2/t_gen_intdot.vcd");
$dumpvars(12, t);
end
`endif
endmodule
module One;
wire one = 1'b1;
endmodule
module Genit (
input clk,
input check);
// ARRAY
One cellarray1[1:0] (); //cellarray[0..1][0..1]
always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop;
always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop;
// IF
generate
// genblk1 refers to the if's name, not the "generate" itself.
if (1'b1) // IMPLIED begin: genblk1
One ifcell1(); // genblk1.ifcell1
else
One ifcell1(); // genblk1.ifcell1
endgenerate
// On compliant simulators "Implicit name" not allowed here; IE we can't use "genblk1" etc
`ifdef verilator
always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
begin : namedif2
if (1'b1)
One ifcell2(); // namedif2.genblk1.ifcell2
end
endgenerate
`ifdef verilator
always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
if (1'b1)
begin : namedif3
One ifcell3(); // namedif3.ifcell3
end
endgenerate
always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop;
// CASE
generate
case (1'b1)
1'b1 :
One casecell10(); // genblk3.casecell10
endcase
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk3.casecell10.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
case (1'b1)
1'b1 : begin : namedcase11
One casecell11();
end
endcase
endgenerate
always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop;
genvar i;
genvar j;
// IF
generate
for (i = 0; i < 2; i = i + 1)
One cellfor20 (); // genblk4[0..1].cellfor20
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk4[0].cellfor20.one !== 1'b1) $stop;
always @ (posedge clk) if (genblk4[1].cellfor20.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
// COMBO
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor21
One cellfor21 (); // namedfor21[0..1].cellfor21
end
endgenerate
always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop;
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor30
for (j = 0; j < 2; j = j + 1)
begin : forb30
if (j == 0)
begin : forif30
One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a
end
else
`ifdef verilator
begin : forif30b
`else
begin : forif30 // forif30 seems to work on some simulators, not verilator yet
`endif
One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b
end
end
end
endgenerate
always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
`ifdef verilator
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
`else
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
`endif
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_pcie # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_ref_clk_p,
input pcie_ref_clk_n,
//PCIe user clock
input pcie_user_clk,
input pcie_user_rst_n,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
output nvme_cc_en,
output [1:0] nvme_cc_shn,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input hcmd_sq_rd_en,
output [18:0] hcmd_sq_rd_data,
output hcmd_sq_empty_n,
input [10:0] hcmd_table_rd_addr,
output [31:0] hcmd_table_rd_data,
input hcmd_cq_wr1_en,
input [34:0] hcmd_cq_wr1_data0,
input [34:0] hcmd_cq_wr1_data1,
output hcmd_cq_wr1_rdy_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n,
input pcie_tx_fifo_alloc_en,
input [9:4] pcie_tx_fifo_alloc_len,
input pcie_tx_fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
output pcie_tx_fifo_full_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n,
output pcie_mreq_err,
output pcie_cpld_err,
output pcie_cpld_len_err,
//PCIe Integrated Block Interface
input [5:0] tx_buf_av,
input tx_err_drop,
input tx_cfg_req,
input s_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_tx_tkeep,
output [3:0] s_axis_tx_tuser,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_cfg_gnt,
input [C_PCIE_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
output rx_np_ok,
output rx_np_req,
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number,
input cfg_to_turnoff,
output cfg_turnoff_ok,
input [15:0] cfg_command,
input [15:0] cfg_dcommand,
input [15:0] cfg_lcommand,
output sys_clk
);
wire w_nvme_intms_ivms;
wire w_nvme_intmc_ivmc;
wire w_cq_irq_status;
wire [7:0] w_hcmd_prp_rd_addr;
wire [44:0] w_hcmd_prp_rd_data;
wire w_hcmd_nlb_wr1_en;
wire [6:0] w_hcmd_nlb_wr1_addr;
wire [18:0] w_hcmd_nlb_wr1_data;
wire w_hcmd_nlb_wr1_rdy_n;
wire [6:0] w_hcmd_nlb_rd_addr;
wire [18:0] w_hcmd_nlb_rd_data;
wire w_hcmd_cq_wr0_en;
wire [34:0] w_hcmd_cq_wr0_data0;
wire [34:0] w_hcmd_cq_wr0_data1;
wire w_hcmd_cq_wr0_rdy_n;
wire w_mreq_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_mreq_fifo_wr_data;
wire [7:0] w_cpld0_fifo_tag;
wire w_cpld0_fifo_tag_last;
wire w_cpld0_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_cpld0_fifo_wr_data;
wire [7:0] w_cpld1_fifo_tag;
wire w_cpld1_fifo_tag_last;
wire w_cpld1_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_cpld1_fifo_wr_data;
wire [7:0] w_cpld2_fifo_tag;
wire w_cpld2_fifo_tag_last;
wire w_cpld2_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_cpld2_fifo_wr_data;
wire w_tx_cpld_req;
wire [7:0] w_tx_cpld_tag;
wire [15:0] w_tx_cpld_req_id;
wire [11:2] w_tx_cpld_len;
wire [11:0] w_tx_cpld_bc;
wire [6:0] w_tx_cpld_laddr;
wire [63:0] w_tx_cpld_data;
wire w_tx_cpld_req_ack;
wire w_tx_mrd0_req;
wire [7:0] w_tx_mrd0_tag;
wire [11:2] w_tx_mrd0_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mrd0_addr;
wire w_tx_mrd0_req_ack;
wire w_tx_mrd1_req;
wire [7:0] w_tx_mrd1_tag;
wire [11:2] w_tx_mrd1_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mrd1_addr;
wire w_tx_mrd1_req_ack;
wire w_tx_mrd2_req;
wire [7:0] w_tx_mrd2_tag;
wire [11:2] w_tx_mrd2_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mrd2_addr;
wire w_tx_mrd2_req_ack;
wire w_tx_mwr0_req;
wire [7:0] w_tx_mwr0_tag;
wire [11:2] w_tx_mwr0_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mwr0_addr;
wire w_tx_mwr0_req_ack;
wire w_tx_mwr0_rd_en;
wire [C_PCIE_DATA_WIDTH-1 : 0] w_tx_mwr0_rd_data;
wire w_tx_mwr0_data_last;
wire w_tx_mwr1_req;
wire [7:0] w_tx_mwr1_tag;
wire [11:2] w_tx_mwr1_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mwr1_addr;
wire w_tx_mwr1_req_ack;
wire w_tx_mwr1_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_tx_mwr1_rd_data;
wire w_tx_mwr1_data_last;
wire [C_PCIE_ADDR_WIDTH-1:2] w_admin_sq_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_admin_cq_bs_addr;
wire [7:0] w_admin_sq_size;
wire [7:0] w_admin_cq_size;
wire [7:0] w_admin_sq_tail_ptr;
wire [7:0] w_io_sq1_tail_ptr;
wire [7:0] w_io_sq2_tail_ptr;
wire [7:0] w_io_sq3_tail_ptr;
wire [7:0] w_io_sq4_tail_ptr;
wire [7:0] w_io_sq5_tail_ptr;
wire [7:0] w_io_sq6_tail_ptr;
wire [7:0] w_io_sq7_tail_ptr;
wire [7:0] w_io_sq8_tail_ptr;
wire [7:0] w_admin_cq_tail_ptr;
wire [7:0] w_io_cq1_tail_ptr;
wire [7:0] w_io_cq2_tail_ptr;
wire [7:0] w_io_cq3_tail_ptr;
wire [7:0] w_io_cq4_tail_ptr;
wire [7:0] w_io_cq5_tail_ptr;
wire [7:0] w_io_cq6_tail_ptr;
wire [7:0] w_io_cq7_tail_ptr;
wire [7:0] w_io_cq8_tail_ptr;
wire [7:0] w_admin_cq_head_ptr;
wire [7:0] w_io_cq1_head_ptr;
wire [7:0] w_io_cq2_head_ptr;
wire [7:0] w_io_cq3_head_ptr;
wire [7:0] w_io_cq4_head_ptr;
wire [7:0] w_io_cq5_head_ptr;
wire [7:0] w_io_cq6_head_ptr;
wire [7:0] w_io_cq7_head_ptr;
wire [7:0] w_io_cq8_head_ptr;
wire [8:0] w_cq_head_update;
reg r_cfg_turnoff_ok;
IBUFDS_GTE2 pcie_ref_clk_ibuf (.O(sys_clk), .ODIV2(), .I(pcie_ref_clk_p), .CEB(1'b0), .IB(pcie_ref_clk_n));
assign cfg_turnoff_ok = r_cfg_turnoff_ok;
always @(posedge pcie_user_clk) begin
r_cfg_turnoff_ok <= cfg_to_turnoff;
end
pcie_cntl_slave # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_cntl_slave_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.rx_np_ok (rx_np_ok),
.rx_np_req (rx_np_req),
.mreq_fifo_wr_en (w_mreq_fifo_wr_en),
.mreq_fifo_wr_data (w_mreq_fifo_wr_data),
.tx_cpld_req (w_tx_cpld_req),
.tx_cpld_tag (w_tx_cpld_tag),
.tx_cpld_req_id (w_tx_cpld_req_id),
.tx_cpld_len (w_tx_cpld_len),
.tx_cpld_bc (w_tx_cpld_bc),
.tx_cpld_laddr (w_tx_cpld_laddr),
.tx_cpld_data (w_tx_cpld_data),
.tx_cpld_req_ack (w_tx_cpld_req_ack),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.nvme_intms_ivms (w_nvme_intms_ivms),
.nvme_intmc_ivmc (w_nvme_intmc_ivmc),
.cq_irq_status (w_cq_irq_status),
.sq_rst_n (sq_rst_n),
.cq_rst_n (cq_rst_n),
.admin_sq_bs_addr (w_admin_sq_bs_addr),
.admin_cq_bs_addr (w_admin_cq_bs_addr),
.admin_sq_size (w_admin_sq_size),
.admin_cq_size (w_admin_cq_size),
.admin_sq_tail_ptr (w_admin_sq_tail_ptr),
.io_sq1_tail_ptr (w_io_sq1_tail_ptr),
.io_sq2_tail_ptr (w_io_sq2_tail_ptr),
.io_sq3_tail_ptr (w_io_sq3_tail_ptr),
.io_sq4_tail_ptr (w_io_sq4_tail_ptr),
.io_sq5_tail_ptr (w_io_sq5_tail_ptr),
.io_sq6_tail_ptr (w_io_sq6_tail_ptr),
.io_sq7_tail_ptr (w_io_sq7_tail_ptr),
.io_sq8_tail_ptr (w_io_sq8_tail_ptr),
.admin_cq_head_ptr (w_admin_cq_head_ptr),
.io_cq1_head_ptr (w_io_cq1_head_ptr),
.io_cq2_head_ptr (w_io_cq2_head_ptr),
.io_cq3_head_ptr (w_io_cq3_head_ptr),
.io_cq4_head_ptr (w_io_cq4_head_ptr),
.io_cq5_head_ptr (w_io_cq5_head_ptr),
.io_cq6_head_ptr (w_io_cq6_head_ptr),
.io_cq7_head_ptr (w_io_cq7_head_ptr),
.io_cq8_head_ptr (w_io_cq8_head_ptr),
.cq_head_update (w_cq_head_update)
);
pcie_hcmd # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.admin_sq_bs_addr (w_admin_sq_bs_addr),
.admin_cq_bs_addr (w_admin_cq_bs_addr),
.admin_sq_size (w_admin_sq_size),
.admin_cq_size (w_admin_cq_size),
.admin_sq_tail_ptr (w_admin_sq_tail_ptr),
.io_sq1_tail_ptr (w_io_sq1_tail_ptr),
.io_sq2_tail_ptr (w_io_sq2_tail_ptr),
.io_sq3_tail_ptr (w_io_sq3_tail_ptr),
.io_sq4_tail_ptr (w_io_sq4_tail_ptr),
.io_sq5_tail_ptr (w_io_sq5_tail_ptr),
.io_sq6_tail_ptr (w_io_sq6_tail_ptr),
.io_sq7_tail_ptr (w_io_sq7_tail_ptr),
.io_sq8_tail_ptr (w_io_sq8_tail_ptr),
.cpld_sq_fifo_tag (w_cpld0_fifo_tag),
.cpld_sq_fifo_wr_data (w_cpld0_fifo_wr_data),
.cpld_sq_fifo_wr_en (w_cpld0_fifo_wr_en),
.cpld_sq_fifo_tag_last (w_cpld0_fifo_tag_last),
.tx_mrd_req (w_tx_mrd0_req),
.tx_mrd_tag (w_tx_mrd0_tag),
.tx_mrd_len (w_tx_mrd0_len),
.tx_mrd_addr (w_tx_mrd0_addr),
.tx_mrd_req_ack (w_tx_mrd0_req_ack),
.admin_cq_tail_ptr (w_admin_cq_tail_ptr),
.io_cq1_tail_ptr (w_io_cq1_tail_ptr),
.io_cq2_tail_ptr (w_io_cq2_tail_ptr),
.io_cq3_tail_ptr (w_io_cq3_tail_ptr),
.io_cq4_tail_ptr (w_io_cq4_tail_ptr),
.io_cq5_tail_ptr (w_io_cq5_tail_ptr),
.io_cq6_tail_ptr (w_io_cq6_tail_ptr),
.io_cq7_tail_ptr (w_io_cq7_tail_ptr),
.io_cq8_tail_ptr (w_io_cq8_tail_ptr),
.tx_cq_mwr_req (w_tx_mwr0_req),
.tx_cq_mwr_tag (w_tx_mwr0_tag),
.tx_cq_mwr_len (w_tx_mwr0_len),
.tx_cq_mwr_addr (w_tx_mwr0_addr),
.tx_cq_mwr_req_ack (w_tx_mwr0_req_ack),
.tx_cq_mwr_rd_en (w_tx_mwr0_rd_en),
.tx_cq_mwr_rd_data (w_tx_mwr0_rd_data),
.tx_cq_mwr_data_last (w_tx_mwr0_data_last),
.hcmd_prp_rd_addr (w_hcmd_prp_rd_addr),
.hcmd_prp_rd_data (w_hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (w_hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (w_hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (w_hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (w_hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (w_hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (w_hcmd_nlb_rd_data),
.hcmd_cq_wr0_en (w_hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (w_hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (w_hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (w_hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.sq_rst_n (sq_rst_n),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n),
.hcmd_table_rd_addr (hcmd_table_rd_addr),
.hcmd_table_rd_data (hcmd_table_rd_data),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n)
);
dma_if
dma_if_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_payload_size (cfg_dcommand[7:5]),
.pcie_max_read_req_size (cfg_dcommand[14:12]),
.pcie_rcb (cfg_lcommand[3]),
.hcmd_prp_rd_addr (w_hcmd_prp_rd_addr),
.hcmd_prp_rd_data (w_hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (w_hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (w_hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (w_hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (w_hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (w_hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (w_hcmd_nlb_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.tx_prp_mrd_req (w_tx_mrd1_req),
.tx_prp_mrd_tag (w_tx_mrd1_tag),
.tx_prp_mrd_len (w_tx_mrd1_len),
.tx_prp_mrd_addr (w_tx_mrd1_addr),
.tx_prp_mrd_req_ack (w_tx_mrd1_req_ack),
.cpld_prp_fifo_tag (w_cpld1_fifo_tag),
.cpld_prp_fifo_wr_data (w_cpld1_fifo_wr_data),
.cpld_prp_fifo_wr_en (w_cpld1_fifo_wr_en),
.cpld_prp_fifo_tag_last (w_cpld1_fifo_tag_last),
.tx_dma_mrd_req (w_tx_mrd2_req),
.tx_dma_mrd_tag (w_tx_mrd2_tag),
.tx_dma_mrd_len (w_tx_mrd2_len),
.tx_dma_mrd_addr (w_tx_mrd2_addr),
.tx_dma_mrd_req_ack (w_tx_mrd2_req_ack),
.cpld_dma_fifo_tag (w_cpld2_fifo_tag),
.cpld_dma_fifo_wr_data (w_cpld2_fifo_wr_data),
.cpld_dma_fifo_wr_en (w_cpld2_fifo_wr_en),
.cpld_dma_fifo_tag_last (w_cpld2_fifo_tag_last),
.tx_dma_mwr_req (w_tx_mwr1_req),
.tx_dma_mwr_tag (w_tx_mwr1_tag),
.tx_dma_mwr_len (w_tx_mwr1_len),
.tx_dma_mwr_addr (w_tx_mwr1_addr),
.tx_dma_mwr_req_ack (w_tx_mwr1_req_ack),
.tx_dma_mwr_data_last (w_tx_mwr1_data_last),
.pcie_tx_dma_fifo_rd_en (w_tx_mwr1_rd_en),
.pcie_tx_dma_fifo_rd_data (w_tx_mwr1_rd_data),
.hcmd_cq_wr0_en (w_hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (w_hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (w_hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (w_hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_tans_if # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tans_if_inst0(
//PCIe user clock
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
//pcie rx signal
.mreq_fifo_wr_en (w_mreq_fifo_wr_en),
.mreq_fifo_wr_data (w_mreq_fifo_wr_data),
.cpld0_fifo_tag (w_cpld0_fifo_tag),
.cpld0_fifo_tag_last (w_cpld0_fifo_tag_last),
.cpld0_fifo_wr_en (w_cpld0_fifo_wr_en),
.cpld0_fifo_wr_data (w_cpld0_fifo_wr_data),
.cpld1_fifo_tag (w_cpld1_fifo_tag),
.cpld1_fifo_tag_last (w_cpld1_fifo_tag_last),
.cpld1_fifo_wr_en (w_cpld1_fifo_wr_en),
.cpld1_fifo_wr_data (w_cpld1_fifo_wr_data),
.cpld2_fifo_tag (w_cpld2_fifo_tag),
.cpld2_fifo_tag_last (w_cpld2_fifo_tag_last),
.cpld2_fifo_wr_en (w_cpld2_fifo_wr_en),
.cpld2_fifo_wr_data (w_cpld2_fifo_wr_data),
.tx_cpld_req (w_tx_cpld_req),
.tx_cpld_tag (w_tx_cpld_tag),
.tx_cpld_req_id (w_tx_cpld_req_id),
.tx_cpld_len (w_tx_cpld_len),
.tx_cpld_bc (w_tx_cpld_bc),
.tx_cpld_laddr (w_tx_cpld_laddr),
.tx_cpld_data (w_tx_cpld_data),
.tx_cpld_req_ack (w_tx_cpld_req_ack),
.tx_mrd0_req (w_tx_mrd0_req),
.tx_mrd0_tag (w_tx_mrd0_tag),
.tx_mrd0_len (w_tx_mrd0_len),
.tx_mrd0_addr (w_tx_mrd0_addr),
.tx_mrd0_req_ack (w_tx_mrd0_req_ack),
.tx_mrd1_req (w_tx_mrd1_req),
.tx_mrd1_tag (w_tx_mrd1_tag),
.tx_mrd1_len (w_tx_mrd1_len),
.tx_mrd1_addr (w_tx_mrd1_addr),
.tx_mrd1_req_ack (w_tx_mrd1_req_ack),
.tx_mrd2_req (w_tx_mrd2_req),
.tx_mrd2_tag (w_tx_mrd2_tag),
.tx_mrd2_len (w_tx_mrd2_len),
.tx_mrd2_addr (w_tx_mrd2_addr),
.tx_mrd2_req_ack (w_tx_mrd2_req_ack),
.tx_mwr0_req (w_tx_mwr0_req),
.tx_mwr0_tag (w_tx_mwr0_tag),
.tx_mwr0_len (w_tx_mwr0_len),
.tx_mwr0_addr (w_tx_mwr0_addr),
.tx_mwr0_req_ack (w_tx_mwr0_req_ack),
.tx_mwr0_rd_en (w_tx_mwr0_rd_en),
.tx_mwr0_rd_data (w_tx_mwr0_rd_data),
.tx_mwr0_data_last (w_tx_mwr0_data_last),
.tx_mwr1_req (w_tx_mwr1_req),
.tx_mwr1_tag (w_tx_mwr1_tag),
.tx_mwr1_len (w_tx_mwr1_len),
.tx_mwr1_addr (w_tx_mwr1_addr),
.tx_mwr1_req_ack (w_tx_mwr1_req_ack),
.tx_mwr1_rd_en (w_tx_mwr1_rd_en),
.tx_mwr1_rd_data (w_tx_mwr1_rd_data),
.tx_mwr1_data_last (w_tx_mwr1_data_last),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.tx_buf_av (tx_buf_av),
.tx_err_drop (tx_err_drop),
.tx_cfg_req (tx_cfg_req),
.s_axis_tx_tready (s_axis_tx_tready),
.s_axis_tx_tdata (s_axis_tx_tdata),
.s_axis_tx_tkeep (s_axis_tx_tkeep),
.s_axis_tx_tuser (s_axis_tx_tuser),
.s_axis_tx_tlast (s_axis_tx_tlast),
.s_axis_tx_tvalid (s_axis_tx_tvalid),
.tx_cfg_gnt (tx_cfg_gnt),
.m_axis_rx_tdata (m_axis_rx_tdata),
.m_axis_rx_tkeep (m_axis_rx_tkeep),
.m_axis_rx_tlast (m_axis_rx_tlast),
.m_axis_rx_tvalid (m_axis_rx_tvalid),
.m_axis_rx_tready (m_axis_rx_tready),
.m_axis_rx_tuser (m_axis_rx_tuser),
.fc_cpld (fc_cpld),
.fc_cplh (fc_cplh),
.fc_npd (fc_npd),
.fc_nph (fc_nph),
.fc_pd (fc_pd),
.fc_ph (fc_ph),
.fc_sel (fc_sel),
.cfg_bus_number (cfg_bus_number),
.cfg_device_number (cfg_device_number),
.cfg_function_number (cfg_function_number)
);
nvme_irq
nvme_irq_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.nvme_intms_ivms (w_nvme_intms_ivms),
.nvme_intmc_ivmc (w_nvme_intmc_ivmc),
.cq_irq_status (w_cq_irq_status),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.admin_cq_tail_ptr (w_admin_cq_tail_ptr),
.io_cq1_tail_ptr (w_io_cq1_tail_ptr),
.io_cq2_tail_ptr (w_io_cq2_tail_ptr),
.io_cq3_tail_ptr (w_io_cq3_tail_ptr),
.io_cq4_tail_ptr (w_io_cq4_tail_ptr),
.io_cq5_tail_ptr (w_io_cq5_tail_ptr),
.io_cq6_tail_ptr (w_io_cq6_tail_ptr),
.io_cq7_tail_ptr (w_io_cq7_tail_ptr),
.io_cq8_tail_ptr (w_io_cq8_tail_ptr),
.admin_cq_head_ptr (w_admin_cq_head_ptr),
.io_cq1_head_ptr (w_io_cq1_head_ptr),
.io_cq2_head_ptr (w_io_cq2_head_ptr),
.io_cq3_head_ptr (w_io_cq3_head_ptr),
.io_cq4_head_ptr (w_io_cq4_head_ptr),
.io_cq5_head_ptr (w_io_cq5_head_ptr),
.io_cq6_head_ptr (w_io_cq6_head_ptr),
.io_cq7_head_ptr (w_io_cq7_head_ptr),
.io_cq8_head_ptr (w_io_cq8_head_ptr),
.cq_head_update (w_cq_head_update)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_pcie # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_ref_clk_p,
input pcie_ref_clk_n,
//PCIe user clock
input pcie_user_clk,
input pcie_user_rst_n,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
output nvme_cc_en,
output [1:0] nvme_cc_shn,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input hcmd_sq_rd_en,
output [18:0] hcmd_sq_rd_data,
output hcmd_sq_empty_n,
input [10:0] hcmd_table_rd_addr,
output [31:0] hcmd_table_rd_data,
input hcmd_cq_wr1_en,
input [34:0] hcmd_cq_wr1_data0,
input [34:0] hcmd_cq_wr1_data1,
output hcmd_cq_wr1_rdy_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n,
input pcie_tx_fifo_alloc_en,
input [9:4] pcie_tx_fifo_alloc_len,
input pcie_tx_fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
output pcie_tx_fifo_full_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n,
output pcie_mreq_err,
output pcie_cpld_err,
output pcie_cpld_len_err,
//PCIe Integrated Block Interface
input [5:0] tx_buf_av,
input tx_err_drop,
input tx_cfg_req,
input s_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_tx_tkeep,
output [3:0] s_axis_tx_tuser,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_cfg_gnt,
input [C_PCIE_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
output rx_np_ok,
output rx_np_req,
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number,
input cfg_to_turnoff,
output cfg_turnoff_ok,
input [15:0] cfg_command,
input [15:0] cfg_dcommand,
input [15:0] cfg_lcommand,
output sys_clk
);
wire w_nvme_intms_ivms;
wire w_nvme_intmc_ivmc;
wire w_cq_irq_status;
wire [7:0] w_hcmd_prp_rd_addr;
wire [44:0] w_hcmd_prp_rd_data;
wire w_hcmd_nlb_wr1_en;
wire [6:0] w_hcmd_nlb_wr1_addr;
wire [18:0] w_hcmd_nlb_wr1_data;
wire w_hcmd_nlb_wr1_rdy_n;
wire [6:0] w_hcmd_nlb_rd_addr;
wire [18:0] w_hcmd_nlb_rd_data;
wire w_hcmd_cq_wr0_en;
wire [34:0] w_hcmd_cq_wr0_data0;
wire [34:0] w_hcmd_cq_wr0_data1;
wire w_hcmd_cq_wr0_rdy_n;
wire w_mreq_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_mreq_fifo_wr_data;
wire [7:0] w_cpld0_fifo_tag;
wire w_cpld0_fifo_tag_last;
wire w_cpld0_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_cpld0_fifo_wr_data;
wire [7:0] w_cpld1_fifo_tag;
wire w_cpld1_fifo_tag_last;
wire w_cpld1_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_cpld1_fifo_wr_data;
wire [7:0] w_cpld2_fifo_tag;
wire w_cpld2_fifo_tag_last;
wire w_cpld2_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_cpld2_fifo_wr_data;
wire w_tx_cpld_req;
wire [7:0] w_tx_cpld_tag;
wire [15:0] w_tx_cpld_req_id;
wire [11:2] w_tx_cpld_len;
wire [11:0] w_tx_cpld_bc;
wire [6:0] w_tx_cpld_laddr;
wire [63:0] w_tx_cpld_data;
wire w_tx_cpld_req_ack;
wire w_tx_mrd0_req;
wire [7:0] w_tx_mrd0_tag;
wire [11:2] w_tx_mrd0_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mrd0_addr;
wire w_tx_mrd0_req_ack;
wire w_tx_mrd1_req;
wire [7:0] w_tx_mrd1_tag;
wire [11:2] w_tx_mrd1_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mrd1_addr;
wire w_tx_mrd1_req_ack;
wire w_tx_mrd2_req;
wire [7:0] w_tx_mrd2_tag;
wire [11:2] w_tx_mrd2_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mrd2_addr;
wire w_tx_mrd2_req_ack;
wire w_tx_mwr0_req;
wire [7:0] w_tx_mwr0_tag;
wire [11:2] w_tx_mwr0_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mwr0_addr;
wire w_tx_mwr0_req_ack;
wire w_tx_mwr0_rd_en;
wire [C_PCIE_DATA_WIDTH-1 : 0] w_tx_mwr0_rd_data;
wire w_tx_mwr0_data_last;
wire w_tx_mwr1_req;
wire [7:0] w_tx_mwr1_tag;
wire [11:2] w_tx_mwr1_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mwr1_addr;
wire w_tx_mwr1_req_ack;
wire w_tx_mwr1_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_tx_mwr1_rd_data;
wire w_tx_mwr1_data_last;
wire [C_PCIE_ADDR_WIDTH-1:2] w_admin_sq_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_admin_cq_bs_addr;
wire [7:0] w_admin_sq_size;
wire [7:0] w_admin_cq_size;
wire [7:0] w_admin_sq_tail_ptr;
wire [7:0] w_io_sq1_tail_ptr;
wire [7:0] w_io_sq2_tail_ptr;
wire [7:0] w_io_sq3_tail_ptr;
wire [7:0] w_io_sq4_tail_ptr;
wire [7:0] w_io_sq5_tail_ptr;
wire [7:0] w_io_sq6_tail_ptr;
wire [7:0] w_io_sq7_tail_ptr;
wire [7:0] w_io_sq8_tail_ptr;
wire [7:0] w_admin_cq_tail_ptr;
wire [7:0] w_io_cq1_tail_ptr;
wire [7:0] w_io_cq2_tail_ptr;
wire [7:0] w_io_cq3_tail_ptr;
wire [7:0] w_io_cq4_tail_ptr;
wire [7:0] w_io_cq5_tail_ptr;
wire [7:0] w_io_cq6_tail_ptr;
wire [7:0] w_io_cq7_tail_ptr;
wire [7:0] w_io_cq8_tail_ptr;
wire [7:0] w_admin_cq_head_ptr;
wire [7:0] w_io_cq1_head_ptr;
wire [7:0] w_io_cq2_head_ptr;
wire [7:0] w_io_cq3_head_ptr;
wire [7:0] w_io_cq4_head_ptr;
wire [7:0] w_io_cq5_head_ptr;
wire [7:0] w_io_cq6_head_ptr;
wire [7:0] w_io_cq7_head_ptr;
wire [7:0] w_io_cq8_head_ptr;
wire [8:0] w_cq_head_update;
reg r_cfg_turnoff_ok;
IBUFDS_GTE2 pcie_ref_clk_ibuf (.O(sys_clk), .ODIV2(), .I(pcie_ref_clk_p), .CEB(1'b0), .IB(pcie_ref_clk_n));
assign cfg_turnoff_ok = r_cfg_turnoff_ok;
always @(posedge pcie_user_clk) begin
r_cfg_turnoff_ok <= cfg_to_turnoff;
end
pcie_cntl_slave # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_cntl_slave_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.rx_np_ok (rx_np_ok),
.rx_np_req (rx_np_req),
.mreq_fifo_wr_en (w_mreq_fifo_wr_en),
.mreq_fifo_wr_data (w_mreq_fifo_wr_data),
.tx_cpld_req (w_tx_cpld_req),
.tx_cpld_tag (w_tx_cpld_tag),
.tx_cpld_req_id (w_tx_cpld_req_id),
.tx_cpld_len (w_tx_cpld_len),
.tx_cpld_bc (w_tx_cpld_bc),
.tx_cpld_laddr (w_tx_cpld_laddr),
.tx_cpld_data (w_tx_cpld_data),
.tx_cpld_req_ack (w_tx_cpld_req_ack),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.nvme_intms_ivms (w_nvme_intms_ivms),
.nvme_intmc_ivmc (w_nvme_intmc_ivmc),
.cq_irq_status (w_cq_irq_status),
.sq_rst_n (sq_rst_n),
.cq_rst_n (cq_rst_n),
.admin_sq_bs_addr (w_admin_sq_bs_addr),
.admin_cq_bs_addr (w_admin_cq_bs_addr),
.admin_sq_size (w_admin_sq_size),
.admin_cq_size (w_admin_cq_size),
.admin_sq_tail_ptr (w_admin_sq_tail_ptr),
.io_sq1_tail_ptr (w_io_sq1_tail_ptr),
.io_sq2_tail_ptr (w_io_sq2_tail_ptr),
.io_sq3_tail_ptr (w_io_sq3_tail_ptr),
.io_sq4_tail_ptr (w_io_sq4_tail_ptr),
.io_sq5_tail_ptr (w_io_sq5_tail_ptr),
.io_sq6_tail_ptr (w_io_sq6_tail_ptr),
.io_sq7_tail_ptr (w_io_sq7_tail_ptr),
.io_sq8_tail_ptr (w_io_sq8_tail_ptr),
.admin_cq_head_ptr (w_admin_cq_head_ptr),
.io_cq1_head_ptr (w_io_cq1_head_ptr),
.io_cq2_head_ptr (w_io_cq2_head_ptr),
.io_cq3_head_ptr (w_io_cq3_head_ptr),
.io_cq4_head_ptr (w_io_cq4_head_ptr),
.io_cq5_head_ptr (w_io_cq5_head_ptr),
.io_cq6_head_ptr (w_io_cq6_head_ptr),
.io_cq7_head_ptr (w_io_cq7_head_ptr),
.io_cq8_head_ptr (w_io_cq8_head_ptr),
.cq_head_update (w_cq_head_update)
);
pcie_hcmd # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.admin_sq_bs_addr (w_admin_sq_bs_addr),
.admin_cq_bs_addr (w_admin_cq_bs_addr),
.admin_sq_size (w_admin_sq_size),
.admin_cq_size (w_admin_cq_size),
.admin_sq_tail_ptr (w_admin_sq_tail_ptr),
.io_sq1_tail_ptr (w_io_sq1_tail_ptr),
.io_sq2_tail_ptr (w_io_sq2_tail_ptr),
.io_sq3_tail_ptr (w_io_sq3_tail_ptr),
.io_sq4_tail_ptr (w_io_sq4_tail_ptr),
.io_sq5_tail_ptr (w_io_sq5_tail_ptr),
.io_sq6_tail_ptr (w_io_sq6_tail_ptr),
.io_sq7_tail_ptr (w_io_sq7_tail_ptr),
.io_sq8_tail_ptr (w_io_sq8_tail_ptr),
.cpld_sq_fifo_tag (w_cpld0_fifo_tag),
.cpld_sq_fifo_wr_data (w_cpld0_fifo_wr_data),
.cpld_sq_fifo_wr_en (w_cpld0_fifo_wr_en),
.cpld_sq_fifo_tag_last (w_cpld0_fifo_tag_last),
.tx_mrd_req (w_tx_mrd0_req),
.tx_mrd_tag (w_tx_mrd0_tag),
.tx_mrd_len (w_tx_mrd0_len),
.tx_mrd_addr (w_tx_mrd0_addr),
.tx_mrd_req_ack (w_tx_mrd0_req_ack),
.admin_cq_tail_ptr (w_admin_cq_tail_ptr),
.io_cq1_tail_ptr (w_io_cq1_tail_ptr),
.io_cq2_tail_ptr (w_io_cq2_tail_ptr),
.io_cq3_tail_ptr (w_io_cq3_tail_ptr),
.io_cq4_tail_ptr (w_io_cq4_tail_ptr),
.io_cq5_tail_ptr (w_io_cq5_tail_ptr),
.io_cq6_tail_ptr (w_io_cq6_tail_ptr),
.io_cq7_tail_ptr (w_io_cq7_tail_ptr),
.io_cq8_tail_ptr (w_io_cq8_tail_ptr),
.tx_cq_mwr_req (w_tx_mwr0_req),
.tx_cq_mwr_tag (w_tx_mwr0_tag),
.tx_cq_mwr_len (w_tx_mwr0_len),
.tx_cq_mwr_addr (w_tx_mwr0_addr),
.tx_cq_mwr_req_ack (w_tx_mwr0_req_ack),
.tx_cq_mwr_rd_en (w_tx_mwr0_rd_en),
.tx_cq_mwr_rd_data (w_tx_mwr0_rd_data),
.tx_cq_mwr_data_last (w_tx_mwr0_data_last),
.hcmd_prp_rd_addr (w_hcmd_prp_rd_addr),
.hcmd_prp_rd_data (w_hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (w_hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (w_hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (w_hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (w_hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (w_hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (w_hcmd_nlb_rd_data),
.hcmd_cq_wr0_en (w_hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (w_hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (w_hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (w_hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.sq_rst_n (sq_rst_n),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n),
.hcmd_table_rd_addr (hcmd_table_rd_addr),
.hcmd_table_rd_data (hcmd_table_rd_data),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n)
);
dma_if
dma_if_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_payload_size (cfg_dcommand[7:5]),
.pcie_max_read_req_size (cfg_dcommand[14:12]),
.pcie_rcb (cfg_lcommand[3]),
.hcmd_prp_rd_addr (w_hcmd_prp_rd_addr),
.hcmd_prp_rd_data (w_hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (w_hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (w_hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (w_hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (w_hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (w_hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (w_hcmd_nlb_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.tx_prp_mrd_req (w_tx_mrd1_req),
.tx_prp_mrd_tag (w_tx_mrd1_tag),
.tx_prp_mrd_len (w_tx_mrd1_len),
.tx_prp_mrd_addr (w_tx_mrd1_addr),
.tx_prp_mrd_req_ack (w_tx_mrd1_req_ack),
.cpld_prp_fifo_tag (w_cpld1_fifo_tag),
.cpld_prp_fifo_wr_data (w_cpld1_fifo_wr_data),
.cpld_prp_fifo_wr_en (w_cpld1_fifo_wr_en),
.cpld_prp_fifo_tag_last (w_cpld1_fifo_tag_last),
.tx_dma_mrd_req (w_tx_mrd2_req),
.tx_dma_mrd_tag (w_tx_mrd2_tag),
.tx_dma_mrd_len (w_tx_mrd2_len),
.tx_dma_mrd_addr (w_tx_mrd2_addr),
.tx_dma_mrd_req_ack (w_tx_mrd2_req_ack),
.cpld_dma_fifo_tag (w_cpld2_fifo_tag),
.cpld_dma_fifo_wr_data (w_cpld2_fifo_wr_data),
.cpld_dma_fifo_wr_en (w_cpld2_fifo_wr_en),
.cpld_dma_fifo_tag_last (w_cpld2_fifo_tag_last),
.tx_dma_mwr_req (w_tx_mwr1_req),
.tx_dma_mwr_tag (w_tx_mwr1_tag),
.tx_dma_mwr_len (w_tx_mwr1_len),
.tx_dma_mwr_addr (w_tx_mwr1_addr),
.tx_dma_mwr_req_ack (w_tx_mwr1_req_ack),
.tx_dma_mwr_data_last (w_tx_mwr1_data_last),
.pcie_tx_dma_fifo_rd_en (w_tx_mwr1_rd_en),
.pcie_tx_dma_fifo_rd_data (w_tx_mwr1_rd_data),
.hcmd_cq_wr0_en (w_hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (w_hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (w_hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (w_hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_tans_if # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tans_if_inst0(
//PCIe user clock
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
//pcie rx signal
.mreq_fifo_wr_en (w_mreq_fifo_wr_en),
.mreq_fifo_wr_data (w_mreq_fifo_wr_data),
.cpld0_fifo_tag (w_cpld0_fifo_tag),
.cpld0_fifo_tag_last (w_cpld0_fifo_tag_last),
.cpld0_fifo_wr_en (w_cpld0_fifo_wr_en),
.cpld0_fifo_wr_data (w_cpld0_fifo_wr_data),
.cpld1_fifo_tag (w_cpld1_fifo_tag),
.cpld1_fifo_tag_last (w_cpld1_fifo_tag_last),
.cpld1_fifo_wr_en (w_cpld1_fifo_wr_en),
.cpld1_fifo_wr_data (w_cpld1_fifo_wr_data),
.cpld2_fifo_tag (w_cpld2_fifo_tag),
.cpld2_fifo_tag_last (w_cpld2_fifo_tag_last),
.cpld2_fifo_wr_en (w_cpld2_fifo_wr_en),
.cpld2_fifo_wr_data (w_cpld2_fifo_wr_data),
.tx_cpld_req (w_tx_cpld_req),
.tx_cpld_tag (w_tx_cpld_tag),
.tx_cpld_req_id (w_tx_cpld_req_id),
.tx_cpld_len (w_tx_cpld_len),
.tx_cpld_bc (w_tx_cpld_bc),
.tx_cpld_laddr (w_tx_cpld_laddr),
.tx_cpld_data (w_tx_cpld_data),
.tx_cpld_req_ack (w_tx_cpld_req_ack),
.tx_mrd0_req (w_tx_mrd0_req),
.tx_mrd0_tag (w_tx_mrd0_tag),
.tx_mrd0_len (w_tx_mrd0_len),
.tx_mrd0_addr (w_tx_mrd0_addr),
.tx_mrd0_req_ack (w_tx_mrd0_req_ack),
.tx_mrd1_req (w_tx_mrd1_req),
.tx_mrd1_tag (w_tx_mrd1_tag),
.tx_mrd1_len (w_tx_mrd1_len),
.tx_mrd1_addr (w_tx_mrd1_addr),
.tx_mrd1_req_ack (w_tx_mrd1_req_ack),
.tx_mrd2_req (w_tx_mrd2_req),
.tx_mrd2_tag (w_tx_mrd2_tag),
.tx_mrd2_len (w_tx_mrd2_len),
.tx_mrd2_addr (w_tx_mrd2_addr),
.tx_mrd2_req_ack (w_tx_mrd2_req_ack),
.tx_mwr0_req (w_tx_mwr0_req),
.tx_mwr0_tag (w_tx_mwr0_tag),
.tx_mwr0_len (w_tx_mwr0_len),
.tx_mwr0_addr (w_tx_mwr0_addr),
.tx_mwr0_req_ack (w_tx_mwr0_req_ack),
.tx_mwr0_rd_en (w_tx_mwr0_rd_en),
.tx_mwr0_rd_data (w_tx_mwr0_rd_data),
.tx_mwr0_data_last (w_tx_mwr0_data_last),
.tx_mwr1_req (w_tx_mwr1_req),
.tx_mwr1_tag (w_tx_mwr1_tag),
.tx_mwr1_len (w_tx_mwr1_len),
.tx_mwr1_addr (w_tx_mwr1_addr),
.tx_mwr1_req_ack (w_tx_mwr1_req_ack),
.tx_mwr1_rd_en (w_tx_mwr1_rd_en),
.tx_mwr1_rd_data (w_tx_mwr1_rd_data),
.tx_mwr1_data_last (w_tx_mwr1_data_last),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.tx_buf_av (tx_buf_av),
.tx_err_drop (tx_err_drop),
.tx_cfg_req (tx_cfg_req),
.s_axis_tx_tready (s_axis_tx_tready),
.s_axis_tx_tdata (s_axis_tx_tdata),
.s_axis_tx_tkeep (s_axis_tx_tkeep),
.s_axis_tx_tuser (s_axis_tx_tuser),
.s_axis_tx_tlast (s_axis_tx_tlast),
.s_axis_tx_tvalid (s_axis_tx_tvalid),
.tx_cfg_gnt (tx_cfg_gnt),
.m_axis_rx_tdata (m_axis_rx_tdata),
.m_axis_rx_tkeep (m_axis_rx_tkeep),
.m_axis_rx_tlast (m_axis_rx_tlast),
.m_axis_rx_tvalid (m_axis_rx_tvalid),
.m_axis_rx_tready (m_axis_rx_tready),
.m_axis_rx_tuser (m_axis_rx_tuser),
.fc_cpld (fc_cpld),
.fc_cplh (fc_cplh),
.fc_npd (fc_npd),
.fc_nph (fc_nph),
.fc_pd (fc_pd),
.fc_ph (fc_ph),
.fc_sel (fc_sel),
.cfg_bus_number (cfg_bus_number),
.cfg_device_number (cfg_device_number),
.cfg_function_number (cfg_function_number)
);
nvme_irq
nvme_irq_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.nvme_intms_ivms (w_nvme_intms_ivms),
.nvme_intmc_ivmc (w_nvme_intmc_ivmc),
.cq_irq_status (w_cq_irq_status),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.admin_cq_tail_ptr (w_admin_cq_tail_ptr),
.io_cq1_tail_ptr (w_io_cq1_tail_ptr),
.io_cq2_tail_ptr (w_io_cq2_tail_ptr),
.io_cq3_tail_ptr (w_io_cq3_tail_ptr),
.io_cq4_tail_ptr (w_io_cq4_tail_ptr),
.io_cq5_tail_ptr (w_io_cq5_tail_ptr),
.io_cq6_tail_ptr (w_io_cq6_tail_ptr),
.io_cq7_tail_ptr (w_io_cq7_tail_ptr),
.io_cq8_tail_ptr (w_io_cq8_tail_ptr),
.admin_cq_head_ptr (w_admin_cq_head_ptr),
.io_cq1_head_ptr (w_io_cq1_head_ptr),
.io_cq2_head_ptr (w_io_cq2_head_ptr),
.io_cq3_head_ptr (w_io_cq3_head_ptr),
.io_cq4_head_ptr (w_io_cq4_head_ptr),
.io_cq5_head_ptr (w_io_cq5_head_ptr),
.io_cq6_head_ptr (w_io_cq6_head_ptr),
.io_cq7_head_ptr (w_io_cq7_head_ptr),
.io_cq8_head_ptr (w_io_cq8_head_ptr),
.cq_head_update (w_cq_head_update)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_pcie # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_ref_clk_p,
input pcie_ref_clk_n,
//PCIe user clock
input pcie_user_clk,
input pcie_user_rst_n,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
output nvme_cc_en,
output [1:0] nvme_cc_shn,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input hcmd_sq_rd_en,
output [18:0] hcmd_sq_rd_data,
output hcmd_sq_empty_n,
input [10:0] hcmd_table_rd_addr,
output [31:0] hcmd_table_rd_data,
input hcmd_cq_wr1_en,
input [34:0] hcmd_cq_wr1_data0,
input [34:0] hcmd_cq_wr1_data1,
output hcmd_cq_wr1_rdy_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n,
input pcie_tx_fifo_alloc_en,
input [9:4] pcie_tx_fifo_alloc_len,
input pcie_tx_fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
output pcie_tx_fifo_full_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n,
output pcie_mreq_err,
output pcie_cpld_err,
output pcie_cpld_len_err,
//PCIe Integrated Block Interface
input [5:0] tx_buf_av,
input tx_err_drop,
input tx_cfg_req,
input s_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_tx_tkeep,
output [3:0] s_axis_tx_tuser,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_cfg_gnt,
input [C_PCIE_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
output rx_np_ok,
output rx_np_req,
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number,
input cfg_to_turnoff,
output cfg_turnoff_ok,
input [15:0] cfg_command,
input [15:0] cfg_dcommand,
input [15:0] cfg_lcommand,
output sys_clk
);
wire w_nvme_intms_ivms;
wire w_nvme_intmc_ivmc;
wire w_cq_irq_status;
wire [7:0] w_hcmd_prp_rd_addr;
wire [44:0] w_hcmd_prp_rd_data;
wire w_hcmd_nlb_wr1_en;
wire [6:0] w_hcmd_nlb_wr1_addr;
wire [18:0] w_hcmd_nlb_wr1_data;
wire w_hcmd_nlb_wr1_rdy_n;
wire [6:0] w_hcmd_nlb_rd_addr;
wire [18:0] w_hcmd_nlb_rd_data;
wire w_hcmd_cq_wr0_en;
wire [34:0] w_hcmd_cq_wr0_data0;
wire [34:0] w_hcmd_cq_wr0_data1;
wire w_hcmd_cq_wr0_rdy_n;
wire w_mreq_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_mreq_fifo_wr_data;
wire [7:0] w_cpld0_fifo_tag;
wire w_cpld0_fifo_tag_last;
wire w_cpld0_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_cpld0_fifo_wr_data;
wire [7:0] w_cpld1_fifo_tag;
wire w_cpld1_fifo_tag_last;
wire w_cpld1_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_cpld1_fifo_wr_data;
wire [7:0] w_cpld2_fifo_tag;
wire w_cpld2_fifo_tag_last;
wire w_cpld2_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_cpld2_fifo_wr_data;
wire w_tx_cpld_req;
wire [7:0] w_tx_cpld_tag;
wire [15:0] w_tx_cpld_req_id;
wire [11:2] w_tx_cpld_len;
wire [11:0] w_tx_cpld_bc;
wire [6:0] w_tx_cpld_laddr;
wire [63:0] w_tx_cpld_data;
wire w_tx_cpld_req_ack;
wire w_tx_mrd0_req;
wire [7:0] w_tx_mrd0_tag;
wire [11:2] w_tx_mrd0_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mrd0_addr;
wire w_tx_mrd0_req_ack;
wire w_tx_mrd1_req;
wire [7:0] w_tx_mrd1_tag;
wire [11:2] w_tx_mrd1_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mrd1_addr;
wire w_tx_mrd1_req_ack;
wire w_tx_mrd2_req;
wire [7:0] w_tx_mrd2_tag;
wire [11:2] w_tx_mrd2_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mrd2_addr;
wire w_tx_mrd2_req_ack;
wire w_tx_mwr0_req;
wire [7:0] w_tx_mwr0_tag;
wire [11:2] w_tx_mwr0_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mwr0_addr;
wire w_tx_mwr0_req_ack;
wire w_tx_mwr0_rd_en;
wire [C_PCIE_DATA_WIDTH-1 : 0] w_tx_mwr0_rd_data;
wire w_tx_mwr0_data_last;
wire w_tx_mwr1_req;
wire [7:0] w_tx_mwr1_tag;
wire [11:2] w_tx_mwr1_len;
wire [C_PCIE_ADDR_WIDTH-1:2] w_tx_mwr1_addr;
wire w_tx_mwr1_req_ack;
wire w_tx_mwr1_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_tx_mwr1_rd_data;
wire w_tx_mwr1_data_last;
wire [C_PCIE_ADDR_WIDTH-1:2] w_admin_sq_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_admin_cq_bs_addr;
wire [7:0] w_admin_sq_size;
wire [7:0] w_admin_cq_size;
wire [7:0] w_admin_sq_tail_ptr;
wire [7:0] w_io_sq1_tail_ptr;
wire [7:0] w_io_sq2_tail_ptr;
wire [7:0] w_io_sq3_tail_ptr;
wire [7:0] w_io_sq4_tail_ptr;
wire [7:0] w_io_sq5_tail_ptr;
wire [7:0] w_io_sq6_tail_ptr;
wire [7:0] w_io_sq7_tail_ptr;
wire [7:0] w_io_sq8_tail_ptr;
wire [7:0] w_admin_cq_tail_ptr;
wire [7:0] w_io_cq1_tail_ptr;
wire [7:0] w_io_cq2_tail_ptr;
wire [7:0] w_io_cq3_tail_ptr;
wire [7:0] w_io_cq4_tail_ptr;
wire [7:0] w_io_cq5_tail_ptr;
wire [7:0] w_io_cq6_tail_ptr;
wire [7:0] w_io_cq7_tail_ptr;
wire [7:0] w_io_cq8_tail_ptr;
wire [7:0] w_admin_cq_head_ptr;
wire [7:0] w_io_cq1_head_ptr;
wire [7:0] w_io_cq2_head_ptr;
wire [7:0] w_io_cq3_head_ptr;
wire [7:0] w_io_cq4_head_ptr;
wire [7:0] w_io_cq5_head_ptr;
wire [7:0] w_io_cq6_head_ptr;
wire [7:0] w_io_cq7_head_ptr;
wire [7:0] w_io_cq8_head_ptr;
wire [8:0] w_cq_head_update;
reg r_cfg_turnoff_ok;
IBUFDS_GTE2 pcie_ref_clk_ibuf (.O(sys_clk), .ODIV2(), .I(pcie_ref_clk_p), .CEB(1'b0), .IB(pcie_ref_clk_n));
assign cfg_turnoff_ok = r_cfg_turnoff_ok;
always @(posedge pcie_user_clk) begin
r_cfg_turnoff_ok <= cfg_to_turnoff;
end
pcie_cntl_slave # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_cntl_slave_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.rx_np_ok (rx_np_ok),
.rx_np_req (rx_np_req),
.mreq_fifo_wr_en (w_mreq_fifo_wr_en),
.mreq_fifo_wr_data (w_mreq_fifo_wr_data),
.tx_cpld_req (w_tx_cpld_req),
.tx_cpld_tag (w_tx_cpld_tag),
.tx_cpld_req_id (w_tx_cpld_req_id),
.tx_cpld_len (w_tx_cpld_len),
.tx_cpld_bc (w_tx_cpld_bc),
.tx_cpld_laddr (w_tx_cpld_laddr),
.tx_cpld_data (w_tx_cpld_data),
.tx_cpld_req_ack (w_tx_cpld_req_ack),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.nvme_intms_ivms (w_nvme_intms_ivms),
.nvme_intmc_ivmc (w_nvme_intmc_ivmc),
.cq_irq_status (w_cq_irq_status),
.sq_rst_n (sq_rst_n),
.cq_rst_n (cq_rst_n),
.admin_sq_bs_addr (w_admin_sq_bs_addr),
.admin_cq_bs_addr (w_admin_cq_bs_addr),
.admin_sq_size (w_admin_sq_size),
.admin_cq_size (w_admin_cq_size),
.admin_sq_tail_ptr (w_admin_sq_tail_ptr),
.io_sq1_tail_ptr (w_io_sq1_tail_ptr),
.io_sq2_tail_ptr (w_io_sq2_tail_ptr),
.io_sq3_tail_ptr (w_io_sq3_tail_ptr),
.io_sq4_tail_ptr (w_io_sq4_tail_ptr),
.io_sq5_tail_ptr (w_io_sq5_tail_ptr),
.io_sq6_tail_ptr (w_io_sq6_tail_ptr),
.io_sq7_tail_ptr (w_io_sq7_tail_ptr),
.io_sq8_tail_ptr (w_io_sq8_tail_ptr),
.admin_cq_head_ptr (w_admin_cq_head_ptr),
.io_cq1_head_ptr (w_io_cq1_head_ptr),
.io_cq2_head_ptr (w_io_cq2_head_ptr),
.io_cq3_head_ptr (w_io_cq3_head_ptr),
.io_cq4_head_ptr (w_io_cq4_head_ptr),
.io_cq5_head_ptr (w_io_cq5_head_ptr),
.io_cq6_head_ptr (w_io_cq6_head_ptr),
.io_cq7_head_ptr (w_io_cq7_head_ptr),
.io_cq8_head_ptr (w_io_cq8_head_ptr),
.cq_head_update (w_cq_head_update)
);
pcie_hcmd # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.admin_sq_bs_addr (w_admin_sq_bs_addr),
.admin_cq_bs_addr (w_admin_cq_bs_addr),
.admin_sq_size (w_admin_sq_size),
.admin_cq_size (w_admin_cq_size),
.admin_sq_tail_ptr (w_admin_sq_tail_ptr),
.io_sq1_tail_ptr (w_io_sq1_tail_ptr),
.io_sq2_tail_ptr (w_io_sq2_tail_ptr),
.io_sq3_tail_ptr (w_io_sq3_tail_ptr),
.io_sq4_tail_ptr (w_io_sq4_tail_ptr),
.io_sq5_tail_ptr (w_io_sq5_tail_ptr),
.io_sq6_tail_ptr (w_io_sq6_tail_ptr),
.io_sq7_tail_ptr (w_io_sq7_tail_ptr),
.io_sq8_tail_ptr (w_io_sq8_tail_ptr),
.cpld_sq_fifo_tag (w_cpld0_fifo_tag),
.cpld_sq_fifo_wr_data (w_cpld0_fifo_wr_data),
.cpld_sq_fifo_wr_en (w_cpld0_fifo_wr_en),
.cpld_sq_fifo_tag_last (w_cpld0_fifo_tag_last),
.tx_mrd_req (w_tx_mrd0_req),
.tx_mrd_tag (w_tx_mrd0_tag),
.tx_mrd_len (w_tx_mrd0_len),
.tx_mrd_addr (w_tx_mrd0_addr),
.tx_mrd_req_ack (w_tx_mrd0_req_ack),
.admin_cq_tail_ptr (w_admin_cq_tail_ptr),
.io_cq1_tail_ptr (w_io_cq1_tail_ptr),
.io_cq2_tail_ptr (w_io_cq2_tail_ptr),
.io_cq3_tail_ptr (w_io_cq3_tail_ptr),
.io_cq4_tail_ptr (w_io_cq4_tail_ptr),
.io_cq5_tail_ptr (w_io_cq5_tail_ptr),
.io_cq6_tail_ptr (w_io_cq6_tail_ptr),
.io_cq7_tail_ptr (w_io_cq7_tail_ptr),
.io_cq8_tail_ptr (w_io_cq8_tail_ptr),
.tx_cq_mwr_req (w_tx_mwr0_req),
.tx_cq_mwr_tag (w_tx_mwr0_tag),
.tx_cq_mwr_len (w_tx_mwr0_len),
.tx_cq_mwr_addr (w_tx_mwr0_addr),
.tx_cq_mwr_req_ack (w_tx_mwr0_req_ack),
.tx_cq_mwr_rd_en (w_tx_mwr0_rd_en),
.tx_cq_mwr_rd_data (w_tx_mwr0_rd_data),
.tx_cq_mwr_data_last (w_tx_mwr0_data_last),
.hcmd_prp_rd_addr (w_hcmd_prp_rd_addr),
.hcmd_prp_rd_data (w_hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (w_hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (w_hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (w_hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (w_hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (w_hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (w_hcmd_nlb_rd_data),
.hcmd_cq_wr0_en (w_hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (w_hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (w_hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (w_hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.sq_rst_n (sq_rst_n),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n),
.hcmd_table_rd_addr (hcmd_table_rd_addr),
.hcmd_table_rd_data (hcmd_table_rd_data),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n)
);
dma_if
dma_if_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_payload_size (cfg_dcommand[7:5]),
.pcie_max_read_req_size (cfg_dcommand[14:12]),
.pcie_rcb (cfg_lcommand[3]),
.hcmd_prp_rd_addr (w_hcmd_prp_rd_addr),
.hcmd_prp_rd_data (w_hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (w_hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (w_hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (w_hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (w_hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (w_hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (w_hcmd_nlb_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.tx_prp_mrd_req (w_tx_mrd1_req),
.tx_prp_mrd_tag (w_tx_mrd1_tag),
.tx_prp_mrd_len (w_tx_mrd1_len),
.tx_prp_mrd_addr (w_tx_mrd1_addr),
.tx_prp_mrd_req_ack (w_tx_mrd1_req_ack),
.cpld_prp_fifo_tag (w_cpld1_fifo_tag),
.cpld_prp_fifo_wr_data (w_cpld1_fifo_wr_data),
.cpld_prp_fifo_wr_en (w_cpld1_fifo_wr_en),
.cpld_prp_fifo_tag_last (w_cpld1_fifo_tag_last),
.tx_dma_mrd_req (w_tx_mrd2_req),
.tx_dma_mrd_tag (w_tx_mrd2_tag),
.tx_dma_mrd_len (w_tx_mrd2_len),
.tx_dma_mrd_addr (w_tx_mrd2_addr),
.tx_dma_mrd_req_ack (w_tx_mrd2_req_ack),
.cpld_dma_fifo_tag (w_cpld2_fifo_tag),
.cpld_dma_fifo_wr_data (w_cpld2_fifo_wr_data),
.cpld_dma_fifo_wr_en (w_cpld2_fifo_wr_en),
.cpld_dma_fifo_tag_last (w_cpld2_fifo_tag_last),
.tx_dma_mwr_req (w_tx_mwr1_req),
.tx_dma_mwr_tag (w_tx_mwr1_tag),
.tx_dma_mwr_len (w_tx_mwr1_len),
.tx_dma_mwr_addr (w_tx_mwr1_addr),
.tx_dma_mwr_req_ack (w_tx_mwr1_req_ack),
.tx_dma_mwr_data_last (w_tx_mwr1_data_last),
.pcie_tx_dma_fifo_rd_en (w_tx_mwr1_rd_en),
.pcie_tx_dma_fifo_rd_data (w_tx_mwr1_rd_data),
.hcmd_cq_wr0_en (w_hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (w_hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (w_hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (w_hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_tans_if # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tans_if_inst0(
//PCIe user clock
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
//pcie rx signal
.mreq_fifo_wr_en (w_mreq_fifo_wr_en),
.mreq_fifo_wr_data (w_mreq_fifo_wr_data),
.cpld0_fifo_tag (w_cpld0_fifo_tag),
.cpld0_fifo_tag_last (w_cpld0_fifo_tag_last),
.cpld0_fifo_wr_en (w_cpld0_fifo_wr_en),
.cpld0_fifo_wr_data (w_cpld0_fifo_wr_data),
.cpld1_fifo_tag (w_cpld1_fifo_tag),
.cpld1_fifo_tag_last (w_cpld1_fifo_tag_last),
.cpld1_fifo_wr_en (w_cpld1_fifo_wr_en),
.cpld1_fifo_wr_data (w_cpld1_fifo_wr_data),
.cpld2_fifo_tag (w_cpld2_fifo_tag),
.cpld2_fifo_tag_last (w_cpld2_fifo_tag_last),
.cpld2_fifo_wr_en (w_cpld2_fifo_wr_en),
.cpld2_fifo_wr_data (w_cpld2_fifo_wr_data),
.tx_cpld_req (w_tx_cpld_req),
.tx_cpld_tag (w_tx_cpld_tag),
.tx_cpld_req_id (w_tx_cpld_req_id),
.tx_cpld_len (w_tx_cpld_len),
.tx_cpld_bc (w_tx_cpld_bc),
.tx_cpld_laddr (w_tx_cpld_laddr),
.tx_cpld_data (w_tx_cpld_data),
.tx_cpld_req_ack (w_tx_cpld_req_ack),
.tx_mrd0_req (w_tx_mrd0_req),
.tx_mrd0_tag (w_tx_mrd0_tag),
.tx_mrd0_len (w_tx_mrd0_len),
.tx_mrd0_addr (w_tx_mrd0_addr),
.tx_mrd0_req_ack (w_tx_mrd0_req_ack),
.tx_mrd1_req (w_tx_mrd1_req),
.tx_mrd1_tag (w_tx_mrd1_tag),
.tx_mrd1_len (w_tx_mrd1_len),
.tx_mrd1_addr (w_tx_mrd1_addr),
.tx_mrd1_req_ack (w_tx_mrd1_req_ack),
.tx_mrd2_req (w_tx_mrd2_req),
.tx_mrd2_tag (w_tx_mrd2_tag),
.tx_mrd2_len (w_tx_mrd2_len),
.tx_mrd2_addr (w_tx_mrd2_addr),
.tx_mrd2_req_ack (w_tx_mrd2_req_ack),
.tx_mwr0_req (w_tx_mwr0_req),
.tx_mwr0_tag (w_tx_mwr0_tag),
.tx_mwr0_len (w_tx_mwr0_len),
.tx_mwr0_addr (w_tx_mwr0_addr),
.tx_mwr0_req_ack (w_tx_mwr0_req_ack),
.tx_mwr0_rd_en (w_tx_mwr0_rd_en),
.tx_mwr0_rd_data (w_tx_mwr0_rd_data),
.tx_mwr0_data_last (w_tx_mwr0_data_last),
.tx_mwr1_req (w_tx_mwr1_req),
.tx_mwr1_tag (w_tx_mwr1_tag),
.tx_mwr1_len (w_tx_mwr1_len),
.tx_mwr1_addr (w_tx_mwr1_addr),
.tx_mwr1_req_ack (w_tx_mwr1_req_ack),
.tx_mwr1_rd_en (w_tx_mwr1_rd_en),
.tx_mwr1_rd_data (w_tx_mwr1_rd_data),
.tx_mwr1_data_last (w_tx_mwr1_data_last),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.tx_buf_av (tx_buf_av),
.tx_err_drop (tx_err_drop),
.tx_cfg_req (tx_cfg_req),
.s_axis_tx_tready (s_axis_tx_tready),
.s_axis_tx_tdata (s_axis_tx_tdata),
.s_axis_tx_tkeep (s_axis_tx_tkeep),
.s_axis_tx_tuser (s_axis_tx_tuser),
.s_axis_tx_tlast (s_axis_tx_tlast),
.s_axis_tx_tvalid (s_axis_tx_tvalid),
.tx_cfg_gnt (tx_cfg_gnt),
.m_axis_rx_tdata (m_axis_rx_tdata),
.m_axis_rx_tkeep (m_axis_rx_tkeep),
.m_axis_rx_tlast (m_axis_rx_tlast),
.m_axis_rx_tvalid (m_axis_rx_tvalid),
.m_axis_rx_tready (m_axis_rx_tready),
.m_axis_rx_tuser (m_axis_rx_tuser),
.fc_cpld (fc_cpld),
.fc_cplh (fc_cplh),
.fc_npd (fc_npd),
.fc_nph (fc_nph),
.fc_pd (fc_pd),
.fc_ph (fc_ph),
.fc_sel (fc_sel),
.cfg_bus_number (cfg_bus_number),
.cfg_device_number (cfg_device_number),
.cfg_function_number (cfg_function_number)
);
nvme_irq
nvme_irq_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.nvme_intms_ivms (w_nvme_intms_ivms),
.nvme_intmc_ivmc (w_nvme_intmc_ivmc),
.cq_irq_status (w_cq_irq_status),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.admin_cq_tail_ptr (w_admin_cq_tail_ptr),
.io_cq1_tail_ptr (w_io_cq1_tail_ptr),
.io_cq2_tail_ptr (w_io_cq2_tail_ptr),
.io_cq3_tail_ptr (w_io_cq3_tail_ptr),
.io_cq4_tail_ptr (w_io_cq4_tail_ptr),
.io_cq5_tail_ptr (w_io_cq5_tail_ptr),
.io_cq6_tail_ptr (w_io_cq6_tail_ptr),
.io_cq7_tail_ptr (w_io_cq7_tail_ptr),
.io_cq8_tail_ptr (w_io_cq8_tail_ptr),
.admin_cq_head_ptr (w_admin_cq_head_ptr),
.io_cq1_head_ptr (w_io_cq1_head_ptr),
.io_cq2_head_ptr (w_io_cq2_head_ptr),
.io_cq3_head_ptr (w_io_cq3_head_ptr),
.io_cq4_head_ptr (w_io_cq4_head_ptr),
.io_cq5_head_ptr (w_io_cq5_head_ptr),
.io_cq6_head_ptr (w_io_cq6_head_ptr),
.io_cq7_head_ptr (w_io_cq7_head_ptr),
.io_cq8_head_ptr (w_io_cq8_head_ptr),
.cq_head_update (w_cq_head_update)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
`ifdef ALLOW_UNOPT
/*verilator lint_off UNOPTFLAT*/
`endif
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] b; // From file of file.v
wire [31:0] c; // From file of file.v
wire [31:0] d; // From file of file.v
// End of automatics
file file (/*AUTOINST*/
// Outputs
.b (b[31:0]),
.c (c[31:0]),
.d (d[31:0]),
// Inputs
.crc (crc[31:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n",$time,cyc,crc,sum, b, d);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {b, d}
^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h649ee1713d624dd9) $stop;
$finish;
end
end
endmodule
module file (/*AUTOARG*/
// Outputs
b, c, d,
// Inputs
crc
);
input [31:0] crc;
`ifdef ISOLATE
output reg [31:0] b /* verilator isolate_assignments*/;
`else
output reg [31:0] b;
`endif
output reg [31:0] c;
output reg [31:0] d;
always @* begin
// Note that while c and b depend on crc, b doesn't depend on c.
casez (crc[3:0])
4'b??01: begin
b = {crc[15:0],get_31_16(crc)};
d = c;
end
4'b??00: begin
b = {crc[15:0],~crc[31:16]};
d = {crc[15:0],~c[31:16]};
end
default: begin
set_b_d(crc, c);
end
endcase
end
function [31:16] get_31_16 /* verilator isolate_assignments*/;
input [31:0] t_crc /* verilator isolate_assignments*/;
get_31_16 = t_crc[31:16];
endfunction
task set_b_d;
`ifdef ISOLATE
input [31:0] t_crc /* verilator isolate_assignments*/;
input [31:0] t_c /* verilator isolate_assignments*/;
`else
input [31:0] t_crc;
input [31:0] t_c;
`endif
begin
b = {t_crc[31:16],~t_crc[23:8]};
d = {t_crc[31:16], ~t_c[23:8]};
end
endtask
always @* begin
// Any complicated equation we can't optimize
casez (crc[3:0])
4'b00??: begin
c = {b[29:0],2'b11};
end
4'b01??: begin
c = {b[30:1],2'b01};
end
4'b10??: begin
c = {b[31:2],2'b10};
end
4'b11??: begin
c = {b[31:2],2'b00};
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
`ifdef ALLOW_UNOPT
/*verilator lint_off UNOPTFLAT*/
`endif
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] b; // From file of file.v
wire [31:0] c; // From file of file.v
wire [31:0] d; // From file of file.v
// End of automatics
file file (/*AUTOINST*/
// Outputs
.b (b[31:0]),
.c (c[31:0]),
.d (d[31:0]),
// Inputs
.crc (crc[31:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n",$time,cyc,crc,sum, b, d);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {b, d}
^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h649ee1713d624dd9) $stop;
$finish;
end
end
endmodule
module file (/*AUTOARG*/
// Outputs
b, c, d,
// Inputs
crc
);
input [31:0] crc;
`ifdef ISOLATE
output reg [31:0] b /* verilator isolate_assignments*/;
`else
output reg [31:0] b;
`endif
output reg [31:0] c;
output reg [31:0] d;
always @* begin
// Note that while c and b depend on crc, b doesn't depend on c.
casez (crc[3:0])
4'b??01: begin
b = {crc[15:0],get_31_16(crc)};
d = c;
end
4'b??00: begin
b = {crc[15:0],~crc[31:16]};
d = {crc[15:0],~c[31:16]};
end
default: begin
set_b_d(crc, c);
end
endcase
end
function [31:16] get_31_16 /* verilator isolate_assignments*/;
input [31:0] t_crc /* verilator isolate_assignments*/;
get_31_16 = t_crc[31:16];
endfunction
task set_b_d;
`ifdef ISOLATE
input [31:0] t_crc /* verilator isolate_assignments*/;
input [31:0] t_c /* verilator isolate_assignments*/;
`else
input [31:0] t_crc;
input [31:0] t_c;
`endif
begin
b = {t_crc[31:16],~t_crc[23:8]};
d = {t_crc[31:16], ~t_c[23:8]};
end
endtask
always @* begin
// Any complicated equation we can't optimize
casez (crc[3:0])
4'b00??: begin
c = {b[29:0],2'b11};
end
4'b01??: begin
c = {b[30:1],2'b01};
end
4'b10??: begin
c = {b[31:2],2'b10};
end
4'b11??: begin
c = {b[31:2],2'b00};
end
endcase
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_table # (
parameter P_DATA_WIDTH = 128,
parameter P_ADDR_WIDTH = 9
)
(
input wr_clk,
input wr_en,
input [P_ADDR_WIDTH-1:0] wr_addr,
input [P_DATA_WIDTH-1:0] wr_data,
input rd_clk,
input [P_ADDR_WIDTH+1:0] rd_addr,
output [31:0] rd_data
);
wire [P_DATA_WIDTH-1:0] w_rd_data;
reg [31:0] r_rd_data;
assign rd_data = r_rd_data;
always @ (*)
begin
case(rd_addr[1:0]) // synthesis parallel_case full_case
2'b00: r_rd_data <= w_rd_data[31:0];
2'b01: r_rd_data <= w_rd_data[63:32];
2'b10: r_rd_data <= w_rd_data[95:64];
2'b11: r_rd_data <= w_rd_data[127:96];
endcase
end
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = rd_addr[P_ADDR_WIDTH+1:2];
assign wraddr = wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, rd_addr[P_ADDR_WIDTH+1:2]};
assign wraddr = {zero_padding, wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (w_rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (w_rd_data[P_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_table # (
parameter P_DATA_WIDTH = 128,
parameter P_ADDR_WIDTH = 9
)
(
input wr_clk,
input wr_en,
input [P_ADDR_WIDTH-1:0] wr_addr,
input [P_DATA_WIDTH-1:0] wr_data,
input rd_clk,
input [P_ADDR_WIDTH+1:0] rd_addr,
output [31:0] rd_data
);
wire [P_DATA_WIDTH-1:0] w_rd_data;
reg [31:0] r_rd_data;
assign rd_data = r_rd_data;
always @ (*)
begin
case(rd_addr[1:0]) // synthesis parallel_case full_case
2'b00: r_rd_data <= w_rd_data[31:0];
2'b01: r_rd_data <= w_rd_data[63:32];
2'b10: r_rd_data <= w_rd_data[95:64];
2'b11: r_rd_data <= w_rd_data[127:96];
endcase
end
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = rd_addr[P_ADDR_WIDTH+1:2];
assign wraddr = wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, rd_addr[P_ADDR_WIDTH+1:2]};
assign wraddr = {zero_padding, wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (w_rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (w_rd_data[P_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_table # (
parameter P_DATA_WIDTH = 128,
parameter P_ADDR_WIDTH = 9
)
(
input wr_clk,
input wr_en,
input [P_ADDR_WIDTH-1:0] wr_addr,
input [P_DATA_WIDTH-1:0] wr_data,
input rd_clk,
input [P_ADDR_WIDTH+1:0] rd_addr,
output [31:0] rd_data
);
wire [P_DATA_WIDTH-1:0] w_rd_data;
reg [31:0] r_rd_data;
assign rd_data = r_rd_data;
always @ (*)
begin
case(rd_addr[1:0]) // synthesis parallel_case full_case
2'b00: r_rd_data <= w_rd_data[31:0];
2'b01: r_rd_data <= w_rd_data[63:32];
2'b10: r_rd_data <= w_rd_data[95:64];
2'b11: r_rd_data <= w_rd_data[127:96];
endcase
end
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = rd_addr[P_ADDR_WIDTH+1:2];
assign wraddr = wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, rd_addr[P_ADDR_WIDTH+1:2]};
assign wraddr = {zero_padding, wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (w_rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (w_rd_data[P_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2012 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t (/*AUTOARG*/);
`define ASSERT(x) initial if (!(x)) $stop
// See IEEE 6.20.2 on value parameters
localparam unsigned [63:0] UNSIGNED =64'h99934567_89abcdef;
localparam signed [63:0] SIGNED =64'sh99934567_89abcdef;
localparam real REAL=1.234;
`ASSERT(UNSIGNED > 0);
`ASSERT(SIGNED < 0);
// bullet 1
localparam A1_WIDE = UNSIGNED;
`ASSERT($bits(A1_WIDE)==64);
localparam A2_REAL = REAL;
`ASSERT(A2_REAL == 1.234);
localparam A3_SIGNED = SIGNED;
`ASSERT($bits(A3_SIGNED)==64 && A3_SIGNED < 0);
localparam A4_EXPR = (2'b01 + 2'b10);
`ASSERT($bits(A4_EXPR)==2 && A4_EXPR==2'b11);
// bullet 2
localparam [63:0] B_UNSIGNED = SIGNED;
`ASSERT($bits(B_UNSIGNED)==64 && B_UNSIGNED > 0);
// bullet 3
localparam signed C_SIGNED = UNSIGNED;
`ASSERT($bits(C_SIGNED)==64 && C_SIGNED < 0);
localparam unsigned C_UNSIGNED = SIGNED;
`ASSERT($bits(C_UNSIGNED)==64 && C_UNSIGNED > 0);
// bullet 4
// verilator lint_off WIDTH
localparam signed [59:0] D_SIGNED = UNSIGNED;
`ASSERT($bits(D_SIGNED)==60 && D_SIGNED < 0);
// verilator lint_on WIDTH
// verilator lint_off WIDTH
localparam unsigned [59:0] D_UNSIGNED = SIGNED;
`ASSERT($bits(D_UNSIGNED)==60 && D_UNSIGNED > 0);
// verilator lint_on WIDTH
// bullet 6
localparam UNSIZED = 23;
`ASSERT($bits(UNSIZED)>=32);
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
function int int123(); int123 = 32'h123; endfunction
function bit f_bit ; input bit i; f_bit = ~i; endfunction
function int f_int ; input int i; f_int = ~i; endfunction
function byte f_byte ; input byte i; f_byte = ~i; endfunction
function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction
function longint f_longint ; input longint i; f_longint = ~i; endfunction
function chandle f_chandle ; input chandle i; f_chandle = i; endfunction
// Note there's no "input" here vvvv, it's the default
function bit g_bit (bit i); g_bit = ~i; endfunction
function int g_int (int i); g_int = ~i; endfunction
function byte g_byte (byte i); g_byte = ~i; endfunction
function shortint g_shortint(shortint i); g_shortint = ~i; endfunction
function longint g_longint (longint i); g_longint = ~i; endfunction
function chandle g_chandle (chandle i); g_chandle = i; endfunction
chandle c;
initial begin
if (int123() !== 32'h123) $stop;
if (f_bit(1'h1) !== 1'h0) $stop;
if (f_bit(1'h0) !== 1'h1) $stop;
if (f_int(32'h1) !== 32'hfffffffe) $stop;
if (f_byte(8'h1) !== 8'hfe) $stop;
if (f_shortint(16'h1) !== 16'hfffe) $stop;
if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (f_chandle(c) !== c) $stop;
if (g_bit(1'h1) !== 1'h0) $stop;
if (g_bit(1'h0) !== 1'h1) $stop;
if (g_int(32'h1) !== 32'hfffffffe) $stop;
if (g_byte(8'h1) !== 8'hfe) $stop;
if (g_shortint(16'h1) !== 16'hfffe) $stop;
if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (g_chandle(c) !== c) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
function int int123(); int123 = 32'h123; endfunction
function bit f_bit ; input bit i; f_bit = ~i; endfunction
function int f_int ; input int i; f_int = ~i; endfunction
function byte f_byte ; input byte i; f_byte = ~i; endfunction
function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction
function longint f_longint ; input longint i; f_longint = ~i; endfunction
function chandle f_chandle ; input chandle i; f_chandle = i; endfunction
// Note there's no "input" here vvvv, it's the default
function bit g_bit (bit i); g_bit = ~i; endfunction
function int g_int (int i); g_int = ~i; endfunction
function byte g_byte (byte i); g_byte = ~i; endfunction
function shortint g_shortint(shortint i); g_shortint = ~i; endfunction
function longint g_longint (longint i); g_longint = ~i; endfunction
function chandle g_chandle (chandle i); g_chandle = i; endfunction
chandle c;
initial begin
if (int123() !== 32'h123) $stop;
if (f_bit(1'h1) !== 1'h0) $stop;
if (f_bit(1'h0) !== 1'h1) $stop;
if (f_int(32'h1) !== 32'hfffffffe) $stop;
if (f_byte(8'h1) !== 8'hfe) $stop;
if (f_shortint(16'h1) !== 16'hfffe) $stop;
if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (f_chandle(c) !== c) $stop;
if (g_bit(1'h1) !== 1'h0) $stop;
if (g_bit(1'h0) !== 1'h1) $stop;
if (g_int(32'h1) !== 32'hfffffffe) $stop;
if (g_byte(8'h1) !== 8'hfe) $stop;
if (g_shortint(16'h1) !== 16'hfffe) $stop;
if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (g_chandle(c) !== c) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
function int int123(); int123 = 32'h123; endfunction
function bit f_bit ; input bit i; f_bit = ~i; endfunction
function int f_int ; input int i; f_int = ~i; endfunction
function byte f_byte ; input byte i; f_byte = ~i; endfunction
function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction
function longint f_longint ; input longint i; f_longint = ~i; endfunction
function chandle f_chandle ; input chandle i; f_chandle = i; endfunction
// Note there's no "input" here vvvv, it's the default
function bit g_bit (bit i); g_bit = ~i; endfunction
function int g_int (int i); g_int = ~i; endfunction
function byte g_byte (byte i); g_byte = ~i; endfunction
function shortint g_shortint(shortint i); g_shortint = ~i; endfunction
function longint g_longint (longint i); g_longint = ~i; endfunction
function chandle g_chandle (chandle i); g_chandle = i; endfunction
chandle c;
initial begin
if (int123() !== 32'h123) $stop;
if (f_bit(1'h1) !== 1'h0) $stop;
if (f_bit(1'h0) !== 1'h1) $stop;
if (f_int(32'h1) !== 32'hfffffffe) $stop;
if (f_byte(8'h1) !== 8'hfe) $stop;
if (f_shortint(16'h1) !== 16'hfffe) $stop;
if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (f_chandle(c) !== c) $stop;
if (g_bit(1'h1) !== 1'h0) $stop;
if (g_bit(1'h0) !== 1'h1) $stop;
if (g_int(32'h1) !== 32'hfffffffe) $stop;
if (g_byte(8'h1) !== 8'hfe) $stop;
if (g_shortint(16'h1) !== 16'hfffe) $stop;
if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (g_chandle(c) !== c) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
function int int123(); int123 = 32'h123; endfunction
function bit f_bit ; input bit i; f_bit = ~i; endfunction
function int f_int ; input int i; f_int = ~i; endfunction
function byte f_byte ; input byte i; f_byte = ~i; endfunction
function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction
function longint f_longint ; input longint i; f_longint = ~i; endfunction
function chandle f_chandle ; input chandle i; f_chandle = i; endfunction
// Note there's no "input" here vvvv, it's the default
function bit g_bit (bit i); g_bit = ~i; endfunction
function int g_int (int i); g_int = ~i; endfunction
function byte g_byte (byte i); g_byte = ~i; endfunction
function shortint g_shortint(shortint i); g_shortint = ~i; endfunction
function longint g_longint (longint i); g_longint = ~i; endfunction
function chandle g_chandle (chandle i); g_chandle = i; endfunction
chandle c;
initial begin
if (int123() !== 32'h123) $stop;
if (f_bit(1'h1) !== 1'h0) $stop;
if (f_bit(1'h0) !== 1'h1) $stop;
if (f_int(32'h1) !== 32'hfffffffe) $stop;
if (f_byte(8'h1) !== 8'hfe) $stop;
if (f_shortint(16'h1) !== 16'hfffe) $stop;
if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (f_chandle(c) !== c) $stop;
if (g_bit(1'h1) !== 1'h0) $stop;
if (g_bit(1'h0) !== 1'h1) $stop;
if (g_int(32'h1) !== 32'hfffffffe) $stop;
if (g_byte(8'h1) !== 8'hfe) $stop;
if (g_shortint(16'h1) !== 16'hfffe) $stop;
if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (g_chandle(c) !== c) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
function int int123(); int123 = 32'h123; endfunction
function bit f_bit ; input bit i; f_bit = ~i; endfunction
function int f_int ; input int i; f_int = ~i; endfunction
function byte f_byte ; input byte i; f_byte = ~i; endfunction
function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction
function longint f_longint ; input longint i; f_longint = ~i; endfunction
function chandle f_chandle ; input chandle i; f_chandle = i; endfunction
// Note there's no "input" here vvvv, it's the default
function bit g_bit (bit i); g_bit = ~i; endfunction
function int g_int (int i); g_int = ~i; endfunction
function byte g_byte (byte i); g_byte = ~i; endfunction
function shortint g_shortint(shortint i); g_shortint = ~i; endfunction
function longint g_longint (longint i); g_longint = ~i; endfunction
function chandle g_chandle (chandle i); g_chandle = i; endfunction
chandle c;
initial begin
if (int123() !== 32'h123) $stop;
if (f_bit(1'h1) !== 1'h0) $stop;
if (f_bit(1'h0) !== 1'h1) $stop;
if (f_int(32'h1) !== 32'hfffffffe) $stop;
if (f_byte(8'h1) !== 8'hfe) $stop;
if (f_shortint(16'h1) !== 16'hfffe) $stop;
if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (f_chandle(c) !== c) $stop;
if (g_bit(1'h1) !== 1'h0) $stop;
if (g_bit(1'h0) !== 1'h1) $stop;
if (g_int(32'h1) !== 32'hfffffffe) $stop;
if (g_byte(8'h1) !== 8'hfe) $stop;
if (g_shortint(16'h1) !== 16'hfffe) $stop;
if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (g_chandle(c) !== c) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
function int int123(); int123 = 32'h123; endfunction
function bit f_bit ; input bit i; f_bit = ~i; endfunction
function int f_int ; input int i; f_int = ~i; endfunction
function byte f_byte ; input byte i; f_byte = ~i; endfunction
function shortint f_shortint; input shortint i; f_shortint = ~i; endfunction
function longint f_longint ; input longint i; f_longint = ~i; endfunction
function chandle f_chandle ; input chandle i; f_chandle = i; endfunction
// Note there's no "input" here vvvv, it's the default
function bit g_bit (bit i); g_bit = ~i; endfunction
function int g_int (int i); g_int = ~i; endfunction
function byte g_byte (byte i); g_byte = ~i; endfunction
function shortint g_shortint(shortint i); g_shortint = ~i; endfunction
function longint g_longint (longint i); g_longint = ~i; endfunction
function chandle g_chandle (chandle i); g_chandle = i; endfunction
chandle c;
initial begin
if (int123() !== 32'h123) $stop;
if (f_bit(1'h1) !== 1'h0) $stop;
if (f_bit(1'h0) !== 1'h1) $stop;
if (f_int(32'h1) !== 32'hfffffffe) $stop;
if (f_byte(8'h1) !== 8'hfe) $stop;
if (f_shortint(16'h1) !== 16'hfffe) $stop;
if (f_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (f_chandle(c) !== c) $stop;
if (g_bit(1'h1) !== 1'h0) $stop;
if (g_bit(1'h0) !== 1'h1) $stop;
if (g_int(32'h1) !== 32'hfffffffe) $stop;
if (g_byte(8'h1) !== 8'hfe) $stop;
if (g_shortint(16'h1) !== 16'hfffe) $stop;
if (g_longint(64'h1) !== 64'hfffffffffffffffe) $stop;
if (g_chandle(c) !== c) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub3 (/*AUTOARG*/
// Outputs
outr,
// Inputs
clk, index
);
input clk;
input [9:0] index;
output [3:0] outr;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [3:0] outr;
// End of automatics
// =============================
// Created from perl
//for $i (0..255) { $r=rand(4); printf "\t8'h%02x: begin outr <= outr^index[8:5]^4'h%01x; end\n", $i,
//rand(256); };
// Reset cheating
initial outr = 4'b0;
always @(posedge clk) begin
case (index[7:0])
8'h00: begin outr <= 4'h0; end
8'h01: begin /*No Change*/ end
8'h02: begin outr <= outr^index[8:5]^4'ha; end
8'h03: begin outr <= outr^index[8:5]^4'h4; end
8'h04: begin outr <= outr^index[8:5]^4'hd; end
8'h05: begin outr <= outr^index[8:5]^4'h1; end
8'h06: begin outr <= outr^index[8:5]^4'hf; end
8'h07: begin outr <= outr^index[8:5]^4'he; end
8'h08: begin outr <= outr^index[8:5]^4'h0; end
8'h09: begin outr <= outr^index[8:5]^4'h4; end
8'h0a: begin outr <= outr^index[8:5]^4'h5; end
8'h0b: begin outr <= outr^index[8:5]^4'ha; end
8'h0c: begin outr <= outr^index[8:5]^4'h2; end
8'h0d: begin outr <= outr^index[8:5]^4'hf; end
8'h0e: begin outr <= outr^index[8:5]^4'h5; end
8'h0f: begin outr <= outr^index[8:5]^4'h0; end
8'h10: begin outr <= outr^index[8:5]^4'h3; end
8'h11: begin outr <= outr^index[8:5]^4'hb; end
8'h12: begin outr <= outr^index[8:5]^4'h0; end
8'h13: begin outr <= outr^index[8:5]^4'hf; end
8'h14: begin outr <= outr^index[8:5]^4'h3; end
8'h15: begin outr <= outr^index[8:5]^4'h5; end
8'h16: begin outr <= outr^index[8:5]^4'h7; end
8'h17: begin outr <= outr^index[8:5]^4'h2; end
8'h18: begin outr <= outr^index[8:5]^4'h3; end
8'h19: begin outr <= outr^index[8:5]^4'hb; end
8'h1a: begin outr <= outr^index[8:5]^4'h5; end
8'h1b: begin outr <= outr^index[8:5]^4'h4; end
8'h1c: begin outr <= outr^index[8:5]^4'h2; end
8'h1d: begin outr <= outr^index[8:5]^4'hf; end
8'h1e: begin outr <= outr^index[8:5]^4'h0; end
8'h1f: begin outr <= outr^index[8:5]^4'h4; end
8'h20: begin outr <= outr^index[8:5]^4'h6; end
8'h21: begin outr <= outr^index[8:5]^4'ha; end
8'h22: begin outr <= outr^index[8:5]^4'h6; end
8'h23: begin outr <= outr^index[8:5]^4'hb; end
8'h24: begin outr <= outr^index[8:5]^4'ha; end
8'h25: begin outr <= outr^index[8:5]^4'he; end
8'h26: begin outr <= outr^index[8:5]^4'h7; end
8'h27: begin outr <= outr^index[8:5]^4'ha; end
8'h28: begin outr <= outr^index[8:5]^4'h3; end
8'h29: begin outr <= outr^index[8:5]^4'h8; end
8'h2a: begin outr <= outr^index[8:5]^4'h1; end
8'h2b: begin outr <= outr^index[8:5]^4'h8; end
8'h2c: begin outr <= outr^index[8:5]^4'h4; end
8'h2d: begin outr <= outr^index[8:5]^4'h4; end
8'h2e: begin outr <= outr^index[8:5]^4'he; end
8'h2f: begin outr <= outr^index[8:5]^4'h8; end
8'h30: begin outr <= outr^index[8:5]^4'ha; end
8'h31: begin outr <= outr^index[8:5]^4'h7; end
8'h32: begin outr <= outr^index[8:5]^4'h0; end
8'h33: begin outr <= outr^index[8:5]^4'h3; end
8'h34: begin outr <= outr^index[8:5]^4'h1; end
8'h35: begin outr <= outr^index[8:5]^4'h3; end
8'h36: begin outr <= outr^index[8:5]^4'h4; end
8'h37: begin outr <= outr^index[8:5]^4'h6; end
8'h38: begin outr <= outr^index[8:5]^4'h4; end
8'h39: begin outr <= outr^index[8:5]^4'hb; end
8'h3a: begin outr <= outr^index[8:5]^4'h7; end
8'h3b: begin outr <= outr^index[8:5]^4'h1; end
8'h3c: begin outr <= outr^index[8:5]^4'h2; end
8'h3d: begin outr <= outr^index[8:5]^4'h0; end
8'h3e: begin outr <= outr^index[8:5]^4'h2; end
8'h3f: begin outr <= outr^index[8:5]^4'ha; end
8'h40: begin outr <= outr^index[8:5]^4'h7; end
8'h41: begin outr <= outr^index[8:5]^4'h5; end
8'h42: begin outr <= outr^index[8:5]^4'h5; end
8'h43: begin outr <= outr^index[8:5]^4'h4; end
8'h44: begin outr <= outr^index[8:5]^4'h8; end
8'h45: begin outr <= outr^index[8:5]^4'h5; end
8'h46: begin outr <= outr^index[8:5]^4'hf; end
8'h47: begin outr <= outr^index[8:5]^4'h6; end
8'h48: begin outr <= outr^index[8:5]^4'h7; end
8'h49: begin outr <= outr^index[8:5]^4'h4; end
8'h4a: begin outr <= outr^index[8:5]^4'ha; end
8'h4b: begin outr <= outr^index[8:5]^4'hd; end
8'h4c: begin outr <= outr^index[8:5]^4'hb; end
8'h4d: begin outr <= outr^index[8:5]^4'hf; end
8'h4e: begin outr <= outr^index[8:5]^4'hd; end
8'h4f: begin outr <= outr^index[8:5]^4'h7; end
8'h50: begin outr <= outr^index[8:5]^4'h9; end
8'h51: begin outr <= outr^index[8:5]^4'ha; end
8'h52: begin outr <= outr^index[8:5]^4'hf; end
8'h53: begin outr <= outr^index[8:5]^4'h3; end
8'h54: begin outr <= outr^index[8:5]^4'h1; end
8'h55: begin outr <= outr^index[8:5]^4'h0; end
8'h56: begin outr <= outr^index[8:5]^4'h2; end
8'h57: begin outr <= outr^index[8:5]^4'h9; end
8'h58: begin outr <= outr^index[8:5]^4'h2; end
8'h59: begin outr <= outr^index[8:5]^4'h4; end
8'h5a: begin outr <= outr^index[8:5]^4'hc; end
8'h5b: begin outr <= outr^index[8:5]^4'hd; end
8'h5c: begin outr <= outr^index[8:5]^4'h3; end
8'h5d: begin outr <= outr^index[8:5]^4'hb; end
8'h5e: begin outr <= outr^index[8:5]^4'hd; end
8'h5f: begin outr <= outr^index[8:5]^4'h7; end
8'h60: begin outr <= outr^index[8:5]^4'h7; end
8'h61: begin outr <= outr^index[8:5]^4'h3; end
8'h62: begin outr <= outr^index[8:5]^4'h3; end
8'h63: begin outr <= outr^index[8:5]^4'hb; end
8'h64: begin outr <= outr^index[8:5]^4'h9; end
8'h65: begin outr <= outr^index[8:5]^4'h4; end
8'h66: begin outr <= outr^index[8:5]^4'h3; end
8'h67: begin outr <= outr^index[8:5]^4'h6; end
8'h68: begin outr <= outr^index[8:5]^4'h7; end
8'h69: begin outr <= outr^index[8:5]^4'h7; end
8'h6a: begin outr <= outr^index[8:5]^4'hf; end
8'h6b: begin outr <= outr^index[8:5]^4'h6; end
8'h6c: begin outr <= outr^index[8:5]^4'h8; end
8'h6d: begin outr <= outr^index[8:5]^4'he; end
8'h6e: begin outr <= outr^index[8:5]^4'h4; end
8'h6f: begin outr <= outr^index[8:5]^4'h6; end
8'h70: begin outr <= outr^index[8:5]^4'hc; end
8'h71: begin outr <= outr^index[8:5]^4'h9; end
8'h72: begin outr <= outr^index[8:5]^4'h5; end
8'h73: begin outr <= outr^index[8:5]^4'ha; end
8'h74: begin outr <= outr^index[8:5]^4'h7; end
8'h75: begin outr <= outr^index[8:5]^4'h0; end
8'h76: begin outr <= outr^index[8:5]^4'h1; end
8'h77: begin outr <= outr^index[8:5]^4'he; end
8'h78: begin outr <= outr^index[8:5]^4'ha; end
8'h79: begin outr <= outr^index[8:5]^4'h7; end
8'h7a: begin outr <= outr^index[8:5]^4'hf; end
8'h7b: begin outr <= outr^index[8:5]^4'he; end
8'h7c: begin outr <= outr^index[8:5]^4'h6; end
8'h7d: begin outr <= outr^index[8:5]^4'hc; end
8'h7e: begin outr <= outr^index[8:5]^4'hc; end
8'h7f: begin outr <= outr^index[8:5]^4'h0; end
8'h80: begin outr <= outr^index[8:5]^4'h0; end
8'h81: begin outr <= outr^index[8:5]^4'hd; end
8'h82: begin outr <= outr^index[8:5]^4'hb; end
8'h83: begin outr <= outr^index[8:5]^4'hc; end
8'h84: begin outr <= outr^index[8:5]^4'h2; end
8'h85: begin outr <= outr^index[8:5]^4'h8; end
8'h86: begin outr <= outr^index[8:5]^4'h3; end
8'h87: begin outr <= outr^index[8:5]^4'ha; end
8'h88: begin outr <= outr^index[8:5]^4'he; end
8'h89: begin outr <= outr^index[8:5]^4'h9; end
8'h8a: begin outr <= outr^index[8:5]^4'h1; end
8'h8b: begin outr <= outr^index[8:5]^4'h1; end
8'h8c: begin outr <= outr^index[8:5]^4'hc; end
8'h8d: begin outr <= outr^index[8:5]^4'h2; end
8'h8e: begin outr <= outr^index[8:5]^4'h2; end
8'h8f: begin outr <= outr^index[8:5]^4'hd; end
8'h90: begin outr <= outr^index[8:5]^4'h0; end
8'h91: begin outr <= outr^index[8:5]^4'h6; end
8'h92: begin outr <= outr^index[8:5]^4'h7; end
8'h93: begin outr <= outr^index[8:5]^4'hc; end
8'h94: begin outr <= outr^index[8:5]^4'hb; end
8'h95: begin outr <= outr^index[8:5]^4'h3; end
8'h96: begin outr <= outr^index[8:5]^4'h0; end
8'h97: begin outr <= outr^index[8:5]^4'hc; end
8'h98: begin outr <= outr^index[8:5]^4'hc; end
8'h99: begin outr <= outr^index[8:5]^4'hb; end
8'h9a: begin outr <= outr^index[8:5]^4'h6; end
8'h9b: begin outr <= outr^index[8:5]^4'h5; end
8'h9c: begin outr <= outr^index[8:5]^4'h5; end
8'h9d: begin outr <= outr^index[8:5]^4'h4; end
8'h9e: begin outr <= outr^index[8:5]^4'h7; end
8'h9f: begin outr <= outr^index[8:5]^4'he; end
8'ha0: begin outr <= outr^index[8:5]^4'hc; end
8'ha1: begin outr <= outr^index[8:5]^4'hc; end
8'ha2: begin outr <= outr^index[8:5]^4'h0; end
8'ha3: begin outr <= outr^index[8:5]^4'h1; end
8'ha4: begin outr <= outr^index[8:5]^4'hd; end
8'ha5: begin outr <= outr^index[8:5]^4'h3; end
8'ha6: begin outr <= outr^index[8:5]^4'hc; end
8'ha7: begin outr <= outr^index[8:5]^4'h2; end
8'ha8: begin outr <= outr^index[8:5]^4'h3; end
8'ha9: begin outr <= outr^index[8:5]^4'hd; end
8'haa: begin outr <= outr^index[8:5]^4'h5; end
8'hab: begin outr <= outr^index[8:5]^4'hb; end
8'hac: begin outr <= outr^index[8:5]^4'he; end
8'had: begin outr <= outr^index[8:5]^4'h0; end
8'hae: begin outr <= outr^index[8:5]^4'hf; end
8'haf: begin outr <= outr^index[8:5]^4'h9; end
8'hb0: begin outr <= outr^index[8:5]^4'hf; end
8'hb1: begin outr <= outr^index[8:5]^4'h7; end
8'hb2: begin outr <= outr^index[8:5]^4'h9; end
8'hb3: begin outr <= outr^index[8:5]^4'hf; end
8'hb4: begin outr <= outr^index[8:5]^4'he; end
8'hb5: begin outr <= outr^index[8:5]^4'h3; end
8'hb6: begin outr <= outr^index[8:5]^4'he; end
8'hb7: begin outr <= outr^index[8:5]^4'h8; end
8'hb8: begin outr <= outr^index[8:5]^4'hf; end
8'hb9: begin outr <= outr^index[8:5]^4'hd; end
8'hba: begin outr <= outr^index[8:5]^4'h3; end
8'hbb: begin outr <= outr^index[8:5]^4'h5; end
8'hbc: begin outr <= outr^index[8:5]^4'hd; end
8'hbd: begin outr <= outr^index[8:5]^4'ha; end
8'hbe: begin outr <= outr^index[8:5]^4'h7; end
8'hbf: begin outr <= outr^index[8:5]^4'he; end
8'hc0: begin outr <= outr^index[8:5]^4'h2; end
8'hc1: begin outr <= outr^index[8:5]^4'he; end
8'hc2: begin outr <= outr^index[8:5]^4'h9; end
8'hc3: begin outr <= outr^index[8:5]^4'hb; end
8'hc4: begin outr <= outr^index[8:5]^4'h0; end
8'hc5: begin outr <= outr^index[8:5]^4'h5; end
8'hc6: begin outr <= outr^index[8:5]^4'h9; end
8'hc7: begin outr <= outr^index[8:5]^4'h6; end
8'hc8: begin outr <= outr^index[8:5]^4'ha; end
8'hc9: begin outr <= outr^index[8:5]^4'hf; end
8'hca: begin outr <= outr^index[8:5]^4'h3; end
8'hcb: begin outr <= outr^index[8:5]^4'hb; end
8'hcc: begin outr <= outr^index[8:5]^4'he; end
8'hcd: begin outr <= outr^index[8:5]^4'h2; end
8'hce: begin outr <= outr^index[8:5]^4'h5; end
8'hcf: begin outr <= outr^index[8:5]^4'hf; end
8'hd0: begin outr <= outr^index[8:5]^4'h2; end
8'hd1: begin outr <= outr^index[8:5]^4'h9; end
8'hd2: begin outr <= outr^index[8:5]^4'hb; end
8'hd3: begin outr <= outr^index[8:5]^4'h8; end
8'hd4: begin outr <= outr^index[8:5]^4'h0; end
8'hd5: begin outr <= outr^index[8:5]^4'h2; end
8'hd6: begin outr <= outr^index[8:5]^4'hb; end
8'hd7: begin outr <= outr^index[8:5]^4'h2; end
8'hd8: begin outr <= outr^index[8:5]^4'ha; end
8'hd9: begin outr <= outr^index[8:5]^4'hf; end
8'hda: begin outr <= outr^index[8:5]^4'h8; end
8'hdb: begin outr <= outr^index[8:5]^4'h4; end
8'hdc: begin outr <= outr^index[8:5]^4'he; end
8'hdd: begin outr <= outr^index[8:5]^4'h6; end
8'hde: begin outr <= outr^index[8:5]^4'h9; end
8'hdf: begin outr <= outr^index[8:5]^4'h9; end
8'he0: begin outr <= outr^index[8:5]^4'h7; end
8'he1: begin outr <= outr^index[8:5]^4'h0; end
8'he2: begin outr <= outr^index[8:5]^4'h9; end
8'he3: begin outr <= outr^index[8:5]^4'h3; end
8'he4: begin outr <= outr^index[8:5]^4'h2; end
8'he5: begin outr <= outr^index[8:5]^4'h4; end
8'he6: begin outr <= outr^index[8:5]^4'h5; end
8'he7: begin outr <= outr^index[8:5]^4'h5; end
8'he8: begin outr <= outr^index[8:5]^4'hf; end
8'he9: begin outr <= outr^index[8:5]^4'ha; end
8'hea: begin outr <= outr^index[8:5]^4'hc; end
8'heb: begin outr <= outr^index[8:5]^4'hd; end
8'hec: begin outr <= outr^index[8:5]^4'h1; end
8'hed: begin outr <= outr^index[8:5]^4'h5; end
8'hee: begin outr <= outr^index[8:5]^4'h9; end
8'hef: begin outr <= outr^index[8:5]^4'h0; end
8'hf0: begin outr <= outr^index[8:5]^4'hd; end
8'hf1: begin outr <= outr^index[8:5]^4'hf; end
8'hf2: begin outr <= outr^index[8:5]^4'h4; end
8'hf3: begin outr <= outr^index[8:5]^4'ha; end
8'hf4: begin outr <= outr^index[8:5]^4'h8; end
8'hf5: begin outr <= outr^index[8:5]^4'he; end
8'hf6: begin outr <= outr^index[8:5]^4'he; end
8'hf7: begin outr <= outr^index[8:5]^4'h1; end
8'hf8: begin outr <= outr^index[8:5]^4'h6; end
8'hf9: begin outr <= outr^index[8:5]^4'h0; end
8'hfa: begin outr <= outr^index[8:5]^4'h5; end
8'hfb: begin outr <= outr^index[8:5]^4'h1; end
8'hfc: begin outr <= outr^index[8:5]^4'h8; end
8'hfd: begin outr <= outr^index[8:5]^4'h6; end
8'hfe: begin outr <= outr^index[8:5]^4'h1; end
default: begin outr <= outr^index[8:5]^4'h6; end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t_case_huge_sub3 (/*AUTOARG*/
// Outputs
outr,
// Inputs
clk, index
);
input clk;
input [9:0] index;
output [3:0] outr;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [3:0] outr;
// End of automatics
// =============================
// Created from perl
//for $i (0..255) { $r=rand(4); printf "\t8'h%02x: begin outr <= outr^index[8:5]^4'h%01x; end\n", $i,
//rand(256); };
// Reset cheating
initial outr = 4'b0;
always @(posedge clk) begin
case (index[7:0])
8'h00: begin outr <= 4'h0; end
8'h01: begin /*No Change*/ end
8'h02: begin outr <= outr^index[8:5]^4'ha; end
8'h03: begin outr <= outr^index[8:5]^4'h4; end
8'h04: begin outr <= outr^index[8:5]^4'hd; end
8'h05: begin outr <= outr^index[8:5]^4'h1; end
8'h06: begin outr <= outr^index[8:5]^4'hf; end
8'h07: begin outr <= outr^index[8:5]^4'he; end
8'h08: begin outr <= outr^index[8:5]^4'h0; end
8'h09: begin outr <= outr^index[8:5]^4'h4; end
8'h0a: begin outr <= outr^index[8:5]^4'h5; end
8'h0b: begin outr <= outr^index[8:5]^4'ha; end
8'h0c: begin outr <= outr^index[8:5]^4'h2; end
8'h0d: begin outr <= outr^index[8:5]^4'hf; end
8'h0e: begin outr <= outr^index[8:5]^4'h5; end
8'h0f: begin outr <= outr^index[8:5]^4'h0; end
8'h10: begin outr <= outr^index[8:5]^4'h3; end
8'h11: begin outr <= outr^index[8:5]^4'hb; end
8'h12: begin outr <= outr^index[8:5]^4'h0; end
8'h13: begin outr <= outr^index[8:5]^4'hf; end
8'h14: begin outr <= outr^index[8:5]^4'h3; end
8'h15: begin outr <= outr^index[8:5]^4'h5; end
8'h16: begin outr <= outr^index[8:5]^4'h7; end
8'h17: begin outr <= outr^index[8:5]^4'h2; end
8'h18: begin outr <= outr^index[8:5]^4'h3; end
8'h19: begin outr <= outr^index[8:5]^4'hb; end
8'h1a: begin outr <= outr^index[8:5]^4'h5; end
8'h1b: begin outr <= outr^index[8:5]^4'h4; end
8'h1c: begin outr <= outr^index[8:5]^4'h2; end
8'h1d: begin outr <= outr^index[8:5]^4'hf; end
8'h1e: begin outr <= outr^index[8:5]^4'h0; end
8'h1f: begin outr <= outr^index[8:5]^4'h4; end
8'h20: begin outr <= outr^index[8:5]^4'h6; end
8'h21: begin outr <= outr^index[8:5]^4'ha; end
8'h22: begin outr <= outr^index[8:5]^4'h6; end
8'h23: begin outr <= outr^index[8:5]^4'hb; end
8'h24: begin outr <= outr^index[8:5]^4'ha; end
8'h25: begin outr <= outr^index[8:5]^4'he; end
8'h26: begin outr <= outr^index[8:5]^4'h7; end
8'h27: begin outr <= outr^index[8:5]^4'ha; end
8'h28: begin outr <= outr^index[8:5]^4'h3; end
8'h29: begin outr <= outr^index[8:5]^4'h8; end
8'h2a: begin outr <= outr^index[8:5]^4'h1; end
8'h2b: begin outr <= outr^index[8:5]^4'h8; end
8'h2c: begin outr <= outr^index[8:5]^4'h4; end
8'h2d: begin outr <= outr^index[8:5]^4'h4; end
8'h2e: begin outr <= outr^index[8:5]^4'he; end
8'h2f: begin outr <= outr^index[8:5]^4'h8; end
8'h30: begin outr <= outr^index[8:5]^4'ha; end
8'h31: begin outr <= outr^index[8:5]^4'h7; end
8'h32: begin outr <= outr^index[8:5]^4'h0; end
8'h33: begin outr <= outr^index[8:5]^4'h3; end
8'h34: begin outr <= outr^index[8:5]^4'h1; end
8'h35: begin outr <= outr^index[8:5]^4'h3; end
8'h36: begin outr <= outr^index[8:5]^4'h4; end
8'h37: begin outr <= outr^index[8:5]^4'h6; end
8'h38: begin outr <= outr^index[8:5]^4'h4; end
8'h39: begin outr <= outr^index[8:5]^4'hb; end
8'h3a: begin outr <= outr^index[8:5]^4'h7; end
8'h3b: begin outr <= outr^index[8:5]^4'h1; end
8'h3c: begin outr <= outr^index[8:5]^4'h2; end
8'h3d: begin outr <= outr^index[8:5]^4'h0; end
8'h3e: begin outr <= outr^index[8:5]^4'h2; end
8'h3f: begin outr <= outr^index[8:5]^4'ha; end
8'h40: begin outr <= outr^index[8:5]^4'h7; end
8'h41: begin outr <= outr^index[8:5]^4'h5; end
8'h42: begin outr <= outr^index[8:5]^4'h5; end
8'h43: begin outr <= outr^index[8:5]^4'h4; end
8'h44: begin outr <= outr^index[8:5]^4'h8; end
8'h45: begin outr <= outr^index[8:5]^4'h5; end
8'h46: begin outr <= outr^index[8:5]^4'hf; end
8'h47: begin outr <= outr^index[8:5]^4'h6; end
8'h48: begin outr <= outr^index[8:5]^4'h7; end
8'h49: begin outr <= outr^index[8:5]^4'h4; end
8'h4a: begin outr <= outr^index[8:5]^4'ha; end
8'h4b: begin outr <= outr^index[8:5]^4'hd; end
8'h4c: begin outr <= outr^index[8:5]^4'hb; end
8'h4d: begin outr <= outr^index[8:5]^4'hf; end
8'h4e: begin outr <= outr^index[8:5]^4'hd; end
8'h4f: begin outr <= outr^index[8:5]^4'h7; end
8'h50: begin outr <= outr^index[8:5]^4'h9; end
8'h51: begin outr <= outr^index[8:5]^4'ha; end
8'h52: begin outr <= outr^index[8:5]^4'hf; end
8'h53: begin outr <= outr^index[8:5]^4'h3; end
8'h54: begin outr <= outr^index[8:5]^4'h1; end
8'h55: begin outr <= outr^index[8:5]^4'h0; end
8'h56: begin outr <= outr^index[8:5]^4'h2; end
8'h57: begin outr <= outr^index[8:5]^4'h9; end
8'h58: begin outr <= outr^index[8:5]^4'h2; end
8'h59: begin outr <= outr^index[8:5]^4'h4; end
8'h5a: begin outr <= outr^index[8:5]^4'hc; end
8'h5b: begin outr <= outr^index[8:5]^4'hd; end
8'h5c: begin outr <= outr^index[8:5]^4'h3; end
8'h5d: begin outr <= outr^index[8:5]^4'hb; end
8'h5e: begin outr <= outr^index[8:5]^4'hd; end
8'h5f: begin outr <= outr^index[8:5]^4'h7; end
8'h60: begin outr <= outr^index[8:5]^4'h7; end
8'h61: begin outr <= outr^index[8:5]^4'h3; end
8'h62: begin outr <= outr^index[8:5]^4'h3; end
8'h63: begin outr <= outr^index[8:5]^4'hb; end
8'h64: begin outr <= outr^index[8:5]^4'h9; end
8'h65: begin outr <= outr^index[8:5]^4'h4; end
8'h66: begin outr <= outr^index[8:5]^4'h3; end
8'h67: begin outr <= outr^index[8:5]^4'h6; end
8'h68: begin outr <= outr^index[8:5]^4'h7; end
8'h69: begin outr <= outr^index[8:5]^4'h7; end
8'h6a: begin outr <= outr^index[8:5]^4'hf; end
8'h6b: begin outr <= outr^index[8:5]^4'h6; end
8'h6c: begin outr <= outr^index[8:5]^4'h8; end
8'h6d: begin outr <= outr^index[8:5]^4'he; end
8'h6e: begin outr <= outr^index[8:5]^4'h4; end
8'h6f: begin outr <= outr^index[8:5]^4'h6; end
8'h70: begin outr <= outr^index[8:5]^4'hc; end
8'h71: begin outr <= outr^index[8:5]^4'h9; end
8'h72: begin outr <= outr^index[8:5]^4'h5; end
8'h73: begin outr <= outr^index[8:5]^4'ha; end
8'h74: begin outr <= outr^index[8:5]^4'h7; end
8'h75: begin outr <= outr^index[8:5]^4'h0; end
8'h76: begin outr <= outr^index[8:5]^4'h1; end
8'h77: begin outr <= outr^index[8:5]^4'he; end
8'h78: begin outr <= outr^index[8:5]^4'ha; end
8'h79: begin outr <= outr^index[8:5]^4'h7; end
8'h7a: begin outr <= outr^index[8:5]^4'hf; end
8'h7b: begin outr <= outr^index[8:5]^4'he; end
8'h7c: begin outr <= outr^index[8:5]^4'h6; end
8'h7d: begin outr <= outr^index[8:5]^4'hc; end
8'h7e: begin outr <= outr^index[8:5]^4'hc; end
8'h7f: begin outr <= outr^index[8:5]^4'h0; end
8'h80: begin outr <= outr^index[8:5]^4'h0; end
8'h81: begin outr <= outr^index[8:5]^4'hd; end
8'h82: begin outr <= outr^index[8:5]^4'hb; end
8'h83: begin outr <= outr^index[8:5]^4'hc; end
8'h84: begin outr <= outr^index[8:5]^4'h2; end
8'h85: begin outr <= outr^index[8:5]^4'h8; end
8'h86: begin outr <= outr^index[8:5]^4'h3; end
8'h87: begin outr <= outr^index[8:5]^4'ha; end
8'h88: begin outr <= outr^index[8:5]^4'he; end
8'h89: begin outr <= outr^index[8:5]^4'h9; end
8'h8a: begin outr <= outr^index[8:5]^4'h1; end
8'h8b: begin outr <= outr^index[8:5]^4'h1; end
8'h8c: begin outr <= outr^index[8:5]^4'hc; end
8'h8d: begin outr <= outr^index[8:5]^4'h2; end
8'h8e: begin outr <= outr^index[8:5]^4'h2; end
8'h8f: begin outr <= outr^index[8:5]^4'hd; end
8'h90: begin outr <= outr^index[8:5]^4'h0; end
8'h91: begin outr <= outr^index[8:5]^4'h6; end
8'h92: begin outr <= outr^index[8:5]^4'h7; end
8'h93: begin outr <= outr^index[8:5]^4'hc; end
8'h94: begin outr <= outr^index[8:5]^4'hb; end
8'h95: begin outr <= outr^index[8:5]^4'h3; end
8'h96: begin outr <= outr^index[8:5]^4'h0; end
8'h97: begin outr <= outr^index[8:5]^4'hc; end
8'h98: begin outr <= outr^index[8:5]^4'hc; end
8'h99: begin outr <= outr^index[8:5]^4'hb; end
8'h9a: begin outr <= outr^index[8:5]^4'h6; end
8'h9b: begin outr <= outr^index[8:5]^4'h5; end
8'h9c: begin outr <= outr^index[8:5]^4'h5; end
8'h9d: begin outr <= outr^index[8:5]^4'h4; end
8'h9e: begin outr <= outr^index[8:5]^4'h7; end
8'h9f: begin outr <= outr^index[8:5]^4'he; end
8'ha0: begin outr <= outr^index[8:5]^4'hc; end
8'ha1: begin outr <= outr^index[8:5]^4'hc; end
8'ha2: begin outr <= outr^index[8:5]^4'h0; end
8'ha3: begin outr <= outr^index[8:5]^4'h1; end
8'ha4: begin outr <= outr^index[8:5]^4'hd; end
8'ha5: begin outr <= outr^index[8:5]^4'h3; end
8'ha6: begin outr <= outr^index[8:5]^4'hc; end
8'ha7: begin outr <= outr^index[8:5]^4'h2; end
8'ha8: begin outr <= outr^index[8:5]^4'h3; end
8'ha9: begin outr <= outr^index[8:5]^4'hd; end
8'haa: begin outr <= outr^index[8:5]^4'h5; end
8'hab: begin outr <= outr^index[8:5]^4'hb; end
8'hac: begin outr <= outr^index[8:5]^4'he; end
8'had: begin outr <= outr^index[8:5]^4'h0; end
8'hae: begin outr <= outr^index[8:5]^4'hf; end
8'haf: begin outr <= outr^index[8:5]^4'h9; end
8'hb0: begin outr <= outr^index[8:5]^4'hf; end
8'hb1: begin outr <= outr^index[8:5]^4'h7; end
8'hb2: begin outr <= outr^index[8:5]^4'h9; end
8'hb3: begin outr <= outr^index[8:5]^4'hf; end
8'hb4: begin outr <= outr^index[8:5]^4'he; end
8'hb5: begin outr <= outr^index[8:5]^4'h3; end
8'hb6: begin outr <= outr^index[8:5]^4'he; end
8'hb7: begin outr <= outr^index[8:5]^4'h8; end
8'hb8: begin outr <= outr^index[8:5]^4'hf; end
8'hb9: begin outr <= outr^index[8:5]^4'hd; end
8'hba: begin outr <= outr^index[8:5]^4'h3; end
8'hbb: begin outr <= outr^index[8:5]^4'h5; end
8'hbc: begin outr <= outr^index[8:5]^4'hd; end
8'hbd: begin outr <= outr^index[8:5]^4'ha; end
8'hbe: begin outr <= outr^index[8:5]^4'h7; end
8'hbf: begin outr <= outr^index[8:5]^4'he; end
8'hc0: begin outr <= outr^index[8:5]^4'h2; end
8'hc1: begin outr <= outr^index[8:5]^4'he; end
8'hc2: begin outr <= outr^index[8:5]^4'h9; end
8'hc3: begin outr <= outr^index[8:5]^4'hb; end
8'hc4: begin outr <= outr^index[8:5]^4'h0; end
8'hc5: begin outr <= outr^index[8:5]^4'h5; end
8'hc6: begin outr <= outr^index[8:5]^4'h9; end
8'hc7: begin outr <= outr^index[8:5]^4'h6; end
8'hc8: begin outr <= outr^index[8:5]^4'ha; end
8'hc9: begin outr <= outr^index[8:5]^4'hf; end
8'hca: begin outr <= outr^index[8:5]^4'h3; end
8'hcb: begin outr <= outr^index[8:5]^4'hb; end
8'hcc: begin outr <= outr^index[8:5]^4'he; end
8'hcd: begin outr <= outr^index[8:5]^4'h2; end
8'hce: begin outr <= outr^index[8:5]^4'h5; end
8'hcf: begin outr <= outr^index[8:5]^4'hf; end
8'hd0: begin outr <= outr^index[8:5]^4'h2; end
8'hd1: begin outr <= outr^index[8:5]^4'h9; end
8'hd2: begin outr <= outr^index[8:5]^4'hb; end
8'hd3: begin outr <= outr^index[8:5]^4'h8; end
8'hd4: begin outr <= outr^index[8:5]^4'h0; end
8'hd5: begin outr <= outr^index[8:5]^4'h2; end
8'hd6: begin outr <= outr^index[8:5]^4'hb; end
8'hd7: begin outr <= outr^index[8:5]^4'h2; end
8'hd8: begin outr <= outr^index[8:5]^4'ha; end
8'hd9: begin outr <= outr^index[8:5]^4'hf; end
8'hda: begin outr <= outr^index[8:5]^4'h8; end
8'hdb: begin outr <= outr^index[8:5]^4'h4; end
8'hdc: begin outr <= outr^index[8:5]^4'he; end
8'hdd: begin outr <= outr^index[8:5]^4'h6; end
8'hde: begin outr <= outr^index[8:5]^4'h9; end
8'hdf: begin outr <= outr^index[8:5]^4'h9; end
8'he0: begin outr <= outr^index[8:5]^4'h7; end
8'he1: begin outr <= outr^index[8:5]^4'h0; end
8'he2: begin outr <= outr^index[8:5]^4'h9; end
8'he3: begin outr <= outr^index[8:5]^4'h3; end
8'he4: begin outr <= outr^index[8:5]^4'h2; end
8'he5: begin outr <= outr^index[8:5]^4'h4; end
8'he6: begin outr <= outr^index[8:5]^4'h5; end
8'he7: begin outr <= outr^index[8:5]^4'h5; end
8'he8: begin outr <= outr^index[8:5]^4'hf; end
8'he9: begin outr <= outr^index[8:5]^4'ha; end
8'hea: begin outr <= outr^index[8:5]^4'hc; end
8'heb: begin outr <= outr^index[8:5]^4'hd; end
8'hec: begin outr <= outr^index[8:5]^4'h1; end
8'hed: begin outr <= outr^index[8:5]^4'h5; end
8'hee: begin outr <= outr^index[8:5]^4'h9; end
8'hef: begin outr <= outr^index[8:5]^4'h0; end
8'hf0: begin outr <= outr^index[8:5]^4'hd; end
8'hf1: begin outr <= outr^index[8:5]^4'hf; end
8'hf2: begin outr <= outr^index[8:5]^4'h4; end
8'hf3: begin outr <= outr^index[8:5]^4'ha; end
8'hf4: begin outr <= outr^index[8:5]^4'h8; end
8'hf5: begin outr <= outr^index[8:5]^4'he; end
8'hf6: begin outr <= outr^index[8:5]^4'he; end
8'hf7: begin outr <= outr^index[8:5]^4'h1; end
8'hf8: begin outr <= outr^index[8:5]^4'h6; end
8'hf9: begin outr <= outr^index[8:5]^4'h0; end
8'hfa: begin outr <= outr^index[8:5]^4'h5; end
8'hfb: begin outr <= outr^index[8:5]^4'h1; end
8'hfc: begin outr <= outr^index[8:5]^4'h8; end
8'hfd: begin outr <= outr^index[8:5]^4'h6; end
8'hfe: begin outr <= outr^index[8:5]^4'h1; end
default: begin outr <= outr^index[8:5]^4'h6; end
endcase
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dev_rx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 30,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dev_rx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 30,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dev_rx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 30,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [31:0] inp = crc[31:0];
wire reset = (cyc < 5);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] outp; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.outp (outp[31:0]),
// Inputs
.reset (reset),
.clk (clk),
.inp (inp[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, outp};
// What checksum will we end up with
`define EXPECTED_SUM 64'ha7f0a34f9cf56ccb
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
outp,
// Inputs
reset, clk, inp
);
input reset;
input clk;
input [31:0] inp;
output [31:0] outp;
function [31:0] no_inline_function;
input [31:0] var1;
input [31:0] var2;
/*verilator no_inline_task*/
reg [31*2:0] product1 ;
reg [31*2:0] product2 ;
integer i;
reg [31:0] tmp;
begin
product2 = {(31*2+1){1'b0}};
for (i = 0; i < 32; i = i + 1)
if (var2[i]) begin
product1 = { {31*2+1-32{1'b0}}, var1} << i;
product2 = product2 ^ product1;
end
no_inline_function = 0;
for (i= 0; i < 31; i = i + 1 )
no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i];
end
endfunction
reg [31:0] outp;
reg [31:0] inp_d;
always @( posedge clk ) begin
if( reset ) begin
outp <= 0;
end
else begin
inp_d <= inp;
outp <= no_inline_function(inp, inp_d);
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [31:0] inp = crc[31:0];
wire reset = (cyc < 5);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] outp; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.outp (outp[31:0]),
// Inputs
.reset (reset),
.clk (clk),
.inp (inp[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, outp};
// What checksum will we end up with
`define EXPECTED_SUM 64'ha7f0a34f9cf56ccb
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
outp,
// Inputs
reset, clk, inp
);
input reset;
input clk;
input [31:0] inp;
output [31:0] outp;
function [31:0] no_inline_function;
input [31:0] var1;
input [31:0] var2;
/*verilator no_inline_task*/
reg [31*2:0] product1 ;
reg [31*2:0] product2 ;
integer i;
reg [31:0] tmp;
begin
product2 = {(31*2+1){1'b0}};
for (i = 0; i < 32; i = i + 1)
if (var2[i]) begin
product1 = { {31*2+1-32{1'b0}}, var1} << i;
product2 = product2 ^ product1;
end
no_inline_function = 0;
for (i= 0; i < 31; i = i + 1 )
no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i];
end
endfunction
reg [31:0] outp;
reg [31:0] inp_d;
always @( posedge clk ) begin
if( reset ) begin
outp <= 0;
end
else begin
inp_d <= inp;
outp <= no_inline_function(inp, inp_d);
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_cntl_rx_fifo # (
parameter P_FIFO_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
output almost_full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg r_almost_full_n;
wire w_almost_full_n;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_front_addr;
assign full_n = ~(( r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign almost_full_n = r_almost_full_n;
assign w_invalid_front_addr = {~r_front_addr[P_FIFO_DEPTH_WIDTH], r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]};
assign w_invalid_space = w_invalid_front_addr - r_rear_addr;
assign w_almost_full_n = (w_invalid_space > 8);
always @(posedge clk)
begin
r_almost_full_n <= w_almost_full_n;
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (rd_data[P_FIFO_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_FIFO_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire out;
reg in;
Genit g (.clk(clk), .value(in), .result(out));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, in, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 1'b1;
end
else if (cyc==1) begin
in <= 1'b0;
end
else if (cyc==2) begin
if (out != 1'b1) $stop;
end
else if (cyc==3) begin
if (out != 1'b0) $stop;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile("obj_dir/t_gen_intdot/t_gen_intdot.vcd");
$dumpvars(12, t);
end
`endif
endmodule
module Generate (clk, value, result);
input clk;
input value;
output result;
reg Internal;
assign result = Internal ^ clk;
always @(posedge clk)
Internal <= #1 value;
endmodule
module Checker (clk, value);
input clk, value;
always @(posedge clk) begin
$write ("[%0t] value=%h\n", $time, value);
end
endmodule
module Test (clk, value, result);
input clk;
input value;
output result;
Generate gen (clk, value, result);
Checker chk (clk, gen.Internal);
endmodule
module Genit (clk, value, result);
input clk;
input value;
output result;
`ifndef ATSIM // else unsupported
`ifndef NC // else unsupported
`define WITH_FOR_GENVAR
`endif
`endif
`define WITH_GENERATE
`ifdef WITH_GENERATE
`ifndef WITH_FOR_GENVAR
genvar i;
`endif
generate
for (
`ifdef WITH_FOR_GENVAR
genvar
`endif
i = 0; i < 1; i = i + 1)
begin : foo
Test tt (clk, value, result);
end
endgenerate
`else
Test tt (clk, value, result);
`endif
wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change!
always @ (posedge clk) begin
$write("[%0t] Result2 = %x\n", $time, Result2);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
wire out;
reg in;
Genit g (.clk(clk), .value(in), .result(out));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, in, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 1'b1;
end
else if (cyc==1) begin
in <= 1'b0;
end
else if (cyc==2) begin
if (out != 1'b1) $stop;
end
else if (cyc==3) begin
if (out != 1'b0) $stop;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile("obj_dir/t_gen_intdot/t_gen_intdot.vcd");
$dumpvars(12, t);
end
`endif
endmodule
module Generate (clk, value, result);
input clk;
input value;
output result;
reg Internal;
assign result = Internal ^ clk;
always @(posedge clk)
Internal <= #1 value;
endmodule
module Checker (clk, value);
input clk, value;
always @(posedge clk) begin
$write ("[%0t] value=%h\n", $time, value);
end
endmodule
module Test (clk, value, result);
input clk;
input value;
output result;
Generate gen (clk, value, result);
Checker chk (clk, gen.Internal);
endmodule
module Genit (clk, value, result);
input clk;
input value;
output result;
`ifndef ATSIM // else unsupported
`ifndef NC // else unsupported
`define WITH_FOR_GENVAR
`endif
`endif
`define WITH_GENERATE
`ifdef WITH_GENERATE
`ifndef WITH_FOR_GENVAR
genvar i;
`endif
generate
for (
`ifdef WITH_FOR_GENVAR
genvar
`endif
i = 0; i < 1; i = i + 1)
begin : foo
Test tt (clk, value, result);
end
endgenerate
`else
Test tt (clk, value, result);
`endif
wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change!
always @ (posedge clk) begin
$write("[%0t] Result2 = %x\n", $time, Result2);
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_nvme.vh"
module pcie_cntl_reg # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output rx_np_ok,
output rx_np_req,
output mreq_fifo_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_rd_data,
input mreq_fifo_empty_n,
output tx_cpld_req,
output [7:0] tx_cpld_tag,
output [15:0] tx_cpld_req_id,
output [11:2] tx_cpld_len,
output [11:0] tx_cpld_bc,
output [6:0] tx_cpld_laddr,
output [63:0] tx_cpld_data,
input tx_cpld_req_ack,
output nvme_cc_en,
output [1:0] nvme_cc_shn,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
output nvme_intms_ivms,
output nvme_intmc_ivmc,
input cq_irq_status,
input [8:0] sq_rst_n,
input [8:0] cq_rst_n,
output [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
output [7:0] admin_sq_size,
output [7:0] admin_cq_size,
output [7:0] admin_sq_tail_ptr,
output [7:0] io_sq1_tail_ptr,
output [7:0] io_sq2_tail_ptr,
output [7:0] io_sq3_tail_ptr,
output [7:0] io_sq4_tail_ptr,
output [7:0] io_sq5_tail_ptr,
output [7:0] io_sq6_tail_ptr,
output [7:0] io_sq7_tail_ptr,
output [7:0] io_sq8_tail_ptr,
output [7:0] admin_cq_head_ptr,
output [7:0] io_cq1_head_ptr,
output [7:0] io_cq2_head_ptr,
output [7:0] io_cq3_head_ptr,
output [7:0] io_cq4_head_ptr,
output [7:0] io_cq5_head_ptr,
output [7:0] io_cq6_head_ptr,
output [7:0] io_cq7_head_ptr,
output [7:0] io_cq8_head_ptr,
output [8:0] cq_head_update
);
localparam S_IDLE = 9'b000000001;
localparam S_PCIE_RD_HEAD = 9'b000000010;
localparam S_PCIE_ADDR = 9'b000000100;
localparam S_PCIE_WAIT_WR_DATA = 9'b000001000;
localparam S_PCIE_WR_DATA = 9'b000010000;
localparam S_PCIE_MWR = 9'b000100000;
localparam S_PCIE_MRD = 9'b001000000;
localparam S_PCIE_CPLD_REQ = 9'b010000000;
localparam S_PCIE_CPLD_ACK = 9'b100000000;
reg [8:0] cur_state;
reg [8:0] next_state;
reg r_intms_ivms;
reg r_intmc_ivmc;
reg r_cq_irq_status;
reg [23:20] r_cc_iocqes;
reg [19:16] r_cc_iosqes;
reg [15:14] r_cc_shn;
reg [13:11] r_cc_asm;
reg [10:7] r_cc_mps;
reg [6:4] r_cc_ccs;
reg [0:0] r_cc_en;
reg [23:16] r_aqa_acqs;
reg [7:0] r_aqa_asqs;
reg [C_PCIE_ADDR_WIDTH-1:2] r_asq_asqb;
reg [C_PCIE_ADDR_WIDTH-1:2] r_acq_acqb;
reg [7:0] r_reg_sq0tdbl;
reg [7:0] r_reg_sq1tdbl;
reg [7:0] r_reg_sq2tdbl;
reg [7:0] r_reg_sq3tdbl;
reg [7:0] r_reg_sq4tdbl;
reg [7:0] r_reg_sq5tdbl;
reg [7:0] r_reg_sq6tdbl;
reg [7:0] r_reg_sq7tdbl;
reg [7:0] r_reg_sq8tdbl;
reg [7:0] r_reg_cq0hdbl;
reg [7:0] r_reg_cq1hdbl;
reg [7:0] r_reg_cq2hdbl;
reg [7:0] r_reg_cq3hdbl;
reg [7:0] r_reg_cq4hdbl;
reg [7:0] r_reg_cq5hdbl;
reg [7:0] r_reg_cq6hdbl;
reg [7:0] r_reg_cq7hdbl;
reg [7:0] r_reg_cq8hdbl;
reg [8:0] r_cq_head_update;
wire [31:0] w_pcie_head0;
wire [31:0] w_pcie_head1;
wire [31:0] w_pcie_head2;
wire [31:0] w_pcie_head3;
reg [31:0] r_pcie_head2;
reg [31:0] r_pcie_head3;
wire [2:0] w_mreq_head_fmt;
//wire [4:0] w_mreq_head_type;
//wire [2:0] w_mreq_head_tc;
//wire w_mreq_head_attr1;
//wire w_mreq_head_th;
//wire w_mreq_head_td;
//wire w_mreq_head_ep;
//wire [1:0] w_mreq_head_attr0;
//wire [1:0] w_mreq_head_at;
wire [9:0] w_mreq_head_len;
wire [7:0] w_mreq_head_req_bus_num;
wire [4:0] w_mreq_head_req_dev_num;
wire [2:0] w_mreq_head_req_func_num;
wire [15:0] w_mreq_head_req_id;
wire [7:0] w_mreq_head_tag;
wire [3:0] w_mreq_head_last_be;
wire [3:0] w_mreq_head_1st_be;
//reg [4:0] r_rx_np_req_cnt;
//reg r_rx_np_req;
wire w_mwr;
wire w_4dw;
reg [2:0] r_mreq_head_fmt;
reg [9:0] r_mreq_head_len;
reg [15:0] r_mreq_head_req_id;
reg [7:0] r_mreq_head_tag;
reg [3:0] r_mreq_head_last_be;
reg [3:0] r_mreq_head_1st_be;
reg [12:0] r_mreq_addr;
reg [63:0] r_mreq_data;
reg [3:0] r_cpld_bc;
reg r_lbytes_en;
reg r_hbytes_en;
reg r_wr_reg;
reg r_wr_doorbell;
reg r_tx_cpld_req;
reg [63:0] r_rd_data;
reg [63:0] r_rd_reg;
reg [63:0] r_rd_doorbell;
reg r_mreq_fifo_rd_en;
wire [8:0] w_sq_rst_n;
wire [8:0] w_cq_rst_n;
//pcie mrd or mwr, memory rd/wr request
assign w_pcie_head0 = mreq_fifo_rd_data[31:0];
assign w_pcie_head1 = mreq_fifo_rd_data[63:32];
assign w_pcie_head2 = mreq_fifo_rd_data[95:64];
assign w_pcie_head3 = mreq_fifo_rd_data[127:96];
assign w_mreq_head_fmt = w_pcie_head0[31:29];
//assign w_mreq_head_type = w_pcie_head0[28:24];
//assign w_mreq_head_tc = w_pcie_head0[22:20];
//assign w_mreq_head_attr1 = w_pcie_head0[18];
//assign w_mreq_head_th = w_pcie_head0[16];
//assign w_mreq_head_td = w_pcie_head0[15];
//assign w_mreq_head_ep = w_pcie_head0[14];
//assign w_mreq_head_attr0 = w_pcie_head0[13:12];
//assign w_mreq_head_at = w_pcie_head0[11:10];
assign w_mreq_head_len = w_pcie_head0[9:0];
assign w_mreq_head_req_bus_num = w_pcie_head1[31:24];
assign w_mreq_head_req_dev_num = w_pcie_head1[23:19];
assign w_mreq_head_req_func_num = w_pcie_head1[18:16];
assign w_mreq_head_req_id = {w_mreq_head_req_bus_num, w_mreq_head_req_dev_num, w_mreq_head_req_func_num};
assign w_mreq_head_tag = w_pcie_head1[15:8];
assign w_mreq_head_last_be = w_pcie_head1[7:4];
assign w_mreq_head_1st_be = w_pcie_head1[3:0];
assign w_mwr = r_mreq_head_fmt[1];
assign w_4dw = r_mreq_head_fmt[0];
assign tx_cpld_req = r_tx_cpld_req;
assign tx_cpld_tag = r_mreq_head_tag;
assign tx_cpld_req_id = r_mreq_head_req_id;
assign tx_cpld_len = {8'b0, r_mreq_head_len[1:0]};
assign tx_cpld_bc = {8'b0, r_cpld_bc};
assign tx_cpld_laddr = r_mreq_addr[6:0];
assign tx_cpld_data = (r_mreq_addr[2] == 1) ? {32'b0, r_rd_data[63:32]} : r_rd_data;
assign rx_np_ok = 1'b1;
assign rx_np_req = 1'b1;
assign mreq_fifo_rd_en = r_mreq_fifo_rd_en;
assign admin_sq_bs_addr = r_asq_asqb;
assign admin_cq_bs_addr = r_acq_acqb;
assign nvme_cc_en = r_cc_en;
assign nvme_cc_shn = r_cc_shn;
assign nvme_intms_ivms = r_intms_ivms;
assign nvme_intmc_ivmc = r_intmc_ivmc;
assign admin_sq_size = r_aqa_asqs;
assign admin_cq_size = r_aqa_acqs;
assign admin_sq_tail_ptr = r_reg_sq0tdbl;
assign io_sq1_tail_ptr = r_reg_sq1tdbl;
assign io_sq2_tail_ptr = r_reg_sq2tdbl;
assign io_sq3_tail_ptr = r_reg_sq3tdbl;
assign io_sq4_tail_ptr = r_reg_sq4tdbl;
assign io_sq5_tail_ptr = r_reg_sq5tdbl;
assign io_sq6_tail_ptr = r_reg_sq6tdbl;
assign io_sq7_tail_ptr = r_reg_sq7tdbl;
assign io_sq8_tail_ptr = r_reg_sq8tdbl;
assign admin_cq_head_ptr = r_reg_cq0hdbl;
assign io_cq1_head_ptr = r_reg_cq1hdbl;
assign io_cq2_head_ptr = r_reg_cq2hdbl;
assign io_cq3_head_ptr = r_reg_cq3hdbl;
assign io_cq4_head_ptr = r_reg_cq4hdbl;
assign io_cq5_head_ptr = r_reg_cq5hdbl;
assign io_cq6_head_ptr = r_reg_cq6hdbl;
assign io_cq7_head_ptr = r_reg_cq7hdbl;
assign io_cq8_head_ptr = r_reg_cq8hdbl;
assign cq_head_update = r_cq_head_update;
always @ (posedge pcie_user_clk)
begin
r_cq_irq_status <= cq_irq_status;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(mreq_fifo_empty_n == 1)
next_state <= S_PCIE_RD_HEAD;
else
next_state <= S_IDLE;
end
S_PCIE_RD_HEAD: begin
next_state <= S_PCIE_ADDR;
end
S_PCIE_ADDR: begin
if(w_mwr == 1) begin
if(w_4dw == 1 || r_mreq_head_len[1] == 1) begin
if(mreq_fifo_empty_n == 1)
next_state <= S_PCIE_WR_DATA;
else
next_state <= S_PCIE_WAIT_WR_DATA;
end
else
next_state <= S_PCIE_MWR;
end
else begin
next_state <= S_PCIE_MRD;
end
end
S_PCIE_WAIT_WR_DATA: begin
if(mreq_fifo_empty_n == 1)
next_state <= S_PCIE_WR_DATA;
else
next_state <= S_PCIE_WAIT_WR_DATA;
end
S_PCIE_WR_DATA: begin
next_state <= S_PCIE_MWR;
end
S_PCIE_MWR: begin
next_state <= S_IDLE;
end
S_PCIE_MRD: begin
next_state <= S_PCIE_CPLD_REQ;
end
S_PCIE_CPLD_REQ: begin
next_state <= S_PCIE_CPLD_ACK;
end
S_PCIE_CPLD_ACK: begin
if(tx_cpld_req_ack == 1)
next_state <= S_IDLE;
else
next_state <= S_PCIE_CPLD_ACK;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_PCIE_RD_HEAD: begin
r_mreq_head_fmt <= w_mreq_head_fmt;
r_mreq_head_len <= w_mreq_head_len;
r_mreq_head_req_id <= w_mreq_head_req_id;
r_mreq_head_tag <= w_mreq_head_tag;
r_mreq_head_last_be <= w_mreq_head_last_be;
r_mreq_head_1st_be <= w_mreq_head_1st_be;
r_pcie_head2 <= w_pcie_head2;
r_pcie_head3 <= w_pcie_head3;
end
S_PCIE_ADDR: begin
if(w_4dw == 1) begin
r_mreq_addr[12:2] <= r_pcie_head3[12:2];
r_lbytes_en <= ~r_pcie_head3[2] & (r_pcie_head3[11:7] == 0);
r_hbytes_en <= (r_pcie_head3[2] | r_mreq_head_len[1]) & (r_pcie_head3[11:7] == 0);
end
else begin
r_mreq_addr[12:2] <= r_pcie_head2[12:2];
r_lbytes_en <= ~r_pcie_head2[2] & (r_pcie_head2[11:7] == 0);;
r_hbytes_en <= (r_pcie_head2[2] | r_mreq_head_len[1]) & (r_pcie_head2[11:7] == 0);
if(r_pcie_head2[2] == 1)
r_mreq_data[63:32] <= {r_pcie_head3[7:0], r_pcie_head3[15:8], r_pcie_head3[23:16], r_pcie_head3[31:24]};
else
r_mreq_data[31:0] <= {r_pcie_head3[7:0], r_pcie_head3[15:8], r_pcie_head3[23:16], r_pcie_head3[31:24]};
end
end
S_PCIE_WAIT_WR_DATA: begin
end
S_PCIE_WR_DATA: begin
if(w_4dw == 1) begin
if(r_mreq_addr[2] == 1)
r_mreq_data[63:32] <= {mreq_fifo_rd_data[7:0], mreq_fifo_rd_data[15:8], mreq_fifo_rd_data[23:16], mreq_fifo_rd_data[31:24]};
else begin
r_mreq_data[31:0] <= {mreq_fifo_rd_data[7:0], mreq_fifo_rd_data[15:8], mreq_fifo_rd_data[23:16], mreq_fifo_rd_data[31:24]};
r_mreq_data[63:32] <= {mreq_fifo_rd_data[39:32], mreq_fifo_rd_data[47:40], mreq_fifo_rd_data[55:48], mreq_fifo_rd_data[63:56]};
end
end
else
r_mreq_data[63:32] <= {mreq_fifo_rd_data[7:0], mreq_fifo_rd_data[15:8], mreq_fifo_rd_data[23:16], mreq_fifo_rd_data[31:24]};
end
S_PCIE_MWR: begin
end
S_PCIE_MRD: begin
if(r_lbytes_en | r_hbytes_en) begin
if(r_mreq_addr[12] == 1) begin
r_rd_data[31:0] <= {r_rd_doorbell[7:0], r_rd_doorbell[15:8], r_rd_doorbell[23:16], r_rd_doorbell[31:24]};
r_rd_data[63:32] <= {r_rd_doorbell[39:32], r_rd_doorbell[47:40], r_rd_doorbell[55:48], r_rd_doorbell[63:56]};
end
else begin
r_rd_data[31:0] <= {r_rd_reg[7:0], r_rd_reg[15:8], r_rd_reg[23:16], r_rd_reg[31:24]};
r_rd_data[63:32] <= {r_rd_reg[39:32], r_rd_reg[47:40], r_rd_reg[55:48], r_rd_reg[63:56]};
end
end
else
r_rd_data <= 64'b0;
if(r_mreq_head_1st_be[0] == 1)
r_mreq_addr[1:0] <= 2'b00;
else if(r_mreq_head_1st_be[1] == 1)
r_mreq_addr[1:0] <= 2'b01;
else if(r_mreq_head_1st_be[2] == 1)
r_mreq_addr[1:0] <= 2'b10;
else
r_mreq_addr[1:0] <= 2'b11;
r_cpld_bc <= ((r_mreq_head_1st_be[0] + r_mreq_head_1st_be[1])
+ (r_mreq_head_1st_be[2] + r_mreq_head_1st_be[3]))
+ ((r_mreq_head_last_be[0] + r_mreq_head_last_be[1])
+ (r_mreq_head_last_be[2] + r_mreq_head_last_be[3]));
end
S_PCIE_CPLD_REQ: begin
end
S_PCIE_CPLD_ACK: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_RD_HEAD: begin
r_mreq_fifo_rd_en <= 1;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_ADDR: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_WAIT_WR_DATA: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_WR_DATA: begin
r_mreq_fifo_rd_en <= 1;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_MWR: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= ~r_mreq_addr[12];
r_wr_doorbell <= r_mreq_addr[12];
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_MRD: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_CPLD_REQ: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 1;
//r_rx_np_req <= 1;
end
S_PCIE_CPLD_ACK: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
default: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_intms_ivms <= 0;
r_intmc_ivmc <= 0;
{r_cc_iocqes, r_cc_iosqes, r_cc_shn, r_cc_asm, r_cc_mps, r_cc_ccs, r_cc_en} <= 0;
{r_aqa_acqs, r_aqa_asqs} <= 0;
r_asq_asqb <= 0;
r_acq_acqb <= 0;
end
else begin
if(r_wr_reg == 1) begin
if(r_lbytes_en == 1) begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h5: r_asq_asqb[31:2] <= r_mreq_data[31:2];
4'h6: r_acq_acqb[31:2] <= r_mreq_data[31:2];
endcase
if(r_mreq_addr[6:3] == 4'h1)
r_intmc_ivmc <= r_mreq_data[0];
else
r_intmc_ivmc <= 0;
end
if(r_hbytes_en == 1) begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h2: {r_cc_iocqes, r_cc_iosqes, r_cc_shn, r_cc_asm, r_cc_mps, r_cc_ccs, r_cc_en}
<= {r_mreq_data[55:52], r_mreq_data[51:48], r_mreq_data[47:46], r_mreq_data[45:43], r_mreq_data[42:39], r_mreq_data[38:36], r_mreq_data[32]};
4'h4: {r_aqa_acqs, r_aqa_asqs} <= {r_mreq_data[55:48], r_mreq_data[39:32]};
4'h5: r_asq_asqb[C_PCIE_ADDR_WIDTH-1:32] <= r_mreq_data[C_PCIE_ADDR_WIDTH-1:32];
4'h6: r_acq_acqb[C_PCIE_ADDR_WIDTH-1:32] <= r_mreq_data[C_PCIE_ADDR_WIDTH-1:32];
endcase
if(r_mreq_addr[6:3] == 4'h1)
r_intms_ivms <= r_mreq_data[32];
else
r_intms_ivms <= 0;
end
end
else begin
r_intms_ivms <= 0;
r_intmc_ivmc <= 0;
end
end
end
assign w_sq_rst_n[0] = pcie_user_rst_n & sq_rst_n[0];
assign w_sq_rst_n[1] = pcie_user_rst_n & sq_rst_n[1];
assign w_sq_rst_n[2] = pcie_user_rst_n & sq_rst_n[2];
assign w_sq_rst_n[3] = pcie_user_rst_n & sq_rst_n[3];
assign w_sq_rst_n[4] = pcie_user_rst_n & sq_rst_n[4];
assign w_sq_rst_n[5] = pcie_user_rst_n & sq_rst_n[5];
assign w_sq_rst_n[6] = pcie_user_rst_n & sq_rst_n[6];
assign w_sq_rst_n[7] = pcie_user_rst_n & sq_rst_n[7];
assign w_sq_rst_n[8] = pcie_user_rst_n & sq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[0])
begin
if(w_sq_rst_n[0] == 0) begin
r_reg_sq0tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h0)) == 1)
r_reg_sq0tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[1])
begin
if(w_sq_rst_n[1] == 0) begin
r_reg_sq1tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h1)) == 1)
r_reg_sq1tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[2])
begin
if(w_sq_rst_n[2] == 0) begin
r_reg_sq2tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h2)) == 1)
r_reg_sq2tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[3])
begin
if(w_sq_rst_n[3] == 0) begin
r_reg_sq3tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h3)) == 1)
r_reg_sq3tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[4])
begin
if(w_sq_rst_n[4] == 0) begin
r_reg_sq4tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h4)) == 1)
r_reg_sq4tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[5])
begin
if(w_sq_rst_n[5] == 0) begin
r_reg_sq5tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h5)) == 1)
r_reg_sq5tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[6])
begin
if(w_sq_rst_n[6] == 0) begin
r_reg_sq6tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h6)) == 1)
r_reg_sq6tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[7])
begin
if(w_sq_rst_n[7] == 0) begin
r_reg_sq7tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h7)) == 1)
r_reg_sq7tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[8])
begin
if(w_sq_rst_n[8] == 0) begin
r_reg_sq8tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h8)) == 1)
r_reg_sq8tdbl <= r_mreq_data[7:0];
end
end
assign w_cq_rst_n[0] = pcie_user_rst_n & cq_rst_n[0];
assign w_cq_rst_n[1] = pcie_user_rst_n & cq_rst_n[1];
assign w_cq_rst_n[2] = pcie_user_rst_n & cq_rst_n[2];
assign w_cq_rst_n[3] = pcie_user_rst_n & cq_rst_n[3];
assign w_cq_rst_n[4] = pcie_user_rst_n & cq_rst_n[4];
assign w_cq_rst_n[5] = pcie_user_rst_n & cq_rst_n[5];
assign w_cq_rst_n[6] = pcie_user_rst_n & cq_rst_n[6];
assign w_cq_rst_n[7] = pcie_user_rst_n & cq_rst_n[7];
assign w_cq_rst_n[8] = pcie_user_rst_n & cq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[0])
begin
if(w_cq_rst_n[0] == 0) begin
r_reg_cq0hdbl <= 0;
r_cq_head_update[0] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h0)) == 1) begin
r_reg_cq0hdbl <= r_mreq_data[39:32];
r_cq_head_update[0] <= 1;
end
else
r_cq_head_update[0] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[1])
begin
if(w_cq_rst_n[1] == 0) begin
r_reg_cq1hdbl <= 0;
r_cq_head_update[1] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h1)) == 1) begin
r_reg_cq1hdbl <= r_mreq_data[39:32];
r_cq_head_update[1] <= 1;
end
else
r_cq_head_update[1] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[2])
begin
if(w_cq_rst_n[2] == 0) begin
r_reg_cq2hdbl <= 0;
r_cq_head_update[2] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h2)) == 1) begin
r_reg_cq2hdbl <= r_mreq_data[39:32];
r_cq_head_update[2] <= 1;
end
else
r_cq_head_update[2] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[3])
begin
if(w_cq_rst_n[3] == 0) begin
r_reg_cq3hdbl <= 0;
r_cq_head_update[3] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h3)) == 1) begin
r_reg_cq3hdbl <= r_mreq_data[39:32];
r_cq_head_update[3] <= 1;
end
else
r_cq_head_update[3] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[4])
begin
if(w_cq_rst_n[4] == 0) begin
r_reg_cq4hdbl <= 0;
r_cq_head_update[4] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h4)) == 1) begin
r_reg_cq4hdbl <= r_mreq_data[39:32];
r_cq_head_update[4] <= 1;
end
else
r_cq_head_update[4] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[5])
begin
if(w_cq_rst_n[5] == 0) begin
r_reg_cq5hdbl <= 0;
r_cq_head_update[5] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h5)) == 1) begin
r_reg_cq5hdbl <= r_mreq_data[39:32];
r_cq_head_update[5] <= 1;
end
else
r_cq_head_update[5] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[6])
begin
if(w_cq_rst_n[6] == 0) begin
r_reg_cq6hdbl <= 0;
r_cq_head_update[6] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h6)) == 1) begin
r_reg_cq6hdbl <= r_mreq_data[39:32];
r_cq_head_update[6] <= 1;
end
else
r_cq_head_update[6] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[7])
begin
if(w_cq_rst_n[7] == 0) begin
r_reg_cq7hdbl <= 0;
r_cq_head_update[7] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h7)) == 1) begin
r_reg_cq7hdbl <= r_mreq_data[39:32];
r_cq_head_update[7] <= 1;
end
else
r_cq_head_update[7] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[8])
begin
if(w_cq_rst_n[8] == 0) begin
r_reg_cq8hdbl <= 0;
r_cq_head_update[8] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h8)) == 1) begin
r_reg_cq8hdbl <= r_mreq_data[39:32];
r_cq_head_update[8] <= 1;
end
else
r_cq_head_update[8] <= 0;
end
end
always @ (*)
begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h0: r_rd_reg <= {8'h0, `D_CAP_MPSMAX, `D_CAP_MPSMIN, 3'h0, `D_CAP_CSS, `D_CAP_NSSRS, `D_CAP_DSTRD, `D_CAP_TO, 5'h0, `D_CAP_AMS, `D_CAP_CQR, `D_CAP_MQES};
4'h1: r_rd_reg <= {31'b0, r_cq_irq_status, `D_VS_MJR, `D_VS_MNR, 8'b0};
4'h2: r_rd_reg <= {8'b0, r_cc_iocqes, r_cc_iosqes, r_cc_shn, r_cc_asm, r_cc_mps, r_cc_ccs, 3'b0, r_cc_en, 31'b0, r_cq_irq_status};
4'h3: r_rd_reg <= {28'b0, nvme_csts_shst, 1'b0, nvme_csts_rdy, 32'b0};
4'h4: r_rd_reg <= {8'b0, r_aqa_acqs, 8'b0, r_aqa_asqs, 32'b0};
4'h5: r_rd_reg <= {26'b0, r_asq_asqb, 2'b0};
4'h6: r_rd_reg <= {26'b0, r_acq_acqb, 2'b0};
default: r_rd_reg <= 64'b0;
endcase
end
always @ (*)
begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h0: r_rd_doorbell <= {24'b0, r_reg_cq0hdbl, 24'b0, r_reg_sq0tdbl};
4'h1: r_rd_doorbell <= {24'b0, r_reg_cq1hdbl, 24'b0, r_reg_sq1tdbl};
4'h2: r_rd_doorbell <= {24'b0, r_reg_cq2hdbl, 24'b0, r_reg_sq2tdbl};
4'h3: r_rd_doorbell <= {24'b0, r_reg_cq3hdbl, 24'b0, r_reg_sq3tdbl};
4'h4: r_rd_doorbell <= {24'b0, r_reg_cq4hdbl, 24'b0, r_reg_sq4tdbl};
4'h5: r_rd_doorbell <= {24'b0, r_reg_cq5hdbl, 24'b0, r_reg_sq5tdbl};
4'h6: r_rd_doorbell <= {24'b0, r_reg_cq6hdbl, 24'b0, r_reg_sq6tdbl};
4'h7: r_rd_doorbell <= {24'b0, r_reg_cq7hdbl, 24'b0, r_reg_sq7tdbl};
4'h8: r_rd_doorbell <= {24'b0, r_reg_cq8hdbl, 24'b0, r_reg_sq8tdbl};
default: r_rd_doorbell <= 64'b0;
endcase
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_nvme.vh"
module pcie_cntl_reg # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output rx_np_ok,
output rx_np_req,
output mreq_fifo_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_rd_data,
input mreq_fifo_empty_n,
output tx_cpld_req,
output [7:0] tx_cpld_tag,
output [15:0] tx_cpld_req_id,
output [11:2] tx_cpld_len,
output [11:0] tx_cpld_bc,
output [6:0] tx_cpld_laddr,
output [63:0] tx_cpld_data,
input tx_cpld_req_ack,
output nvme_cc_en,
output [1:0] nvme_cc_shn,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
output nvme_intms_ivms,
output nvme_intmc_ivmc,
input cq_irq_status,
input [8:0] sq_rst_n,
input [8:0] cq_rst_n,
output [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
output [7:0] admin_sq_size,
output [7:0] admin_cq_size,
output [7:0] admin_sq_tail_ptr,
output [7:0] io_sq1_tail_ptr,
output [7:0] io_sq2_tail_ptr,
output [7:0] io_sq3_tail_ptr,
output [7:0] io_sq4_tail_ptr,
output [7:0] io_sq5_tail_ptr,
output [7:0] io_sq6_tail_ptr,
output [7:0] io_sq7_tail_ptr,
output [7:0] io_sq8_tail_ptr,
output [7:0] admin_cq_head_ptr,
output [7:0] io_cq1_head_ptr,
output [7:0] io_cq2_head_ptr,
output [7:0] io_cq3_head_ptr,
output [7:0] io_cq4_head_ptr,
output [7:0] io_cq5_head_ptr,
output [7:0] io_cq6_head_ptr,
output [7:0] io_cq7_head_ptr,
output [7:0] io_cq8_head_ptr,
output [8:0] cq_head_update
);
localparam S_IDLE = 9'b000000001;
localparam S_PCIE_RD_HEAD = 9'b000000010;
localparam S_PCIE_ADDR = 9'b000000100;
localparam S_PCIE_WAIT_WR_DATA = 9'b000001000;
localparam S_PCIE_WR_DATA = 9'b000010000;
localparam S_PCIE_MWR = 9'b000100000;
localparam S_PCIE_MRD = 9'b001000000;
localparam S_PCIE_CPLD_REQ = 9'b010000000;
localparam S_PCIE_CPLD_ACK = 9'b100000000;
reg [8:0] cur_state;
reg [8:0] next_state;
reg r_intms_ivms;
reg r_intmc_ivmc;
reg r_cq_irq_status;
reg [23:20] r_cc_iocqes;
reg [19:16] r_cc_iosqes;
reg [15:14] r_cc_shn;
reg [13:11] r_cc_asm;
reg [10:7] r_cc_mps;
reg [6:4] r_cc_ccs;
reg [0:0] r_cc_en;
reg [23:16] r_aqa_acqs;
reg [7:0] r_aqa_asqs;
reg [C_PCIE_ADDR_WIDTH-1:2] r_asq_asqb;
reg [C_PCIE_ADDR_WIDTH-1:2] r_acq_acqb;
reg [7:0] r_reg_sq0tdbl;
reg [7:0] r_reg_sq1tdbl;
reg [7:0] r_reg_sq2tdbl;
reg [7:0] r_reg_sq3tdbl;
reg [7:0] r_reg_sq4tdbl;
reg [7:0] r_reg_sq5tdbl;
reg [7:0] r_reg_sq6tdbl;
reg [7:0] r_reg_sq7tdbl;
reg [7:0] r_reg_sq8tdbl;
reg [7:0] r_reg_cq0hdbl;
reg [7:0] r_reg_cq1hdbl;
reg [7:0] r_reg_cq2hdbl;
reg [7:0] r_reg_cq3hdbl;
reg [7:0] r_reg_cq4hdbl;
reg [7:0] r_reg_cq5hdbl;
reg [7:0] r_reg_cq6hdbl;
reg [7:0] r_reg_cq7hdbl;
reg [7:0] r_reg_cq8hdbl;
reg [8:0] r_cq_head_update;
wire [31:0] w_pcie_head0;
wire [31:0] w_pcie_head1;
wire [31:0] w_pcie_head2;
wire [31:0] w_pcie_head3;
reg [31:0] r_pcie_head2;
reg [31:0] r_pcie_head3;
wire [2:0] w_mreq_head_fmt;
//wire [4:0] w_mreq_head_type;
//wire [2:0] w_mreq_head_tc;
//wire w_mreq_head_attr1;
//wire w_mreq_head_th;
//wire w_mreq_head_td;
//wire w_mreq_head_ep;
//wire [1:0] w_mreq_head_attr0;
//wire [1:0] w_mreq_head_at;
wire [9:0] w_mreq_head_len;
wire [7:0] w_mreq_head_req_bus_num;
wire [4:0] w_mreq_head_req_dev_num;
wire [2:0] w_mreq_head_req_func_num;
wire [15:0] w_mreq_head_req_id;
wire [7:0] w_mreq_head_tag;
wire [3:0] w_mreq_head_last_be;
wire [3:0] w_mreq_head_1st_be;
//reg [4:0] r_rx_np_req_cnt;
//reg r_rx_np_req;
wire w_mwr;
wire w_4dw;
reg [2:0] r_mreq_head_fmt;
reg [9:0] r_mreq_head_len;
reg [15:0] r_mreq_head_req_id;
reg [7:0] r_mreq_head_tag;
reg [3:0] r_mreq_head_last_be;
reg [3:0] r_mreq_head_1st_be;
reg [12:0] r_mreq_addr;
reg [63:0] r_mreq_data;
reg [3:0] r_cpld_bc;
reg r_lbytes_en;
reg r_hbytes_en;
reg r_wr_reg;
reg r_wr_doorbell;
reg r_tx_cpld_req;
reg [63:0] r_rd_data;
reg [63:0] r_rd_reg;
reg [63:0] r_rd_doorbell;
reg r_mreq_fifo_rd_en;
wire [8:0] w_sq_rst_n;
wire [8:0] w_cq_rst_n;
//pcie mrd or mwr, memory rd/wr request
assign w_pcie_head0 = mreq_fifo_rd_data[31:0];
assign w_pcie_head1 = mreq_fifo_rd_data[63:32];
assign w_pcie_head2 = mreq_fifo_rd_data[95:64];
assign w_pcie_head3 = mreq_fifo_rd_data[127:96];
assign w_mreq_head_fmt = w_pcie_head0[31:29];
//assign w_mreq_head_type = w_pcie_head0[28:24];
//assign w_mreq_head_tc = w_pcie_head0[22:20];
//assign w_mreq_head_attr1 = w_pcie_head0[18];
//assign w_mreq_head_th = w_pcie_head0[16];
//assign w_mreq_head_td = w_pcie_head0[15];
//assign w_mreq_head_ep = w_pcie_head0[14];
//assign w_mreq_head_attr0 = w_pcie_head0[13:12];
//assign w_mreq_head_at = w_pcie_head0[11:10];
assign w_mreq_head_len = w_pcie_head0[9:0];
assign w_mreq_head_req_bus_num = w_pcie_head1[31:24];
assign w_mreq_head_req_dev_num = w_pcie_head1[23:19];
assign w_mreq_head_req_func_num = w_pcie_head1[18:16];
assign w_mreq_head_req_id = {w_mreq_head_req_bus_num, w_mreq_head_req_dev_num, w_mreq_head_req_func_num};
assign w_mreq_head_tag = w_pcie_head1[15:8];
assign w_mreq_head_last_be = w_pcie_head1[7:4];
assign w_mreq_head_1st_be = w_pcie_head1[3:0];
assign w_mwr = r_mreq_head_fmt[1];
assign w_4dw = r_mreq_head_fmt[0];
assign tx_cpld_req = r_tx_cpld_req;
assign tx_cpld_tag = r_mreq_head_tag;
assign tx_cpld_req_id = r_mreq_head_req_id;
assign tx_cpld_len = {8'b0, r_mreq_head_len[1:0]};
assign tx_cpld_bc = {8'b0, r_cpld_bc};
assign tx_cpld_laddr = r_mreq_addr[6:0];
assign tx_cpld_data = (r_mreq_addr[2] == 1) ? {32'b0, r_rd_data[63:32]} : r_rd_data;
assign rx_np_ok = 1'b1;
assign rx_np_req = 1'b1;
assign mreq_fifo_rd_en = r_mreq_fifo_rd_en;
assign admin_sq_bs_addr = r_asq_asqb;
assign admin_cq_bs_addr = r_acq_acqb;
assign nvme_cc_en = r_cc_en;
assign nvme_cc_shn = r_cc_shn;
assign nvme_intms_ivms = r_intms_ivms;
assign nvme_intmc_ivmc = r_intmc_ivmc;
assign admin_sq_size = r_aqa_asqs;
assign admin_cq_size = r_aqa_acqs;
assign admin_sq_tail_ptr = r_reg_sq0tdbl;
assign io_sq1_tail_ptr = r_reg_sq1tdbl;
assign io_sq2_tail_ptr = r_reg_sq2tdbl;
assign io_sq3_tail_ptr = r_reg_sq3tdbl;
assign io_sq4_tail_ptr = r_reg_sq4tdbl;
assign io_sq5_tail_ptr = r_reg_sq5tdbl;
assign io_sq6_tail_ptr = r_reg_sq6tdbl;
assign io_sq7_tail_ptr = r_reg_sq7tdbl;
assign io_sq8_tail_ptr = r_reg_sq8tdbl;
assign admin_cq_head_ptr = r_reg_cq0hdbl;
assign io_cq1_head_ptr = r_reg_cq1hdbl;
assign io_cq2_head_ptr = r_reg_cq2hdbl;
assign io_cq3_head_ptr = r_reg_cq3hdbl;
assign io_cq4_head_ptr = r_reg_cq4hdbl;
assign io_cq5_head_ptr = r_reg_cq5hdbl;
assign io_cq6_head_ptr = r_reg_cq6hdbl;
assign io_cq7_head_ptr = r_reg_cq7hdbl;
assign io_cq8_head_ptr = r_reg_cq8hdbl;
assign cq_head_update = r_cq_head_update;
always @ (posedge pcie_user_clk)
begin
r_cq_irq_status <= cq_irq_status;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(mreq_fifo_empty_n == 1)
next_state <= S_PCIE_RD_HEAD;
else
next_state <= S_IDLE;
end
S_PCIE_RD_HEAD: begin
next_state <= S_PCIE_ADDR;
end
S_PCIE_ADDR: begin
if(w_mwr == 1) begin
if(w_4dw == 1 || r_mreq_head_len[1] == 1) begin
if(mreq_fifo_empty_n == 1)
next_state <= S_PCIE_WR_DATA;
else
next_state <= S_PCIE_WAIT_WR_DATA;
end
else
next_state <= S_PCIE_MWR;
end
else begin
next_state <= S_PCIE_MRD;
end
end
S_PCIE_WAIT_WR_DATA: begin
if(mreq_fifo_empty_n == 1)
next_state <= S_PCIE_WR_DATA;
else
next_state <= S_PCIE_WAIT_WR_DATA;
end
S_PCIE_WR_DATA: begin
next_state <= S_PCIE_MWR;
end
S_PCIE_MWR: begin
next_state <= S_IDLE;
end
S_PCIE_MRD: begin
next_state <= S_PCIE_CPLD_REQ;
end
S_PCIE_CPLD_REQ: begin
next_state <= S_PCIE_CPLD_ACK;
end
S_PCIE_CPLD_ACK: begin
if(tx_cpld_req_ack == 1)
next_state <= S_IDLE;
else
next_state <= S_PCIE_CPLD_ACK;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_PCIE_RD_HEAD: begin
r_mreq_head_fmt <= w_mreq_head_fmt;
r_mreq_head_len <= w_mreq_head_len;
r_mreq_head_req_id <= w_mreq_head_req_id;
r_mreq_head_tag <= w_mreq_head_tag;
r_mreq_head_last_be <= w_mreq_head_last_be;
r_mreq_head_1st_be <= w_mreq_head_1st_be;
r_pcie_head2 <= w_pcie_head2;
r_pcie_head3 <= w_pcie_head3;
end
S_PCIE_ADDR: begin
if(w_4dw == 1) begin
r_mreq_addr[12:2] <= r_pcie_head3[12:2];
r_lbytes_en <= ~r_pcie_head3[2] & (r_pcie_head3[11:7] == 0);
r_hbytes_en <= (r_pcie_head3[2] | r_mreq_head_len[1]) & (r_pcie_head3[11:7] == 0);
end
else begin
r_mreq_addr[12:2] <= r_pcie_head2[12:2];
r_lbytes_en <= ~r_pcie_head2[2] & (r_pcie_head2[11:7] == 0);;
r_hbytes_en <= (r_pcie_head2[2] | r_mreq_head_len[1]) & (r_pcie_head2[11:7] == 0);
if(r_pcie_head2[2] == 1)
r_mreq_data[63:32] <= {r_pcie_head3[7:0], r_pcie_head3[15:8], r_pcie_head3[23:16], r_pcie_head3[31:24]};
else
r_mreq_data[31:0] <= {r_pcie_head3[7:0], r_pcie_head3[15:8], r_pcie_head3[23:16], r_pcie_head3[31:24]};
end
end
S_PCIE_WAIT_WR_DATA: begin
end
S_PCIE_WR_DATA: begin
if(w_4dw == 1) begin
if(r_mreq_addr[2] == 1)
r_mreq_data[63:32] <= {mreq_fifo_rd_data[7:0], mreq_fifo_rd_data[15:8], mreq_fifo_rd_data[23:16], mreq_fifo_rd_data[31:24]};
else begin
r_mreq_data[31:0] <= {mreq_fifo_rd_data[7:0], mreq_fifo_rd_data[15:8], mreq_fifo_rd_data[23:16], mreq_fifo_rd_data[31:24]};
r_mreq_data[63:32] <= {mreq_fifo_rd_data[39:32], mreq_fifo_rd_data[47:40], mreq_fifo_rd_data[55:48], mreq_fifo_rd_data[63:56]};
end
end
else
r_mreq_data[63:32] <= {mreq_fifo_rd_data[7:0], mreq_fifo_rd_data[15:8], mreq_fifo_rd_data[23:16], mreq_fifo_rd_data[31:24]};
end
S_PCIE_MWR: begin
end
S_PCIE_MRD: begin
if(r_lbytes_en | r_hbytes_en) begin
if(r_mreq_addr[12] == 1) begin
r_rd_data[31:0] <= {r_rd_doorbell[7:0], r_rd_doorbell[15:8], r_rd_doorbell[23:16], r_rd_doorbell[31:24]};
r_rd_data[63:32] <= {r_rd_doorbell[39:32], r_rd_doorbell[47:40], r_rd_doorbell[55:48], r_rd_doorbell[63:56]};
end
else begin
r_rd_data[31:0] <= {r_rd_reg[7:0], r_rd_reg[15:8], r_rd_reg[23:16], r_rd_reg[31:24]};
r_rd_data[63:32] <= {r_rd_reg[39:32], r_rd_reg[47:40], r_rd_reg[55:48], r_rd_reg[63:56]};
end
end
else
r_rd_data <= 64'b0;
if(r_mreq_head_1st_be[0] == 1)
r_mreq_addr[1:0] <= 2'b00;
else if(r_mreq_head_1st_be[1] == 1)
r_mreq_addr[1:0] <= 2'b01;
else if(r_mreq_head_1st_be[2] == 1)
r_mreq_addr[1:0] <= 2'b10;
else
r_mreq_addr[1:0] <= 2'b11;
r_cpld_bc <= ((r_mreq_head_1st_be[0] + r_mreq_head_1st_be[1])
+ (r_mreq_head_1st_be[2] + r_mreq_head_1st_be[3]))
+ ((r_mreq_head_last_be[0] + r_mreq_head_last_be[1])
+ (r_mreq_head_last_be[2] + r_mreq_head_last_be[3]));
end
S_PCIE_CPLD_REQ: begin
end
S_PCIE_CPLD_ACK: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_RD_HEAD: begin
r_mreq_fifo_rd_en <= 1;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_ADDR: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_WAIT_WR_DATA: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_WR_DATA: begin
r_mreq_fifo_rd_en <= 1;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_MWR: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= ~r_mreq_addr[12];
r_wr_doorbell <= r_mreq_addr[12];
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_MRD: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
S_PCIE_CPLD_REQ: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 1;
//r_rx_np_req <= 1;
end
S_PCIE_CPLD_ACK: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
default: begin
r_mreq_fifo_rd_en <= 0;
r_wr_reg <= 0;
r_wr_doorbell <= 0;
r_tx_cpld_req <= 0;
//r_rx_np_req <= 0;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_intms_ivms <= 0;
r_intmc_ivmc <= 0;
{r_cc_iocqes, r_cc_iosqes, r_cc_shn, r_cc_asm, r_cc_mps, r_cc_ccs, r_cc_en} <= 0;
{r_aqa_acqs, r_aqa_asqs} <= 0;
r_asq_asqb <= 0;
r_acq_acqb <= 0;
end
else begin
if(r_wr_reg == 1) begin
if(r_lbytes_en == 1) begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h5: r_asq_asqb[31:2] <= r_mreq_data[31:2];
4'h6: r_acq_acqb[31:2] <= r_mreq_data[31:2];
endcase
if(r_mreq_addr[6:3] == 4'h1)
r_intmc_ivmc <= r_mreq_data[0];
else
r_intmc_ivmc <= 0;
end
if(r_hbytes_en == 1) begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h2: {r_cc_iocqes, r_cc_iosqes, r_cc_shn, r_cc_asm, r_cc_mps, r_cc_ccs, r_cc_en}
<= {r_mreq_data[55:52], r_mreq_data[51:48], r_mreq_data[47:46], r_mreq_data[45:43], r_mreq_data[42:39], r_mreq_data[38:36], r_mreq_data[32]};
4'h4: {r_aqa_acqs, r_aqa_asqs} <= {r_mreq_data[55:48], r_mreq_data[39:32]};
4'h5: r_asq_asqb[C_PCIE_ADDR_WIDTH-1:32] <= r_mreq_data[C_PCIE_ADDR_WIDTH-1:32];
4'h6: r_acq_acqb[C_PCIE_ADDR_WIDTH-1:32] <= r_mreq_data[C_PCIE_ADDR_WIDTH-1:32];
endcase
if(r_mreq_addr[6:3] == 4'h1)
r_intms_ivms <= r_mreq_data[32];
else
r_intms_ivms <= 0;
end
end
else begin
r_intms_ivms <= 0;
r_intmc_ivmc <= 0;
end
end
end
assign w_sq_rst_n[0] = pcie_user_rst_n & sq_rst_n[0];
assign w_sq_rst_n[1] = pcie_user_rst_n & sq_rst_n[1];
assign w_sq_rst_n[2] = pcie_user_rst_n & sq_rst_n[2];
assign w_sq_rst_n[3] = pcie_user_rst_n & sq_rst_n[3];
assign w_sq_rst_n[4] = pcie_user_rst_n & sq_rst_n[4];
assign w_sq_rst_n[5] = pcie_user_rst_n & sq_rst_n[5];
assign w_sq_rst_n[6] = pcie_user_rst_n & sq_rst_n[6];
assign w_sq_rst_n[7] = pcie_user_rst_n & sq_rst_n[7];
assign w_sq_rst_n[8] = pcie_user_rst_n & sq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[0])
begin
if(w_sq_rst_n[0] == 0) begin
r_reg_sq0tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h0)) == 1)
r_reg_sq0tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[1])
begin
if(w_sq_rst_n[1] == 0) begin
r_reg_sq1tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h1)) == 1)
r_reg_sq1tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[2])
begin
if(w_sq_rst_n[2] == 0) begin
r_reg_sq2tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h2)) == 1)
r_reg_sq2tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[3])
begin
if(w_sq_rst_n[3] == 0) begin
r_reg_sq3tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h3)) == 1)
r_reg_sq3tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[4])
begin
if(w_sq_rst_n[4] == 0) begin
r_reg_sq4tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h4)) == 1)
r_reg_sq4tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[5])
begin
if(w_sq_rst_n[5] == 0) begin
r_reg_sq5tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h5)) == 1)
r_reg_sq5tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[6])
begin
if(w_sq_rst_n[6] == 0) begin
r_reg_sq6tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h6)) == 1)
r_reg_sq6tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[7])
begin
if(w_sq_rst_n[7] == 0) begin
r_reg_sq7tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h7)) == 1)
r_reg_sq7tdbl <= r_mreq_data[7:0];
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[8])
begin
if(w_sq_rst_n[8] == 0) begin
r_reg_sq8tdbl <= 0;
end
else begin
if((r_wr_doorbell & r_lbytes_en & (r_mreq_addr[6:3] == 4'h8)) == 1)
r_reg_sq8tdbl <= r_mreq_data[7:0];
end
end
assign w_cq_rst_n[0] = pcie_user_rst_n & cq_rst_n[0];
assign w_cq_rst_n[1] = pcie_user_rst_n & cq_rst_n[1];
assign w_cq_rst_n[2] = pcie_user_rst_n & cq_rst_n[2];
assign w_cq_rst_n[3] = pcie_user_rst_n & cq_rst_n[3];
assign w_cq_rst_n[4] = pcie_user_rst_n & cq_rst_n[4];
assign w_cq_rst_n[5] = pcie_user_rst_n & cq_rst_n[5];
assign w_cq_rst_n[6] = pcie_user_rst_n & cq_rst_n[6];
assign w_cq_rst_n[7] = pcie_user_rst_n & cq_rst_n[7];
assign w_cq_rst_n[8] = pcie_user_rst_n & cq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[0])
begin
if(w_cq_rst_n[0] == 0) begin
r_reg_cq0hdbl <= 0;
r_cq_head_update[0] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h0)) == 1) begin
r_reg_cq0hdbl <= r_mreq_data[39:32];
r_cq_head_update[0] <= 1;
end
else
r_cq_head_update[0] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[1])
begin
if(w_cq_rst_n[1] == 0) begin
r_reg_cq1hdbl <= 0;
r_cq_head_update[1] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h1)) == 1) begin
r_reg_cq1hdbl <= r_mreq_data[39:32];
r_cq_head_update[1] <= 1;
end
else
r_cq_head_update[1] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[2])
begin
if(w_cq_rst_n[2] == 0) begin
r_reg_cq2hdbl <= 0;
r_cq_head_update[2] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h2)) == 1) begin
r_reg_cq2hdbl <= r_mreq_data[39:32];
r_cq_head_update[2] <= 1;
end
else
r_cq_head_update[2] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[3])
begin
if(w_cq_rst_n[3] == 0) begin
r_reg_cq3hdbl <= 0;
r_cq_head_update[3] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h3)) == 1) begin
r_reg_cq3hdbl <= r_mreq_data[39:32];
r_cq_head_update[3] <= 1;
end
else
r_cq_head_update[3] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[4])
begin
if(w_cq_rst_n[4] == 0) begin
r_reg_cq4hdbl <= 0;
r_cq_head_update[4] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h4)) == 1) begin
r_reg_cq4hdbl <= r_mreq_data[39:32];
r_cq_head_update[4] <= 1;
end
else
r_cq_head_update[4] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[5])
begin
if(w_cq_rst_n[5] == 0) begin
r_reg_cq5hdbl <= 0;
r_cq_head_update[5] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h5)) == 1) begin
r_reg_cq5hdbl <= r_mreq_data[39:32];
r_cq_head_update[5] <= 1;
end
else
r_cq_head_update[5] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[6])
begin
if(w_cq_rst_n[6] == 0) begin
r_reg_cq6hdbl <= 0;
r_cq_head_update[6] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h6)) == 1) begin
r_reg_cq6hdbl <= r_mreq_data[39:32];
r_cq_head_update[6] <= 1;
end
else
r_cq_head_update[6] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[7])
begin
if(w_cq_rst_n[7] == 0) begin
r_reg_cq7hdbl <= 0;
r_cq_head_update[7] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h7)) == 1) begin
r_reg_cq7hdbl <= r_mreq_data[39:32];
r_cq_head_update[7] <= 1;
end
else
r_cq_head_update[7] <= 0;
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[8])
begin
if(w_cq_rst_n[8] == 0) begin
r_reg_cq8hdbl <= 0;
r_cq_head_update[8] <= 0;
end
else begin
if((r_wr_doorbell & r_hbytes_en & (r_mreq_addr[6:3] == 4'h8)) == 1) begin
r_reg_cq8hdbl <= r_mreq_data[39:32];
r_cq_head_update[8] <= 1;
end
else
r_cq_head_update[8] <= 0;
end
end
always @ (*)
begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h0: r_rd_reg <= {8'h0, `D_CAP_MPSMAX, `D_CAP_MPSMIN, 3'h0, `D_CAP_CSS, `D_CAP_NSSRS, `D_CAP_DSTRD, `D_CAP_TO, 5'h0, `D_CAP_AMS, `D_CAP_CQR, `D_CAP_MQES};
4'h1: r_rd_reg <= {31'b0, r_cq_irq_status, `D_VS_MJR, `D_VS_MNR, 8'b0};
4'h2: r_rd_reg <= {8'b0, r_cc_iocqes, r_cc_iosqes, r_cc_shn, r_cc_asm, r_cc_mps, r_cc_ccs, 3'b0, r_cc_en, 31'b0, r_cq_irq_status};
4'h3: r_rd_reg <= {28'b0, nvme_csts_shst, 1'b0, nvme_csts_rdy, 32'b0};
4'h4: r_rd_reg <= {8'b0, r_aqa_acqs, 8'b0, r_aqa_asqs, 32'b0};
4'h5: r_rd_reg <= {26'b0, r_asq_asqb, 2'b0};
4'h6: r_rd_reg <= {26'b0, r_acq_acqb, 2'b0};
default: r_rd_reg <= 64'b0;
endcase
end
always @ (*)
begin
case(r_mreq_addr[6:3]) // synthesis parallel_case
4'h0: r_rd_doorbell <= {24'b0, r_reg_cq0hdbl, 24'b0, r_reg_sq0tdbl};
4'h1: r_rd_doorbell <= {24'b0, r_reg_cq1hdbl, 24'b0, r_reg_sq1tdbl};
4'h2: r_rd_doorbell <= {24'b0, r_reg_cq2hdbl, 24'b0, r_reg_sq2tdbl};
4'h3: r_rd_doorbell <= {24'b0, r_reg_cq3hdbl, 24'b0, r_reg_sq3tdbl};
4'h4: r_rd_doorbell <= {24'b0, r_reg_cq4hdbl, 24'b0, r_reg_sq4tdbl};
4'h5: r_rd_doorbell <= {24'b0, r_reg_cq5hdbl, 24'b0, r_reg_sq5tdbl};
4'h6: r_rd_doorbell <= {24'b0, r_reg_cq6hdbl, 24'b0, r_reg_sq6tdbl};
4'h7: r_rd_doorbell <= {24'b0, r_reg_cq7hdbl, 24'b0, r_reg_sq7tdbl};
4'h8: r_rd_doorbell <= {24'b0, r_reg_cq8hdbl, 24'b0, r_reg_sq8tdbl};
default: r_rd_doorbell <= 64'b0;
endcase
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx_fifo # (
parameter P_FIFO_WR_DATA_WIDTH = 64,
parameter P_FIFO_RD_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 9
)
(
input wr_clk,
input wr_rst_n,
input alloc_en,
input [9:4] alloc_len,
input wr_en,
input [P_FIFO_WR_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_RD_DATA_WIDTH-1:0] rd_data,
input free_en,
input [9:4] free_len,
output empty_n
);
localparam P_FIFO_WR_DEPTH_WIDTH = P_FIFO_DEPTH_WIDTH + 1;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_WR_DEPTH_WIDTH:0] r_rear_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_full_addr;
wire [1:0] w_wr_en;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH:0] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_empty_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH:0] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
wire [P_FIFO_DEPTH_WIDTH:0] w_valid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_space;
assign w_invalid_space = r_front_sync_addr - r_rear_full_addr;
assign full_n = (w_invalid_space >= alloc_len);
assign w_wr_en[0] = wr_en & ~r_rear_addr[0];
assign w_wr_en[1] = wr_en & r_rear_addr[0];
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
r_rear_full_addr <= 0;
end
else begin
if (alloc_en == 1)
r_rear_full_addr <= r_rear_full_addr + alloc_len;
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign w_valid_space = r_rear_sync_addr - r_front_empty_addr;
assign empty_n = (w_valid_space >= free_len);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_front_empty_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (free_en == 1)
r_front_empty_addr <= r_front_empty_addr + free_len;
end
end
assign w_front_addr[P_FIFO_DEPTH_WIDTH-1:0] = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr[P_FIFO_DEPTH_WIDTH] <= 1;
r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:0] <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_WR_DEPTH_WIDTH:1];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data[P_FIFO_DEPTH_WIDTH] <= 1;
r_front_sync_data[P_FIFO_DEPTH_WIDTH-1:0] <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data[P_FIFO_DEPTH_WIDTH] <= ~r_front_addr[P_FIFO_DEPTH_WIDTH];
r_front_sync_data[P_FIFO_DEPTH_WIDTH-1:0] <= r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_RD_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_FIFO_WR_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_WR_DEPTH_WIDTH-1:1];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_WR_DEPTH_WIDTH-1:1]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (w_wr_en[0])
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (rd_data[P_FIFO_RD_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (w_wr_en[1])
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
rst_sync_l, rst_both_l, rst_async_l, d, clk
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To sub1 of sub1.v, ...
input d; // To sub1 of sub1.v, ...
input rst_async_l; // To sub2 of sub2.v
input rst_both_l; // To sub1 of sub1.v, ...
input rst_sync_l; // To sub1 of sub1.v
// End of automatics
sub1 sub1 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_sync_l (rst_sync_l),
.d (d));
sub2 sub2 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_async_l (rst_async_l),
.d (d));
endmodule
module sub1 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_sync_l, d
);
input clk;
input rst_both_l;
input rst_sync_l;
//input rst_async_l;
input d;
reg q1;
reg q2;
always @(posedge clk) begin
if (~rst_sync_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end
end
always @(posedge clk) begin
q2 <= (~rst_both_l) ? 1'b0 : d;
if (0 && q1 && q2) ;
end
endmodule
module sub2 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_async_l, d
);
input clk;
input rst_both_l;
//input rst_sync_l;
input rst_async_l;
input d;
reg q1;
reg q2;
reg q3;
always @(posedge clk or negedge rst_async_l) begin
if (~rst_async_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end
end
always @(posedge clk or negedge rst_both_l) begin
q2 <= (~rst_both_l) ? 1'b0 : d;
end
// Make there be more async uses than sync uses
always @(posedge clk or negedge rst_both_l) begin
q3 <= (~rst_both_l) ? 1'b0 : d;
if (0 && q1 && q2 && q3) ;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
rst_sync_l, rst_both_l, rst_async_l, d, clk
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To sub1 of sub1.v, ...
input d; // To sub1 of sub1.v, ...
input rst_async_l; // To sub2 of sub2.v
input rst_both_l; // To sub1 of sub1.v, ...
input rst_sync_l; // To sub1 of sub1.v
// End of automatics
sub1 sub1 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_sync_l (rst_sync_l),
.d (d));
sub2 sub2 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_async_l (rst_async_l),
.d (d));
endmodule
module sub1 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_sync_l, d
);
input clk;
input rst_both_l;
input rst_sync_l;
//input rst_async_l;
input d;
reg q1;
reg q2;
always @(posedge clk) begin
if (~rst_sync_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end
end
always @(posedge clk) begin
q2 <= (~rst_both_l) ? 1'b0 : d;
if (0 && q1 && q2) ;
end
endmodule
module sub2 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_async_l, d
);
input clk;
input rst_both_l;
//input rst_sync_l;
input rst_async_l;
input d;
reg q1;
reg q2;
reg q3;
always @(posedge clk or negedge rst_async_l) begin
if (~rst_async_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end
end
always @(posedge clk or negedge rst_both_l) begin
q2 <= (~rst_both_l) ? 1'b0 : d;
end
// Make there be more async uses than sync uses
always @(posedge clk or negedge rst_both_l) begin
q3 <= (~rst_both_l) ? 1'b0 : d;
if (0 && q1 && q2 && q3) ;
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module user_top # (
parameter C_S0_AXI_ADDR_WIDTH = 32,
parameter C_S0_AXI_DATA_WIDTH = 32,
parameter C_S0_AXI_BASEADDR = 32'h80000000,
parameter C_S0_AXI_HIGHADDR = 32'h80010000,
parameter C_M0_AXI_ADDR_WIDTH = 32,
parameter C_M0_AXI_DATA_WIDTH = 64,
parameter C_M0_AXI_ID_WIDTH = 1,
parameter C_M0_AXI_AWUSER_WIDTH = 1,
parameter C_M0_AXI_WUSER_WIDTH = 1,
parameter C_M0_AXI_BUSER_WIDTH = 1,
parameter C_M0_AXI_ARUSER_WIDTH = 1,
parameter C_M0_AXI_RUSER_WIDTH = 1,
parameter C_PCIE_DATA_WIDTH = 128
)
(
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
input s0_axi_aclk,
input s0_axi_aresetn,
//Write address channel
input [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_awaddr,
output s0_axi_awready,
input s0_axi_awvalid,
input [2 : 0] s0_axi_awprot,
//Write data channel
input s0_axi_wvalid,
output s0_axi_wready,
input [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_wdata,
input [(C_S0_AXI_DATA_WIDTH/8)-1 : 0] s0_axi_wstrb,
//Write response channel
output s0_axi_bvalid,
input s0_axi_bready,
output [1 : 0] s0_axi_bresp,
//Read address channel
input s0_axi_arvalid,
output s0_axi_arready,
input [C_S0_AXI_ADDR_WIDTH-1 : 0] s0_axi_araddr,
input [2 : 0] s0_axi_arprot,
//Read data channel
output s0_axi_rvalid,
input s0_axi_rready,
output [C_S0_AXI_DATA_WIDTH-1 : 0] s0_axi_rdata,
output [1 : 0] s0_axi_rresp,
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
input m0_axi_aclk,
input m0_axi_aresetn,
// Write address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_awid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_awaddr,
output [7:0] m0_axi_awlen,
output [2:0] m0_axi_awsize,
output [1:0] m0_axi_awburst,
output [1:0] m0_axi_awlock,
output [3:0] m0_axi_awcache,
output [2:0] m0_axi_awprot,
output [3:0] m0_axi_awregion,
output [3:0] m0_axi_awqos,
output [C_M0_AXI_AWUSER_WIDTH-1:0] m0_axi_awuser,
output m0_axi_awvalid,
input m0_axi_awready,
// Write data channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_wid,
output [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_wdata,
output [(C_M0_AXI_DATA_WIDTH/8)-1:0] m0_axi_wstrb,
output m0_axi_wlast,
output [C_M0_AXI_WUSER_WIDTH-1:0] m0_axi_wuser,
output m0_axi_wvalid,
input m0_axi_wready,
// Write response channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_bid,
input [1:0] m0_axi_bresp,
input m0_axi_bvalid,
input [C_M0_AXI_BUSER_WIDTH-1:0] m0_axi_buser,
output m0_axi_bready,
// Read address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_arid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_araddr,
output [7:0] m0_axi_arlen,
output [2:0] m0_axi_arsize,
output [1:0] m0_axi_arburst,
output [1:0] m0_axi_arlock,
output [3:0] m0_axi_arcache,
output [2:0] m0_axi_arprot,
output [3:0] m0_axi_arregion,
output [3:0] m0_axi_arqos,
output [C_M0_AXI_ARUSER_WIDTH-1:0] m0_axi_aruser,
output m0_axi_arvalid,
input m0_axi_arready,
// Read data channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_rid,
input [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_rdata,
input [1:0] m0_axi_rresp,
input m0_axi_rlast,
input [C_M0_AXI_RUSER_WIDTH-1:0] m0_axi_ruser,
input m0_axi_rvalid,
output m0_axi_rready,
input pcie_ref_clk_p,
input pcie_ref_clk_n,
input pcie_perst_n,
output dev_irq_assert,
//PCIe Integrated Block Interface
input user_clk_out,
input user_reset_out,
input user_lnk_up,
input [5:0] tx_buf_av,
input tx_err_drop,
input tx_cfg_req,
input s_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_tx_tkeep,
output [3:0] s_axis_tx_tuser,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_cfg_gnt,
input [C_PCIE_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
output rx_np_ok,
output rx_np_req,
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input cfg_to_turnoff,
output cfg_turnoff_ok,
input [15:0] cfg_command,
input [15:0] cfg_dcommand,
input [15:0] cfg_lcommand,
input [5:0] pl_ltssm_state,
input pl_received_hot_rst,
output sys_clk,
output sys_rst_n
);
parameter C_PCIE_ADDR_WIDTH = 36;
wire pcie_user_rst_n;
wire w_pcie_user_logic_rst;
wire w_pcie_link_up_sync;
wire [5:0] w_pl_ltssm_state_sync;
wire [15:0] w_cfg_command_sync;
wire [2:0] w_cfg_interrupt_mmenable_sync;
wire w_cfg_interrupt_msienable_sync;
wire w_cfg_interrupt_msixenable_sync;
wire w_pcie_mreq_err_sync;
wire w_pcie_cpld_err_sync;
wire w_pcie_cpld_len_err_sync;
wire w_nvme_cc_en_sync;
wire [1:0] w_nvme_cc_shn_sync;
wire [1:0] w_nvme_csts_shst;
wire w_nvme_csts_rdy;
wire [8:0] w_sq_valid;
wire [7:0] w_io_sq1_size;
wire [7:0] w_io_sq2_size;
wire [7:0] w_io_sq3_size;
wire [7:0] w_io_sq4_size;
wire [7:0] w_io_sq5_size;
wire [7:0] w_io_sq6_size;
wire [7:0] w_io_sq7_size;
wire [7:0] w_io_sq8_size;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq1_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq2_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq3_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq4_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq5_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq6_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq7_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq8_bs_addr;
wire [3:0] w_io_sq1_cq_vec;
wire [3:0] w_io_sq2_cq_vec;
wire [3:0] w_io_sq3_cq_vec;
wire [3:0] w_io_sq4_cq_vec;
wire [3:0] w_io_sq5_cq_vec;
wire [3:0] w_io_sq6_cq_vec;
wire [3:0] w_io_sq7_cq_vec;
wire [3:0] w_io_sq8_cq_vec;
wire [8:0] w_cq_valid;
wire [7:0] w_io_cq1_size;
wire [7:0] w_io_cq2_size;
wire [7:0] w_io_cq3_size;
wire [7:0] w_io_cq4_size;
wire [7:0] w_io_cq5_size;
wire [7:0] w_io_cq6_size;
wire [7:0] w_io_cq7_size;
wire [7:0] w_io_cq8_size;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq1_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq2_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq3_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq4_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq5_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq6_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq7_bs_addr;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq8_bs_addr;
wire [8:0] w_io_cq_irq_en;
wire [2:0] w_io_cq1_iv;
wire [2:0] w_io_cq2_iv;
wire [2:0] w_io_cq3_iv;
wire [2:0] w_io_cq4_iv;
wire [2:0] w_io_cq5_iv;
wire [2:0] w_io_cq6_iv;
wire [2:0] w_io_cq7_iv;
wire [2:0] w_io_cq8_iv;
wire w_nvme_cc_en;
wire [1:0] w_nvme_cc_shn;
wire w_pcie_mreq_err;
wire w_pcie_cpld_err;
wire w_pcie_cpld_len_err;
wire [1:0] w_nvme_csts_shst_sync;
wire w_nvme_csts_rdy_sync;
wire [8:0] w_sq_rst_n_sync;
wire [8:0] w_sq_valid_sync;
wire [7:0] w_io_sq1_size_sync;
wire [7:0] w_io_sq2_size_sync;
wire [7:0] w_io_sq3_size_sync;
wire [7:0] w_io_sq4_size_sync;
wire [7:0] w_io_sq5_size_sync;
wire [7:0] w_io_sq6_size_sync;
wire [7:0] w_io_sq7_size_sync;
wire [7:0] w_io_sq8_size_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq1_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq2_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq3_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq4_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq5_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq6_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq7_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_sq8_bs_addr_sync;
wire [3:0] w_io_sq1_cq_vec_sync;
wire [3:0] w_io_sq2_cq_vec_sync;
wire [3:0] w_io_sq3_cq_vec_sync;
wire [3:0] w_io_sq4_cq_vec_sync;
wire [3:0] w_io_sq5_cq_vec_sync;
wire [3:0] w_io_sq6_cq_vec_sync;
wire [3:0] w_io_sq7_cq_vec_sync;
wire [3:0] w_io_sq8_cq_vec_sync;
wire [8:0] w_cq_rst_n_sync;
wire [8:0] w_cq_valid_sync;
wire [7:0] w_io_cq1_size_sync;
wire [7:0] w_io_cq2_size_sync;
wire [7:0] w_io_cq3_size_sync;
wire [7:0] w_io_cq4_size_sync;
wire [7:0] w_io_cq5_size_sync;
wire [7:0] w_io_cq6_size_sync;
wire [7:0] w_io_cq7_size_sync;
wire [7:0] w_io_cq8_size_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq1_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq2_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq3_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq4_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq5_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq6_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq7_bs_addr_sync;
wire [C_PCIE_ADDR_WIDTH-1:2] w_io_cq8_bs_addr_sync;
wire [8:0] w_io_cq_irq_en_sync;
wire [2:0] w_io_cq1_iv_sync;
wire [2:0] w_io_cq2_iv_sync;
wire [2:0] w_io_cq3_iv_sync;
wire [2:0] w_io_cq4_iv_sync;
wire [2:0] w_io_cq5_iv_sync;
wire [2:0] w_io_cq6_iv_sync;
wire [2:0] w_io_cq7_iv_sync;
wire [2:0] w_io_cq8_iv_sync;
wire [10:0] w_hcmd_table_rd_addr;
wire [31:0] w_hcmd_table_rd_data;
wire w_hcmd_sq_rd_en;
wire [18:0] w_hcmd_sq_rd_data;
wire w_hcmd_sq_empty_n;
wire w_hcmd_cq_wr1_en;
wire [34:0] w_hcmd_cq_wr1_data0;
wire [34:0] w_hcmd_cq_wr1_data1;
wire w_hcmd_cq_wr1_rdy_n;
wire w_dma_cmd_wr_en;
wire [49:0] w_dma_cmd_wr_data0;
wire [49:0] w_dma_cmd_wr_data1;
wire w_dma_cmd_wr_rdy_n;
wire [7:0] w_dma_rx_direct_done_cnt;
wire [7:0] w_dma_tx_direct_done_cnt;
wire [7:0] w_dma_rx_done_cnt;
wire [7:0] w_dma_tx_done_cnt;
wire w_pcie_rx_fifo_rd_en;
wire [C_M0_AXI_DATA_WIDTH-1:0] w_pcie_rx_fifo_rd_data;
wire w_pcie_rx_fifo_free_en;
wire [9:4] w_pcie_rx_fifo_free_len;
wire w_pcie_rx_fifo_empty_n;
wire w_pcie_tx_fifo_alloc_en;
wire [9:4] w_pcie_tx_fifo_alloc_len;
wire w_pcie_tx_fifo_wr_en;
wire [C_M0_AXI_DATA_WIDTH-1:0] w_pcie_tx_fifo_wr_data;
wire w_pcie_tx_fifo_full_n;
wire w_dma_rx_done_wr_en;
wire [20:0] w_dma_rx_done_wr_data;
wire w_dma_rx_done_wr_rdy_n;
wire w_dev_rx_cmd_wr_en;
wire [29:0] w_dev_rx_cmd_wr_data;
wire w_dev_rx_cmd_full_n;
wire w_dev_tx_cmd_wr_en;
wire [29:0] w_dev_tx_cmd_wr_data;
wire w_dev_tx_cmd_full_n;
sys_rst
sys_rst_inst0(
.cpu_bus_clk (s0_axi_aclk),
.cpu_bus_rst_n (s0_axi_aresetn),
.pcie_perst_n (pcie_perst_n),
.user_reset_out (user_reset_out),
.pcie_pl_hot_rst (pl_received_hot_rst),
.pcie_user_logic_rst (w_pcie_user_logic_rst),
.pcie_sys_rst_n (sys_rst_n),
.pcie_user_rst_n (pcie_user_rst_n)
);
s_axi_top # (
.C_S0_AXI_ADDR_WIDTH (C_S0_AXI_ADDR_WIDTH),
.C_S0_AXI_DATA_WIDTH (C_S0_AXI_DATA_WIDTH),
.C_S0_AXI_BASEADDR (C_S0_AXI_BASEADDR),
.C_S0_AXI_HIGHADDR (C_S0_AXI_HIGHADDR),
.C_M0_AXI_ADDR_WIDTH (C_M0_AXI_ADDR_WIDTH),
.C_M0_AXI_DATA_WIDTH (C_M0_AXI_DATA_WIDTH),
.C_M0_AXI_ID_WIDTH (C_M0_AXI_ID_WIDTH),
.C_M0_AXI_AWUSER_WIDTH (C_M0_AXI_AWUSER_WIDTH),
.C_M0_AXI_WUSER_WIDTH (C_M0_AXI_WUSER_WIDTH),
.C_M0_AXI_BUSER_WIDTH (C_M0_AXI_BUSER_WIDTH),
.C_M0_AXI_ARUSER_WIDTH (C_M0_AXI_ARUSER_WIDTH),
.C_M0_AXI_RUSER_WIDTH (C_M0_AXI_RUSER_WIDTH)
)
s_axi_top_inst0 (
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
.s0_axi_aclk (s0_axi_aclk),
.s0_axi_aresetn (s0_axi_aresetn),
//Write address channel
.s0_axi_awaddr (s0_axi_awaddr),
.s0_axi_awready (s0_axi_awready),
.s0_axi_awvalid (s0_axi_awvalid),
.s0_axi_awprot (s0_axi_awprot),
//Write data channel
.s0_axi_wvalid (s0_axi_wvalid),
.s0_axi_wready (s0_axi_wready),
.s0_axi_wdata (s0_axi_wdata),
.s0_axi_wstrb (s0_axi_wstrb),
//Write response channel
.s0_axi_bvalid (s0_axi_bvalid),
.s0_axi_bready (s0_axi_bready),
.s0_axi_bresp (s0_axi_bresp),
//Read address channel
.s0_axi_arvalid (s0_axi_arvalid),
.s0_axi_arready (s0_axi_arready),
.s0_axi_araddr (s0_axi_araddr),
.s0_axi_arprot (s0_axi_arprot),
//Read data channel
.s0_axi_rvalid (s0_axi_rvalid),
.s0_axi_rready (s0_axi_rready),
.s0_axi_rdata (s0_axi_rdata),
.s0_axi_rresp (s0_axi_rresp),
.pcie_mreq_err (w_pcie_mreq_err_sync),
.pcie_cpld_err (w_pcie_cpld_err_sync),
.pcie_cpld_len_err (w_pcie_cpld_len_err_sync),
.dev_irq_assert (dev_irq_assert),
.pcie_user_logic_rst (w_pcie_user_logic_rst),
.nvme_cc_en (w_nvme_cc_en_sync),
.nvme_cc_shn (w_nvme_cc_shn_sync),
.nvme_csts_shst (w_nvme_csts_shst),
.nvme_csts_rdy (w_nvme_csts_rdy),
.sq_valid (w_sq_valid),
.io_sq1_size (w_io_sq1_size),
.io_sq2_size (w_io_sq2_size),
.io_sq3_size (w_io_sq3_size),
.io_sq4_size (w_io_sq4_size),
.io_sq5_size (w_io_sq5_size),
.io_sq6_size (w_io_sq6_size),
.io_sq7_size (w_io_sq7_size),
.io_sq8_size (w_io_sq8_size),
.io_sq1_bs_addr (w_io_sq1_bs_addr),
.io_sq2_bs_addr (w_io_sq2_bs_addr),
.io_sq3_bs_addr (w_io_sq3_bs_addr),
.io_sq4_bs_addr (w_io_sq4_bs_addr),
.io_sq5_bs_addr (w_io_sq5_bs_addr),
.io_sq6_bs_addr (w_io_sq6_bs_addr),
.io_sq7_bs_addr (w_io_sq7_bs_addr),
.io_sq8_bs_addr (w_io_sq8_bs_addr),
.io_sq1_cq_vec (w_io_sq1_cq_vec),
.io_sq2_cq_vec (w_io_sq2_cq_vec),
.io_sq3_cq_vec (w_io_sq3_cq_vec),
.io_sq4_cq_vec (w_io_sq4_cq_vec),
.io_sq5_cq_vec (w_io_sq5_cq_vec),
.io_sq6_cq_vec (w_io_sq6_cq_vec),
.io_sq7_cq_vec (w_io_sq7_cq_vec),
.io_sq8_cq_vec (w_io_sq8_cq_vec),
.cq_valid (w_cq_valid),
.io_cq1_size (w_io_cq1_size),
.io_cq2_size (w_io_cq2_size),
.io_cq3_size (w_io_cq3_size),
.io_cq4_size (w_io_cq4_size),
.io_cq5_size (w_io_cq5_size),
.io_cq6_size (w_io_cq6_size),
.io_cq7_size (w_io_cq7_size),
.io_cq8_size (w_io_cq8_size),
.io_cq1_bs_addr (w_io_cq1_bs_addr),
.io_cq2_bs_addr (w_io_cq2_bs_addr),
.io_cq3_bs_addr (w_io_cq3_bs_addr),
.io_cq4_bs_addr (w_io_cq4_bs_addr),
.io_cq5_bs_addr (w_io_cq5_bs_addr),
.io_cq6_bs_addr (w_io_cq6_bs_addr),
.io_cq7_bs_addr (w_io_cq7_bs_addr),
.io_cq8_bs_addr (w_io_cq8_bs_addr),
.io_cq_irq_en (w_io_cq_irq_en),
.io_cq1_iv (w_io_cq1_iv),
.io_cq2_iv (w_io_cq2_iv),
.io_cq3_iv (w_io_cq3_iv),
.io_cq4_iv (w_io_cq4_iv),
.io_cq5_iv (w_io_cq5_iv),
.io_cq6_iv (w_io_cq6_iv),
.io_cq7_iv (w_io_cq7_iv),
.io_cq8_iv (w_io_cq8_iv),
.hcmd_sq_rd_en (w_hcmd_sq_rd_en),
.hcmd_sq_rd_data (w_hcmd_sq_rd_data),
.hcmd_sq_empty_n (w_hcmd_sq_empty_n),
.hcmd_table_rd_addr (w_hcmd_table_rd_addr),
.hcmd_table_rd_data (w_hcmd_table_rd_data),
.hcmd_cq_wr1_en (w_hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (w_hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (w_hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (w_hcmd_cq_wr1_rdy_n),
.dma_cmd_wr_en (w_dma_cmd_wr_en),
.dma_cmd_wr_data0 (w_dma_cmd_wr_data0),
.dma_cmd_wr_data1 (w_dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (w_dma_cmd_wr_rdy_n),
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
.m0_axi_aclk (m0_axi_aclk),
.m0_axi_aresetn (m0_axi_aresetn),
// Write address channel
.m0_axi_awid (m0_axi_awid),
.m0_axi_awaddr (m0_axi_awaddr),
.m0_axi_awlen (m0_axi_awlen),
.m0_axi_awsize (m0_axi_awsize),
.m0_axi_awburst (m0_axi_awburst),
.m0_axi_awlock (m0_axi_awlock),
.m0_axi_awcache (m0_axi_awcache),
.m0_axi_awprot (m0_axi_awprot),
.m0_axi_awregion (m0_axi_awregion),
.m0_axi_awqos (m0_axi_awqos),
.m0_axi_awuser (m0_axi_awuser),
.m0_axi_awvalid (m0_axi_awvalid),
.m0_axi_awready (m0_axi_awready),
// Write data channel
.m0_axi_wid (m0_axi_wid),
.m0_axi_wdata (m0_axi_wdata),
.m0_axi_wstrb (m0_axi_wstrb),
.m0_axi_wlast (m0_axi_wlast),
.m0_axi_wuser (m0_axi_wuser),
.m0_axi_wvalid (m0_axi_wvalid),
.m0_axi_wready (m0_axi_wready),
// Write response channel
.m0_axi_bid (m0_axi_bid),
.m0_axi_bresp (m0_axi_bresp),
.m0_axi_bvalid (m0_axi_bvalid),
.m0_axi_buser (m0_axi_buser),
.m0_axi_bready (m0_axi_bready),
// Read address channel
.m0_axi_arid (m0_axi_arid),
.m0_axi_araddr (m0_axi_araddr),
.m0_axi_arlen (m0_axi_arlen),
.m0_axi_arsize (m0_axi_arsize),
.m0_axi_arburst (m0_axi_arburst),
.m0_axi_arlock (m0_axi_arlock),
.m0_axi_arcache (m0_axi_arcache),
.m0_axi_arprot (m0_axi_arprot),
.m0_axi_arregion (m0_axi_arregion),
.m0_axi_arqos (m0_axi_arqos),
.m0_axi_aruser (m0_axi_aruser),
.m0_axi_arvalid (m0_axi_arvalid),
.m0_axi_arready (m0_axi_arready),
// Read data channel
.m0_axi_rid (m0_axi_rid),
.m0_axi_rdata (m0_axi_rdata),
.m0_axi_rresp (m0_axi_rresp),
.m0_axi_rlast (m0_axi_rlast),
.m0_axi_ruser (m0_axi_ruser),
.m0_axi_rvalid (m0_axi_rvalid),
.m0_axi_rready (m0_axi_rready),
.pcie_rx_fifo_rd_en (w_pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (w_pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (w_pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (w_pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (w_pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (w_pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (w_pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (w_pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (w_pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (w_pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (w_dma_rx_done_wr_en),
.dma_rx_done_wr_data (w_dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (w_dma_rx_done_wr_rdy_n),
.pcie_user_clk (user_clk_out),
.pcie_user_rst_n (pcie_user_rst_n),
.dev_rx_cmd_wr_en (w_dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (w_dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (w_dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (w_dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (w_dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (w_dev_tx_cmd_full_n),
.dma_rx_direct_done_cnt (w_dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (w_dma_tx_direct_done_cnt),
.dma_rx_done_cnt (w_dma_rx_done_cnt),
.dma_tx_done_cnt (w_dma_tx_done_cnt),
.pcie_link_up (w_pcie_link_up_sync),
.pl_ltssm_state (w_pl_ltssm_state_sync),
.cfg_command (w_cfg_command_sync),
.cfg_interrupt_mmenable (w_cfg_interrupt_mmenable_sync),
.cfg_interrupt_msienable (w_cfg_interrupt_msienable_sync),
.cfg_interrupt_msixenable (w_cfg_interrupt_msixenable_sync)
);
reg_cpu_pcie_sync
reg_cpu_pcie_sync_isnt0
(
.cpu_bus_clk (s0_axi_aclk),
.nvme_csts_shst (w_nvme_csts_shst),
.nvme_csts_rdy (w_nvme_csts_rdy),
.sq_valid (w_sq_valid),
.io_sq1_size (w_io_sq1_size),
.io_sq2_size (w_io_sq2_size),
.io_sq3_size (w_io_sq3_size),
.io_sq4_size (w_io_sq4_size),
.io_sq5_size (w_io_sq5_size),
.io_sq6_size (w_io_sq6_size),
.io_sq7_size (w_io_sq7_size),
.io_sq8_size (w_io_sq8_size),
.io_sq1_bs_addr (w_io_sq1_bs_addr),
.io_sq2_bs_addr (w_io_sq2_bs_addr),
.io_sq3_bs_addr (w_io_sq3_bs_addr),
.io_sq4_bs_addr (w_io_sq4_bs_addr),
.io_sq5_bs_addr (w_io_sq5_bs_addr),
.io_sq6_bs_addr (w_io_sq6_bs_addr),
.io_sq7_bs_addr (w_io_sq7_bs_addr),
.io_sq8_bs_addr (w_io_sq8_bs_addr),
.io_sq1_cq_vec (w_io_sq1_cq_vec),
.io_sq2_cq_vec (w_io_sq2_cq_vec),
.io_sq3_cq_vec (w_io_sq3_cq_vec),
.io_sq4_cq_vec (w_io_sq4_cq_vec),
.io_sq5_cq_vec (w_io_sq5_cq_vec),
.io_sq6_cq_vec (w_io_sq6_cq_vec),
.io_sq7_cq_vec (w_io_sq7_cq_vec),
.io_sq8_cq_vec (w_io_sq8_cq_vec),
.cq_valid (w_cq_valid),
.io_cq1_size (w_io_cq1_size),
.io_cq2_size (w_io_cq2_size),
.io_cq3_size (w_io_cq3_size),
.io_cq4_size (w_io_cq4_size),
.io_cq5_size (w_io_cq5_size),
.io_cq6_size (w_io_cq6_size),
.io_cq7_size (w_io_cq7_size),
.io_cq8_size (w_io_cq8_size),
.io_cq1_bs_addr (w_io_cq1_bs_addr),
.io_cq2_bs_addr (w_io_cq2_bs_addr),
.io_cq3_bs_addr (w_io_cq3_bs_addr),
.io_cq4_bs_addr (w_io_cq4_bs_addr),
.io_cq5_bs_addr (w_io_cq5_bs_addr),
.io_cq6_bs_addr (w_io_cq6_bs_addr),
.io_cq7_bs_addr (w_io_cq7_bs_addr),
.io_cq8_bs_addr (w_io_cq8_bs_addr),
.io_cq_irq_en (w_io_cq_irq_en),
.io_cq1_iv (w_io_cq1_iv),
.io_cq2_iv (w_io_cq2_iv),
.io_cq3_iv (w_io_cq3_iv),
.io_cq4_iv (w_io_cq4_iv),
.io_cq5_iv (w_io_cq5_iv),
.io_cq6_iv (w_io_cq6_iv),
.io_cq7_iv (w_io_cq7_iv),
.io_cq8_iv (w_io_cq8_iv),
.pcie_link_up_sync (w_pcie_link_up_sync),
.pl_ltssm_state_sync (w_pl_ltssm_state_sync),
.cfg_command_sync (w_cfg_command_sync),
.cfg_interrupt_mmenable_sync (w_cfg_interrupt_mmenable_sync),
.cfg_interrupt_msienable_sync (w_cfg_interrupt_msienable_sync),
.cfg_interrupt_msixenable_sync (w_cfg_interrupt_msixenable_sync),
.pcie_mreq_err_sync (w_pcie_mreq_err_sync),
.pcie_cpld_err_sync (w_pcie_cpld_err_sync),
.pcie_cpld_len_err_sync (w_pcie_cpld_len_err_sync),
.nvme_cc_en_sync (w_nvme_cc_en_sync),
.nvme_cc_shn_sync (w_nvme_cc_shn_sync),
.pcie_user_clk (user_clk_out),
.pcie_link_up (user_lnk_up),
.pl_ltssm_state (pl_ltssm_state),
.cfg_command (cfg_command),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.pcie_mreq_err (w_pcie_mreq_err),
.pcie_cpld_err (w_pcie_cpld_err),
.pcie_cpld_len_err (w_pcie_cpld_len_err),
.nvme_cc_en (w_nvme_cc_en),
.nvme_cc_shn (w_nvme_cc_shn),
.nvme_csts_shst_sync (w_nvme_csts_shst_sync),
.nvme_csts_rdy_sync (w_nvme_csts_rdy_sync),
.sq_rst_n_sync (w_sq_rst_n_sync),
.sq_valid_sync (w_sq_valid_sync),
.io_sq1_size_sync (w_io_sq1_size_sync),
.io_sq2_size_sync (w_io_sq2_size_sync),
.io_sq3_size_sync (w_io_sq3_size_sync),
.io_sq4_size_sync (w_io_sq4_size_sync),
.io_sq5_size_sync (w_io_sq5_size_sync),
.io_sq6_size_sync (w_io_sq6_size_sync),
.io_sq7_size_sync (w_io_sq7_size_sync),
.io_sq8_size_sync (w_io_sq8_size_sync),
.io_sq1_bs_addr_sync (w_io_sq1_bs_addr_sync),
.io_sq2_bs_addr_sync (w_io_sq2_bs_addr_sync),
.io_sq3_bs_addr_sync (w_io_sq3_bs_addr_sync),
.io_sq4_bs_addr_sync (w_io_sq4_bs_addr_sync),
.io_sq5_bs_addr_sync (w_io_sq5_bs_addr_sync),
.io_sq6_bs_addr_sync (w_io_sq6_bs_addr_sync),
.io_sq7_bs_addr_sync (w_io_sq7_bs_addr_sync),
.io_sq8_bs_addr_sync (w_io_sq8_bs_addr_sync),
.io_sq1_cq_vec_sync (w_io_sq1_cq_vec_sync),
.io_sq2_cq_vec_sync (w_io_sq2_cq_vec_sync),
.io_sq3_cq_vec_sync (w_io_sq3_cq_vec_sync),
.io_sq4_cq_vec_sync (w_io_sq4_cq_vec_sync),
.io_sq5_cq_vec_sync (w_io_sq5_cq_vec_sync),
.io_sq6_cq_vec_sync (w_io_sq6_cq_vec_sync),
.io_sq7_cq_vec_sync (w_io_sq7_cq_vec_sync),
.io_sq8_cq_vec_sync (w_io_sq8_cq_vec_sync),
.cq_rst_n_sync (w_cq_rst_n_sync),
.cq_valid_sync (w_cq_valid_sync),
.io_cq1_size_sync (w_io_cq1_size_sync),
.io_cq2_size_sync (w_io_cq2_size_sync),
.io_cq3_size_sync (w_io_cq3_size_sync),
.io_cq4_size_sync (w_io_cq4_size_sync),
.io_cq5_size_sync (w_io_cq5_size_sync),
.io_cq6_size_sync (w_io_cq6_size_sync),
.io_cq7_size_sync (w_io_cq7_size_sync),
.io_cq8_size_sync (w_io_cq8_size_sync),
.io_cq1_bs_addr_sync (w_io_cq1_bs_addr_sync),
.io_cq2_bs_addr_sync (w_io_cq2_bs_addr_sync),
.io_cq3_bs_addr_sync (w_io_cq3_bs_addr_sync),
.io_cq4_bs_addr_sync (w_io_cq4_bs_addr_sync),
.io_cq5_bs_addr_sync (w_io_cq5_bs_addr_sync),
.io_cq6_bs_addr_sync (w_io_cq6_bs_addr_sync),
.io_cq7_bs_addr_sync (w_io_cq7_bs_addr_sync),
.io_cq8_bs_addr_sync (w_io_cq8_bs_addr_sync),
.io_cq_irq_en_sync (w_io_cq_irq_en_sync),
.io_cq1_iv_sync (w_io_cq1_iv_sync),
.io_cq2_iv_sync (w_io_cq2_iv_sync),
.io_cq3_iv_sync (w_io_cq3_iv_sync),
.io_cq4_iv_sync (w_io_cq4_iv_sync),
.io_cq5_iv_sync (w_io_cq5_iv_sync),
.io_cq6_iv_sync (w_io_cq6_iv_sync),
.io_cq7_iv_sync (w_io_cq7_iv_sync),
.io_cq8_iv_sync (w_io_cq8_iv_sync)
);
nvme_pcie # (
.C_PCIE_DATA_WIDTH (128)
)
nvme_pcie_inst0(
.pcie_ref_clk_p (pcie_ref_clk_p),
.pcie_ref_clk_n (pcie_ref_clk_n),
//PCIe user clock
.pcie_user_clk (user_clk_out),
.pcie_user_rst_n (pcie_user_rst_n),
.dev_rx_cmd_wr_en (w_dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (w_dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (w_dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (w_dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (w_dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (w_dev_tx_cmd_full_n),
.cpu_bus_clk (s0_axi_aclk),
.cpu_bus_rst_n (s0_axi_aresetn),
.nvme_cc_en (w_nvme_cc_en),
.nvme_cc_shn (w_nvme_cc_shn),
.nvme_csts_shst (w_nvme_csts_shst_sync),
.nvme_csts_rdy (w_nvme_csts_rdy_sync),
.sq_rst_n (w_sq_rst_n_sync),
.sq_valid (w_sq_valid_sync),
.io_sq1_size (w_io_sq1_size_sync),
.io_sq2_size (w_io_sq2_size_sync),
.io_sq3_size (w_io_sq3_size_sync),
.io_sq4_size (w_io_sq4_size_sync),
.io_sq5_size (w_io_sq5_size_sync),
.io_sq6_size (w_io_sq6_size_sync),
.io_sq7_size (w_io_sq7_size_sync),
.io_sq8_size (w_io_sq8_size_sync),
.io_sq1_bs_addr (w_io_sq1_bs_addr_sync),
.io_sq2_bs_addr (w_io_sq2_bs_addr_sync),
.io_sq3_bs_addr (w_io_sq3_bs_addr_sync),
.io_sq4_bs_addr (w_io_sq4_bs_addr_sync),
.io_sq5_bs_addr (w_io_sq5_bs_addr_sync),
.io_sq6_bs_addr (w_io_sq6_bs_addr_sync),
.io_sq7_bs_addr (w_io_sq7_bs_addr_sync),
.io_sq8_bs_addr (w_io_sq8_bs_addr_sync),
.io_sq1_cq_vec (w_io_sq1_cq_vec_sync),
.io_sq2_cq_vec (w_io_sq2_cq_vec_sync),
.io_sq3_cq_vec (w_io_sq3_cq_vec_sync),
.io_sq4_cq_vec (w_io_sq4_cq_vec_sync),
.io_sq5_cq_vec (w_io_sq5_cq_vec_sync),
.io_sq6_cq_vec (w_io_sq6_cq_vec_sync),
.io_sq7_cq_vec (w_io_sq7_cq_vec_sync),
.io_sq8_cq_vec (w_io_sq8_cq_vec_sync),
.cq_rst_n (w_cq_rst_n_sync),
.cq_valid (w_cq_valid_sync),
.io_cq1_size (w_io_cq1_size_sync),
.io_cq2_size (w_io_cq2_size_sync),
.io_cq3_size (w_io_cq3_size_sync),
.io_cq4_size (w_io_cq4_size_sync),
.io_cq5_size (w_io_cq5_size_sync),
.io_cq6_size (w_io_cq6_size_sync),
.io_cq7_size (w_io_cq7_size_sync),
.io_cq8_size (w_io_cq8_size_sync),
.io_cq1_bs_addr (w_io_cq1_bs_addr_sync),
.io_cq2_bs_addr (w_io_cq2_bs_addr_sync),
.io_cq3_bs_addr (w_io_cq3_bs_addr_sync),
.io_cq4_bs_addr (w_io_cq4_bs_addr_sync),
.io_cq5_bs_addr (w_io_cq5_bs_addr_sync),
.io_cq6_bs_addr (w_io_cq6_bs_addr_sync),
.io_cq7_bs_addr (w_io_cq7_bs_addr_sync),
.io_cq8_bs_addr (w_io_cq8_bs_addr_sync),
.io_cq_irq_en (w_io_cq_irq_en_sync),
.io_cq1_iv (w_io_cq1_iv_sync),
.io_cq2_iv (w_io_cq2_iv_sync),
.io_cq3_iv (w_io_cq3_iv_sync),
.io_cq4_iv (w_io_cq4_iv_sync),
.io_cq5_iv (w_io_cq5_iv_sync),
.io_cq6_iv (w_io_cq6_iv_sync),
.io_cq7_iv (w_io_cq7_iv_sync),
.io_cq8_iv (w_io_cq8_iv_sync),
.hcmd_sq_rd_en (w_hcmd_sq_rd_en),
.hcmd_sq_rd_data (w_hcmd_sq_rd_data),
.hcmd_sq_empty_n (w_hcmd_sq_empty_n),
.hcmd_table_rd_addr (w_hcmd_table_rd_addr),
.hcmd_table_rd_data (w_hcmd_table_rd_data),
.hcmd_cq_wr1_en (w_hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (w_hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (w_hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (w_hcmd_cq_wr1_rdy_n),
.dma_cmd_wr_en (w_dma_cmd_wr_en),
.dma_cmd_wr_data0 (w_dma_cmd_wr_data0),
.dma_cmd_wr_data1 (w_dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (w_dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (w_dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (w_dma_tx_direct_done_cnt),
.dma_rx_done_cnt (w_dma_rx_done_cnt),
.dma_tx_done_cnt (w_dma_tx_done_cnt),
.dma_bus_clk (m0_axi_aclk),
.dma_bus_rst_n (m0_axi_aresetn),
.pcie_rx_fifo_rd_en (w_pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (w_pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (w_pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (w_pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (w_pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (w_pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (w_pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (w_pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (w_pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (w_pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (w_dma_rx_done_wr_en),
.dma_rx_done_wr_data (w_dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (w_dma_rx_done_wr_rdy_n),
.pcie_mreq_err (w_pcie_mreq_err),
.pcie_cpld_err (w_pcie_cpld_err),
.pcie_cpld_len_err (w_pcie_cpld_len_err),
.tx_buf_av (tx_buf_av),
.tx_err_drop (tx_err_drop),
.tx_cfg_req (tx_cfg_req),
.s_axis_tx_tready (s_axis_tx_tready),
.s_axis_tx_tdata (s_axis_tx_tdata),
.s_axis_tx_tkeep (s_axis_tx_tkeep),
.s_axis_tx_tuser (s_axis_tx_tuser),
.s_axis_tx_tlast (s_axis_tx_tlast),
.s_axis_tx_tvalid (s_axis_tx_tvalid),
.tx_cfg_gnt (tx_cfg_gnt),
.m_axis_rx_tdata (m_axis_rx_tdata),
.m_axis_rx_tkeep (m_axis_rx_tkeep),
.m_axis_rx_tlast (m_axis_rx_tlast),
.m_axis_rx_tvalid (m_axis_rx_tvalid),
.m_axis_rx_tready (m_axis_rx_tready),
.m_axis_rx_tuser (m_axis_rx_tuser),
.rx_np_ok (rx_np_ok),
.rx_np_req (rx_np_req),
.fc_cpld (fc_cpld),
.fc_cplh (fc_cplh),
.fc_npd (fc_npd),
.fc_nph (fc_nph),
.fc_pd (fc_pd),
.fc_ph (fc_ph),
.fc_sel (fc_sel),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.cfg_bus_number (cfg_bus_number),
.cfg_device_number (cfg_device_number),
.cfg_function_number (cfg_function_number),
.cfg_to_turnoff (cfg_to_turnoff),
.cfg_turnoff_ok (cfg_turnoff_ok),
.cfg_command (cfg_command),
.cfg_dcommand (cfg_dcommand),
.cfg_lcommand (cfg_lcommand),
.sys_clk (sys_clk)
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off GENCLK
reg printclk;
// verilator lint_on GENCLK
ps ps (printclk);
reg [7:0] a;
wire [7:0] z;
l1 u (~a,z);
always @ (posedge clk) begin
printclk <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
printclk <= 1'b1;
end
if (cyc==2) begin
a <= 8'b1;
end
if (cyc==3) begin
if (z !== 8'hf8) $stop;
//if (u.u1.u1.u1.u0.PARAM !== 1) $stop;
//if (u.u1.u1.u1.u1.PARAM !== 2) $stop;
//if (u.u0.u0.u0.u0.z !== 8'hfe) $stop;
//if (u.u0.u0.u0.u1.z !== 8'hff) $stop;
//if (u.u1.u1.u1.u0.z !== 8'h00) $stop;
//if (u.u1.u1.u1.u1.z !== 8'h01) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
`ifdef USE_PUBLIC
`define PUBLIC /*verilator public*/
`else
`define PUBLIC
`endif
module ps (input printclk);
`INLINE_MODULE
// Check that %m stays correct across inlines
always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time);
endmodule
module l1 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = z0+z1;
l2 u0 (a, z0); l2 u1 (a, z1);
endmodule
module l2 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l3 u0 (a, z0); l3 u1 (a1, z1);
endmodule
module l3 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l4 u0 (a, z0); l4 u1 (a1, z1);
endmodule
module l4 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1);
endmodule
module l5 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
parameter PARAM = 5;
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = a;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off GENCLK
reg printclk;
// verilator lint_on GENCLK
ps ps (printclk);
reg [7:0] a;
wire [7:0] z;
l1 u (~a,z);
always @ (posedge clk) begin
printclk <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
printclk <= 1'b1;
end
if (cyc==2) begin
a <= 8'b1;
end
if (cyc==3) begin
if (z !== 8'hf8) $stop;
//if (u.u1.u1.u1.u0.PARAM !== 1) $stop;
//if (u.u1.u1.u1.u1.PARAM !== 2) $stop;
//if (u.u0.u0.u0.u0.z !== 8'hfe) $stop;
//if (u.u0.u0.u0.u1.z !== 8'hff) $stop;
//if (u.u1.u1.u1.u0.z !== 8'h00) $stop;
//if (u.u1.u1.u1.u1.z !== 8'h01) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
`ifdef USE_PUBLIC
`define PUBLIC /*verilator public*/
`else
`define PUBLIC
`endif
module ps (input printclk);
`INLINE_MODULE
// Check that %m stays correct across inlines
always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time);
endmodule
module l1 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = z0+z1;
l2 u0 (a, z0); l2 u1 (a, z1);
endmodule
module l2 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l3 u0 (a, z0); l3 u1 (a1, z1);
endmodule
module l3 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l4 u0 (a, z0); l4 u1 (a1, z1);
endmodule
module l4 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1);
endmodule
module l5 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
parameter PARAM = 5;
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = a;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
// bug291
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer out18;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire out1; // From test of Test.v
wire out19; // From test of Test.v
wire out1b; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out1 (out1),
.out18 (out18),
.out1b (out1b),
.out19 (out19));
// Test loop
always @ (posedge clk) begin
if (out1 !== 1'b1) $stop;
if (out18 !== 32'h18) $stop;
if (out1b !== 1'b1) $stop;
if (out19 !== 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module Test (
output wire out1 = 1'b1,
output integer out18 = 32'h18,
output var out1b = 1'b1,
output var logic out19 = 1'b1
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
// bug291
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer out18;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire out1; // From test of Test.v
wire out19; // From test of Test.v
wire out1b; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out1 (out1),
.out18 (out18),
.out1b (out1b),
.out19 (out19));
// Test loop
always @ (posedge clk) begin
if (out1 !== 1'b1) $stop;
if (out18 !== 32'h18) $stop;
if (out1b !== 1'b1) $stop;
if (out19 !== 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module Test (
output wire out1 = 1'b1,
output integer out18 = 32'h18,
output var out1b = 1'b1,
output var logic out19 = 1'b1
);
endmodule
|
(** * PE: Partial Evaluation *)
(* Chapter author/maintainer: Chung-chieh Shan *)
(** Equiv.v introduced constant folding as an example of a program
transformation and proved that it preserves the meaning of the
program. Constant folding operates on manifest constants such
as [ANum] expressions. For example, it simplifies the command
[Y ::= APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4].
However, it does not propagate known constants along data flow.
For example, it does not simplify the sequence
X ::= ANum 3;; Y ::= APlus (AId X) (ANum 1)
to
X ::= ANum 3;; Y ::= ANum 4
because it forgets that [X] is [3] by the time it gets to [Y].
We naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is
like running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X ::= ANum 3;; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
to
X ::= ANum 3;; Y ::= AMinus (ANum 4) (AId Y)
without knowing the initial value of [Y]. *)
Require Export Imp.
Require Import FunctionalExtensionality.
(* ####################################################### *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if eq_id_dec V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
compare V V' SCase
means to reason by cases over [eq_id_dec V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) ident(c) :=
let H := fresh "Heq" i j in
destruct (eq_id_dec i j);
[ Case_aux c "equal"; subst j
| Case_aux c "not equal" ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
Case "[]". inversion H.
Case "::". simpl in H. simpl. compare V V' SCase; auto. Qed.
(** *** Aside on [In].
We will make heavy use of the [In] predicate from the standard library.
[In] is equivalent to the [appears_in] predicate introduced in Logic.v, but
defined using a [Fixpoint] rather than an [Inductive]. *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** [In] comes with various useful lemmas. *)
Check in_or_app.
(* ===> in_or_app: forall (A : Type) (l m : list A) (a : A),
In a l \/ In a m -> In a (l ++ m) *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
Check in_dec.
(* ===> in_dec : forall A : Type,
(forall x y : A, {x = y} + {x <> y}) ->
forall (a : A) (l : list A), {In a l} + {~ In a l}] *)
(** Note that we can compute with [in_dec], just as with [eq_id_dec]. *)
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
Case "AId".
remember (pe_lookup pe_st i) as l. destruct l.
SCase "Some". rewrite H with (n:=n) by apply Heql. reflexivity.
SCase "None". reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to just
Y ::= AMinus (ANum 3) (AId Y);; X ::= ANum 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to
Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_override (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => update (pe_override st pe_st) V n
end.
Example test_pe_override:
pe_override (update empty_state Y 1) [(X,3);(Z,2)]
= update (update (update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_override] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_override_correct: forall st pe_st V0,
pe_override st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold update.
compare V0 V Case; auto. rewrite eq_id; auto. rewrite neq_id; auto. Qed.
(** We can relate [pe_consistent] to [pe_override] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_override_consistent: forall st pe_st,
pe_consistent (pe_override st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_override_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_override: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_override st pe_st V.
Proof. intros st pe_st H V. rewrite pe_override_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_override st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
aexp_cases (induction a) Case; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_override_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if ble_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_override st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
bexp_cases (induction b) Case; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_override st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_override st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0); try destruct (ble_nat n n0);
reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st || c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_override] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if eq_id_dec V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if eq_id_dec V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
Case "[]". destruct (eq_id_dec V V0); reflexivity.
Case "::". simpl. compare V V' SCase.
SCase "equal". rewrite IHpe_st.
destruct (eq_id_dec V V0). reflexivity. rewrite neq_id; auto.
SCase "not equal". simpl. compare V0 V' SSCase.
SSCase "equal". rewrite neq_id; auto.
SSCase "not equal". rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if eq_id_dec V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0 Case.
Case "equal". rewrite eq_id; auto.
Case "not equal". rewrite pe_remove_correct. repeat rewrite neq_id; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_override_update_remove: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override (update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_remove_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
Theorem pe_override_update_add: forall st pe_st V n,
update (pe_override st pe_st) V n =
pe_override st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold update. rewrite !pe_override_correct. rewrite pe_add_correct.
destruct (eq_id_dec V V0); reflexivity. Qed.
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;;
SKIP;;
Y ::= ANum 4
ELSE SKIP FI
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_or_app.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l => x :: filter (fun y => if eq_id_dec x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
Case "->".
intros. inversion H; clear H.
left. assumption.
destruct (eq_id_dec h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite neq_id; auto.
Case "<-".
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
Case "->".
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
Case "<-".
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
SCase "Proof of assertion".
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
apply ex_falso_quodlibet. apply Heq. split. assumption. reflexivity.
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite negb_false_iff in Hagree.
apply beq_nat_true in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_override] only depends on the
[pe_lookup] interpretation of partial states, [pe_override] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_override] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if in_dec eq_id_dec V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V Case.
reflexivity.
destruct (in_dec eq_id_dec V ids);
reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof. intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (in_dec eq_id_dec V (pe_compare pe_st1 pe_st2)).
reflexivity.
apply pe_compare_correct. auto. Qed.
Theorem pe_compare_override: forall pe_st1 pe_st2 st,
pe_override st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_override st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids;; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => if in_dec eq_id_dec V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_override st pe_st =
pe_override (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_override_correct. rewrite pe_removes_correct. unfold assigned.
destruct (in_dec eq_id_dec V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st || st1 -> (forall V, st1 V = st2 V) -> c / st || st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st || assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
Case "[]". eapply ceval_extensionality. apply E_Skip. reflexivity.
Case "V::ids".
remember (pe_lookup pe_st V) as lookup. destruct lookup.
SCase "Some". eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold update. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup. reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); auto.
SCase "None". eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0 SSCase.
SSCase "equal". rewrite <- Heqlookup.
destruct (in_dec eq_id_dec V ids); reflexivity.
SSCase "not equal". destruct (in_dec eq_id_dec V0 ids); reflexivity. Qed.
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '||' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st || c1' / pe_st' ->
c2 / pe_st' || c2' / pe_st'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 ->
c2 / pe_st || c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '||' c1' '/' st'" := (pe_com c1 st c1' st').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If" ].
Hint Constructors pe_com.
Hint Constructors ceval.
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] || (SKIP;; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ;; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] || (SKIP;; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
|| (SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP;; SKIP);; (SKIP;; Y ::= ANum 4)
ELSE SKIP;; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '||' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st || st' ->
pe_override st' pe_st' = st'' ->
c' / pe_st' / st || st''
where "c' '/' pe_st' '/' st '||' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') ->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. reflexivity.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
reflexivity.
Case "PE_Seq".
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c' / pe_st' / st || st'') ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
Case "PE_If".
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
SCase "E_IfTrue".
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
SCase "E_IfFalse".
rewrite -> pe_compare_override.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(c' / pe_st' / st || st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". apply pe_com_complete. apply H.
Case "<-". apply pe_com_sound. apply H.
Qed.
(* ####################################################### *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y)
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking if [Y] is even or odd:
X ::= ANum 0;;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
X ::= AMinus (ANum 1) (AId X)
END
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1;; EXIT
FI
END;;
X ::= ANum 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '||' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st || SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st || SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st || (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st || c1' / pe_st' / SKIP ->
c2 / pe_st' || c2' / pe_st'' / c'' ->
(c1 ;; c2) / pe_st || (c1' ;; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st || c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st || c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st || c1' / pe_st1 / c'' ->
c2 / pe_st || c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st || (c1';;c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' || c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
|| (IFB pe_bexp pe_st b1
THEN c1';; c2';; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st || SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
|| SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st || c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
|| c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
|| (WHILE pe_bexp pe_st b1 DO c1';; c2' END) / pe_st / SKIP
where "c1 '/' st '||' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Tactic Notation "pe_com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "PE_Skip"
| Case_aux c "PE_AssStatic" | Case_aux c "PE_AssDynamic"
| Case_aux c "PE_Seq"
| Case_aux c "PE_IfTrue" | Case_aux c "PE_IfFalse" | Case_aux c "PE_If"
| Case_aux c "PE_WhileEnd" | Case_aux c "PE_WhileLoop"
| Case_aux c "PE_While" | Case_aux c "PE_WhileFixedEnd"
| Case_aux c "PE_WhileFixedLoop" | Case_aux c "PE_WhileFixed" ].
Hint Constructors pe_com.
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
|| (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1));; SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3;; square_loop) / []
|| (SKIP;;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3;; subtract_slowly) / []
|| (SKIP;;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP;; X ::= AMinus (AId X) (ANum 1));; SKIP
END;;
SKIP;; Z ::= ANum 0
ELSE SKIP;; Z ::= ANum 1 FI;; SKIP
ELSE SKIP;; Z ::= ANum 2 FI;; SKIP
ELSE SKIP;; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] || (SKIP;; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ || c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '||' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st || st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st || (update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st || st' # n1 ->
c2 / st' || st'' # n2 ->
(c1 ;; c2) / st || st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st || st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st || st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st || st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st || st' # n1 ->
(WHILE b1 DO c1 END) / st' || st'' # n2 ->
(WHILE b1 DO c1 END) / st || st'' # S (n1 + n2)
where "c1 '/' st '||' st' # n" := (ceval_count c1 st st' n).
Tactic Notation "ceval_count_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E'Skip" | Case_aux c "E'Ass" | Case_aux c "E'Seq"
| Case_aux c "E'IfTrue" | Case_aux c "E'IfFalse"
| Case_aux c "E'WhileEnd" | Case_aux c "E'WhileLoop" ].
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st || st' -> exists n, c / st || st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st || st' # n -> c / st || st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_override: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_override st pe_st1 = pe_override st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_override_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st || st' ->
c'' / pe_override st' pe_st' || st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st || st'' # n
where "c' '/' pe_st' '/' c'' '/' st '||' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st || st'' # n' ->
c' / pe_st' / c'' / st || st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_override st pe_st || st'' # n) ->
(c' / pe_st' / c'' / st || st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
Case "PE_AssStatic". econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_add.
rewrite -> H. apply E'Skip. auto.
Case "PE_AssDynamic". econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_override_update_remove.
apply E'Skip. auto.
Case "PE_Seq".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_If". inversion Heval; subst.
SCase "E'IfTrue". edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
SCase "E_IfFalse". edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_override.
rewrite <- assign_removes. eassumption. eassumption.
Case "PE_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
Case "PE_While". inversion Heval; subst.
SCase "E_WhileEnd". econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
SCase "E_WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_override, <- assign_removes. eassumption.
omega.
Case "PE_WhileFixedLoop". apply ex_falso_quodlibet.
generalize dependent (S (n1 + n2)). intros n.
clear - Case H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct, H in H7. inversion H7.
SCase "E'WhileLoop".
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
Case "PE_WhileFixed". generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
SCase "E'WhileEnd". rewrite pe_bexp_correct in H8. eauto.
SCase "E'WhileLoop". rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st || c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st || st'' # n) ->
(c / pe_override st pe_st || st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
pe_com_cases (induction Hpe) Case;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
Case "PE_AssStatic". rewrite <- pe_override_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
Case "PE_AssDynamic". rewrite <- pe_override_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
Case "PE_Seq". eapply E_Seq; eauto.
Case "PE_IfTrue". apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_IfFalse". apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
Case "PE_If". inversion Heval; subst; inversion H7; subst; clear H7.
SCase "E_IfTrue".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
SCase "E_IfFalse".
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
Case "PE_WhileEnd". apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
Case "PE_WhileLoop". eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
Case "PE_While". inversion Heval; subst.
SCase "E_IfTrue".
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_override in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
SCase "E_IfFalse". apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
SSCase "c2'' = SKIP". inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
SSCase "c2'' = WHILE b1 DO c1 END". assumption.
Case "PE_WhileFixedEnd". eapply ceval_count_sound. apply Heval'.
Case "PE_WhileFixedLoop".
apply loop_never_stops in Heval. inversion Heval.
Case "PE_WhileFixed".
clear - Case H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1';; c2' END) as c'.
ceval_cases (induction Heval) SCase;
inversion Heqc'; subst; clear Heqc'.
SCase "E_WhileEnd". apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
SCase "E_WhileLoop".
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_override _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st || c' / pe_st' / SKIP ->
forall st st'',
(c / pe_override st pe_st || st'') <->
(exists st', c' / st || st' /\ pe_override st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
Case "->". intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
Case "<-". intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ####################################################### *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Tactic Notation "block_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Goto" | Case_aux c "If" | Case_aux c "Assign" ].
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (update (update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite update_same; auto.
Qed.
Tactic Notation "peval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_None" | Case_aux c "E_Some" ].
(** ** Partial evaluation of basic blocks and flowchart programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_override st pe_st) k = (pe_override st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
block_cases (induction k as [l | b l1 l2 | i a k]) Case;
intros st pe_st H.
Case "Goto". inversion H; reflexivity.
Case "If".
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
Case "Assign".
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_override_update_add; apply IHk; apply H];
solve [rewrite pe_override_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_override st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_override st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split; [Case "->" | Case "<-"].
Case "->". intros Heval.
remember (pe_override st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
peval_cases (induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ])
SCase; intros st pe_st Heqsto; subst sto.
SCase "E_None". eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
SCase "E_Some".
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
Case "<-". intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
peval_cases (induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ])
SCase; intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
SCase "E_None". apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
SCase "E_Some".
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_dma_cmd_gen # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output pcie_cmd_rd_en,
input [33:0] pcie_cmd_rd_data,
input pcie_cmd_empty_n,
output prp_fifo_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] prp_fifo_rd_data,
output prp_fifo_free_en,
output [5:4] prp_fifo_free_len,
input prp_fifo_empty_n,
output pcie_rx_cmd_wr_en,
output [33:0] pcie_rx_cmd_wr_data,
input pcie_rx_cmd_full_n,
output pcie_tx_cmd_wr_en,
output [33:0] pcie_tx_cmd_wr_data,
input pcie_tx_cmd_full_n
);
localparam S_IDLE = 15'b000000000000001;
localparam S_CMD0 = 15'b000000000000010;
localparam S_CMD1 = 15'b000000000000100;
localparam S_CMD2 = 15'b000000000001000;
localparam S_CMD3 = 15'b000000000010000;
localparam S_CHECK_PRP_FIFO = 15'b000000000100000;
localparam S_RD_PRP0 = 15'b000000001000000;
localparam S_RD_PRP1 = 15'b000000010000000;
localparam S_PCIE_PRP = 15'b000000100000000;
localparam S_CHECK_PCIE_CMD_FIFO0 = 15'b000001000000000;
localparam S_PCIE_CMD0 = 15'b000010000000000;
localparam S_PCIE_CMD1 = 15'b000100000000000;
localparam S_CHECK_PCIE_CMD_FIFO1 = 15'b001000000000000;
localparam S_PCIE_CMD2 = 15'b010000000000000;
localparam S_PCIE_CMD3 = 15'b100000000000000;
reg [14:0] cur_state;
reg [14:0] next_state;
reg r_dma_cmd_type;
reg r_dma_cmd_dir;
reg r_2st_valid;
reg r_1st_mrd_need;
reg r_2st_mrd_need;
reg [6:0] r_hcmd_slot_tag;
reg r_pcie_rcb_cross;
reg [12:2] r_1st_4b_len;
reg [12:2] r_2st_4b_len;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_1;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_2;
reg [63:2] r_prp_1;
reg [63:2] r_prp_2;
reg r_pcie_cmd_rd_en;
reg r_prp_fifo_rd_en;
reg r_prp_fifo_free_en;
reg r_pcie_rx_cmd_wr_en;
reg r_pcie_tx_cmd_wr_en;
reg [3:0] r_pcie_cmd_wr_data_sel;
reg [33:0] r_pcie_cmd_wr_data;
wire w_pcie_cmd_full_n;
assign pcie_cmd_rd_en = r_pcie_cmd_rd_en;
assign prp_fifo_rd_en = r_prp_fifo_rd_en;
assign prp_fifo_free_en = r_prp_fifo_free_en;
assign prp_fifo_free_len = (r_pcie_rcb_cross == 0) ? 2'b01 : 2'b10;
assign pcie_rx_cmd_wr_en = r_pcie_rx_cmd_wr_en;
assign pcie_rx_cmd_wr_data = r_pcie_cmd_wr_data;
assign pcie_tx_cmd_wr_en = r_pcie_tx_cmd_wr_en;
assign pcie_tx_cmd_wr_data = r_pcie_cmd_wr_data;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
assign w_pcie_cmd_full_n = (r_dma_cmd_dir == 1'b1) ? pcie_tx_cmd_full_n : pcie_rx_cmd_full_n;
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(pcie_cmd_empty_n == 1'b1)
next_state <= S_CMD0;
else
next_state <= S_IDLE;
end
S_CMD0: begin
next_state <= S_CMD1;
end
S_CMD1: begin
next_state <= S_CMD2;
end
S_CMD2: begin
next_state <= S_CMD3;
end
S_CMD3: begin
if((r_1st_mrd_need | (r_2st_valid & r_2st_mrd_need)) == 1'b1)
next_state <= S_CHECK_PRP_FIFO;
else
next_state <= S_CHECK_PCIE_CMD_FIFO0;
end
S_CHECK_PRP_FIFO: begin
if(prp_fifo_empty_n == 1)
next_state <= S_RD_PRP0;
else
next_state <= S_CHECK_PRP_FIFO;
end
S_RD_PRP0: begin
if(r_pcie_rcb_cross == 1)
next_state <= S_RD_PRP1;
else
next_state <= S_PCIE_PRP;
end
S_RD_PRP1: begin
next_state <= S_PCIE_PRP;
end
S_PCIE_PRP: begin
next_state <= S_CHECK_PCIE_CMD_FIFO0;
end
S_CHECK_PCIE_CMD_FIFO0: begin
if(w_pcie_cmd_full_n == 1'b1)
next_state <= S_PCIE_CMD0;
else
next_state <= S_CHECK_PCIE_CMD_FIFO0;
end
S_PCIE_CMD0: begin
next_state <= S_PCIE_CMD1;
end
S_PCIE_CMD1: begin
if(r_2st_valid == 1'b1)
next_state <= S_CHECK_PCIE_CMD_FIFO1;
else
next_state <= S_IDLE;
end
S_CHECK_PCIE_CMD_FIFO1: begin
if(w_pcie_cmd_full_n == 1'b1)
next_state <= S_PCIE_CMD2;
else
next_state <= S_CHECK_PCIE_CMD_FIFO1;
end
S_PCIE_CMD2: begin
next_state <= S_PCIE_CMD3;
end
S_PCIE_CMD3: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CMD0: begin
r_dma_cmd_type <= pcie_cmd_rd_data[11];
r_dma_cmd_dir <= pcie_cmd_rd_data[10];
r_2st_valid <= pcie_cmd_rd_data[9];
r_1st_mrd_need <= pcie_cmd_rd_data[8];
r_2st_mrd_need <= pcie_cmd_rd_data[7];
r_hcmd_slot_tag <= pcie_cmd_rd_data[6:0];
end
S_CMD1: begin
r_pcie_rcb_cross <= pcie_cmd_rd_data[22];
r_1st_4b_len <= pcie_cmd_rd_data[21:11];
r_2st_4b_len <= pcie_cmd_rd_data[10:0];
end
S_CMD2: begin
r_hcmd_prp_1 <= pcie_cmd_rd_data[33:0];
end
S_CMD3: begin
r_hcmd_prp_2 <= {pcie_cmd_rd_data[33:10], 10'b0};
end
S_CHECK_PRP_FIFO: begin
end
S_RD_PRP0: begin
r_prp_1 <= prp_fifo_rd_data[63:2];
r_prp_2 <= prp_fifo_rd_data[127:66];
end
S_RD_PRP1: begin
r_prp_2 <= prp_fifo_rd_data[63:2];
end
S_PCIE_PRP: begin
if(r_1st_mrd_need == 1) begin
r_hcmd_prp_1[C_PCIE_ADDR_WIDTH-1:12] <= r_prp_1[C_PCIE_ADDR_WIDTH-1:12];
r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12] <= r_prp_2[C_PCIE_ADDR_WIDTH-1:12];
end
else begin
r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12] <= r_prp_1[C_PCIE_ADDR_WIDTH-1:12];
end
end
S_CHECK_PCIE_CMD_FIFO0: begin
end
S_PCIE_CMD0: begin
end
S_PCIE_CMD1: begin
end
S_CHECK_PCIE_CMD_FIFO1: begin
end
S_PCIE_CMD2: begin
end
S_PCIE_CMD3: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(r_pcie_cmd_wr_data_sel) // synthesis parallel_case full_case
4'b0001: r_pcie_cmd_wr_data <= {14'b0, r_dma_cmd_type, ~r_2st_valid, r_hcmd_slot_tag, r_1st_4b_len};
4'b0010: r_pcie_cmd_wr_data <= r_hcmd_prp_1;
4'b0100: r_pcie_cmd_wr_data <= {14'b0, r_dma_cmd_type, 1'b1, r_hcmd_slot_tag, r_2st_4b_len};
4'b1000: r_pcie_cmd_wr_data <= {r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12], 10'b0};
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CMD0: begin
r_pcie_cmd_rd_en <= 1;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CMD1: begin
r_pcie_cmd_rd_en <= 1;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CMD2: begin
r_pcie_cmd_rd_en <= 1;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CMD3: begin
r_pcie_cmd_rd_en <= 1;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CHECK_PRP_FIFO: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_RD_PRP0: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 1;
r_prp_fifo_free_en <= 1;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_RD_PRP1: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 1;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_PCIE_PRP: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_CHECK_PCIE_CMD_FIFO0: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_PCIE_CMD0: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_pcie_tx_cmd_wr_en <= r_dma_cmd_dir;
r_pcie_cmd_wr_data_sel <= 4'b0001;
end
S_PCIE_CMD1: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_pcie_tx_cmd_wr_en <= r_dma_cmd_dir;
r_pcie_cmd_wr_data_sel <= 4'b0010;
end
S_CHECK_PCIE_CMD_FIFO1: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
S_PCIE_CMD2: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_pcie_tx_cmd_wr_en <= r_dma_cmd_dir;
r_pcie_cmd_wr_data_sel <= 4'b0100;
end
S_PCIE_CMD3: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_pcie_tx_cmd_wr_en <= r_dma_cmd_dir;
r_pcie_cmd_wr_data_sel <= 4'b1000;
end
default: begin
r_pcie_cmd_rd_en <= 0;
r_prp_fifo_rd_en <= 0;
r_prp_fifo_free_en <= 0;
r_pcie_rx_cmd_wr_en <= 0;
r_pcie_tx_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0000;
end
endcase
end
endmodule |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Interface to Cypress FX2 bus
// A packet is 512 Bytes. Each fifo line is 2 bytes
// Fifo has 1024 or 2048 lines
module tx_buffer
( input usbclk,
input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
input reset, // standard DSP-side reset
input [15:0] usbdata,
input wire WR,
output wire have_space,
output reg tx_underrun,
input wire [3:0] channels,
output reg [15:0] tx_i_0,
output reg [15:0] tx_q_0,
output reg [15:0] tx_i_1,
output reg [15:0] tx_q_1,
output reg [15:0] tx_i_2,
output reg [15:0] tx_q_2,
output reg [15:0] tx_i_3,
output reg [15:0] tx_q_3,
input txclk,
input txstrobe,
input clear_status,
output wire tx_empty,
output [11:0] debugbus
);
wire [11:0] txfifolevel;
reg [8:0] write_count;
wire tx_full;
wire [15:0] fifodata;
wire rdreq;
reg [3:0] load_next;
// DAC Side of FIFO
assign rdreq = ((load_next != channels) & !tx_empty);
always @(posedge txclk)
if(reset)
begin
{tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
<= #1 128'h0;
load_next <= #1 4'd0;
end
else
if(load_next != channels)
begin
load_next <= #1 load_next + 4'd1;
case(load_next)
4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
endcase // case(load_next)
end // if (load_next != channels)
else if(txstrobe & (load_next == channels))
begin
load_next <= #1 4'd0;
end
// USB Side of FIFO
assign have_space = (txfifolevel <= (4095-256));
always @(posedge usbclk)
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR ? write_count : 9'b0;
// Detect Underruns
always @(posedge txclk)
if(reset)
tx_underrun <= 1'b0;
else if(txstrobe & (load_next != channels))
tx_underrun <= 1'b1;
else if(clear_status)
tx_underrun <= 1'b0;
// FIFO
fifo_4k txfifo
( .data ( usbdata ),
.wrreq ( WR & ~write_count[8] ),
.wrclk ( usbclk ),
.q ( fifodata ),
.rdreq ( rdreq ),
.rdclk ( txclk ),
.aclr ( reset ), // asynch, so we can use either
.rdempty ( tx_empty ),
.rdusedw ( ),
.wrfull ( tx_full ),
.wrusedw ( txfifolevel )
);
// Debugging Aids
assign debugbus[0] = WR;
assign debugbus[1] = have_space;
assign debugbus[2] = tx_empty;
assign debugbus[3] = tx_full;
assign debugbus[4] = tx_underrun;
assign debugbus[5] = write_count[8];
assign debugbus[6] = txstrobe;
assign debugbus[7] = rdreq;
assign debugbus[11:8] = load_next;
endmodule // tx_buffer
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Interface to Cypress FX2 bus
// A packet is 512 Bytes. Each fifo line is 2 bytes
// Fifo has 1024 or 2048 lines
module tx_buffer
( input usbclk,
input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
input reset, // standard DSP-side reset
input [15:0] usbdata,
input wire WR,
output wire have_space,
output reg tx_underrun,
input wire [3:0] channels,
output reg [15:0] tx_i_0,
output reg [15:0] tx_q_0,
output reg [15:0] tx_i_1,
output reg [15:0] tx_q_1,
output reg [15:0] tx_i_2,
output reg [15:0] tx_q_2,
output reg [15:0] tx_i_3,
output reg [15:0] tx_q_3,
input txclk,
input txstrobe,
input clear_status,
output wire tx_empty,
output [11:0] debugbus
);
wire [11:0] txfifolevel;
reg [8:0] write_count;
wire tx_full;
wire [15:0] fifodata;
wire rdreq;
reg [3:0] load_next;
// DAC Side of FIFO
assign rdreq = ((load_next != channels) & !tx_empty);
always @(posedge txclk)
if(reset)
begin
{tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
<= #1 128'h0;
load_next <= #1 4'd0;
end
else
if(load_next != channels)
begin
load_next <= #1 load_next + 4'd1;
case(load_next)
4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
endcase // case(load_next)
end // if (load_next != channels)
else if(txstrobe & (load_next == channels))
begin
load_next <= #1 4'd0;
end
// USB Side of FIFO
assign have_space = (txfifolevel <= (4095-256));
always @(posedge usbclk)
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR ? write_count : 9'b0;
// Detect Underruns
always @(posedge txclk)
if(reset)
tx_underrun <= 1'b0;
else if(txstrobe & (load_next != channels))
tx_underrun <= 1'b1;
else if(clear_status)
tx_underrun <= 1'b0;
// FIFO
fifo_4k txfifo
( .data ( usbdata ),
.wrreq ( WR & ~write_count[8] ),
.wrclk ( usbclk ),
.q ( fifodata ),
.rdreq ( rdreq ),
.rdclk ( txclk ),
.aclr ( reset ), // asynch, so we can use either
.rdempty ( tx_empty ),
.rdusedw ( ),
.wrfull ( tx_full ),
.wrusedw ( txfifolevel )
);
// Debugging Aids
assign debugbus[0] = WR;
assign debugbus[1] = have_space;
assign debugbus[2] = tx_empty;
assign debugbus[3] = tx_full;
assign debugbus[4] = tx_underrun;
assign debugbus[5] = write_count[8];
assign debugbus[6] = txstrobe;
assign debugbus[7] = rdreq;
assign debugbus[11:8] = load_next;
endmodule // tx_buffer
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Interface to Cypress FX2 bus
// A packet is 512 Bytes. Each fifo line is 2 bytes
// Fifo has 1024 or 2048 lines
module tx_buffer
( input usbclk,
input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
input reset, // standard DSP-side reset
input [15:0] usbdata,
input wire WR,
output wire have_space,
output reg tx_underrun,
input wire [3:0] channels,
output reg [15:0] tx_i_0,
output reg [15:0] tx_q_0,
output reg [15:0] tx_i_1,
output reg [15:0] tx_q_1,
output reg [15:0] tx_i_2,
output reg [15:0] tx_q_2,
output reg [15:0] tx_i_3,
output reg [15:0] tx_q_3,
input txclk,
input txstrobe,
input clear_status,
output wire tx_empty,
output [11:0] debugbus
);
wire [11:0] txfifolevel;
reg [8:0] write_count;
wire tx_full;
wire [15:0] fifodata;
wire rdreq;
reg [3:0] load_next;
// DAC Side of FIFO
assign rdreq = ((load_next != channels) & !tx_empty);
always @(posedge txclk)
if(reset)
begin
{tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
<= #1 128'h0;
load_next <= #1 4'd0;
end
else
if(load_next != channels)
begin
load_next <= #1 load_next + 4'd1;
case(load_next)
4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
endcase // case(load_next)
end // if (load_next != channels)
else if(txstrobe & (load_next == channels))
begin
load_next <= #1 4'd0;
end
// USB Side of FIFO
assign have_space = (txfifolevel <= (4095-256));
always @(posedge usbclk)
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR ? write_count : 9'b0;
// Detect Underruns
always @(posedge txclk)
if(reset)
tx_underrun <= 1'b0;
else if(txstrobe & (load_next != channels))
tx_underrun <= 1'b1;
else if(clear_status)
tx_underrun <= 1'b0;
// FIFO
fifo_4k txfifo
( .data ( usbdata ),
.wrreq ( WR & ~write_count[8] ),
.wrclk ( usbclk ),
.q ( fifodata ),
.rdreq ( rdreq ),
.rdclk ( txclk ),
.aclr ( reset ), // asynch, so we can use either
.rdempty ( tx_empty ),
.rdusedw ( ),
.wrfull ( tx_full ),
.wrusedw ( txfifolevel )
);
// Debugging Aids
assign debugbus[0] = WR;
assign debugbus[1] = have_space;
assign debugbus[2] = tx_empty;
assign debugbus[3] = tx_full;
assign debugbus[4] = tx_underrun;
assign debugbus[5] = write_count[8];
assign debugbus[6] = txstrobe;
assign debugbus[7] = rdreq;
assign debugbus[11:8] = load_next;
endmodule // tx_buffer
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Interface to Cypress FX2 bus
// A packet is 512 Bytes. Each fifo line is 2 bytes
// Fifo has 1024 or 2048 lines
module tx_buffer
( input usbclk,
input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
input reset, // standard DSP-side reset
input [15:0] usbdata,
input wire WR,
output wire have_space,
output reg tx_underrun,
input wire [3:0] channels,
output reg [15:0] tx_i_0,
output reg [15:0] tx_q_0,
output reg [15:0] tx_i_1,
output reg [15:0] tx_q_1,
output reg [15:0] tx_i_2,
output reg [15:0] tx_q_2,
output reg [15:0] tx_i_3,
output reg [15:0] tx_q_3,
input txclk,
input txstrobe,
input clear_status,
output wire tx_empty,
output [11:0] debugbus
);
wire [11:0] txfifolevel;
reg [8:0] write_count;
wire tx_full;
wire [15:0] fifodata;
wire rdreq;
reg [3:0] load_next;
// DAC Side of FIFO
assign rdreq = ((load_next != channels) & !tx_empty);
always @(posedge txclk)
if(reset)
begin
{tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
<= #1 128'h0;
load_next <= #1 4'd0;
end
else
if(load_next != channels)
begin
load_next <= #1 load_next + 4'd1;
case(load_next)
4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
endcase // case(load_next)
end // if (load_next != channels)
else if(txstrobe & (load_next == channels))
begin
load_next <= #1 4'd0;
end
// USB Side of FIFO
assign have_space = (txfifolevel <= (4095-256));
always @(posedge usbclk)
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR ? write_count : 9'b0;
// Detect Underruns
always @(posedge txclk)
if(reset)
tx_underrun <= 1'b0;
else if(txstrobe & (load_next != channels))
tx_underrun <= 1'b1;
else if(clear_status)
tx_underrun <= 1'b0;
// FIFO
fifo_4k txfifo
( .data ( usbdata ),
.wrreq ( WR & ~write_count[8] ),
.wrclk ( usbclk ),
.q ( fifodata ),
.rdreq ( rdreq ),
.rdclk ( txclk ),
.aclr ( reset ), // asynch, so we can use either
.rdempty ( tx_empty ),
.rdusedw ( ),
.wrfull ( tx_full ),
.wrusedw ( txfifolevel )
);
// Debugging Aids
assign debugbus[0] = WR;
assign debugbus[1] = have_space;
assign debugbus[2] = tx_empty;
assign debugbus[3] = tx_full;
assign debugbus[4] = tx_underrun;
assign debugbus[5] = write_count[8];
assign debugbus[6] = txstrobe;
assign debugbus[7] = rdreq;
assign debugbus[11:8] = load_next;
endmodule // tx_buffer
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Interface to Cypress FX2 bus
// A packet is 512 Bytes. Each fifo line is 2 bytes
// Fifo has 1024 or 2048 lines
module tx_buffer
( input usbclk,
input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
input reset, // standard DSP-side reset
input [15:0] usbdata,
input wire WR,
output wire have_space,
output reg tx_underrun,
input wire [3:0] channels,
output reg [15:0] tx_i_0,
output reg [15:0] tx_q_0,
output reg [15:0] tx_i_1,
output reg [15:0] tx_q_1,
output reg [15:0] tx_i_2,
output reg [15:0] tx_q_2,
output reg [15:0] tx_i_3,
output reg [15:0] tx_q_3,
input txclk,
input txstrobe,
input clear_status,
output wire tx_empty,
output [11:0] debugbus
);
wire [11:0] txfifolevel;
reg [8:0] write_count;
wire tx_full;
wire [15:0] fifodata;
wire rdreq;
reg [3:0] load_next;
// DAC Side of FIFO
assign rdreq = ((load_next != channels) & !tx_empty);
always @(posedge txclk)
if(reset)
begin
{tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
<= #1 128'h0;
load_next <= #1 4'd0;
end
else
if(load_next != channels)
begin
load_next <= #1 load_next + 4'd1;
case(load_next)
4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
endcase // case(load_next)
end // if (load_next != channels)
else if(txstrobe & (load_next == channels))
begin
load_next <= #1 4'd0;
end
// USB Side of FIFO
assign have_space = (txfifolevel <= (4095-256));
always @(posedge usbclk)
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR ? write_count : 9'b0;
// Detect Underruns
always @(posedge txclk)
if(reset)
tx_underrun <= 1'b0;
else if(txstrobe & (load_next != channels))
tx_underrun <= 1'b1;
else if(clear_status)
tx_underrun <= 1'b0;
// FIFO
fifo_4k txfifo
( .data ( usbdata ),
.wrreq ( WR & ~write_count[8] ),
.wrclk ( usbclk ),
.q ( fifodata ),
.rdreq ( rdreq ),
.rdclk ( txclk ),
.aclr ( reset ), // asynch, so we can use either
.rdempty ( tx_empty ),
.rdusedw ( ),
.wrfull ( tx_full ),
.wrusedw ( txfifolevel )
);
// Debugging Aids
assign debugbus[0] = WR;
assign debugbus[1] = have_space;
assign debugbus[2] = tx_empty;
assign debugbus[3] = tx_full;
assign debugbus[4] = tx_underrun;
assign debugbus[5] = write_count[8];
assign debugbus[6] = txstrobe;
assign debugbus[7] = rdreq;
assign debugbus[11:8] = load_next;
endmodule // tx_buffer
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_cpld_sel# (
parameter C_PCIE_DATA_WIDTH = 128
)
(
input pcie_user_clk,
input cpld_fifo_wr_en,
input [C_PCIE_DATA_WIDTH-1:0] cpld_fifo_wr_data,
input [7:0] cpld_fifo_tag,
input cpld_fifo_tag_last,
output [7:0] cpld0_fifo_tag,
output cpld0_fifo_tag_last,
output cpld0_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld0_fifo_wr_data,
output [7:0] cpld1_fifo_tag,
output cpld1_fifo_tag_last,
output cpld1_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld1_fifo_wr_data,
output [7:0] cpld2_fifo_tag,
output cpld2_fifo_tag_last,
output cpld2_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld2_fifo_wr_data
);
reg [7:0] r_cpld_fifo_tag;
reg [C_PCIE_DATA_WIDTH-1:0] r_cpld_fifo_wr_data;
reg r_cpld0_fifo_tag_last;
reg r_cpld0_fifo_wr_en;
reg r_cpld1_fifo_tag_last;
reg r_cpld1_fifo_wr_en;
reg r_cpld2_fifo_tag_last;
reg r_cpld2_fifo_wr_en;
wire [2:0] w_cpld_prefix_tag_hit;
assign w_cpld_prefix_tag_hit[0] = (cpld_fifo_tag[7:3] == 5'b00000);
assign w_cpld_prefix_tag_hit[1] = (cpld_fifo_tag[7:3] == 5'b00001);
assign w_cpld_prefix_tag_hit[2] = (cpld_fifo_tag[7:4] == 4'b0001);
assign cpld0_fifo_tag = r_cpld_fifo_tag;
assign cpld0_fifo_tag_last = r_cpld0_fifo_tag_last;
assign cpld0_fifo_wr_en = r_cpld0_fifo_wr_en;
assign cpld0_fifo_wr_data = r_cpld_fifo_wr_data;
assign cpld1_fifo_tag = r_cpld_fifo_tag;
assign cpld1_fifo_tag_last = r_cpld1_fifo_tag_last;
assign cpld1_fifo_wr_en = r_cpld1_fifo_wr_en;
assign cpld1_fifo_wr_data = r_cpld_fifo_wr_data;
assign cpld2_fifo_tag = r_cpld_fifo_tag;
assign cpld2_fifo_tag_last = r_cpld2_fifo_tag_last;
assign cpld2_fifo_wr_en = r_cpld2_fifo_wr_en;
assign cpld2_fifo_wr_data = r_cpld_fifo_wr_data;
always @(posedge pcie_user_clk)
begin
r_cpld_fifo_tag <= cpld_fifo_tag;
r_cpld_fifo_wr_data <= cpld_fifo_wr_data;
r_cpld0_fifo_tag_last = cpld_fifo_tag_last & w_cpld_prefix_tag_hit[0];
r_cpld0_fifo_wr_en <= cpld_fifo_wr_en & w_cpld_prefix_tag_hit[0];
r_cpld1_fifo_tag_last = cpld_fifo_tag_last & w_cpld_prefix_tag_hit[1];
r_cpld1_fifo_wr_en <= cpld_fifo_wr_en & w_cpld_prefix_tag_hit[1];
r_cpld2_fifo_tag_last = cpld_fifo_tag_last & w_cpld_prefix_tag_hit[2];
r_cpld2_fifo_wr_en <= cpld_fifo_wr_en & w_cpld_prefix_tag_hit[2];
end
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [223:0] sum;
wire [255:0] mglehy = {32{~crc}};
wire [215:0] drricx = {27{crc}};
wire [15:0] apqrli = {2{~crc}};
wire [2:0] szlfpf = crc[2:0];
wire [15:0] dzosui = {2{crc}};
wire [31:0] zndrba = {16{crc[1:0]}};
wire [223:0] bxiouf;
vliw vliw (
// Outputs
.bxiouf (bxiouf),
// Inputs
.mglehy (mglehy[255:0]),
.drricx (drricx[215:0]),
.apqrli (apqrli[15:0]),
.szlfpf (szlfpf[2:0]),
.dzosui (dzosui[15:0]),
.zndrba (zndrba[31:0]));
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
sum <= 224'h0;
end
else if (cyc<90) begin
//$write("[%0t] cyc==%0d BXI=%x\n",$time, cyc, bxiouf);
sum <= {sum[222:0],sum[223]} ^ bxiouf;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
if (crc !== 8'b01110000) $stop;
if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module vliw (
input[255:0] mglehy,
input[215:0] drricx,
input[15:0] apqrli,
input[2:0] szlfpf,
input[15:0] dzosui,
input[31:0] zndrba,
output [223:0] bxiouf
);
wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]})
| ({29{apqrli}} & {mglehy[247:0], drricx});
wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128])
| ({21{dzosui}} & zhknfc[335:0]);
wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000};
wire [223:0] rzyeut = viuvoc[335:112];
wire [223:0] bxiouf = {rzyeut[7:0],
rzyeut[15:8],
rzyeut[23:16],
rzyeut[31:24],
rzyeut[39:32],
rzyeut[47:40],
rzyeut[55:48],
rzyeut[63:56],
rzyeut[71:64],
rzyeut[79:72],
rzyeut[87:80],
rzyeut[95:88],
rzyeut[103:96],
rzyeut[111:104],
rzyeut[119:112],
rzyeut[127:120],
rzyeut[135:128],
rzyeut[143:136],
rzyeut[151:144],
rzyeut[159:152],
rzyeut[167:160],
rzyeut[175:168],
rzyeut[183:176],
rzyeut[191:184],
rzyeut[199:192],
rzyeut[207:200],
rzyeut[215:208],
rzyeut[223:216]};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [223:0] sum;
wire [255:0] mglehy = {32{~crc}};
wire [215:0] drricx = {27{crc}};
wire [15:0] apqrli = {2{~crc}};
wire [2:0] szlfpf = crc[2:0];
wire [15:0] dzosui = {2{crc}};
wire [31:0] zndrba = {16{crc[1:0]}};
wire [223:0] bxiouf;
vliw vliw (
// Outputs
.bxiouf (bxiouf),
// Inputs
.mglehy (mglehy[255:0]),
.drricx (drricx[215:0]),
.apqrli (apqrli[15:0]),
.szlfpf (szlfpf[2:0]),
.dzosui (dzosui[15:0]),
.zndrba (zndrba[31:0]));
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
sum <= 224'h0;
end
else if (cyc<90) begin
//$write("[%0t] cyc==%0d BXI=%x\n",$time, cyc, bxiouf);
sum <= {sum[222:0],sum[223]} ^ bxiouf;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
if (crc !== 8'b01110000) $stop;
if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module vliw (
input[255:0] mglehy,
input[215:0] drricx,
input[15:0] apqrli,
input[2:0] szlfpf,
input[15:0] dzosui,
input[31:0] zndrba,
output [223:0] bxiouf
);
wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]})
| ({29{apqrli}} & {mglehy[247:0], drricx});
wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128])
| ({21{dzosui}} & zhknfc[335:0]);
wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000};
wire [223:0] rzyeut = viuvoc[335:112];
wire [223:0] bxiouf = {rzyeut[7:0],
rzyeut[15:8],
rzyeut[23:16],
rzyeut[31:24],
rzyeut[39:32],
rzyeut[47:40],
rzyeut[55:48],
rzyeut[63:56],
rzyeut[71:64],
rzyeut[79:72],
rzyeut[87:80],
rzyeut[95:88],
rzyeut[103:96],
rzyeut[111:104],
rzyeut[119:112],
rzyeut[127:120],
rzyeut[135:128],
rzyeut[143:136],
rzyeut[151:144],
rzyeut[159:152],
rzyeut[167:160],
rzyeut[175:168],
rzyeut[183:176],
rzyeut[191:184],
rzyeut[199:192],
rzyeut[207:200],
rzyeut[215:208],
rzyeut[223:216]};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [7:0] crc;
reg [223:0] sum;
wire [255:0] mglehy = {32{~crc}};
wire [215:0] drricx = {27{crc}};
wire [15:0] apqrli = {2{~crc}};
wire [2:0] szlfpf = crc[2:0];
wire [15:0] dzosui = {2{crc}};
wire [31:0] zndrba = {16{crc[1:0]}};
wire [223:0] bxiouf;
vliw vliw (
// Outputs
.bxiouf (bxiouf),
// Inputs
.mglehy (mglehy[255:0]),
.drricx (drricx[215:0]),
.apqrli (apqrli[15:0]),
.szlfpf (szlfpf[2:0]),
.dzosui (dzosui[15:0]),
.zndrba (zndrba[31:0]));
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==0) begin
// Setup
crc <= 8'hed;
sum <= 224'h0;
end
else if (cyc<90) begin
//$write("[%0t] cyc==%0d BXI=%x\n",$time, cyc, bxiouf);
sum <= {sum[222:0],sum[223]} ^ bxiouf;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b %x\n",$time, cyc, crc, sum);
if (crc !== 8'b01110000) $stop;
if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module vliw (
input[255:0] mglehy,
input[215:0] drricx,
input[15:0] apqrli,
input[2:0] szlfpf,
input[15:0] dzosui,
input[31:0] zndrba,
output [223:0] bxiouf
);
wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]})
| ({29{apqrli}} & {mglehy[247:0], drricx});
wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128])
| ({21{dzosui}} & zhknfc[335:0]);
wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000};
wire [223:0] rzyeut = viuvoc[335:112];
wire [223:0] bxiouf = {rzyeut[7:0],
rzyeut[15:8],
rzyeut[23:16],
rzyeut[31:24],
rzyeut[39:32],
rzyeut[47:40],
rzyeut[55:48],
rzyeut[63:56],
rzyeut[71:64],
rzyeut[79:72],
rzyeut[87:80],
rzyeut[95:88],
rzyeut[103:96],
rzyeut[111:104],
rzyeut[119:112],
rzyeut[127:120],
rzyeut[135:128],
rzyeut[143:136],
rzyeut[151:144],
rzyeut[159:152],
rzyeut[167:160],
rzyeut[175:168],
rzyeut[183:176],
rzyeut[191:184],
rzyeut[199:192],
rzyeut[207:200],
rzyeut[215:208],
rzyeut[223:216]};
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] pcie_dev_id,
output tx_err_drop,
input tx_cpld_gnt,
input tx_mrd_gnt,
input tx_mwr_gnt,
//pcie tx signal
input m_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] m_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_tx_tkeep,
output [3:0] m_axis_tx_tuser,
output m_axis_tx_tlast,
output m_axis_tx_tvalid,
input tx_cpld_req,
input [7:0] tx_cpld_tag,
input [15:0] tx_cpld_req_id,
input [11:2] tx_cpld_len,
input [11:0] tx_cpld_bc,
input [6:0] tx_cpld_laddr,
input [63:0] tx_cpld_data,
output tx_cpld_req_ack,
input tx_mrd0_req,
input [7:0] tx_mrd0_tag,
input [11:2] tx_mrd0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd0_addr,
output tx_mrd0_req_ack,
input tx_mrd1_req,
input [7:0] tx_mrd1_tag,
input [11:2] tx_mrd1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd1_addr,
output tx_mrd1_req_ack,
input tx_mrd2_req,
input [7:0] tx_mrd2_tag,
input [11:2] tx_mrd2_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd2_addr,
output tx_mrd2_req_ack,
input tx_mwr0_req,
input [7:0] tx_mwr0_tag,
input [11:2] tx_mwr0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr0_addr,
output tx_mwr0_req_ack,
output tx_mwr0_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr0_rd_data,
output tx_mwr0_data_last,
input tx_mwr1_req,
input [7:0] tx_mwr1_tag,
input [11:2] tx_mwr1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr1_addr,
output tx_mwr1_req_ack,
output tx_mwr1_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr1_rd_data,
output tx_mwr1_data_last
);
wire w_tx_arb_valid;
wire [5:0] w_tx_arb_gnt;
wire [2:0] w_tx_arb_type;
wire [11:2] w_tx_pcie_len;
wire [127:0] w_tx_pcie_head;
wire [31:0] w_tx_cpld_udata;
wire w_tx_arb_rdy;
pcie_tx_arb # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tx_arb_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_dev_id (pcie_dev_id),
.tx_cpld_gnt (tx_cpld_gnt),
.tx_mrd_gnt (tx_mrd_gnt),
.tx_mwr_gnt (tx_mwr_gnt),
.tx_cpld_req (tx_cpld_req),
.tx_cpld_tag (tx_cpld_tag),
.tx_cpld_req_id (tx_cpld_req_id),
.tx_cpld_len (tx_cpld_len),
.tx_cpld_bc (tx_cpld_bc),
.tx_cpld_laddr (tx_cpld_laddr),
.tx_cpld_data (tx_cpld_data),
.tx_cpld_req_ack (tx_cpld_req_ack),
.tx_mrd0_req (tx_mrd0_req),
.tx_mrd0_tag (tx_mrd0_tag),
.tx_mrd0_len (tx_mrd0_len),
.tx_mrd0_addr (tx_mrd0_addr),
.tx_mrd0_req_ack (tx_mrd0_req_ack),
.tx_mrd1_req (tx_mrd1_req),
.tx_mrd1_tag (tx_mrd1_tag),
.tx_mrd1_len (tx_mrd1_len),
.tx_mrd1_addr (tx_mrd1_addr),
.tx_mrd1_req_ack (tx_mrd1_req_ack),
.tx_mrd2_req (tx_mrd2_req),
.tx_mrd2_tag (tx_mrd2_tag),
.tx_mrd2_len (tx_mrd2_len),
.tx_mrd2_addr (tx_mrd2_addr),
.tx_mrd2_req_ack (tx_mrd2_req_ack),
.tx_mwr0_req (tx_mwr0_req),
.tx_mwr0_tag (tx_mwr0_tag),
.tx_mwr0_len (tx_mwr0_len),
.tx_mwr0_addr (tx_mwr0_addr),
.tx_mwr0_req_ack (tx_mwr0_req_ack),
.tx_mwr1_req (tx_mwr1_req),
.tx_mwr1_tag (tx_mwr1_tag),
.tx_mwr1_len (tx_mwr1_len),
.tx_mwr1_addr (tx_mwr1_addr),
.tx_mwr1_req_ack (tx_mwr1_req_ack),
.tx_arb_valid (w_tx_arb_valid),
.tx_arb_gnt (w_tx_arb_gnt),
.tx_arb_type (w_tx_arb_type),
.tx_pcie_len (w_tx_pcie_len),
.tx_pcie_head (w_tx_pcie_head),
.tx_cpld_udata (w_tx_cpld_udata),
.tx_arb_rdy (w_tx_arb_rdy)
);
pcie_tx_tran # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tx_tran_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.tx_err_drop (tx_err_drop),
//pcie tx signal
.m_axis_tx_tready (m_axis_tx_tready),
.m_axis_tx_tdata (m_axis_tx_tdata),
.m_axis_tx_tkeep (m_axis_tx_tkeep),
.m_axis_tx_tuser (m_axis_tx_tuser),
.m_axis_tx_tlast (m_axis_tx_tlast),
.m_axis_tx_tvalid (m_axis_tx_tvalid),
.tx_arb_valid (w_tx_arb_valid),
.tx_arb_gnt (w_tx_arb_gnt),
.tx_arb_type (w_tx_arb_type),
.tx_pcie_len (w_tx_pcie_len),
.tx_pcie_head (w_tx_pcie_head),
.tx_cpld_udata (w_tx_cpld_udata),
.tx_arb_rdy (w_tx_arb_rdy),
.tx_mwr0_rd_en (tx_mwr0_rd_en),
.tx_mwr0_rd_data (tx_mwr0_rd_data),
.tx_mwr0_data_last (tx_mwr0_data_last),
.tx_mwr1_rd_en (tx_mwr1_rd_en),
.tx_mwr1_rd_data (tx_mwr1_rd_data),
.tx_mwr1_data_last (tx_mwr1_data_last)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] pcie_dev_id,
output tx_err_drop,
input tx_cpld_gnt,
input tx_mrd_gnt,
input tx_mwr_gnt,
//pcie tx signal
input m_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] m_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_tx_tkeep,
output [3:0] m_axis_tx_tuser,
output m_axis_tx_tlast,
output m_axis_tx_tvalid,
input tx_cpld_req,
input [7:0] tx_cpld_tag,
input [15:0] tx_cpld_req_id,
input [11:2] tx_cpld_len,
input [11:0] tx_cpld_bc,
input [6:0] tx_cpld_laddr,
input [63:0] tx_cpld_data,
output tx_cpld_req_ack,
input tx_mrd0_req,
input [7:0] tx_mrd0_tag,
input [11:2] tx_mrd0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd0_addr,
output tx_mrd0_req_ack,
input tx_mrd1_req,
input [7:0] tx_mrd1_tag,
input [11:2] tx_mrd1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd1_addr,
output tx_mrd1_req_ack,
input tx_mrd2_req,
input [7:0] tx_mrd2_tag,
input [11:2] tx_mrd2_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd2_addr,
output tx_mrd2_req_ack,
input tx_mwr0_req,
input [7:0] tx_mwr0_tag,
input [11:2] tx_mwr0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr0_addr,
output tx_mwr0_req_ack,
output tx_mwr0_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr0_rd_data,
output tx_mwr0_data_last,
input tx_mwr1_req,
input [7:0] tx_mwr1_tag,
input [11:2] tx_mwr1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr1_addr,
output tx_mwr1_req_ack,
output tx_mwr1_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr1_rd_data,
output tx_mwr1_data_last
);
wire w_tx_arb_valid;
wire [5:0] w_tx_arb_gnt;
wire [2:0] w_tx_arb_type;
wire [11:2] w_tx_pcie_len;
wire [127:0] w_tx_pcie_head;
wire [31:0] w_tx_cpld_udata;
wire w_tx_arb_rdy;
pcie_tx_arb # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tx_arb_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_dev_id (pcie_dev_id),
.tx_cpld_gnt (tx_cpld_gnt),
.tx_mrd_gnt (tx_mrd_gnt),
.tx_mwr_gnt (tx_mwr_gnt),
.tx_cpld_req (tx_cpld_req),
.tx_cpld_tag (tx_cpld_tag),
.tx_cpld_req_id (tx_cpld_req_id),
.tx_cpld_len (tx_cpld_len),
.tx_cpld_bc (tx_cpld_bc),
.tx_cpld_laddr (tx_cpld_laddr),
.tx_cpld_data (tx_cpld_data),
.tx_cpld_req_ack (tx_cpld_req_ack),
.tx_mrd0_req (tx_mrd0_req),
.tx_mrd0_tag (tx_mrd0_tag),
.tx_mrd0_len (tx_mrd0_len),
.tx_mrd0_addr (tx_mrd0_addr),
.tx_mrd0_req_ack (tx_mrd0_req_ack),
.tx_mrd1_req (tx_mrd1_req),
.tx_mrd1_tag (tx_mrd1_tag),
.tx_mrd1_len (tx_mrd1_len),
.tx_mrd1_addr (tx_mrd1_addr),
.tx_mrd1_req_ack (tx_mrd1_req_ack),
.tx_mrd2_req (tx_mrd2_req),
.tx_mrd2_tag (tx_mrd2_tag),
.tx_mrd2_len (tx_mrd2_len),
.tx_mrd2_addr (tx_mrd2_addr),
.tx_mrd2_req_ack (tx_mrd2_req_ack),
.tx_mwr0_req (tx_mwr0_req),
.tx_mwr0_tag (tx_mwr0_tag),
.tx_mwr0_len (tx_mwr0_len),
.tx_mwr0_addr (tx_mwr0_addr),
.tx_mwr0_req_ack (tx_mwr0_req_ack),
.tx_mwr1_req (tx_mwr1_req),
.tx_mwr1_tag (tx_mwr1_tag),
.tx_mwr1_len (tx_mwr1_len),
.tx_mwr1_addr (tx_mwr1_addr),
.tx_mwr1_req_ack (tx_mwr1_req_ack),
.tx_arb_valid (w_tx_arb_valid),
.tx_arb_gnt (w_tx_arb_gnt),
.tx_arb_type (w_tx_arb_type),
.tx_pcie_len (w_tx_pcie_len),
.tx_pcie_head (w_tx_pcie_head),
.tx_cpld_udata (w_tx_cpld_udata),
.tx_arb_rdy (w_tx_arb_rdy)
);
pcie_tx_tran # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tx_tran_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.tx_err_drop (tx_err_drop),
//pcie tx signal
.m_axis_tx_tready (m_axis_tx_tready),
.m_axis_tx_tdata (m_axis_tx_tdata),
.m_axis_tx_tkeep (m_axis_tx_tkeep),
.m_axis_tx_tuser (m_axis_tx_tuser),
.m_axis_tx_tlast (m_axis_tx_tlast),
.m_axis_tx_tvalid (m_axis_tx_tvalid),
.tx_arb_valid (w_tx_arb_valid),
.tx_arb_gnt (w_tx_arb_gnt),
.tx_arb_type (w_tx_arb_type),
.tx_pcie_len (w_tx_pcie_len),
.tx_pcie_head (w_tx_pcie_head),
.tx_cpld_udata (w_tx_cpld_udata),
.tx_arb_rdy (w_tx_arb_rdy),
.tx_mwr0_rd_en (tx_mwr0_rd_en),
.tx_mwr0_rd_data (tx_mwr0_rd_data),
.tx_mwr0_data_last (tx_mwr0_data_last),
.tx_mwr1_rd_en (tx_mwr1_rd_en),
.tx_mwr1_rd_data (tx_mwr1_rd_data),
.tx_mwr1_data_last (tx_mwr1_data_last)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] pcie_dev_id,
output tx_err_drop,
input tx_cpld_gnt,
input tx_mrd_gnt,
input tx_mwr_gnt,
//pcie tx signal
input m_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] m_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_tx_tkeep,
output [3:0] m_axis_tx_tuser,
output m_axis_tx_tlast,
output m_axis_tx_tvalid,
input tx_cpld_req,
input [7:0] tx_cpld_tag,
input [15:0] tx_cpld_req_id,
input [11:2] tx_cpld_len,
input [11:0] tx_cpld_bc,
input [6:0] tx_cpld_laddr,
input [63:0] tx_cpld_data,
output tx_cpld_req_ack,
input tx_mrd0_req,
input [7:0] tx_mrd0_tag,
input [11:2] tx_mrd0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd0_addr,
output tx_mrd0_req_ack,
input tx_mrd1_req,
input [7:0] tx_mrd1_tag,
input [11:2] tx_mrd1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd1_addr,
output tx_mrd1_req_ack,
input tx_mrd2_req,
input [7:0] tx_mrd2_tag,
input [11:2] tx_mrd2_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd2_addr,
output tx_mrd2_req_ack,
input tx_mwr0_req,
input [7:0] tx_mwr0_tag,
input [11:2] tx_mwr0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr0_addr,
output tx_mwr0_req_ack,
output tx_mwr0_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr0_rd_data,
output tx_mwr0_data_last,
input tx_mwr1_req,
input [7:0] tx_mwr1_tag,
input [11:2] tx_mwr1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr1_addr,
output tx_mwr1_req_ack,
output tx_mwr1_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr1_rd_data,
output tx_mwr1_data_last
);
wire w_tx_arb_valid;
wire [5:0] w_tx_arb_gnt;
wire [2:0] w_tx_arb_type;
wire [11:2] w_tx_pcie_len;
wire [127:0] w_tx_pcie_head;
wire [31:0] w_tx_cpld_udata;
wire w_tx_arb_rdy;
pcie_tx_arb # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tx_arb_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_dev_id (pcie_dev_id),
.tx_cpld_gnt (tx_cpld_gnt),
.tx_mrd_gnt (tx_mrd_gnt),
.tx_mwr_gnt (tx_mwr_gnt),
.tx_cpld_req (tx_cpld_req),
.tx_cpld_tag (tx_cpld_tag),
.tx_cpld_req_id (tx_cpld_req_id),
.tx_cpld_len (tx_cpld_len),
.tx_cpld_bc (tx_cpld_bc),
.tx_cpld_laddr (tx_cpld_laddr),
.tx_cpld_data (tx_cpld_data),
.tx_cpld_req_ack (tx_cpld_req_ack),
.tx_mrd0_req (tx_mrd0_req),
.tx_mrd0_tag (tx_mrd0_tag),
.tx_mrd0_len (tx_mrd0_len),
.tx_mrd0_addr (tx_mrd0_addr),
.tx_mrd0_req_ack (tx_mrd0_req_ack),
.tx_mrd1_req (tx_mrd1_req),
.tx_mrd1_tag (tx_mrd1_tag),
.tx_mrd1_len (tx_mrd1_len),
.tx_mrd1_addr (tx_mrd1_addr),
.tx_mrd1_req_ack (tx_mrd1_req_ack),
.tx_mrd2_req (tx_mrd2_req),
.tx_mrd2_tag (tx_mrd2_tag),
.tx_mrd2_len (tx_mrd2_len),
.tx_mrd2_addr (tx_mrd2_addr),
.tx_mrd2_req_ack (tx_mrd2_req_ack),
.tx_mwr0_req (tx_mwr0_req),
.tx_mwr0_tag (tx_mwr0_tag),
.tx_mwr0_len (tx_mwr0_len),
.tx_mwr0_addr (tx_mwr0_addr),
.tx_mwr0_req_ack (tx_mwr0_req_ack),
.tx_mwr1_req (tx_mwr1_req),
.tx_mwr1_tag (tx_mwr1_tag),
.tx_mwr1_len (tx_mwr1_len),
.tx_mwr1_addr (tx_mwr1_addr),
.tx_mwr1_req_ack (tx_mwr1_req_ack),
.tx_arb_valid (w_tx_arb_valid),
.tx_arb_gnt (w_tx_arb_gnt),
.tx_arb_type (w_tx_arb_type),
.tx_pcie_len (w_tx_pcie_len),
.tx_pcie_head (w_tx_pcie_head),
.tx_cpld_udata (w_tx_cpld_udata),
.tx_arb_rdy (w_tx_arb_rdy)
);
pcie_tx_tran # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tx_tran_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.tx_err_drop (tx_err_drop),
//pcie tx signal
.m_axis_tx_tready (m_axis_tx_tready),
.m_axis_tx_tdata (m_axis_tx_tdata),
.m_axis_tx_tkeep (m_axis_tx_tkeep),
.m_axis_tx_tuser (m_axis_tx_tuser),
.m_axis_tx_tlast (m_axis_tx_tlast),
.m_axis_tx_tvalid (m_axis_tx_tvalid),
.tx_arb_valid (w_tx_arb_valid),
.tx_arb_gnt (w_tx_arb_gnt),
.tx_arb_type (w_tx_arb_type),
.tx_pcie_len (w_tx_pcie_len),
.tx_pcie_head (w_tx_pcie_head),
.tx_cpld_udata (w_tx_cpld_udata),
.tx_arb_rdy (w_tx_arb_rdy),
.tx_mwr0_rd_en (tx_mwr0_rd_en),
.tx_mwr0_rd_data (tx_mwr0_rd_data),
.tx_mwr0_data_last (tx_mwr0_data_last),
.tx_mwr1_rd_en (tx_mwr1_rd_en),
.tx_mwr1_rd_data (tx_mwr1_rd_data),
.tx_mwr1_data_last (tx_mwr1_data_last)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tans_if # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
//PCIe user clock
input pcie_user_clk,
input pcie_user_rst_n,
//PCIe rx interface
output mreq_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output [7:0] cpld0_fifo_tag,
output cpld0_fifo_tag_last,
output cpld0_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld0_fifo_wr_data,
output [7:0] cpld1_fifo_tag,
output cpld1_fifo_tag_last,
output cpld1_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld1_fifo_wr_data,
output [7:0] cpld2_fifo_tag,
output cpld2_fifo_tag_last,
output cpld2_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld2_fifo_wr_data,
//PCIe tx interface
input tx_cpld_req,
input [7:0] tx_cpld_tag,
input [15:0] tx_cpld_req_id,
input [11:2] tx_cpld_len,
input [11:0] tx_cpld_bc,
input [6:0] tx_cpld_laddr,
input [63:0] tx_cpld_data,
output tx_cpld_req_ack,
input tx_mrd0_req,
input [7:0] tx_mrd0_tag,
input [11:2] tx_mrd0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd0_addr,
output tx_mrd0_req_ack,
input tx_mrd1_req,
input [7:0] tx_mrd1_tag,
input [11:2] tx_mrd1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd1_addr,
output tx_mrd1_req_ack,
input tx_mrd2_req,
input [7:0] tx_mrd2_tag,
input [11:2] tx_mrd2_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd2_addr,
output tx_mrd2_req_ack,
input tx_mwr0_req,
input [7:0] tx_mwr0_tag,
input [11:2] tx_mwr0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr0_addr,
output tx_mwr0_req_ack,
output tx_mwr0_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr0_rd_data,
output tx_mwr0_data_last,
input tx_mwr1_req,
input [7:0] tx_mwr1_tag,
input [11:2] tx_mwr1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr1_addr,
output tx_mwr1_req_ack,
output tx_mwr1_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr1_rd_data,
output tx_mwr1_data_last,
output pcie_mreq_err,
output pcie_cpld_err,
output pcie_cpld_len_err,
//PCIe Integrated Block Interface
input [5:0] tx_buf_av,
input tx_err_drop,
input tx_cfg_req,
input s_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_tx_tkeep,
output [3:0] s_axis_tx_tuser,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_cfg_gnt,
input [C_PCIE_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number
);
wire w_tx_cpld_gnt;
wire w_tx_mrd_gnt;
wire w_tx_mwr_gnt;
reg [15:0] r_pcie_dev_id;
always @(posedge pcie_user_clk) begin
r_pcie_dev_id <= {cfg_bus_number, cfg_device_number, cfg_function_number};
end
pcie_fc_cntl
pcie_fc_cntl_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.fc_cpld (fc_cpld),
.fc_cplh (fc_cplh),
.fc_npd (fc_npd),
.fc_nph (fc_nph),
.fc_pd (fc_pd),
.fc_ph (fc_ph),
.fc_sel (fc_sel),
.tx_buf_av (tx_buf_av),
.tx_cfg_req (tx_cfg_req),
.tx_cfg_gnt (tx_cfg_gnt),
.tx_cpld_gnt (w_tx_cpld_gnt),
.tx_mrd_gnt (w_tx_mrd_gnt),
.tx_mwr_gnt (w_tx_mwr_gnt)
);
pcie_rx # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_rx_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
//pcie rx signal
.s_axis_rx_tdata (m_axis_rx_tdata),
.s_axis_rx_tkeep (m_axis_rx_tkeep),
.s_axis_rx_tlast (m_axis_rx_tlast),
.s_axis_rx_tvalid (m_axis_rx_tvalid),
.s_axis_rx_tready (m_axis_rx_tready),
.s_axis_rx_tuser (m_axis_rx_tuser),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.mreq_fifo_wr_en (mreq_fifo_wr_en),
.mreq_fifo_wr_data (mreq_fifo_wr_data),
.cpld0_fifo_tag (cpld0_fifo_tag),
.cpld0_fifo_tag_last (cpld0_fifo_tag_last),
.cpld0_fifo_wr_en (cpld0_fifo_wr_en),
.cpld0_fifo_wr_data (cpld0_fifo_wr_data),
.cpld1_fifo_tag (cpld1_fifo_tag),
.cpld1_fifo_tag_last (cpld1_fifo_tag_last),
.cpld1_fifo_wr_en (cpld1_fifo_wr_en),
.cpld1_fifo_wr_data (cpld1_fifo_wr_data),
.cpld2_fifo_tag (cpld2_fifo_tag),
.cpld2_fifo_tag_last (cpld2_fifo_tag_last),
.cpld2_fifo_wr_en (cpld2_fifo_wr_en),
.cpld2_fifo_wr_data (cpld2_fifo_wr_data)
);
pcie_tx # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tx_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_dev_id (r_pcie_dev_id),
.tx_err_drop (tx_err_drop),
.tx_cpld_gnt (w_tx_cpld_gnt),
.tx_mrd_gnt (w_tx_mrd_gnt),
.tx_mwr_gnt (w_tx_mwr_gnt),
//pcie tx signal
.m_axis_tx_tready (s_axis_tx_tready),
.m_axis_tx_tdata (s_axis_tx_tdata),
.m_axis_tx_tkeep (s_axis_tx_tkeep),
.m_axis_tx_tuser (s_axis_tx_tuser),
.m_axis_tx_tlast (s_axis_tx_tlast),
.m_axis_tx_tvalid (s_axis_tx_tvalid),
.tx_cpld_req (tx_cpld_req),
.tx_cpld_tag (tx_cpld_tag),
.tx_cpld_req_id (tx_cpld_req_id),
.tx_cpld_len (tx_cpld_len),
.tx_cpld_bc (tx_cpld_bc),
.tx_cpld_laddr (tx_cpld_laddr),
.tx_cpld_data (tx_cpld_data),
.tx_cpld_req_ack (tx_cpld_req_ack),
.tx_mrd0_req (tx_mrd0_req),
.tx_mrd0_tag (tx_mrd0_tag),
.tx_mrd0_len (tx_mrd0_len),
.tx_mrd0_addr (tx_mrd0_addr),
.tx_mrd0_req_ack (tx_mrd0_req_ack),
.tx_mrd1_req (tx_mrd1_req),
.tx_mrd1_tag (tx_mrd1_tag),
.tx_mrd1_len (tx_mrd1_len),
.tx_mrd1_addr (tx_mrd1_addr),
.tx_mrd1_req_ack (tx_mrd1_req_ack),
.tx_mrd2_req (tx_mrd2_req),
.tx_mrd2_tag (tx_mrd2_tag),
.tx_mrd2_len (tx_mrd2_len),
.tx_mrd2_addr (tx_mrd2_addr),
.tx_mrd2_req_ack (tx_mrd2_req_ack),
.tx_mwr0_req (tx_mwr0_req),
.tx_mwr0_tag (tx_mwr0_tag),
.tx_mwr0_len (tx_mwr0_len),
.tx_mwr0_addr (tx_mwr0_addr),
.tx_mwr0_req_ack (tx_mwr0_req_ack),
.tx_mwr0_rd_en (tx_mwr0_rd_en),
.tx_mwr0_rd_data (tx_mwr0_rd_data),
.tx_mwr0_data_last (tx_mwr0_data_last),
.tx_mwr1_req (tx_mwr1_req),
.tx_mwr1_tag (tx_mwr1_tag),
.tx_mwr1_len (tx_mwr1_len),
.tx_mwr1_addr (tx_mwr1_addr),
.tx_mwr1_req_ack (tx_mwr1_req_ack),
.tx_mwr1_rd_en (tx_mwr1_rd_en),
.tx_mwr1_rd_data (tx_mwr1_rd_data),
.tx_mwr1_data_last (tx_mwr1_data_last)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tans_if # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
//PCIe user clock
input pcie_user_clk,
input pcie_user_rst_n,
//PCIe rx interface
output mreq_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output [7:0] cpld0_fifo_tag,
output cpld0_fifo_tag_last,
output cpld0_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld0_fifo_wr_data,
output [7:0] cpld1_fifo_tag,
output cpld1_fifo_tag_last,
output cpld1_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld1_fifo_wr_data,
output [7:0] cpld2_fifo_tag,
output cpld2_fifo_tag_last,
output cpld2_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld2_fifo_wr_data,
//PCIe tx interface
input tx_cpld_req,
input [7:0] tx_cpld_tag,
input [15:0] tx_cpld_req_id,
input [11:2] tx_cpld_len,
input [11:0] tx_cpld_bc,
input [6:0] tx_cpld_laddr,
input [63:0] tx_cpld_data,
output tx_cpld_req_ack,
input tx_mrd0_req,
input [7:0] tx_mrd0_tag,
input [11:2] tx_mrd0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd0_addr,
output tx_mrd0_req_ack,
input tx_mrd1_req,
input [7:0] tx_mrd1_tag,
input [11:2] tx_mrd1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd1_addr,
output tx_mrd1_req_ack,
input tx_mrd2_req,
input [7:0] tx_mrd2_tag,
input [11:2] tx_mrd2_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd2_addr,
output tx_mrd2_req_ack,
input tx_mwr0_req,
input [7:0] tx_mwr0_tag,
input [11:2] tx_mwr0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr0_addr,
output tx_mwr0_req_ack,
output tx_mwr0_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr0_rd_data,
output tx_mwr0_data_last,
input tx_mwr1_req,
input [7:0] tx_mwr1_tag,
input [11:2] tx_mwr1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr1_addr,
output tx_mwr1_req_ack,
output tx_mwr1_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr1_rd_data,
output tx_mwr1_data_last,
output pcie_mreq_err,
output pcie_cpld_err,
output pcie_cpld_len_err,
//PCIe Integrated Block Interface
input [5:0] tx_buf_av,
input tx_err_drop,
input tx_cfg_req,
input s_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_tx_tkeep,
output [3:0] s_axis_tx_tuser,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_cfg_gnt,
input [C_PCIE_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number
);
wire w_tx_cpld_gnt;
wire w_tx_mrd_gnt;
wire w_tx_mwr_gnt;
reg [15:0] r_pcie_dev_id;
always @(posedge pcie_user_clk) begin
r_pcie_dev_id <= {cfg_bus_number, cfg_device_number, cfg_function_number};
end
pcie_fc_cntl
pcie_fc_cntl_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.fc_cpld (fc_cpld),
.fc_cplh (fc_cplh),
.fc_npd (fc_npd),
.fc_nph (fc_nph),
.fc_pd (fc_pd),
.fc_ph (fc_ph),
.fc_sel (fc_sel),
.tx_buf_av (tx_buf_av),
.tx_cfg_req (tx_cfg_req),
.tx_cfg_gnt (tx_cfg_gnt),
.tx_cpld_gnt (w_tx_cpld_gnt),
.tx_mrd_gnt (w_tx_mrd_gnt),
.tx_mwr_gnt (w_tx_mwr_gnt)
);
pcie_rx # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_rx_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
//pcie rx signal
.s_axis_rx_tdata (m_axis_rx_tdata),
.s_axis_rx_tkeep (m_axis_rx_tkeep),
.s_axis_rx_tlast (m_axis_rx_tlast),
.s_axis_rx_tvalid (m_axis_rx_tvalid),
.s_axis_rx_tready (m_axis_rx_tready),
.s_axis_rx_tuser (m_axis_rx_tuser),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.mreq_fifo_wr_en (mreq_fifo_wr_en),
.mreq_fifo_wr_data (mreq_fifo_wr_data),
.cpld0_fifo_tag (cpld0_fifo_tag),
.cpld0_fifo_tag_last (cpld0_fifo_tag_last),
.cpld0_fifo_wr_en (cpld0_fifo_wr_en),
.cpld0_fifo_wr_data (cpld0_fifo_wr_data),
.cpld1_fifo_tag (cpld1_fifo_tag),
.cpld1_fifo_tag_last (cpld1_fifo_tag_last),
.cpld1_fifo_wr_en (cpld1_fifo_wr_en),
.cpld1_fifo_wr_data (cpld1_fifo_wr_data),
.cpld2_fifo_tag (cpld2_fifo_tag),
.cpld2_fifo_tag_last (cpld2_fifo_tag_last),
.cpld2_fifo_wr_en (cpld2_fifo_wr_en),
.cpld2_fifo_wr_data (cpld2_fifo_wr_data)
);
pcie_tx # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tx_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_dev_id (r_pcie_dev_id),
.tx_err_drop (tx_err_drop),
.tx_cpld_gnt (w_tx_cpld_gnt),
.tx_mrd_gnt (w_tx_mrd_gnt),
.tx_mwr_gnt (w_tx_mwr_gnt),
//pcie tx signal
.m_axis_tx_tready (s_axis_tx_tready),
.m_axis_tx_tdata (s_axis_tx_tdata),
.m_axis_tx_tkeep (s_axis_tx_tkeep),
.m_axis_tx_tuser (s_axis_tx_tuser),
.m_axis_tx_tlast (s_axis_tx_tlast),
.m_axis_tx_tvalid (s_axis_tx_tvalid),
.tx_cpld_req (tx_cpld_req),
.tx_cpld_tag (tx_cpld_tag),
.tx_cpld_req_id (tx_cpld_req_id),
.tx_cpld_len (tx_cpld_len),
.tx_cpld_bc (tx_cpld_bc),
.tx_cpld_laddr (tx_cpld_laddr),
.tx_cpld_data (tx_cpld_data),
.tx_cpld_req_ack (tx_cpld_req_ack),
.tx_mrd0_req (tx_mrd0_req),
.tx_mrd0_tag (tx_mrd0_tag),
.tx_mrd0_len (tx_mrd0_len),
.tx_mrd0_addr (tx_mrd0_addr),
.tx_mrd0_req_ack (tx_mrd0_req_ack),
.tx_mrd1_req (tx_mrd1_req),
.tx_mrd1_tag (tx_mrd1_tag),
.tx_mrd1_len (tx_mrd1_len),
.tx_mrd1_addr (tx_mrd1_addr),
.tx_mrd1_req_ack (tx_mrd1_req_ack),
.tx_mrd2_req (tx_mrd2_req),
.tx_mrd2_tag (tx_mrd2_tag),
.tx_mrd2_len (tx_mrd2_len),
.tx_mrd2_addr (tx_mrd2_addr),
.tx_mrd2_req_ack (tx_mrd2_req_ack),
.tx_mwr0_req (tx_mwr0_req),
.tx_mwr0_tag (tx_mwr0_tag),
.tx_mwr0_len (tx_mwr0_len),
.tx_mwr0_addr (tx_mwr0_addr),
.tx_mwr0_req_ack (tx_mwr0_req_ack),
.tx_mwr0_rd_en (tx_mwr0_rd_en),
.tx_mwr0_rd_data (tx_mwr0_rd_data),
.tx_mwr0_data_last (tx_mwr0_data_last),
.tx_mwr1_req (tx_mwr1_req),
.tx_mwr1_tag (tx_mwr1_tag),
.tx_mwr1_len (tx_mwr1_len),
.tx_mwr1_addr (tx_mwr1_addr),
.tx_mwr1_req_ack (tx_mwr1_req_ack),
.tx_mwr1_rd_en (tx_mwr1_rd_en),
.tx_mwr1_rd_data (tx_mwr1_rd_data),
.tx_mwr1_data_last (tx_mwr1_data_last)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 34,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 34,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx_req # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_payload_size,
output pcie_tx_cmd_rd_en,
input [33:0] pcie_tx_cmd_rd_data,
input pcie_tx_cmd_empty_n,
output pcie_tx_fifo_free_en,
output [9:4] pcie_tx_fifo_free_len,
input pcie_tx_fifo_empty_n,
output tx_dma_mwr_req,
output [7:0] tx_dma_mwr_tag,
output [11:2] tx_dma_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr,
input tx_dma_mwr_req_ack,
input tx_dma_mwr_data_last,
output dma_tx_done_wr_en,
output [20:0] dma_tx_done_wr_data,
input dma_tx_done_wr_rdy_n
);
localparam S_IDLE = 10'b0000000001;
localparam S_PCIE_TX_CMD_0 = 10'b0000000010;
localparam S_PCIE_TX_CMD_1 = 10'b0000000100;
localparam S_PCIE_CHK_FIFO = 10'b0000001000;
localparam S_PCIE_MWR_REQ = 10'b0000010000;
localparam S_PCIE_MWR_ACK = 10'b0000100000;
localparam S_PCIE_MWR_DONE = 10'b0001000000;
localparam S_PCIE_MWR_NEXT = 10'b0010000000;
localparam S_PCIE_DMA_DONE_WR_WAIT = 10'b0100000000;
localparam S_PCIE_DMA_DONE_WR = 10'b1000000000;
reg [9:0] cur_state;
reg [9:0] next_state;
reg [2:0] r_pcie_max_payload_size;
reg r_pcie_tx_cmd_rd_en;
reg r_pcie_tx_fifo_free_en;
reg r_tx_dma_mwr_req;
reg r_dma_cmd_type;
reg r_dma_done_check;
reg [6:0] r_hcmd_slot_tag;
reg [12:2] r_pcie_tx_len;
reg [12:2] r_pcie_orig_len;
reg [9:2] r_pcie_tx_cur_len;
reg [C_PCIE_ADDR_WIDTH-1:2] r_pcie_addr;
reg r_dma_tx_done_wr_en;
assign pcie_tx_cmd_rd_en = r_pcie_tx_cmd_rd_en;
assign pcie_tx_fifo_free_en = r_pcie_tx_fifo_free_en;
assign pcie_tx_fifo_free_len = r_pcie_tx_cur_len[9:4];
assign tx_dma_mwr_req = r_tx_dma_mwr_req;
assign tx_dma_mwr_tag = 8'b0;
assign tx_dma_mwr_len = {2'b0, r_pcie_tx_cur_len};
assign tx_dma_mwr_addr = r_pcie_addr;
assign dma_tx_done_wr_en = r_dma_tx_done_wr_en;
assign dma_tx_done_wr_data = {r_dma_cmd_type, r_dma_done_check, 1'b1, r_hcmd_slot_tag, r_pcie_orig_len};
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(pcie_tx_cmd_empty_n == 1)
next_state <= S_PCIE_TX_CMD_0;
else
next_state <= S_IDLE;
end
S_PCIE_TX_CMD_0: begin
next_state <= S_PCIE_TX_CMD_1;
end
S_PCIE_TX_CMD_1: begin
next_state <= S_PCIE_CHK_FIFO;
end
S_PCIE_CHK_FIFO: begin
if(pcie_tx_fifo_empty_n == 1)
next_state <= S_PCIE_MWR_REQ;
else
next_state <= S_PCIE_CHK_FIFO;
end
S_PCIE_MWR_REQ: begin
next_state <= S_PCIE_MWR_ACK;
end
S_PCIE_MWR_ACK: begin
if(tx_dma_mwr_req_ack == 1)
next_state <= S_PCIE_MWR_DONE;
else
next_state <= S_PCIE_MWR_ACK;
end
S_PCIE_MWR_DONE: begin
next_state <= S_PCIE_MWR_NEXT;
end
S_PCIE_MWR_NEXT: begin
if(r_pcie_tx_len == 0)
next_state <= S_PCIE_DMA_DONE_WR_WAIT;
else
next_state <= S_PCIE_CHK_FIFO;
end
S_PCIE_DMA_DONE_WR_WAIT: begin
if(dma_tx_done_wr_rdy_n == 1)
next_state <= S_PCIE_DMA_DONE_WR_WAIT;
else
next_state <= S_PCIE_DMA_DONE_WR;
end
S_PCIE_DMA_DONE_WR: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
r_pcie_max_payload_size <= pcie_max_payload_size;
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_PCIE_TX_CMD_0: begin
r_dma_cmd_type <= pcie_tx_cmd_rd_data[19];
r_dma_done_check <= pcie_tx_cmd_rd_data[18];
r_hcmd_slot_tag <= pcie_tx_cmd_rd_data[17:11];
r_pcie_tx_len <= {pcie_tx_cmd_rd_data[10:2], 2'b0};
end
S_PCIE_TX_CMD_1: begin
r_pcie_orig_len <= r_pcie_tx_len;
case(r_pcie_max_payload_size)
3'b010: begin
if(r_pcie_tx_len[8:7] == 0 && r_pcie_tx_len[6:2] == 0)
r_pcie_tx_cur_len[9:7] <= 3'b100;
else
r_pcie_tx_cur_len[9:7] <= {1'b0, r_pcie_tx_len[8:7]};
end
3'b001: begin
if(r_pcie_tx_len[7] == 0 && r_pcie_tx_len[6:2] == 0)
r_pcie_tx_cur_len[9:7] <= 3'b010;
else
r_pcie_tx_cur_len[9:7] <= {2'b0, r_pcie_tx_len[7]};
end
default: begin
if(r_pcie_tx_len[6:2] == 0)
r_pcie_tx_cur_len[9:7] <= 3'b001;
else
r_pcie_tx_cur_len[9:7] <= 3'b000;
end
endcase
r_pcie_tx_cur_len[6:2] <= r_pcie_tx_len[6:2];
r_pcie_addr <= {pcie_tx_cmd_rd_data[33:2], 2'b0};
end
S_PCIE_CHK_FIFO: begin
end
S_PCIE_MWR_REQ: begin
end
S_PCIE_MWR_ACK: begin
end
S_PCIE_MWR_DONE: begin
r_pcie_addr <= r_pcie_addr + r_pcie_tx_cur_len;
r_pcie_tx_len <= r_pcie_tx_len - r_pcie_tx_cur_len;
case(r_pcie_max_payload_size)
3'b010: r_pcie_tx_cur_len <= 8'h80;
3'b001: r_pcie_tx_cur_len <= 8'h40;
default: r_pcie_tx_cur_len <= 8'h20;
endcase
end
S_PCIE_MWR_NEXT: begin
end
S_PCIE_DMA_DONE_WR_WAIT: begin
end
S_PCIE_DMA_DONE_WR: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_TX_CMD_0: begin
r_pcie_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_TX_CMD_1: begin
r_pcie_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_CHK_FIFO: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_MWR_REQ: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 1;
r_tx_dma_mwr_req <= 1;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_MWR_ACK: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_MWR_DONE: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_MWR_NEXT: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_DMA_DONE_WR_WAIT: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_DMA_DONE_WR: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 1;
end
default: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
endcase
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tx_req # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_payload_size,
output pcie_tx_cmd_rd_en,
input [33:0] pcie_tx_cmd_rd_data,
input pcie_tx_cmd_empty_n,
output pcie_tx_fifo_free_en,
output [9:4] pcie_tx_fifo_free_len,
input pcie_tx_fifo_empty_n,
output tx_dma_mwr_req,
output [7:0] tx_dma_mwr_tag,
output [11:2] tx_dma_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr,
input tx_dma_mwr_req_ack,
input tx_dma_mwr_data_last,
output dma_tx_done_wr_en,
output [20:0] dma_tx_done_wr_data,
input dma_tx_done_wr_rdy_n
);
localparam S_IDLE = 10'b0000000001;
localparam S_PCIE_TX_CMD_0 = 10'b0000000010;
localparam S_PCIE_TX_CMD_1 = 10'b0000000100;
localparam S_PCIE_CHK_FIFO = 10'b0000001000;
localparam S_PCIE_MWR_REQ = 10'b0000010000;
localparam S_PCIE_MWR_ACK = 10'b0000100000;
localparam S_PCIE_MWR_DONE = 10'b0001000000;
localparam S_PCIE_MWR_NEXT = 10'b0010000000;
localparam S_PCIE_DMA_DONE_WR_WAIT = 10'b0100000000;
localparam S_PCIE_DMA_DONE_WR = 10'b1000000000;
reg [9:0] cur_state;
reg [9:0] next_state;
reg [2:0] r_pcie_max_payload_size;
reg r_pcie_tx_cmd_rd_en;
reg r_pcie_tx_fifo_free_en;
reg r_tx_dma_mwr_req;
reg r_dma_cmd_type;
reg r_dma_done_check;
reg [6:0] r_hcmd_slot_tag;
reg [12:2] r_pcie_tx_len;
reg [12:2] r_pcie_orig_len;
reg [9:2] r_pcie_tx_cur_len;
reg [C_PCIE_ADDR_WIDTH-1:2] r_pcie_addr;
reg r_dma_tx_done_wr_en;
assign pcie_tx_cmd_rd_en = r_pcie_tx_cmd_rd_en;
assign pcie_tx_fifo_free_en = r_pcie_tx_fifo_free_en;
assign pcie_tx_fifo_free_len = r_pcie_tx_cur_len[9:4];
assign tx_dma_mwr_req = r_tx_dma_mwr_req;
assign tx_dma_mwr_tag = 8'b0;
assign tx_dma_mwr_len = {2'b0, r_pcie_tx_cur_len};
assign tx_dma_mwr_addr = r_pcie_addr;
assign dma_tx_done_wr_en = r_dma_tx_done_wr_en;
assign dma_tx_done_wr_data = {r_dma_cmd_type, r_dma_done_check, 1'b1, r_hcmd_slot_tag, r_pcie_orig_len};
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(pcie_tx_cmd_empty_n == 1)
next_state <= S_PCIE_TX_CMD_0;
else
next_state <= S_IDLE;
end
S_PCIE_TX_CMD_0: begin
next_state <= S_PCIE_TX_CMD_1;
end
S_PCIE_TX_CMD_1: begin
next_state <= S_PCIE_CHK_FIFO;
end
S_PCIE_CHK_FIFO: begin
if(pcie_tx_fifo_empty_n == 1)
next_state <= S_PCIE_MWR_REQ;
else
next_state <= S_PCIE_CHK_FIFO;
end
S_PCIE_MWR_REQ: begin
next_state <= S_PCIE_MWR_ACK;
end
S_PCIE_MWR_ACK: begin
if(tx_dma_mwr_req_ack == 1)
next_state <= S_PCIE_MWR_DONE;
else
next_state <= S_PCIE_MWR_ACK;
end
S_PCIE_MWR_DONE: begin
next_state <= S_PCIE_MWR_NEXT;
end
S_PCIE_MWR_NEXT: begin
if(r_pcie_tx_len == 0)
next_state <= S_PCIE_DMA_DONE_WR_WAIT;
else
next_state <= S_PCIE_CHK_FIFO;
end
S_PCIE_DMA_DONE_WR_WAIT: begin
if(dma_tx_done_wr_rdy_n == 1)
next_state <= S_PCIE_DMA_DONE_WR_WAIT;
else
next_state <= S_PCIE_DMA_DONE_WR;
end
S_PCIE_DMA_DONE_WR: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
r_pcie_max_payload_size <= pcie_max_payload_size;
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_PCIE_TX_CMD_0: begin
r_dma_cmd_type <= pcie_tx_cmd_rd_data[19];
r_dma_done_check <= pcie_tx_cmd_rd_data[18];
r_hcmd_slot_tag <= pcie_tx_cmd_rd_data[17:11];
r_pcie_tx_len <= {pcie_tx_cmd_rd_data[10:2], 2'b0};
end
S_PCIE_TX_CMD_1: begin
r_pcie_orig_len <= r_pcie_tx_len;
case(r_pcie_max_payload_size)
3'b010: begin
if(r_pcie_tx_len[8:7] == 0 && r_pcie_tx_len[6:2] == 0)
r_pcie_tx_cur_len[9:7] <= 3'b100;
else
r_pcie_tx_cur_len[9:7] <= {1'b0, r_pcie_tx_len[8:7]};
end
3'b001: begin
if(r_pcie_tx_len[7] == 0 && r_pcie_tx_len[6:2] == 0)
r_pcie_tx_cur_len[9:7] <= 3'b010;
else
r_pcie_tx_cur_len[9:7] <= {2'b0, r_pcie_tx_len[7]};
end
default: begin
if(r_pcie_tx_len[6:2] == 0)
r_pcie_tx_cur_len[9:7] <= 3'b001;
else
r_pcie_tx_cur_len[9:7] <= 3'b000;
end
endcase
r_pcie_tx_cur_len[6:2] <= r_pcie_tx_len[6:2];
r_pcie_addr <= {pcie_tx_cmd_rd_data[33:2], 2'b0};
end
S_PCIE_CHK_FIFO: begin
end
S_PCIE_MWR_REQ: begin
end
S_PCIE_MWR_ACK: begin
end
S_PCIE_MWR_DONE: begin
r_pcie_addr <= r_pcie_addr + r_pcie_tx_cur_len;
r_pcie_tx_len <= r_pcie_tx_len - r_pcie_tx_cur_len;
case(r_pcie_max_payload_size)
3'b010: r_pcie_tx_cur_len <= 8'h80;
3'b001: r_pcie_tx_cur_len <= 8'h40;
default: r_pcie_tx_cur_len <= 8'h20;
endcase
end
S_PCIE_MWR_NEXT: begin
end
S_PCIE_DMA_DONE_WR_WAIT: begin
end
S_PCIE_DMA_DONE_WR: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_TX_CMD_0: begin
r_pcie_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_TX_CMD_1: begin
r_pcie_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_CHK_FIFO: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_MWR_REQ: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 1;
r_tx_dma_mwr_req <= 1;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_MWR_ACK: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_MWR_DONE: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_MWR_NEXT: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_DMA_DONE_WR_WAIT: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
S_PCIE_DMA_DONE_WR: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 1;
end
default: begin
r_pcie_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_free_en <= 0;
r_tx_dma_mwr_req <= 0;
r_dma_tx_done_wr_en <= 0;
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off COMBDLY
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
reg c1_start; initial c1_start = 0;
wire [31:0] c1_count;
comb_loop c1 (.count(c1_count), .start(c1_start));
wire s2_start = (c1_count==0 && c1_start);
wire [31:0] s2_count;
seq_loop s2 (.count(s2_count), .start(s2_start));
wire c3_start = (s2_count[0]);
wire [31:0] c3_count;
comb_loop c3 (.count(c3_count), .start(c3_start));
reg [7:0] cyc; initial cyc=0;
always @ (posedge clk) begin
//$write("[%0t] %x counts %x %x %x\n",$time,cyc,c1_count,s2_count,c3_count);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
c1_start <= 1'b0;
end
8'd01: begin
c1_start <= 1'b1;
end
default: ;
endcase
case (cyc)
8'd02: begin
if (c1_count!=32'h3) $stop;
if (s2_count!=32'h3) $stop;
if (c3_count!=32'h6) $stop;
end
8'd03: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
module comb_loop (/*AUTOARG*/
// Outputs
count,
// Inputs
start
);
input start;
output reg [31:0] count; initial count = 0;
reg [31:0] runnerm1, runner; initial runner = 0;
always @ (start) begin
if (start) begin
runner = 3;
end
end
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
count = count + 1;
runner = runnerm1;
$write ("%m count=%d runner =%x\n",count, runnerm1);
end
end
endmodule
module seq_loop (/*AUTOARG*/
// Outputs
count,
// Inputs
start
);
input start;
output reg [31:0] count; initial count = 0;
reg [31:0] runnerm1, runner; initial runner = 0;
always @ (start) begin
if (start) begin
runner <= 3;
end
end
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
count = count + 1;
runner <= runnerm1;
$write ("%m count=%d runner<=%x\n",count, runnerm1);
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off COMBDLY
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
reg c1_start; initial c1_start = 0;
wire [31:0] c1_count;
comb_loop c1 (.count(c1_count), .start(c1_start));
wire s2_start = (c1_count==0 && c1_start);
wire [31:0] s2_count;
seq_loop s2 (.count(s2_count), .start(s2_start));
wire c3_start = (s2_count[0]);
wire [31:0] c3_count;
comb_loop c3 (.count(c3_count), .start(c3_start));
reg [7:0] cyc; initial cyc=0;
always @ (posedge clk) begin
//$write("[%0t] %x counts %x %x %x\n",$time,cyc,c1_count,s2_count,c3_count);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
c1_start <= 1'b0;
end
8'd01: begin
c1_start <= 1'b1;
end
default: ;
endcase
case (cyc)
8'd02: begin
if (c1_count!=32'h3) $stop;
if (s2_count!=32'h3) $stop;
if (c3_count!=32'h6) $stop;
end
8'd03: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
module comb_loop (/*AUTOARG*/
// Outputs
count,
// Inputs
start
);
input start;
output reg [31:0] count; initial count = 0;
reg [31:0] runnerm1, runner; initial runner = 0;
always @ (start) begin
if (start) begin
runner = 3;
end
end
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
count = count + 1;
runner = runnerm1;
$write ("%m count=%d runner =%x\n",count, runnerm1);
end
end
endmodule
module seq_loop (/*AUTOARG*/
// Outputs
count,
// Inputs
start
);
input start;
output reg [31:0] count; initial count = 0;
reg [31:0] runnerm1, runner; initial runner = 0;
always @ (start) begin
if (start) begin
runner <= 3;
end
end
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
count = count + 1;
runner <= runnerm1;
$write ("%m count=%d runner<=%x\n",count, runnerm1);
end
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module debounce (
clk,
reset_n,
data_in,
data_out
);
parameter WIDTH = 32; // set to be the width of the bus being debounced
parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce
parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state
parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT))
input wire clk;
input wire reset_n;
input wire [WIDTH-1:0] data_in;
output wire [WIDTH-1:0] data_out;
reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1];
wire counter_reset [0:WIDTH-1];
wire counter_enable [0:WIDTH-1];
// need one counter per input to debounce
genvar i;
generate for (i = 0; i < WIDTH; i = i+1)
begin: debounce_counter_loop
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
counter[i] <= 0;
end
else
begin
if (counter_reset[i] == 1) // resetting the counter needs to win
begin
counter[i] <= 0;
end
else if (counter_enable[i] == 1)
begin
counter[i] <= counter[i] + 1'b1;
end
end
end
if (POLARITY == "HIGH")
begin
assign counter_reset[i] = (data_in[i] == 0);
assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0;
end
else
begin
assign counter_reset[i] = (data_in[i] == 1);
assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1;
end
end
endgenerate
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module debounce (
clk,
reset_n,
data_in,
data_out
);
parameter WIDTH = 32; // set to be the width of the bus being debounced
parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce
parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state
parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT))
input wire clk;
input wire reset_n;
input wire [WIDTH-1:0] data_in;
output wire [WIDTH-1:0] data_out;
reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1];
wire counter_reset [0:WIDTH-1];
wire counter_enable [0:WIDTH-1];
// need one counter per input to debounce
genvar i;
generate for (i = 0; i < WIDTH; i = i+1)
begin: debounce_counter_loop
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
counter[i] <= 0;
end
else
begin
if (counter_reset[i] == 1) // resetting the counter needs to win
begin
counter[i] <= 0;
end
else if (counter_enable[i] == 1)
begin
counter[i] <= counter[i] + 1'b1;
end
end
end
if (POLARITY == "HIGH")
begin
assign counter_reset[i] = (data_in[i] == 0);
assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0;
end
else
begin
assign counter_reset[i] = (data_in[i] == 1);
assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1;
end
end
endgenerate
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module debounce (
clk,
reset_n,
data_in,
data_out
);
parameter WIDTH = 32; // set to be the width of the bus being debounced
parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce
parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state
parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT))
input wire clk;
input wire reset_n;
input wire [WIDTH-1:0] data_in;
output wire [WIDTH-1:0] data_out;
reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1];
wire counter_reset [0:WIDTH-1];
wire counter_enable [0:WIDTH-1];
// need one counter per input to debounce
genvar i;
generate for (i = 0; i < WIDTH; i = i+1)
begin: debounce_counter_loop
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
counter[i] <= 0;
end
else
begin
if (counter_reset[i] == 1) // resetting the counter needs to win
begin
counter[i] <= 0;
end
else if (counter_enable[i] == 1)
begin
counter[i] <= counter[i] + 1'b1;
end
end
end
if (POLARITY == "HIGH")
begin
assign counter_reset[i] = (data_in[i] == 0);
assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0;
end
else
begin
assign counter_reset[i] = (data_in[i] == 1);
assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1;
end
end
endgenerate
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module debounce (
clk,
reset_n,
data_in,
data_out
);
parameter WIDTH = 32; // set to be the width of the bus being debounced
parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce
parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state
parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT))
input wire clk;
input wire reset_n;
input wire [WIDTH-1:0] data_in;
output wire [WIDTH-1:0] data_out;
reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1];
wire counter_reset [0:WIDTH-1];
wire counter_enable [0:WIDTH-1];
// need one counter per input to debounce
genvar i;
generate for (i = 0; i < WIDTH; i = i+1)
begin: debounce_counter_loop
always @ (posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
counter[i] <= 0;
end
else
begin
if (counter_reset[i] == 1) // resetting the counter needs to win
begin
counter[i] <= 0;
end
else if (counter_enable[i] == 1)
begin
counter[i] <= counter[i] + 1'b1;
end
end
end
if (POLARITY == "HIGH")
begin
assign counter_reset[i] = (data_in[i] == 0);
assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0;
end
else
begin
assign counter_reset[i] = (data_in[i] == 1);
assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT);
assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1;
end
end
endgenerate
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module m_axi_dma # (
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 64,
parameter C_M_AXI_ID_WIDTH = 1,
parameter C_M_AXI_AWUSER_WIDTH = 1,
parameter C_M_AXI_WUSER_WIDTH = 1,
parameter C_M_AXI_BUSER_WIDTH = 1,
parameter C_M_AXI_ARUSER_WIDTH = 1,
parameter C_M_AXI_RUSER_WIDTH = 1
)
(
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
input m_axi_aclk,
input m_axi_aresetn,
// Write address channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_M_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [7:0] m_axi_awlen,
output [2:0] m_axi_awsize,
output [1:0] m_axi_awburst,
output [1:0] m_axi_awlock,
output [3:0] m_axi_awcache,
output [2:0] m_axi_awprot,
output [3:0] m_axi_awregion,
output [3:0] m_axi_awqos,
output [C_M_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
// Write data channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [(C_M_AXI_DATA_WIDTH/8)-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_M_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
// Write response channel
input [C_M_AXI_ID_WIDTH-1:0] m_axi_bid,
input [1:0] m_axi_bresp,
input m_axi_bvalid,
input [C_M_AXI_BUSER_WIDTH-1:0] m_axi_buser,
output m_axi_bready,
// Read address channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_M_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [7:0] m_axi_arlen,
output [2:0] m_axi_arsize,
output [1:0] m_axi_arburst,
output [1:0] m_axi_arlock,
output [3:0] m_axi_arcache,
output [2:0] m_axi_arprot,
output [3:0] m_axi_arregion,
output [3:0] m_axi_arqos,
output [C_M_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
// Read data channel
input [C_M_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [1:0] m_axi_rresp,
input m_axi_rlast,
input [C_M_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
output m_axi_bresp_err,
output m_axi_rresp_err,
output pcie_rx_fifo_rd_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
output pcie_rx_fifo_free_en,
output [9:4] pcie_rx_fifo_free_len,
input pcie_rx_fifo_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n,
input pcie_user_clk,
input pcie_user_rst_n,
input dev_rx_cmd_wr_en,
input [29:0] dev_rx_cmd_wr_data,
output dev_rx_cmd_full_n,
input dev_tx_cmd_wr_en,
input [29:0] dev_tx_cmd_wr_data,
output dev_tx_cmd_full_n,
output dma_rx_done_wr_en,
output [20:0] dma_rx_done_wr_data,
input dma_rx_done_wr_rdy_n
);
wire w_dev_rx_cmd_rd_en;
wire [29:0] w_dev_rx_cmd_rd_data;
wire w_dev_rx_cmd_empty_n;
wire w_dev_tx_cmd_rd_en;
wire [29:0] w_dev_tx_cmd_rd_data;
wire w_dev_tx_cmd_empty_n;
dev_rx_cmd_fifo
dev_rx_cmd_fifo_inst0
(
.wr_clk (pcie_user_clk),
.wr_rst_n (pcie_user_rst_n),
.wr_en (dev_rx_cmd_wr_en),
.wr_data (dev_rx_cmd_wr_data),
.full_n (dev_rx_cmd_full_n),
.rd_clk (m_axi_aclk),
.rd_rst_n (m_axi_aresetn & pcie_user_rst_n),
.rd_en (w_dev_rx_cmd_rd_en),
.rd_data (w_dev_rx_cmd_rd_data),
.empty_n (w_dev_rx_cmd_empty_n)
);
dev_tx_cmd_fifo
dev_tx_cmd_fifo_inst0
(
.wr_clk (pcie_user_clk),
.wr_rst_n (pcie_user_rst_n),
.wr_en (dev_tx_cmd_wr_en),
.wr_data (dev_tx_cmd_wr_data),
.full_n (dev_tx_cmd_full_n),
.rd_clk (m_axi_aclk),
.rd_rst_n (m_axi_aresetn & pcie_user_rst_n),
.rd_en (w_dev_tx_cmd_rd_en),
.rd_data (w_dev_tx_cmd_rd_data),
.empty_n (w_dev_tx_cmd_empty_n)
);
m_axi_write # (
.C_M_AXI_ADDR_WIDTH (C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_ID_WIDTH (C_M_AXI_ID_WIDTH),
.C_M_AXI_AWUSER_WIDTH (C_M_AXI_AWUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH (C_M_AXI_WUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH (C_M_AXI_BUSER_WIDTH)
)
m_axi_write_inst0(
////////////////////////////////////////////////////////////////
//AXI4 master write channel signal
.m_axi_aclk (m_axi_aclk),
.m_axi_aresetn (m_axi_aresetn),
// Write address channel
.m_axi_awid (m_axi_awid),
.m_axi_awaddr (m_axi_awaddr),
.m_axi_awlen (m_axi_awlen),
.m_axi_awsize (m_axi_awsize),
.m_axi_awburst (m_axi_awburst),
.m_axi_awlock (m_axi_awlock),
.m_axi_awcache (m_axi_awcache),
.m_axi_awprot (m_axi_awprot),
.m_axi_awregion (m_axi_awregion),
.m_axi_awqos (m_axi_awqos),
.m_axi_awuser (m_axi_awuser),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_awready (m_axi_awready),
// Write data channel
.m_axi_wid (m_axi_wid),
.m_axi_wdata (m_axi_wdata),
.m_axi_wstrb (m_axi_wstrb),
.m_axi_wlast (m_axi_wlast),
.m_axi_wuser (m_axi_wuser),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_wready (m_axi_wready),
// Write response channel
.m_axi_bid (m_axi_bid),
.m_axi_bresp (m_axi_bresp),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_buser (m_axi_buser),
.m_axi_bready (m_axi_bready),
.m_axi_bresp_err (m_axi_bresp_err),
.dev_rx_cmd_rd_en (w_dev_rx_cmd_rd_en),
.dev_rx_cmd_rd_data (w_dev_rx_cmd_rd_data),
.dev_rx_cmd_empty_n (w_dev_rx_cmd_empty_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
m_axi_read # (
.C_M_AXI_ADDR_WIDTH (C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_ID_WIDTH (C_M_AXI_ID_WIDTH),
.C_M_AXI_ARUSER_WIDTH (C_M_AXI_ARUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH (C_M_AXI_RUSER_WIDTH)
)
m_axi_read_inst0(
////////////////////////////////////////////////////////////////
//AXI4 master read channel signals
.m_axi_aclk (m_axi_aclk),
.m_axi_aresetn (m_axi_aresetn),
// Read address channel
.m_axi_arid (m_axi_arid),
.m_axi_araddr (m_axi_araddr),
.m_axi_arlen (m_axi_arlen),
.m_axi_arsize (m_axi_arsize),
.m_axi_arburst (m_axi_arburst),
.m_axi_arlock (m_axi_arlock),
.m_axi_arcache (m_axi_arcache),
.m_axi_arprot (m_axi_arprot),
.m_axi_arregion (m_axi_arregion),
.m_axi_arqos (m_axi_arqos),
.m_axi_aruser (m_axi_aruser),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_arready (m_axi_arready),
// Read data channel
.m_axi_rid (m_axi_rid),
.m_axi_rdata (m_axi_rdata),
.m_axi_rresp (m_axi_rresp),
.m_axi_rlast (m_axi_rlast),
.m_axi_ruser (m_axi_ruser),
.m_axi_rvalid (m_axi_rvalid),
.m_axi_rready (m_axi_rready),
.m_axi_rresp_err (m_axi_rresp_err),
.dev_tx_cmd_rd_en (w_dev_tx_cmd_rd_en),
.dev_tx_cmd_rd_data (w_dev_tx_cmd_rd_data),
.dev_tx_cmd_empty_n (w_dev_tx_cmd_empty_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module m_axi_dma # (
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 64,
parameter C_M_AXI_ID_WIDTH = 1,
parameter C_M_AXI_AWUSER_WIDTH = 1,
parameter C_M_AXI_WUSER_WIDTH = 1,
parameter C_M_AXI_BUSER_WIDTH = 1,
parameter C_M_AXI_ARUSER_WIDTH = 1,
parameter C_M_AXI_RUSER_WIDTH = 1
)
(
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
input m_axi_aclk,
input m_axi_aresetn,
// Write address channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_M_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [7:0] m_axi_awlen,
output [2:0] m_axi_awsize,
output [1:0] m_axi_awburst,
output [1:0] m_axi_awlock,
output [3:0] m_axi_awcache,
output [2:0] m_axi_awprot,
output [3:0] m_axi_awregion,
output [3:0] m_axi_awqos,
output [C_M_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
// Write data channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [(C_M_AXI_DATA_WIDTH/8)-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_M_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
// Write response channel
input [C_M_AXI_ID_WIDTH-1:0] m_axi_bid,
input [1:0] m_axi_bresp,
input m_axi_bvalid,
input [C_M_AXI_BUSER_WIDTH-1:0] m_axi_buser,
output m_axi_bready,
// Read address channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_M_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [7:0] m_axi_arlen,
output [2:0] m_axi_arsize,
output [1:0] m_axi_arburst,
output [1:0] m_axi_arlock,
output [3:0] m_axi_arcache,
output [2:0] m_axi_arprot,
output [3:0] m_axi_arregion,
output [3:0] m_axi_arqos,
output [C_M_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
// Read data channel
input [C_M_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [1:0] m_axi_rresp,
input m_axi_rlast,
input [C_M_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
output m_axi_bresp_err,
output m_axi_rresp_err,
output pcie_rx_fifo_rd_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
output pcie_rx_fifo_free_en,
output [9:4] pcie_rx_fifo_free_len,
input pcie_rx_fifo_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n,
input pcie_user_clk,
input pcie_user_rst_n,
input dev_rx_cmd_wr_en,
input [29:0] dev_rx_cmd_wr_data,
output dev_rx_cmd_full_n,
input dev_tx_cmd_wr_en,
input [29:0] dev_tx_cmd_wr_data,
output dev_tx_cmd_full_n,
output dma_rx_done_wr_en,
output [20:0] dma_rx_done_wr_data,
input dma_rx_done_wr_rdy_n
);
wire w_dev_rx_cmd_rd_en;
wire [29:0] w_dev_rx_cmd_rd_data;
wire w_dev_rx_cmd_empty_n;
wire w_dev_tx_cmd_rd_en;
wire [29:0] w_dev_tx_cmd_rd_data;
wire w_dev_tx_cmd_empty_n;
dev_rx_cmd_fifo
dev_rx_cmd_fifo_inst0
(
.wr_clk (pcie_user_clk),
.wr_rst_n (pcie_user_rst_n),
.wr_en (dev_rx_cmd_wr_en),
.wr_data (dev_rx_cmd_wr_data),
.full_n (dev_rx_cmd_full_n),
.rd_clk (m_axi_aclk),
.rd_rst_n (m_axi_aresetn & pcie_user_rst_n),
.rd_en (w_dev_rx_cmd_rd_en),
.rd_data (w_dev_rx_cmd_rd_data),
.empty_n (w_dev_rx_cmd_empty_n)
);
dev_tx_cmd_fifo
dev_tx_cmd_fifo_inst0
(
.wr_clk (pcie_user_clk),
.wr_rst_n (pcie_user_rst_n),
.wr_en (dev_tx_cmd_wr_en),
.wr_data (dev_tx_cmd_wr_data),
.full_n (dev_tx_cmd_full_n),
.rd_clk (m_axi_aclk),
.rd_rst_n (m_axi_aresetn & pcie_user_rst_n),
.rd_en (w_dev_tx_cmd_rd_en),
.rd_data (w_dev_tx_cmd_rd_data),
.empty_n (w_dev_tx_cmd_empty_n)
);
m_axi_write # (
.C_M_AXI_ADDR_WIDTH (C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_ID_WIDTH (C_M_AXI_ID_WIDTH),
.C_M_AXI_AWUSER_WIDTH (C_M_AXI_AWUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH (C_M_AXI_WUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH (C_M_AXI_BUSER_WIDTH)
)
m_axi_write_inst0(
////////////////////////////////////////////////////////////////
//AXI4 master write channel signal
.m_axi_aclk (m_axi_aclk),
.m_axi_aresetn (m_axi_aresetn),
// Write address channel
.m_axi_awid (m_axi_awid),
.m_axi_awaddr (m_axi_awaddr),
.m_axi_awlen (m_axi_awlen),
.m_axi_awsize (m_axi_awsize),
.m_axi_awburst (m_axi_awburst),
.m_axi_awlock (m_axi_awlock),
.m_axi_awcache (m_axi_awcache),
.m_axi_awprot (m_axi_awprot),
.m_axi_awregion (m_axi_awregion),
.m_axi_awqos (m_axi_awqos),
.m_axi_awuser (m_axi_awuser),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_awready (m_axi_awready),
// Write data channel
.m_axi_wid (m_axi_wid),
.m_axi_wdata (m_axi_wdata),
.m_axi_wstrb (m_axi_wstrb),
.m_axi_wlast (m_axi_wlast),
.m_axi_wuser (m_axi_wuser),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_wready (m_axi_wready),
// Write response channel
.m_axi_bid (m_axi_bid),
.m_axi_bresp (m_axi_bresp),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_buser (m_axi_buser),
.m_axi_bready (m_axi_bready),
.m_axi_bresp_err (m_axi_bresp_err),
.dev_rx_cmd_rd_en (w_dev_rx_cmd_rd_en),
.dev_rx_cmd_rd_data (w_dev_rx_cmd_rd_data),
.dev_rx_cmd_empty_n (w_dev_rx_cmd_empty_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
m_axi_read # (
.C_M_AXI_ADDR_WIDTH (C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_ID_WIDTH (C_M_AXI_ID_WIDTH),
.C_M_AXI_ARUSER_WIDTH (C_M_AXI_ARUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH (C_M_AXI_RUSER_WIDTH)
)
m_axi_read_inst0(
////////////////////////////////////////////////////////////////
//AXI4 master read channel signals
.m_axi_aclk (m_axi_aclk),
.m_axi_aresetn (m_axi_aresetn),
// Read address channel
.m_axi_arid (m_axi_arid),
.m_axi_araddr (m_axi_araddr),
.m_axi_arlen (m_axi_arlen),
.m_axi_arsize (m_axi_arsize),
.m_axi_arburst (m_axi_arburst),
.m_axi_arlock (m_axi_arlock),
.m_axi_arcache (m_axi_arcache),
.m_axi_arprot (m_axi_arprot),
.m_axi_arregion (m_axi_arregion),
.m_axi_arqos (m_axi_arqos),
.m_axi_aruser (m_axi_aruser),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_arready (m_axi_arready),
// Read data channel
.m_axi_rid (m_axi_rid),
.m_axi_rdata (m_axi_rdata),
.m_axi_rresp (m_axi_rresp),
.m_axi_rlast (m_axi_rlast),
.m_axi_ruser (m_axi_ruser),
.m_axi_rvalid (m_axi_rvalid),
.m_axi_rready (m_axi_rready),
.m_axi_rresp_err (m_axi_rresp_err),
.dev_tx_cmd_rd_en (w_dev_tx_cmd_rd_en),
.dev_tx_cmd_rd_data (w_dev_tx_cmd_rd_data),
.dev_tx_cmd_empty_n (w_dev_tx_cmd_empty_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n)
);
endmodule |
module cmd_reader
(//System
input reset, input txclk, input [31:0] adc_time,
//FX2 Side
output reg skip, output reg rdreq,
input [31:0] fifodata, input pkt_waiting,
//Rx side
input rx_WR_enabled, output reg [15:0] rx_databus,
output reg rx_WR, output reg rx_WR_done,
//register io
input wire [31:0] reg_data_out, output reg [31:0] reg_data_in,
output reg [6:0] reg_addr, output reg [1:0] reg_io_enable,
output wire [14:0] debug, output reg stop, output reg [15:0] stop_time);
// States
parameter IDLE = 4'd0;
parameter HEADER = 4'd1;
parameter TIMESTAMP = 4'd2;
parameter WAIT = 4'd3;
parameter TEST = 4'd4;
parameter SEND = 4'd5;
parameter PING = 4'd6;
parameter WRITE_REG = 4'd7;
parameter WRITE_REG_MASKED = 4'd8;
parameter READ_REG = 4'd9;
parameter DELAY = 4'd14;
`define OP_PING_FIXED 8'd0
`define OP_PING_FIXED_REPLY 8'd1
`define OP_WRITE_REG 8'd2
`define OP_WRITE_REG_MASKED 8'd3
`define OP_READ_REG 8'd4
`define OP_READ_REG_REPLY 8'd5
`define OP_DELAY 8'd12
reg [6:0] payload;
reg [6:0] payload_read;
reg [3:0] state;
reg [15:0] high;
reg [15:0] low;
reg pending;
reg [31:0] value0;
reg [31:0] value1;
reg [31:0] value2;
reg [1:0] lines_in;
reg [1:0] lines_out;
reg [1:0] lines_out_total;
`define JITTER 5
`define OP_CODE 31:24
`define PAYLOAD 8:2
wire [7:0] ops;
assign ops = value0[`OP_CODE];
assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled, value0[2:0], ops[2:0]};
always @(posedge txclk)
if (reset)
begin
pending <= 0;
state <= IDLE;
skip <= 0;
rdreq <= 0;
rx_WR <= 0;
reg_io_enable <= 0;
reg_data_in <= 0;
reg_addr <= 0;
stop <= 0;
end
else case (state)
IDLE :
begin
payload_read <= 0;
skip <= 0;
lines_in <= 0;
if(pkt_waiting)
begin
state <= HEADER;
rdreq <= 1;
end
end
HEADER :
begin
payload <= fifodata[`PAYLOAD];
state <= TIMESTAMP;
end
TIMESTAMP :
begin
value0 <= fifodata;
state <= WAIT;
rdreq <= 0;
end
WAIT :
begin
// Let's send it
if ((value0 <= adc_time + `JITTER
&& value0 > adc_time)
|| value0 == 32'hFFFFFFFF)
state <= TEST;
// Wait a little bit more
else if (value0 > adc_time + `JITTER)
state <= WAIT;
// Outdated
else if (value0 < adc_time)
begin
state <= IDLE;
skip <= 1;
end
end
TEST :
begin
reg_io_enable <= 0;
rx_WR <= 0;
rx_WR_done <= 1;
stop <= 0;
if (payload_read == payload)
begin
skip <= 1;
state <= IDLE;
rdreq <= 0;
end
else
begin
value0 <= fifodata;
lines_in <= 2'd1;
rdreq <= 1;
payload_read <= payload_read + 7'd1;
lines_out <= 0;
case (fifodata[`OP_CODE])
`OP_PING_FIXED:
begin
state <= PING;
end
`OP_WRITE_REG:
begin
state <= WRITE_REG;
pending <= 1;
end
`OP_WRITE_REG_MASKED:
begin
state <= WRITE_REG_MASKED;
pending <= 1;
end
`OP_READ_REG:
begin
state <= READ_REG;
end
`OP_DELAY:
begin
state <= DELAY;
end
default:
begin
//error, skip this packet
skip <= 1;
state <= IDLE;
end
endcase
end
end
SEND:
begin
rdreq <= 0;
rx_WR_done <= 0;
if (pending)
begin
rx_WR <= 1;
rx_databus <= high;
pending <= 0;
if (lines_out == lines_out_total)
state <= TEST;
else case (ops)
`OP_READ_REG:
begin
state <= READ_REG;
end
default:
begin
state <= TEST;
end
endcase
end
else
begin
if (rx_WR_enabled)
begin
rx_WR <= 1;
rx_databus <= low;
pending <= 1;
lines_out <= lines_out + 2'd1;
end
else
rx_WR <= 0;
end
end
PING:
begin
rx_WR <= 0;
rdreq <= 0;
rx_WR_done <= 0;
lines_out_total <= 2'd1;
pending <= 0;
state <= SEND;
high <= {`OP_PING_FIXED_REPLY, 8'd2};
low <= value0[15:0];
end
READ_REG:
begin
rx_WR <= 0;
rx_WR_done <= 0;
rdreq <= 0;
lines_out_total <= 2'd2;
pending <= 0;
state <= SEND;
if (lines_out == 0)
begin
high <= {`OP_READ_REG_REPLY, 8'd6};
low <= value0[15:0];
reg_io_enable <= 2'd3;
reg_addr <= value0[6:0];
end
else
begin
high <= reg_data_out[31:16];
low <= reg_data_out[15:0];
end
end
WRITE_REG:
begin
rx_WR <= 0;
if (pending)
pending <= 0;
else
begin
if (lines_in == 2'd1)
begin
payload_read <= payload_read + 7'd1;
lines_in <= lines_in + 2'd1;
value1 <= fifodata;
rdreq <= 0;
end
else
begin
reg_io_enable <= 2'd2;
reg_data_in <= value1;
reg_addr <= value0[6:0];
state <= TEST;
end
end
end
WRITE_REG_MASKED:
begin
rx_WR <= 0;
if (pending)
pending <= 0;
else
begin
if (lines_in == 2'd1)
begin
rdreq <= 1;
payload_read <= payload_read + 7'd1;
lines_in <= lines_in + 2'd1;
value1 <= fifodata;
end
else if (lines_in == 2'd2)
begin
rdreq <= 0;
payload_read <= payload_read + 7'd1;
lines_in <= lines_in + 2'd1;
value2 <= fifodata;
end
else
begin
reg_io_enable <= 2'd2;
reg_data_in <= (value1 & value2);
reg_addr <= value0[6:0];
state <= TEST;
end
end
end
DELAY :
begin
rdreq <= 0;
stop <= 1;
stop_time <= value0[15:0];
state <= TEST;
end
default :
begin
//error state handling
state <= IDLE;
end
endcase
endmodule
|
module cmd_reader
(//System
input reset, input txclk, input [31:0] adc_time,
//FX2 Side
output reg skip, output reg rdreq,
input [31:0] fifodata, input pkt_waiting,
//Rx side
input rx_WR_enabled, output reg [15:0] rx_databus,
output reg rx_WR, output reg rx_WR_done,
//register io
input wire [31:0] reg_data_out, output reg [31:0] reg_data_in,
output reg [6:0] reg_addr, output reg [1:0] reg_io_enable,
output wire [14:0] debug, output reg stop, output reg [15:0] stop_time);
// States
parameter IDLE = 4'd0;
parameter HEADER = 4'd1;
parameter TIMESTAMP = 4'd2;
parameter WAIT = 4'd3;
parameter TEST = 4'd4;
parameter SEND = 4'd5;
parameter PING = 4'd6;
parameter WRITE_REG = 4'd7;
parameter WRITE_REG_MASKED = 4'd8;
parameter READ_REG = 4'd9;
parameter DELAY = 4'd14;
`define OP_PING_FIXED 8'd0
`define OP_PING_FIXED_REPLY 8'd1
`define OP_WRITE_REG 8'd2
`define OP_WRITE_REG_MASKED 8'd3
`define OP_READ_REG 8'd4
`define OP_READ_REG_REPLY 8'd5
`define OP_DELAY 8'd12
reg [6:0] payload;
reg [6:0] payload_read;
reg [3:0] state;
reg [15:0] high;
reg [15:0] low;
reg pending;
reg [31:0] value0;
reg [31:0] value1;
reg [31:0] value2;
reg [1:0] lines_in;
reg [1:0] lines_out;
reg [1:0] lines_out_total;
`define JITTER 5
`define OP_CODE 31:24
`define PAYLOAD 8:2
wire [7:0] ops;
assign ops = value0[`OP_CODE];
assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled, value0[2:0], ops[2:0]};
always @(posedge txclk)
if (reset)
begin
pending <= 0;
state <= IDLE;
skip <= 0;
rdreq <= 0;
rx_WR <= 0;
reg_io_enable <= 0;
reg_data_in <= 0;
reg_addr <= 0;
stop <= 0;
end
else case (state)
IDLE :
begin
payload_read <= 0;
skip <= 0;
lines_in <= 0;
if(pkt_waiting)
begin
state <= HEADER;
rdreq <= 1;
end
end
HEADER :
begin
payload <= fifodata[`PAYLOAD];
state <= TIMESTAMP;
end
TIMESTAMP :
begin
value0 <= fifodata;
state <= WAIT;
rdreq <= 0;
end
WAIT :
begin
// Let's send it
if ((value0 <= adc_time + `JITTER
&& value0 > adc_time)
|| value0 == 32'hFFFFFFFF)
state <= TEST;
// Wait a little bit more
else if (value0 > adc_time + `JITTER)
state <= WAIT;
// Outdated
else if (value0 < adc_time)
begin
state <= IDLE;
skip <= 1;
end
end
TEST :
begin
reg_io_enable <= 0;
rx_WR <= 0;
rx_WR_done <= 1;
stop <= 0;
if (payload_read == payload)
begin
skip <= 1;
state <= IDLE;
rdreq <= 0;
end
else
begin
value0 <= fifodata;
lines_in <= 2'd1;
rdreq <= 1;
payload_read <= payload_read + 7'd1;
lines_out <= 0;
case (fifodata[`OP_CODE])
`OP_PING_FIXED:
begin
state <= PING;
end
`OP_WRITE_REG:
begin
state <= WRITE_REG;
pending <= 1;
end
`OP_WRITE_REG_MASKED:
begin
state <= WRITE_REG_MASKED;
pending <= 1;
end
`OP_READ_REG:
begin
state <= READ_REG;
end
`OP_DELAY:
begin
state <= DELAY;
end
default:
begin
//error, skip this packet
skip <= 1;
state <= IDLE;
end
endcase
end
end
SEND:
begin
rdreq <= 0;
rx_WR_done <= 0;
if (pending)
begin
rx_WR <= 1;
rx_databus <= high;
pending <= 0;
if (lines_out == lines_out_total)
state <= TEST;
else case (ops)
`OP_READ_REG:
begin
state <= READ_REG;
end
default:
begin
state <= TEST;
end
endcase
end
else
begin
if (rx_WR_enabled)
begin
rx_WR <= 1;
rx_databus <= low;
pending <= 1;
lines_out <= lines_out + 2'd1;
end
else
rx_WR <= 0;
end
end
PING:
begin
rx_WR <= 0;
rdreq <= 0;
rx_WR_done <= 0;
lines_out_total <= 2'd1;
pending <= 0;
state <= SEND;
high <= {`OP_PING_FIXED_REPLY, 8'd2};
low <= value0[15:0];
end
READ_REG:
begin
rx_WR <= 0;
rx_WR_done <= 0;
rdreq <= 0;
lines_out_total <= 2'd2;
pending <= 0;
state <= SEND;
if (lines_out == 0)
begin
high <= {`OP_READ_REG_REPLY, 8'd6};
low <= value0[15:0];
reg_io_enable <= 2'd3;
reg_addr <= value0[6:0];
end
else
begin
high <= reg_data_out[31:16];
low <= reg_data_out[15:0];
end
end
WRITE_REG:
begin
rx_WR <= 0;
if (pending)
pending <= 0;
else
begin
if (lines_in == 2'd1)
begin
payload_read <= payload_read + 7'd1;
lines_in <= lines_in + 2'd1;
value1 <= fifodata;
rdreq <= 0;
end
else
begin
reg_io_enable <= 2'd2;
reg_data_in <= value1;
reg_addr <= value0[6:0];
state <= TEST;
end
end
end
WRITE_REG_MASKED:
begin
rx_WR <= 0;
if (pending)
pending <= 0;
else
begin
if (lines_in == 2'd1)
begin
rdreq <= 1;
payload_read <= payload_read + 7'd1;
lines_in <= lines_in + 2'd1;
value1 <= fifodata;
end
else if (lines_in == 2'd2)
begin
rdreq <= 0;
payload_read <= payload_read + 7'd1;
lines_in <= lines_in + 2'd1;
value2 <= fifodata;
end
else
begin
reg_io_enable <= 2'd2;
reg_data_in <= (value1 & value2);
reg_addr <= value0[6:0];
state <= TEST;
end
end
end
DELAY :
begin
rdreq <= 0;
stop <= 1;
stop_time <= value0[15:0];
state <= TEST;
end
default :
begin
//error state handling
state <= IDLE;
end
endcase
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dev_tx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 30,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dev_tx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 30,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule |
// niosii_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
niosii_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// niosii_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
niosii_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// niosii_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
niosii_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test suba (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subb (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subc (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Don't flatten out these modules please:
// verilator no_inline_module
// Labeled cover
cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test suba (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subb (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subc (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Don't flatten out these modules please:
// verilator no_inline_module
// Labeled cover
cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test suba (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subb (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subc (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Don't flatten out these modules please:
// verilator no_inline_module
// Labeled cover
cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_done # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output dma_done_rd_en,
input [20:0] dma_done_rd_data,
input dma_done_empty_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt
);
localparam LP_NLB_WR_DELAY = 1;
localparam S_IDLE = 11'b00000000001;
localparam S_DMA_INFO = 11'b00000000010;
localparam S_NLB_RD_WAIT = 11'b00000000100;
localparam S_NLB_INFO = 11'b00000001000;
localparam S_NLB_CALC = 11'b00000010000;
localparam S_NLB_WR_WAIT = 11'b00000100000;
localparam S_NLB_WR = 11'b00001000000;
localparam S_NLB_WR_DELAY = 11'b00010000000;
localparam S_CQ_WR_WAIT = 11'b00100000000;
localparam S_CQ_WR = 11'b01000000000;
localparam S_NLB_DONE = 11'b10000000000;
reg [10:0] cur_state;
reg [10:0] next_state;
reg r_dma_cmd_type;
reg r_dma_done_check;
reg r_dma_dir;
reg [6:0] r_hcmd_slot_tag;
reg [12:2] r_dma_len;
reg [20:2] r_hcmd_data_len;
reg r_dma_done_rd_en;
reg r_hcmd_nlb_wr1_en;
reg r_hcmd_cq_wr0_en;
reg r_dma_rx_direct_done_en;
reg r_dma_tx_direct_done_en;
reg r_dma_rx_done_en;
reg r_dma_tx_done_en;
reg r_dma_rx_direct_done_en_d1;
reg r_dma_tx_direct_done_en_d1;
reg r_dma_rx_done_en_d1;
reg r_dma_tx_done_en_d1;
reg r_dma_rx_direct_done_en_sync;
reg r_dma_tx_direct_done_en_sync;
reg r_dma_rx_done_en_sync;
reg r_dma_tx_done_en_sync;
reg [3:0] r_nlb_wr_delay;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_direct_done;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_direct_done;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_done;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_done;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_direct_done_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_direct_done_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_done_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_done_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_direct_done_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_direct_done_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_rx_done_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_dma_tx_done_d2;
reg [7:0] r_dma_rx_direct_done_cnt;
reg [7:0] r_dma_tx_direct_done_cnt;
reg [7:0] r_dma_rx_done_cnt;
reg [7:0] r_dma_tx_done_cnt;
assign dma_done_rd_en = r_dma_done_rd_en;
assign hcmd_nlb_rd_addr = r_hcmd_slot_tag;
assign hcmd_nlb_wr1_en = r_hcmd_nlb_wr1_en;
assign hcmd_nlb_wr1_addr = r_hcmd_slot_tag;
assign hcmd_nlb_wr1_data = r_hcmd_data_len;
assign hcmd_cq_wr0_en = r_hcmd_cq_wr0_en;
assign hcmd_cq_wr0_data0 = {26'b0, r_hcmd_slot_tag, 1'b0, 1'b1};
assign hcmd_cq_wr0_data1 = 35'b0;
assign dma_rx_direct_done_cnt = r_dma_rx_direct_done_cnt;
assign dma_tx_direct_done_cnt = r_dma_tx_direct_done_cnt;
assign dma_rx_done_cnt = r_dma_rx_done_cnt;
assign dma_tx_done_cnt = r_dma_tx_done_cnt;
always @ (posedge cpu_bus_clk or negedge cpu_bus_rst_n)
begin
if(cpu_bus_rst_n == 0) begin
r_dma_rx_direct_done_cnt <= 0;
r_dma_tx_direct_done_cnt <= 0;
r_dma_rx_done_cnt <= 0;
r_dma_tx_done_cnt <= 0;
end
else begin
if(r_dma_rx_direct_done_d1 == 1 && r_dma_rx_direct_done_d2 == 0)
r_dma_rx_direct_done_cnt <= r_dma_rx_direct_done_cnt + 1;
if(r_dma_tx_direct_done_d1 == 1 && r_dma_tx_direct_done_d2 == 0)
r_dma_tx_direct_done_cnt <= r_dma_tx_direct_done_cnt + 1;
if(r_dma_rx_done_d1 == 1 && r_dma_rx_done_d2 == 0)
r_dma_rx_done_cnt <= r_dma_rx_done_cnt + 1;
if(r_dma_tx_done_d1 == 1 && r_dma_tx_done_d2 == 0)
r_dma_tx_done_cnt <= r_dma_tx_done_cnt + 1;
end
end
always @ (posedge cpu_bus_clk)
begin
r_dma_rx_direct_done <= r_dma_rx_direct_done_en_sync;
r_dma_tx_direct_done <= r_dma_tx_direct_done_en_sync;
r_dma_rx_done <= r_dma_rx_done_en_sync;
r_dma_tx_done <= r_dma_tx_done_en_sync;
r_dma_rx_direct_done_d1 <= r_dma_rx_direct_done;
r_dma_tx_direct_done_d1 <= r_dma_tx_direct_done;
r_dma_rx_done_d1 <= r_dma_rx_done;
r_dma_tx_done_d1 <= r_dma_tx_done;
r_dma_rx_direct_done_d2 <= r_dma_rx_direct_done_d1;
r_dma_tx_direct_done_d2 <= r_dma_tx_direct_done_d1;
r_dma_rx_done_d2 <= r_dma_rx_done_d1;
r_dma_tx_done_d2 <= r_dma_tx_done_d1;
end
always @ (posedge pcie_user_clk)
begin
r_dma_rx_direct_done_en_d1 <= r_dma_rx_direct_done_en;
r_dma_tx_direct_done_en_d1 <= r_dma_tx_direct_done_en;
r_dma_rx_done_en_d1 <= r_dma_rx_done_en;
r_dma_tx_done_en_d1 <= r_dma_tx_done_en;
r_dma_rx_direct_done_en_sync <= r_dma_rx_direct_done_en | r_dma_rx_direct_done_en_d1;
r_dma_tx_direct_done_en_sync <= r_dma_tx_direct_done_en | r_dma_tx_direct_done_en_d1;
r_dma_rx_done_en_sync <= r_dma_rx_done_en | r_dma_rx_done_en_d1;
r_dma_tx_done_en_sync <= r_dma_tx_done_en | r_dma_tx_done_en_d1;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(dma_done_empty_n == 1'b1)
next_state <= S_DMA_INFO;
else
next_state <= S_IDLE;
end
S_DMA_INFO: begin
next_state <= S_NLB_RD_WAIT;
end
S_NLB_RD_WAIT: begin
if(r_dma_cmd_type == 1)
next_state <= S_NLB_DONE;
else
next_state <= S_NLB_INFO;
end
S_NLB_INFO: begin
next_state <= S_NLB_CALC;
end
S_NLB_CALC: begin
if(r_hcmd_data_len == r_dma_len)
next_state <= S_CQ_WR_WAIT;
else
next_state <= S_NLB_WR_WAIT;
end
S_NLB_WR_WAIT: begin
if(hcmd_nlb_wr1_rdy_n == 1)
next_state <= S_NLB_WR_WAIT;
else
next_state <= S_NLB_WR;
end
S_NLB_WR: begin
next_state <= S_NLB_WR_DELAY;
end
S_NLB_WR_DELAY: begin
if(r_nlb_wr_delay == 0)
next_state <= S_NLB_DONE;
else
next_state <= S_NLB_WR_DELAY;
end
S_CQ_WR_WAIT: begin
if(hcmd_cq_wr0_rdy_n == 1)
next_state <= S_CQ_WR_WAIT;
else
next_state <= S_CQ_WR;
end
S_CQ_WR: begin
next_state <= S_NLB_DONE;
end
S_NLB_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_DMA_INFO: begin
r_dma_cmd_type <= dma_done_rd_data[20];
r_dma_done_check <= dma_done_rd_data[19];
r_dma_dir <= dma_done_rd_data[18];
r_hcmd_slot_tag <= dma_done_rd_data[17:11];
r_dma_len <= dma_done_rd_data[10:0];
end
S_NLB_RD_WAIT: begin
end
S_NLB_INFO: begin
r_hcmd_data_len <= hcmd_nlb_rd_data;
end
S_NLB_CALC: begin
r_hcmd_data_len <= r_hcmd_data_len - r_dma_len;
end
S_NLB_WR_WAIT: begin
end
S_NLB_WR: begin
r_nlb_wr_delay <= LP_NLB_WR_DELAY;
end
S_NLB_WR_DELAY: begin
r_nlb_wr_delay <= r_nlb_wr_delay - 1;
end
S_CQ_WR_WAIT: begin
end
S_CQ_WR: begin
end
S_NLB_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_DMA_INFO: begin
r_dma_done_rd_en <= 1;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_RD_WAIT: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_INFO: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_CALC: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_WR_WAIT: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_WR: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 1;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_WR_DELAY: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_CQ_WR_WAIT: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_CQ_WR: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 1;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
S_NLB_DONE: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= r_dma_cmd_type & r_dma_done_check & ~r_dma_dir;
r_dma_tx_direct_done_en <= r_dma_cmd_type & r_dma_done_check & r_dma_dir;
r_dma_rx_done_en <= ~r_dma_cmd_type & r_dma_done_check & ~r_dma_dir;
r_dma_tx_done_en <= ~r_dma_cmd_type & r_dma_done_check & r_dma_dir;
end
default: begin
r_dma_done_rd_en <= 0;
r_hcmd_nlb_wr1_en <= 0;
r_hcmd_cq_wr0_en <= 0;
r_dma_rx_direct_done_en <= 0;
r_dma_tx_direct_done_en <= 0;
r_dma_rx_done_en <= 0;
r_dma_tx_done_en <= 0;
end
endcase
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_done_fifo # (
parameter P_FIFO_DATA_WIDTH = 21,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input clk,
input rst_n,
input wr0_en,
input [P_FIFO_DATA_WIDTH-1:0] wr0_data,
output wr0_rdy_n,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n,
input wr1_clk,
input wr1_rst_n,
input wr1_en,
input [P_FIFO_DATA_WIDTH-1:0] wr1_data,
output wr1_rdy_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
localparam S_IDLE = 2'b01;
localparam S_WRITE = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg r_wr0_req;
reg r_wr1_req;
reg r_wr0_req_ack;
reg r_wr1_req_ack;
reg [1:0] r_wr_gnt;
wire w_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d2;
reg r_wr1_en_sync;
reg r_wr1_en_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d2;
reg r_wr1_rdy_n;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data_sync;
reg r_wr_en;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr_data;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr0_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data;
assign wr0_rdy_n = r_wr0_req;
assign wr1_rdy_n = r_wr1_rdy_n;
always @(posedge wr1_clk)
begin
r_wr1_en_sync_d1 <= wr1_en;
r_wr1_en_sync <= r_wr1_en_sync_d1 | wr1_en;
if(wr1_en == 1) begin
r_wr1_data_sync <= wr1_data;
end
r_wr1_rdy_n_sync <= r_wr1_req;
r_wr1_rdy_n_sync_d1 <= r_wr1_rdy_n_sync;
r_wr1_rdy_n_sync_d2 <= r_wr1_rdy_n_sync_d1;
end
always @(posedge wr1_clk or negedge wr1_rst_n)
begin
if(wr1_rst_n == 0) begin
r_wr1_rdy_n <= 0;
end
else begin
if(wr1_en == 1)
r_wr1_rdy_n <= 1;
else if(r_wr1_rdy_n_sync_d1 == 0 && r_wr1_rdy_n_sync_d2 == 1)
r_wr1_rdy_n <= 0;
end
end
assign w_wr1_en = r_wr1_en_d1 & ~r_wr1_en_d2;
always @(posedge clk)
begin
if(wr0_en == 1) begin
r_wr0_data <= wr0_data;
end
r_wr1_en <= r_wr1_en_sync;
r_wr1_en_d1 <= r_wr1_en;
r_wr1_en_d2 <= r_wr1_en_d1;
if(w_wr1_en == 1) begin
r_wr1_data <= r_wr1_data_sync;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_wr0_req <= 0;
r_wr1_req <= 0;
end
else begin
if(r_wr0_req_ack == 1)
r_wr0_req <= 0;
else if(wr0_en == 1)
r_wr0_req <= 1;
if(r_wr1_req_ack == 1)
r_wr1_req <= 0;
else if(w_wr1_en == 1)
r_wr1_req <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if((r_wr0_req == 1 || r_wr1_req == 1) && (full_n == 1))
next_state <= S_WRITE;
else
next_state <= S_IDLE;
end
S_WRITE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge clk)
begin
case(cur_state)
S_IDLE: begin
if(r_wr0_req == 1)
r_wr_gnt <= 2'b01;
else if(r_wr1_req == 1)
r_wr_gnt <= 2'b10;
end
S_WRITE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE: begin
r_wr_en <= 1;
r_wr0_req_ack <= r_wr_gnt[0];
r_wr1_req_ack <= r_wr_gnt[1];
end
default: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
endcase
end
always @ (*)
begin
case(r_wr_gnt) // synthesis parallel_case full_case
2'b01: r_wr_data <= r_wr0_data;
2'b10: r_wr_data <= r_wr1_data;
endcase
end
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (r_wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (r_wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (r_wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_done_fifo # (
parameter P_FIFO_DATA_WIDTH = 21,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input clk,
input rst_n,
input wr0_en,
input [P_FIFO_DATA_WIDTH-1:0] wr0_data,
output wr0_rdy_n,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n,
input wr1_clk,
input wr1_rst_n,
input wr1_en,
input [P_FIFO_DATA_WIDTH-1:0] wr1_data,
output wr1_rdy_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
localparam S_IDLE = 2'b01;
localparam S_WRITE = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg r_wr0_req;
reg r_wr1_req;
reg r_wr0_req_ack;
reg r_wr1_req_ack;
reg [1:0] r_wr_gnt;
wire w_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d2;
reg r_wr1_en_sync;
reg r_wr1_en_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d2;
reg r_wr1_rdy_n;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data_sync;
reg r_wr_en;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr_data;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr0_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data;
assign wr0_rdy_n = r_wr0_req;
assign wr1_rdy_n = r_wr1_rdy_n;
always @(posedge wr1_clk)
begin
r_wr1_en_sync_d1 <= wr1_en;
r_wr1_en_sync <= r_wr1_en_sync_d1 | wr1_en;
if(wr1_en == 1) begin
r_wr1_data_sync <= wr1_data;
end
r_wr1_rdy_n_sync <= r_wr1_req;
r_wr1_rdy_n_sync_d1 <= r_wr1_rdy_n_sync;
r_wr1_rdy_n_sync_d2 <= r_wr1_rdy_n_sync_d1;
end
always @(posedge wr1_clk or negedge wr1_rst_n)
begin
if(wr1_rst_n == 0) begin
r_wr1_rdy_n <= 0;
end
else begin
if(wr1_en == 1)
r_wr1_rdy_n <= 1;
else if(r_wr1_rdy_n_sync_d1 == 0 && r_wr1_rdy_n_sync_d2 == 1)
r_wr1_rdy_n <= 0;
end
end
assign w_wr1_en = r_wr1_en_d1 & ~r_wr1_en_d2;
always @(posedge clk)
begin
if(wr0_en == 1) begin
r_wr0_data <= wr0_data;
end
r_wr1_en <= r_wr1_en_sync;
r_wr1_en_d1 <= r_wr1_en;
r_wr1_en_d2 <= r_wr1_en_d1;
if(w_wr1_en == 1) begin
r_wr1_data <= r_wr1_data_sync;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_wr0_req <= 0;
r_wr1_req <= 0;
end
else begin
if(r_wr0_req_ack == 1)
r_wr0_req <= 0;
else if(wr0_en == 1)
r_wr0_req <= 1;
if(r_wr1_req_ack == 1)
r_wr1_req <= 0;
else if(w_wr1_en == 1)
r_wr1_req <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if((r_wr0_req == 1 || r_wr1_req == 1) && (full_n == 1))
next_state <= S_WRITE;
else
next_state <= S_IDLE;
end
S_WRITE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge clk)
begin
case(cur_state)
S_IDLE: begin
if(r_wr0_req == 1)
r_wr_gnt <= 2'b01;
else if(r_wr1_req == 1)
r_wr_gnt <= 2'b10;
end
S_WRITE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE: begin
r_wr_en <= 1;
r_wr0_req_ack <= r_wr_gnt[0];
r_wr1_req_ack <= r_wr_gnt[1];
end
default: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
endcase
end
always @ (*)
begin
case(r_wr_gnt) // synthesis parallel_case full_case
2'b01: r_wr_data <= r_wr0_data;
2'b10: r_wr_data <= r_wr1_data;
endcase
end
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (r_wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (r_wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (r_wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_done_fifo # (
parameter P_FIFO_DATA_WIDTH = 21,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input clk,
input rst_n,
input wr0_en,
input [P_FIFO_DATA_WIDTH-1:0] wr0_data,
output wr0_rdy_n,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n,
input wr1_clk,
input wr1_rst_n,
input wr1_en,
input [P_FIFO_DATA_WIDTH-1:0] wr1_data,
output wr1_rdy_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
localparam S_IDLE = 2'b01;
localparam S_WRITE = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg r_wr0_req;
reg r_wr1_req;
reg r_wr0_req_ack;
reg r_wr1_req_ack;
reg [1:0] r_wr_gnt;
wire w_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d2;
reg r_wr1_en_sync;
reg r_wr1_en_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d2;
reg r_wr1_rdy_n;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data_sync;
reg r_wr_en;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr_data;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr0_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data;
assign wr0_rdy_n = r_wr0_req;
assign wr1_rdy_n = r_wr1_rdy_n;
always @(posedge wr1_clk)
begin
r_wr1_en_sync_d1 <= wr1_en;
r_wr1_en_sync <= r_wr1_en_sync_d1 | wr1_en;
if(wr1_en == 1) begin
r_wr1_data_sync <= wr1_data;
end
r_wr1_rdy_n_sync <= r_wr1_req;
r_wr1_rdy_n_sync_d1 <= r_wr1_rdy_n_sync;
r_wr1_rdy_n_sync_d2 <= r_wr1_rdy_n_sync_d1;
end
always @(posedge wr1_clk or negedge wr1_rst_n)
begin
if(wr1_rst_n == 0) begin
r_wr1_rdy_n <= 0;
end
else begin
if(wr1_en == 1)
r_wr1_rdy_n <= 1;
else if(r_wr1_rdy_n_sync_d1 == 0 && r_wr1_rdy_n_sync_d2 == 1)
r_wr1_rdy_n <= 0;
end
end
assign w_wr1_en = r_wr1_en_d1 & ~r_wr1_en_d2;
always @(posedge clk)
begin
if(wr0_en == 1) begin
r_wr0_data <= wr0_data;
end
r_wr1_en <= r_wr1_en_sync;
r_wr1_en_d1 <= r_wr1_en;
r_wr1_en_d2 <= r_wr1_en_d1;
if(w_wr1_en == 1) begin
r_wr1_data <= r_wr1_data_sync;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_wr0_req <= 0;
r_wr1_req <= 0;
end
else begin
if(r_wr0_req_ack == 1)
r_wr0_req <= 0;
else if(wr0_en == 1)
r_wr0_req <= 1;
if(r_wr1_req_ack == 1)
r_wr1_req <= 0;
else if(w_wr1_en == 1)
r_wr1_req <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if((r_wr0_req == 1 || r_wr1_req == 1) && (full_n == 1))
next_state <= S_WRITE;
else
next_state <= S_IDLE;
end
S_WRITE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge clk)
begin
case(cur_state)
S_IDLE: begin
if(r_wr0_req == 1)
r_wr_gnt <= 2'b01;
else if(r_wr1_req == 1)
r_wr_gnt <= 2'b10;
end
S_WRITE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE: begin
r_wr_en <= 1;
r_wr0_req_ack <= r_wr_gnt[0];
r_wr1_req_ack <= r_wr_gnt[1];
end
default: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
endcase
end
always @ (*)
begin
case(r_wr_gnt) // synthesis parallel_case full_case
2'b01: r_wr_data <= r_wr0_data;
2'b10: r_wr_data <= r_wr1_data;
endcase
end
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (r_wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (r_wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (r_wr_en)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle; initial toggle=0;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
alpha a1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
alpha a2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
tsk t1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
off o1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= '0;
if (cyc==3) begin
toggle <= '1;
end
else if (cyc==5) begin
`ifdef VERILATOR
$c("call_task();");
`else
call_task();
`endif
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task call_task;
/* verilator public */
t1.center_task(1'b1);
endtask
endmodule
module alpha (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.a*",2)
// t.a1 and t.a2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't even get added
// verilator coverage_block_off
$write("");
end
end
endmodule
module beta (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
if (0) begin
// CHECK_COVER(-1,"top.v.b*",0)
// Make sure that we don't optimize away zero buckets
end
if (toggle) begin
// CHECK_COVER(-1,"top.v.b*",2)
// t.b1 and t.b2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't
// verilator coverage_block_off
$write("");
end
end
endmodule
module tsk (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
center_task(1'b0);
end
task center_task;
input external;
begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.t1",1)
end
if (external) begin
// CHECK_COVER(-1,"top.v.t1",1)
$write("[%0t] Got external pulse\n", $time);
end
end
endtask
endmodule
module off (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
// verilator coverage_off
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// because under coverage_module_off
end
end
// verilator coverage_on
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.o1",1)
// because under coverage_module_off
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle; initial toggle=0;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
alpha a1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
alpha a2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
beta b2 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
tsk t1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
off o1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= '0;
if (cyc==3) begin
toggle <= '1;
end
else if (cyc==5) begin
`ifdef VERILATOR
$c("call_task();");
`else
call_task();
`endif
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
task call_task;
/* verilator public */
t1.center_task(1'b1);
endtask
endmodule
module alpha (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.a*",2)
// t.a1 and t.a2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't even get added
// verilator coverage_block_off
$write("");
end
end
endmodule
module beta (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
if (0) begin
// CHECK_COVER(-1,"top.v.b*",0)
// Make sure that we don't optimize away zero buckets
end
if (toggle) begin
// CHECK_COVER(-1,"top.v.b*",2)
// t.b1 and t.b2 collapse to a count of 2
end
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// This doesn't
// verilator coverage_block_off
$write("");
end
end
endmodule
module tsk (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
/* verilator public_module */
always @ (posedge clk) begin
center_task(1'b0);
end
task center_task;
input external;
begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.t1",1)
end
if (external) begin
// CHECK_COVER(-1,"top.v.t1",1)
$write("[%0t] Got external pulse\n", $time);
end
end
endtask
endmodule
module off (/*AUTOARG*/
// Inputs
clk, toggle
);
input clk;
input toggle;
// verilator coverage_off
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER_MISSING(-1)
// because under coverage_module_off
end
end
// verilator coverage_on
always @ (posedge clk) begin
if (toggle) begin
// CHECK_COVER(-1,"top.v.o1",1)
// because under coverage_module_off
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t;
sub a (.inst(1));
sub b (.inst(2));
// Returns integer line number, or -1 for all ok
import "DPI-C" context function int dpix_run_tests();
export "DPI-C" task dpix_t_int;
task dpix_t_int(input int i, output int o); o = ~i; endtask
export "DPI-C" dpix_t_renamed = task dpix_t_ren;
task dpix_t_ren(input int i, output int o); o = i+2; endtask
export "DPI-C" function dpix_int123;
function int dpix_int123(); dpix_int123 = 32'h123; endfunction
export "DPI-C" function dpix_f_bit;
export "DPI-C" function dpix_f_bit15;
export "DPI-C" function dpix_f_int;
export "DPI-C" function dpix_f_byte;
export "DPI-C" function dpix_f_shortint;
export "DPI-C" function dpix_f_longint;
export "DPI-C" function dpix_f_chandle;
function bit dpix_f_bit (bit i); dpix_f_bit = ~i; endfunction
function bit [14:0] dpix_f_bit15 (bit [14:0] i); dpix_f_bit15 = ~i; endfunction
function int dpix_f_int (int i); dpix_f_int = ~i; endfunction
function byte dpix_f_byte (byte i); dpix_f_byte = ~i; endfunction
function shortint dpix_f_shortint(shortint i); dpix_f_shortint = ~i; endfunction
function longint dpix_f_longint (longint i); dpix_f_longint = ~i; endfunction
function chandle dpix_f_chandle (chandle i); dpix_f_chandle = i; endfunction
export "DPI-C" task dpix_t_bit95;
task dpix_t_bit95(input bit [94:0] i, output bit [94:0] o); o = ~i; endtask
export "DPI-C" task dpix_t_bit96;
task dpix_t_bit96(input bit [95:0] i, output bit [95:0] o); o = ~i; endtask
int lineno;
initial begin
lineno = dpix_run_tests();
if (lineno != -1) begin
$display("[%0t] %%Error: t_dpix_ort_c.c:%0d: dpix_run_tests returned an error", $time, lineno);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub (input int inst);
export "DPI-C" function dpix_sub_inst;
function int dpix_sub_inst (int i); dpix_sub_inst = inst + i; endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [89:0] in;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [89:0] out; // From test of Test.v
wire [44:0] line0;
wire [44:0] line1;
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[89:0]),
.line0 (line0[44:0]),
.line1 (line1[44:0]),
// Inputs
.clk (clk),
.in (in[89:0]));
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF;
end
else if (cyc==10) begin
if (in==out) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$write("*-* Failed!! *-*\n");
$finish;
end
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
line0, line1, out,
// Inputs
clk, in
);
input clk;
input [89:0] in;
output reg [44:0] line0;
output reg [44:0] line1;
output reg [89:0] out;
assign {line0,line1} = in;
always @(posedge clk) begin
out <= {line0,line1};
end
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SRAM (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_design_SRAM.hex";
output [ 31: 0] readdata;
input [ 14: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 20480,
the_altsyncram.numwords_a = 20480,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 15;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SRAM (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_design_SRAM.hex";
output [ 31: 0] readdata;
input [ 14: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 20480,
the_altsyncram.numwords_a = 20480,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 15;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SRAM (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_design_SRAM.hex";
output [ 31: 0] readdata;
input [ 14: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 20480,
the_altsyncram.numwords_a = 20480,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 15;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SRAM (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_design_SRAM.hex";
output [ 31: 0] readdata;
input [ 14: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 20480,
the_altsyncram.numwords_a = 20480,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 15;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SRAM (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_design_SRAM.hex";
output [ 31: 0] readdata;
input [ 14: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 20480,
the_altsyncram.numwords_a = 20480,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 15;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
wire noswap = crc[32];
wire nibble = crc[33];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
wire [31:0] swapped; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
.swapped (swapped[31:0]),
// Inputs
.clk (clk),
.noswap (noswap),
.nibble (nibble),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h89522c3f5e5ca324) $stop;
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, swapped,
// Inputs
clk, noswap, nibble, in
);
input clk;
input noswap;
input nibble;
input [31:0] in;
output [31:0] out;
output [31:0] swapped;
function [7:0] EndianSwap;
input Nibble;
input [7:0] Data;
begin
EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3],
Data[4], Data[5], Data[6], Data[7] }
: { 4'h0, Data[0], Data[1], Data[2], Data[3] });
end
endfunction
assign out[31:24] = (noswap ? in[31:24]
: EndianSwap(nibble, in[31:24]));
assign out[23:16] = (noswap ? in[23:16]
: EndianSwap(nibble, in[23:16]));
assign out[15:8] = (noswap ? in[15:8]
: EndianSwap(nibble, in[15:8]));
assign out[7:0] = (noswap ? in[7:0]
: EndianSwap(nibble, in[7:0]));
reg [31:0] swapped;
always @(posedge clk) begin
swapped[31:24] <= EndianSwap(nibble, in[31:24]);
swapped[23:16] <= EndianSwap(nibble, in[23:16]);
swapped[15:8] <= EndianSwap(nibble, in[15:8] );
swapped[7:0] <= EndianSwap(nibble, in[7:0] );
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
wire noswap = crc[32];
wire nibble = crc[33];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
wire [31:0] swapped; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
.swapped (swapped[31:0]),
// Inputs
.clk (clk),
.noswap (noswap),
.nibble (nibble),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h89522c3f5e5ca324) $stop;
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, swapped,
// Inputs
clk, noswap, nibble, in
);
input clk;
input noswap;
input nibble;
input [31:0] in;
output [31:0] out;
output [31:0] swapped;
function [7:0] EndianSwap;
input Nibble;
input [7:0] Data;
begin
EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3],
Data[4], Data[5], Data[6], Data[7] }
: { 4'h0, Data[0], Data[1], Data[2], Data[3] });
end
endfunction
assign out[31:24] = (noswap ? in[31:24]
: EndianSwap(nibble, in[31:24]));
assign out[23:16] = (noswap ? in[23:16]
: EndianSwap(nibble, in[23:16]));
assign out[15:8] = (noswap ? in[15:8]
: EndianSwap(nibble, in[15:8]));
assign out[7:0] = (noswap ? in[7:0]
: EndianSwap(nibble, in[7:0]));
reg [31:0] swapped;
always @(posedge clk) begin
swapped[31:24] <= EndianSwap(nibble, in[31:24]);
swapped[23:16] <= EndianSwap(nibble, in[23:16]);
swapped[15:8] <= EndianSwap(nibble, in[15:8] );
swapped[7:0] <= EndianSwap(nibble, in[7:0] );
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_fifo # (
parameter P_FIFO_DATA_WIDTH = 19,
parameter P_FIFO_DEPTH_WIDTH = 7
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_fifo # (
parameter P_FIFO_DATA_WIDTH = 19,
parameter P_FIFO_DEPTH_WIDTH = 7
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule
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