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/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_cq_fifo # (
parameter P_FIFO_DATA_WIDTH = 35,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr0_en,
input [P_FIFO_DATA_WIDTH-1:0] wr0_data0,
input [P_FIFO_DATA_WIDTH-1:0] wr0_data1,
output wr0_rdy_n,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n,
input wr1_clk,
input wr1_rst_n,
input wr1_en,
input [P_FIFO_DATA_WIDTH-1:0] wr1_data0,
input [P_FIFO_DATA_WIDTH-1:0] wr1_data1,
output wr1_rdy_n
);
localparam P_FIFO_ALLOC_WIDTH = 1; //128 bits
localparam S_IDLE = 3'b001;
localparam S_WRITE0 = 3'b010;
localparam S_WRITE1 = 3'b100;
reg [2:0] cur_state;
reg [2:0] next_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg r_wr0_req;
reg r_wr1_req;
reg r_wr0_req_ack;
reg r_wr1_req_ack;
reg [3:0] r_wr_gnt;
wire w_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d2;
reg r_wr1_en_sync;
reg r_wr1_en_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d2;
reg r_wr1_rdy_n;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data0_sync;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data1_sync;
reg r_wr_en;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr_data;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr0_data0;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr0_data1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data0;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data1;
assign wr0_rdy_n = r_wr0_req;
assign wr1_rdy_n = r_wr1_rdy_n;
always @(posedge wr1_clk)
begin
r_wr1_en_sync_d1 <= wr1_en;
r_wr1_en_sync <= wr1_en | r_wr1_en_sync_d1;
if(wr1_en == 1) begin
r_wr1_data0_sync <= wr1_data0;
r_wr1_data1_sync <= wr1_data1;
end
r_wr1_rdy_n_sync <= r_wr1_req;
r_wr1_rdy_n_sync_d1 <= r_wr1_rdy_n_sync;
r_wr1_rdy_n_sync_d2 <= r_wr1_rdy_n_sync_d1;
end
always @(posedge wr1_clk or negedge wr1_rst_n)
begin
if(wr1_rst_n == 0) begin
r_wr1_rdy_n <= 0;
end
else begin
if(wr1_en == 1)
r_wr1_rdy_n <= 1;
else if(r_wr1_rdy_n_sync_d1 == 0 && r_wr1_rdy_n_sync_d2 == 1)
r_wr1_rdy_n <= 0;
end
end
assign w_wr1_en = r_wr1_en_d1 & ~r_wr1_en_d2;
always @(posedge clk)
begin
if(wr0_en == 1) begin
r_wr0_data0 <= wr0_data0;
r_wr0_data1 <= wr0_data1;
end
r_wr1_en <= r_wr1_en_sync;
r_wr1_en_d1 <= r_wr1_en;
r_wr1_en_d2 <= r_wr1_en_d1;
if(w_wr1_en == 1) begin
r_wr1_data0 <= r_wr1_data0_sync;
r_wr1_data1 <= r_wr1_data1_sync;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_wr0_req <= 0;
r_wr1_req <= 0;
end
else begin
if(r_wr0_req_ack == 1)
r_wr0_req <= 0;
else if(wr0_en == 1)
r_wr0_req <= 1;
if(r_wr1_req_ack == 1)
r_wr1_req <= 0;
else if(w_wr1_en == 1)
r_wr1_req <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if((r_wr0_req == 1 || r_wr1_req == 1) && (full_n == 1))
next_state <= S_WRITE0;
else
next_state <= S_IDLE;
end
S_WRITE0: begin
next_state <= S_WRITE1;
end
S_WRITE1: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge clk)
begin
case(cur_state)
S_IDLE: begin
if(r_wr0_req == 1)
r_wr_gnt <= 4'b0001;
else if(r_wr1_req == 1)
r_wr_gnt <= 4'b0100;
end
S_WRITE0: begin
r_wr_gnt <= {r_wr_gnt[2:0], 1'b0};
end
S_WRITE1: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE0: begin
r_wr_en <= 1;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE1: begin
r_wr_en <= 1;
r_wr0_req_ack <= r_wr_gnt[1];
r_wr1_req_ack <= r_wr_gnt[3];
end
default: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
endcase
end
always @ (*)
begin
case(r_wr_gnt) // synthesis parallel_case full_case
4'b0001: r_wr_data <= r_wr0_data0;
4'b0010: r_wr_data <= r_wr0_data1;
4'b0100: r_wr_data <= r_wr1_data0;
4'b1000: r_wr_data <= r_wr1_data1;
endcase
end
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (r_wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (r_wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (r_wr_en)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [1:0] in;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] out10; // From test of Test.v
wire [1:0] out32; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out32 (out32[1:0]),
.out10 (out10[1:0]),
// Inputs
.in (in[1:0]));
// Test loop
always @ (posedge clk) begin
in <= in + 1;
`ifdef TEST_VERBOSE
$write("[%0t] in=%d out32=%d out10=%d\n",$time, in, out32, out10);
`endif
if (in==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out32, out10,
// Inputs
in
);
input [1:0] in;
output [1:0] out32;
output [1:0] out10;
assign out32 = in[3:2];
assign out10 = in[1:0];
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_req # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input arb_sq_rdy,
input [3:0] sq_qid,
input [C_PCIE_ADDR_WIDTH-1:2] hcmd_pcie_addr,
output sq_hcmd_ack,
input hcmd_slot_rdy,
input [6:0] hcmd_slot_tag,
output hcmd_slot_alloc_en,
output pcie_sq_cmd_fifo_wr_en,
output [10:0] pcie_sq_cmd_fifo_wr_data,
input pcie_sq_cmd_fifo_full_n,
output pcie_sq_rx_tag_alloc,
output [7:0] pcie_sq_rx_alloc_tag,
output [6:4] pcie_sq_rx_tag_alloc_len,
input pcie_sq_rx_tag_full_n,
input pcie_sq_rx_fifo_full_n,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack
);
localparam LP_HCMD_PCIE_TAG_PREFIX = 5'b00000;
localparam LP_HCMD_PCIE_SIZE = 10'h10;
localparam S_IDLE = 6'b000001;
localparam S_CMD_INFO = 6'b000010;
localparam S_CHECK_FIFO = 6'b000100;
localparam S_PCIE_MRD_REQ = 6'b001000;
localparam S_PCIE_MRD_ACK = 6'b010000;
localparam S_PCIE_MRD_DONE = 6'b100000;
reg [5:0] cur_state;
reg [5:0] next_state;
reg r_sq_hcmd_ack;
reg r_hcmd_slot_alloc_en;
reg r_tx_mrd_req;
reg [2:0] r_hcmd_pcie_tag;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_pcie_addr;
reg r_hcmd_pcie_tag_update;
reg [3:0] r_sq_qid;
reg [6:0] r_hcmd_slot_tag;
reg r_pcie_sq_cmd_fifo_wr_en;
reg r_pcie_sq_rx_tag_alloc;
assign sq_hcmd_ack = r_sq_hcmd_ack;
assign hcmd_slot_alloc_en = r_hcmd_slot_alloc_en;
assign pcie_sq_cmd_fifo_wr_en = r_pcie_sq_cmd_fifo_wr_en;
assign pcie_sq_cmd_fifo_wr_data = {r_sq_qid, r_hcmd_slot_tag};
assign pcie_sq_rx_tag_alloc = r_pcie_sq_rx_tag_alloc;
assign pcie_sq_rx_alloc_tag = {LP_HCMD_PCIE_TAG_PREFIX, r_hcmd_pcie_tag};
assign pcie_sq_rx_tag_alloc_len = 3'b100;
assign tx_mrd_req = r_tx_mrd_req;
assign tx_mrd_tag = {LP_HCMD_PCIE_TAG_PREFIX, r_hcmd_pcie_tag};
assign tx_mrd_len = LP_HCMD_PCIE_SIZE;
assign tx_mrd_addr = r_hcmd_pcie_addr;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(arb_sq_rdy == 1 && hcmd_slot_rdy == 1)
next_state <= S_CMD_INFO;
else
next_state <= S_IDLE;
end
S_CMD_INFO: begin
next_state <= S_CHECK_FIFO;
end
S_CHECK_FIFO: begin
if(pcie_sq_cmd_fifo_full_n == 1 && pcie_sq_rx_tag_full_n == 1 && pcie_sq_rx_fifo_full_n == 1)
next_state <= S_PCIE_MRD_REQ;
else
next_state <= S_CHECK_FIFO;
end
S_PCIE_MRD_REQ: begin
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_ACK: begin
if(tx_mrd_req_ack == 1)
next_state <= S_PCIE_MRD_DONE;
else
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_hcmd_pcie_tag <= 0;
end
else begin
if(r_hcmd_pcie_tag_update == 1)
r_hcmd_pcie_tag <= r_hcmd_pcie_tag + 1;
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CMD_INFO: begin
r_sq_qid <= sq_qid;
r_hcmd_pcie_addr <= hcmd_pcie_addr;
r_hcmd_slot_tag <= hcmd_slot_tag;
end
S_CHECK_FIFO: begin
end
S_PCIE_MRD_REQ: begin
end
S_PCIE_MRD_ACK: begin
end
S_PCIE_MRD_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_CMD_INFO: begin
r_sq_hcmd_ack <= 1;
r_hcmd_slot_alloc_en <= 1;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_CHECK_FIFO: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_REQ: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 1;
r_pcie_sq_rx_tag_alloc <= 1;
r_tx_mrd_req <= 1;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_ACK: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_DONE: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 1;
end
default: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
endcase
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_req # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input arb_sq_rdy,
input [3:0] sq_qid,
input [C_PCIE_ADDR_WIDTH-1:2] hcmd_pcie_addr,
output sq_hcmd_ack,
input hcmd_slot_rdy,
input [6:0] hcmd_slot_tag,
output hcmd_slot_alloc_en,
output pcie_sq_cmd_fifo_wr_en,
output [10:0] pcie_sq_cmd_fifo_wr_data,
input pcie_sq_cmd_fifo_full_n,
output pcie_sq_rx_tag_alloc,
output [7:0] pcie_sq_rx_alloc_tag,
output [6:4] pcie_sq_rx_tag_alloc_len,
input pcie_sq_rx_tag_full_n,
input pcie_sq_rx_fifo_full_n,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack
);
localparam LP_HCMD_PCIE_TAG_PREFIX = 5'b00000;
localparam LP_HCMD_PCIE_SIZE = 10'h10;
localparam S_IDLE = 6'b000001;
localparam S_CMD_INFO = 6'b000010;
localparam S_CHECK_FIFO = 6'b000100;
localparam S_PCIE_MRD_REQ = 6'b001000;
localparam S_PCIE_MRD_ACK = 6'b010000;
localparam S_PCIE_MRD_DONE = 6'b100000;
reg [5:0] cur_state;
reg [5:0] next_state;
reg r_sq_hcmd_ack;
reg r_hcmd_slot_alloc_en;
reg r_tx_mrd_req;
reg [2:0] r_hcmd_pcie_tag;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_pcie_addr;
reg r_hcmd_pcie_tag_update;
reg [3:0] r_sq_qid;
reg [6:0] r_hcmd_slot_tag;
reg r_pcie_sq_cmd_fifo_wr_en;
reg r_pcie_sq_rx_tag_alloc;
assign sq_hcmd_ack = r_sq_hcmd_ack;
assign hcmd_slot_alloc_en = r_hcmd_slot_alloc_en;
assign pcie_sq_cmd_fifo_wr_en = r_pcie_sq_cmd_fifo_wr_en;
assign pcie_sq_cmd_fifo_wr_data = {r_sq_qid, r_hcmd_slot_tag};
assign pcie_sq_rx_tag_alloc = r_pcie_sq_rx_tag_alloc;
assign pcie_sq_rx_alloc_tag = {LP_HCMD_PCIE_TAG_PREFIX, r_hcmd_pcie_tag};
assign pcie_sq_rx_tag_alloc_len = 3'b100;
assign tx_mrd_req = r_tx_mrd_req;
assign tx_mrd_tag = {LP_HCMD_PCIE_TAG_PREFIX, r_hcmd_pcie_tag};
assign tx_mrd_len = LP_HCMD_PCIE_SIZE;
assign tx_mrd_addr = r_hcmd_pcie_addr;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(arb_sq_rdy == 1 && hcmd_slot_rdy == 1)
next_state <= S_CMD_INFO;
else
next_state <= S_IDLE;
end
S_CMD_INFO: begin
next_state <= S_CHECK_FIFO;
end
S_CHECK_FIFO: begin
if(pcie_sq_cmd_fifo_full_n == 1 && pcie_sq_rx_tag_full_n == 1 && pcie_sq_rx_fifo_full_n == 1)
next_state <= S_PCIE_MRD_REQ;
else
next_state <= S_CHECK_FIFO;
end
S_PCIE_MRD_REQ: begin
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_ACK: begin
if(tx_mrd_req_ack == 1)
next_state <= S_PCIE_MRD_DONE;
else
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_hcmd_pcie_tag <= 0;
end
else begin
if(r_hcmd_pcie_tag_update == 1)
r_hcmd_pcie_tag <= r_hcmd_pcie_tag + 1;
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CMD_INFO: begin
r_sq_qid <= sq_qid;
r_hcmd_pcie_addr <= hcmd_pcie_addr;
r_hcmd_slot_tag <= hcmd_slot_tag;
end
S_CHECK_FIFO: begin
end
S_PCIE_MRD_REQ: begin
end
S_PCIE_MRD_ACK: begin
end
S_PCIE_MRD_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_CMD_INFO: begin
r_sq_hcmd_ack <= 1;
r_hcmd_slot_alloc_en <= 1;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_CHECK_FIFO: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_REQ: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 1;
r_pcie_sq_rx_tag_alloc <= 1;
r_tx_mrd_req <= 1;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_ACK: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
S_PCIE_MRD_DONE: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 1;
end
default: begin
r_sq_hcmd_ack <= 0;
r_hcmd_slot_alloc_en <= 0;
r_pcie_sq_cmd_fifo_wr_en <= 0;
r_pcie_sq_rx_tag_alloc <= 0;
r_tx_mrd_req <= 0;
r_hcmd_pcie_tag_update <= 0;
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Simple cover
cover property (@(posedge clk) cyc==3);
// With statement, in generate
generate if (1) begin
cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4");
end
endgenerate
// Labeled cover
cyc_eq_5:
cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
// Using default clock
default clocking @(posedge clk); endclocking
cover property (cyc==6) $display("*COVER: Cyc==6");
// Disable statement
// Note () after disable are required
cover property (@(posedge clk) disable iff (toggle) cyc==8)
$display("*COVER: Cyc==8");
cover property (@(posedge clk) disable iff (!toggle) cyc==8)
$stop;
//============================================================
// Using a macro and generate
wire reset = (cyc < 2);
`define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn))
genvar i;
generate
for (i=0; i<32; i=i+1)
begin: cycval
CycCover_i: `covclk( cyc[i] );
end
endgenerate
`ifndef verilator // Unsupported
//============================================================
// Using a more complicated property
property C1;
@(posedge clk)
disable iff (!toggle)
cyc==5;
endproperty
cover property (C1) $display("*COVER: Cyc==5");
// Using covergroup
// Note a covergroup is really inheritance of a special system "covergroup" class.
covergroup counter1 @ (posedge cyc);
// Automatic methods: stop(), start(), sample(), set_inst_name()
// Each bin value must be <= 32 bits. Strange.
cyc_value : coverpoint cyc {
}
cyc_bined : coverpoint cyc {
bins zero = {0};
bins low = {1,5};
// Note 5 is also in the bin above. Only the first bin matching is counted.
bins mid = {[5:$]};
// illegal_bins // Has precidence over "first matching bin", creates assertion
// ignore_bins // Not counted, and not part of total
}
toggle : coverpoint (toggle) {
bins off = {0};
bins on = {1};
}
cyc5 : coverpoint (cyc==5) {
bins five = {1};
}
// option.at_least = {number}; // Default 1 - Hits to be considered covered
// option.auto_bin_max = {number}; // Default 64
// option.comment = {string}
// option.goal = {number}; // Default 90%
// option.name = {string}
// option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1)
// option.weight = {number}; // Default 1
// CROSS
value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n>
cross cyc_value, toggle;
endgroup
counter1 c1 = new();
`endif
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Simple cover
cover property (@(posedge clk) cyc==3);
// With statement, in generate
generate if (1) begin
cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4");
end
endgenerate
// Labeled cover
cyc_eq_5:
cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
// Using default clock
default clocking @(posedge clk); endclocking
cover property (cyc==6) $display("*COVER: Cyc==6");
// Disable statement
// Note () after disable are required
cover property (@(posedge clk) disable iff (toggle) cyc==8)
$display("*COVER: Cyc==8");
cover property (@(posedge clk) disable iff (!toggle) cyc==8)
$stop;
//============================================================
// Using a macro and generate
wire reset = (cyc < 2);
`define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn))
genvar i;
generate
for (i=0; i<32; i=i+1)
begin: cycval
CycCover_i: `covclk( cyc[i] );
end
endgenerate
`ifndef verilator // Unsupported
//============================================================
// Using a more complicated property
property C1;
@(posedge clk)
disable iff (!toggle)
cyc==5;
endproperty
cover property (C1) $display("*COVER: Cyc==5");
// Using covergroup
// Note a covergroup is really inheritance of a special system "covergroup" class.
covergroup counter1 @ (posedge cyc);
// Automatic methods: stop(), start(), sample(), set_inst_name()
// Each bin value must be <= 32 bits. Strange.
cyc_value : coverpoint cyc {
}
cyc_bined : coverpoint cyc {
bins zero = {0};
bins low = {1,5};
// Note 5 is also in the bin above. Only the first bin matching is counted.
bins mid = {[5:$]};
// illegal_bins // Has precidence over "first matching bin", creates assertion
// ignore_bins // Not counted, and not part of total
}
toggle : coverpoint (toggle) {
bins off = {0};
bins on = {1};
}
cyc5 : coverpoint (cyc==5) {
bins five = {1};
}
// option.at_least = {number}; // Default 1 - Hits to be considered covered
// option.auto_bin_max = {number}; // Default 64
// option.comment = {string}
// option.goal = {number}; // Default 90%
// option.name = {string}
// option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1)
// option.weight = {number}; // Default 1
// CROSS
value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n>
cross cyc_value, toggle;
endgroup
counter1 c1 = new();
`endif
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_arb # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] admin_sq_size,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
output arb_sq_rdy,
output [3:0] sq_qid,
output [C_PCIE_ADDR_WIDTH-1:2] hcmd_pcie_addr,
input sq_hcmd_ack
);
localparam S_ARB_HCMD = 5'b00001;
localparam S_LOAD_HEAD_PTR = 5'b00010;
localparam S_CALC_ADDR = 5'b00100;
localparam S_GNT_HCMD = 5'b01000;
localparam S_UPDATE_HEAD_PTR = 5'b10000;
reg [4:0] cur_state;
reg [4:0] next_state;
reg [7:0] r_admin_sq_head_ptr;
reg [7:0] r_io_sq1_head_ptr;
reg [7:0] r_io_sq2_head_ptr;
reg [7:0] r_io_sq3_head_ptr;
reg [7:0] r_io_sq4_head_ptr;
reg [7:0] r_io_sq5_head_ptr;
reg [7:0] r_io_sq6_head_ptr;
reg [7:0] r_io_sq7_head_ptr;
reg [7:0] r_io_sq8_head_ptr;
reg r_arb_sq_rdy;
reg [3:0] r_sq_qid;
reg [7:0] r_sq_head_ptr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_pcie_addr;
wire [8:0] w_sq_entry_valid;
wire w_sq_entry_valid_ok;
reg [8:0] r_sq_entry_valid;
wire [8:0] w_sq_valid_mask;
reg [8:0] r_sq_update_entry;
wire [8:0] w_sq_rst_n;
assign arb_sq_rdy = r_arb_sq_rdy;
assign sq_qid = r_sq_qid;
assign hcmd_pcie_addr = r_hcmd_pcie_addr;
assign w_sq_entry_valid[0] = (r_admin_sq_head_ptr != admin_sq_tail_ptr) & sq_valid[0];
assign w_sq_entry_valid[1] = (r_io_sq1_head_ptr != io_sq1_tail_ptr) & sq_valid[1];
assign w_sq_entry_valid[2] = (r_io_sq2_head_ptr != io_sq2_tail_ptr) & sq_valid[2];
assign w_sq_entry_valid[3] = (r_io_sq3_head_ptr != io_sq3_tail_ptr) & sq_valid[3];
assign w_sq_entry_valid[4] = (r_io_sq4_head_ptr != io_sq4_tail_ptr) & sq_valid[4];
assign w_sq_entry_valid[5] = (r_io_sq5_head_ptr != io_sq5_tail_ptr) & sq_valid[5];
assign w_sq_entry_valid[6] = (r_io_sq6_head_ptr != io_sq6_tail_ptr) & sq_valid[6];
assign w_sq_entry_valid[7] = (r_io_sq7_head_ptr != io_sq7_tail_ptr) & sq_valid[7];
assign w_sq_entry_valid[8] = (r_io_sq8_head_ptr != io_sq8_tail_ptr) & sq_valid[8];
assign w_sq_valid_mask = {r_sq_entry_valid[7:0], r_sq_entry_valid[8]};
assign w_sq_entry_valid_ok = ((w_sq_entry_valid[8:1] & w_sq_valid_mask[8:1]) != 0) | w_sq_entry_valid[0];
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_ARB_HCMD;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid_ok == 1)
next_state <= S_LOAD_HEAD_PTR;
else
next_state <= S_ARB_HCMD;
end
S_LOAD_HEAD_PTR: begin
next_state <= S_CALC_ADDR;
end
S_CALC_ADDR: begin
next_state <= S_GNT_HCMD;
end
S_GNT_HCMD: begin
if(sq_hcmd_ack == 1)
next_state <= S_UPDATE_HEAD_PTR;
else
next_state <= S_GNT_HCMD;
end
S_UPDATE_HEAD_PTR: begin
next_state <= S_ARB_HCMD;
end
default: begin
next_state <= S_ARB_HCMD;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_sq_entry_valid <= 1;
end
else begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid[0] == 1)
r_sq_entry_valid <= 1;
else
r_sq_entry_valid <= w_sq_valid_mask;
end
S_LOAD_HEAD_PTR: begin
end
S_CALC_ADDR: begin
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_ARB_HCMD: begin
end
S_LOAD_HEAD_PTR: begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: begin
r_hcmd_pcie_addr <= admin_sq_bs_addr;
r_sq_head_ptr <= r_admin_sq_head_ptr;
end
9'b000000010: begin
r_hcmd_pcie_addr <= io_sq1_bs_addr;
r_sq_head_ptr <= r_io_sq1_head_ptr;
end
9'b000000100: begin
r_hcmd_pcie_addr <= io_sq2_bs_addr;
r_sq_head_ptr <= r_io_sq2_head_ptr;
end
9'b000001000: begin
r_hcmd_pcie_addr <= io_sq3_bs_addr;
r_sq_head_ptr <= r_io_sq3_head_ptr;
end
9'b000010000: begin
r_hcmd_pcie_addr <= io_sq4_bs_addr;
r_sq_head_ptr <= r_io_sq4_head_ptr;
end
9'b000100000: begin
r_hcmd_pcie_addr <= io_sq5_bs_addr;
r_sq_head_ptr <= r_io_sq5_head_ptr;
end
9'b001000000: begin
r_hcmd_pcie_addr <= io_sq6_bs_addr;
r_sq_head_ptr <= r_io_sq6_head_ptr;
end
9'b010000000: begin
r_hcmd_pcie_addr <= io_sq7_bs_addr;
r_sq_head_ptr <= r_io_sq7_head_ptr;
end
9'b100000000: begin
r_hcmd_pcie_addr <= io_sq8_bs_addr;
r_sq_head_ptr <= r_io_sq8_head_ptr;
end
endcase
end
S_CALC_ADDR: begin
r_hcmd_pcie_addr <= r_hcmd_pcie_addr + {r_sq_head_ptr, 4'b0};
r_sq_head_ptr <= r_sq_head_ptr + 1;
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_LOAD_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_CALC_ADDR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_GNT_HCMD: begin
r_arb_sq_rdy <= 1;
r_sq_update_entry <= 0;
end
S_UPDATE_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= r_sq_entry_valid;
end
default: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
endcase
end
always @ (*)
begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: r_sq_qid <= 4'h0;
9'b000000010: r_sq_qid <= 4'h1;
9'b000000100: r_sq_qid <= 4'h2;
9'b000001000: r_sq_qid <= 4'h3;
9'b000010000: r_sq_qid <= 4'h4;
9'b000100000: r_sq_qid <= 4'h5;
9'b001000000: r_sq_qid <= 4'h6;
9'b010000000: r_sq_qid <= 4'h7;
9'b100000000: r_sq_qid <= 4'h8;
endcase
end
assign w_sq_rst_n[0] = pcie_user_rst_n & sq_rst_n[0];
assign w_sq_rst_n[1] = pcie_user_rst_n & sq_rst_n[1];
assign w_sq_rst_n[2] = pcie_user_rst_n & sq_rst_n[2];
assign w_sq_rst_n[3] = pcie_user_rst_n & sq_rst_n[3];
assign w_sq_rst_n[4] = pcie_user_rst_n & sq_rst_n[4];
assign w_sq_rst_n[5] = pcie_user_rst_n & sq_rst_n[5];
assign w_sq_rst_n[6] = pcie_user_rst_n & sq_rst_n[6];
assign w_sq_rst_n[7] = pcie_user_rst_n & sq_rst_n[7];
assign w_sq_rst_n[8] = pcie_user_rst_n & sq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[0])
begin
if(w_sq_rst_n[0] == 0) begin
r_admin_sq_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[0] == 1) begin
if(r_admin_sq_head_ptr == admin_sq_size) begin
r_admin_sq_head_ptr <= 0;
end
else begin
r_admin_sq_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[1])
begin
if(w_sq_rst_n[1] == 0) begin
r_io_sq1_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[1] == 1) begin
if(r_io_sq1_head_ptr == io_sq1_size) begin
r_io_sq1_head_ptr <= 0;
end
else begin
r_io_sq1_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[2])
begin
if(w_sq_rst_n[2] == 0) begin
r_io_sq2_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[2] == 1) begin
if(r_io_sq2_head_ptr == io_sq2_size) begin
r_io_sq2_head_ptr <= 0;
end
else begin
r_io_sq2_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[3])
begin
if(w_sq_rst_n[3] == 0) begin
r_io_sq3_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[3] == 1) begin
if(r_io_sq3_head_ptr == io_sq3_size) begin
r_io_sq3_head_ptr <= 0;
end
else begin
r_io_sq3_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[4])
begin
if(w_sq_rst_n[4] == 0) begin
r_io_sq4_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[4] == 1) begin
if(r_io_sq4_head_ptr == io_sq4_size) begin
r_io_sq4_head_ptr <= 0;
end
else begin
r_io_sq4_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[5])
begin
if(w_sq_rst_n[5] == 0) begin
r_io_sq5_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[5] == 1) begin
if(r_io_sq5_head_ptr == io_sq5_size) begin
r_io_sq5_head_ptr <= 0;
end
else begin
r_io_sq5_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[6])
begin
if(w_sq_rst_n[6] == 0) begin
r_io_sq6_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[6] == 1) begin
if(r_io_sq6_head_ptr == io_sq6_size) begin
r_io_sq6_head_ptr <= 0;
end
else begin
r_io_sq6_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[7])
begin
if(w_sq_rst_n[7] == 0) begin
r_io_sq7_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[7] == 1) begin
if(r_io_sq7_head_ptr == io_sq7_size) begin
r_io_sq7_head_ptr <= 0;
end
else begin
r_io_sq7_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[8])
begin
if(w_sq_rst_n[8] == 0) begin
r_io_sq8_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[8] == 1) begin
if(r_io_sq8_head_ptr == io_sq8_size) begin
r_io_sq8_head_ptr <= 0;
end
else begin
r_io_sq8_head_ptr <= r_sq_head_ptr;
end
end
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_arb # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] admin_sq_size,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
output arb_sq_rdy,
output [3:0] sq_qid,
output [C_PCIE_ADDR_WIDTH-1:2] hcmd_pcie_addr,
input sq_hcmd_ack
);
localparam S_ARB_HCMD = 5'b00001;
localparam S_LOAD_HEAD_PTR = 5'b00010;
localparam S_CALC_ADDR = 5'b00100;
localparam S_GNT_HCMD = 5'b01000;
localparam S_UPDATE_HEAD_PTR = 5'b10000;
reg [4:0] cur_state;
reg [4:0] next_state;
reg [7:0] r_admin_sq_head_ptr;
reg [7:0] r_io_sq1_head_ptr;
reg [7:0] r_io_sq2_head_ptr;
reg [7:0] r_io_sq3_head_ptr;
reg [7:0] r_io_sq4_head_ptr;
reg [7:0] r_io_sq5_head_ptr;
reg [7:0] r_io_sq6_head_ptr;
reg [7:0] r_io_sq7_head_ptr;
reg [7:0] r_io_sq8_head_ptr;
reg r_arb_sq_rdy;
reg [3:0] r_sq_qid;
reg [7:0] r_sq_head_ptr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_pcie_addr;
wire [8:0] w_sq_entry_valid;
wire w_sq_entry_valid_ok;
reg [8:0] r_sq_entry_valid;
wire [8:0] w_sq_valid_mask;
reg [8:0] r_sq_update_entry;
wire [8:0] w_sq_rst_n;
assign arb_sq_rdy = r_arb_sq_rdy;
assign sq_qid = r_sq_qid;
assign hcmd_pcie_addr = r_hcmd_pcie_addr;
assign w_sq_entry_valid[0] = (r_admin_sq_head_ptr != admin_sq_tail_ptr) & sq_valid[0];
assign w_sq_entry_valid[1] = (r_io_sq1_head_ptr != io_sq1_tail_ptr) & sq_valid[1];
assign w_sq_entry_valid[2] = (r_io_sq2_head_ptr != io_sq2_tail_ptr) & sq_valid[2];
assign w_sq_entry_valid[3] = (r_io_sq3_head_ptr != io_sq3_tail_ptr) & sq_valid[3];
assign w_sq_entry_valid[4] = (r_io_sq4_head_ptr != io_sq4_tail_ptr) & sq_valid[4];
assign w_sq_entry_valid[5] = (r_io_sq5_head_ptr != io_sq5_tail_ptr) & sq_valid[5];
assign w_sq_entry_valid[6] = (r_io_sq6_head_ptr != io_sq6_tail_ptr) & sq_valid[6];
assign w_sq_entry_valid[7] = (r_io_sq7_head_ptr != io_sq7_tail_ptr) & sq_valid[7];
assign w_sq_entry_valid[8] = (r_io_sq8_head_ptr != io_sq8_tail_ptr) & sq_valid[8];
assign w_sq_valid_mask = {r_sq_entry_valid[7:0], r_sq_entry_valid[8]};
assign w_sq_entry_valid_ok = ((w_sq_entry_valid[8:1] & w_sq_valid_mask[8:1]) != 0) | w_sq_entry_valid[0];
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_ARB_HCMD;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid_ok == 1)
next_state <= S_LOAD_HEAD_PTR;
else
next_state <= S_ARB_HCMD;
end
S_LOAD_HEAD_PTR: begin
next_state <= S_CALC_ADDR;
end
S_CALC_ADDR: begin
next_state <= S_GNT_HCMD;
end
S_GNT_HCMD: begin
if(sq_hcmd_ack == 1)
next_state <= S_UPDATE_HEAD_PTR;
else
next_state <= S_GNT_HCMD;
end
S_UPDATE_HEAD_PTR: begin
next_state <= S_ARB_HCMD;
end
default: begin
next_state <= S_ARB_HCMD;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_sq_entry_valid <= 1;
end
else begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid[0] == 1)
r_sq_entry_valid <= 1;
else
r_sq_entry_valid <= w_sq_valid_mask;
end
S_LOAD_HEAD_PTR: begin
end
S_CALC_ADDR: begin
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_ARB_HCMD: begin
end
S_LOAD_HEAD_PTR: begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: begin
r_hcmd_pcie_addr <= admin_sq_bs_addr;
r_sq_head_ptr <= r_admin_sq_head_ptr;
end
9'b000000010: begin
r_hcmd_pcie_addr <= io_sq1_bs_addr;
r_sq_head_ptr <= r_io_sq1_head_ptr;
end
9'b000000100: begin
r_hcmd_pcie_addr <= io_sq2_bs_addr;
r_sq_head_ptr <= r_io_sq2_head_ptr;
end
9'b000001000: begin
r_hcmd_pcie_addr <= io_sq3_bs_addr;
r_sq_head_ptr <= r_io_sq3_head_ptr;
end
9'b000010000: begin
r_hcmd_pcie_addr <= io_sq4_bs_addr;
r_sq_head_ptr <= r_io_sq4_head_ptr;
end
9'b000100000: begin
r_hcmd_pcie_addr <= io_sq5_bs_addr;
r_sq_head_ptr <= r_io_sq5_head_ptr;
end
9'b001000000: begin
r_hcmd_pcie_addr <= io_sq6_bs_addr;
r_sq_head_ptr <= r_io_sq6_head_ptr;
end
9'b010000000: begin
r_hcmd_pcie_addr <= io_sq7_bs_addr;
r_sq_head_ptr <= r_io_sq7_head_ptr;
end
9'b100000000: begin
r_hcmd_pcie_addr <= io_sq8_bs_addr;
r_sq_head_ptr <= r_io_sq8_head_ptr;
end
endcase
end
S_CALC_ADDR: begin
r_hcmd_pcie_addr <= r_hcmd_pcie_addr + {r_sq_head_ptr, 4'b0};
r_sq_head_ptr <= r_sq_head_ptr + 1;
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_LOAD_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_CALC_ADDR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_GNT_HCMD: begin
r_arb_sq_rdy <= 1;
r_sq_update_entry <= 0;
end
S_UPDATE_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= r_sq_entry_valid;
end
default: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
endcase
end
always @ (*)
begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: r_sq_qid <= 4'h0;
9'b000000010: r_sq_qid <= 4'h1;
9'b000000100: r_sq_qid <= 4'h2;
9'b000001000: r_sq_qid <= 4'h3;
9'b000010000: r_sq_qid <= 4'h4;
9'b000100000: r_sq_qid <= 4'h5;
9'b001000000: r_sq_qid <= 4'h6;
9'b010000000: r_sq_qid <= 4'h7;
9'b100000000: r_sq_qid <= 4'h8;
endcase
end
assign w_sq_rst_n[0] = pcie_user_rst_n & sq_rst_n[0];
assign w_sq_rst_n[1] = pcie_user_rst_n & sq_rst_n[1];
assign w_sq_rst_n[2] = pcie_user_rst_n & sq_rst_n[2];
assign w_sq_rst_n[3] = pcie_user_rst_n & sq_rst_n[3];
assign w_sq_rst_n[4] = pcie_user_rst_n & sq_rst_n[4];
assign w_sq_rst_n[5] = pcie_user_rst_n & sq_rst_n[5];
assign w_sq_rst_n[6] = pcie_user_rst_n & sq_rst_n[6];
assign w_sq_rst_n[7] = pcie_user_rst_n & sq_rst_n[7];
assign w_sq_rst_n[8] = pcie_user_rst_n & sq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[0])
begin
if(w_sq_rst_n[0] == 0) begin
r_admin_sq_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[0] == 1) begin
if(r_admin_sq_head_ptr == admin_sq_size) begin
r_admin_sq_head_ptr <= 0;
end
else begin
r_admin_sq_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[1])
begin
if(w_sq_rst_n[1] == 0) begin
r_io_sq1_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[1] == 1) begin
if(r_io_sq1_head_ptr == io_sq1_size) begin
r_io_sq1_head_ptr <= 0;
end
else begin
r_io_sq1_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[2])
begin
if(w_sq_rst_n[2] == 0) begin
r_io_sq2_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[2] == 1) begin
if(r_io_sq2_head_ptr == io_sq2_size) begin
r_io_sq2_head_ptr <= 0;
end
else begin
r_io_sq2_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[3])
begin
if(w_sq_rst_n[3] == 0) begin
r_io_sq3_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[3] == 1) begin
if(r_io_sq3_head_ptr == io_sq3_size) begin
r_io_sq3_head_ptr <= 0;
end
else begin
r_io_sq3_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[4])
begin
if(w_sq_rst_n[4] == 0) begin
r_io_sq4_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[4] == 1) begin
if(r_io_sq4_head_ptr == io_sq4_size) begin
r_io_sq4_head_ptr <= 0;
end
else begin
r_io_sq4_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[5])
begin
if(w_sq_rst_n[5] == 0) begin
r_io_sq5_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[5] == 1) begin
if(r_io_sq5_head_ptr == io_sq5_size) begin
r_io_sq5_head_ptr <= 0;
end
else begin
r_io_sq5_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[6])
begin
if(w_sq_rst_n[6] == 0) begin
r_io_sq6_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[6] == 1) begin
if(r_io_sq6_head_ptr == io_sq6_size) begin
r_io_sq6_head_ptr <= 0;
end
else begin
r_io_sq6_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[7])
begin
if(w_sq_rst_n[7] == 0) begin
r_io_sq7_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[7] == 1) begin
if(r_io_sq7_head_ptr == io_sq7_size) begin
r_io_sq7_head_ptr <= 0;
end
else begin
r_io_sq7_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[8])
begin
if(w_sq_rst_n[8] == 0) begin
r_io_sq8_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[8] == 1) begin
if(r_io_sq8_head_ptr == io_sq8_size) begin
r_io_sq8_head_ptr <= 0;
end
else begin
r_io_sq8_head_ptr <= r_sq_head_ptr;
end
end
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_cmd_gen # (
parameter P_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_rcb,
output dma_cmd_rd_en,
input [49:0] dma_cmd_rd_data,
input dma_cmd_empty_n,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output pcie_cmd_wr_en,
output [33:0] pcie_cmd_wr_data,
input pcie_cmd_full_n,
output prp_pcie_alloc,
output [7:0] prp_pcie_alloc_tag,
output [5:4] prp_pcie_tag_alloc_len,
input pcie_tag_full_n,
input prp_fifo_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack
);
localparam LP_PRP_PCIE_TAG_PREFIX = 5'b00001;
localparam S_IDLE = 17'b00000000000000001;
localparam S_DMA_CMD0 = 17'b00000000000000010;
localparam S_DMA_CMD1 = 17'b00000000000000100;
localparam S_PRP_INFO0 = 17'b00000000000001000;
localparam S_PRP_INFO1 = 17'b00000000000010000;
localparam S_CALC_LEN0 = 17'b00000000000100000;
localparam S_CALC_LEN1 = 17'b00000000001000000;
localparam S_CALC_LEN2 = 17'b00000000010000000;
localparam S_CHECK_FIFO = 17'b00000000100000000;
localparam S_CMD0 = 17'b00000001000000000;
localparam S_CMD1 = 17'b00000010000000000;
localparam S_CMD2 = 17'b00000100000000000;
localparam S_CMD3 = 17'b00001000000000000;
localparam S_PCIE_MRD_CHECK = 17'b00010000000000000;
localparam S_PCIE_MRD_REQ = 17'b00100000000000000;
localparam S_PCIE_MRD_ACK = 17'b01000000000000000;
localparam S_PCIE_MRD_REQ_DONE = 17'b10000000000000000;
reg [16:0] cur_state;
reg [16:0] next_state;
reg r_pcie_rcb;
reg r_pcie_rcb_cross;
reg r_dma_cmd_type;
reg r_dma_cmd_dir;
reg [6:0] r_hcmd_slot_tag;
reg [31:2] r_dev_addr;
reg [12:2] r_dev_dma_len;
reg [8:0] r_4k_offset;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_1;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_2;
reg [8:0] r_hcmd_nlb;
reg r_prp2_type;
reg [8:0] r_prp_offset;
reg r_prp_offset_is_0;
reg [11:2] r_prp_4b_offset;
reg [12:2] r_1st_prp_4b_len;
reg [12:2] r_1st_4b_len;
reg [12:2] r_2st_4b_len;
reg r_2st_valid;
reg r_1st_mrd_need;
reg r_2st_mrd_need;
wire w_2st_mrd_need;
reg [2:0] r_tx_prp_mrd_tag;
reg [4:3] r_pcie_mrd_len;
reg [C_PCIE_ADDR_WIDTH-1:2] r_tx_prp_mrd_addr;
wire [20:2] w_4b_offset;
wire w_dev_cmd_full_n;
reg r_dma_cmd_rd_en;
reg r_hcmd_prp_rd_sel;
reg r_dev_rx_cmd_wr_en;
reg r_dev_tx_cmd_wr_en;
reg r_dev_cmd_wr_data_sel;
reg r_pcie_cmd_wr_en;
reg [3:0] r_pcie_cmd_wr_data_sel;
reg r_prp_pcie_alloc;
reg r_tx_prp_mrd_req;
reg r_mrd_tag_update;
reg [29:0] r_dev_cmd_wr_data;
reg [33:0] r_pcie_cmd_wr_data;
assign dma_cmd_rd_en = r_dma_cmd_rd_en;
assign hcmd_prp_rd_addr = {r_hcmd_slot_tag, r_hcmd_prp_rd_sel};
assign dev_rx_cmd_wr_en = r_dev_rx_cmd_wr_en;
assign dev_rx_cmd_wr_data = r_dev_cmd_wr_data;
assign dev_tx_cmd_wr_en = r_dev_tx_cmd_wr_en;
assign dev_tx_cmd_wr_data = r_dev_cmd_wr_data;
assign pcie_cmd_wr_en = r_pcie_cmd_wr_en;
assign pcie_cmd_wr_data = r_pcie_cmd_wr_data;
assign prp_pcie_alloc = r_prp_pcie_alloc;
assign prp_pcie_alloc_tag = {LP_PRP_PCIE_TAG_PREFIX, r_tx_prp_mrd_tag};
assign prp_pcie_tag_alloc_len = (r_pcie_rcb_cross == 0) ? 2'b01 : 2'b10;
assign tx_prp_mrd_req = r_tx_prp_mrd_req;
assign tx_prp_mrd_tag = {LP_PRP_PCIE_TAG_PREFIX, r_tx_prp_mrd_tag};
assign tx_prp_mrd_len = {7'b0, r_pcie_mrd_len, 1'b0};
assign tx_prp_mrd_addr = r_tx_prp_mrd_addr;
always @ (posedge pcie_user_clk)
begin
r_pcie_rcb <= pcie_rcb;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
assign w_dev_cmd_full_n = (r_dma_cmd_dir == 1'b1) ? dev_tx_cmd_full_n : dev_rx_cmd_full_n;
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(dma_cmd_empty_n == 1'b1)
next_state <= S_DMA_CMD0;
else
next_state <= S_IDLE;
end
S_DMA_CMD0: begin
next_state <= S_DMA_CMD1;
end
S_DMA_CMD1: begin
if(r_dma_cmd_type == 1'b1)
next_state <= S_CHECK_FIFO;
else
next_state <= S_PRP_INFO0;
end
S_PRP_INFO0: begin
next_state <= S_PRP_INFO1;
end
S_PRP_INFO1: begin
next_state <= S_CALC_LEN0;
end
S_CALC_LEN0: begin
next_state <= S_CALC_LEN1;
end
S_CALC_LEN1: begin
next_state <= S_CALC_LEN2;
end
S_CALC_LEN2: begin
next_state <= S_CHECK_FIFO;
end
S_CHECK_FIFO: begin
if(w_dev_cmd_full_n == 1'b1 && pcie_cmd_full_n == 1'b1)
next_state <= S_CMD0;
else
next_state <= S_CHECK_FIFO;
end
S_CMD0: begin
next_state <= S_CMD1;
end
S_CMD1: begin
next_state <= S_CMD2;
end
S_CMD2: begin
next_state <= S_CMD3;
end
S_CMD3: begin
if((r_1st_mrd_need | (r_2st_valid & r_2st_mrd_need)) == 1'b1)
next_state <= S_PCIE_MRD_CHECK;
else
next_state <= S_IDLE;
end
S_PCIE_MRD_CHECK: begin
if(pcie_tag_full_n == 1 && prp_fifo_full_n == 1)
next_state <= S_PCIE_MRD_REQ;
else
next_state <= S_PCIE_MRD_CHECK;
end
S_PCIE_MRD_REQ: begin
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_ACK: begin
if(tx_prp_mrd_req_ack == 1'b1)
next_state <= S_PCIE_MRD_REQ_DONE;
else
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_REQ_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_tx_prp_mrd_tag <= 0;
end
else begin
if(r_mrd_tag_update == 1)
r_tx_prp_mrd_tag <= r_tx_prp_mrd_tag + 1;
end
end
assign w_4b_offset[20:2] = {r_4k_offset, 10'b0} + r_hcmd_prp_1[11:2];
assign w_2st_mrd_need = r_2st_valid & r_2st_mrd_need;
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
r_2st_valid <= 0;
r_1st_mrd_need <= 0;
r_2st_mrd_need <= 0;
r_pcie_rcb_cross <= 0;
end
S_DMA_CMD0: begin
r_dev_addr <= dma_cmd_rd_data[29:0];
r_dev_dma_len <= dma_cmd_rd_data[40:30];
r_hcmd_slot_tag <= dma_cmd_rd_data[47:41];
r_dma_cmd_dir <= dma_cmd_rd_data[48];
r_dma_cmd_type <= dma_cmd_rd_data[49];
end
S_DMA_CMD1: begin
r_hcmd_prp_1 <= dma_cmd_rd_data[33:0];
r_4k_offset <= dma_cmd_rd_data[42:34];
r_1st_4b_len <= r_dev_dma_len;
end
S_PRP_INFO0: begin
r_hcmd_prp_1 <= hcmd_prp_rd_data[33:0];
end
S_PRP_INFO1: begin
r_hcmd_nlb <= {1'b0, hcmd_prp_rd_data[41:34]};
r_hcmd_prp_2 <= hcmd_prp_rd_data[33:0];
end
S_CALC_LEN0: begin
r_prp_offset <= w_4b_offset[20:12];
r_prp_4b_offset <= w_4b_offset[11:2];
r_hcmd_nlb <= r_hcmd_nlb + 1;
end
S_CALC_LEN1: begin
r_dev_addr[11:2] <= 0;
r_dev_dma_len <= 11'h400;
r_prp_offset_is_0 <= (r_prp_offset == 0);
r_1st_prp_4b_len <= 11'h400 - r_prp_4b_offset;
if((12'h800 - r_hcmd_prp_1[11:2]) >= {r_hcmd_nlb, 10'b0})
r_prp2_type <= 0;
else
r_prp2_type <= 1;
end
S_CALC_LEN2: begin
if(r_dev_dma_len > r_1st_prp_4b_len) begin
r_1st_4b_len <= r_1st_prp_4b_len;
r_2st_4b_len <= r_dev_dma_len - r_1st_prp_4b_len;
r_2st_valid <= 1;
end
else begin
r_1st_4b_len <= r_dev_dma_len;
r_2st_valid <= 0;
end
if(r_prp_offset_is_0 == 1) begin
r_1st_mrd_need <= 0;
r_2st_mrd_need <= r_prp2_type;
end
else begin
r_hcmd_prp_1[C_PCIE_ADDR_WIDTH-1:12] <= r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12];
r_1st_mrd_need <= r_prp2_type;
r_2st_mrd_need <= r_prp2_type;
r_prp_offset <= r_prp_offset - 1'b1;
end
r_hcmd_prp_1[11:2] <= r_prp_4b_offset;
end
S_CHECK_FIFO: begin
r_tx_prp_mrd_addr <= r_hcmd_prp_2 + {r_prp_offset, 1'b0};
r_pcie_mrd_len <= r_1st_mrd_need + w_2st_mrd_need;
end
S_CMD0: begin
if(r_pcie_mrd_len == 2 && r_tx_prp_mrd_addr[5:2] == 4'b1110) begin
if(r_pcie_rcb == 1)
r_pcie_rcb_cross <= r_tx_prp_mrd_addr[6];
else
r_pcie_rcb_cross <= 1;
end
else
r_pcie_rcb_cross <= 0;
end
S_CMD1: begin
end
S_CMD2: begin
end
S_CMD3: begin
end
S_PCIE_MRD_CHECK: begin
end
S_PCIE_MRD_REQ: begin
end
S_PCIE_MRD_ACK: begin
end
S_PCIE_MRD_REQ_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
if(r_dev_cmd_wr_data_sel == 0)
r_dev_cmd_wr_data <= {10'b0, r_dma_cmd_type, 1'b0, r_hcmd_slot_tag, r_dev_dma_len};
else
r_dev_cmd_wr_data <= r_dev_addr;
case(r_pcie_cmd_wr_data_sel) // synthesis parallel_case full_case
4'b0001: r_pcie_cmd_wr_data <= {22'b0, r_dma_cmd_type, r_dma_cmd_dir, r_2st_valid, r_1st_mrd_need, r_2st_mrd_need, r_hcmd_slot_tag};
4'b0010: r_pcie_cmd_wr_data <= {11'b0, r_pcie_rcb_cross, r_1st_4b_len, r_2st_4b_len};
4'b0100: r_pcie_cmd_wr_data <= r_hcmd_prp_1;
4'b1000: r_pcie_cmd_wr_data <= {r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12], 10'b0};
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_DMA_CMD0: begin
r_dma_cmd_rd_en <= 1;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_DMA_CMD1: begin
r_dma_cmd_rd_en <= 1;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PRP_INFO0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 1;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PRP_INFO1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN2: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CHECK_FIFO: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_dev_tx_cmd_wr_en <= r_dma_cmd_dir;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0001;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_dev_tx_cmd_wr_en <= r_dma_cmd_dir;
r_dev_cmd_wr_data_sel <= 1;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0010;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD2: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0100;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD3: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b1000;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_CHECK: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_REQ: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 1;
r_tx_prp_mrd_req <= 1;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_ACK: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_REQ_DONE: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 1;
end
default: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
endcase
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_cmd_gen # (
parameter P_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_rcb,
output dma_cmd_rd_en,
input [49:0] dma_cmd_rd_data,
input dma_cmd_empty_n,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output pcie_cmd_wr_en,
output [33:0] pcie_cmd_wr_data,
input pcie_cmd_full_n,
output prp_pcie_alloc,
output [7:0] prp_pcie_alloc_tag,
output [5:4] prp_pcie_tag_alloc_len,
input pcie_tag_full_n,
input prp_fifo_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack
);
localparam LP_PRP_PCIE_TAG_PREFIX = 5'b00001;
localparam S_IDLE = 17'b00000000000000001;
localparam S_DMA_CMD0 = 17'b00000000000000010;
localparam S_DMA_CMD1 = 17'b00000000000000100;
localparam S_PRP_INFO0 = 17'b00000000000001000;
localparam S_PRP_INFO1 = 17'b00000000000010000;
localparam S_CALC_LEN0 = 17'b00000000000100000;
localparam S_CALC_LEN1 = 17'b00000000001000000;
localparam S_CALC_LEN2 = 17'b00000000010000000;
localparam S_CHECK_FIFO = 17'b00000000100000000;
localparam S_CMD0 = 17'b00000001000000000;
localparam S_CMD1 = 17'b00000010000000000;
localparam S_CMD2 = 17'b00000100000000000;
localparam S_CMD3 = 17'b00001000000000000;
localparam S_PCIE_MRD_CHECK = 17'b00010000000000000;
localparam S_PCIE_MRD_REQ = 17'b00100000000000000;
localparam S_PCIE_MRD_ACK = 17'b01000000000000000;
localparam S_PCIE_MRD_REQ_DONE = 17'b10000000000000000;
reg [16:0] cur_state;
reg [16:0] next_state;
reg r_pcie_rcb;
reg r_pcie_rcb_cross;
reg r_dma_cmd_type;
reg r_dma_cmd_dir;
reg [6:0] r_hcmd_slot_tag;
reg [31:2] r_dev_addr;
reg [12:2] r_dev_dma_len;
reg [8:0] r_4k_offset;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_1;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_2;
reg [8:0] r_hcmd_nlb;
reg r_prp2_type;
reg [8:0] r_prp_offset;
reg r_prp_offset_is_0;
reg [11:2] r_prp_4b_offset;
reg [12:2] r_1st_prp_4b_len;
reg [12:2] r_1st_4b_len;
reg [12:2] r_2st_4b_len;
reg r_2st_valid;
reg r_1st_mrd_need;
reg r_2st_mrd_need;
wire w_2st_mrd_need;
reg [2:0] r_tx_prp_mrd_tag;
reg [4:3] r_pcie_mrd_len;
reg [C_PCIE_ADDR_WIDTH-1:2] r_tx_prp_mrd_addr;
wire [20:2] w_4b_offset;
wire w_dev_cmd_full_n;
reg r_dma_cmd_rd_en;
reg r_hcmd_prp_rd_sel;
reg r_dev_rx_cmd_wr_en;
reg r_dev_tx_cmd_wr_en;
reg r_dev_cmd_wr_data_sel;
reg r_pcie_cmd_wr_en;
reg [3:0] r_pcie_cmd_wr_data_sel;
reg r_prp_pcie_alloc;
reg r_tx_prp_mrd_req;
reg r_mrd_tag_update;
reg [29:0] r_dev_cmd_wr_data;
reg [33:0] r_pcie_cmd_wr_data;
assign dma_cmd_rd_en = r_dma_cmd_rd_en;
assign hcmd_prp_rd_addr = {r_hcmd_slot_tag, r_hcmd_prp_rd_sel};
assign dev_rx_cmd_wr_en = r_dev_rx_cmd_wr_en;
assign dev_rx_cmd_wr_data = r_dev_cmd_wr_data;
assign dev_tx_cmd_wr_en = r_dev_tx_cmd_wr_en;
assign dev_tx_cmd_wr_data = r_dev_cmd_wr_data;
assign pcie_cmd_wr_en = r_pcie_cmd_wr_en;
assign pcie_cmd_wr_data = r_pcie_cmd_wr_data;
assign prp_pcie_alloc = r_prp_pcie_alloc;
assign prp_pcie_alloc_tag = {LP_PRP_PCIE_TAG_PREFIX, r_tx_prp_mrd_tag};
assign prp_pcie_tag_alloc_len = (r_pcie_rcb_cross == 0) ? 2'b01 : 2'b10;
assign tx_prp_mrd_req = r_tx_prp_mrd_req;
assign tx_prp_mrd_tag = {LP_PRP_PCIE_TAG_PREFIX, r_tx_prp_mrd_tag};
assign tx_prp_mrd_len = {7'b0, r_pcie_mrd_len, 1'b0};
assign tx_prp_mrd_addr = r_tx_prp_mrd_addr;
always @ (posedge pcie_user_clk)
begin
r_pcie_rcb <= pcie_rcb;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
assign w_dev_cmd_full_n = (r_dma_cmd_dir == 1'b1) ? dev_tx_cmd_full_n : dev_rx_cmd_full_n;
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(dma_cmd_empty_n == 1'b1)
next_state <= S_DMA_CMD0;
else
next_state <= S_IDLE;
end
S_DMA_CMD0: begin
next_state <= S_DMA_CMD1;
end
S_DMA_CMD1: begin
if(r_dma_cmd_type == 1'b1)
next_state <= S_CHECK_FIFO;
else
next_state <= S_PRP_INFO0;
end
S_PRP_INFO0: begin
next_state <= S_PRP_INFO1;
end
S_PRP_INFO1: begin
next_state <= S_CALC_LEN0;
end
S_CALC_LEN0: begin
next_state <= S_CALC_LEN1;
end
S_CALC_LEN1: begin
next_state <= S_CALC_LEN2;
end
S_CALC_LEN2: begin
next_state <= S_CHECK_FIFO;
end
S_CHECK_FIFO: begin
if(w_dev_cmd_full_n == 1'b1 && pcie_cmd_full_n == 1'b1)
next_state <= S_CMD0;
else
next_state <= S_CHECK_FIFO;
end
S_CMD0: begin
next_state <= S_CMD1;
end
S_CMD1: begin
next_state <= S_CMD2;
end
S_CMD2: begin
next_state <= S_CMD3;
end
S_CMD3: begin
if((r_1st_mrd_need | (r_2st_valid & r_2st_mrd_need)) == 1'b1)
next_state <= S_PCIE_MRD_CHECK;
else
next_state <= S_IDLE;
end
S_PCIE_MRD_CHECK: begin
if(pcie_tag_full_n == 1 && prp_fifo_full_n == 1)
next_state <= S_PCIE_MRD_REQ;
else
next_state <= S_PCIE_MRD_CHECK;
end
S_PCIE_MRD_REQ: begin
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_ACK: begin
if(tx_prp_mrd_req_ack == 1'b1)
next_state <= S_PCIE_MRD_REQ_DONE;
else
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_REQ_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_tx_prp_mrd_tag <= 0;
end
else begin
if(r_mrd_tag_update == 1)
r_tx_prp_mrd_tag <= r_tx_prp_mrd_tag + 1;
end
end
assign w_4b_offset[20:2] = {r_4k_offset, 10'b0} + r_hcmd_prp_1[11:2];
assign w_2st_mrd_need = r_2st_valid & r_2st_mrd_need;
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
r_2st_valid <= 0;
r_1st_mrd_need <= 0;
r_2st_mrd_need <= 0;
r_pcie_rcb_cross <= 0;
end
S_DMA_CMD0: begin
r_dev_addr <= dma_cmd_rd_data[29:0];
r_dev_dma_len <= dma_cmd_rd_data[40:30];
r_hcmd_slot_tag <= dma_cmd_rd_data[47:41];
r_dma_cmd_dir <= dma_cmd_rd_data[48];
r_dma_cmd_type <= dma_cmd_rd_data[49];
end
S_DMA_CMD1: begin
r_hcmd_prp_1 <= dma_cmd_rd_data[33:0];
r_4k_offset <= dma_cmd_rd_data[42:34];
r_1st_4b_len <= r_dev_dma_len;
end
S_PRP_INFO0: begin
r_hcmd_prp_1 <= hcmd_prp_rd_data[33:0];
end
S_PRP_INFO1: begin
r_hcmd_nlb <= {1'b0, hcmd_prp_rd_data[41:34]};
r_hcmd_prp_2 <= hcmd_prp_rd_data[33:0];
end
S_CALC_LEN0: begin
r_prp_offset <= w_4b_offset[20:12];
r_prp_4b_offset <= w_4b_offset[11:2];
r_hcmd_nlb <= r_hcmd_nlb + 1;
end
S_CALC_LEN1: begin
r_dev_addr[11:2] <= 0;
r_dev_dma_len <= 11'h400;
r_prp_offset_is_0 <= (r_prp_offset == 0);
r_1st_prp_4b_len <= 11'h400 - r_prp_4b_offset;
if((12'h800 - r_hcmd_prp_1[11:2]) >= {r_hcmd_nlb, 10'b0})
r_prp2_type <= 0;
else
r_prp2_type <= 1;
end
S_CALC_LEN2: begin
if(r_dev_dma_len > r_1st_prp_4b_len) begin
r_1st_4b_len <= r_1st_prp_4b_len;
r_2st_4b_len <= r_dev_dma_len - r_1st_prp_4b_len;
r_2st_valid <= 1;
end
else begin
r_1st_4b_len <= r_dev_dma_len;
r_2st_valid <= 0;
end
if(r_prp_offset_is_0 == 1) begin
r_1st_mrd_need <= 0;
r_2st_mrd_need <= r_prp2_type;
end
else begin
r_hcmd_prp_1[C_PCIE_ADDR_WIDTH-1:12] <= r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12];
r_1st_mrd_need <= r_prp2_type;
r_2st_mrd_need <= r_prp2_type;
r_prp_offset <= r_prp_offset - 1'b1;
end
r_hcmd_prp_1[11:2] <= r_prp_4b_offset;
end
S_CHECK_FIFO: begin
r_tx_prp_mrd_addr <= r_hcmd_prp_2 + {r_prp_offset, 1'b0};
r_pcie_mrd_len <= r_1st_mrd_need + w_2st_mrd_need;
end
S_CMD0: begin
if(r_pcie_mrd_len == 2 && r_tx_prp_mrd_addr[5:2] == 4'b1110) begin
if(r_pcie_rcb == 1)
r_pcie_rcb_cross <= r_tx_prp_mrd_addr[6];
else
r_pcie_rcb_cross <= 1;
end
else
r_pcie_rcb_cross <= 0;
end
S_CMD1: begin
end
S_CMD2: begin
end
S_CMD3: begin
end
S_PCIE_MRD_CHECK: begin
end
S_PCIE_MRD_REQ: begin
end
S_PCIE_MRD_ACK: begin
end
S_PCIE_MRD_REQ_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
if(r_dev_cmd_wr_data_sel == 0)
r_dev_cmd_wr_data <= {10'b0, r_dma_cmd_type, 1'b0, r_hcmd_slot_tag, r_dev_dma_len};
else
r_dev_cmd_wr_data <= r_dev_addr;
case(r_pcie_cmd_wr_data_sel) // synthesis parallel_case full_case
4'b0001: r_pcie_cmd_wr_data <= {22'b0, r_dma_cmd_type, r_dma_cmd_dir, r_2st_valid, r_1st_mrd_need, r_2st_mrd_need, r_hcmd_slot_tag};
4'b0010: r_pcie_cmd_wr_data <= {11'b0, r_pcie_rcb_cross, r_1st_4b_len, r_2st_4b_len};
4'b0100: r_pcie_cmd_wr_data <= r_hcmd_prp_1;
4'b1000: r_pcie_cmd_wr_data <= {r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12], 10'b0};
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_DMA_CMD0: begin
r_dma_cmd_rd_en <= 1;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_DMA_CMD1: begin
r_dma_cmd_rd_en <= 1;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PRP_INFO0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 1;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PRP_INFO1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN2: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CHECK_FIFO: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_dev_tx_cmd_wr_en <= r_dma_cmd_dir;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0001;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_dev_tx_cmd_wr_en <= r_dma_cmd_dir;
r_dev_cmd_wr_data_sel <= 1;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0010;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD2: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0100;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD3: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b1000;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_CHECK: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_REQ: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 1;
r_tx_prp_mrd_req <= 1;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_ACK: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_REQ_DONE: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 1;
end
default: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
endcase
end
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks.
//
// This implements a 4096:1 mux via two stages of 64:1 muxing.
// change these two parameters to see the speed differences
//`define DATA_WIDTH 12
//`define MUX2_SIZE 32
`define DATA_WIDTH 2
`define MUX2_SIZE 8
// if you change these, then the testbench will break
`define ADDR_WIDTH 12
`define MUX1_SIZE 64
// Total of DATA_WIDTH*MUX2_SIZE*(MUX1_SIZE+1) instantiations of mux64
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v
// End of automatics
reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai;
reg [`ADDR_WIDTH-1:0] addr;
// Mux: takes in addr and datai and outputs datao
mux4096 mux4096 (/*AUTOINST*/
// Outputs
.datao (datao[`DATA_WIDTH-1:0]),
// Inputs
.datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]),
.addr (addr[`ADDR_WIDTH-1:0]));
// calculate what the answer should be from datai. This is bit
// tricky given the way datai gets sliced. datai is in bit
// planes where all the LSBs are contiguous and then the next bit.
reg [`DATA_WIDTH-1:0] datao_check;
integer j;
always @(datai or addr) begin
for(j=0;j<`DATA_WIDTH;j=j+1) begin
/* verilator lint_off WIDTH */
datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr);
/* verilator lint_on WIDTH */
end
end
// Run the test loop. This just increments the address
integer i, result;
always @ (posedge clk) begin
// initial the input data with random values
if (addr == 0) begin
result = 1;
datai = 0;
for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin
/* verilator lint_off WIDTH */
datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}});
/* verilator lint_on WIDTH */
end
end
addr <= addr + 1;
if (datao_check != datao) begin
result = 0;
$stop;
end
$write("Addr=%d datao_check=%d datao=%d\n", addr, datao_check, datao);
// only run the first 10 addresses for now
if (addr > 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module mux4096
(input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai,
input [`ADDR_WIDTH-1:0] addr,
output [`DATA_WIDTH-1:0] datao
);
// DATA_WIDTH instantiations of mux4096_1bit
mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0]
(.addr(addr),
.datai(datai),
.datao(datao)
);
endmodule
module mux4096_1bit
(input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai,
input [`ADDR_WIDTH-1:0] addr,
output datao
);
// address decoding
wire [3:0] A = (4'b1) << addr[1:0];
wire [3:0] B = (4'b1) << addr[3:2];
wire [3:0] C = (4'b1) << addr[5:4];
wire [3:0] D = (4'b1) << addr[7:6];
wire [3:0] E = (4'b1) << addr[9:8];
wire [3:0] F = (4'b1) << addr[11:10];
wire [`MUX2_SIZE-1:0] data0;
// DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64
// first stage of 64:1 muxing
mux64 #(.MUX_SIZE(`MUX1_SIZE)) mux1[`MUX2_SIZE-1:0]
(.A(A),
.B(B),
.C(C),
.datai(datai),
.datao(data0));
// DATA_WIDTH*MUX2_SIZE instantiations of mux64
// second stage of 64:1 muxing
mux64 #(.MUX_SIZE(`MUX2_SIZE)) mux2
(.A(D),
.B(E),
.C(F),
.datai(data0),
.datao(datao));
endmodule
module mux64
#(parameter MUX_SIZE=64)
(input [3:0] A,
input [3:0] B,
input [3:0] C,
input [MUX_SIZE-1:0] datai,
output datao
);
wire [63:0] colSelA = { 16{ A[3:0] }};
wire [63:0] colSelB = { 4{ {4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}};
wire [63:0] colSelC = { {16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}};
wire [MUX_SIZE-1:0] data_bus;
// Note each of these becomes a separate wire.
//.colSelA(colSelA[MUX_SIZE-1:0]),
//.colSelB(colSelB[MUX_SIZE-1:0]),
//.colSelC(colSelC[MUX_SIZE-1:0]),
drv drv[MUX_SIZE-1:0]
(.colSelA(colSelA[MUX_SIZE-1:0]),
.colSelB(colSelB[MUX_SIZE-1:0]),
.colSelC(colSelC[MUX_SIZE-1:0]),
.datai(datai),
.datao(data_bus)
);
assign datao = |data_bus;
endmodule
module drv
(input colSelA,
input colSelB,
input colSelC,
input datai,
output datao
);
assign datao = colSelC & colSelB & colSelA & datai;
endmodule
|
module packet_builder #(parameter NUM_CHAN = 1)(
// System
input rxclk,
input reset,
input [31:0] adctime,
input [3:0] channels,
// ADC side
input [15:0]chan_fifodata,
input [NUM_CHAN:0]chan_empty,
input [9:0]chan_usedw,
output reg [3:0]rd_select,
output reg chan_rdreq,
// FX2 side
output reg WR,
output reg [15:0]fifodata,
input have_space,
input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
input wire [31:0]rssi_3, output wire [7:0] debugbus,
input [NUM_CHAN:0] underrun);
// States
`define IDLE 3'd0
`define HEADER1 3'd1
`define HEADER2 3'd2
`define TIMESTAMP 3'd3
`define FORWARD 3'd4
`define MAXPAYLOAD 504
`define PAYLOAD_LEN 8:0
`define TAG 12:9
`define MBZ 15:13
`define CHAN 4:0
`define RSSI 10:5
`define BURST 12:11
`define DROPPED 13
`define UNDERRUN 14
`define OVERRUN 15
reg [NUM_CHAN:0] overrun;
reg [2:0] state;
reg [8:0] read_length;
reg [8:0] payload_len;
reg tstamp_complete;
reg [3:0] check_next;
wire [31:0] true_rssi;
wire [4:0] true_channel;
wire ready_to_send;
assign debugbus = {chan_empty[0], rd_select[0], have_space,
(chan_usedw >= 10'd504), (chan_usedw ==0),
ready_to_send, state[1:0]};
assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
((rd_select[0]) ? rssi_1:rssi_0);
assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
//assign true_channel = (check_next == NUM_CHAN ? 5'h1f : {1'd0,check_next});
assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) ||
((rd_select == NUM_CHAN)&&(chan_usedw > 0));
always @(posedge rxclk)
begin
if (reset)
begin
overrun <= 0;
WR <= 0;
rd_select <= 0;
chan_rdreq <= 0;
tstamp_complete <= 0;
check_next <= 0;
state <= `IDLE;
end
else case (state)
`IDLE: begin
chan_rdreq <= #1 0;
//check if the channel is full
if(~chan_empty[check_next])
begin
if (have_space)
begin
//transmit if the usb buffer have space
//check if we should send
if (ready_to_send)
state <= #1 `HEADER1;
overrun[check_next] <= 0;
end
else
begin
state <= #1 `IDLE;
overrun[check_next] <= 1;
end
rd_select <= #1 check_next;
end
check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
end //end of `IDLE
`HEADER1: begin
fifodata[`PAYLOAD_LEN] <= #1 9'd504;
payload_len <= #1 9'd504;
fifodata[`TAG] <= #1 0;
fifodata[`MBZ] <= #1 0;
WR <= #1 1;
state <= #1 `HEADER2;
read_length <= #1 0;
end
`HEADER2: begin
fifodata[`CHAN] <= #1 true_channel;
fifodata[`RSSI] <= #1 true_rssi[5:0];
fifodata[`BURST] <= #1 0;
fifodata[`DROPPED] <= #1 0;
fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel];
fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel];
state <= #1 `TIMESTAMP;
end
`TIMESTAMP: begin
fifodata <= #1 (tstamp_complete ? adctime[31:16] : adctime[15:0]);
tstamp_complete <= #1 ~tstamp_complete;
if (~tstamp_complete)
chan_rdreq <= #1 1;
state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP);
end
`FORWARD: begin
read_length <= #1 read_length + 9'd2;
fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata);
if (read_length >= `MAXPAYLOAD)
begin
WR <= #1 0;
state <= #1 `IDLE;
chan_rdreq <= #1 0;
end
else if (read_length == payload_len - 4)
chan_rdreq <= #1 0;
end
default: begin
//handling error state
state <= `IDLE;
end
endcase
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_irq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] cfg_command,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input nvme_intms_ivms,
input nvme_intmc_ivmc,
output cq_irq_status,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input [7:0] admin_cq_tail_ptr,
input [7:0] io_cq1_tail_ptr,
input [7:0] io_cq2_tail_ptr,
input [7:0] io_cq3_tail_ptr,
input [7:0] io_cq4_tail_ptr,
input [7:0] io_cq5_tail_ptr,
input [7:0] io_cq6_tail_ptr,
input [7:0] io_cq7_tail_ptr,
input [7:0] io_cq8_tail_ptr,
input [7:0] admin_cq_head_ptr,
input [7:0] io_cq1_head_ptr,
input [7:0] io_cq2_head_ptr,
input [7:0] io_cq3_head_ptr,
input [7:0] io_cq4_head_ptr,
input [7:0] io_cq5_head_ptr,
input [7:0] io_cq6_head_ptr,
input [7:0] io_cq7_head_ptr,
input [7:0] io_cq8_head_ptr,
input [8:0] cq_head_update
);
wire w_pcie_legacy_irq_set;
wire w_pcie_msi_irq_set;
wire [2:0] w_pcie_irq_vector;
wire w_pcie_legacy_irq_clear;
wire w_pcie_irq_done;
pcie_irq_gen
pcie_irq_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
nvme_irq_handler
nvme_irq_handler_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.nvme_intms_ivms (nvme_intms_ivms),
.nvme_intmc_ivmc (nvme_intmc_ivmc),
.cq_irq_status (cq_irq_status),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_cq_head_ptr (admin_cq_head_ptr),
.io_cq1_head_ptr (io_cq1_head_ptr),
.io_cq2_head_ptr (io_cq2_head_ptr),
.io_cq3_head_ptr (io_cq3_head_ptr),
.io_cq4_head_ptr (io_cq4_head_ptr),
.io_cq5_head_ptr (io_cq5_head_ptr),
.io_cq6_head_ptr (io_cq6_head_ptr),
.io_cq7_head_ptr (io_cq7_head_ptr),
.io_cq8_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_irq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] cfg_command,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input nvme_intms_ivms,
input nvme_intmc_ivmc,
output cq_irq_status,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input [7:0] admin_cq_tail_ptr,
input [7:0] io_cq1_tail_ptr,
input [7:0] io_cq2_tail_ptr,
input [7:0] io_cq3_tail_ptr,
input [7:0] io_cq4_tail_ptr,
input [7:0] io_cq5_tail_ptr,
input [7:0] io_cq6_tail_ptr,
input [7:0] io_cq7_tail_ptr,
input [7:0] io_cq8_tail_ptr,
input [7:0] admin_cq_head_ptr,
input [7:0] io_cq1_head_ptr,
input [7:0] io_cq2_head_ptr,
input [7:0] io_cq3_head_ptr,
input [7:0] io_cq4_head_ptr,
input [7:0] io_cq5_head_ptr,
input [7:0] io_cq6_head_ptr,
input [7:0] io_cq7_head_ptr,
input [7:0] io_cq8_head_ptr,
input [8:0] cq_head_update
);
wire w_pcie_legacy_irq_set;
wire w_pcie_msi_irq_set;
wire [2:0] w_pcie_irq_vector;
wire w_pcie_legacy_irq_clear;
wire w_pcie_irq_done;
pcie_irq_gen
pcie_irq_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
nvme_irq_handler
nvme_irq_handler_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.nvme_intms_ivms (nvme_intms_ivms),
.nvme_intmc_ivmc (nvme_intmc_ivmc),
.cq_irq_status (cq_irq_status),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_cq_head_ptr (admin_cq_head_ptr),
.io_cq1_head_ptr (io_cq1_head_ptr),
.io_cq2_head_ptr (io_cq2_head_ptr),
.io_cq3_head_ptr (io_cq3_head_ptr),
.io_cq4_head_ptr (io_cq4_head_ptr),
.io_cq5_head_ptr (io_cq5_head_ptr),
.io_cq6_head_ptr (io_cq6_head_ptr),
.io_cq7_head_ptr (io_cq7_head_ptr),
.io_cq8_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module s_axi_top # (
parameter C_S0_AXI_ADDR_WIDTH = 32,
parameter C_S0_AXI_DATA_WIDTH = 32,
parameter C_S0_AXI_BASEADDR = 32'h80000000,
parameter C_S0_AXI_HIGHADDR = 32'h80010000,
parameter C_M0_AXI_ADDR_WIDTH = 32,
parameter C_M0_AXI_DATA_WIDTH = 64,
parameter C_M0_AXI_ID_WIDTH = 1,
parameter C_M0_AXI_AWUSER_WIDTH = 1,
parameter C_M0_AXI_WUSER_WIDTH = 1,
parameter C_M0_AXI_BUSER_WIDTH = 1,
parameter C_M0_AXI_ARUSER_WIDTH = 1,
parameter C_M0_AXI_RUSER_WIDTH = 1,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
input s0_axi_aclk,
input s0_axi_aresetn,
//Write address channel
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr,
output s0_axi_awready,
input s0_axi_awvalid,
input [2:0] s0_axi_awprot,
//Write data channel
input s0_axi_wvalid,
output s0_axi_wready,
input [C_S0_AXI_DATA_WIDTH-1 :0] s0_axi_wdata,
input [(C_S0_AXI_DATA_WIDTH/8)-1:0] s0_axi_wstrb,
//Write response channel
output s0_axi_bvalid,
input s0_axi_bready,
output [1:0] s0_axi_bresp,
//Read address channel
input s0_axi_arvalid,
output s0_axi_arready,
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr,
input [2:0] s0_axi_arprot,
//Read data channel
output s0_axi_rvalid,
input s0_axi_rready,
output [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_rdata,
output [1:0] s0_axi_rresp,
output dev_irq_assert,
output pcie_user_logic_rst,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst,
output nvme_csts_rdy,
output [8:0] sq_valid,
output [7:0] io_sq1_size,
output [7:0] io_sq2_size,
output [7:0] io_sq3_size,
output [7:0] io_sq4_size,
output [7:0] io_sq5_size,
output [7:0] io_sq6_size,
output [7:0] io_sq7_size,
output [7:0] io_sq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
output [3:0] io_sq1_cq_vec,
output [3:0] io_sq2_cq_vec,
output [3:0] io_sq3_cq_vec,
output [3:0] io_sq4_cq_vec,
output [3:0] io_sq5_cq_vec,
output [3:0] io_sq6_cq_vec,
output [3:0] io_sq7_cq_vec,
output [3:0] io_sq8_cq_vec,
output [8:0] cq_valid,
output [7:0] io_cq1_size,
output [7:0] io_cq2_size,
output [7:0] io_cq3_size,
output [7:0] io_cq4_size,
output [7:0] io_cq5_size,
output [7:0] io_cq6_size,
output [7:0] io_cq7_size,
output [7:0] io_cq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
output [8:0] io_cq_irq_en,
output [2:0] io_cq1_iv,
output [2:0] io_cq2_iv,
output [2:0] io_cq3_iv,
output [2:0] io_cq4_iv,
output [2:0] io_cq5_iv,
output [2:0] io_cq6_iv,
output [2:0] io_cq7_iv,
output [2:0] io_cq8_iv,
output hcmd_sq_rd_en,
input [18:0] hcmd_sq_rd_data,
input hcmd_sq_empty_n,
output [10:0] hcmd_table_rd_addr,
input [31:0] hcmd_table_rd_data,
output hcmd_cq_wr1_en,
output [34:0] hcmd_cq_wr1_data0,
output [34:0] hcmd_cq_wr1_data1,
input hcmd_cq_wr1_rdy_n,
output dma_cmd_wr_en,
output [49:0] dma_cmd_wr_data0,
output [49:0] dma_cmd_wr_data1,
input dma_cmd_wr_rdy_n,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
input m0_axi_aclk,
input m0_axi_aresetn,
// Write address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_awid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_awaddr,
output [7:0] m0_axi_awlen,
output [2:0] m0_axi_awsize,
output [1:0] m0_axi_awburst,
output [1:0] m0_axi_awlock,
output [3:0] m0_axi_awcache,
output [2:0] m0_axi_awprot,
output [3:0] m0_axi_awregion,
output [3:0] m0_axi_awqos,
output [C_M0_AXI_AWUSER_WIDTH-1:0] m0_axi_awuser,
output m0_axi_awvalid,
input m0_axi_awready,
// Write data channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_wid,
output [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_wdata,
output [(C_M0_AXI_DATA_WIDTH/8)-1:0] m0_axi_wstrb,
output m0_axi_wlast,
output [C_M0_AXI_WUSER_WIDTH-1:0] m0_axi_wuser,
output m0_axi_wvalid,
input m0_axi_wready,
// Write response channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_bid,
input [1:0] m0_axi_bresp,
input m0_axi_bvalid,
input [C_M0_AXI_BUSER_WIDTH-1:0] m0_axi_buser,
output m0_axi_bready,
// Read address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_arid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_araddr,
output [7:0] m0_axi_arlen,
output [2:0] m0_axi_arsize,
output [1:0] m0_axi_arburst,
output [1:0] m0_axi_arlock,
output [3:0] m0_axi_arcache,
output [2:0] m0_axi_arprot,
output [3:0] m0_axi_arregion,
output [3:0] m0_axi_arqos,
output [C_M0_AXI_ARUSER_WIDTH-1:0] m0_axi_aruser,
output m0_axi_arvalid,
input m0_axi_arready,
// Read data channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_rid,
input [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_rdata,
input [1:0] m0_axi_rresp,
input m0_axi_rlast,
input [C_M0_AXI_RUSER_WIDTH-1:0] m0_axi_ruser,
input m0_axi_rvalid,
output m0_axi_rready,
output pcie_rx_fifo_rd_en,
input [C_M0_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
output pcie_rx_fifo_free_en,
output [9:4] pcie_rx_fifo_free_len,
input pcie_rx_fifo_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M0_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n,
output dma_rx_done_wr_en,
output [20:0] dma_rx_done_wr_data,
input dma_rx_done_wr_rdy_n,
input pcie_user_clk,
input pcie_user_rst_n,
input dev_rx_cmd_wr_en,
input [29:0] dev_rx_cmd_wr_data,
output dev_rx_cmd_full_n,
input dev_tx_cmd_wr_en,
input [29:0] dev_tx_cmd_wr_data,
output dev_tx_cmd_full_n,
input [7:0] dma_rx_direct_done_cnt,
input [7:0] dma_tx_direct_done_cnt,
input [7:0] dma_rx_done_cnt,
input [7:0] dma_tx_done_cnt,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable
);
wire w_m0_axi_bresp_err;
wire w_m0_axi_rresp_err;
s_axi_reg # (
.C_S_AXI_ADDR_WIDTH (C_S0_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S0_AXI_DATA_WIDTH),
.C_S_AXI_BASEADDR (C_S0_AXI_BASEADDR),
.C_S_AXI_HIGHADDR (C_S0_AXI_HIGHADDR)
)
s_axi_reg_inst0 (
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
.s_axi_aclk (s0_axi_aclk),
.s_axi_aresetn (s0_axi_aresetn),
//Write address channel
.s_axi_awaddr (s0_axi_awaddr),
.s_axi_awready (s0_axi_awready),
.s_axi_awvalid (s0_axi_awvalid),
.s_axi_awprot (s0_axi_awprot),
//Write data channel
.s_axi_wvalid (s0_axi_wvalid),
.s_axi_wready (s0_axi_wready),
.s_axi_wdata (s0_axi_wdata),
.s_axi_wstrb (s0_axi_wstrb),
//Write response channel
.s_axi_bvalid (s0_axi_bvalid),
.s_axi_bready (s0_axi_bready),
.s_axi_bresp (s0_axi_bresp),
//Read address channel
.s_axi_arvalid (s0_axi_arvalid),
.s_axi_arready (s0_axi_arready),
.s_axi_araddr (s0_axi_araddr),
.s_axi_arprot (s0_axi_arprot),
//Read data channel
.s_axi_rvalid (s0_axi_rvalid),
.s_axi_rready (s0_axi_rready),
.s_axi_rdata (s0_axi_rdata),
.s_axi_rresp (s0_axi_rresp),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.m0_axi_bresp_err (w_m0_axi_bresp_err),
.m0_axi_rresp_err (w_m0_axi_rresp_err),
.dev_irq_assert (dev_irq_assert),
.pcie_user_logic_rst (pcie_user_logic_rst),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n),
.hcmd_table_rd_addr (hcmd_table_rd_addr),
.hcmd_table_rd_data (hcmd_table_rd_data),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.pcie_link_up (pcie_link_up),
.pl_ltssm_state (pl_ltssm_state),
.cfg_command (cfg_command),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable)
);
m_axi_dma # (
.C_M_AXI_ADDR_WIDTH (C_M0_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M0_AXI_DATA_WIDTH),
.C_M_AXI_ID_WIDTH (C_M0_AXI_ID_WIDTH),
.C_M_AXI_AWUSER_WIDTH (C_M0_AXI_AWUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH (C_M0_AXI_WUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH (C_M0_AXI_BUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH (C_M0_AXI_ARUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH (C_M0_AXI_RUSER_WIDTH)
)
m_axi_dma_inst0(
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
.m_axi_aclk (m0_axi_aclk),
.m_axi_aresetn (m0_axi_aresetn),
// Write address channel
.m_axi_awid (m0_axi_awid),
.m_axi_awaddr (m0_axi_awaddr),
.m_axi_awlen (m0_axi_awlen),
.m_axi_awsize (m0_axi_awsize),
.m_axi_awburst (m0_axi_awburst),
.m_axi_awlock (m0_axi_awlock),
.m_axi_awcache (m0_axi_awcache),
.m_axi_awprot (m0_axi_awprot),
.m_axi_awregion (m0_axi_awregion),
.m_axi_awqos (m0_axi_awqos),
.m_axi_awuser (m0_axi_awuser),
.m_axi_awvalid (m0_axi_awvalid),
.m_axi_awready (m0_axi_awready),
// Write data channel
.m_axi_wid (m0_axi_wid),
.m_axi_wdata (m0_axi_wdata),
.m_axi_wstrb (m0_axi_wstrb),
.m_axi_wlast (m0_axi_wlast),
.m_axi_wuser (m0_axi_wuser),
.m_axi_wvalid (m0_axi_wvalid),
.m_axi_wready (m0_axi_wready),
// Write response channel
.m_axi_bid (m0_axi_bid),
.m_axi_bresp (m0_axi_bresp),
.m_axi_bvalid (m0_axi_bvalid),
.m_axi_buser (m0_axi_buser),
.m_axi_bready (m0_axi_bready),
// Read address channel
.m_axi_arid (m0_axi_arid),
.m_axi_araddr (m0_axi_araddr),
.m_axi_arlen (m0_axi_arlen),
.m_axi_arsize (m0_axi_arsize),
.m_axi_arburst (m0_axi_arburst),
.m_axi_arlock (m0_axi_arlock),
.m_axi_arcache (m0_axi_arcache),
.m_axi_arprot (m0_axi_arprot),
.m_axi_arregion (m0_axi_arregion),
.m_axi_arqos (m0_axi_arqos),
.m_axi_aruser (m0_axi_aruser),
.m_axi_arvalid (m0_axi_arvalid),
.m_axi_arready (m0_axi_arready),
// Read data channel
.m_axi_rid (m0_axi_rid),
.m_axi_rdata (m0_axi_rdata),
.m_axi_rresp (m0_axi_rresp),
.m_axi_rlast (m0_axi_rlast),
.m_axi_ruser (m0_axi_ruser),
.m_axi_rvalid (m0_axi_rvalid),
.m_axi_rready (m0_axi_rready),
.m_axi_bresp_err (w_m0_axi_bresp_err),
.m_axi_rresp_err (w_m0_axi_rresp_err),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n),
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module s_axi_top # (
parameter C_S0_AXI_ADDR_WIDTH = 32,
parameter C_S0_AXI_DATA_WIDTH = 32,
parameter C_S0_AXI_BASEADDR = 32'h80000000,
parameter C_S0_AXI_HIGHADDR = 32'h80010000,
parameter C_M0_AXI_ADDR_WIDTH = 32,
parameter C_M0_AXI_DATA_WIDTH = 64,
parameter C_M0_AXI_ID_WIDTH = 1,
parameter C_M0_AXI_AWUSER_WIDTH = 1,
parameter C_M0_AXI_WUSER_WIDTH = 1,
parameter C_M0_AXI_BUSER_WIDTH = 1,
parameter C_M0_AXI_ARUSER_WIDTH = 1,
parameter C_M0_AXI_RUSER_WIDTH = 1,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
input s0_axi_aclk,
input s0_axi_aresetn,
//Write address channel
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr,
output s0_axi_awready,
input s0_axi_awvalid,
input [2:0] s0_axi_awprot,
//Write data channel
input s0_axi_wvalid,
output s0_axi_wready,
input [C_S0_AXI_DATA_WIDTH-1 :0] s0_axi_wdata,
input [(C_S0_AXI_DATA_WIDTH/8)-1:0] s0_axi_wstrb,
//Write response channel
output s0_axi_bvalid,
input s0_axi_bready,
output [1:0] s0_axi_bresp,
//Read address channel
input s0_axi_arvalid,
output s0_axi_arready,
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr,
input [2:0] s0_axi_arprot,
//Read data channel
output s0_axi_rvalid,
input s0_axi_rready,
output [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_rdata,
output [1:0] s0_axi_rresp,
output dev_irq_assert,
output pcie_user_logic_rst,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst,
output nvme_csts_rdy,
output [8:0] sq_valid,
output [7:0] io_sq1_size,
output [7:0] io_sq2_size,
output [7:0] io_sq3_size,
output [7:0] io_sq4_size,
output [7:0] io_sq5_size,
output [7:0] io_sq6_size,
output [7:0] io_sq7_size,
output [7:0] io_sq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
output [3:0] io_sq1_cq_vec,
output [3:0] io_sq2_cq_vec,
output [3:0] io_sq3_cq_vec,
output [3:0] io_sq4_cq_vec,
output [3:0] io_sq5_cq_vec,
output [3:0] io_sq6_cq_vec,
output [3:0] io_sq7_cq_vec,
output [3:0] io_sq8_cq_vec,
output [8:0] cq_valid,
output [7:0] io_cq1_size,
output [7:0] io_cq2_size,
output [7:0] io_cq3_size,
output [7:0] io_cq4_size,
output [7:0] io_cq5_size,
output [7:0] io_cq6_size,
output [7:0] io_cq7_size,
output [7:0] io_cq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
output [8:0] io_cq_irq_en,
output [2:0] io_cq1_iv,
output [2:0] io_cq2_iv,
output [2:0] io_cq3_iv,
output [2:0] io_cq4_iv,
output [2:0] io_cq5_iv,
output [2:0] io_cq6_iv,
output [2:0] io_cq7_iv,
output [2:0] io_cq8_iv,
output hcmd_sq_rd_en,
input [18:0] hcmd_sq_rd_data,
input hcmd_sq_empty_n,
output [10:0] hcmd_table_rd_addr,
input [31:0] hcmd_table_rd_data,
output hcmd_cq_wr1_en,
output [34:0] hcmd_cq_wr1_data0,
output [34:0] hcmd_cq_wr1_data1,
input hcmd_cq_wr1_rdy_n,
output dma_cmd_wr_en,
output [49:0] dma_cmd_wr_data0,
output [49:0] dma_cmd_wr_data1,
input dma_cmd_wr_rdy_n,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
input m0_axi_aclk,
input m0_axi_aresetn,
// Write address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_awid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_awaddr,
output [7:0] m0_axi_awlen,
output [2:0] m0_axi_awsize,
output [1:0] m0_axi_awburst,
output [1:0] m0_axi_awlock,
output [3:0] m0_axi_awcache,
output [2:0] m0_axi_awprot,
output [3:0] m0_axi_awregion,
output [3:0] m0_axi_awqos,
output [C_M0_AXI_AWUSER_WIDTH-1:0] m0_axi_awuser,
output m0_axi_awvalid,
input m0_axi_awready,
// Write data channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_wid,
output [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_wdata,
output [(C_M0_AXI_DATA_WIDTH/8)-1:0] m0_axi_wstrb,
output m0_axi_wlast,
output [C_M0_AXI_WUSER_WIDTH-1:0] m0_axi_wuser,
output m0_axi_wvalid,
input m0_axi_wready,
// Write response channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_bid,
input [1:0] m0_axi_bresp,
input m0_axi_bvalid,
input [C_M0_AXI_BUSER_WIDTH-1:0] m0_axi_buser,
output m0_axi_bready,
// Read address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_arid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_araddr,
output [7:0] m0_axi_arlen,
output [2:0] m0_axi_arsize,
output [1:0] m0_axi_arburst,
output [1:0] m0_axi_arlock,
output [3:0] m0_axi_arcache,
output [2:0] m0_axi_arprot,
output [3:0] m0_axi_arregion,
output [3:0] m0_axi_arqos,
output [C_M0_AXI_ARUSER_WIDTH-1:0] m0_axi_aruser,
output m0_axi_arvalid,
input m0_axi_arready,
// Read data channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_rid,
input [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_rdata,
input [1:0] m0_axi_rresp,
input m0_axi_rlast,
input [C_M0_AXI_RUSER_WIDTH-1:0] m0_axi_ruser,
input m0_axi_rvalid,
output m0_axi_rready,
output pcie_rx_fifo_rd_en,
input [C_M0_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
output pcie_rx_fifo_free_en,
output [9:4] pcie_rx_fifo_free_len,
input pcie_rx_fifo_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M0_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n,
output dma_rx_done_wr_en,
output [20:0] dma_rx_done_wr_data,
input dma_rx_done_wr_rdy_n,
input pcie_user_clk,
input pcie_user_rst_n,
input dev_rx_cmd_wr_en,
input [29:0] dev_rx_cmd_wr_data,
output dev_rx_cmd_full_n,
input dev_tx_cmd_wr_en,
input [29:0] dev_tx_cmd_wr_data,
output dev_tx_cmd_full_n,
input [7:0] dma_rx_direct_done_cnt,
input [7:0] dma_tx_direct_done_cnt,
input [7:0] dma_rx_done_cnt,
input [7:0] dma_tx_done_cnt,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable
);
wire w_m0_axi_bresp_err;
wire w_m0_axi_rresp_err;
s_axi_reg # (
.C_S_AXI_ADDR_WIDTH (C_S0_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S0_AXI_DATA_WIDTH),
.C_S_AXI_BASEADDR (C_S0_AXI_BASEADDR),
.C_S_AXI_HIGHADDR (C_S0_AXI_HIGHADDR)
)
s_axi_reg_inst0 (
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
.s_axi_aclk (s0_axi_aclk),
.s_axi_aresetn (s0_axi_aresetn),
//Write address channel
.s_axi_awaddr (s0_axi_awaddr),
.s_axi_awready (s0_axi_awready),
.s_axi_awvalid (s0_axi_awvalid),
.s_axi_awprot (s0_axi_awprot),
//Write data channel
.s_axi_wvalid (s0_axi_wvalid),
.s_axi_wready (s0_axi_wready),
.s_axi_wdata (s0_axi_wdata),
.s_axi_wstrb (s0_axi_wstrb),
//Write response channel
.s_axi_bvalid (s0_axi_bvalid),
.s_axi_bready (s0_axi_bready),
.s_axi_bresp (s0_axi_bresp),
//Read address channel
.s_axi_arvalid (s0_axi_arvalid),
.s_axi_arready (s0_axi_arready),
.s_axi_araddr (s0_axi_araddr),
.s_axi_arprot (s0_axi_arprot),
//Read data channel
.s_axi_rvalid (s0_axi_rvalid),
.s_axi_rready (s0_axi_rready),
.s_axi_rdata (s0_axi_rdata),
.s_axi_rresp (s0_axi_rresp),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.m0_axi_bresp_err (w_m0_axi_bresp_err),
.m0_axi_rresp_err (w_m0_axi_rresp_err),
.dev_irq_assert (dev_irq_assert),
.pcie_user_logic_rst (pcie_user_logic_rst),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n),
.hcmd_table_rd_addr (hcmd_table_rd_addr),
.hcmd_table_rd_data (hcmd_table_rd_data),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.pcie_link_up (pcie_link_up),
.pl_ltssm_state (pl_ltssm_state),
.cfg_command (cfg_command),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable)
);
m_axi_dma # (
.C_M_AXI_ADDR_WIDTH (C_M0_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M0_AXI_DATA_WIDTH),
.C_M_AXI_ID_WIDTH (C_M0_AXI_ID_WIDTH),
.C_M_AXI_AWUSER_WIDTH (C_M0_AXI_AWUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH (C_M0_AXI_WUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH (C_M0_AXI_BUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH (C_M0_AXI_ARUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH (C_M0_AXI_RUSER_WIDTH)
)
m_axi_dma_inst0(
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
.m_axi_aclk (m0_axi_aclk),
.m_axi_aresetn (m0_axi_aresetn),
// Write address channel
.m_axi_awid (m0_axi_awid),
.m_axi_awaddr (m0_axi_awaddr),
.m_axi_awlen (m0_axi_awlen),
.m_axi_awsize (m0_axi_awsize),
.m_axi_awburst (m0_axi_awburst),
.m_axi_awlock (m0_axi_awlock),
.m_axi_awcache (m0_axi_awcache),
.m_axi_awprot (m0_axi_awprot),
.m_axi_awregion (m0_axi_awregion),
.m_axi_awqos (m0_axi_awqos),
.m_axi_awuser (m0_axi_awuser),
.m_axi_awvalid (m0_axi_awvalid),
.m_axi_awready (m0_axi_awready),
// Write data channel
.m_axi_wid (m0_axi_wid),
.m_axi_wdata (m0_axi_wdata),
.m_axi_wstrb (m0_axi_wstrb),
.m_axi_wlast (m0_axi_wlast),
.m_axi_wuser (m0_axi_wuser),
.m_axi_wvalid (m0_axi_wvalid),
.m_axi_wready (m0_axi_wready),
// Write response channel
.m_axi_bid (m0_axi_bid),
.m_axi_bresp (m0_axi_bresp),
.m_axi_bvalid (m0_axi_bvalid),
.m_axi_buser (m0_axi_buser),
.m_axi_bready (m0_axi_bready),
// Read address channel
.m_axi_arid (m0_axi_arid),
.m_axi_araddr (m0_axi_araddr),
.m_axi_arlen (m0_axi_arlen),
.m_axi_arsize (m0_axi_arsize),
.m_axi_arburst (m0_axi_arburst),
.m_axi_arlock (m0_axi_arlock),
.m_axi_arcache (m0_axi_arcache),
.m_axi_arprot (m0_axi_arprot),
.m_axi_arregion (m0_axi_arregion),
.m_axi_arqos (m0_axi_arqos),
.m_axi_aruser (m0_axi_aruser),
.m_axi_arvalid (m0_axi_arvalid),
.m_axi_arready (m0_axi_arready),
// Read data channel
.m_axi_rid (m0_axi_rid),
.m_axi_rdata (m0_axi_rdata),
.m_axi_rresp (m0_axi_rresp),
.m_axi_rlast (m0_axi_rlast),
.m_axi_ruser (m0_axi_ruser),
.m_axi_rvalid (m0_axi_rvalid),
.m_axi_rready (m0_axi_rready),
.m_axi_bresp_err (w_m0_axi_bresp_err),
.m_axi_rresp_err (w_m0_axi_rresp_err),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n),
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module s_axi_top # (
parameter C_S0_AXI_ADDR_WIDTH = 32,
parameter C_S0_AXI_DATA_WIDTH = 32,
parameter C_S0_AXI_BASEADDR = 32'h80000000,
parameter C_S0_AXI_HIGHADDR = 32'h80010000,
parameter C_M0_AXI_ADDR_WIDTH = 32,
parameter C_M0_AXI_DATA_WIDTH = 64,
parameter C_M0_AXI_ID_WIDTH = 1,
parameter C_M0_AXI_AWUSER_WIDTH = 1,
parameter C_M0_AXI_WUSER_WIDTH = 1,
parameter C_M0_AXI_BUSER_WIDTH = 1,
parameter C_M0_AXI_ARUSER_WIDTH = 1,
parameter C_M0_AXI_RUSER_WIDTH = 1,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
input s0_axi_aclk,
input s0_axi_aresetn,
//Write address channel
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr,
output s0_axi_awready,
input s0_axi_awvalid,
input [2:0] s0_axi_awprot,
//Write data channel
input s0_axi_wvalid,
output s0_axi_wready,
input [C_S0_AXI_DATA_WIDTH-1 :0] s0_axi_wdata,
input [(C_S0_AXI_DATA_WIDTH/8)-1:0] s0_axi_wstrb,
//Write response channel
output s0_axi_bvalid,
input s0_axi_bready,
output [1:0] s0_axi_bresp,
//Read address channel
input s0_axi_arvalid,
output s0_axi_arready,
input [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr,
input [2:0] s0_axi_arprot,
//Read data channel
output s0_axi_rvalid,
input s0_axi_rready,
output [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_rdata,
output [1:0] s0_axi_rresp,
output dev_irq_assert,
output pcie_user_logic_rst,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst,
output nvme_csts_rdy,
output [8:0] sq_valid,
output [7:0] io_sq1_size,
output [7:0] io_sq2_size,
output [7:0] io_sq3_size,
output [7:0] io_sq4_size,
output [7:0] io_sq5_size,
output [7:0] io_sq6_size,
output [7:0] io_sq7_size,
output [7:0] io_sq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
output [3:0] io_sq1_cq_vec,
output [3:0] io_sq2_cq_vec,
output [3:0] io_sq3_cq_vec,
output [3:0] io_sq4_cq_vec,
output [3:0] io_sq5_cq_vec,
output [3:0] io_sq6_cq_vec,
output [3:0] io_sq7_cq_vec,
output [3:0] io_sq8_cq_vec,
output [8:0] cq_valid,
output [7:0] io_cq1_size,
output [7:0] io_cq2_size,
output [7:0] io_cq3_size,
output [7:0] io_cq4_size,
output [7:0] io_cq5_size,
output [7:0] io_cq6_size,
output [7:0] io_cq7_size,
output [7:0] io_cq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
output [8:0] io_cq_irq_en,
output [2:0] io_cq1_iv,
output [2:0] io_cq2_iv,
output [2:0] io_cq3_iv,
output [2:0] io_cq4_iv,
output [2:0] io_cq5_iv,
output [2:0] io_cq6_iv,
output [2:0] io_cq7_iv,
output [2:0] io_cq8_iv,
output hcmd_sq_rd_en,
input [18:0] hcmd_sq_rd_data,
input hcmd_sq_empty_n,
output [10:0] hcmd_table_rd_addr,
input [31:0] hcmd_table_rd_data,
output hcmd_cq_wr1_en,
output [34:0] hcmd_cq_wr1_data0,
output [34:0] hcmd_cq_wr1_data1,
input hcmd_cq_wr1_rdy_n,
output dma_cmd_wr_en,
output [49:0] dma_cmd_wr_data0,
output [49:0] dma_cmd_wr_data1,
input dma_cmd_wr_rdy_n,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
input m0_axi_aclk,
input m0_axi_aresetn,
// Write address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_awid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_awaddr,
output [7:0] m0_axi_awlen,
output [2:0] m0_axi_awsize,
output [1:0] m0_axi_awburst,
output [1:0] m0_axi_awlock,
output [3:0] m0_axi_awcache,
output [2:0] m0_axi_awprot,
output [3:0] m0_axi_awregion,
output [3:0] m0_axi_awqos,
output [C_M0_AXI_AWUSER_WIDTH-1:0] m0_axi_awuser,
output m0_axi_awvalid,
input m0_axi_awready,
// Write data channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_wid,
output [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_wdata,
output [(C_M0_AXI_DATA_WIDTH/8)-1:0] m0_axi_wstrb,
output m0_axi_wlast,
output [C_M0_AXI_WUSER_WIDTH-1:0] m0_axi_wuser,
output m0_axi_wvalid,
input m0_axi_wready,
// Write response channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_bid,
input [1:0] m0_axi_bresp,
input m0_axi_bvalid,
input [C_M0_AXI_BUSER_WIDTH-1:0] m0_axi_buser,
output m0_axi_bready,
// Read address channel
output [C_M0_AXI_ID_WIDTH-1:0] m0_axi_arid,
output [C_M0_AXI_ADDR_WIDTH-1:0] m0_axi_araddr,
output [7:0] m0_axi_arlen,
output [2:0] m0_axi_arsize,
output [1:0] m0_axi_arburst,
output [1:0] m0_axi_arlock,
output [3:0] m0_axi_arcache,
output [2:0] m0_axi_arprot,
output [3:0] m0_axi_arregion,
output [3:0] m0_axi_arqos,
output [C_M0_AXI_ARUSER_WIDTH-1:0] m0_axi_aruser,
output m0_axi_arvalid,
input m0_axi_arready,
// Read data channel
input [C_M0_AXI_ID_WIDTH-1:0] m0_axi_rid,
input [C_M0_AXI_DATA_WIDTH-1:0] m0_axi_rdata,
input [1:0] m0_axi_rresp,
input m0_axi_rlast,
input [C_M0_AXI_RUSER_WIDTH-1:0] m0_axi_ruser,
input m0_axi_rvalid,
output m0_axi_rready,
output pcie_rx_fifo_rd_en,
input [C_M0_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
output pcie_rx_fifo_free_en,
output [9:4] pcie_rx_fifo_free_len,
input pcie_rx_fifo_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M0_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n,
output dma_rx_done_wr_en,
output [20:0] dma_rx_done_wr_data,
input dma_rx_done_wr_rdy_n,
input pcie_user_clk,
input pcie_user_rst_n,
input dev_rx_cmd_wr_en,
input [29:0] dev_rx_cmd_wr_data,
output dev_rx_cmd_full_n,
input dev_tx_cmd_wr_en,
input [29:0] dev_tx_cmd_wr_data,
output dev_tx_cmd_full_n,
input [7:0] dma_rx_direct_done_cnt,
input [7:0] dma_tx_direct_done_cnt,
input [7:0] dma_rx_done_cnt,
input [7:0] dma_tx_done_cnt,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable
);
wire w_m0_axi_bresp_err;
wire w_m0_axi_rresp_err;
s_axi_reg # (
.C_S_AXI_ADDR_WIDTH (C_S0_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S0_AXI_DATA_WIDTH),
.C_S_AXI_BASEADDR (C_S0_AXI_BASEADDR),
.C_S_AXI_HIGHADDR (C_S0_AXI_HIGHADDR)
)
s_axi_reg_inst0 (
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
.s_axi_aclk (s0_axi_aclk),
.s_axi_aresetn (s0_axi_aresetn),
//Write address channel
.s_axi_awaddr (s0_axi_awaddr),
.s_axi_awready (s0_axi_awready),
.s_axi_awvalid (s0_axi_awvalid),
.s_axi_awprot (s0_axi_awprot),
//Write data channel
.s_axi_wvalid (s0_axi_wvalid),
.s_axi_wready (s0_axi_wready),
.s_axi_wdata (s0_axi_wdata),
.s_axi_wstrb (s0_axi_wstrb),
//Write response channel
.s_axi_bvalid (s0_axi_bvalid),
.s_axi_bready (s0_axi_bready),
.s_axi_bresp (s0_axi_bresp),
//Read address channel
.s_axi_arvalid (s0_axi_arvalid),
.s_axi_arready (s0_axi_arready),
.s_axi_araddr (s0_axi_araddr),
.s_axi_arprot (s0_axi_arprot),
//Read data channel
.s_axi_rvalid (s0_axi_rvalid),
.s_axi_rready (s0_axi_rready),
.s_axi_rdata (s0_axi_rdata),
.s_axi_rresp (s0_axi_rresp),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.m0_axi_bresp_err (w_m0_axi_bresp_err),
.m0_axi_rresp_err (w_m0_axi_rresp_err),
.dev_irq_assert (dev_irq_assert),
.pcie_user_logic_rst (pcie_user_logic_rst),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n),
.hcmd_table_rd_addr (hcmd_table_rd_addr),
.hcmd_table_rd_data (hcmd_table_rd_data),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.pcie_link_up (pcie_link_up),
.pl_ltssm_state (pl_ltssm_state),
.cfg_command (cfg_command),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable)
);
m_axi_dma # (
.C_M_AXI_ADDR_WIDTH (C_M0_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M0_AXI_DATA_WIDTH),
.C_M_AXI_ID_WIDTH (C_M0_AXI_ID_WIDTH),
.C_M_AXI_AWUSER_WIDTH (C_M0_AXI_AWUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH (C_M0_AXI_WUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH (C_M0_AXI_BUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH (C_M0_AXI_ARUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH (C_M0_AXI_RUSER_WIDTH)
)
m_axi_dma_inst0(
////////////////////////////////////////////////////////////////
//AXI4 master interface signals
.m_axi_aclk (m0_axi_aclk),
.m_axi_aresetn (m0_axi_aresetn),
// Write address channel
.m_axi_awid (m0_axi_awid),
.m_axi_awaddr (m0_axi_awaddr),
.m_axi_awlen (m0_axi_awlen),
.m_axi_awsize (m0_axi_awsize),
.m_axi_awburst (m0_axi_awburst),
.m_axi_awlock (m0_axi_awlock),
.m_axi_awcache (m0_axi_awcache),
.m_axi_awprot (m0_axi_awprot),
.m_axi_awregion (m0_axi_awregion),
.m_axi_awqos (m0_axi_awqos),
.m_axi_awuser (m0_axi_awuser),
.m_axi_awvalid (m0_axi_awvalid),
.m_axi_awready (m0_axi_awready),
// Write data channel
.m_axi_wid (m0_axi_wid),
.m_axi_wdata (m0_axi_wdata),
.m_axi_wstrb (m0_axi_wstrb),
.m_axi_wlast (m0_axi_wlast),
.m_axi_wuser (m0_axi_wuser),
.m_axi_wvalid (m0_axi_wvalid),
.m_axi_wready (m0_axi_wready),
// Write response channel
.m_axi_bid (m0_axi_bid),
.m_axi_bresp (m0_axi_bresp),
.m_axi_bvalid (m0_axi_bvalid),
.m_axi_buser (m0_axi_buser),
.m_axi_bready (m0_axi_bready),
// Read address channel
.m_axi_arid (m0_axi_arid),
.m_axi_araddr (m0_axi_araddr),
.m_axi_arlen (m0_axi_arlen),
.m_axi_arsize (m0_axi_arsize),
.m_axi_arburst (m0_axi_arburst),
.m_axi_arlock (m0_axi_arlock),
.m_axi_arcache (m0_axi_arcache),
.m_axi_arprot (m0_axi_arprot),
.m_axi_arregion (m0_axi_arregion),
.m_axi_arqos (m0_axi_arqos),
.m_axi_aruser (m0_axi_aruser),
.m_axi_arvalid (m0_axi_arvalid),
.m_axi_arready (m0_axi_arready),
// Read data channel
.m_axi_rid (m0_axi_rid),
.m_axi_rdata (m0_axi_rdata),
.m_axi_rresp (m0_axi_rresp),
.m_axi_rlast (m0_axi_rlast),
.m_axi_ruser (m0_axi_ruser),
.m_axi_rvalid (m0_axi_rvalid),
.m_axi_rready (m0_axi_rready),
.m_axi_bresp_err (w_m0_axi_bresp_err),
.m_axi_rresp_err (w_m0_axi_rresp_err),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n),
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n)
);
endmodule |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
integer v;
reg i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oa; // From a of a.v
wire oz; // From z of z.v
// End of automatics
a a (.*);
z z (.*);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz);
`endif
cyc <= cyc + 1;
i <= cyc[0];
if (cyc==0) begin
v = 3;
if (v !== 3) $stop;
if (assignin(v) !== 2) $stop;
if (v !== 3) $stop; // Make sure V didn't get changed
end
else if (cyc<10) begin
if (cyc==11 && oz!==1'b0) $stop;
if (cyc==12 && oz!==1'b1) $stop;
if (cyc==12 && oa!==1'b1) $stop;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer assignin(input integer i);
i = 2;
assignin = i;
endfunction
endmodule
module a (input i, output oa);
// verilator lint_off ASSIGNIN
assign i = 1'b1;
assign oa = i;
endmodule
module z (input i, output oz);
assign oz = i;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
integer v;
reg i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oa; // From a of a.v
wire oz; // From z of z.v
// End of automatics
a a (.*);
z z (.*);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz);
`endif
cyc <= cyc + 1;
i <= cyc[0];
if (cyc==0) begin
v = 3;
if (v !== 3) $stop;
if (assignin(v) !== 2) $stop;
if (v !== 3) $stop; // Make sure V didn't get changed
end
else if (cyc<10) begin
if (cyc==11 && oz!==1'b0) $stop;
if (cyc==12 && oz!==1'b1) $stop;
if (cyc==12 && oa!==1'b1) $stop;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer assignin(input integer i);
i = 2;
assignin = i;
endfunction
endmodule
module a (input i, output oa);
// verilator lint_off ASSIGNIN
assign i = 1'b1;
assign oa = i;
endmodule
module z (input i, output oz);
assign oz = i;
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_w the_niosii_jtag_uart_0_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_r the_niosii_jtag_uart_0_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0 (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
niosii_jtag_uart_0_scfifo_w the_niosii_jtag_uart_0_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
niosii_jtag_uart_0_scfifo_r the_niosii_jtag_uart_0_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic niosii_jtag_uart_0_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam niosii_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_w the_niosii_jtag_uart_0_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_r the_niosii_jtag_uart_0_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0 (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
niosii_jtag_uart_0_scfifo_w the_niosii_jtag_uart_0_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
niosii_jtag_uart_0_scfifo_r the_niosii_jtag_uart_0_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic niosii_jtag_uart_0_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam niosii_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
module t (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
reg inmod;
generate
if (1) begin
// Traces as genblk1.ingen
integer ingen;
initial $display("ingen: {mod}.genblk1 %m");
end
endgenerate
integer rawmod;
initial begin
begin
integer upa;
begin : d3nameda
// %m='.d3nameda' var=_unnamed#.d3nameda.b1
integer d3a;
$display("d3a: {mod}.d3nameda %m");
end
end
end
initial begin
integer b2;
$display("b2: {mod} %m");
begin : b3named
integer b3n;
$display("b3n: {mod}.b3named: %m");
end
if (1) begin
integer b3;
$display("b3: {mod} %m");
if (1) begin
begin
begin
begin
integer b4;
$display("b4: {mod} %m");
end
end
end
end
else begin
integer b4;
$display("bb %m");
end
end
else begin
integer b4;
$display("b4 %m");
end
tsk;
$write("*-* All Finished *-*\n");
$finish;
end
task tsk;
integer t1;
$display("t1 {mod}.tsk %m");
begin
integer t2;
$display("t2 {mod}.tsk %m");
end
endtask
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_table_cid # (
parameter P_DATA_WIDTH = 20,
parameter P_ADDR_WIDTH = 7
)
(
input clk,
input wr_en,
input [P_ADDR_WIDTH-1:0] wr_addr,
input [P_DATA_WIDTH-1:0] wr_data,
input [P_ADDR_WIDTH-1:0] rd_addr,
output [P_DATA_WIDTH-1:0] rd_data
);
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = rd_addr[P_ADDR_WIDTH-1:0];
assign wraddr = wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, rd_addr[P_ADDR_WIDTH-1:0]};
assign wraddr = {zero_padding, wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_table_cid # (
parameter P_DATA_WIDTH = 20,
parameter P_ADDR_WIDTH = 7
)
(
input clk,
input wr_en,
input [P_ADDR_WIDTH-1:0] wr_addr,
input [P_DATA_WIDTH-1:0] wr_data,
input [P_ADDR_WIDTH-1:0] rd_addr,
output [P_DATA_WIDTH-1:0] rd_data
);
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = rd_addr[P_ADDR_WIDTH-1:0];
assign wraddr = wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, rd_addr[P_ADDR_WIDTH-1:0]};
assign wraddr = {zero_padding, wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t_embed1_wrap (/*AUTOARG*/
// Outputs
bit_out, vec_out, wide_out, did_init_out,
// Inputs
clk, bit_in, vec_in, wide_in, is_ref
);
/*AUTOINOUTMODULE("t_embed1_child")*/
// Beginning of automatic in/out/inouts (from specific module)
output bit_out;
output [30:0] vec_out;
output [123:0] wide_out;
output did_init_out;
input clk;
input bit_in;
input [30:0] vec_in;
input [123:0] wide_in;
input is_ref;
// End of automatics
`ifdef verilator
// Import $t_embed_child__initial etc as a DPI function
`endif
//TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this
import "DPI-C" context function void t_embed_child_initial();
import "DPI-C" context function void t_embed_child_final();
import "DPI-C" context function void t_embed_child_eval();
import "DPI-C" context function void t_embed_child_io_eval
(
//TODO we support bit, but not logic
input bit clk,
input bit bit_in,
input bit [30:0] vec_in,
input bit [123:0] wide_in,
input bit is_ref,
output bit bit_out,
output bit [30:0] vec_out,
output bit [123:0] wide_out,
output bit did_init_out);
initial begin
// Load all values
t_embed_child_initial();
end
// Only if system verilog, and if a "final" block in the code
final begin
t_embed_child_final();
end
bit _temp_bit_out;
bit _temp_did_init_out;
bit [30:0] _temp_vec_out;
bit [123:0] _temp_wide_out;
always @* begin
t_embed_child_io_eval(
clk,
bit_in,
vec_in,
wide_in,
is_ref,
_temp_bit_out,
_temp_vec_out,
_temp_wide_out,
_temp_did_init_out
);
// TODO might eliminate these temporaries
bit_out = _temp_bit_out;
did_init_out = _temp_did_init_out;
end
// Send all variables every cycle,
// or have a sensitivity routine for each?
// How to make sure we call eval at end of variable changes?
// #0 (though not verilator compatible!)
// TODO for now, we know what changes when
always @ (posedge clk) begin
vec_out <= _temp_vec_out;
wide_out <= _temp_wide_out;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t_embed1_wrap (/*AUTOARG*/
// Outputs
bit_out, vec_out, wide_out, did_init_out,
// Inputs
clk, bit_in, vec_in, wide_in, is_ref
);
/*AUTOINOUTMODULE("t_embed1_child")*/
// Beginning of automatic in/out/inouts (from specific module)
output bit_out;
output [30:0] vec_out;
output [123:0] wide_out;
output did_init_out;
input clk;
input bit_in;
input [30:0] vec_in;
input [123:0] wide_in;
input is_ref;
// End of automatics
`ifdef verilator
// Import $t_embed_child__initial etc as a DPI function
`endif
//TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this
import "DPI-C" context function void t_embed_child_initial();
import "DPI-C" context function void t_embed_child_final();
import "DPI-C" context function void t_embed_child_eval();
import "DPI-C" context function void t_embed_child_io_eval
(
//TODO we support bit, but not logic
input bit clk,
input bit bit_in,
input bit [30:0] vec_in,
input bit [123:0] wide_in,
input bit is_ref,
output bit bit_out,
output bit [30:0] vec_out,
output bit [123:0] wide_out,
output bit did_init_out);
initial begin
// Load all values
t_embed_child_initial();
end
// Only if system verilog, and if a "final" block in the code
final begin
t_embed_child_final();
end
bit _temp_bit_out;
bit _temp_did_init_out;
bit [30:0] _temp_vec_out;
bit [123:0] _temp_wide_out;
always @* begin
t_embed_child_io_eval(
clk,
bit_in,
vec_in,
wide_in,
is_ref,
_temp_bit_out,
_temp_vec_out,
_temp_wide_out,
_temp_did_init_out
);
// TODO might eliminate these temporaries
bit_out = _temp_bit_out;
did_init_out = _temp_did_init_out;
end
// Send all variables every cycle,
// or have a sensitivity routine for each?
// How to make sure we call eval at end of variable changes?
// #0 (though not verilator compatible!)
// TODO for now, we know what changes when
always @ (posedge clk) begin
vec_out <= _temp_vec_out;
wide_out <= _temp_wide_out;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_order_a (/*AUTOARG*/
// Outputs
m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12,
// Inputs
clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one
);
input clk;
input [7:0] a_to_clk_levm3;
input [7:0] b_to_clk_levm1;
input [7:0] c_com_levs10;
input [7:0] d_to_clk_levm2;
input [7:0] one;
output [7:0] m_from_clk_lev1_r;
output [7:0] n_from_clk_lev2;
output [7:0] o_from_com_levs11;
output [7:0] o_from_comandclk_levs12;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [7:0] m_from_clk_lev1_r;
// End of automatics
// surefire lint_off ASWEBB
// surefire lint_off ASWEMB
wire [7:0] a_to_clk_levm1;
wire [7:0] a_to_clk_levm2;
wire [7:0] c_com_levs11;
reg [7:0] o_from_comandclk_levs12;
wire [7:0] n_from_clk_lev2;
wire [7:0] n_from_clk_lev3;
assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2;
assign a_to_clk_levm2 = a_to_clk_levm3 + 0;
always @ (posedge clk) begin
m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1;
end
assign c_com_levs11 = c_com_levs10 + one;
always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3;
assign n_from_clk_lev2 = m_from_clk_lev1_r;
assign n_from_clk_lev3 = n_from_clk_lev2;
wire [7:0] o_from_com_levs11 = c_com_levs10 + 1;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t_order_a (/*AUTOARG*/
// Outputs
m_from_clk_lev1_r, n_from_clk_lev2, o_from_com_levs11, o_from_comandclk_levs12,
// Inputs
clk, a_to_clk_levm3, b_to_clk_levm1, c_com_levs10, d_to_clk_levm2, one
);
input clk;
input [7:0] a_to_clk_levm3;
input [7:0] b_to_clk_levm1;
input [7:0] c_com_levs10;
input [7:0] d_to_clk_levm2;
input [7:0] one;
output [7:0] m_from_clk_lev1_r;
output [7:0] n_from_clk_lev2;
output [7:0] o_from_com_levs11;
output [7:0] o_from_comandclk_levs12;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [7:0] m_from_clk_lev1_r;
// End of automatics
// surefire lint_off ASWEBB
// surefire lint_off ASWEMB
wire [7:0] a_to_clk_levm1;
wire [7:0] a_to_clk_levm2;
wire [7:0] c_com_levs11;
reg [7:0] o_from_comandclk_levs12;
wire [7:0] n_from_clk_lev2;
wire [7:0] n_from_clk_lev3;
assign a_to_clk_levm1 = a_to_clk_levm2 + d_to_clk_levm2;
assign a_to_clk_levm2 = a_to_clk_levm3 + 0;
always @ (posedge clk) begin
m_from_clk_lev1_r <= a_to_clk_levm1 + b_to_clk_levm1;
end
assign c_com_levs11 = c_com_levs10 + one;
always @ (/*AS*/c_com_levs11 or n_from_clk_lev3) o_from_comandclk_levs12 = c_com_levs11 + n_from_clk_lev3;
assign n_from_clk_lev2 = m_from_clk_lev1_r;
assign n_from_clk_lev3 = n_from_clk_lev2;
wire [7:0] o_from_com_levs11 = c_com_levs10 + 1;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_on GENCLK
reg [31:0] long;
reg [63:0] quad;
wire [31:0] longout;
wire [63:0] quadout;
wire [7:0] narrow = long[7:0];
sub sub (/*AUTOINST*/
// Outputs
.longout (longout[31:0]),
.quadout (quadout[63:0]),
// Inputs
.narrow (narrow[7:0]),
.quad (quad[63:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
long <= 32'h12345678;
quad <= 64'h12345678_abcdef12;
end
if (cyc==2) begin
if (longout !== 32'h79) $stop;
if (quadout !== 64'h12345678_abcdef13) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (input [7:0] narrow, input [63:0] quad, output [31:0] longout, output [63:0] quadout);
// verilator public_module
`ifdef verilator
wire [31:0] longout = $c32("(",narrow,"+1)");
wire [63:0] quadout = $c64("(",quad,"+1)");
`else
wire [31:0] longout = narrow + 8'd1;
wire [63:0] quadout = quad + 64'd1;
`endif
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_sq_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 11,
parameter P_FIFO_DEPTH_WIDTH = 2
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 2;
localparam LP_ADDR_TOTAL_WITDH = 10;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// spi_shift.v ////
//// ////
//// This file is part of the SPI IP core project ////
//// http://www.opencores.org/projects/spi/ ////
//// ////
//// Author(s): ////
//// - Simon Srot ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
////
//// /* Modifications to spi_shift.v */
//// /* Copyright (c) 2006 Rice University */
//// /* All Rights Reserved */
//// /* This code is covered by the Rice-WARP license */
//// /* See http://warp.rice.edu/license/ for details */
module spi_shift (clk, rst, len, lsb, go,
pos_edge, neg_edge, rx_negedge, tx_negedge,
tip, last,
p_in, p_out, s_clk, s_out);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input [4:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input go; // start stansfer
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input rx_negedge; // s_in is sampled on negative edge
input tx_negedge; // s_out is driven on negative edge
output tip; // transfer in progress
output last; // last bit
input /*31*/ [17:0] p_in; // parallel in
output [17:0] p_out; // parallel out
input s_clk; // serial clock
output s_out; // serial out
reg s_out;
reg tip;
reg [5:0] cnt; // data bit count
wire [17:0] data; // shift register
wire [5:0] tx_bit_pos; // next bit position
wire [5:0] rx_bit_pos; // next bit position
wire rx_clk; // rx clock enable
wire tx_clk; // tx clock enable
//assign p_out = data;
assign data = p_in;
assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{5{1'b0}},1'b1};
assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{5{1'b0}},1'b1} : cnt) :
(rx_negedge ? cnt : cnt - {{5{1'b0}},1'b1});
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
always @(posedge clk or posedge rst)
begin
if(rst)
cnt <= #Tp {6{1'b0}};
else
begin
if(tip)
cnt <= #Tp pos_edge ? (cnt - {{5{1'b0}}, 1'b1}) : cnt;
else
cnt <= #Tp !(|len) ? {1'b1, {5{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst)
begin
if(rst)
tip <= #Tp 1'b0;
else if(go && ~tip)
tip <= #Tp 1'b1;
else if(tip && last && pos_edge)
tip <= #Tp 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst)
begin
if (rst)
s_out <= #Tp 1'b0;
else
s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[4:0]] : s_out;
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_cq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output [6:0] hcmd_cid_rd_addr,
input [19:0] hcmd_cid_rd_data,
input [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
input [7:0] admin_cq_size,
output [7:0] admin_cq_tail_ptr,
output [7:0] io_cq1_tail_ptr,
output [7:0] io_cq2_tail_ptr,
output [7:0] io_cq3_tail_ptr,
output [7:0] io_cq4_tail_ptr,
output [7:0] io_cq5_tail_ptr,
output [7:0] io_cq6_tail_ptr,
output [7:0] io_cq7_tail_ptr,
output [7:0] io_cq8_tail_ptr,
input [7:0] admin_sq_head_ptr,
input [7:0] io_sq1_head_ptr,
input [7:0] io_sq2_head_ptr,
input [7:0] io_sq3_head_ptr,
input [7:0] io_sq4_head_ptr,
input [7:0] io_sq5_head_ptr,
input [7:0] io_sq6_head_ptr,
input [7:0] io_sq7_head_ptr,
input [7:0] io_sq8_head_ptr,
output hcmd_slot_free_en,
output [6:0] hcmd_slot_invalid_tag,
output tx_cq_mwr_req,
output [7:0] tx_cq_mwr_tag,
output [11:2] tx_cq_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_cq_mwr_addr,
input tx_cq_mwr_req_ack,
input tx_cq_mwr_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] tx_cq_mwr_rd_data,
input tx_cq_mwr_data_last,
input hcmd_cq_wr0_en,
input [34:0] hcmd_cq_wr0_data0,
input [34:0] hcmd_cq_wr0_data1,
output hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] sq_valid,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input hcmd_cq_wr1_en,
input [34:0] hcmd_cq_wr1_data0,
input [34:0] hcmd_cq_wr1_data1,
output hcmd_cq_wr1_rdy_n
);
wire w_hcmd_cq_rd_en;
wire [34:0] w_hcmd_cq_rd_data;
wire w_hcmd_cq_empty_n;
pcie_hcmd_cq_fifo
pcie_hcmd_cq_fifo_inst0(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (hcmd_cq_wr0_en),
.wr0_data0 (hcmd_cq_wr0_data0),
.wr0_data1 (hcmd_cq_wr0_data1),
.wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.full_n (),
.rd_en (w_hcmd_cq_rd_en),
.rd_data (w_hcmd_cq_rd_data),
.empty_n (w_hcmd_cq_empty_n),
.wr1_clk (cpu_bus_clk),
.wr1_rst_n (pcie_user_rst_n),
.wr1_en (hcmd_cq_wr1_en),
.wr1_data0 (hcmd_cq_wr1_data0),
.wr1_data1 (hcmd_cq_wr1_data1),
.wr1_rdy_n (hcmd_cq_wr1_rdy_n)
);
pcie_hcmd_cq_req # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_cq_req_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.hcmd_cq_rd_en (w_hcmd_cq_rd_en),
.hcmd_cq_rd_data (w_hcmd_cq_rd_data),
.hcmd_cq_empty_n (w_hcmd_cq_empty_n),
.hcmd_cid_rd_addr (hcmd_cid_rd_addr),
.hcmd_cid_rd_data (hcmd_cid_rd_data),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.sq_valid (sq_valid),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.admin_cq_size (admin_cq_size),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.admin_cq_bs_addr (admin_cq_bs_addr),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_sq_head_ptr (admin_sq_head_ptr),
.io_sq1_head_ptr (io_sq1_head_ptr),
.io_sq2_head_ptr (io_sq2_head_ptr),
.io_sq3_head_ptr (io_sq3_head_ptr),
.io_sq4_head_ptr (io_sq4_head_ptr),
.io_sq5_head_ptr (io_sq5_head_ptr),
.io_sq6_head_ptr (io_sq6_head_ptr),
.io_sq7_head_ptr (io_sq7_head_ptr),
.io_sq8_head_ptr (io_sq8_head_ptr),
.hcmd_slot_free_en (hcmd_slot_free_en),
.hcmd_slot_invalid_tag (hcmd_slot_invalid_tag),
.tx_cq_mwr_req (tx_cq_mwr_req),
.tx_cq_mwr_tag (tx_cq_mwr_tag),
.tx_cq_mwr_len (tx_cq_mwr_len),
.tx_cq_mwr_addr (tx_cq_mwr_addr),
.tx_cq_mwr_req_ack (tx_cq_mwr_req_ack),
.tx_cq_mwr_rd_en (tx_cq_mwr_rd_en),
.tx_cq_mwr_rd_data (tx_cq_mwr_rd_data),
.tx_cq_mwr_data_last (tx_cq_mwr_data_last)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_cq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output [6:0] hcmd_cid_rd_addr,
input [19:0] hcmd_cid_rd_data,
input [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
input [7:0] admin_cq_size,
output [7:0] admin_cq_tail_ptr,
output [7:0] io_cq1_tail_ptr,
output [7:0] io_cq2_tail_ptr,
output [7:0] io_cq3_tail_ptr,
output [7:0] io_cq4_tail_ptr,
output [7:0] io_cq5_tail_ptr,
output [7:0] io_cq6_tail_ptr,
output [7:0] io_cq7_tail_ptr,
output [7:0] io_cq8_tail_ptr,
input [7:0] admin_sq_head_ptr,
input [7:0] io_sq1_head_ptr,
input [7:0] io_sq2_head_ptr,
input [7:0] io_sq3_head_ptr,
input [7:0] io_sq4_head_ptr,
input [7:0] io_sq5_head_ptr,
input [7:0] io_sq6_head_ptr,
input [7:0] io_sq7_head_ptr,
input [7:0] io_sq8_head_ptr,
output hcmd_slot_free_en,
output [6:0] hcmd_slot_invalid_tag,
output tx_cq_mwr_req,
output [7:0] tx_cq_mwr_tag,
output [11:2] tx_cq_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_cq_mwr_addr,
input tx_cq_mwr_req_ack,
input tx_cq_mwr_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] tx_cq_mwr_rd_data,
input tx_cq_mwr_data_last,
input hcmd_cq_wr0_en,
input [34:0] hcmd_cq_wr0_data0,
input [34:0] hcmd_cq_wr0_data1,
output hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] sq_valid,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input hcmd_cq_wr1_en,
input [34:0] hcmd_cq_wr1_data0,
input [34:0] hcmd_cq_wr1_data1,
output hcmd_cq_wr1_rdy_n
);
wire w_hcmd_cq_rd_en;
wire [34:0] w_hcmd_cq_rd_data;
wire w_hcmd_cq_empty_n;
pcie_hcmd_cq_fifo
pcie_hcmd_cq_fifo_inst0(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (hcmd_cq_wr0_en),
.wr0_data0 (hcmd_cq_wr0_data0),
.wr0_data1 (hcmd_cq_wr0_data1),
.wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.full_n (),
.rd_en (w_hcmd_cq_rd_en),
.rd_data (w_hcmd_cq_rd_data),
.empty_n (w_hcmd_cq_empty_n),
.wr1_clk (cpu_bus_clk),
.wr1_rst_n (pcie_user_rst_n),
.wr1_en (hcmd_cq_wr1_en),
.wr1_data0 (hcmd_cq_wr1_data0),
.wr1_data1 (hcmd_cq_wr1_data1),
.wr1_rdy_n (hcmd_cq_wr1_rdy_n)
);
pcie_hcmd_cq_req # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_cq_req_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.hcmd_cq_rd_en (w_hcmd_cq_rd_en),
.hcmd_cq_rd_data (w_hcmd_cq_rd_data),
.hcmd_cq_empty_n (w_hcmd_cq_empty_n),
.hcmd_cid_rd_addr (hcmd_cid_rd_addr),
.hcmd_cid_rd_data (hcmd_cid_rd_data),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.sq_valid (sq_valid),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.admin_cq_size (admin_cq_size),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.admin_cq_bs_addr (admin_cq_bs_addr),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_sq_head_ptr (admin_sq_head_ptr),
.io_sq1_head_ptr (io_sq1_head_ptr),
.io_sq2_head_ptr (io_sq2_head_ptr),
.io_sq3_head_ptr (io_sq3_head_ptr),
.io_sq4_head_ptr (io_sq4_head_ptr),
.io_sq5_head_ptr (io_sq5_head_ptr),
.io_sq6_head_ptr (io_sq6_head_ptr),
.io_sq7_head_ptr (io_sq7_head_ptr),
.io_sq8_head_ptr (io_sq8_head_ptr),
.hcmd_slot_free_en (hcmd_slot_free_en),
.hcmd_slot_invalid_tag (hcmd_slot_invalid_tag),
.tx_cq_mwr_req (tx_cq_mwr_req),
.tx_cq_mwr_tag (tx_cq_mwr_tag),
.tx_cq_mwr_len (tx_cq_mwr_len),
.tx_cq_mwr_addr (tx_cq_mwr_addr),
.tx_cq_mwr_req_ack (tx_cq_mwr_req_ack),
.tx_cq_mwr_rd_en (tx_cq_mwr_rd_en),
.tx_cq_mwr_rd_data (tx_cq_mwr_rd_data),
.tx_cq_mwr_data_last (tx_cq_mwr_data_last)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_recv # (
parameter C_PCIE_DATA_WIDTH = 128
)
(
input pcie_user_clk,
input pcie_user_rst_n,
//pcie rx signal
input [C_PCIE_DATA_WIDTH-1:0] s_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_rx_tkeep,
input s_axis_rx_tlast,
input s_axis_rx_tvalid,
output s_axis_rx_tready,
input [21:0] s_axis_rx_tuser,
output pcie_mreq_err,
output pcie_cpld_err,
output pcie_cpld_len_err,
output mreq_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output [7:0] cpld_fifo_tag,
output [C_PCIE_DATA_WIDTH-1:0] cpld_fifo_wr_data,
output cpld_fifo_wr_en,
output cpld_fifo_tag_last
);
localparam S_RX_IDLE_SOF = 4'b0001;
localparam S_RX_DATA = 4'b0010;
localparam S_RX_STRADDLED = 4'b0100;
localparam S_RX_STRADDLED_HOLD = 4'b1000;
reg [3:0] cur_state;
reg [3:0] next_state;
wire [4:0] w_rx_is_sof;
wire [4:0] w_rx_is_eof;
reg [31:0] r_pcie_head0;
reg [31:0] r_pcie_head1;
reg [31:0] r_pcie_head2;
wire [2:0] w_mreq_head_fmt;
wire [4:0] w_mreq_head_type;
//wire [2:0] w_mreq_head_tc;
//wire w_mreq_head_attr1;
//wire w_mreq_head_th;
//wire w_mreq_head_td;
wire w_mreq_head_ep;
//wire [1:0] w_mreq_head_atqtr0;
//wire [1:0] w_mreq_head_at;
//wire [9:0] w_mreq_head_len;
//wire [7:0] w_mreq_head_re_bus_num;
//wire [4:0] w_mreq_head_req_dev_num;
//wire [2:0] w_mreq_head_req_func_num;
//wire [15:0] w_mreq_head_req_id;
//wire [7:0] w_mreq_head_tag;
wire [2:0] w_cpld_head_fmt;
wire [4:0] w_cpld_head_type;
//wire [2:0] w_cpld_head_tc;
//wire w_cpld_head_attr1;
//wire w_cpld_head_th;
//wire w_cpld_head_td;
wire w_cpld_head_ep;
//wire [1:0] w_cpld_head_attr0;
//wire [1:0] w_cpld_head_at;
wire [9:0] w_cpld_head_len;
//wire [7:0] w_cpld_head_cpl_bus_num;
//wire [4:0] w_cpld_head_cpl_dev_num;
//wire [2:0] w_cpld_head_cpl_func_num;
//wire [15:0] w_cpld_head_cpl_id;
wire [2:0] w_cpld_head_cs;
//wire w_cpld_head_bcm;
wire [11:0] w_cpld_head_bc;
//wire [7:0] w_cpld_head_req_bus_num;
//wire [4:0] w_cpld_head_req_dev_num;
//wire [2:0] w_cpld_head_req_func_num;
//wire [15:0] w_cpld_head_req_id;
wire [7:0] w_cpld_head_tag;
//wire [6:0] w_cpld_head_la;
wire w_pcie_mreq_type;
wire w_pcie_cpld_type;
reg r_pcie_mreq_type;
reg r_pcie_cpld_type;
reg r_pcie_mreq_err;
reg r_pcie_cpld_err;
reg r_pcie_cpld_len_err;
reg [7:0] r_cpld_tag;
reg [11:2] r_cpld_len;
reg [11:2] r_cpld_bc;
reg r_cpld_lhead;
reg r_mem_req_en;
reg r_cpld_data_en;
reg r_cpld_tag_last;
reg r_rx_straddled;
reg r_rx_straddled_hold;
reg r_rx_data_straddled;
reg [127:0] r_s_axis_rx_tdata;
reg [127:0] r_s_axis_rx_tdata_d1;
reg r_mreq_fifo_wr_en;
reg [127:0] r_mreq_fifo_wr_data;
reg r_cpld_fifo_tag_en;
reg r_cpld_fifo_wr_en;
reg [127:0] r_cpld_fifo_wr_data;
reg r_cpld_fifo_tag_last;
assign s_axis_rx_tready = ~r_rx_straddled_hold;
assign pcie_mreq_err = r_pcie_mreq_err;
assign pcie_cpld_err = r_pcie_cpld_err;
assign pcie_cpld_len_err = r_pcie_cpld_len_err;
assign mreq_fifo_wr_en = r_mreq_fifo_wr_en;
assign mreq_fifo_wr_data = r_mreq_fifo_wr_data;
assign cpld_fifo_tag = r_cpld_tag;
assign cpld_fifo_wr_en = r_cpld_fifo_wr_en;
assign cpld_fifo_wr_data[31:0] = {r_cpld_fifo_wr_data[7:0], r_cpld_fifo_wr_data[15:8], r_cpld_fifo_wr_data[23:16], r_cpld_fifo_wr_data[31:24]};
assign cpld_fifo_wr_data[63:32] = {r_cpld_fifo_wr_data[39:32], r_cpld_fifo_wr_data[47:40], r_cpld_fifo_wr_data[55:48], r_cpld_fifo_wr_data[63:56]};
assign cpld_fifo_wr_data[95:64] = {r_cpld_fifo_wr_data[71:64], r_cpld_fifo_wr_data[79:72], r_cpld_fifo_wr_data[87:80], r_cpld_fifo_wr_data[95:88]};
assign cpld_fifo_wr_data[127:96] = {r_cpld_fifo_wr_data[103:96], r_cpld_fifo_wr_data[111:104], r_cpld_fifo_wr_data[119:112], r_cpld_fifo_wr_data[127:120]};
assign cpld_fifo_tag_last = r_cpld_fifo_tag_last;
assign w_rx_is_sof = s_axis_rx_tuser[14:10];
assign w_rx_is_eof = s_axis_rx_tuser[21:17];
always @ (*)
begin
if(w_rx_is_sof[3] == 1) begin
r_pcie_head0 <= s_axis_rx_tdata[95:64];
r_pcie_head1 <= s_axis_rx_tdata[127:96];
end
else begin
r_pcie_head0 <= s_axis_rx_tdata[31:0];
r_pcie_head1 <= s_axis_rx_tdata[63:32];
end
if(r_rx_straddled == 1)
r_pcie_head2 <= s_axis_rx_tdata[31:0];
else
r_pcie_head2 <= s_axis_rx_tdata[95:64];
end
//pcie mrd or mwr, memory rd/wr request
assign w_mreq_head_fmt = r_pcie_head0[31:29];
assign w_mreq_head_type = r_pcie_head0[28:24];
//assign w_mreq_head_tc = r_pcie_head0[22:20];
//assign w_mreq_head_attr1 = r_pcie_head0[18];
//assign w_mreq_head_th = r_pcie_head0[16];
//assign w_mreq_head_td = r_pcie_head0[15];
assign w_mreq_head_ep = r_pcie_head0[14];
//assign w_mreq_head_attr0 = r_pcie_head0[13:12];
//assign w_mreq_head_at = r_pcie_head0[11:10];
//assign w_mreq_head_len = r_pcie_head0[9:0];
//assign w_mreq_head_req_bus_num = r_pcie_head1[31:24];
//assign w_mreq_head_req_dev_num = r_pcie_head1[23:19];
//assign w_mreq_head_req_func_num = r_pcie_head1[18:16];
//assign w_mreq_head_req_id = {w_mreq_head_req_bus_num, w_mreq_head_req_dev_num, w_mreq_head_req_func_num};
//assign w_mreq_head_tag = r_pcie_head1[15:8];
//pcie cpl or cpld
assign w_cpld_head_fmt = r_pcie_head0[31:29];
assign w_cpld_head_type = r_pcie_head0[28:24];
//assign w_cpld_head_tc = r_pcie_head0[22:20];
//assign w_cpld_head_attr1 = r_pcie_head0[18];
//assign w_cpld_head_th = r_pcie_head0[16];
//assign w_cpld_head_td = r_pcie_head0[15];
assign w_cpld_head_ep = r_pcie_head0[14];
//assign w_cpld_head_attr0 = r_pcie_head0[13:12];
//assign w_cpld_head_at = r_pcie_head0[11:10];
assign w_cpld_head_len = r_pcie_head0[9:0];
//assign w_cpld_head_cpl_bus_num = r_pcie_head1[31:24];
//assign w_cpld_head_cpl_dev_num = r_pcie_head1[23:19];
//assign w_cpld_head_cpl_func_num = r_pcie_head1[18:16];
//assign w_cpld_head_cpl_id = {w_cpld_head_cpl_bus_num, w_cpld_head_cpl_dev_num, w_cpld_head_cpl_func_num};
assign w_cpld_head_cs = r_pcie_head1[15:13];
//assign w_cpld_head_bcm = r_pcie_head1[12];
assign w_cpld_head_bc = r_pcie_head1[11:0];
//assign w_cpld_head_req_bus_num = r_pcie_head2[31:24];
//assign w_cpld_head_req_dev_num = r_pcie_head2[23:19];
//assign w_cpld_head_req_func_num = r_pcie_head2[18:16];
//assign w_cpld_head_req_id = {w_cpld_head_req_bus_num, w_cpld_head_req_dev_num, w_cpld_head_req_func_num};
assign w_cpld_head_tag = r_pcie_head2[15:8];
//assign w_cpld_head_la = r_pcie_head2[6:0];
assign w_pcie_mreq_type = ({w_mreq_head_fmt[2], w_mreq_head_type} == {1'b0, 5'b00000});
assign w_pcie_cpld_type = ({w_cpld_head_fmt, w_cpld_head_type} == {3'b010, 5'b01010});
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RX_IDLE_SOF;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RX_IDLE_SOF: begin
if(s_axis_rx_tvalid == 1 && w_rx_is_sof[4] == 1 && w_rx_is_eof[4] == 0 ) begin
if(w_rx_is_sof[3] == 1)
next_state <= S_RX_STRADDLED;
else
next_state <= S_RX_DATA;
end
else
next_state <= S_RX_IDLE_SOF;
end
S_RX_DATA: begin
if(s_axis_rx_tvalid == 1 && w_rx_is_eof[4] == 1) begin
if(w_rx_is_sof[4] == 1)
next_state <= S_RX_STRADDLED;
else
next_state <= S_RX_IDLE_SOF;
end
else
next_state <= S_RX_DATA;
end
S_RX_STRADDLED: begin
if(s_axis_rx_tvalid == 1 && w_rx_is_eof[4] == 1) begin
if(w_rx_is_sof[4] == 1)
next_state <= S_RX_STRADDLED;
else if(w_rx_is_eof[3] == 1)
next_state <= S_RX_STRADDLED_HOLD;
else
next_state <= S_RX_IDLE_SOF;
end
else
next_state <= S_RX_STRADDLED;
end
S_RX_STRADDLED_HOLD: begin
next_state <= S_RX_IDLE_SOF;
end
default: begin
next_state <= S_RX_IDLE_SOF;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
if(s_axis_rx_tvalid == 1 && w_rx_is_sof[4] == 1) begin
r_pcie_mreq_type <= w_pcie_mreq_type & ~w_mreq_head_ep;
r_pcie_cpld_type <= w_pcie_cpld_type & ~w_cpld_head_ep & (w_cpld_head_cs == 0);
r_cpld_len <= w_cpld_head_len;
r_cpld_bc[11:2] <= w_cpld_head_bc[11:2];
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_mreq_err <= 0;
r_pcie_cpld_err <= 0;
r_pcie_cpld_len_err <= 0;
end
else begin
if(r_pcie_cpld_type == 1 && r_cpld_len < 2) begin
r_pcie_cpld_len_err <= 1;
end
if(s_axis_rx_tvalid == 1 && w_rx_is_sof[4] == 1) begin
r_pcie_mreq_err <= w_pcie_mreq_type & w_mreq_head_ep;
r_pcie_cpld_err <= w_pcie_cpld_type & (w_cpld_head_ep | (w_cpld_head_cs != 0));
end
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_RX_IDLE_SOF: begin
r_cpld_tag <= w_cpld_head_tag;
r_cpld_lhead <= 0;
end
S_RX_DATA: begin
end
S_RX_STRADDLED: begin
if(s_axis_rx_tvalid == 1)
r_cpld_lhead <= ~w_rx_is_sof[4];
if(r_cpld_lhead == 0)
r_cpld_tag <= w_cpld_head_tag;
end
S_RX_STRADDLED_HOLD: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RX_IDLE_SOF: begin
r_mem_req_en <= (s_axis_rx_tvalid & w_rx_is_sof[4] & ~w_rx_is_sof[3]) & w_pcie_mreq_type;
r_cpld_data_en <= 0;
r_cpld_tag_last <= 0;
r_rx_straddled <= 0;
r_rx_straddled_hold <= 0;
end
S_RX_DATA: begin
r_mem_req_en <= s_axis_rx_tvalid & r_pcie_mreq_type;
r_cpld_data_en <= s_axis_rx_tvalid & r_pcie_cpld_type;
r_cpld_tag_last <= (r_cpld_len == r_cpld_bc[11:2]) & (s_axis_rx_tvalid & r_pcie_cpld_type & w_rx_is_eof[4]);
r_rx_straddled <= 0;
r_rx_straddled_hold <= 0;
end
S_RX_STRADDLED: begin
r_mem_req_en <= s_axis_rx_tvalid & r_pcie_mreq_type;
r_cpld_data_en <= s_axis_rx_tvalid & r_pcie_cpld_type & r_cpld_lhead;
r_cpld_tag_last <= (r_cpld_len == r_cpld_bc[11:2]) & (s_axis_rx_tvalid & r_pcie_cpld_type & w_rx_is_eof[4] & ~w_rx_is_eof[3]);
r_rx_straddled <= 1;
r_rx_straddled_hold <= 0;
end
S_RX_STRADDLED_HOLD: begin
r_mem_req_en <= r_pcie_mreq_type;
r_cpld_data_en <= r_pcie_cpld_type;
r_cpld_tag_last <= (r_cpld_len == r_cpld_bc[11:2]) & r_pcie_cpld_type;
r_rx_straddled <= 1;
r_rx_straddled_hold <= 1;
end
default: begin
r_mem_req_en <= 0;
r_cpld_data_en <= 0;
r_cpld_tag_last <= 0;
r_rx_straddled <= 0;
r_rx_straddled_hold <= 0;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
r_mreq_fifo_wr_en <= r_mem_req_en;
r_cpld_fifo_wr_en <= r_cpld_data_en;
r_cpld_fifo_tag_last <= r_cpld_tag_last;
r_rx_data_straddled <= r_rx_straddled;
if(s_axis_rx_tvalid == 1 || r_rx_straddled_hold == 1) begin
r_s_axis_rx_tdata <= s_axis_rx_tdata;
r_s_axis_rx_tdata_d1 <= r_s_axis_rx_tdata;
end
end
always @ (*)
begin
if(r_rx_data_straddled == 1)
r_mreq_fifo_wr_data <= {r_s_axis_rx_tdata[63:0], r_s_axis_rx_tdata_d1[127:64]};
else
r_mreq_fifo_wr_data <= r_s_axis_rx_tdata;
if(r_rx_data_straddled == 1)
r_cpld_fifo_wr_data <= {r_s_axis_rx_tdata[31:0], r_s_axis_rx_tdata_d1[127:32]};
else
r_cpld_fifo_wr_data <= {r_s_axis_rx_tdata[95:0], r_s_axis_rx_tdata_d1[127:96]};
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_recv # (
parameter C_PCIE_DATA_WIDTH = 128
)
(
input pcie_user_clk,
input pcie_user_rst_n,
//pcie rx signal
input [C_PCIE_DATA_WIDTH-1:0] s_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_rx_tkeep,
input s_axis_rx_tlast,
input s_axis_rx_tvalid,
output s_axis_rx_tready,
input [21:0] s_axis_rx_tuser,
output pcie_mreq_err,
output pcie_cpld_err,
output pcie_cpld_len_err,
output mreq_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output [7:0] cpld_fifo_tag,
output [C_PCIE_DATA_WIDTH-1:0] cpld_fifo_wr_data,
output cpld_fifo_wr_en,
output cpld_fifo_tag_last
);
localparam S_RX_IDLE_SOF = 4'b0001;
localparam S_RX_DATA = 4'b0010;
localparam S_RX_STRADDLED = 4'b0100;
localparam S_RX_STRADDLED_HOLD = 4'b1000;
reg [3:0] cur_state;
reg [3:0] next_state;
wire [4:0] w_rx_is_sof;
wire [4:0] w_rx_is_eof;
reg [31:0] r_pcie_head0;
reg [31:0] r_pcie_head1;
reg [31:0] r_pcie_head2;
wire [2:0] w_mreq_head_fmt;
wire [4:0] w_mreq_head_type;
//wire [2:0] w_mreq_head_tc;
//wire w_mreq_head_attr1;
//wire w_mreq_head_th;
//wire w_mreq_head_td;
wire w_mreq_head_ep;
//wire [1:0] w_mreq_head_atqtr0;
//wire [1:0] w_mreq_head_at;
//wire [9:0] w_mreq_head_len;
//wire [7:0] w_mreq_head_re_bus_num;
//wire [4:0] w_mreq_head_req_dev_num;
//wire [2:0] w_mreq_head_req_func_num;
//wire [15:0] w_mreq_head_req_id;
//wire [7:0] w_mreq_head_tag;
wire [2:0] w_cpld_head_fmt;
wire [4:0] w_cpld_head_type;
//wire [2:0] w_cpld_head_tc;
//wire w_cpld_head_attr1;
//wire w_cpld_head_th;
//wire w_cpld_head_td;
wire w_cpld_head_ep;
//wire [1:0] w_cpld_head_attr0;
//wire [1:0] w_cpld_head_at;
wire [9:0] w_cpld_head_len;
//wire [7:0] w_cpld_head_cpl_bus_num;
//wire [4:0] w_cpld_head_cpl_dev_num;
//wire [2:0] w_cpld_head_cpl_func_num;
//wire [15:0] w_cpld_head_cpl_id;
wire [2:0] w_cpld_head_cs;
//wire w_cpld_head_bcm;
wire [11:0] w_cpld_head_bc;
//wire [7:0] w_cpld_head_req_bus_num;
//wire [4:0] w_cpld_head_req_dev_num;
//wire [2:0] w_cpld_head_req_func_num;
//wire [15:0] w_cpld_head_req_id;
wire [7:0] w_cpld_head_tag;
//wire [6:0] w_cpld_head_la;
wire w_pcie_mreq_type;
wire w_pcie_cpld_type;
reg r_pcie_mreq_type;
reg r_pcie_cpld_type;
reg r_pcie_mreq_err;
reg r_pcie_cpld_err;
reg r_pcie_cpld_len_err;
reg [7:0] r_cpld_tag;
reg [11:2] r_cpld_len;
reg [11:2] r_cpld_bc;
reg r_cpld_lhead;
reg r_mem_req_en;
reg r_cpld_data_en;
reg r_cpld_tag_last;
reg r_rx_straddled;
reg r_rx_straddled_hold;
reg r_rx_data_straddled;
reg [127:0] r_s_axis_rx_tdata;
reg [127:0] r_s_axis_rx_tdata_d1;
reg r_mreq_fifo_wr_en;
reg [127:0] r_mreq_fifo_wr_data;
reg r_cpld_fifo_tag_en;
reg r_cpld_fifo_wr_en;
reg [127:0] r_cpld_fifo_wr_data;
reg r_cpld_fifo_tag_last;
assign s_axis_rx_tready = ~r_rx_straddled_hold;
assign pcie_mreq_err = r_pcie_mreq_err;
assign pcie_cpld_err = r_pcie_cpld_err;
assign pcie_cpld_len_err = r_pcie_cpld_len_err;
assign mreq_fifo_wr_en = r_mreq_fifo_wr_en;
assign mreq_fifo_wr_data = r_mreq_fifo_wr_data;
assign cpld_fifo_tag = r_cpld_tag;
assign cpld_fifo_wr_en = r_cpld_fifo_wr_en;
assign cpld_fifo_wr_data[31:0] = {r_cpld_fifo_wr_data[7:0], r_cpld_fifo_wr_data[15:8], r_cpld_fifo_wr_data[23:16], r_cpld_fifo_wr_data[31:24]};
assign cpld_fifo_wr_data[63:32] = {r_cpld_fifo_wr_data[39:32], r_cpld_fifo_wr_data[47:40], r_cpld_fifo_wr_data[55:48], r_cpld_fifo_wr_data[63:56]};
assign cpld_fifo_wr_data[95:64] = {r_cpld_fifo_wr_data[71:64], r_cpld_fifo_wr_data[79:72], r_cpld_fifo_wr_data[87:80], r_cpld_fifo_wr_data[95:88]};
assign cpld_fifo_wr_data[127:96] = {r_cpld_fifo_wr_data[103:96], r_cpld_fifo_wr_data[111:104], r_cpld_fifo_wr_data[119:112], r_cpld_fifo_wr_data[127:120]};
assign cpld_fifo_tag_last = r_cpld_fifo_tag_last;
assign w_rx_is_sof = s_axis_rx_tuser[14:10];
assign w_rx_is_eof = s_axis_rx_tuser[21:17];
always @ (*)
begin
if(w_rx_is_sof[3] == 1) begin
r_pcie_head0 <= s_axis_rx_tdata[95:64];
r_pcie_head1 <= s_axis_rx_tdata[127:96];
end
else begin
r_pcie_head0 <= s_axis_rx_tdata[31:0];
r_pcie_head1 <= s_axis_rx_tdata[63:32];
end
if(r_rx_straddled == 1)
r_pcie_head2 <= s_axis_rx_tdata[31:0];
else
r_pcie_head2 <= s_axis_rx_tdata[95:64];
end
//pcie mrd or mwr, memory rd/wr request
assign w_mreq_head_fmt = r_pcie_head0[31:29];
assign w_mreq_head_type = r_pcie_head0[28:24];
//assign w_mreq_head_tc = r_pcie_head0[22:20];
//assign w_mreq_head_attr1 = r_pcie_head0[18];
//assign w_mreq_head_th = r_pcie_head0[16];
//assign w_mreq_head_td = r_pcie_head0[15];
assign w_mreq_head_ep = r_pcie_head0[14];
//assign w_mreq_head_attr0 = r_pcie_head0[13:12];
//assign w_mreq_head_at = r_pcie_head0[11:10];
//assign w_mreq_head_len = r_pcie_head0[9:0];
//assign w_mreq_head_req_bus_num = r_pcie_head1[31:24];
//assign w_mreq_head_req_dev_num = r_pcie_head1[23:19];
//assign w_mreq_head_req_func_num = r_pcie_head1[18:16];
//assign w_mreq_head_req_id = {w_mreq_head_req_bus_num, w_mreq_head_req_dev_num, w_mreq_head_req_func_num};
//assign w_mreq_head_tag = r_pcie_head1[15:8];
//pcie cpl or cpld
assign w_cpld_head_fmt = r_pcie_head0[31:29];
assign w_cpld_head_type = r_pcie_head0[28:24];
//assign w_cpld_head_tc = r_pcie_head0[22:20];
//assign w_cpld_head_attr1 = r_pcie_head0[18];
//assign w_cpld_head_th = r_pcie_head0[16];
//assign w_cpld_head_td = r_pcie_head0[15];
assign w_cpld_head_ep = r_pcie_head0[14];
//assign w_cpld_head_attr0 = r_pcie_head0[13:12];
//assign w_cpld_head_at = r_pcie_head0[11:10];
assign w_cpld_head_len = r_pcie_head0[9:0];
//assign w_cpld_head_cpl_bus_num = r_pcie_head1[31:24];
//assign w_cpld_head_cpl_dev_num = r_pcie_head1[23:19];
//assign w_cpld_head_cpl_func_num = r_pcie_head1[18:16];
//assign w_cpld_head_cpl_id = {w_cpld_head_cpl_bus_num, w_cpld_head_cpl_dev_num, w_cpld_head_cpl_func_num};
assign w_cpld_head_cs = r_pcie_head1[15:13];
//assign w_cpld_head_bcm = r_pcie_head1[12];
assign w_cpld_head_bc = r_pcie_head1[11:0];
//assign w_cpld_head_req_bus_num = r_pcie_head2[31:24];
//assign w_cpld_head_req_dev_num = r_pcie_head2[23:19];
//assign w_cpld_head_req_func_num = r_pcie_head2[18:16];
//assign w_cpld_head_req_id = {w_cpld_head_req_bus_num, w_cpld_head_req_dev_num, w_cpld_head_req_func_num};
assign w_cpld_head_tag = r_pcie_head2[15:8];
//assign w_cpld_head_la = r_pcie_head2[6:0];
assign w_pcie_mreq_type = ({w_mreq_head_fmt[2], w_mreq_head_type} == {1'b0, 5'b00000});
assign w_pcie_cpld_type = ({w_cpld_head_fmt, w_cpld_head_type} == {3'b010, 5'b01010});
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RX_IDLE_SOF;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RX_IDLE_SOF: begin
if(s_axis_rx_tvalid == 1 && w_rx_is_sof[4] == 1 && w_rx_is_eof[4] == 0 ) begin
if(w_rx_is_sof[3] == 1)
next_state <= S_RX_STRADDLED;
else
next_state <= S_RX_DATA;
end
else
next_state <= S_RX_IDLE_SOF;
end
S_RX_DATA: begin
if(s_axis_rx_tvalid == 1 && w_rx_is_eof[4] == 1) begin
if(w_rx_is_sof[4] == 1)
next_state <= S_RX_STRADDLED;
else
next_state <= S_RX_IDLE_SOF;
end
else
next_state <= S_RX_DATA;
end
S_RX_STRADDLED: begin
if(s_axis_rx_tvalid == 1 && w_rx_is_eof[4] == 1) begin
if(w_rx_is_sof[4] == 1)
next_state <= S_RX_STRADDLED;
else if(w_rx_is_eof[3] == 1)
next_state <= S_RX_STRADDLED_HOLD;
else
next_state <= S_RX_IDLE_SOF;
end
else
next_state <= S_RX_STRADDLED;
end
S_RX_STRADDLED_HOLD: begin
next_state <= S_RX_IDLE_SOF;
end
default: begin
next_state <= S_RX_IDLE_SOF;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
if(s_axis_rx_tvalid == 1 && w_rx_is_sof[4] == 1) begin
r_pcie_mreq_type <= w_pcie_mreq_type & ~w_mreq_head_ep;
r_pcie_cpld_type <= w_pcie_cpld_type & ~w_cpld_head_ep & (w_cpld_head_cs == 0);
r_cpld_len <= w_cpld_head_len;
r_cpld_bc[11:2] <= w_cpld_head_bc[11:2];
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_mreq_err <= 0;
r_pcie_cpld_err <= 0;
r_pcie_cpld_len_err <= 0;
end
else begin
if(r_pcie_cpld_type == 1 && r_cpld_len < 2) begin
r_pcie_cpld_len_err <= 1;
end
if(s_axis_rx_tvalid == 1 && w_rx_is_sof[4] == 1) begin
r_pcie_mreq_err <= w_pcie_mreq_type & w_mreq_head_ep;
r_pcie_cpld_err <= w_pcie_cpld_type & (w_cpld_head_ep | (w_cpld_head_cs != 0));
end
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_RX_IDLE_SOF: begin
r_cpld_tag <= w_cpld_head_tag;
r_cpld_lhead <= 0;
end
S_RX_DATA: begin
end
S_RX_STRADDLED: begin
if(s_axis_rx_tvalid == 1)
r_cpld_lhead <= ~w_rx_is_sof[4];
if(r_cpld_lhead == 0)
r_cpld_tag <= w_cpld_head_tag;
end
S_RX_STRADDLED_HOLD: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RX_IDLE_SOF: begin
r_mem_req_en <= (s_axis_rx_tvalid & w_rx_is_sof[4] & ~w_rx_is_sof[3]) & w_pcie_mreq_type;
r_cpld_data_en <= 0;
r_cpld_tag_last <= 0;
r_rx_straddled <= 0;
r_rx_straddled_hold <= 0;
end
S_RX_DATA: begin
r_mem_req_en <= s_axis_rx_tvalid & r_pcie_mreq_type;
r_cpld_data_en <= s_axis_rx_tvalid & r_pcie_cpld_type;
r_cpld_tag_last <= (r_cpld_len == r_cpld_bc[11:2]) & (s_axis_rx_tvalid & r_pcie_cpld_type & w_rx_is_eof[4]);
r_rx_straddled <= 0;
r_rx_straddled_hold <= 0;
end
S_RX_STRADDLED: begin
r_mem_req_en <= s_axis_rx_tvalid & r_pcie_mreq_type;
r_cpld_data_en <= s_axis_rx_tvalid & r_pcie_cpld_type & r_cpld_lhead;
r_cpld_tag_last <= (r_cpld_len == r_cpld_bc[11:2]) & (s_axis_rx_tvalid & r_pcie_cpld_type & w_rx_is_eof[4] & ~w_rx_is_eof[3]);
r_rx_straddled <= 1;
r_rx_straddled_hold <= 0;
end
S_RX_STRADDLED_HOLD: begin
r_mem_req_en <= r_pcie_mreq_type;
r_cpld_data_en <= r_pcie_cpld_type;
r_cpld_tag_last <= (r_cpld_len == r_cpld_bc[11:2]) & r_pcie_cpld_type;
r_rx_straddled <= 1;
r_rx_straddled_hold <= 1;
end
default: begin
r_mem_req_en <= 0;
r_cpld_data_en <= 0;
r_cpld_tag_last <= 0;
r_rx_straddled <= 0;
r_rx_straddled_hold <= 0;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
r_mreq_fifo_wr_en <= r_mem_req_en;
r_cpld_fifo_wr_en <= r_cpld_data_en;
r_cpld_fifo_tag_last <= r_cpld_tag_last;
r_rx_data_straddled <= r_rx_straddled;
if(s_axis_rx_tvalid == 1 || r_rx_straddled_hold == 1) begin
r_s_axis_rx_tdata <= s_axis_rx_tdata;
r_s_axis_rx_tdata_d1 <= r_s_axis_rx_tdata;
end
end
always @ (*)
begin
if(r_rx_data_straddled == 1)
r_mreq_fifo_wr_data <= {r_s_axis_rx_tdata[63:0], r_s_axis_rx_tdata_d1[127:64]};
else
r_mreq_fifo_wr_data <= r_s_axis_rx_tdata;
if(r_rx_data_straddled == 1)
r_cpld_fifo_wr_data <= {r_s_axis_rx_tdata[31:0], r_s_axis_rx_tdata_d1[127:32]};
else
r_cpld_fifo_wr_data <= {r_s_axis_rx_tdata[95:0], r_s_axis_rx_tdata_d1[127:96]};
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module reg_cpu_pcie_sync # (
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input cpu_bus_clk,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
output pcie_link_up_sync,
output [5:0] pl_ltssm_state_sync,
output [15:0] cfg_command_sync,
output [2:0] cfg_interrupt_mmenable_sync,
output cfg_interrupt_msienable_sync,
output cfg_interrupt_msixenable_sync,
output pcie_mreq_err_sync,
output pcie_cpld_err_sync,
output pcie_cpld_len_err_sync,
output nvme_cc_en_sync,
output [1:0] nvme_cc_shn_sync,
input pcie_user_clk,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst_sync,
output nvme_csts_rdy_sync,
output [8:0] sq_rst_n_sync,
output [8:0] sq_valid_sync,
output [7:0] io_sq1_size_sync,
output [7:0] io_sq2_size_sync,
output [7:0] io_sq3_size_sync,
output [7:0] io_sq4_size_sync,
output [7:0] io_sq5_size_sync,
output [7:0] io_sq6_size_sync,
output [7:0] io_sq7_size_sync,
output [7:0] io_sq8_size_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr_sync,
output [3:0] io_sq1_cq_vec_sync,
output [3:0] io_sq2_cq_vec_sync,
output [3:0] io_sq3_cq_vec_sync,
output [3:0] io_sq4_cq_vec_sync,
output [3:0] io_sq5_cq_vec_sync,
output [3:0] io_sq6_cq_vec_sync,
output [3:0] io_sq7_cq_vec_sync,
output [3:0] io_sq8_cq_vec_sync,
output [8:0] cq_rst_n_sync,
output [8:0] cq_valid_sync,
output [7:0] io_cq1_size_sync,
output [7:0] io_cq2_size_sync,
output [7:0] io_cq3_size_sync,
output [7:0] io_cq4_size_sync,
output [7:0] io_cq5_size_sync,
output [7:0] io_cq6_size_sync,
output [7:0] io_cq7_size_sync,
output [7:0] io_cq8_size_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr_sync,
output [8:0] io_cq_irq_en_sync,
output [2:0] io_cq1_iv_sync,
output [2:0] io_cq2_iv_sync,
output [2:0] io_cq3_iv_sync,
output [2:0] io_cq4_iv_sync,
output [2:0] io_cq5_iv_sync,
output [2:0] io_cq6_iv_sync,
output [2:0] io_cq7_iv_sync,
output [2:0] io_cq8_iv_sync
);
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_link_up;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_link_up_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [5:0] r_pl_ltssm_state;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [5:0] r_pl_ltssm_state_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] r_cfg_command;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] r_cfg_command_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_cfg_interrupt_mmenable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_cfg_interrupt_mmenable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msienable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msienable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msixenable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msixenable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_mreq_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_mreq_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_len_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_len_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_cc_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_cc_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_cc_shn;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_cc_shn_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_csts_shst;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_csts_shst_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_csts_rdy;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_csts_rdy_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d3;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq1_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq2_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq3_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq4_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq5_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq6_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq7_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq8_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq1_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq2_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq3_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq4_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq5_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq6_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq7_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq8_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq1_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq2_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq3_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq4_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq5_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq6_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq7_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq8_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d3;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq1_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq2_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq3_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq4_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq5_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq6_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq7_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq8_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq1_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq2_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq3_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq4_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq5_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq6_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq7_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq8_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_io_cq_irq_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_io_cq_irq_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq1_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq2_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq3_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq4_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq5_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq6_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq7_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq8_iv;
assign pcie_link_up_sync = r_pcie_link_up_d1;
assign pl_ltssm_state_sync = r_pl_ltssm_state_d1;
assign cfg_command_sync = r_cfg_command_d1;
assign cfg_interrupt_mmenable_sync = r_cfg_interrupt_mmenable_d1;
assign cfg_interrupt_msienable_sync = r_cfg_interrupt_msienable_d1;
assign cfg_interrupt_msixenable_sync = r_cfg_interrupt_msixenable_d1;
assign pcie_mreq_err_sync = r_pcie_mreq_err_d1;
assign pcie_cpld_err_sync = r_pcie_cpld_err_d1;
assign pcie_cpld_len_err_sync = r_pcie_cpld_len_err_d1;
assign nvme_cc_en_sync = r_nvme_cc_en_d1;
assign nvme_cc_shn_sync = r_nvme_cc_shn_d1;
assign nvme_csts_shst_sync = r_nvme_csts_shst_d1;
assign nvme_csts_rdy_sync = r_nvme_csts_rdy_d1;
assign sq_rst_n_sync = r_sq_valid_d3;
assign sq_valid_sync = r_sq_valid_d1;
assign io_sq1_size_sync = r_io_sq1_size;
assign io_sq2_size_sync = r_io_sq2_size;
assign io_sq3_size_sync = r_io_sq3_size;
assign io_sq4_size_sync = r_io_sq4_size;
assign io_sq5_size_sync = r_io_sq5_size;
assign io_sq6_size_sync = r_io_sq6_size;
assign io_sq7_size_sync = r_io_sq7_size;
assign io_sq8_size_sync = r_io_sq8_size;
assign io_sq1_bs_addr_sync = r_io_sq1_bs_addr;
assign io_sq2_bs_addr_sync = r_io_sq2_bs_addr;
assign io_sq3_bs_addr_sync = r_io_sq3_bs_addr;
assign io_sq4_bs_addr_sync = r_io_sq4_bs_addr;
assign io_sq5_bs_addr_sync = r_io_sq5_bs_addr;
assign io_sq6_bs_addr_sync = r_io_sq6_bs_addr;
assign io_sq7_bs_addr_sync = r_io_sq7_bs_addr;
assign io_sq8_bs_addr_sync = r_io_sq8_bs_addr;
assign io_sq1_cq_vec_sync = r_io_sq1_cq_vec;
assign io_sq2_cq_vec_sync = r_io_sq2_cq_vec;
assign io_sq3_cq_vec_sync = r_io_sq3_cq_vec;
assign io_sq4_cq_vec_sync = r_io_sq4_cq_vec;
assign io_sq5_cq_vec_sync = r_io_sq5_cq_vec;
assign io_sq6_cq_vec_sync = r_io_sq6_cq_vec;
assign io_sq7_cq_vec_sync = r_io_sq7_cq_vec;
assign io_sq8_cq_vec_sync = r_io_sq8_cq_vec;
assign cq_rst_n_sync = r_cq_valid_d3;
assign cq_valid_sync = r_cq_valid_d1;
assign io_cq1_size_sync = r_io_cq1_size;
assign io_cq2_size_sync = r_io_cq2_size;
assign io_cq3_size_sync = r_io_cq3_size;
assign io_cq4_size_sync = r_io_cq4_size;
assign io_cq5_size_sync = r_io_cq5_size;
assign io_cq6_size_sync = r_io_cq6_size;
assign io_cq7_size_sync = r_io_cq7_size;
assign io_cq8_size_sync = r_io_cq8_size;
assign io_cq1_bs_addr_sync = r_io_cq1_bs_addr;
assign io_cq2_bs_addr_sync = r_io_cq2_bs_addr;
assign io_cq3_bs_addr_sync = r_io_cq3_bs_addr;
assign io_cq4_bs_addr_sync = r_io_cq4_bs_addr;
assign io_cq5_bs_addr_sync = r_io_cq5_bs_addr;
assign io_cq6_bs_addr_sync = r_io_cq6_bs_addr;
assign io_cq7_bs_addr_sync = r_io_cq7_bs_addr;
assign io_cq8_bs_addr_sync = r_io_cq8_bs_addr;
assign io_cq_irq_en_sync = r_io_cq_irq_en_d1;
assign io_cq1_iv_sync = r_io_cq1_iv;
assign io_cq2_iv_sync = r_io_cq2_iv;
assign io_cq3_iv_sync = r_io_cq3_iv;
assign io_cq4_iv_sync = r_io_cq4_iv;
assign io_cq5_iv_sync = r_io_cq5_iv;
assign io_cq6_iv_sync = r_io_cq6_iv;
assign io_cq7_iv_sync = r_io_cq7_iv;
assign io_cq8_iv_sync = r_io_cq8_iv;
always @ (posedge cpu_bus_clk)
begin
r_pcie_link_up <= pcie_link_up;
r_pcie_link_up_d1 <= r_pcie_link_up;
r_pl_ltssm_state <= pl_ltssm_state;
r_pl_ltssm_state_d1 <= r_pl_ltssm_state;
r_cfg_command <= cfg_command;
r_cfg_command_d1 <= r_cfg_command;
r_cfg_interrupt_mmenable <= cfg_interrupt_mmenable;
r_cfg_interrupt_mmenable_d1 <= r_cfg_interrupt_mmenable;
r_cfg_interrupt_msienable <= cfg_interrupt_msienable;
r_cfg_interrupt_msienable_d1 <= r_cfg_interrupt_msienable;
r_cfg_interrupt_msixenable <= cfg_interrupt_msixenable;
r_cfg_interrupt_msixenable_d1 <= r_cfg_interrupt_msixenable;
r_pcie_mreq_err <= pcie_mreq_err;
r_pcie_mreq_err_d1 <= r_pcie_mreq_err;
r_pcie_cpld_err <= pcie_cpld_err;
r_pcie_cpld_err_d1 <= r_pcie_cpld_err;
r_pcie_cpld_len_err <= pcie_cpld_len_err;
r_pcie_cpld_len_err_d1 <= r_pcie_cpld_len_err;
r_nvme_cc_en <= nvme_cc_en;
r_nvme_cc_en_d1 <= r_nvme_cc_en;
r_nvme_cc_shn <= nvme_cc_shn;
r_nvme_cc_shn_d1 <= r_nvme_cc_shn;
end
always @ (posedge pcie_user_clk)
begin
r_nvme_csts_shst <= nvme_csts_shst;
r_nvme_csts_shst_d1 <= r_nvme_csts_shst;
r_nvme_csts_rdy <= nvme_csts_rdy;
r_nvme_csts_rdy_d1 <= r_nvme_csts_rdy;
r_sq_valid <= sq_valid;
r_sq_valid_d1 <= r_sq_valid;
r_sq_valid_d2 <= r_sq_valid_d1;
r_sq_valid_d3 <= r_sq_valid_d2;
r_io_sq1_size <= io_sq1_size;
r_io_sq2_size <= io_sq2_size;
r_io_sq3_size <= io_sq3_size;
r_io_sq4_size <= io_sq4_size;
r_io_sq5_size <= io_sq5_size;
r_io_sq6_size <= io_sq6_size;
r_io_sq7_size <= io_sq7_size;
r_io_sq8_size <= io_sq8_size;
r_io_sq1_bs_addr <= io_sq1_bs_addr;
r_io_sq2_bs_addr <= io_sq2_bs_addr;
r_io_sq3_bs_addr <= io_sq3_bs_addr;
r_io_sq4_bs_addr <= io_sq4_bs_addr;
r_io_sq5_bs_addr <= io_sq5_bs_addr;
r_io_sq6_bs_addr <= io_sq6_bs_addr;
r_io_sq7_bs_addr <= io_sq7_bs_addr;
r_io_sq8_bs_addr <= io_sq8_bs_addr;
r_io_sq1_cq_vec <= io_sq1_cq_vec;
r_io_sq2_cq_vec <= io_sq2_cq_vec;
r_io_sq3_cq_vec <= io_sq3_cq_vec;
r_io_sq4_cq_vec <= io_sq4_cq_vec;
r_io_sq5_cq_vec <= io_sq5_cq_vec;
r_io_sq6_cq_vec <= io_sq6_cq_vec;
r_io_sq7_cq_vec <= io_sq7_cq_vec;
r_io_sq8_cq_vec <= io_sq8_cq_vec;
r_cq_valid <= cq_valid;
r_cq_valid_d1 <= r_cq_valid;
r_cq_valid_d2 <= r_cq_valid_d1;
r_cq_valid_d3 <= r_cq_valid_d2;
r_io_cq1_size <= io_cq1_size;
r_io_cq2_size <= io_cq2_size;
r_io_cq3_size <= io_cq3_size;
r_io_cq4_size <= io_cq4_size;
r_io_cq5_size <= io_cq5_size;
r_io_cq6_size <= io_cq6_size;
r_io_cq7_size <= io_cq7_size;
r_io_cq8_size <= io_cq8_size;
r_io_cq1_bs_addr <= io_cq1_bs_addr;
r_io_cq2_bs_addr <= io_cq2_bs_addr;
r_io_cq3_bs_addr <= io_cq3_bs_addr;
r_io_cq4_bs_addr <= io_cq4_bs_addr;
r_io_cq5_bs_addr <= io_cq5_bs_addr;
r_io_cq6_bs_addr <= io_cq6_bs_addr;
r_io_cq7_bs_addr <= io_cq7_bs_addr;
r_io_cq8_bs_addr <= io_cq8_bs_addr;
r_io_cq_irq_en <= io_cq_irq_en;
r_io_cq_irq_en_d1 <= r_io_cq_irq_en;
r_io_cq1_iv <= io_cq1_iv;
r_io_cq2_iv <= io_cq2_iv;
r_io_cq3_iv <= io_cq3_iv;
r_io_cq4_iv <= io_cq4_iv;
r_io_cq5_iv <= io_cq5_iv;
r_io_cq6_iv <= io_cq6_iv;
r_io_cq7_iv <= io_cq7_iv;
r_io_cq8_iv <= io_cq8_iv;
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module reg_cpu_pcie_sync # (
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input cpu_bus_clk,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
output pcie_link_up_sync,
output [5:0] pl_ltssm_state_sync,
output [15:0] cfg_command_sync,
output [2:0] cfg_interrupt_mmenable_sync,
output cfg_interrupt_msienable_sync,
output cfg_interrupt_msixenable_sync,
output pcie_mreq_err_sync,
output pcie_cpld_err_sync,
output pcie_cpld_len_err_sync,
output nvme_cc_en_sync,
output [1:0] nvme_cc_shn_sync,
input pcie_user_clk,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst_sync,
output nvme_csts_rdy_sync,
output [8:0] sq_rst_n_sync,
output [8:0] sq_valid_sync,
output [7:0] io_sq1_size_sync,
output [7:0] io_sq2_size_sync,
output [7:0] io_sq3_size_sync,
output [7:0] io_sq4_size_sync,
output [7:0] io_sq5_size_sync,
output [7:0] io_sq6_size_sync,
output [7:0] io_sq7_size_sync,
output [7:0] io_sq8_size_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr_sync,
output [3:0] io_sq1_cq_vec_sync,
output [3:0] io_sq2_cq_vec_sync,
output [3:0] io_sq3_cq_vec_sync,
output [3:0] io_sq4_cq_vec_sync,
output [3:0] io_sq5_cq_vec_sync,
output [3:0] io_sq6_cq_vec_sync,
output [3:0] io_sq7_cq_vec_sync,
output [3:0] io_sq8_cq_vec_sync,
output [8:0] cq_rst_n_sync,
output [8:0] cq_valid_sync,
output [7:0] io_cq1_size_sync,
output [7:0] io_cq2_size_sync,
output [7:0] io_cq3_size_sync,
output [7:0] io_cq4_size_sync,
output [7:0] io_cq5_size_sync,
output [7:0] io_cq6_size_sync,
output [7:0] io_cq7_size_sync,
output [7:0] io_cq8_size_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr_sync,
output [8:0] io_cq_irq_en_sync,
output [2:0] io_cq1_iv_sync,
output [2:0] io_cq2_iv_sync,
output [2:0] io_cq3_iv_sync,
output [2:0] io_cq4_iv_sync,
output [2:0] io_cq5_iv_sync,
output [2:0] io_cq6_iv_sync,
output [2:0] io_cq7_iv_sync,
output [2:0] io_cq8_iv_sync
);
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_link_up;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_link_up_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [5:0] r_pl_ltssm_state;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [5:0] r_pl_ltssm_state_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] r_cfg_command;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] r_cfg_command_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_cfg_interrupt_mmenable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_cfg_interrupt_mmenable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msienable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msienable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msixenable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msixenable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_mreq_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_mreq_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_len_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_len_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_cc_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_cc_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_cc_shn;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_cc_shn_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_csts_shst;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_csts_shst_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_csts_rdy;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_csts_rdy_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d3;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq1_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq2_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq3_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq4_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq5_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq6_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq7_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq8_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq1_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq2_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq3_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq4_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq5_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq6_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq7_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq8_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq1_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq2_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq3_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq4_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq5_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq6_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq7_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq8_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d3;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq1_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq2_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq3_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq4_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq5_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq6_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq7_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq8_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq1_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq2_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq3_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq4_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq5_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq6_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq7_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq8_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_io_cq_irq_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_io_cq_irq_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq1_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq2_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq3_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq4_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq5_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq6_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq7_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq8_iv;
assign pcie_link_up_sync = r_pcie_link_up_d1;
assign pl_ltssm_state_sync = r_pl_ltssm_state_d1;
assign cfg_command_sync = r_cfg_command_d1;
assign cfg_interrupt_mmenable_sync = r_cfg_interrupt_mmenable_d1;
assign cfg_interrupt_msienable_sync = r_cfg_interrupt_msienable_d1;
assign cfg_interrupt_msixenable_sync = r_cfg_interrupt_msixenable_d1;
assign pcie_mreq_err_sync = r_pcie_mreq_err_d1;
assign pcie_cpld_err_sync = r_pcie_cpld_err_d1;
assign pcie_cpld_len_err_sync = r_pcie_cpld_len_err_d1;
assign nvme_cc_en_sync = r_nvme_cc_en_d1;
assign nvme_cc_shn_sync = r_nvme_cc_shn_d1;
assign nvme_csts_shst_sync = r_nvme_csts_shst_d1;
assign nvme_csts_rdy_sync = r_nvme_csts_rdy_d1;
assign sq_rst_n_sync = r_sq_valid_d3;
assign sq_valid_sync = r_sq_valid_d1;
assign io_sq1_size_sync = r_io_sq1_size;
assign io_sq2_size_sync = r_io_sq2_size;
assign io_sq3_size_sync = r_io_sq3_size;
assign io_sq4_size_sync = r_io_sq4_size;
assign io_sq5_size_sync = r_io_sq5_size;
assign io_sq6_size_sync = r_io_sq6_size;
assign io_sq7_size_sync = r_io_sq7_size;
assign io_sq8_size_sync = r_io_sq8_size;
assign io_sq1_bs_addr_sync = r_io_sq1_bs_addr;
assign io_sq2_bs_addr_sync = r_io_sq2_bs_addr;
assign io_sq3_bs_addr_sync = r_io_sq3_bs_addr;
assign io_sq4_bs_addr_sync = r_io_sq4_bs_addr;
assign io_sq5_bs_addr_sync = r_io_sq5_bs_addr;
assign io_sq6_bs_addr_sync = r_io_sq6_bs_addr;
assign io_sq7_bs_addr_sync = r_io_sq7_bs_addr;
assign io_sq8_bs_addr_sync = r_io_sq8_bs_addr;
assign io_sq1_cq_vec_sync = r_io_sq1_cq_vec;
assign io_sq2_cq_vec_sync = r_io_sq2_cq_vec;
assign io_sq3_cq_vec_sync = r_io_sq3_cq_vec;
assign io_sq4_cq_vec_sync = r_io_sq4_cq_vec;
assign io_sq5_cq_vec_sync = r_io_sq5_cq_vec;
assign io_sq6_cq_vec_sync = r_io_sq6_cq_vec;
assign io_sq7_cq_vec_sync = r_io_sq7_cq_vec;
assign io_sq8_cq_vec_sync = r_io_sq8_cq_vec;
assign cq_rst_n_sync = r_cq_valid_d3;
assign cq_valid_sync = r_cq_valid_d1;
assign io_cq1_size_sync = r_io_cq1_size;
assign io_cq2_size_sync = r_io_cq2_size;
assign io_cq3_size_sync = r_io_cq3_size;
assign io_cq4_size_sync = r_io_cq4_size;
assign io_cq5_size_sync = r_io_cq5_size;
assign io_cq6_size_sync = r_io_cq6_size;
assign io_cq7_size_sync = r_io_cq7_size;
assign io_cq8_size_sync = r_io_cq8_size;
assign io_cq1_bs_addr_sync = r_io_cq1_bs_addr;
assign io_cq2_bs_addr_sync = r_io_cq2_bs_addr;
assign io_cq3_bs_addr_sync = r_io_cq3_bs_addr;
assign io_cq4_bs_addr_sync = r_io_cq4_bs_addr;
assign io_cq5_bs_addr_sync = r_io_cq5_bs_addr;
assign io_cq6_bs_addr_sync = r_io_cq6_bs_addr;
assign io_cq7_bs_addr_sync = r_io_cq7_bs_addr;
assign io_cq8_bs_addr_sync = r_io_cq8_bs_addr;
assign io_cq_irq_en_sync = r_io_cq_irq_en_d1;
assign io_cq1_iv_sync = r_io_cq1_iv;
assign io_cq2_iv_sync = r_io_cq2_iv;
assign io_cq3_iv_sync = r_io_cq3_iv;
assign io_cq4_iv_sync = r_io_cq4_iv;
assign io_cq5_iv_sync = r_io_cq5_iv;
assign io_cq6_iv_sync = r_io_cq6_iv;
assign io_cq7_iv_sync = r_io_cq7_iv;
assign io_cq8_iv_sync = r_io_cq8_iv;
always @ (posedge cpu_bus_clk)
begin
r_pcie_link_up <= pcie_link_up;
r_pcie_link_up_d1 <= r_pcie_link_up;
r_pl_ltssm_state <= pl_ltssm_state;
r_pl_ltssm_state_d1 <= r_pl_ltssm_state;
r_cfg_command <= cfg_command;
r_cfg_command_d1 <= r_cfg_command;
r_cfg_interrupt_mmenable <= cfg_interrupt_mmenable;
r_cfg_interrupt_mmenable_d1 <= r_cfg_interrupt_mmenable;
r_cfg_interrupt_msienable <= cfg_interrupt_msienable;
r_cfg_interrupt_msienable_d1 <= r_cfg_interrupt_msienable;
r_cfg_interrupt_msixenable <= cfg_interrupt_msixenable;
r_cfg_interrupt_msixenable_d1 <= r_cfg_interrupt_msixenable;
r_pcie_mreq_err <= pcie_mreq_err;
r_pcie_mreq_err_d1 <= r_pcie_mreq_err;
r_pcie_cpld_err <= pcie_cpld_err;
r_pcie_cpld_err_d1 <= r_pcie_cpld_err;
r_pcie_cpld_len_err <= pcie_cpld_len_err;
r_pcie_cpld_len_err_d1 <= r_pcie_cpld_len_err;
r_nvme_cc_en <= nvme_cc_en;
r_nvme_cc_en_d1 <= r_nvme_cc_en;
r_nvme_cc_shn <= nvme_cc_shn;
r_nvme_cc_shn_d1 <= r_nvme_cc_shn;
end
always @ (posedge pcie_user_clk)
begin
r_nvme_csts_shst <= nvme_csts_shst;
r_nvme_csts_shst_d1 <= r_nvme_csts_shst;
r_nvme_csts_rdy <= nvme_csts_rdy;
r_nvme_csts_rdy_d1 <= r_nvme_csts_rdy;
r_sq_valid <= sq_valid;
r_sq_valid_d1 <= r_sq_valid;
r_sq_valid_d2 <= r_sq_valid_d1;
r_sq_valid_d3 <= r_sq_valid_d2;
r_io_sq1_size <= io_sq1_size;
r_io_sq2_size <= io_sq2_size;
r_io_sq3_size <= io_sq3_size;
r_io_sq4_size <= io_sq4_size;
r_io_sq5_size <= io_sq5_size;
r_io_sq6_size <= io_sq6_size;
r_io_sq7_size <= io_sq7_size;
r_io_sq8_size <= io_sq8_size;
r_io_sq1_bs_addr <= io_sq1_bs_addr;
r_io_sq2_bs_addr <= io_sq2_bs_addr;
r_io_sq3_bs_addr <= io_sq3_bs_addr;
r_io_sq4_bs_addr <= io_sq4_bs_addr;
r_io_sq5_bs_addr <= io_sq5_bs_addr;
r_io_sq6_bs_addr <= io_sq6_bs_addr;
r_io_sq7_bs_addr <= io_sq7_bs_addr;
r_io_sq8_bs_addr <= io_sq8_bs_addr;
r_io_sq1_cq_vec <= io_sq1_cq_vec;
r_io_sq2_cq_vec <= io_sq2_cq_vec;
r_io_sq3_cq_vec <= io_sq3_cq_vec;
r_io_sq4_cq_vec <= io_sq4_cq_vec;
r_io_sq5_cq_vec <= io_sq5_cq_vec;
r_io_sq6_cq_vec <= io_sq6_cq_vec;
r_io_sq7_cq_vec <= io_sq7_cq_vec;
r_io_sq8_cq_vec <= io_sq8_cq_vec;
r_cq_valid <= cq_valid;
r_cq_valid_d1 <= r_cq_valid;
r_cq_valid_d2 <= r_cq_valid_d1;
r_cq_valid_d3 <= r_cq_valid_d2;
r_io_cq1_size <= io_cq1_size;
r_io_cq2_size <= io_cq2_size;
r_io_cq3_size <= io_cq3_size;
r_io_cq4_size <= io_cq4_size;
r_io_cq5_size <= io_cq5_size;
r_io_cq6_size <= io_cq6_size;
r_io_cq7_size <= io_cq7_size;
r_io_cq8_size <= io_cq8_size;
r_io_cq1_bs_addr <= io_cq1_bs_addr;
r_io_cq2_bs_addr <= io_cq2_bs_addr;
r_io_cq3_bs_addr <= io_cq3_bs_addr;
r_io_cq4_bs_addr <= io_cq4_bs_addr;
r_io_cq5_bs_addr <= io_cq5_bs_addr;
r_io_cq6_bs_addr <= io_cq6_bs_addr;
r_io_cq7_bs_addr <= io_cq7_bs_addr;
r_io_cq8_bs_addr <= io_cq8_bs_addr;
r_io_cq_irq_en <= io_cq_irq_en;
r_io_cq_irq_en_d1 <= r_io_cq_irq_en;
r_io_cq1_iv <= io_cq1_iv;
r_io_cq2_iv <= io_cq2_iv;
r_io_cq3_iv <= io_cq3_iv;
r_io_cq4_iv <= io_cq4_iv;
r_io_cq5_iv <= io_cq5_iv;
r_io_cq6_iv <= io_cq6_iv;
r_io_cq7_iv <= io_cq7_iv;
r_io_cq8_iv <= io_cq8_iv;
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file golden_nonce_fifo.v when simulating
// the core, golden_nonce_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module golden_nonce_fifo(
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input wr_clk;
input rd_clk;
input [31 : 0] din;
input wr_en;
input rd_en;
output [31 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V8_2 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(7),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("spartan6"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(125),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(124),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(7),
.C_RD_DEPTH(128),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(7),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(7),
.C_WR_DEPTH(128),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(7),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.RST(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
// Async clears must not race with clocks if we want repeatable results
reg set_l = in[20];
reg clr_l = in[21];
always @ (negedge clk) begin
set_l <= in[20];
clr_l <= in[21];
end
//====== Mux
wire [1:0] qm;
// delay z a b sel
udp_mux2 #(0.1) m0 (qm[0], in[0], in[2], in[4]);
udp_mux2 #0.1 m1 (qm[1], in[1], in[3], in[4]);
`define verilatorxx
`ifdef verilatorxx
reg [1:0] ql;
reg [1:0] qd;
// No sequential tables, yet
// always @* begin
// if (!clk) ql = in[13:12];
// end
always @(posedge clk or negedge set_l or negedge clr_l) begin
if (!set_l) qd <= ~2'b0;
else if (!clr_l) qd <= 2'b0;
else qd <= in[17:16];
end
`else
//====== Latch
// wire [1:0] ql;
// // q clk d
// udp_latch l0 (ql[0], !in[8], in[12]);
// udp_latch l1 (ql[1], !in[8], in[13]);
//====== DFF
wire [1:0] qd;
//always @* $display("UL q=%b c=%b d=%b", ql[1:0], in[8], in[13:12]);
// q clk d set_l clr_l
udp_dff d0 (qd[0], in[8], in[16], set_l, clr_l);
udp_dff d2 (qd[1], in[8], in[17], set_l, clr_l);
`endif
// Aggregate outputs into a single result vector
wire [63:0] result = {52'h0, 2'b0,qd, 4'b0, 2'b0,qm};
// wire [63:0] result = {52'h0, 2'b0,qd, 2'b0,ql, 2'b0,qm};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
// Note not all simulators agree about the latch result. Maybe have a race?
`define EXPECTED_SUM 64'hb73acf228acaeaa3
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
primitive udp_mux2 (z, a, b, sel);
output z;
input a, b, sel;
table
//a b s o
? 1 1 : 1 ;
? 0 1 : 0 ;
1 ? 0 : 1 ;
0 ? 0 : 0 ;
1 1 x : 1 ;
0 0 x : 0 ;
endtable
endprimitive
primitive udp_latch (q, clk, d);
output q; reg q;
input clk, d;
table
//clk d q q'
0 1 : ? : 1;
0 0 : ? : 0;
1 ? : ? : -;
endtable
endprimitive
primitive udp_dff (q, clk, d, set_l, clr_l);
output q;
input clk, d, set_l, clr_l;
reg q;
table
//ck d s c : q : q'
r 0 1 ? : ? : 0 ;
r 1 ? 1 : ? : 1 ;
* 1 ? 1 : 1 : 1 ;
* 0 1 ? : 0 : 0 ;
f ? ? ? : ? : - ;
b * ? ? : ? : - ;
? ? 0 ? : ? : 1 ;
b ? * 1 : 1 : 1 ;
x 1 * 1 : 1 : 1 ;
? ? 1 0 : ? : 0 ;
b ? 1 * : 0 : 0 ;
x 0 1 * : 0 : 0 ;
endtable
endprimitive
|
module register_io
(clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr, strobe_wr,
rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1, reg_2, reg_3,
atr_tx_delay, atr_rx_delay, master_controls, debug_en, interp_rate, decim_rate,
atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1,
atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3,
txa_refclk, txb_refclk, rxa_refclk, rxb_refclk, misc, txmux);
input clk;
input reset;
input wire [1:0] enable;
input wire [6:0] addr;
input wire [31:0] datain;
output reg [31:0] dataout;
output wire [15:0] debugbus;
output reg [6:0] addr_wr;
output reg [31:0] data_wr;
output wire strobe_wr;
input wire [31:0] rssi_0;
input wire [31:0] rssi_1;
input wire [31:0] rssi_2;
input wire [31:0] rssi_3;
output wire [31:0] threshhold;
output wire [31:0] rssi_wait;
input wire [15:0] reg_0;
input wire [15:0] reg_1;
input wire [15:0] reg_2;
input wire [15:0] reg_3;
input wire [11:0] atr_tx_delay;
input wire [11:0] atr_rx_delay;
input wire [7:0] master_controls;
input wire [3:0] debug_en;
input wire [15:0] atr_mask_0;
input wire [15:0] atr_txval_0;
input wire [15:0] atr_rxval_0;
input wire [15:0] atr_mask_1;
input wire [15:0] atr_txval_1;
input wire [15:0] atr_rxval_1;
input wire [15:0] atr_mask_2;
input wire [15:0] atr_txval_2;
input wire [15:0] atr_rxval_2;
input wire [15:0] atr_mask_3;
input wire [15:0] atr_txval_3;
input wire [15:0] atr_rxval_3;
input wire [7:0] txa_refclk;
input wire [7:0] txb_refclk;
input wire [7:0] rxa_refclk;
input wire [7:0] rxb_refclk;
input wire [7:0] interp_rate;
input wire [7:0] decim_rate;
input wire [7:0] misc;
input wire [31:0] txmux;
wire [31:0] bundle[43:0];
assign bundle[0] = 32'hFFFFFFFF;
assign bundle[1] = 32'hFFFFFFFF;
assign bundle[2] = {20'd0, atr_tx_delay};
assign bundle[3] = {20'd0, atr_rx_delay};
assign bundle[4] = {24'sd0, master_controls};
assign bundle[5] = 32'hFFFFFFFF;
assign bundle[6] = 32'hFFFFFFFF;
assign bundle[7] = 32'hFFFFFFFF;
assign bundle[8] = 32'hFFFFFFFF;
assign bundle[9] = {15'd0, reg_0};
assign bundle[10] = {15'd0, reg_1};
assign bundle[11] = {15'd0, reg_2};
assign bundle[12] = {15'd0, reg_3};
assign bundle[13] = {15'd0, misc};
assign bundle[14] = {28'd0, debug_en};
assign bundle[15] = 32'hFFFFFFFF;
assign bundle[16] = 32'hFFFFFFFF;
assign bundle[17] = 32'hFFFFFFFF;
assign bundle[18] = 32'hFFFFFFFF;
assign bundle[19] = 32'hFFFFFFFF;
assign bundle[20] = {16'd0, atr_mask_0};
assign bundle[21] = {16'd0, atr_txval_0};
assign bundle[22] = {16'd0, atr_rxval_0};
assign bundle[23] = {16'd0, atr_mask_1};
assign bundle[24] = {16'd0, atr_txval_1};
assign bundle[25] = {16'd0, atr_rxval_1};
assign bundle[26] = {16'd0, atr_mask_2};
assign bundle[27] = {16'd0, atr_txval_2};
assign bundle[28] = {16'd0, atr_rxval_2};
assign bundle[29] = {16'd0, atr_mask_3};
assign bundle[30] = {16'd0, atr_txval_3};
assign bundle[31] = {16'd0, atr_rxval_3};
assign bundle[32] = {24'd0, interp_rate};
assign bundle[33] = {24'd0, decim_rate};
assign bundle[34] = 32'hFFFFFFFF;
assign bundle[35] = 32'hFFFFFFFF;
assign bundle[36] = 32'hFFFFFFFF;
assign bundle[37] = 32'hFFFFFFFF;
assign bundle[38] = 32'hFFFFFFFF;
assign bundle[39] = txmux;
assign bundle[40] = {24'd0, txa_refclk};
assign bundle[41] = {24'd0, rxa_refclk};
assign bundle[42] = {24'd0, txb_refclk};
assign bundle[43] = {24'd0, rxb_refclk};
reg strobe;
wire [31:0] out[7:0];
assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
assign threshhold = out[1];
assign rssi_wait = out[2];
assign strobe_wr = strobe;
always @(*)
if (reset | ~enable[1])
begin
strobe <= 0;
dataout <= 0;
end
else
begin
if (enable[0])
begin
//read
if (addr <= 7'd43)
dataout <= bundle[addr];
else if (addr <= 7'd57 && addr >= 7'd50)
dataout <= out[addr-7'd50];
else
dataout <= 32'hFFFFFFFF;
strobe <= 0;
end
else
begin
//write
dataout <= dataout;
strobe <= 1;
data_wr <= datain;
addr_wr <= addr;
end
end
//register declarations
setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));
setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1]));
setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2]));
setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3]));
setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4]));
setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[5]));
setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6]));
setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
.strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
outc_w30, outd_w73,
// Inputs
clk, ina_w1, inb_w61
);
input clk;
input ina_w1;
input [60:0] inb_w61;
output [29:0] outc_w30;
output [72:0] outd_w73;
sub sub (
// Outputs
.outy_w92 (outc_w30), // .large => (small)
.outz_w22 (outd_w73), // .small => (large)
// Inputs
.clk (clk),
.inw_w31 (ina_w1), // .large <= (small)
.inx_w11 (inb_w61) // .small <= (large)
);
endmodule
module sub (/*AUTOARG*/
// Outputs
outy_w92, outz_w22,
// Inputs
clk, inw_w31, inx_w11
);
input clk;
input [30:0] inw_w31;
input [10:0] inx_w11;
output reg [91:0] outy_w92 /*verilator public*/;
output reg [21:0] outz_w22 /*verilator public*/;
always @(posedge clk) begin
outy_w92 <= {inw_w31[29:0],inw_w31[29:0],inw_w31[29:0],2'b00};
outz_w22 <= {inx_w11[10:0],inx_w11[10:0]};
end
endmodule // regfile
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
outc_w30, outd_w73,
// Inputs
clk, ina_w1, inb_w61
);
input clk;
input ina_w1;
input [60:0] inb_w61;
output [29:0] outc_w30;
output [72:0] outd_w73;
sub sub (
// Outputs
.outy_w92 (outc_w30), // .large => (small)
.outz_w22 (outd_w73), // .small => (large)
// Inputs
.clk (clk),
.inw_w31 (ina_w1), // .large <= (small)
.inx_w11 (inb_w61) // .small <= (large)
);
endmodule
module sub (/*AUTOARG*/
// Outputs
outy_w92, outz_w22,
// Inputs
clk, inw_w31, inx_w11
);
input clk;
input [30:0] inw_w31;
input [10:0] inx_w11;
output reg [91:0] outy_w92 /*verilator public*/;
output reg [21:0] outz_w22 /*verilator public*/;
always @(posedge clk) begin
outy_w92 <= {inw_w31[29:0],inw_w31[29:0],inw_w31[29:0],2'b00};
outz_w22 <= {inx_w11[10:0],inx_w11[10:0]};
end
endmodule // regfile
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// NOTE This only works for N=4, max interp rate of 128
// NOTE signal "rate" is ONE LESS THAN the actual rate
module cic_int_shifter(rate,signal_in,signal_out);
parameter bw = 16;
parameter maxbitgain = 21;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case(rate)
// Exact Cases
8'd4 : bitgain = 6;
8'd8 : bitgain = 9;
8'd16 : bitgain = 12;
8'd32 : bitgain = 15;
8'd64 : bitgain = 18;
8'd128 : bitgain = 21;
// Nearest without overflow
8'd5 : bitgain = 7;
8'd6 : bitgain = 8;
8'd7 : bitgain = 9;
8'd9,8'd10 : bitgain = 10;
8'd11,8'd12 : bitgain = 11;
8'd13,8'd14,8'd15 : bitgain = 12;
8'd17,8'd18,8'd19,8'd20 : bitgain = 13;
8'd21,8'd22,8'd23,8'd24,8'd25 : bitgain = 14;
8'd26,8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 15;
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38,8'd39,8'd40 : bitgain = 16;
8'd41,8'd42,8'd43,8'd44,8'd45,8'd46,8'd47,8'd48,8'd49,8'd50 : bitgain = 17;
8'd51,8'd52,8'd53,8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 18;
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76,8'd77,8'd78,8'd79,8'd80 : bitgain = 19;
8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90,8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101 : bitgain = 20;
default : bitgain = 19;
endcase // case(rate)
endfunction // bitgain
wire [4:0] shift = bitgain(rate+1);
// We should be able to do this, but can't ....
// assign signal_out = signal_in[shift+bw-1:shift];
always @*
case(shift)
5'd6 : signal_out = signal_in[6+bw-1:6];
5'd9 : signal_out = signal_in[9+bw-1:9];
5'd12 : signal_out = signal_in[12+bw-1:12];
5'd15 : signal_out = signal_in[15+bw-1:15];
5'd18 : signal_out = signal_in[18+bw-1:18];
5'd21 : signal_out = signal_in[21+bw-1:21];
5'd7 : signal_out = signal_in[7+bw-1:7];
5'd8 : signal_out = signal_in[8+bw-1:8];
5'd10 : signal_out = signal_in[10+bw-1:10];
5'd11 : signal_out = signal_in[11+bw-1:11];
5'd13 : signal_out = signal_in[13+bw-1:13];
5'd14 : signal_out = signal_in[14+bw-1:14];
5'd16 : signal_out = signal_in[16+bw-1:16];
5'd17 : signal_out = signal_in[17+bw-1:17];
5'd19 : signal_out = signal_in[19+bw-1:19];
5'd20 : signal_out = signal_in[20+bw-1:20];
default : signal_out = signal_in[21+bw-1:21];
endcase // case(shift)
endmodule // cic_int_shifter
|
//`include "../../firmware/include/fpga_regs_common.v"
//`include "../../firmware/include/fpga_regs_standard.v"
module rx_buffer_inband
( input usbclk,
input bus_reset,
input reset, // DSP side reset (used here), do not reset registers
input reset_regs, //Only reset registers
output [15:0] usbdata,
input RD,
output wire have_pkt_rdy,
output reg rx_overrun,
input wire [3:0] channels,
input wire [15:0] ch_0,
input wire [15:0] ch_1,
input wire [15:0] ch_2,
input wire [15:0] ch_3,
input wire [15:0] ch_4,
input wire [15:0] ch_5,
input wire [15:0] ch_6,
input wire [15:0] ch_7,
input rxclk,
input rxstrobe,
input clear_status,
input [6:0] serial_addr,
input [31:0] serial_data,
input serial_strobe,
output wire [15:0] debugbus,
//Connection with tx_inband
input rx_WR,
input [15:0] rx_databus,
input rx_WR_done,
output reg rx_WR_enabled,
//signal strength
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
input wire [31:0] rssi_2, input wire [31:0] rssi_3,
input wire [1:0] tx_underrun
);
parameter NUM_CHAN =1;
genvar i ;
// FX2 Bug Fix
reg [8:0] read_count;
always @(negedge usbclk)
if(bus_reset)
read_count <= #1 9'd0;
else if(RD & ~read_count[8])
read_count <= #1 read_count + 9'd1;
else
read_count <= #1 RD ? read_count : 9'b0;
// Time counter
reg [31:0] adctime;
always @(posedge rxclk)
if (reset)
adctime <= 0;
else if (rxstrobe)
adctime <= adctime + 1;
// USB side fifo
wire [11:0] rdusedw;
wire [11:0] wrusedw;
wire [15:0] fifodata;
wire [15:0] fifodata_il;
reg [15:0] fifodata_16;
wire WR;
wire have_space;
assign fifodata_il = fifodata_16;
fifo_4kx16_dc rx_usb_fifo (
.aclr ( reset ),
.data ( fifodata ),
.rdclk ( ~usbclk ),
.rdreq ( RD & ~read_count[8] ),
.wrclk ( rxclk ),
.wrreq ( WR ),
.q ( usbdata ),
.rdempty ( ),
.rdusedw ( rdusedw ),
.wrfull ( ),
.wrusedw ( wrusedw ) );
assign have_pkt_rdy = (rdusedw >= 12'd256);
assign have_space = (wrusedw < 12'd760);
// Rx side fifos
wire chan_rdreq;
wire [15:0] chan_fifodata;
wire [9:0] chan_usedw;
wire [NUM_CHAN:0] chan_empty;
wire [3:0] rd_select;
wire [NUM_CHAN:0] rx_full;
wire [7:0] debug;
packet_builder #(NUM_CHAN) rx_pkt_builer (
.rxclk ( rxclk ),
.reset ( reset ),
.adctime ( adctime ),
.channels ( 4'd1 ), //need to be tested and changed to channels
.chan_rdreq ( chan_rdreq ),
.chan_fifodata ( chan_fifodata ),
.chan_empty ( chan_empty ),
.rd_select ( rd_select ),
.chan_usedw ( chan_usedw ),
.WR ( WR ),
.fifodata ( fifodata ),
.have_space ( have_space ),
.rssi_0(rssi_0), .rssi_1(rssi_1),
.rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
.underrun(tx_underrun));
// Detect overrun
always @(posedge rxclk)
if(reset)
rx_overrun <= 1'b0;
else if(rx_full[0])
rx_overrun <= 1'b1;
else if(clear_status)
rx_overrun <= 1'b0;
// TODO write this genericly
//wire [15:0]ch[NUM_CHAN:0];
//assign ch[0] = ch_0;
wire cmd_empty;
always @(posedge rxclk)
if(reset)
rx_WR_enabled <= 1;
else if(cmd_empty)
rx_WR_enabled <= 1;
else if(rx_WR_done)
rx_WR_enabled <= 0;
// Switching of channels
reg [3:0] store_next;
always @(posedge rxclk)
if(reset)
store_next <= #1 4'd0;
else if(rxstrobe & (store_next == 0))
store_next <= #1 4'd1;
else if(~rx_full & (store_next == 4'd2))
store_next <= #1 4'd0;
else if(~rx_full & (store_next != 0))
store_next <= #1 store_next + 4'd1;
always @*
case(store_next)
4'd1 : fifodata_16 = ch_0;
4'd2 : fifodata_16 = ch_1;
default: fifodata_16 = 16'hFFFF;
endcase
wire [15:0] dataout [0:NUM_CHAN];
wire [9:0] usedw [0:NUM_CHAN];
wire empty[0:NUM_CHAN];
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_fifos
wire rdreq;
assign rdreq = (rd_select == i) & chan_rdreq;
fifo_1kx16 rx_chan_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( fifodata_il ),
.rdreq ( rdreq ),
.wrreq ( ~rx_full[i] & (store_next != 0)),
.empty (empty[i]),
.full (rx_full[i]),
.q ( dataout[i]),
.usedw ( usedw[i]),
.almost_empty(chan_empty[i])
);
end
endgenerate
fifo_1kx16 rx_cmd_fifo (
.aclr ( reset ),
.clock ( rxclk ),
.data ( rx_databus ),
.rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
.wrreq ( rx_WR & rx_WR_enabled),
.empty ( cmd_empty),
.full ( rx_full[NUM_CHAN] ),
.q ( dataout[NUM_CHAN]),
.usedw ( usedw[NUM_CHAN] )
);
assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
assign chan_fifodata = dataout[rd_select];
assign chan_usedw = usedw[rd_select];
assign debugbus = {4'd0, rxclk, rxstrobe, store_next[3], store_next[1], store_next[0]};
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_cmd # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output pcie_rx_cmd_wr_en,
output [33:0] pcie_rx_cmd_wr_data,
input pcie_rx_cmd_full_n,
output pcie_tx_cmd_wr_en,
output [33:0] pcie_tx_cmd_wr_data,
input pcie_tx_cmd_full_n,
input dma_tx_done_wr_en,
input [20:0] dma_tx_done_wr_data,
output dma_tx_done_wr_rdy_n,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_dma_cmd_rd_en;
wire [49:0] w_dma_cmd_rd_data;
wire w_dma_cmd_empty_n;
wire w_pcie_cmd_wr_en;
wire [33:0] w_pcie_cmd_wr_data;
wire w_pcie_cmd_full_n;
wire w_pcie_cmd_rd_en;
wire [33:0] w_pcie_cmd_rd_data;
wire w_pcie_cmd_empty_n;
wire w_dma_done_rd_en;
wire [20:0] w_dma_done_rd_data;
wire w_dma_done_empty_n;
wire w_prp_pcie_alloc;
wire [7:0] w_prp_pcie_alloc_tag;
wire [5:4] w_prp_pcie_tag_alloc_len;
wire w_pcie_tag_full_n;
wire w_prp_fifo_wr_en;
wire [4:0] w_prp_fifo_wr_addr;
wire [C_PCIE_DATA_WIDTH-1:0] w_prp_fifo_wr_data;
wire [5:0] w_prp_rear_full_addr;
wire [5:0] w_prp_rear_addr;
wire w_prp_fifo_full_n;
wire w_prp_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_prp_fifo_rd_data;
wire w_prp_fifo_free_en;
wire [5:4] w_prp_fifo_free_len;
wire w_prp_fifo_empty_n;
dma_cmd_fifo
dma_cmd_fifo_inst0
(
.wr_clk (cpu_bus_clk),
.wr_rst_n (pcie_user_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.rd_clk (pcie_user_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (w_dma_cmd_rd_en),
.rd_data (w_dma_cmd_rd_data),
.empty_n (w_dma_cmd_empty_n)
);
pcie_dma_cmd_fifo
pcie_dma_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_cmd_wr_en),
.wr_data (w_pcie_cmd_wr_data),
.full_n (w_pcie_cmd_full_n),
.rd_en (w_pcie_cmd_rd_en),
.rd_data (w_pcie_cmd_rd_data),
.empty_n (w_pcie_cmd_empty_n)
);
dma_done_fifo
dma_done_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (dma_tx_done_wr_en),
.wr0_data (dma_tx_done_wr_data),
.wr0_rdy_n (dma_tx_done_wr_rdy_n),
.full_n (),
.rd_en (w_dma_done_rd_en),
.rd_data (w_dma_done_rd_data),
.empty_n (w_dma_done_empty_n),
.wr1_clk (dma_bus_clk),
.wr1_rst_n (pcie_user_rst_n),
.wr1_en (dma_rx_done_wr_en),
.wr1_data (dma_rx_done_wr_data),
.wr1_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_prp_rx_fifo
pcie_prp_rx_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_prp_fifo_wr_en),
.wr_addr (w_prp_fifo_wr_addr),
.wr_data (w_prp_fifo_wr_data),
.rear_full_addr (w_prp_rear_full_addr),
.rear_addr (w_prp_rear_addr),
.alloc_len (w_prp_pcie_tag_alloc_len),
.full_n (w_prp_fifo_full_n),
.rd_en (w_prp_fifo_rd_en),
.rd_data (w_prp_fifo_rd_data),
.free_en (w_prp_fifo_free_en),
.free_len (w_prp_fifo_free_len),
.empty_n (w_prp_fifo_empty_n)
);
pcie_prp_rx_tag
pcie_prp_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_prp_pcie_alloc),
.pcie_alloc_tag (w_prp_pcie_alloc_tag),
.pcie_tag_alloc_len (w_prp_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.cpld_fifo_tag (cpld_prp_fifo_tag),
.cpld_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_fifo_tag_last (cpld_prp_fifo_tag_last),
.fifo_wr_en (w_prp_fifo_wr_en),
.fifo_wr_addr (w_prp_fifo_wr_addr),
.fifo_wr_data (w_prp_fifo_wr_data),
.rear_full_addr (w_prp_rear_full_addr),
.rear_addr (w_prp_rear_addr)
);
dma_cmd_gen
dma_cmd_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.dma_cmd_rd_en (w_dma_cmd_rd_en),
.dma_cmd_rd_data (w_dma_cmd_rd_data),
.dma_cmd_empty_n (w_dma_cmd_empty_n),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.pcie_cmd_wr_en (w_pcie_cmd_wr_en),
.pcie_cmd_wr_data (w_pcie_cmd_wr_data),
.pcie_cmd_full_n (w_pcie_cmd_full_n),
.prp_pcie_alloc (w_prp_pcie_alloc),
.prp_pcie_alloc_tag (w_prp_pcie_alloc_tag),
.prp_pcie_tag_alloc_len (w_prp_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.prp_fifo_full_n (w_prp_fifo_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack)
);
pcie_dma_cmd_gen
pcie_dma_cmd_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_cmd_rd_en (w_pcie_cmd_rd_en),
.pcie_cmd_rd_data (w_pcie_cmd_rd_data),
.pcie_cmd_empty_n (w_pcie_cmd_empty_n),
.prp_fifo_rd_en (w_prp_fifo_rd_en),
.prp_fifo_rd_data (w_prp_fifo_rd_data),
.prp_fifo_free_en (w_prp_fifo_free_en),
.prp_fifo_free_len (w_prp_fifo_free_len),
.prp_fifo_empty_n (w_prp_fifo_empty_n),
.pcie_rx_cmd_wr_en (pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (pcie_tx_cmd_full_n)
);
dma_done
dma_done_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dma_done_rd_en (w_dma_done_rd_en),
.dma_done_rd_data (w_dma_done_rd_data),
.dma_done_empty_n (w_dma_done_empty_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_cmd # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output pcie_rx_cmd_wr_en,
output [33:0] pcie_rx_cmd_wr_data,
input pcie_rx_cmd_full_n,
output pcie_tx_cmd_wr_en,
output [33:0] pcie_tx_cmd_wr_data,
input pcie_tx_cmd_full_n,
input dma_tx_done_wr_en,
input [20:0] dma_tx_done_wr_data,
output dma_tx_done_wr_rdy_n,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_dma_cmd_rd_en;
wire [49:0] w_dma_cmd_rd_data;
wire w_dma_cmd_empty_n;
wire w_pcie_cmd_wr_en;
wire [33:0] w_pcie_cmd_wr_data;
wire w_pcie_cmd_full_n;
wire w_pcie_cmd_rd_en;
wire [33:0] w_pcie_cmd_rd_data;
wire w_pcie_cmd_empty_n;
wire w_dma_done_rd_en;
wire [20:0] w_dma_done_rd_data;
wire w_dma_done_empty_n;
wire w_prp_pcie_alloc;
wire [7:0] w_prp_pcie_alloc_tag;
wire [5:4] w_prp_pcie_tag_alloc_len;
wire w_pcie_tag_full_n;
wire w_prp_fifo_wr_en;
wire [4:0] w_prp_fifo_wr_addr;
wire [C_PCIE_DATA_WIDTH-1:0] w_prp_fifo_wr_data;
wire [5:0] w_prp_rear_full_addr;
wire [5:0] w_prp_rear_addr;
wire w_prp_fifo_full_n;
wire w_prp_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_prp_fifo_rd_data;
wire w_prp_fifo_free_en;
wire [5:4] w_prp_fifo_free_len;
wire w_prp_fifo_empty_n;
dma_cmd_fifo
dma_cmd_fifo_inst0
(
.wr_clk (cpu_bus_clk),
.wr_rst_n (pcie_user_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.rd_clk (pcie_user_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (w_dma_cmd_rd_en),
.rd_data (w_dma_cmd_rd_data),
.empty_n (w_dma_cmd_empty_n)
);
pcie_dma_cmd_fifo
pcie_dma_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_cmd_wr_en),
.wr_data (w_pcie_cmd_wr_data),
.full_n (w_pcie_cmd_full_n),
.rd_en (w_pcie_cmd_rd_en),
.rd_data (w_pcie_cmd_rd_data),
.empty_n (w_pcie_cmd_empty_n)
);
dma_done_fifo
dma_done_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (dma_tx_done_wr_en),
.wr0_data (dma_tx_done_wr_data),
.wr0_rdy_n (dma_tx_done_wr_rdy_n),
.full_n (),
.rd_en (w_dma_done_rd_en),
.rd_data (w_dma_done_rd_data),
.empty_n (w_dma_done_empty_n),
.wr1_clk (dma_bus_clk),
.wr1_rst_n (pcie_user_rst_n),
.wr1_en (dma_rx_done_wr_en),
.wr1_data (dma_rx_done_wr_data),
.wr1_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_prp_rx_fifo
pcie_prp_rx_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_prp_fifo_wr_en),
.wr_addr (w_prp_fifo_wr_addr),
.wr_data (w_prp_fifo_wr_data),
.rear_full_addr (w_prp_rear_full_addr),
.rear_addr (w_prp_rear_addr),
.alloc_len (w_prp_pcie_tag_alloc_len),
.full_n (w_prp_fifo_full_n),
.rd_en (w_prp_fifo_rd_en),
.rd_data (w_prp_fifo_rd_data),
.free_en (w_prp_fifo_free_en),
.free_len (w_prp_fifo_free_len),
.empty_n (w_prp_fifo_empty_n)
);
pcie_prp_rx_tag
pcie_prp_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_prp_pcie_alloc),
.pcie_alloc_tag (w_prp_pcie_alloc_tag),
.pcie_tag_alloc_len (w_prp_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.cpld_fifo_tag (cpld_prp_fifo_tag),
.cpld_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_fifo_tag_last (cpld_prp_fifo_tag_last),
.fifo_wr_en (w_prp_fifo_wr_en),
.fifo_wr_addr (w_prp_fifo_wr_addr),
.fifo_wr_data (w_prp_fifo_wr_data),
.rear_full_addr (w_prp_rear_full_addr),
.rear_addr (w_prp_rear_addr)
);
dma_cmd_gen
dma_cmd_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.dma_cmd_rd_en (w_dma_cmd_rd_en),
.dma_cmd_rd_data (w_dma_cmd_rd_data),
.dma_cmd_empty_n (w_dma_cmd_empty_n),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.pcie_cmd_wr_en (w_pcie_cmd_wr_en),
.pcie_cmd_wr_data (w_pcie_cmd_wr_data),
.pcie_cmd_full_n (w_pcie_cmd_full_n),
.prp_pcie_alloc (w_prp_pcie_alloc),
.prp_pcie_alloc_tag (w_prp_pcie_alloc_tag),
.prp_pcie_tag_alloc_len (w_prp_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.prp_fifo_full_n (w_prp_fifo_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack)
);
pcie_dma_cmd_gen
pcie_dma_cmd_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_cmd_rd_en (w_pcie_cmd_rd_en),
.pcie_cmd_rd_data (w_pcie_cmd_rd_data),
.pcie_cmd_empty_n (w_pcie_cmd_empty_n),
.prp_fifo_rd_en (w_prp_fifo_rd_en),
.prp_fifo_rd_data (w_prp_fifo_rd_data),
.prp_fifo_free_en (w_prp_fifo_free_en),
.prp_fifo_free_len (w_prp_fifo_free_len),
.prp_fifo_empty_n (w_prp_fifo_empty_n),
.pcie_rx_cmd_wr_en (pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (pcie_tx_cmd_full_n)
);
dma_done
dma_done_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dma_done_rd_en (w_dma_done_rd_en),
.dma_done_rd_data (w_dma_done_rd_data),
.dma_done_empty_n (w_dma_done_empty_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_cmd # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output pcie_rx_cmd_wr_en,
output [33:0] pcie_rx_cmd_wr_data,
input pcie_rx_cmd_full_n,
output pcie_tx_cmd_wr_en,
output [33:0] pcie_tx_cmd_wr_data,
input pcie_tx_cmd_full_n,
input dma_tx_done_wr_en,
input [20:0] dma_tx_done_wr_data,
output dma_tx_done_wr_rdy_n,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_dma_cmd_rd_en;
wire [49:0] w_dma_cmd_rd_data;
wire w_dma_cmd_empty_n;
wire w_pcie_cmd_wr_en;
wire [33:0] w_pcie_cmd_wr_data;
wire w_pcie_cmd_full_n;
wire w_pcie_cmd_rd_en;
wire [33:0] w_pcie_cmd_rd_data;
wire w_pcie_cmd_empty_n;
wire w_dma_done_rd_en;
wire [20:0] w_dma_done_rd_data;
wire w_dma_done_empty_n;
wire w_prp_pcie_alloc;
wire [7:0] w_prp_pcie_alloc_tag;
wire [5:4] w_prp_pcie_tag_alloc_len;
wire w_pcie_tag_full_n;
wire w_prp_fifo_wr_en;
wire [4:0] w_prp_fifo_wr_addr;
wire [C_PCIE_DATA_WIDTH-1:0] w_prp_fifo_wr_data;
wire [5:0] w_prp_rear_full_addr;
wire [5:0] w_prp_rear_addr;
wire w_prp_fifo_full_n;
wire w_prp_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_prp_fifo_rd_data;
wire w_prp_fifo_free_en;
wire [5:4] w_prp_fifo_free_len;
wire w_prp_fifo_empty_n;
dma_cmd_fifo
dma_cmd_fifo_inst0
(
.wr_clk (cpu_bus_clk),
.wr_rst_n (pcie_user_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.rd_clk (pcie_user_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (w_dma_cmd_rd_en),
.rd_data (w_dma_cmd_rd_data),
.empty_n (w_dma_cmd_empty_n)
);
pcie_dma_cmd_fifo
pcie_dma_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_cmd_wr_en),
.wr_data (w_pcie_cmd_wr_data),
.full_n (w_pcie_cmd_full_n),
.rd_en (w_pcie_cmd_rd_en),
.rd_data (w_pcie_cmd_rd_data),
.empty_n (w_pcie_cmd_empty_n)
);
dma_done_fifo
dma_done_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (dma_tx_done_wr_en),
.wr0_data (dma_tx_done_wr_data),
.wr0_rdy_n (dma_tx_done_wr_rdy_n),
.full_n (),
.rd_en (w_dma_done_rd_en),
.rd_data (w_dma_done_rd_data),
.empty_n (w_dma_done_empty_n),
.wr1_clk (dma_bus_clk),
.wr1_rst_n (pcie_user_rst_n),
.wr1_en (dma_rx_done_wr_en),
.wr1_data (dma_rx_done_wr_data),
.wr1_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_prp_rx_fifo
pcie_prp_rx_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_prp_fifo_wr_en),
.wr_addr (w_prp_fifo_wr_addr),
.wr_data (w_prp_fifo_wr_data),
.rear_full_addr (w_prp_rear_full_addr),
.rear_addr (w_prp_rear_addr),
.alloc_len (w_prp_pcie_tag_alloc_len),
.full_n (w_prp_fifo_full_n),
.rd_en (w_prp_fifo_rd_en),
.rd_data (w_prp_fifo_rd_data),
.free_en (w_prp_fifo_free_en),
.free_len (w_prp_fifo_free_len),
.empty_n (w_prp_fifo_empty_n)
);
pcie_prp_rx_tag
pcie_prp_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_prp_pcie_alloc),
.pcie_alloc_tag (w_prp_pcie_alloc_tag),
.pcie_tag_alloc_len (w_prp_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.cpld_fifo_tag (cpld_prp_fifo_tag),
.cpld_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_fifo_tag_last (cpld_prp_fifo_tag_last),
.fifo_wr_en (w_prp_fifo_wr_en),
.fifo_wr_addr (w_prp_fifo_wr_addr),
.fifo_wr_data (w_prp_fifo_wr_data),
.rear_full_addr (w_prp_rear_full_addr),
.rear_addr (w_prp_rear_addr)
);
dma_cmd_gen
dma_cmd_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.dma_cmd_rd_en (w_dma_cmd_rd_en),
.dma_cmd_rd_data (w_dma_cmd_rd_data),
.dma_cmd_empty_n (w_dma_cmd_empty_n),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.pcie_cmd_wr_en (w_pcie_cmd_wr_en),
.pcie_cmd_wr_data (w_pcie_cmd_wr_data),
.pcie_cmd_full_n (w_pcie_cmd_full_n),
.prp_pcie_alloc (w_prp_pcie_alloc),
.prp_pcie_alloc_tag (w_prp_pcie_alloc_tag),
.prp_pcie_tag_alloc_len (w_prp_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.prp_fifo_full_n (w_prp_fifo_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack)
);
pcie_dma_cmd_gen
pcie_dma_cmd_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_cmd_rd_en (w_pcie_cmd_rd_en),
.pcie_cmd_rd_data (w_pcie_cmd_rd_data),
.pcie_cmd_empty_n (w_pcie_cmd_empty_n),
.prp_fifo_rd_en (w_prp_fifo_rd_en),
.prp_fifo_rd_data (w_prp_fifo_rd_data),
.prp_fifo_free_en (w_prp_fifo_free_en),
.prp_fifo_free_len (w_prp_fifo_free_len),
.prp_fifo_empty_n (w_prp_fifo_empty_n),
.pcie_rx_cmd_wr_en (pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (pcie_tx_cmd_full_n)
);
dma_done
dma_done_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dma_done_rd_en (w_dma_done_rd_en),
.dma_done_rd_data (w_dma_done_rd_data),
.dma_done_empty_n (w_dma_done_empty_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt)
);
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2005 Matt Ettus
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Clock, enable, and reset controls for whole system
module master_control
( input master_clk, input usbclk,
input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
output tx_bus_reset, output rx_bus_reset,
output wire tx_dsp_reset, output wire rx_dsp_reset,
output wire enable_tx, output wire enable_rx,
output wire [7:0] interp_rate, output wire [7:0] decim_rate,
output tx_sample_strobe, output strobe_interp,
output rx_sample_strobe, output strobe_decim,
input tx_empty,
input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3,
//the following output is for register reads only
output wire [11:0] atr_tx_delay, output wire [11:0] atr_rx_delay, output wire [7:0] master_controls,
output wire [3:0] debug_en,
output wire [15:0] atr_mask_0, output wire [15:0] atr_txval_0, output wire [15:0] atr_rxval_0,
output wire [15:0] atr_mask_1, output wire [15:0] atr_txval_1, output wire [15:0] atr_rxval_1,
output wire [15:0] atr_mask_2, output wire [15:0] atr_txval_2, output wire [15:0] atr_rxval_2,
output wire [15:0] atr_mask_3, output wire [15:0] atr_txval_3, output wire [15:0] atr_rxval_3,
output wire [7:0] txa_refclk, output wire [7:0] txb_refclk, output wire [7:0] rxa_refclk, output wire [7:0] rxb_refclk
);
// FIXME need a separate reset for all control settings
// Master Controls assignments
//wire [7:0] master_controls;
setting_reg #(`FR_MASTER_CTRL) sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls));
assign enable_tx = master_controls[0];
assign enable_rx = master_controls[1];
assign tx_dsp_reset = master_controls[2];
assign rx_dsp_reset = master_controls[3];
// Unused - 4-7
// Strobe Generators
setting_reg #(`FR_INTERP_RATE) sr_interp(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(interp_rate));
setting_reg #(`FR_DECIM_RATE) sr_decim(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(decim_rate));
strobe_gen da_strobe_gen
( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
.rate(8'd1),.strobe_in(1'b1),.strobe(tx_sample_strobe) );
strobe_gen tx_strobe_gen
( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
.rate(interp_rate),.strobe_in(tx_sample_strobe),.strobe(strobe_interp) );
assign rx_sample_strobe = 1'b1;
strobe_gen decim_strobe_gen
( .clock(master_clk),.reset(rx_dsp_reset),.enable(enable_rx),
.rate(decim_rate),.strobe_in(rx_sample_strobe),.strobe(strobe_decim) );
// Reset syncs for bus (usbclk) side
// The RX bus side reset isn't used, the TX bus side one may not be needed
reg tx_reset_bus_sync1, rx_reset_bus_sync1, tx_reset_bus_sync2, rx_reset_bus_sync2;
always @(posedge usbclk)
begin
tx_reset_bus_sync1 <= #1 tx_dsp_reset;
rx_reset_bus_sync1 <= #1 rx_dsp_reset;
tx_reset_bus_sync2 <= #1 tx_reset_bus_sync1;
rx_reset_bus_sync2 <= #1 rx_reset_bus_sync1;
end
assign tx_bus_reset = tx_reset_bus_sync2;
assign rx_bus_reset = rx_reset_bus_sync2;
//wire [7:0] txa_refclk, rxa_refclk, txb_refclk, rxb_refclk;
wire txaclk,txbclk,rxaclk,rxbclk;
//wire [3:0] debug_en;
wire [3:0] txcvr_ctrl;
wire [31:0] txcvr_rxlines, txcvr_txlines;
setting_reg #(`FR_TX_A_REFCLK) sr_txaref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txa_refclk));
setting_reg #(`FR_RX_A_REFCLK) sr_rxaref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxa_refclk));
setting_reg #(`FR_TX_B_REFCLK) sr_txbref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txb_refclk));
setting_reg #(`FR_RX_B_REFCLK) sr_rxbref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxb_refclk));
setting_reg #(`FR_DEBUG_EN) sr_debugen(.clock(master_clk),.reset(rx_dsp_reset|tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(debug_en));
clk_divider clk_div_0 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txaclk),.ratio(txa_refclk[6:0]));
clk_divider clk_div_1 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxaclk),.ratio(rxa_refclk[6:0]));
clk_divider clk_div_2 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txbclk),.ratio(txb_refclk[6:0]));
clk_divider clk_div_3 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxbclk),.ratio(rxb_refclk[6:0]));
reg [15:0] io_0_reg,io_1_reg,io_2_reg,io_3_reg;
// Upper 16 bits are mask for lower 16
always @(posedge master_clk)
if(serial_strobe)
case(serial_addr)
`FR_IO_0 : io_0_reg
<= #1 (io_0_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_1 : io_1_reg
<= #1 (io_1_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_2 : io_2_reg
<= #1 (io_2_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_3 : io_3_reg
<= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
wire transmit_now;
wire atr_ctl;
//wire [11:0] atr_tx_delay, atr_rx_delay;
//wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3;
setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0));
setting_reg #(`FR_ATR_TXVAL_0) sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0));
setting_reg #(`FR_ATR_RXVAL_0) sr_atr_rxval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_0));
setting_reg #(`FR_ATR_MASK_1) sr_atr_mask_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_1));
setting_reg #(`FR_ATR_TXVAL_1) sr_atr_txval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_1));
setting_reg #(`FR_ATR_RXVAL_1) sr_atr_rxval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_1));
setting_reg #(`FR_ATR_MASK_2) sr_atr_mask_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_2));
setting_reg #(`FR_ATR_TXVAL_2) sr_atr_txval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_2));
setting_reg #(`FR_ATR_RXVAL_2) sr_atr_rxval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_2));
setting_reg #(`FR_ATR_MASK_3) sr_atr_mask_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_3));
setting_reg #(`FR_ATR_TXVAL_3) sr_atr_txval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_3));
setting_reg #(`FR_ATR_RXVAL_3) sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3));
//setting_reg #(`FR_ATR_CTL) sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl));
setting_reg #(`FR_ATR_TX_DELAY) sr_atr_tx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_tx_delay));
setting_reg #(`FR_ATR_RX_DELAY) sr_atr_rx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rx_delay));
assign atr_ctl = 1'b1;
atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl),.tx_empty_i(tx_empty),
.tx_delay_i(atr_tx_delay),.rx_delay_i(atr_rx_delay),.atr_tx_o(transmit_now));
wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0;
wire [15:0] io_0 = ({{16{atr_ctl}}} & atr_mask_0 & atr_selected_0) | (~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg);
wire [15:0] atr_selected_1 = transmit_now ? atr_txval_1 : atr_rxval_1;
wire [15:0] io_1 = ({{16{atr_ctl}}} & atr_mask_1 & atr_selected_1) | (~({{16{atr_ctl}}} & atr_mask_1) & io_1_reg);
wire [15:0] atr_selected_2 = transmit_now ? atr_txval_2 : atr_rxval_2;
wire [15:0] io_2 = ({{16{atr_ctl}}} & atr_mask_2 & atr_selected_2) | (~({{16{atr_ctl}}} & atr_mask_2) & io_2_reg);
wire [15:0] atr_selected_3 = transmit_now ? atr_txval_3 : atr_rxval_3;
wire [15:0] io_3 = ({{16{atr_ctl}}} & atr_mask_3 & atr_selected_3) | (~({{16{atr_ctl}}} & atr_mask_3) & io_3_reg);
assign reg_0 = debug_en[0] ? debug_0 : txa_refclk[7] ? {io_0[15:1],txaclk} : io_0;
assign reg_1 = debug_en[1] ? debug_1 : rxa_refclk[7] ? {io_1[15:1],rxaclk} : io_1;
assign reg_2 = debug_en[2] ? debug_2 : txb_refclk[7] ? {io_2[15:1],txbclk} : io_2;
assign reg_3 = debug_en[3] ? debug_3 : rxb_refclk[7] ? {io_3[15:1],rxbclk} : io_3;
endmodule // master_control
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2005 Matt Ettus
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Clock, enable, and reset controls for whole system
module master_control
( input master_clk, input usbclk,
input wire [6:0] serial_addr, input wire [31:0] serial_data, input wire serial_strobe,
output tx_bus_reset, output rx_bus_reset,
output wire tx_dsp_reset, output wire rx_dsp_reset,
output wire enable_tx, output wire enable_rx,
output wire [7:0] interp_rate, output wire [7:0] decim_rate,
output tx_sample_strobe, output strobe_interp,
output rx_sample_strobe, output strobe_decim,
input tx_empty,
input wire [15:0] debug_0,input wire [15:0] debug_1,input wire [15:0] debug_2,input wire [15:0] debug_3,
output wire [15:0] reg_0, output wire [15:0] reg_1, output wire [15:0] reg_2, output wire [15:0] reg_3,
//the following output is for register reads only
output wire [11:0] atr_tx_delay, output wire [11:0] atr_rx_delay, output wire [7:0] master_controls,
output wire [3:0] debug_en,
output wire [15:0] atr_mask_0, output wire [15:0] atr_txval_0, output wire [15:0] atr_rxval_0,
output wire [15:0] atr_mask_1, output wire [15:0] atr_txval_1, output wire [15:0] atr_rxval_1,
output wire [15:0] atr_mask_2, output wire [15:0] atr_txval_2, output wire [15:0] atr_rxval_2,
output wire [15:0] atr_mask_3, output wire [15:0] atr_txval_3, output wire [15:0] atr_rxval_3,
output wire [7:0] txa_refclk, output wire [7:0] txb_refclk, output wire [7:0] rxa_refclk, output wire [7:0] rxb_refclk
);
// FIXME need a separate reset for all control settings
// Master Controls assignments
//wire [7:0] master_controls;
setting_reg #(`FR_MASTER_CTRL) sr_mstr_ctrl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(master_controls));
assign enable_tx = master_controls[0];
assign enable_rx = master_controls[1];
assign tx_dsp_reset = master_controls[2];
assign rx_dsp_reset = master_controls[3];
// Unused - 4-7
// Strobe Generators
setting_reg #(`FR_INTERP_RATE) sr_interp(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(interp_rate));
setting_reg #(`FR_DECIM_RATE) sr_decim(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(decim_rate));
strobe_gen da_strobe_gen
( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
.rate(8'd1),.strobe_in(1'b1),.strobe(tx_sample_strobe) );
strobe_gen tx_strobe_gen
( .clock(master_clk),.reset(tx_dsp_reset),.enable(enable_tx),
.rate(interp_rate),.strobe_in(tx_sample_strobe),.strobe(strobe_interp) );
assign rx_sample_strobe = 1'b1;
strobe_gen decim_strobe_gen
( .clock(master_clk),.reset(rx_dsp_reset),.enable(enable_rx),
.rate(decim_rate),.strobe_in(rx_sample_strobe),.strobe(strobe_decim) );
// Reset syncs for bus (usbclk) side
// The RX bus side reset isn't used, the TX bus side one may not be needed
reg tx_reset_bus_sync1, rx_reset_bus_sync1, tx_reset_bus_sync2, rx_reset_bus_sync2;
always @(posedge usbclk)
begin
tx_reset_bus_sync1 <= #1 tx_dsp_reset;
rx_reset_bus_sync1 <= #1 rx_dsp_reset;
tx_reset_bus_sync2 <= #1 tx_reset_bus_sync1;
rx_reset_bus_sync2 <= #1 rx_reset_bus_sync1;
end
assign tx_bus_reset = tx_reset_bus_sync2;
assign rx_bus_reset = rx_reset_bus_sync2;
//wire [7:0] txa_refclk, rxa_refclk, txb_refclk, rxb_refclk;
wire txaclk,txbclk,rxaclk,rxbclk;
//wire [3:0] debug_en;
wire [3:0] txcvr_ctrl;
wire [31:0] txcvr_rxlines, txcvr_txlines;
setting_reg #(`FR_TX_A_REFCLK) sr_txaref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txa_refclk));
setting_reg #(`FR_RX_A_REFCLK) sr_rxaref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxa_refclk));
setting_reg #(`FR_TX_B_REFCLK) sr_txbref(.clock(master_clk),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(txb_refclk));
setting_reg #(`FR_RX_B_REFCLK) sr_rxbref(.clock(master_clk),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(rxb_refclk));
setting_reg #(`FR_DEBUG_EN) sr_debugen(.clock(master_clk),.reset(rx_dsp_reset|tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(debug_en));
clk_divider clk_div_0 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txaclk),.ratio(txa_refclk[6:0]));
clk_divider clk_div_1 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxaclk),.ratio(rxa_refclk[6:0]));
clk_divider clk_div_2 (.reset(tx_dsp_reset),.in_clk(master_clk),.out_clk(txbclk),.ratio(txb_refclk[6:0]));
clk_divider clk_div_3 (.reset(rx_dsp_reset),.in_clk(master_clk),.out_clk(rxbclk),.ratio(rxb_refclk[6:0]));
reg [15:0] io_0_reg,io_1_reg,io_2_reg,io_3_reg;
// Upper 16 bits are mask for lower 16
always @(posedge master_clk)
if(serial_strobe)
case(serial_addr)
`FR_IO_0 : io_0_reg
<= #1 (io_0_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_1 : io_1_reg
<= #1 (io_1_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_2 : io_2_reg
<= #1 (io_2_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_IO_3 : io_3_reg
<= #1 (io_3_reg & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
wire transmit_now;
wire atr_ctl;
//wire [11:0] atr_tx_delay, atr_rx_delay;
//wire [15:0] atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1, atr_rxval_1, atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3, atr_rxval_3;
setting_reg #(`FR_ATR_MASK_0) sr_atr_mask_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_0));
setting_reg #(`FR_ATR_TXVAL_0) sr_atr_txval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_0));
setting_reg #(`FR_ATR_RXVAL_0) sr_atr_rxval_0(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_0));
setting_reg #(`FR_ATR_MASK_1) sr_atr_mask_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_1));
setting_reg #(`FR_ATR_TXVAL_1) sr_atr_txval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_1));
setting_reg #(`FR_ATR_RXVAL_1) sr_atr_rxval_1(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_1));
setting_reg #(`FR_ATR_MASK_2) sr_atr_mask_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_2));
setting_reg #(`FR_ATR_TXVAL_2) sr_atr_txval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_2));
setting_reg #(`FR_ATR_RXVAL_2) sr_atr_rxval_2(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_2));
setting_reg #(`FR_ATR_MASK_3) sr_atr_mask_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_mask_3));
setting_reg #(`FR_ATR_TXVAL_3) sr_atr_txval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_txval_3));
setting_reg #(`FR_ATR_RXVAL_3) sr_atr_rxval_3(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rxval_3));
//setting_reg #(`FR_ATR_CTL) sr_atr_ctl(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_ctl));
setting_reg #(`FR_ATR_TX_DELAY) sr_atr_tx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_tx_delay));
setting_reg #(`FR_ATR_RX_DELAY) sr_atr_rx_delay(.clock(master_clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(atr_rx_delay));
assign atr_ctl = 1'b1;
atr_delay atr_delay(.clk_i(master_clk),.rst_i(tx_dsp_reset),.ena_i(atr_ctl),.tx_empty_i(tx_empty),
.tx_delay_i(atr_tx_delay),.rx_delay_i(atr_rx_delay),.atr_tx_o(transmit_now));
wire [15:0] atr_selected_0 = transmit_now ? atr_txval_0 : atr_rxval_0;
wire [15:0] io_0 = ({{16{atr_ctl}}} & atr_mask_0 & atr_selected_0) | (~({{16{atr_ctl}}} & atr_mask_0) & io_0_reg);
wire [15:0] atr_selected_1 = transmit_now ? atr_txval_1 : atr_rxval_1;
wire [15:0] io_1 = ({{16{atr_ctl}}} & atr_mask_1 & atr_selected_1) | (~({{16{atr_ctl}}} & atr_mask_1) & io_1_reg);
wire [15:0] atr_selected_2 = transmit_now ? atr_txval_2 : atr_rxval_2;
wire [15:0] io_2 = ({{16{atr_ctl}}} & atr_mask_2 & atr_selected_2) | (~({{16{atr_ctl}}} & atr_mask_2) & io_2_reg);
wire [15:0] atr_selected_3 = transmit_now ? atr_txval_3 : atr_rxval_3;
wire [15:0] io_3 = ({{16{atr_ctl}}} & atr_mask_3 & atr_selected_3) | (~({{16{atr_ctl}}} & atr_mask_3) & io_3_reg);
assign reg_0 = debug_en[0] ? debug_0 : txa_refclk[7] ? {io_0[15:1],txaclk} : io_0;
assign reg_1 = debug_en[1] ? debug_1 : rxa_refclk[7] ? {io_1[15:1],rxaclk} : io_1;
assign reg_2 = debug_en[2] ? debug_2 : txb_refclk[7] ? {io_2[15:1],txbclk} : io_2;
assign reg_3 = debug_en[3] ? debug_3 : rxb_refclk[7] ? {io_3[15:1],rxbclk} : io_3;
endmodule // master_control
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx # (
parameter C_PCIE_DATA_WIDTH = 128
)
(
input pcie_user_clk,
input pcie_user_rst_n,
//pcie rx signal
input [C_PCIE_DATA_WIDTH-1:0] s_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_rx_tkeep,
input s_axis_rx_tlast,
input s_axis_rx_tvalid,
output s_axis_rx_tready,
input [21:0] s_axis_rx_tuser,
output pcie_mreq_err,
output pcie_cpld_err,
output pcie_cpld_len_err,
output mreq_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output [7:0] cpld0_fifo_tag,
output cpld0_fifo_tag_last,
output cpld0_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld0_fifo_wr_data,
output [7:0] cpld1_fifo_tag,
output cpld1_fifo_tag_last,
output cpld1_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld1_fifo_wr_data,
output [7:0] cpld2_fifo_tag,
output cpld2_fifo_tag_last,
output cpld2_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld2_fifo_wr_data
);
wire [7:0] w_cpld_fifo_tag;
wire w_cpld_fifo_tag_last;
wire w_cpld_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_cpld_fifo_wr_data;
pcie_rx_recv # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_rx_recv_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
//pcie rx signal
.s_axis_rx_tdata (s_axis_rx_tdata),
.s_axis_rx_tkeep (s_axis_rx_tkeep),
.s_axis_rx_tlast (s_axis_rx_tlast),
.s_axis_rx_tvalid (s_axis_rx_tvalid),
.s_axis_rx_tready (s_axis_rx_tready),
.s_axis_rx_tuser (s_axis_rx_tuser),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.mreq_fifo_wr_en (mreq_fifo_wr_en),
.mreq_fifo_wr_data (mreq_fifo_wr_data),
.cpld_fifo_tag (w_cpld_fifo_tag),
.cpld_fifo_tag_last (w_cpld_fifo_tag_last),
.cpld_fifo_wr_en (w_cpld_fifo_wr_en),
.cpld_fifo_wr_data (w_cpld_fifo_wr_data)
);
pcie_rx_cpld_sel
pcie_rx_cpld_sel_inst0(
.pcie_user_clk (pcie_user_clk),
.cpld_fifo_tag (w_cpld_fifo_tag),
.cpld_fifo_tag_last (w_cpld_fifo_tag_last),
.cpld_fifo_wr_en (w_cpld_fifo_wr_en),
.cpld_fifo_wr_data (w_cpld_fifo_wr_data),
.cpld0_fifo_tag (cpld0_fifo_tag),
.cpld0_fifo_tag_last (cpld0_fifo_tag_last),
.cpld0_fifo_wr_en (cpld0_fifo_wr_en),
.cpld0_fifo_wr_data (cpld0_fifo_wr_data),
.cpld1_fifo_tag (cpld1_fifo_tag),
.cpld1_fifo_tag_last (cpld1_fifo_tag_last),
.cpld1_fifo_wr_en (cpld1_fifo_wr_en),
.cpld1_fifo_wr_data (cpld1_fifo_wr_data),
.cpld2_fifo_tag (cpld2_fifo_tag),
.cpld2_fifo_tag_last (cpld2_fifo_tag_last),
.cpld2_fifo_wr_en (cpld2_fifo_wr_en),
.cpld2_fifo_wr_data (cpld2_fifo_wr_data)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx # (
parameter C_PCIE_DATA_WIDTH = 128
)
(
input pcie_user_clk,
input pcie_user_rst_n,
//pcie rx signal
input [C_PCIE_DATA_WIDTH-1:0] s_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_rx_tkeep,
input s_axis_rx_tlast,
input s_axis_rx_tvalid,
output s_axis_rx_tready,
input [21:0] s_axis_rx_tuser,
output pcie_mreq_err,
output pcie_cpld_err,
output pcie_cpld_len_err,
output mreq_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output [7:0] cpld0_fifo_tag,
output cpld0_fifo_tag_last,
output cpld0_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld0_fifo_wr_data,
output [7:0] cpld1_fifo_tag,
output cpld1_fifo_tag_last,
output cpld1_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld1_fifo_wr_data,
output [7:0] cpld2_fifo_tag,
output cpld2_fifo_tag_last,
output cpld2_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld2_fifo_wr_data
);
wire [7:0] w_cpld_fifo_tag;
wire w_cpld_fifo_tag_last;
wire w_cpld_fifo_wr_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_cpld_fifo_wr_data;
pcie_rx_recv # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_rx_recv_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
//pcie rx signal
.s_axis_rx_tdata (s_axis_rx_tdata),
.s_axis_rx_tkeep (s_axis_rx_tkeep),
.s_axis_rx_tlast (s_axis_rx_tlast),
.s_axis_rx_tvalid (s_axis_rx_tvalid),
.s_axis_rx_tready (s_axis_rx_tready),
.s_axis_rx_tuser (s_axis_rx_tuser),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.mreq_fifo_wr_en (mreq_fifo_wr_en),
.mreq_fifo_wr_data (mreq_fifo_wr_data),
.cpld_fifo_tag (w_cpld_fifo_tag),
.cpld_fifo_tag_last (w_cpld_fifo_tag_last),
.cpld_fifo_wr_en (w_cpld_fifo_wr_en),
.cpld_fifo_wr_data (w_cpld_fifo_wr_data)
);
pcie_rx_cpld_sel
pcie_rx_cpld_sel_inst0(
.pcie_user_clk (pcie_user_clk),
.cpld_fifo_tag (w_cpld_fifo_tag),
.cpld_fifo_tag_last (w_cpld_fifo_tag_last),
.cpld_fifo_wr_en (w_cpld_fifo_wr_en),
.cpld_fifo_wr_data (w_cpld_fifo_wr_data),
.cpld0_fifo_tag (cpld0_fifo_tag),
.cpld0_fifo_tag_last (cpld0_fifo_tag_last),
.cpld0_fifo_wr_en (cpld0_fifo_wr_en),
.cpld0_fifo_wr_data (cpld0_fifo_wr_data),
.cpld1_fifo_tag (cpld1_fifo_tag),
.cpld1_fifo_tag_last (cpld1_fifo_tag_last),
.cpld1_fifo_wr_en (cpld1_fifo_wr_en),
.cpld1_fifo_wr_data (cpld1_fifo_wr_data),
.cpld2_fifo_tag (cpld2_fifo_tag),
.cpld2_fifo_tag_last (cpld2_fifo_tag_last),
.cpld2_fifo_wr_en (cpld2_fifo_wr_en),
.cpld2_fifo_wr_data (cpld2_fifo_wr_data)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_axi.vh"
module m_axi_read # (
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 64,
parameter C_M_AXI_ID_WIDTH = 1,
parameter C_M_AXI_ARUSER_WIDTH = 1,
parameter C_M_AXI_RUSER_WIDTH = 1
)
(
////////////////////////////////////////////////////////////////
//AXI4 master read channel signals
input m_axi_aclk,
input m_axi_aresetn,
// Read address channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_M_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [7:0] m_axi_arlen,
output [2:0] m_axi_arsize,
output [1:0] m_axi_arburst,
output [1:0] m_axi_arlock,
output [3:0] m_axi_arcache,
output [2:0] m_axi_arprot,
output [3:0] m_axi_arregion,
output [3:0] m_axi_arqos,
output [C_M_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
// Read data channel
input [C_M_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [1:0] m_axi_rresp,
input m_axi_rlast,
input [C_M_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
output m_axi_rresp_err,
output dev_tx_cmd_rd_en,
input [29:0] dev_tx_cmd_rd_data,
input dev_tx_cmd_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n
);
localparam LP_AR_DELAY = 7;
localparam S_IDLE = 8'b00000001;
localparam S_CMD_0 = 8'b00000010;
localparam S_CMD_1 = 8'b00000100;
localparam S_WAIT_FULL_N = 8'b00001000;
localparam S_AR_REQ = 8'b00010000;
localparam S_AR_WAIT = 8'b00100000;
localparam S_AR_DONE = 8'b01000000;
localparam S_AR_DELAY = 8'b10000000;
reg [7:0] cur_state;
reg [7:0] next_state;
reg [31:2] r_dev_addr;
reg [12:2] r_dev_dma_len;
reg [9:2] r_dev_cur_len;
reg [9:2] r_m_axi_arlen;
reg [4:0] r_ar_delay;
reg r_dev_tx_cmd_rd_en;
reg r_pcie_tx_fifo_alloc_en;
wire w_axi_ar_req_gnt;
reg [2:0] r_axi_ar_req_gnt;
reg r_axi_ar_req;
reg r_m_axi_arvalid;
reg [C_M_AXI_DATA_WIDTH-1 : 0] r_m_axi_rdata;
reg r_m_axi_rlast;
//reg r_m_axi_rlast_d1;
//wire w_m_axi_rlast;
reg r_m_axi_rvalid;
reg [C_M_AXI_ID_WIDTH-1:0] r_m_axi_rid;
reg [1:0] r_m_axi_rresp;
reg r_m_axi_rresp_err;
reg r_m_axi_rresp_err_d1;
reg r_m_axi_rresp_err_d2;
assign m_axi_arid = 0;
assign m_axi_araddr = {r_dev_addr, 2'b0};
assign m_axi_arlen = {1'b0, r_m_axi_arlen[9:3]};
assign m_axi_arsize = `D_AXSIZE_008_BYTES;
assign m_axi_arburst = `D_AXBURST_INCR;
assign m_axi_arlock = `D_AXLOCK_NORMAL;
assign m_axi_arcache = `D_AXCACHE_NON_CACHE;
assign m_axi_arprot = `D_AXPROT_SECURE;
assign m_axi_arregion = 0;
assign m_axi_arqos = 0;
assign m_axi_aruser = 0;
assign m_axi_arvalid = r_m_axi_arvalid;
assign m_axi_rready = 1;
assign m_axi_rresp_err = r_m_axi_rresp_err_d2;
assign dev_tx_cmd_rd_en = r_dev_tx_cmd_rd_en;
assign pcie_tx_fifo_alloc_en = r_pcie_tx_fifo_alloc_en;
assign pcie_tx_fifo_alloc_len = r_dev_cur_len[9:4];
assign pcie_tx_fifo_wr_en = r_m_axi_rvalid;
assign pcie_tx_fifo_wr_data = r_m_axi_rdata;
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(dev_tx_cmd_empty_n == 1)
next_state <= S_CMD_0;
else
next_state <= S_IDLE;
end
S_CMD_0: begin
next_state <= S_CMD_1;
end
S_CMD_1: begin
next_state <= S_WAIT_FULL_N;
end
S_WAIT_FULL_N: begin
if(pcie_tx_fifo_full_n == 1 && w_axi_ar_req_gnt == 1)
next_state <= S_AR_REQ;
else
next_state <= S_WAIT_FULL_N;
end
S_AR_REQ: begin
if(m_axi_arready == 1)
next_state <= S_AR_DONE;
else
next_state <= S_AR_WAIT;
end
S_AR_WAIT: begin
if(m_axi_arready == 1)
next_state <= S_AR_DONE;
else
next_state <= S_AR_WAIT;
end
S_AR_DONE: begin
if(r_dev_dma_len == 0)
next_state <= S_IDLE;
else
next_state <= S_AR_DELAY;
end
S_AR_DELAY: begin
if(r_ar_delay == 0)
next_state <= S_WAIT_FULL_N;
else
next_state <= S_AR_DELAY;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge m_axi_aclk)
begin
case(cur_state)
S_IDLE: begin
end
S_CMD_0: begin
r_dev_dma_len <= {dev_tx_cmd_rd_data[10:2], 2'b0};
end
S_CMD_1: begin
if(r_dev_dma_len[8:2] == 0)
r_dev_cur_len[9] <= 1;
else
r_dev_cur_len[9] <= 0;
r_dev_cur_len[8:2] <= r_dev_dma_len[8:2];
r_dev_addr <= {dev_tx_cmd_rd_data[29:2], 2'b0};
end
S_WAIT_FULL_N: begin
r_m_axi_arlen <= r_dev_cur_len - 2;
end
S_AR_REQ: begin
r_dev_dma_len <= r_dev_dma_len - r_dev_cur_len;
end
S_AR_WAIT: begin
end
S_AR_DONE: begin
r_dev_cur_len <= 8'h80;
r_dev_addr <= r_dev_addr + r_dev_cur_len;
r_ar_delay <= LP_AR_DELAY;
end
S_AR_DELAY: begin
r_ar_delay <= r_ar_delay - 1;
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_CMD_0: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_CMD_1: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_WAIT_FULL_N: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_REQ: begin
r_m_axi_arvalid <= 1;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 1;
r_axi_ar_req <= 1;
end
S_AR_WAIT: begin
r_m_axi_arvalid <= 1;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_DONE: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_DELAY: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
default: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
endcase
end
//assign w_m_axi_rlast = r_m_axi_rlast & ~r_m_axi_rlast_d1;
always @ (posedge m_axi_aclk)
begin
r_m_axi_rid <= m_axi_rid;
r_m_axi_rdata <= m_axi_rdata;
r_m_axi_rlast <= m_axi_rlast & m_axi_rvalid;
//r_m_axi_rlast_d1 <= r_m_axi_rlast;
r_m_axi_rvalid <= m_axi_rvalid;
r_m_axi_rresp <= m_axi_rresp;
r_m_axi_rresp_err_d1 <= r_m_axi_rresp_err;
r_m_axi_rresp_err_d2 <= r_m_axi_rresp_err | r_m_axi_rresp_err_d1;
end
always @ (*)
begin
if(r_m_axi_rvalid == 1 && (r_m_axi_rresp != `D_AXI_RESP_OKAY || r_m_axi_rid != 0))
r_m_axi_rresp_err <= 1;
else
r_m_axi_rresp_err <= 0;
end
assign w_axi_ar_req_gnt = r_axi_ar_req_gnt[2];
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0) begin
r_axi_ar_req_gnt <= 3'b110;
end
else begin
case({r_m_axi_rlast, r_axi_ar_req})
2'b01: begin
r_axi_ar_req_gnt <= {r_axi_ar_req_gnt[1:0], r_axi_ar_req_gnt[2]};
end
2'b10: begin
r_axi_ar_req_gnt <= {r_axi_ar_req_gnt[0], r_axi_ar_req_gnt[2:1]};
end
default: begin
end
endcase
end
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_axi.vh"
module m_axi_read # (
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 64,
parameter C_M_AXI_ID_WIDTH = 1,
parameter C_M_AXI_ARUSER_WIDTH = 1,
parameter C_M_AXI_RUSER_WIDTH = 1
)
(
////////////////////////////////////////////////////////////////
//AXI4 master read channel signals
input m_axi_aclk,
input m_axi_aresetn,
// Read address channel
output [C_M_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_M_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [7:0] m_axi_arlen,
output [2:0] m_axi_arsize,
output [1:0] m_axi_arburst,
output [1:0] m_axi_arlock,
output [3:0] m_axi_arcache,
output [2:0] m_axi_arprot,
output [3:0] m_axi_arregion,
output [3:0] m_axi_arqos,
output [C_M_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
// Read data channel
input [C_M_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [1:0] m_axi_rresp,
input m_axi_rlast,
input [C_M_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
output m_axi_rresp_err,
output dev_tx_cmd_rd_en,
input [29:0] dev_tx_cmd_rd_data,
input dev_tx_cmd_empty_n,
output pcie_tx_fifo_alloc_en,
output [9:4] pcie_tx_fifo_alloc_len,
output pcie_tx_fifo_wr_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
input pcie_tx_fifo_full_n
);
localparam LP_AR_DELAY = 7;
localparam S_IDLE = 8'b00000001;
localparam S_CMD_0 = 8'b00000010;
localparam S_CMD_1 = 8'b00000100;
localparam S_WAIT_FULL_N = 8'b00001000;
localparam S_AR_REQ = 8'b00010000;
localparam S_AR_WAIT = 8'b00100000;
localparam S_AR_DONE = 8'b01000000;
localparam S_AR_DELAY = 8'b10000000;
reg [7:0] cur_state;
reg [7:0] next_state;
reg [31:2] r_dev_addr;
reg [12:2] r_dev_dma_len;
reg [9:2] r_dev_cur_len;
reg [9:2] r_m_axi_arlen;
reg [4:0] r_ar_delay;
reg r_dev_tx_cmd_rd_en;
reg r_pcie_tx_fifo_alloc_en;
wire w_axi_ar_req_gnt;
reg [2:0] r_axi_ar_req_gnt;
reg r_axi_ar_req;
reg r_m_axi_arvalid;
reg [C_M_AXI_DATA_WIDTH-1 : 0] r_m_axi_rdata;
reg r_m_axi_rlast;
//reg r_m_axi_rlast_d1;
//wire w_m_axi_rlast;
reg r_m_axi_rvalid;
reg [C_M_AXI_ID_WIDTH-1:0] r_m_axi_rid;
reg [1:0] r_m_axi_rresp;
reg r_m_axi_rresp_err;
reg r_m_axi_rresp_err_d1;
reg r_m_axi_rresp_err_d2;
assign m_axi_arid = 0;
assign m_axi_araddr = {r_dev_addr, 2'b0};
assign m_axi_arlen = {1'b0, r_m_axi_arlen[9:3]};
assign m_axi_arsize = `D_AXSIZE_008_BYTES;
assign m_axi_arburst = `D_AXBURST_INCR;
assign m_axi_arlock = `D_AXLOCK_NORMAL;
assign m_axi_arcache = `D_AXCACHE_NON_CACHE;
assign m_axi_arprot = `D_AXPROT_SECURE;
assign m_axi_arregion = 0;
assign m_axi_arqos = 0;
assign m_axi_aruser = 0;
assign m_axi_arvalid = r_m_axi_arvalid;
assign m_axi_rready = 1;
assign m_axi_rresp_err = r_m_axi_rresp_err_d2;
assign dev_tx_cmd_rd_en = r_dev_tx_cmd_rd_en;
assign pcie_tx_fifo_alloc_en = r_pcie_tx_fifo_alloc_en;
assign pcie_tx_fifo_alloc_len = r_dev_cur_len[9:4];
assign pcie_tx_fifo_wr_en = r_m_axi_rvalid;
assign pcie_tx_fifo_wr_data = r_m_axi_rdata;
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(dev_tx_cmd_empty_n == 1)
next_state <= S_CMD_0;
else
next_state <= S_IDLE;
end
S_CMD_0: begin
next_state <= S_CMD_1;
end
S_CMD_1: begin
next_state <= S_WAIT_FULL_N;
end
S_WAIT_FULL_N: begin
if(pcie_tx_fifo_full_n == 1 && w_axi_ar_req_gnt == 1)
next_state <= S_AR_REQ;
else
next_state <= S_WAIT_FULL_N;
end
S_AR_REQ: begin
if(m_axi_arready == 1)
next_state <= S_AR_DONE;
else
next_state <= S_AR_WAIT;
end
S_AR_WAIT: begin
if(m_axi_arready == 1)
next_state <= S_AR_DONE;
else
next_state <= S_AR_WAIT;
end
S_AR_DONE: begin
if(r_dev_dma_len == 0)
next_state <= S_IDLE;
else
next_state <= S_AR_DELAY;
end
S_AR_DELAY: begin
if(r_ar_delay == 0)
next_state <= S_WAIT_FULL_N;
else
next_state <= S_AR_DELAY;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge m_axi_aclk)
begin
case(cur_state)
S_IDLE: begin
end
S_CMD_0: begin
r_dev_dma_len <= {dev_tx_cmd_rd_data[10:2], 2'b0};
end
S_CMD_1: begin
if(r_dev_dma_len[8:2] == 0)
r_dev_cur_len[9] <= 1;
else
r_dev_cur_len[9] <= 0;
r_dev_cur_len[8:2] <= r_dev_dma_len[8:2];
r_dev_addr <= {dev_tx_cmd_rd_data[29:2], 2'b0};
end
S_WAIT_FULL_N: begin
r_m_axi_arlen <= r_dev_cur_len - 2;
end
S_AR_REQ: begin
r_dev_dma_len <= r_dev_dma_len - r_dev_cur_len;
end
S_AR_WAIT: begin
end
S_AR_DONE: begin
r_dev_cur_len <= 8'h80;
r_dev_addr <= r_dev_addr + r_dev_cur_len;
r_ar_delay <= LP_AR_DELAY;
end
S_AR_DELAY: begin
r_ar_delay <= r_ar_delay - 1;
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_CMD_0: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_CMD_1: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 1;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_WAIT_FULL_N: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_REQ: begin
r_m_axi_arvalid <= 1;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 1;
r_axi_ar_req <= 1;
end
S_AR_WAIT: begin
r_m_axi_arvalid <= 1;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_DONE: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
S_AR_DELAY: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
default: begin
r_m_axi_arvalid <= 0;
r_dev_tx_cmd_rd_en <= 0;
r_pcie_tx_fifo_alloc_en <= 0;
r_axi_ar_req <= 0;
end
endcase
end
//assign w_m_axi_rlast = r_m_axi_rlast & ~r_m_axi_rlast_d1;
always @ (posedge m_axi_aclk)
begin
r_m_axi_rid <= m_axi_rid;
r_m_axi_rdata <= m_axi_rdata;
r_m_axi_rlast <= m_axi_rlast & m_axi_rvalid;
//r_m_axi_rlast_d1 <= r_m_axi_rlast;
r_m_axi_rvalid <= m_axi_rvalid;
r_m_axi_rresp <= m_axi_rresp;
r_m_axi_rresp_err_d1 <= r_m_axi_rresp_err;
r_m_axi_rresp_err_d2 <= r_m_axi_rresp_err | r_m_axi_rresp_err_d1;
end
always @ (*)
begin
if(r_m_axi_rvalid == 1 && (r_m_axi_rresp != `D_AXI_RESP_OKAY || r_m_axi_rid != 0))
r_m_axi_rresp_err <= 1;
else
r_m_axi_rresp_err <= 0;
end
assign w_axi_ar_req_gnt = r_axi_ar_req_gnt[2];
always @ (posedge m_axi_aclk or negedge m_axi_aresetn)
begin
if(m_axi_aresetn == 0) begin
r_axi_ar_req_gnt <= 3'b110;
end
else begin
case({r_m_axi_rlast, r_axi_ar_req})
2'b01: begin
r_axi_ar_req_gnt <= {r_axi_ar_req_gnt[1:0], r_axi_ar_req_gnt[2]};
end
2'b10: begin
r_axi_ar_req_gnt <= {r_axi_ar_req_gnt[0], r_axi_ar_req_gnt[2:1]};
end
default: begin
end
endcase
end
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_prp_rx_fifo # (
parameter P_FIFO_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DEPTH_WIDTH-1:0] wr_addr,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
input [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
input [P_FIFO_DEPTH_WIDTH:0] rear_addr,
input [5:4] alloc_len,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
input free_en,
input [5:4] free_len,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_empty_addr;
wire [P_FIFO_DEPTH_WIDTH:0] w_valid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_front_addr;
assign w_invalid_front_addr = {~r_front_addr[P_FIFO_DEPTH_WIDTH], r_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign w_invalid_space = w_invalid_front_addr - rear_full_addr;
assign full_n = (w_invalid_space >= alloc_len);
assign w_valid_space = rear_addr - r_front_empty_addr;
assign empty_n = (w_valid_space >= free_len);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_front_empty_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (free_en == 1)
r_front_empty_addr <= r_front_empty_addr + free_len;
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = wr_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], wr_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (rd_data[P_FIFO_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_FIFO_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_prp_rx_fifo # (
parameter P_FIFO_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DEPTH_WIDTH-1:0] wr_addr,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
input [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
input [P_FIFO_DEPTH_WIDTH:0] rear_addr,
input [5:4] alloc_len,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
input free_en,
input [5:4] free_len,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_empty_addr;
wire [P_FIFO_DEPTH_WIDTH:0] w_valid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_front_addr;
assign w_invalid_front_addr = {~r_front_addr[P_FIFO_DEPTH_WIDTH], r_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign w_invalid_space = w_invalid_front_addr - rear_full_addr;
assign full_n = (w_invalid_space >= alloc_len);
assign w_valid_space = rear_addr - r_front_empty_addr;
assign empty_n = (w_valid_space >= free_len);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_front_empty_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (free_en == 1)
r_front_empty_addr <= r_front_empty_addr + free_len;
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = wr_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], wr_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (rd_data[P_FIFO_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_FIFO_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_irq_handler # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] cfg_command,
input cfg_interrupt_msienable,
input nvme_intms_ivms,
input nvme_intmc_ivmc,
output cq_irq_status,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input [7:0] admin_cq_tail_ptr,
input [7:0] io_cq1_tail_ptr,
input [7:0] io_cq2_tail_ptr,
input [7:0] io_cq3_tail_ptr,
input [7:0] io_cq4_tail_ptr,
input [7:0] io_cq5_tail_ptr,
input [7:0] io_cq6_tail_ptr,
input [7:0] io_cq7_tail_ptr,
input [7:0] io_cq8_tail_ptr,
input [7:0] admin_cq_head_ptr,
input [7:0] io_cq1_head_ptr,
input [7:0] io_cq2_head_ptr,
input [7:0] io_cq3_head_ptr,
input [7:0] io_cq4_head_ptr,
input [7:0] io_cq5_head_ptr,
input [7:0] io_cq6_head_ptr,
input [7:0] io_cq7_head_ptr,
input [7:0] io_cq8_head_ptr,
input [8:0] cq_head_update,
output pcie_legacy_irq_set,
output pcie_msi_irq_set,
output [2:0] pcie_irq_vector,
output pcie_legacy_irq_clear,
input pcie_irq_done
);
localparam LP_LEGACY_IRQ_DELAY_TIME = 8'h10;
localparam S_IDLE = 6'b000001;
localparam S_PCIE_MSI_IRQ_SET = 6'b000010;
localparam S_LEGACY_IRQ_SET = 6'b000100;
localparam S_LEGACY_IRQ_TIMER = 6'b001000;
localparam S_CQ_MSI_IRQ_MASK = 6'b010000;
localparam S_CQ_IRQ_DONE = 6'b100000;
reg [5:0] cur_state;
reg [5:0] next_state;
reg r_pcie_irq_en;
reg r_pcie_msi_en;
wire [8:0] w_cq_legacy_irq_status;
reg r_cq_legacy_irq_req;
wire [8:0] w_cq_msi_irq_status;
wire [8:0] w_cq_msi_irq_mask;
reg [8:0] r_cq_msi_irq_sel;
wire w_cq_msi_irq_req;
reg [8:0] r_cq_msi_irq_ack;
reg r_pcie_msi_irq_set;
reg [2:0] r_pcie_irq_vector;
reg r_pcie_legacy_irq_set;
reg [7:0] r_legacy_irq_timer;
assign w_cq_msi_irq_mask = {r_cq_msi_irq_sel[7:0], r_cq_msi_irq_sel[8]};
assign w_cq_msi_irq_req = ((w_cq_msi_irq_status & w_cq_msi_irq_mask) != 0);
assign pcie_legacy_irq_set = r_pcie_legacy_irq_set;
assign pcie_msi_irq_set = r_pcie_msi_irq_set;
assign pcie_irq_vector = r_pcie_irq_vector;
assign pcie_legacy_irq_clear = ((nvme_intms_ivms | nvme_intmc_ivmc) | (~r_cq_legacy_irq_req | ~r_pcie_irq_en) | r_pcie_msi_en);
assign cq_irq_status = r_pcie_legacy_irq_set;
always @ (posedge pcie_user_clk)
begin
r_pcie_irq_en <= ~cfg_command[10];
r_pcie_msi_en <= cfg_interrupt_msienable;
r_cq_legacy_irq_req <= (w_cq_legacy_irq_status != 0);
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(r_pcie_msi_en == 1) begin
if((w_cq_msi_irq_req | w_cq_msi_irq_status[0]) == 1)
next_state <= S_PCIE_MSI_IRQ_SET;
else
next_state <= S_IDLE;
end
else if(r_pcie_irq_en == 1)begin
if(r_cq_legacy_irq_req == 1)
next_state <= S_LEGACY_IRQ_SET;
else
next_state <= S_IDLE;
end
else
next_state <= S_IDLE;
end
S_PCIE_MSI_IRQ_SET: begin
if(pcie_irq_done == 1)
next_state <= S_CQ_MSI_IRQ_MASK;
else
next_state <= S_PCIE_MSI_IRQ_SET;
end
S_LEGACY_IRQ_SET: begin
if(pcie_irq_done == 1)
next_state <= S_LEGACY_IRQ_TIMER;
else
next_state <= S_LEGACY_IRQ_SET;
end
S_LEGACY_IRQ_TIMER: begin
if(r_legacy_irq_timer == 0)
next_state <= S_CQ_IRQ_DONE;
else
next_state <= S_LEGACY_IRQ_TIMER;
end
S_CQ_MSI_IRQ_MASK: begin
next_state <= S_CQ_IRQ_DONE;
end
S_CQ_IRQ_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_PCIE_MSI_IRQ_SET: begin
end
S_LEGACY_IRQ_SET: begin
r_legacy_irq_timer <= LP_LEGACY_IRQ_DELAY_TIME;
end
S_LEGACY_IRQ_TIMER: begin
r_legacy_irq_timer <= r_legacy_irq_timer - 1;
end
S_CQ_MSI_IRQ_MASK: begin
end
S_CQ_IRQ_DONE: begin
end
default: begin
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_cq_msi_irq_sel <= 1;
end
else begin
case(cur_state)
S_IDLE: begin
if(w_cq_msi_irq_status[0] == 1)
r_cq_msi_irq_sel <= 1;
else
r_cq_msi_irq_sel <= w_cq_msi_irq_mask;
end
S_PCIE_MSI_IRQ_SET: begin
end
S_LEGACY_IRQ_SET: begin
end
S_LEGACY_IRQ_TIMER: begin
end
S_CQ_MSI_IRQ_MASK: begin
end
S_CQ_IRQ_DONE: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(r_cq_msi_irq_sel) // synthesis parallel_case full_case
9'b000000001: r_pcie_irq_vector <= 0;
9'b000000010: r_pcie_irq_vector <= io_cq1_iv;
9'b000000100: r_pcie_irq_vector <= io_cq2_iv;
9'b000001000: r_pcie_irq_vector <= io_cq3_iv;
9'b000010000: r_pcie_irq_vector <= io_cq4_iv;
9'b000100000: r_pcie_irq_vector <= io_cq5_iv;
9'b001000000: r_pcie_irq_vector <= io_cq6_iv;
9'b010000000: r_pcie_irq_vector <= io_cq7_iv;
9'b100000000: r_pcie_irq_vector <= io_cq8_iv;
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_pcie_legacy_irq_set <= 0;
r_pcie_msi_irq_set <= 0;
r_cq_msi_irq_ack <= 0;
end
S_PCIE_MSI_IRQ_SET: begin
r_pcie_legacy_irq_set <= 0;
r_pcie_msi_irq_set <= 1;
r_cq_msi_irq_ack <= 0;
end
S_LEGACY_IRQ_SET: begin
r_pcie_legacy_irq_set <= 1;
r_pcie_msi_irq_set <= 0;
r_cq_msi_irq_ack <= 0;
end
S_LEGACY_IRQ_TIMER: begin
r_pcie_legacy_irq_set <= 0;
r_pcie_msi_irq_set <= 0;
r_cq_msi_irq_ack <= 0;
end
S_CQ_MSI_IRQ_MASK: begin
r_pcie_legacy_irq_set <= 0;
r_pcie_msi_irq_set <= 0;
r_cq_msi_irq_ack <= r_cq_msi_irq_sel;
end
S_CQ_IRQ_DONE: begin
r_pcie_legacy_irq_set <= 0;
r_pcie_msi_irq_set <= 0;
r_cq_msi_irq_ack <= 0;
end
default: begin
r_pcie_legacy_irq_set <= 0;
r_pcie_msi_irq_set <= 0;
r_cq_msi_irq_ack <= 0;
end
endcase
end
nvme_cq_check
nvme_cq_check_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[0]),
.cq_valid (cq_valid[0]),
.io_cq_irq_en (io_cq_irq_en[0]),
.cq_tail_ptr (admin_cq_tail_ptr),
.cq_head_ptr (admin_cq_head_ptr),
.cq_head_update (cq_head_update[0]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[0]),
.cq_msi_irq_req (w_cq_msi_irq_status[0]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[0])
);
nvme_cq_check
nvme_cq_check_inst1
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[1]),
.cq_valid (cq_valid[1]),
.io_cq_irq_en (io_cq_irq_en[1]),
.cq_tail_ptr (io_cq1_tail_ptr),
.cq_head_ptr (io_cq1_head_ptr),
.cq_head_update (cq_head_update[1]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[1]),
.cq_msi_irq_req (w_cq_msi_irq_status[1]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[1])
);
nvme_cq_check
nvme_cq_check_inst2
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[2]),
.cq_valid (cq_valid[2]),
.io_cq_irq_en (io_cq_irq_en[2]),
.cq_tail_ptr (io_cq2_tail_ptr),
.cq_head_ptr (io_cq2_head_ptr),
.cq_head_update (cq_head_update[2]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[2]),
.cq_msi_irq_req (w_cq_msi_irq_status[2]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[2])
);
nvme_cq_check
nvme_cq_check_inst3
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[3]),
.cq_valid (cq_valid[3]),
.io_cq_irq_en (io_cq_irq_en[3]),
.cq_tail_ptr (io_cq3_tail_ptr),
.cq_head_ptr (io_cq3_head_ptr),
.cq_head_update (cq_head_update[3]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[3]),
.cq_msi_irq_req (w_cq_msi_irq_status[3]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[3])
);
nvme_cq_check
nvme_cq_check_inst4
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[4]),
.cq_valid (cq_valid[4]),
.io_cq_irq_en (io_cq_irq_en[4]),
.cq_tail_ptr (io_cq4_tail_ptr),
.cq_head_ptr (io_cq4_head_ptr),
.cq_head_update (cq_head_update[4]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[4]),
.cq_msi_irq_req (w_cq_msi_irq_status[4]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[4])
);
nvme_cq_check
nvme_cq_check_inst5
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[5]),
.cq_valid (cq_valid[5]),
.io_cq_irq_en (io_cq_irq_en[5]),
.cq_tail_ptr (io_cq5_tail_ptr),
.cq_head_ptr (io_cq5_head_ptr),
.cq_head_update (cq_head_update[5]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[5]),
.cq_msi_irq_req (w_cq_msi_irq_status[5]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[5])
);
nvme_cq_check
nvme_cq_check_inst6
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[6]),
.cq_valid (cq_valid[6]),
.io_cq_irq_en (io_cq_irq_en[6]),
.cq_tail_ptr (io_cq6_tail_ptr),
.cq_head_ptr (io_cq6_head_ptr),
.cq_head_update (cq_head_update[6]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[6]),
.cq_msi_irq_req (w_cq_msi_irq_status[6]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[6])
);
nvme_cq_check
nvme_cq_check_inst7
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[7]),
.cq_valid (cq_valid[7]),
.io_cq_irq_en (io_cq_irq_en[7]),
.cq_tail_ptr (io_cq7_tail_ptr),
.cq_head_ptr (io_cq7_head_ptr),
.cq_head_update (cq_head_update[7]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[7]),
.cq_msi_irq_req (w_cq_msi_irq_status[7]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[7])
);
nvme_cq_check
nvme_cq_check_inst8
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_msi_en (r_pcie_msi_en),
.cq_rst_n (cq_rst_n[8]),
.cq_valid (cq_valid[8]),
.io_cq_irq_en (io_cq_irq_en[8]),
.cq_tail_ptr (io_cq8_tail_ptr),
.cq_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update[8]),
.cq_legacy_irq_req (w_cq_legacy_irq_status[8]),
.cq_msi_irq_req (w_cq_msi_irq_status[8]),
.cq_msi_irq_ack (r_cq_msi_irq_ack[8])
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [6:0] mem1d;
reg [6:0] mem2d [5:0];
reg [6:0] mem3d [4:0][5:0];
integer i,j,k;
// Four different test cases for out of bounds
// =
// <=
// Continuous assigns
// Output pin interconnect (also covers cont assigns)
// Each with both bit selects and array selects
initial begin
mem1d[0] = 1'b0;
i=7;
mem1d[i] = 1'b1;
if (mem1d[0] !== 1'b0) $stop;
//
for (i=0; i<8; i=i+1) begin
for (j=0; j<8; j=j+1) begin
for (k=0; k<8; k=k+1) begin
mem1d[k] = k[0];
mem2d[j][k] = j[0]+k[0];
mem3d[i][j][k] = i[0]+j[0]+k[0];
end
end
end
for (i=0; i<5; i=i+1) begin
for (j=0; j<6; j=j+1) begin
for (k=0; k<7; k=k+1) begin
if (mem1d[k] !== k[0]) $stop;
if (mem2d[j][k] !== j[0]+k[0]) $stop;
if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop;
end
end
end
end
integer wi;
wire [31:0] wd = cyc;
reg [31:0] reg2d[6:0];
always @ (posedge clk) reg2d[wi[2:0]] <= wd;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n",$time, cyc, wi[2:0], reg2d[wi[2:0]], wd);
`endif
cyc <= cyc + 1;
if (cyc<10) begin
wi <= 0;
end
else if (cyc==10) begin
wi <= 1;
end
else if (cyc==11) begin
if (reg2d[0] !== 10) $stop;
wi <= 6;
end
else if (cyc==12) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
wi <= 7; // Will be ignored
end
else if (cyc==13) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==14) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_axi.vh"
module s_axi_reg # (
parameter C_S_AXI_ADDR_WIDTH = 32,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_BASEADDR = 32'h80000000,
parameter C_S_AXI_HIGHADDR = 32'h80010000,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
input s_axi_aclk,
input s_axi_aresetn,
//Write address channel
input s_axi_awvalid,
output s_axi_awready,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
//Write data channel
input s_axi_wvalid,
output s_axi_wready,
input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,
//Write response channel
output s_axi_bvalid,
input s_axi_bready,
output [1:0] s_axi_bresp,
//Read address channel
input s_axi_arvalid,
output s_axi_arready,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [2:0] s_axi_arprot,
//Read data channel
output s_axi_rvalid,
input s_axi_rready,
output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
input m0_axi_bresp_err,
input m0_axi_rresp_err,
output dev_irq_assert,
output pcie_user_logic_rst,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst,
output nvme_csts_rdy,
output [8:0] sq_valid,
output [7:0] io_sq1_size,
output [7:0] io_sq2_size,
output [7:0] io_sq3_size,
output [7:0] io_sq4_size,
output [7:0] io_sq5_size,
output [7:0] io_sq6_size,
output [7:0] io_sq7_size,
output [7:0] io_sq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
output [3:0] io_sq1_cq_vec,
output [3:0] io_sq2_cq_vec,
output [3:0] io_sq3_cq_vec,
output [3:0] io_sq4_cq_vec,
output [3:0] io_sq5_cq_vec,
output [3:0] io_sq6_cq_vec,
output [3:0] io_sq7_cq_vec,
output [3:0] io_sq8_cq_vec,
output [8:0] cq_valid,
output [7:0] io_cq1_size,
output [7:0] io_cq2_size,
output [7:0] io_cq3_size,
output [7:0] io_cq4_size,
output [7:0] io_cq5_size,
output [7:0] io_cq6_size,
output [7:0] io_cq7_size,
output [7:0] io_cq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
output [8:0] io_cq_irq_en,
output [2:0] io_cq1_iv,
output [2:0] io_cq2_iv,
output [2:0] io_cq3_iv,
output [2:0] io_cq4_iv,
output [2:0] io_cq5_iv,
output [2:0] io_cq6_iv,
output [2:0] io_cq7_iv,
output [2:0] io_cq8_iv,
output hcmd_sq_rd_en,
input [18:0] hcmd_sq_rd_data,
input hcmd_sq_empty_n,
output [10:0] hcmd_table_rd_addr,
input [31:0] hcmd_table_rd_data,
output hcmd_cq_wr1_en,
output [34:0] hcmd_cq_wr1_data0,
output [34:0] hcmd_cq_wr1_data1,
input hcmd_cq_wr1_rdy_n,
output dma_cmd_wr_en,
output [49:0] dma_cmd_wr_data0,
output [49:0] dma_cmd_wr_data1,
input dma_cmd_wr_rdy_n,
input [7:0] dma_rx_direct_done_cnt,
input [7:0] dma_tx_direct_done_cnt,
input [7:0] dma_rx_done_cnt,
input [7:0] dma_tx_done_cnt,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable
);
localparam S_WR_IDLE = 8'b00000001;
localparam S_AW_VAILD = 8'b00000010;
localparam S_W_READY = 8'b00000100;
localparam S_B_VALID = 8'b00001000;
localparam S_WAIT_CQ_RDY = 8'b00010000;
localparam S_WR_CQ = 8'b00100000;
localparam S_WAIT_DMA_RDY = 8'b01000000;
localparam S_WR_DMA = 8'b10000000;
reg [7:0] cur_wr_state;
reg [7:0] next_wr_state;
localparam S_RD_IDLE = 5'b00001;
localparam S_AR_VAILD = 5'b00010;
localparam S_AR_REG = 5'b00100;
localparam S_BRAM_READ = 5'b01000;
localparam S_R_READY = 5'b10000;
reg [4:0] cur_rd_state;
reg [4:0] next_rd_state;
reg r_s_axi_awready;
reg [15:2] r_s_axi_awaddr;
reg r_s_axi_wready;
reg r_s_axi_bvalid;
reg [1:0] r_s_axi_bresp;
reg r_s_axi_arready;
reg [15:2] r_s_axi_araddr;
reg r_s_axi_rvalid;
reg [C_S_AXI_DATA_WIDTH-1:0] r_s_axi_rdata;
reg [1:0] r_s_axi_rresp;
reg r_irq_assert;
reg [11:0] r_irq_req;
reg [11:0] r_irq_mask;
reg [11:0] r_irq_clear;
reg [11:0] r_irq_set;
reg r_pcie_user_logic_rst;
reg [1:0] r_nvme_csts_shst;
reg r_nvme_csts_rdy;
reg [8:0] r_sq_valid;
reg [7:0] r_io_sq1_size;
reg [7:0] r_io_sq2_size;
reg [7:0] r_io_sq3_size;
reg [7:0] r_io_sq4_size;
reg [7:0] r_io_sq5_size;
reg [7:0] r_io_sq6_size;
reg [7:0] r_io_sq7_size;
reg [7:0] r_io_sq8_size;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq1_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq2_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq3_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq4_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq5_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq6_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq7_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq8_bs_addr;
reg [3:0] r_io_sq1_cq_vec;
reg [3:0] r_io_sq2_cq_vec;
reg [3:0] r_io_sq3_cq_vec;
reg [3:0] r_io_sq4_cq_vec;
reg [3:0] r_io_sq5_cq_vec;
reg [3:0] r_io_sq6_cq_vec;
reg [3:0] r_io_sq7_cq_vec;
reg [3:0] r_io_sq8_cq_vec;
reg [8:0] r_cq_valid;
reg [7:0] r_io_cq1_size;
reg [7:0] r_io_cq2_size;
reg [7:0] r_io_cq3_size;
reg [7:0] r_io_cq4_size;
reg [7:0] r_io_cq5_size;
reg [7:0] r_io_cq6_size;
reg [7:0] r_io_cq7_size;
reg [7:0] r_io_cq8_size;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq1_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq2_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq3_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq4_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq5_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq6_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq7_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq8_bs_addr;
reg [8:0] r_io_cq_irq_en;
reg [2:0] r_io_cq1_iv;
reg [2:0] r_io_cq2_iv;
reg [2:0] r_io_cq3_iv;
reg [2:0] r_io_cq4_iv;
reg [2:0] r_io_cq5_iv;
reg [2:0] r_io_cq6_iv;
reg [2:0] r_io_cq7_iv;
reg [2:0] r_io_cq8_iv;
reg [1:0] r_cql_type;
reg [3:0] r_cpl_sq_qid;
reg [15:0] r_cpl_cid;
reg [6:0] r_hcmd_slot_tag;
reg [14:0] r_cpl_status;
reg [31:0] r_cpl_specific;
reg r_dma_cmd_type;
reg r_dma_cmd_dir;
reg [6:0] r_dma_cmd_hcmd_slot_tag;
reg [31:2] r_dma_cmd_dev_addr;
reg [12:2] r_dma_cmd_dev_len;
reg [8:0] r_dma_cmd_4k_offset;
reg [C_PCIE_ADDR_WIDTH-1:2] r_dma_cmd_pcie_addr;
reg r_hcmd_cq_wr1_en;
reg r_dma_cmd_wr_en;
reg r_hcmd_sq_rd_en;
reg [31:0] r_wdata;
reg r_awaddr_cntl_reg_en;
//reg r_awaddr_pcie_reg_en;
reg r_awaddr_nvme_reg_en;
reg r_awaddr_nvme_fifo_en;
reg r_awaddr_hcmd_cq_wr1_en;
reg r_awaddr_dma_cmd_wr_en;
reg r_cntl_reg_en;
//reg r_pcie_reg_en;
reg r_nvme_reg_en;
reg r_nvme_fifo_en;
reg [31:0] r_rdata;
reg r_araddr_cntl_reg_en;
reg r_araddr_pcie_reg_en;
reg r_araddr_nvme_reg_en;
reg r_araddr_nvme_fifo_en;
reg r_araddr_hcmd_table_rd_en;
reg r_araddr_hcmd_sq_rd_en;
reg [31:0] r_cntl_reg_rdata;
reg [31:0] r_pcie_reg_rdata;
reg [31:0] r_nvme_reg_rdata;
reg [31:0] r_nvme_fifo_rdata;
reg r_pcie_link_up;
reg [15:0] r_cfg_command;
reg [2:0] r_cfg_interrupt_mmenable;
reg r_cfg_interrupt_msienable;
reg r_cfg_interrupt_msixenable;
reg r_nvme_cc_en;
reg [1:0] r_nvme_cc_shn;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_bresp_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_bresp_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_bresp_err_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_rresp_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_rresp_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_rresp_err_d2;
reg r_pcie_mreq_err;
reg r_pcie_cpld_err;
reg r_pcie_cpld_len_err;
assign s_axi_awready = r_s_axi_awready;
assign s_axi_wready = r_s_axi_wready;
assign s_axi_bvalid = r_s_axi_bvalid;
assign s_axi_bresp = r_s_axi_bresp;
assign s_axi_arready = r_s_axi_arready;
assign s_axi_rvalid = r_s_axi_rvalid;
assign s_axi_rdata = r_s_axi_rdata;
assign s_axi_rresp = r_s_axi_rresp;
assign dev_irq_assert = r_irq_assert;
assign sq_valid = r_sq_valid;
assign io_sq1_size = r_io_sq1_size;
assign io_sq2_size = r_io_sq2_size;
assign io_sq3_size = r_io_sq3_size;
assign io_sq4_size = r_io_sq4_size;
assign io_sq5_size = r_io_sq5_size;
assign io_sq6_size = r_io_sq6_size;
assign io_sq7_size = r_io_sq7_size;
assign io_sq8_size = r_io_sq8_size;
assign io_sq1_bs_addr = r_io_sq1_bs_addr;
assign io_sq2_bs_addr = r_io_sq2_bs_addr;
assign io_sq3_bs_addr = r_io_sq3_bs_addr;
assign io_sq4_bs_addr = r_io_sq4_bs_addr;
assign io_sq5_bs_addr = r_io_sq5_bs_addr;
assign io_sq6_bs_addr = r_io_sq6_bs_addr;
assign io_sq7_bs_addr = r_io_sq7_bs_addr;
assign io_sq8_bs_addr = r_io_sq8_bs_addr;
assign io_sq1_cq_vec = r_io_sq1_cq_vec;
assign io_sq2_cq_vec = r_io_sq2_cq_vec;
assign io_sq3_cq_vec = r_io_sq3_cq_vec;
assign io_sq4_cq_vec = r_io_sq4_cq_vec;
assign io_sq5_cq_vec = r_io_sq5_cq_vec;
assign io_sq6_cq_vec = r_io_sq6_cq_vec;
assign io_sq7_cq_vec = r_io_sq7_cq_vec;
assign io_sq8_cq_vec = r_io_sq8_cq_vec;
assign cq_valid = r_cq_valid;
assign io_cq1_size = r_io_cq1_size;
assign io_cq2_size = r_io_cq2_size;
assign io_cq3_size = r_io_cq3_size;
assign io_cq4_size = r_io_cq4_size;
assign io_cq5_size = r_io_cq5_size;
assign io_cq6_size = r_io_cq6_size;
assign io_cq7_size = r_io_cq7_size;
assign io_cq8_size = r_io_cq8_size;
assign io_cq1_bs_addr = r_io_cq1_bs_addr;
assign io_cq2_bs_addr = r_io_cq2_bs_addr;
assign io_cq3_bs_addr = r_io_cq3_bs_addr;
assign io_cq4_bs_addr = r_io_cq4_bs_addr;
assign io_cq5_bs_addr = r_io_cq5_bs_addr;
assign io_cq6_bs_addr = r_io_cq6_bs_addr;
assign io_cq7_bs_addr = r_io_cq7_bs_addr;
assign io_cq8_bs_addr = r_io_cq8_bs_addr;
assign io_cq_irq_en = r_io_cq_irq_en;
assign io_cq1_iv = r_io_cq1_iv;
assign io_cq2_iv = r_io_cq2_iv;
assign io_cq3_iv = r_io_cq3_iv;
assign io_cq4_iv = r_io_cq4_iv;
assign io_cq5_iv = r_io_cq5_iv;
assign io_cq6_iv = r_io_cq6_iv;
assign io_cq7_iv = r_io_cq7_iv;
assign io_cq8_iv = r_io_cq8_iv;
assign pcie_user_logic_rst = r_pcie_user_logic_rst;
assign nvme_csts_shst = r_nvme_csts_shst;
assign nvme_csts_rdy = r_nvme_csts_rdy;
assign hcmd_table_rd_addr = r_s_axi_araddr[12:2];
assign hcmd_sq_rd_en = r_hcmd_sq_rd_en;
assign hcmd_cq_wr1_en = r_hcmd_cq_wr1_en;
assign hcmd_cq_wr1_data0 = ((r_cql_type[1] | r_cql_type[0]) == 1) ? {r_cpl_status[12:0], r_cpl_sq_qid, r_cpl_cid[15:7], r_hcmd_slot_tag, r_cql_type}
: {r_cpl_status[12:0], r_cpl_sq_qid, r_cpl_cid, r_cql_type};
assign hcmd_cq_wr1_data1 = {1'b0, r_cpl_specific[31:0], r_cpl_status[14:13]};
assign dma_cmd_wr_en = r_dma_cmd_wr_en;
assign dma_cmd_wr_data0 = {r_dma_cmd_type, r_dma_cmd_dir, r_dma_cmd_hcmd_slot_tag, r_dma_cmd_dev_len, r_dma_cmd_dev_addr};
assign dma_cmd_wr_data1 = {7'b0, r_dma_cmd_4k_offset, r_dma_cmd_pcie_addr};
always @ (posedge s_axi_aclk)
begin
r_pcie_link_up <= pcie_link_up;
r_cfg_command <= cfg_command;
r_cfg_interrupt_mmenable <= cfg_interrupt_mmenable;
r_cfg_interrupt_msienable <= cfg_interrupt_msienable;
r_cfg_interrupt_msixenable <= cfg_interrupt_msixenable;
r_nvme_cc_en <= nvme_cc_en;
r_nvme_cc_shn <= nvme_cc_shn;
r_m0_axi_bresp_err <= m0_axi_bresp_err;
r_m0_axi_bresp_err_d1 <= r_m0_axi_bresp_err;
r_m0_axi_bresp_err_d2 <= r_m0_axi_bresp_err_d1;
r_m0_axi_rresp_err <= m0_axi_rresp_err;
r_m0_axi_rresp_err_d1 <= r_m0_axi_rresp_err;
r_m0_axi_rresp_err_d2 <= r_m0_axi_rresp_err_d1;
r_pcie_mreq_err <= pcie_mreq_err;
r_pcie_cpld_err <= pcie_cpld_err;
r_pcie_cpld_len_err <= pcie_cpld_len_err;
end
always @ (posedge s_axi_aclk)
begin
r_irq_req[0] <= (pcie_link_up ^ r_pcie_link_up);
r_irq_req[1] <= (cfg_command[2] ^ r_cfg_command[2]);
r_irq_req[2] <= (cfg_command[10] ^ r_cfg_command[10]);
r_irq_req[3] <= (cfg_interrupt_msienable ^ r_cfg_interrupt_msienable);
r_irq_req[4] <= (cfg_interrupt_msixenable ^ r_cfg_interrupt_msixenable);
r_irq_req[5] <= (nvme_cc_en ^ r_nvme_cc_en);
r_irq_req[6] <= (nvme_cc_shn != r_nvme_cc_shn);
r_irq_req[7] <= (r_m0_axi_bresp_err_d1 ^ r_m0_axi_bresp_err_d2);
r_irq_req[8] <= (r_m0_axi_rresp_err_d1 ^ r_m0_axi_rresp_err_d2);
r_irq_req[9] <= (pcie_mreq_err ^ r_pcie_mreq_err);
r_irq_req[10] <= (pcie_cpld_err ^ r_pcie_cpld_err);
r_irq_req[11] <= (pcie_cpld_len_err ^ r_pcie_cpld_len_err);
r_irq_assert <= (r_irq_set != 0);
end
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0)
cur_wr_state <= S_WR_IDLE;
else
cur_wr_state <= next_wr_state;
end
always @ (*)
begin
case(cur_wr_state)
S_WR_IDLE: begin
if(s_axi_awvalid == 1)
next_wr_state <= S_AW_VAILD;
else
next_wr_state <= S_WR_IDLE;
end
S_AW_VAILD: begin
next_wr_state <= S_W_READY;
end
S_W_READY: begin
if(s_axi_wvalid == 1)
next_wr_state <= S_B_VALID;
else
next_wr_state <= S_W_READY;
end
S_B_VALID: begin
if(s_axi_bready == 1) begin
if(r_awaddr_hcmd_cq_wr1_en == 1)
next_wr_state <= S_WAIT_CQ_RDY;
else if(r_awaddr_dma_cmd_wr_en == 1)
next_wr_state <= S_WAIT_DMA_RDY;
else
next_wr_state <= S_WR_IDLE;
end
else
next_wr_state <= S_B_VALID;
end
S_WAIT_CQ_RDY: begin
if(hcmd_cq_wr1_rdy_n == 1)
next_wr_state <= S_WAIT_CQ_RDY;
else
next_wr_state <= S_WR_CQ;
end
S_WR_CQ: begin
next_wr_state <= S_WR_IDLE;
end
S_WAIT_DMA_RDY: begin
if(dma_cmd_wr_rdy_n == 1)
next_wr_state <= S_WAIT_DMA_RDY;
else
next_wr_state <= S_WR_DMA;
end
S_WR_DMA: begin
next_wr_state <= S_WR_IDLE;
end
default: begin
next_wr_state <= S_WR_IDLE;
end
endcase
end
always @ (posedge s_axi_aclk)
begin
case(cur_wr_state)
S_WR_IDLE: begin
r_s_axi_awaddr[15:2] <= s_axi_awaddr[15:2];
end
S_AW_VAILD: begin
r_awaddr_cntl_reg_en <= (r_s_axi_awaddr[15:8] == 8'h0);
// r_awaddr_pcie_reg_en <= (r_s_axi_awaddr[15:8] == 8'h1);
r_awaddr_nvme_reg_en <= (r_s_axi_awaddr[15:8] == 8'h2);
r_awaddr_nvme_fifo_en <= (r_s_axi_awaddr[15:8] == 8'h3);
r_awaddr_hcmd_cq_wr1_en <= (r_s_axi_awaddr[15:2] == 14'hC3);
r_awaddr_dma_cmd_wr_en <= (r_s_axi_awaddr[15:2] == 14'hC7);
end
S_W_READY: begin
r_wdata <= s_axi_wdata;
end
S_B_VALID: begin
end
S_WAIT_CQ_RDY: begin
end
S_WR_CQ: begin
end
S_WAIT_DMA_RDY: begin
end
S_WR_DMA: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_wr_state)
S_WR_IDLE: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_AW_VAILD: begin
r_s_axi_awready <= 1;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_W_READY: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 1;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_B_VALID: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 1;
r_s_axi_bresp <= `D_AXI_RESP_OKAY;
r_cntl_reg_en <= r_awaddr_cntl_reg_en;
// r_pcie_reg_en <= r_awaddr_pcie_reg_en;
r_nvme_reg_en <= r_awaddr_nvme_reg_en;
r_nvme_fifo_en <= r_awaddr_nvme_fifo_en;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_WAIT_CQ_RDY: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_WR_CQ: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 1;
r_dma_cmd_wr_en <= 0;
end
S_WAIT_DMA_RDY: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_WR_DMA: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 1;
end
default: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
endcase
end
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0) begin
r_irq_mask <= 0;
end
else begin
if(r_cntl_reg_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h01: r_irq_mask <= r_wdata[11:0];
endcase
end
end
end
always @ (posedge s_axi_aclk)
begin
if(r_cntl_reg_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h00: begin
r_pcie_user_logic_rst <= r_wdata[0];
r_irq_clear <= 0;
end
6'h02: begin
r_pcie_user_logic_rst <= 0;
r_irq_clear <= r_wdata[11:0];
end
default: begin
r_pcie_user_logic_rst <= 0;
r_irq_clear <= 0;
end
endcase
end
else begin
r_pcie_user_logic_rst <= 0;
r_irq_clear <= 0;
end
end
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0) begin
r_irq_set <= 0;
end
else begin
r_irq_set <= (r_irq_set | r_irq_req) & (~r_irq_clear & r_irq_mask);
end
end
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0) begin
r_sq_valid <= 0;
r_cq_valid <= 0;
r_io_cq_irq_en <= 0;
r_nvme_csts_shst <= 0;
r_nvme_csts_rdy <= 0;
end
else begin
if(r_nvme_reg_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h00: begin
r_nvme_csts_shst <= r_wdata[6:5];
r_nvme_csts_rdy <= r_wdata[4];
end
6'h07: begin
r_io_cq_irq_en[0] <= r_wdata[2];
r_sq_valid[0] <= r_wdata[1];
r_cq_valid[0] <= r_wdata[0];
end
6'h09: begin
r_sq_valid[1] <= r_wdata[15];
end
6'h0B: begin
r_sq_valid[2] <= r_wdata[15];
end
6'h0D: begin
r_sq_valid[3] <= r_wdata[15];
end
6'h0F: begin
r_sq_valid[4] <= r_wdata[15];
end
6'h11: begin
r_sq_valid[5] <= r_wdata[15];
end
6'h13: begin
r_sq_valid[6] <= r_wdata[15];
end
6'h15: begin
r_sq_valid[7] <= r_wdata[15];
end
6'h17: begin
r_sq_valid[8] <= r_wdata[15];
end
6'h19: begin
r_io_cq_irq_en[1] <= r_wdata[19];
r_cq_valid[1] <= r_wdata[15];
end
6'h1B: begin
r_io_cq_irq_en[2] <= r_wdata[19];
r_cq_valid[2] <= r_wdata[15];
end
6'h1D: begin
r_io_cq_irq_en[3] <= r_wdata[19];
r_cq_valid[3] <= r_wdata[15];
end
6'h1F: begin
r_io_cq_irq_en[4] <= r_wdata[19];
r_cq_valid[4] <= r_wdata[15];
end
6'h21: begin
r_io_cq_irq_en[5] <= r_wdata[19];
r_cq_valid[5] <= r_wdata[15];
end
6'h23: begin
r_io_cq_irq_en[6] <= r_wdata[19];
r_cq_valid[6] <= r_wdata[15];
end
6'h25: begin
r_io_cq_irq_en[7] <= r_wdata[19];
r_cq_valid[7] <= r_wdata[15];
end
6'h27: begin
r_io_cq_irq_en[8] <= r_wdata[19];
r_cq_valid[8] <= r_wdata[15];
end
endcase
end
end
end
always @ (posedge s_axi_aclk)
begin
if(r_nvme_reg_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h08: begin
r_io_sq1_bs_addr[31:2] <= r_wdata[31:2];
end
6'h09: begin
r_io_sq1_size <= r_wdata[31:24];
r_io_sq1_cq_vec <= r_wdata[19:16];
r_io_sq1_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h0A: begin
r_io_sq2_bs_addr[31:2] <= r_wdata[31:2];
end
6'h0B: begin
r_io_sq2_size <= r_wdata[31:24];
r_io_sq2_cq_vec <= r_wdata[19:16];
r_io_sq2_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h0C: begin
r_io_sq3_bs_addr[31:2] <= r_wdata[31:2];
end
6'h0D: begin
r_io_sq3_size <= r_wdata[31:24];
r_io_sq3_cq_vec <= r_wdata[19:16];
r_io_sq3_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h0E: begin
r_io_sq4_bs_addr[31:2] <= r_wdata[31:2];
end
6'h0F: begin
r_io_sq4_size <= r_wdata[31:24];
r_io_sq4_cq_vec <= r_wdata[19:16];
r_io_sq4_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h10: begin
r_io_sq5_bs_addr[31:2] <= r_wdata[31:2];
end
6'h11: begin
r_io_sq5_size <= r_wdata[31:24];
r_io_sq5_cq_vec <= r_wdata[19:16];
r_io_sq5_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h12: begin
r_io_sq6_bs_addr[31:2] <= r_wdata[31:2];
end
6'h13: begin
r_io_sq6_size <= r_wdata[31:24];
r_io_sq6_cq_vec <= r_wdata[19:16];
r_io_sq6_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h14: begin
r_io_sq7_bs_addr[31:2] <= r_wdata[31:2];
end
6'h15: begin
r_io_sq7_size <= r_wdata[31:24];
r_io_sq7_cq_vec <= r_wdata[19:16];
r_io_sq7_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h16: begin
r_io_sq8_bs_addr[31:2] <= r_wdata[31:2];
end
6'h17: begin
r_io_sq8_size <= r_wdata[31:24];
r_io_sq8_cq_vec <= r_wdata[19:16];
r_io_sq8_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h18: begin
r_io_cq1_bs_addr[31:2] <= r_wdata[31:2];
end
6'h19: begin
r_io_cq1_size <= r_wdata[31:24];
r_io_cq1_iv <= r_wdata[18:16];
r_io_cq1_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h1A: begin
r_io_cq2_bs_addr[31:2] <= r_wdata[31:2];
end
6'h1B: begin
r_io_cq2_size <= r_wdata[31:24];
r_io_cq2_iv <= r_wdata[18:16];
r_io_cq2_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h1C: begin
r_io_cq3_bs_addr[31:2] <= r_wdata[31:2];
end
6'h1D: begin
r_io_cq3_size <= r_wdata[31:24];
r_io_cq3_iv <= r_wdata[18:16];
r_io_cq3_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h1E: begin
r_io_cq4_bs_addr[31:2] <= r_wdata[31:2];
end
6'h1F: begin
r_io_cq4_size <= r_wdata[31:24];
r_io_cq4_iv <= r_wdata[18:16];
r_io_cq4_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h20: begin
r_io_cq5_bs_addr[31:2] <= r_wdata[31:2];
end
6'h21: begin
r_io_cq5_size <= r_wdata[31:24];
r_io_cq5_iv <= r_wdata[18:16];
r_io_cq5_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h22: begin
r_io_cq6_bs_addr[31:2] <= r_wdata[31:2];
end
6'h23: begin
r_io_cq6_size <= r_wdata[31:24];
r_io_cq6_iv <= r_wdata[18:16];
r_io_cq6_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h24: begin
r_io_cq7_bs_addr[31:2] <= r_wdata[31:2];
end
6'h25: begin
r_io_cq7_size <= r_wdata[31:24];
r_io_cq7_iv <= r_wdata[18:16];
r_io_cq7_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h26: begin
r_io_cq8_bs_addr[31:2] <= r_wdata[31:2];
end
6'h27: begin
r_io_cq8_size <= r_wdata[31:24];
r_io_cq8_iv <= r_wdata[18:16];
r_io_cq8_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
endcase
end
end
always @ (posedge s_axi_aclk)
begin
if(r_nvme_fifo_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h01: {r_cpl_sq_qid, r_cpl_cid} <= r_wdata[19:0];
6'h02: r_cpl_specific <= r_wdata;
6'h03: {r_cpl_status, r_cql_type, r_hcmd_slot_tag} <= {r_wdata[31:17], r_wdata[15:14], r_wdata[6:0]};
6'h04: r_dma_cmd_dev_addr <= r_wdata[31:2];
6'h05: r_dma_cmd_pcie_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[C_PCIE_ADDR_WIDTH-1-32:0];
6'h06: r_dma_cmd_pcie_addr[31:2] <= r_wdata[31:2];
6'h07: begin
r_dma_cmd_type <= r_wdata[31];
r_dma_cmd_dir <= r_wdata[30];
r_dma_cmd_hcmd_slot_tag <= r_wdata[29:23];
r_dma_cmd_4k_offset <= r_wdata[22:14];
r_dma_cmd_dev_len <= r_wdata[12:2];
end
endcase
end
end
//////////////////////////////////////////////////////////////////////////////////////
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0)
cur_rd_state <= S_RD_IDLE;
else
cur_rd_state <= next_rd_state;
end
always @ (*)
begin
case(cur_rd_state)
S_RD_IDLE: begin
if(s_axi_arvalid == 1)
next_rd_state <= S_AR_VAILD;
else
next_rd_state <= S_RD_IDLE;
end
S_AR_VAILD: begin
next_rd_state <= S_AR_REG;
end
S_AR_REG: begin
if(r_araddr_hcmd_sq_rd_en == 1 || r_araddr_hcmd_table_rd_en == 1)
next_rd_state <= S_BRAM_READ;
else
next_rd_state <= S_R_READY;
end
S_BRAM_READ: begin
next_rd_state <= S_R_READY;
end
S_R_READY: begin
if(s_axi_rready == 1)
next_rd_state <= S_RD_IDLE;
else
next_rd_state <= S_R_READY;
end
default: begin
next_rd_state <= S_RD_IDLE;
end
endcase
end
always @ (posedge s_axi_aclk)
begin
case(cur_rd_state)
S_RD_IDLE: begin
r_s_axi_araddr <= s_axi_araddr[15:2];
end
S_AR_VAILD: begin
r_araddr_cntl_reg_en <= (r_s_axi_araddr[15:8] == 8'h0);
r_araddr_pcie_reg_en <= (r_s_axi_araddr[15:8] == 8'h1);
r_araddr_nvme_reg_en <= (r_s_axi_araddr[15:8] == 8'h2);
r_araddr_nvme_fifo_en <= (r_s_axi_araddr[15:8] == 8'h3);
r_araddr_hcmd_table_rd_en <= (r_s_axi_araddr[15:13] == 3'h1);
r_araddr_hcmd_sq_rd_en <= (r_s_axi_araddr[15:2] == 14'hC0) & hcmd_sq_empty_n;
end
S_AR_REG: begin
case({r_araddr_nvme_fifo_en, r_araddr_nvme_reg_en, r_araddr_pcie_reg_en, r_araddr_cntl_reg_en}) // synthesis parallel_case full_case
4'b0001: r_rdata <= r_cntl_reg_rdata;
4'b0010: r_rdata <= r_pcie_reg_rdata;
4'b0100: r_rdata <= r_nvme_reg_rdata;
4'b1000: r_rdata <= r_nvme_fifo_rdata;
endcase
end
S_BRAM_READ: begin
case({r_araddr_hcmd_table_rd_en, r_araddr_hcmd_sq_rd_en}) // synthesis parallel_case full_case
2'b01: r_rdata <= {1'b1, 7'b0, hcmd_sq_rd_data[18:11], 1'b0, hcmd_sq_rd_data[10:4], 4'b0, hcmd_sq_rd_data[3:0]};
2'b10: r_rdata <= hcmd_table_rd_data;
endcase
end
S_R_READY: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_rd_state)
S_RD_IDLE: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= 0;
end
S_AR_VAILD: begin
r_s_axi_arready <= 1;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= 0;
end
S_AR_REG: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= 0;
end
S_BRAM_READ: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= r_araddr_hcmd_sq_rd_en;
end
S_R_READY: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 1;
r_s_axi_rdata <= r_rdata;
r_s_axi_rresp <= `D_AXI_RESP_OKAY;
r_hcmd_sq_rd_en <= 0;
end
default: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= 0;
end
endcase
end
always @ (*)
begin
case(r_s_axi_araddr[7:2]) // synthesis parallel_case full_case
6'h01: r_cntl_reg_rdata <= {20'b0, r_irq_mask};
6'h03: r_cntl_reg_rdata <= {20'b0, r_irq_set};
endcase
end
always @ (*)
begin
case(r_s_axi_araddr[7:2]) // synthesis parallel_case full_case
6'h00: r_pcie_reg_rdata <= {23'b0, r_pcie_link_up, 2'b0, pl_ltssm_state};
6'h01: r_pcie_reg_rdata <= {25'b0, r_cfg_interrupt_mmenable, ~r_cfg_command[10], r_cfg_interrupt_msixenable, r_cfg_interrupt_msienable, r_cfg_command[2]};
endcase
end
always @ (*)
begin
case(r_s_axi_araddr[7:2]) // synthesis parallel_case full_case
6'h00: r_nvme_reg_rdata <= {25'b0, r_nvme_csts_shst, r_nvme_csts_rdy, 1'b0, r_nvme_cc_shn, r_nvme_cc_en};
6'h01: r_nvme_reg_rdata <= {dma_tx_done_cnt, dma_rx_done_cnt, dma_tx_direct_done_cnt, dma_rx_direct_done_cnt};
6'h07: r_nvme_reg_rdata <= {19'b0, r_io_cq_irq_en[0], r_sq_valid[0], r_cq_valid[0]};
6'h08: r_nvme_reg_rdata <= {r_io_sq1_bs_addr[31:2], 2'b0};
6'h09: r_nvme_reg_rdata <= {r_io_sq1_size, 4'b0, r_io_sq1_cq_vec, r_sq_valid[1], 11'b0, r_io_sq1_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h0A: r_nvme_reg_rdata <= {r_io_sq2_bs_addr[31:2], 2'b0};
6'h0B: r_nvme_reg_rdata <= {r_io_sq2_size, 4'b0, r_io_sq2_cq_vec, r_sq_valid[2], 11'b0, r_io_sq2_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h0C: r_nvme_reg_rdata <= {r_io_sq3_bs_addr[31:2], 2'b0};
6'h0D: r_nvme_reg_rdata <= {r_io_sq3_size, 4'b0, r_io_sq3_cq_vec, r_sq_valid[3], 11'b0, r_io_sq3_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h0E: r_nvme_reg_rdata <= {r_io_sq4_bs_addr[31:2], 2'b0};
6'h0F: r_nvme_reg_rdata <= {r_io_sq4_size, 4'b0, r_io_sq4_cq_vec, r_sq_valid[4], 11'b0, r_io_sq4_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h10: r_nvme_reg_rdata <= {r_io_sq5_bs_addr[31:2], 2'b0};
6'h11: r_nvme_reg_rdata <= {r_io_sq5_size, 4'b0, r_io_sq5_cq_vec, r_sq_valid[5], 11'b0, r_io_sq5_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h12: r_nvme_reg_rdata <= {r_io_sq6_bs_addr[31:2], 2'b0};
6'h13: r_nvme_reg_rdata <= {r_io_sq6_size, 4'b0, r_io_sq6_cq_vec, r_sq_valid[6], 11'b0, r_io_sq6_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h14: r_nvme_reg_rdata <= {r_io_sq7_bs_addr[31:2], 2'b0};
6'h15: r_nvme_reg_rdata <= {r_io_sq7_size, 4'b0, r_io_sq7_cq_vec, r_sq_valid[7], 11'b0, r_io_sq7_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h16: r_nvme_reg_rdata <= {r_io_sq8_bs_addr[31:2], 2'b0};
6'h17: r_nvme_reg_rdata <= {r_io_sq8_size, 4'b0, r_io_sq8_cq_vec, r_sq_valid[8], 11'b0, r_io_sq8_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h18: r_nvme_reg_rdata <= {r_io_cq1_bs_addr[31:2], 2'b0};
6'h19: r_nvme_reg_rdata <= {r_io_cq1_size, 4'b0, r_io_cq_irq_en[1], r_io_cq1_iv, r_cq_valid[1], 11'b0, r_io_cq1_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h1A: r_nvme_reg_rdata <= {r_io_cq2_bs_addr[31:2], 2'b0};
6'h1B: r_nvme_reg_rdata <= {r_io_cq2_size, 4'b0, r_io_cq_irq_en[2], r_io_cq2_iv, r_cq_valid[2], 11'b0, r_io_cq2_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h1C: r_nvme_reg_rdata <= {r_io_cq3_bs_addr[31:2], 2'b0};
6'h1D: r_nvme_reg_rdata <= {r_io_cq3_size, 4'b0, r_io_cq_irq_en[3], r_io_cq3_iv, r_cq_valid[3], 11'b0, r_io_cq3_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h1E: r_nvme_reg_rdata <= {r_io_cq4_bs_addr[31:2], 2'b0};
6'h1F: r_nvme_reg_rdata <= {r_io_cq4_size, 4'b0, r_io_cq_irq_en[4], r_io_cq4_iv, r_cq_valid[4], 11'b0, r_io_cq4_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h20: r_nvme_reg_rdata <= {r_io_cq5_bs_addr[31:2], 2'b0};
6'h21: r_nvme_reg_rdata <= {r_io_cq5_size, 4'b0, r_io_cq_irq_en[5], r_io_cq5_iv, r_cq_valid[5], 11'b0, r_io_cq5_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h22: r_nvme_reg_rdata <= {r_io_cq6_bs_addr[31:2], 2'b0};
6'h23: r_nvme_reg_rdata <= {r_io_cq6_size, 4'b0, r_io_cq_irq_en[6], r_io_cq6_iv, r_cq_valid[6], 11'b0, r_io_cq6_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h24: r_nvme_reg_rdata <= {r_io_cq7_bs_addr[31:2], 2'b0};
6'h25: r_nvme_reg_rdata <= {r_io_cq7_size, 4'b0, r_io_cq_irq_en[7], r_io_cq7_iv, r_cq_valid[7], 11'b0, r_io_cq7_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h26: r_nvme_reg_rdata <= {r_io_cq8_bs_addr[31:2], 2'b0};
6'h27: r_nvme_reg_rdata <= {r_io_cq8_size, 4'b0, r_io_cq_irq_en[8], r_io_cq8_iv, r_cq_valid[8], 11'b0, r_io_cq8_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
endcase
end
always @ (*)
begin
case(r_s_axi_araddr[7:2]) // synthesis parallel_case full_case
6'h00: r_nvme_fifo_rdata <= 0;
6'h01: r_nvme_fifo_rdata <= {12'b0, r_cpl_sq_qid, r_cpl_cid};
6'h02: r_nvme_fifo_rdata <= r_cpl_specific;
6'h03: r_nvme_fifo_rdata <= {r_cpl_status, 1'b0, r_cql_type, 7'b0, r_hcmd_slot_tag};
6'h04: r_nvme_fifo_rdata <= {r_dma_cmd_dev_addr, 2'b0};
6'h05: r_nvme_fifo_rdata <= {28'b0, r_dma_cmd_pcie_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h06: r_nvme_fifo_rdata <= {r_dma_cmd_pcie_addr[31:2], 2'b0};
6'h07: r_nvme_fifo_rdata <= {r_dma_cmd_type, r_dma_cmd_dir, r_dma_cmd_hcmd_slot_tag, r_dma_cmd_4k_offset, 1'b0, r_dma_cmd_dev_len, 2'b0};
endcase
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_axi.vh"
module s_axi_reg # (
parameter C_S_AXI_ADDR_WIDTH = 32,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_BASEADDR = 32'h80000000,
parameter C_S_AXI_HIGHADDR = 32'h80010000,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
////////////////////////////////////////////////////////////////
//AXI4-lite slave interface signals
input s_axi_aclk,
input s_axi_aresetn,
//Write address channel
input s_axi_awvalid,
output s_axi_awready,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
//Write data channel
input s_axi_wvalid,
output s_axi_wready,
input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb,
//Write response channel
output s_axi_bvalid,
input s_axi_bready,
output [1:0] s_axi_bresp,
//Read address channel
input s_axi_arvalid,
output s_axi_arready,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [2:0] s_axi_arprot,
//Read data channel
output s_axi_rvalid,
input s_axi_rready,
output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
input m0_axi_bresp_err,
input m0_axi_rresp_err,
output dev_irq_assert,
output pcie_user_logic_rst,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst,
output nvme_csts_rdy,
output [8:0] sq_valid,
output [7:0] io_sq1_size,
output [7:0] io_sq2_size,
output [7:0] io_sq3_size,
output [7:0] io_sq4_size,
output [7:0] io_sq5_size,
output [7:0] io_sq6_size,
output [7:0] io_sq7_size,
output [7:0] io_sq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
output [3:0] io_sq1_cq_vec,
output [3:0] io_sq2_cq_vec,
output [3:0] io_sq3_cq_vec,
output [3:0] io_sq4_cq_vec,
output [3:0] io_sq5_cq_vec,
output [3:0] io_sq6_cq_vec,
output [3:0] io_sq7_cq_vec,
output [3:0] io_sq8_cq_vec,
output [8:0] cq_valid,
output [7:0] io_cq1_size,
output [7:0] io_cq2_size,
output [7:0] io_cq3_size,
output [7:0] io_cq4_size,
output [7:0] io_cq5_size,
output [7:0] io_cq6_size,
output [7:0] io_cq7_size,
output [7:0] io_cq8_size,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
output [8:0] io_cq_irq_en,
output [2:0] io_cq1_iv,
output [2:0] io_cq2_iv,
output [2:0] io_cq3_iv,
output [2:0] io_cq4_iv,
output [2:0] io_cq5_iv,
output [2:0] io_cq6_iv,
output [2:0] io_cq7_iv,
output [2:0] io_cq8_iv,
output hcmd_sq_rd_en,
input [18:0] hcmd_sq_rd_data,
input hcmd_sq_empty_n,
output [10:0] hcmd_table_rd_addr,
input [31:0] hcmd_table_rd_data,
output hcmd_cq_wr1_en,
output [34:0] hcmd_cq_wr1_data0,
output [34:0] hcmd_cq_wr1_data1,
input hcmd_cq_wr1_rdy_n,
output dma_cmd_wr_en,
output [49:0] dma_cmd_wr_data0,
output [49:0] dma_cmd_wr_data1,
input dma_cmd_wr_rdy_n,
input [7:0] dma_rx_direct_done_cnt,
input [7:0] dma_tx_direct_done_cnt,
input [7:0] dma_rx_done_cnt,
input [7:0] dma_tx_done_cnt,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable
);
localparam S_WR_IDLE = 8'b00000001;
localparam S_AW_VAILD = 8'b00000010;
localparam S_W_READY = 8'b00000100;
localparam S_B_VALID = 8'b00001000;
localparam S_WAIT_CQ_RDY = 8'b00010000;
localparam S_WR_CQ = 8'b00100000;
localparam S_WAIT_DMA_RDY = 8'b01000000;
localparam S_WR_DMA = 8'b10000000;
reg [7:0] cur_wr_state;
reg [7:0] next_wr_state;
localparam S_RD_IDLE = 5'b00001;
localparam S_AR_VAILD = 5'b00010;
localparam S_AR_REG = 5'b00100;
localparam S_BRAM_READ = 5'b01000;
localparam S_R_READY = 5'b10000;
reg [4:0] cur_rd_state;
reg [4:0] next_rd_state;
reg r_s_axi_awready;
reg [15:2] r_s_axi_awaddr;
reg r_s_axi_wready;
reg r_s_axi_bvalid;
reg [1:0] r_s_axi_bresp;
reg r_s_axi_arready;
reg [15:2] r_s_axi_araddr;
reg r_s_axi_rvalid;
reg [C_S_AXI_DATA_WIDTH-1:0] r_s_axi_rdata;
reg [1:0] r_s_axi_rresp;
reg r_irq_assert;
reg [11:0] r_irq_req;
reg [11:0] r_irq_mask;
reg [11:0] r_irq_clear;
reg [11:0] r_irq_set;
reg r_pcie_user_logic_rst;
reg [1:0] r_nvme_csts_shst;
reg r_nvme_csts_rdy;
reg [8:0] r_sq_valid;
reg [7:0] r_io_sq1_size;
reg [7:0] r_io_sq2_size;
reg [7:0] r_io_sq3_size;
reg [7:0] r_io_sq4_size;
reg [7:0] r_io_sq5_size;
reg [7:0] r_io_sq6_size;
reg [7:0] r_io_sq7_size;
reg [7:0] r_io_sq8_size;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq1_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq2_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq3_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq4_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq5_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq6_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq7_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq8_bs_addr;
reg [3:0] r_io_sq1_cq_vec;
reg [3:0] r_io_sq2_cq_vec;
reg [3:0] r_io_sq3_cq_vec;
reg [3:0] r_io_sq4_cq_vec;
reg [3:0] r_io_sq5_cq_vec;
reg [3:0] r_io_sq6_cq_vec;
reg [3:0] r_io_sq7_cq_vec;
reg [3:0] r_io_sq8_cq_vec;
reg [8:0] r_cq_valid;
reg [7:0] r_io_cq1_size;
reg [7:0] r_io_cq2_size;
reg [7:0] r_io_cq3_size;
reg [7:0] r_io_cq4_size;
reg [7:0] r_io_cq5_size;
reg [7:0] r_io_cq6_size;
reg [7:0] r_io_cq7_size;
reg [7:0] r_io_cq8_size;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq1_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq2_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq3_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq4_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq5_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq6_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq7_bs_addr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq8_bs_addr;
reg [8:0] r_io_cq_irq_en;
reg [2:0] r_io_cq1_iv;
reg [2:0] r_io_cq2_iv;
reg [2:0] r_io_cq3_iv;
reg [2:0] r_io_cq4_iv;
reg [2:0] r_io_cq5_iv;
reg [2:0] r_io_cq6_iv;
reg [2:0] r_io_cq7_iv;
reg [2:0] r_io_cq8_iv;
reg [1:0] r_cql_type;
reg [3:0] r_cpl_sq_qid;
reg [15:0] r_cpl_cid;
reg [6:0] r_hcmd_slot_tag;
reg [14:0] r_cpl_status;
reg [31:0] r_cpl_specific;
reg r_dma_cmd_type;
reg r_dma_cmd_dir;
reg [6:0] r_dma_cmd_hcmd_slot_tag;
reg [31:2] r_dma_cmd_dev_addr;
reg [12:2] r_dma_cmd_dev_len;
reg [8:0] r_dma_cmd_4k_offset;
reg [C_PCIE_ADDR_WIDTH-1:2] r_dma_cmd_pcie_addr;
reg r_hcmd_cq_wr1_en;
reg r_dma_cmd_wr_en;
reg r_hcmd_sq_rd_en;
reg [31:0] r_wdata;
reg r_awaddr_cntl_reg_en;
//reg r_awaddr_pcie_reg_en;
reg r_awaddr_nvme_reg_en;
reg r_awaddr_nvme_fifo_en;
reg r_awaddr_hcmd_cq_wr1_en;
reg r_awaddr_dma_cmd_wr_en;
reg r_cntl_reg_en;
//reg r_pcie_reg_en;
reg r_nvme_reg_en;
reg r_nvme_fifo_en;
reg [31:0] r_rdata;
reg r_araddr_cntl_reg_en;
reg r_araddr_pcie_reg_en;
reg r_araddr_nvme_reg_en;
reg r_araddr_nvme_fifo_en;
reg r_araddr_hcmd_table_rd_en;
reg r_araddr_hcmd_sq_rd_en;
reg [31:0] r_cntl_reg_rdata;
reg [31:0] r_pcie_reg_rdata;
reg [31:0] r_nvme_reg_rdata;
reg [31:0] r_nvme_fifo_rdata;
reg r_pcie_link_up;
reg [15:0] r_cfg_command;
reg [2:0] r_cfg_interrupt_mmenable;
reg r_cfg_interrupt_msienable;
reg r_cfg_interrupt_msixenable;
reg r_nvme_cc_en;
reg [1:0] r_nvme_cc_shn;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_bresp_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_bresp_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_bresp_err_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_rresp_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_rresp_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_m0_axi_rresp_err_d2;
reg r_pcie_mreq_err;
reg r_pcie_cpld_err;
reg r_pcie_cpld_len_err;
assign s_axi_awready = r_s_axi_awready;
assign s_axi_wready = r_s_axi_wready;
assign s_axi_bvalid = r_s_axi_bvalid;
assign s_axi_bresp = r_s_axi_bresp;
assign s_axi_arready = r_s_axi_arready;
assign s_axi_rvalid = r_s_axi_rvalid;
assign s_axi_rdata = r_s_axi_rdata;
assign s_axi_rresp = r_s_axi_rresp;
assign dev_irq_assert = r_irq_assert;
assign sq_valid = r_sq_valid;
assign io_sq1_size = r_io_sq1_size;
assign io_sq2_size = r_io_sq2_size;
assign io_sq3_size = r_io_sq3_size;
assign io_sq4_size = r_io_sq4_size;
assign io_sq5_size = r_io_sq5_size;
assign io_sq6_size = r_io_sq6_size;
assign io_sq7_size = r_io_sq7_size;
assign io_sq8_size = r_io_sq8_size;
assign io_sq1_bs_addr = r_io_sq1_bs_addr;
assign io_sq2_bs_addr = r_io_sq2_bs_addr;
assign io_sq3_bs_addr = r_io_sq3_bs_addr;
assign io_sq4_bs_addr = r_io_sq4_bs_addr;
assign io_sq5_bs_addr = r_io_sq5_bs_addr;
assign io_sq6_bs_addr = r_io_sq6_bs_addr;
assign io_sq7_bs_addr = r_io_sq7_bs_addr;
assign io_sq8_bs_addr = r_io_sq8_bs_addr;
assign io_sq1_cq_vec = r_io_sq1_cq_vec;
assign io_sq2_cq_vec = r_io_sq2_cq_vec;
assign io_sq3_cq_vec = r_io_sq3_cq_vec;
assign io_sq4_cq_vec = r_io_sq4_cq_vec;
assign io_sq5_cq_vec = r_io_sq5_cq_vec;
assign io_sq6_cq_vec = r_io_sq6_cq_vec;
assign io_sq7_cq_vec = r_io_sq7_cq_vec;
assign io_sq8_cq_vec = r_io_sq8_cq_vec;
assign cq_valid = r_cq_valid;
assign io_cq1_size = r_io_cq1_size;
assign io_cq2_size = r_io_cq2_size;
assign io_cq3_size = r_io_cq3_size;
assign io_cq4_size = r_io_cq4_size;
assign io_cq5_size = r_io_cq5_size;
assign io_cq6_size = r_io_cq6_size;
assign io_cq7_size = r_io_cq7_size;
assign io_cq8_size = r_io_cq8_size;
assign io_cq1_bs_addr = r_io_cq1_bs_addr;
assign io_cq2_bs_addr = r_io_cq2_bs_addr;
assign io_cq3_bs_addr = r_io_cq3_bs_addr;
assign io_cq4_bs_addr = r_io_cq4_bs_addr;
assign io_cq5_bs_addr = r_io_cq5_bs_addr;
assign io_cq6_bs_addr = r_io_cq6_bs_addr;
assign io_cq7_bs_addr = r_io_cq7_bs_addr;
assign io_cq8_bs_addr = r_io_cq8_bs_addr;
assign io_cq_irq_en = r_io_cq_irq_en;
assign io_cq1_iv = r_io_cq1_iv;
assign io_cq2_iv = r_io_cq2_iv;
assign io_cq3_iv = r_io_cq3_iv;
assign io_cq4_iv = r_io_cq4_iv;
assign io_cq5_iv = r_io_cq5_iv;
assign io_cq6_iv = r_io_cq6_iv;
assign io_cq7_iv = r_io_cq7_iv;
assign io_cq8_iv = r_io_cq8_iv;
assign pcie_user_logic_rst = r_pcie_user_logic_rst;
assign nvme_csts_shst = r_nvme_csts_shst;
assign nvme_csts_rdy = r_nvme_csts_rdy;
assign hcmd_table_rd_addr = r_s_axi_araddr[12:2];
assign hcmd_sq_rd_en = r_hcmd_sq_rd_en;
assign hcmd_cq_wr1_en = r_hcmd_cq_wr1_en;
assign hcmd_cq_wr1_data0 = ((r_cql_type[1] | r_cql_type[0]) == 1) ? {r_cpl_status[12:0], r_cpl_sq_qid, r_cpl_cid[15:7], r_hcmd_slot_tag, r_cql_type}
: {r_cpl_status[12:0], r_cpl_sq_qid, r_cpl_cid, r_cql_type};
assign hcmd_cq_wr1_data1 = {1'b0, r_cpl_specific[31:0], r_cpl_status[14:13]};
assign dma_cmd_wr_en = r_dma_cmd_wr_en;
assign dma_cmd_wr_data0 = {r_dma_cmd_type, r_dma_cmd_dir, r_dma_cmd_hcmd_slot_tag, r_dma_cmd_dev_len, r_dma_cmd_dev_addr};
assign dma_cmd_wr_data1 = {7'b0, r_dma_cmd_4k_offset, r_dma_cmd_pcie_addr};
always @ (posedge s_axi_aclk)
begin
r_pcie_link_up <= pcie_link_up;
r_cfg_command <= cfg_command;
r_cfg_interrupt_mmenable <= cfg_interrupt_mmenable;
r_cfg_interrupt_msienable <= cfg_interrupt_msienable;
r_cfg_interrupt_msixenable <= cfg_interrupt_msixenable;
r_nvme_cc_en <= nvme_cc_en;
r_nvme_cc_shn <= nvme_cc_shn;
r_m0_axi_bresp_err <= m0_axi_bresp_err;
r_m0_axi_bresp_err_d1 <= r_m0_axi_bresp_err;
r_m0_axi_bresp_err_d2 <= r_m0_axi_bresp_err_d1;
r_m0_axi_rresp_err <= m0_axi_rresp_err;
r_m0_axi_rresp_err_d1 <= r_m0_axi_rresp_err;
r_m0_axi_rresp_err_d2 <= r_m0_axi_rresp_err_d1;
r_pcie_mreq_err <= pcie_mreq_err;
r_pcie_cpld_err <= pcie_cpld_err;
r_pcie_cpld_len_err <= pcie_cpld_len_err;
end
always @ (posedge s_axi_aclk)
begin
r_irq_req[0] <= (pcie_link_up ^ r_pcie_link_up);
r_irq_req[1] <= (cfg_command[2] ^ r_cfg_command[2]);
r_irq_req[2] <= (cfg_command[10] ^ r_cfg_command[10]);
r_irq_req[3] <= (cfg_interrupt_msienable ^ r_cfg_interrupt_msienable);
r_irq_req[4] <= (cfg_interrupt_msixenable ^ r_cfg_interrupt_msixenable);
r_irq_req[5] <= (nvme_cc_en ^ r_nvme_cc_en);
r_irq_req[6] <= (nvme_cc_shn != r_nvme_cc_shn);
r_irq_req[7] <= (r_m0_axi_bresp_err_d1 ^ r_m0_axi_bresp_err_d2);
r_irq_req[8] <= (r_m0_axi_rresp_err_d1 ^ r_m0_axi_rresp_err_d2);
r_irq_req[9] <= (pcie_mreq_err ^ r_pcie_mreq_err);
r_irq_req[10] <= (pcie_cpld_err ^ r_pcie_cpld_err);
r_irq_req[11] <= (pcie_cpld_len_err ^ r_pcie_cpld_len_err);
r_irq_assert <= (r_irq_set != 0);
end
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0)
cur_wr_state <= S_WR_IDLE;
else
cur_wr_state <= next_wr_state;
end
always @ (*)
begin
case(cur_wr_state)
S_WR_IDLE: begin
if(s_axi_awvalid == 1)
next_wr_state <= S_AW_VAILD;
else
next_wr_state <= S_WR_IDLE;
end
S_AW_VAILD: begin
next_wr_state <= S_W_READY;
end
S_W_READY: begin
if(s_axi_wvalid == 1)
next_wr_state <= S_B_VALID;
else
next_wr_state <= S_W_READY;
end
S_B_VALID: begin
if(s_axi_bready == 1) begin
if(r_awaddr_hcmd_cq_wr1_en == 1)
next_wr_state <= S_WAIT_CQ_RDY;
else if(r_awaddr_dma_cmd_wr_en == 1)
next_wr_state <= S_WAIT_DMA_RDY;
else
next_wr_state <= S_WR_IDLE;
end
else
next_wr_state <= S_B_VALID;
end
S_WAIT_CQ_RDY: begin
if(hcmd_cq_wr1_rdy_n == 1)
next_wr_state <= S_WAIT_CQ_RDY;
else
next_wr_state <= S_WR_CQ;
end
S_WR_CQ: begin
next_wr_state <= S_WR_IDLE;
end
S_WAIT_DMA_RDY: begin
if(dma_cmd_wr_rdy_n == 1)
next_wr_state <= S_WAIT_DMA_RDY;
else
next_wr_state <= S_WR_DMA;
end
S_WR_DMA: begin
next_wr_state <= S_WR_IDLE;
end
default: begin
next_wr_state <= S_WR_IDLE;
end
endcase
end
always @ (posedge s_axi_aclk)
begin
case(cur_wr_state)
S_WR_IDLE: begin
r_s_axi_awaddr[15:2] <= s_axi_awaddr[15:2];
end
S_AW_VAILD: begin
r_awaddr_cntl_reg_en <= (r_s_axi_awaddr[15:8] == 8'h0);
// r_awaddr_pcie_reg_en <= (r_s_axi_awaddr[15:8] == 8'h1);
r_awaddr_nvme_reg_en <= (r_s_axi_awaddr[15:8] == 8'h2);
r_awaddr_nvme_fifo_en <= (r_s_axi_awaddr[15:8] == 8'h3);
r_awaddr_hcmd_cq_wr1_en <= (r_s_axi_awaddr[15:2] == 14'hC3);
r_awaddr_dma_cmd_wr_en <= (r_s_axi_awaddr[15:2] == 14'hC7);
end
S_W_READY: begin
r_wdata <= s_axi_wdata;
end
S_B_VALID: begin
end
S_WAIT_CQ_RDY: begin
end
S_WR_CQ: begin
end
S_WAIT_DMA_RDY: begin
end
S_WR_DMA: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_wr_state)
S_WR_IDLE: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_AW_VAILD: begin
r_s_axi_awready <= 1;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_W_READY: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 1;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_B_VALID: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 1;
r_s_axi_bresp <= `D_AXI_RESP_OKAY;
r_cntl_reg_en <= r_awaddr_cntl_reg_en;
// r_pcie_reg_en <= r_awaddr_pcie_reg_en;
r_nvme_reg_en <= r_awaddr_nvme_reg_en;
r_nvme_fifo_en <= r_awaddr_nvme_fifo_en;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_WAIT_CQ_RDY: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_WR_CQ: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 1;
r_dma_cmd_wr_en <= 0;
end
S_WAIT_DMA_RDY: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
S_WR_DMA: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 1;
end
default: begin
r_s_axi_awready <= 0;
r_s_axi_wready <= 0;
r_s_axi_bvalid <= 0;
r_s_axi_bresp <= 0;
r_cntl_reg_en <= 0;
// r_pcie_reg_en <= 0;
r_nvme_reg_en <= 0;
r_nvme_fifo_en <= 0;
r_hcmd_cq_wr1_en <= 0;
r_dma_cmd_wr_en <= 0;
end
endcase
end
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0) begin
r_irq_mask <= 0;
end
else begin
if(r_cntl_reg_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h01: r_irq_mask <= r_wdata[11:0];
endcase
end
end
end
always @ (posedge s_axi_aclk)
begin
if(r_cntl_reg_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h00: begin
r_pcie_user_logic_rst <= r_wdata[0];
r_irq_clear <= 0;
end
6'h02: begin
r_pcie_user_logic_rst <= 0;
r_irq_clear <= r_wdata[11:0];
end
default: begin
r_pcie_user_logic_rst <= 0;
r_irq_clear <= 0;
end
endcase
end
else begin
r_pcie_user_logic_rst <= 0;
r_irq_clear <= 0;
end
end
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0) begin
r_irq_set <= 0;
end
else begin
r_irq_set <= (r_irq_set | r_irq_req) & (~r_irq_clear & r_irq_mask);
end
end
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0) begin
r_sq_valid <= 0;
r_cq_valid <= 0;
r_io_cq_irq_en <= 0;
r_nvme_csts_shst <= 0;
r_nvme_csts_rdy <= 0;
end
else begin
if(r_nvme_reg_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h00: begin
r_nvme_csts_shst <= r_wdata[6:5];
r_nvme_csts_rdy <= r_wdata[4];
end
6'h07: begin
r_io_cq_irq_en[0] <= r_wdata[2];
r_sq_valid[0] <= r_wdata[1];
r_cq_valid[0] <= r_wdata[0];
end
6'h09: begin
r_sq_valid[1] <= r_wdata[15];
end
6'h0B: begin
r_sq_valid[2] <= r_wdata[15];
end
6'h0D: begin
r_sq_valid[3] <= r_wdata[15];
end
6'h0F: begin
r_sq_valid[4] <= r_wdata[15];
end
6'h11: begin
r_sq_valid[5] <= r_wdata[15];
end
6'h13: begin
r_sq_valid[6] <= r_wdata[15];
end
6'h15: begin
r_sq_valid[7] <= r_wdata[15];
end
6'h17: begin
r_sq_valid[8] <= r_wdata[15];
end
6'h19: begin
r_io_cq_irq_en[1] <= r_wdata[19];
r_cq_valid[1] <= r_wdata[15];
end
6'h1B: begin
r_io_cq_irq_en[2] <= r_wdata[19];
r_cq_valid[2] <= r_wdata[15];
end
6'h1D: begin
r_io_cq_irq_en[3] <= r_wdata[19];
r_cq_valid[3] <= r_wdata[15];
end
6'h1F: begin
r_io_cq_irq_en[4] <= r_wdata[19];
r_cq_valid[4] <= r_wdata[15];
end
6'h21: begin
r_io_cq_irq_en[5] <= r_wdata[19];
r_cq_valid[5] <= r_wdata[15];
end
6'h23: begin
r_io_cq_irq_en[6] <= r_wdata[19];
r_cq_valid[6] <= r_wdata[15];
end
6'h25: begin
r_io_cq_irq_en[7] <= r_wdata[19];
r_cq_valid[7] <= r_wdata[15];
end
6'h27: begin
r_io_cq_irq_en[8] <= r_wdata[19];
r_cq_valid[8] <= r_wdata[15];
end
endcase
end
end
end
always @ (posedge s_axi_aclk)
begin
if(r_nvme_reg_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h08: begin
r_io_sq1_bs_addr[31:2] <= r_wdata[31:2];
end
6'h09: begin
r_io_sq1_size <= r_wdata[31:24];
r_io_sq1_cq_vec <= r_wdata[19:16];
r_io_sq1_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h0A: begin
r_io_sq2_bs_addr[31:2] <= r_wdata[31:2];
end
6'h0B: begin
r_io_sq2_size <= r_wdata[31:24];
r_io_sq2_cq_vec <= r_wdata[19:16];
r_io_sq2_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h0C: begin
r_io_sq3_bs_addr[31:2] <= r_wdata[31:2];
end
6'h0D: begin
r_io_sq3_size <= r_wdata[31:24];
r_io_sq3_cq_vec <= r_wdata[19:16];
r_io_sq3_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h0E: begin
r_io_sq4_bs_addr[31:2] <= r_wdata[31:2];
end
6'h0F: begin
r_io_sq4_size <= r_wdata[31:24];
r_io_sq4_cq_vec <= r_wdata[19:16];
r_io_sq4_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h10: begin
r_io_sq5_bs_addr[31:2] <= r_wdata[31:2];
end
6'h11: begin
r_io_sq5_size <= r_wdata[31:24];
r_io_sq5_cq_vec <= r_wdata[19:16];
r_io_sq5_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h12: begin
r_io_sq6_bs_addr[31:2] <= r_wdata[31:2];
end
6'h13: begin
r_io_sq6_size <= r_wdata[31:24];
r_io_sq6_cq_vec <= r_wdata[19:16];
r_io_sq6_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h14: begin
r_io_sq7_bs_addr[31:2] <= r_wdata[31:2];
end
6'h15: begin
r_io_sq7_size <= r_wdata[31:24];
r_io_sq7_cq_vec <= r_wdata[19:16];
r_io_sq7_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h16: begin
r_io_sq8_bs_addr[31:2] <= r_wdata[31:2];
end
6'h17: begin
r_io_sq8_size <= r_wdata[31:24];
r_io_sq8_cq_vec <= r_wdata[19:16];
r_io_sq8_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h18: begin
r_io_cq1_bs_addr[31:2] <= r_wdata[31:2];
end
6'h19: begin
r_io_cq1_size <= r_wdata[31:24];
r_io_cq1_iv <= r_wdata[18:16];
r_io_cq1_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h1A: begin
r_io_cq2_bs_addr[31:2] <= r_wdata[31:2];
end
6'h1B: begin
r_io_cq2_size <= r_wdata[31:24];
r_io_cq2_iv <= r_wdata[18:16];
r_io_cq2_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h1C: begin
r_io_cq3_bs_addr[31:2] <= r_wdata[31:2];
end
6'h1D: begin
r_io_cq3_size <= r_wdata[31:24];
r_io_cq3_iv <= r_wdata[18:16];
r_io_cq3_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h1E: begin
r_io_cq4_bs_addr[31:2] <= r_wdata[31:2];
end
6'h1F: begin
r_io_cq4_size <= r_wdata[31:24];
r_io_cq4_iv <= r_wdata[18:16];
r_io_cq4_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h20: begin
r_io_cq5_bs_addr[31:2] <= r_wdata[31:2];
end
6'h21: begin
r_io_cq5_size <= r_wdata[31:24];
r_io_cq5_iv <= r_wdata[18:16];
r_io_cq5_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h22: begin
r_io_cq6_bs_addr[31:2] <= r_wdata[31:2];
end
6'h23: begin
r_io_cq6_size <= r_wdata[31:24];
r_io_cq6_iv <= r_wdata[18:16];
r_io_cq6_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h24: begin
r_io_cq7_bs_addr[31:2] <= r_wdata[31:2];
end
6'h25: begin
r_io_cq7_size <= r_wdata[31:24];
r_io_cq7_iv <= r_wdata[18:16];
r_io_cq7_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
6'h26: begin
r_io_cq8_bs_addr[31:2] <= r_wdata[31:2];
end
6'h27: begin
r_io_cq8_size <= r_wdata[31:24];
r_io_cq8_iv <= r_wdata[18:16];
r_io_cq8_bs_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[3:0];
end
endcase
end
end
always @ (posedge s_axi_aclk)
begin
if(r_nvme_fifo_en == 1) begin
case(r_s_axi_awaddr[7:2]) // synthesis parallel_case
6'h01: {r_cpl_sq_qid, r_cpl_cid} <= r_wdata[19:0];
6'h02: r_cpl_specific <= r_wdata;
6'h03: {r_cpl_status, r_cql_type, r_hcmd_slot_tag} <= {r_wdata[31:17], r_wdata[15:14], r_wdata[6:0]};
6'h04: r_dma_cmd_dev_addr <= r_wdata[31:2];
6'h05: r_dma_cmd_pcie_addr[C_PCIE_ADDR_WIDTH-1:32] <= r_wdata[C_PCIE_ADDR_WIDTH-1-32:0];
6'h06: r_dma_cmd_pcie_addr[31:2] <= r_wdata[31:2];
6'h07: begin
r_dma_cmd_type <= r_wdata[31];
r_dma_cmd_dir <= r_wdata[30];
r_dma_cmd_hcmd_slot_tag <= r_wdata[29:23];
r_dma_cmd_4k_offset <= r_wdata[22:14];
r_dma_cmd_dev_len <= r_wdata[12:2];
end
endcase
end
end
//////////////////////////////////////////////////////////////////////////////////////
always @ (posedge s_axi_aclk or negedge s_axi_aresetn)
begin
if(s_axi_aresetn == 0)
cur_rd_state <= S_RD_IDLE;
else
cur_rd_state <= next_rd_state;
end
always @ (*)
begin
case(cur_rd_state)
S_RD_IDLE: begin
if(s_axi_arvalid == 1)
next_rd_state <= S_AR_VAILD;
else
next_rd_state <= S_RD_IDLE;
end
S_AR_VAILD: begin
next_rd_state <= S_AR_REG;
end
S_AR_REG: begin
if(r_araddr_hcmd_sq_rd_en == 1 || r_araddr_hcmd_table_rd_en == 1)
next_rd_state <= S_BRAM_READ;
else
next_rd_state <= S_R_READY;
end
S_BRAM_READ: begin
next_rd_state <= S_R_READY;
end
S_R_READY: begin
if(s_axi_rready == 1)
next_rd_state <= S_RD_IDLE;
else
next_rd_state <= S_R_READY;
end
default: begin
next_rd_state <= S_RD_IDLE;
end
endcase
end
always @ (posedge s_axi_aclk)
begin
case(cur_rd_state)
S_RD_IDLE: begin
r_s_axi_araddr <= s_axi_araddr[15:2];
end
S_AR_VAILD: begin
r_araddr_cntl_reg_en <= (r_s_axi_araddr[15:8] == 8'h0);
r_araddr_pcie_reg_en <= (r_s_axi_araddr[15:8] == 8'h1);
r_araddr_nvme_reg_en <= (r_s_axi_araddr[15:8] == 8'h2);
r_araddr_nvme_fifo_en <= (r_s_axi_araddr[15:8] == 8'h3);
r_araddr_hcmd_table_rd_en <= (r_s_axi_araddr[15:13] == 3'h1);
r_araddr_hcmd_sq_rd_en <= (r_s_axi_araddr[15:2] == 14'hC0) & hcmd_sq_empty_n;
end
S_AR_REG: begin
case({r_araddr_nvme_fifo_en, r_araddr_nvme_reg_en, r_araddr_pcie_reg_en, r_araddr_cntl_reg_en}) // synthesis parallel_case full_case
4'b0001: r_rdata <= r_cntl_reg_rdata;
4'b0010: r_rdata <= r_pcie_reg_rdata;
4'b0100: r_rdata <= r_nvme_reg_rdata;
4'b1000: r_rdata <= r_nvme_fifo_rdata;
endcase
end
S_BRAM_READ: begin
case({r_araddr_hcmd_table_rd_en, r_araddr_hcmd_sq_rd_en}) // synthesis parallel_case full_case
2'b01: r_rdata <= {1'b1, 7'b0, hcmd_sq_rd_data[18:11], 1'b0, hcmd_sq_rd_data[10:4], 4'b0, hcmd_sq_rd_data[3:0]};
2'b10: r_rdata <= hcmd_table_rd_data;
endcase
end
S_R_READY: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_rd_state)
S_RD_IDLE: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= 0;
end
S_AR_VAILD: begin
r_s_axi_arready <= 1;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= 0;
end
S_AR_REG: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= 0;
end
S_BRAM_READ: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= r_araddr_hcmd_sq_rd_en;
end
S_R_READY: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 1;
r_s_axi_rdata <= r_rdata;
r_s_axi_rresp <= `D_AXI_RESP_OKAY;
r_hcmd_sq_rd_en <= 0;
end
default: begin
r_s_axi_arready <= 0;
r_s_axi_rvalid <= 0;
r_s_axi_rdata <= 0;
r_s_axi_rresp <= 0;
r_hcmd_sq_rd_en <= 0;
end
endcase
end
always @ (*)
begin
case(r_s_axi_araddr[7:2]) // synthesis parallel_case full_case
6'h01: r_cntl_reg_rdata <= {20'b0, r_irq_mask};
6'h03: r_cntl_reg_rdata <= {20'b0, r_irq_set};
endcase
end
always @ (*)
begin
case(r_s_axi_araddr[7:2]) // synthesis parallel_case full_case
6'h00: r_pcie_reg_rdata <= {23'b0, r_pcie_link_up, 2'b0, pl_ltssm_state};
6'h01: r_pcie_reg_rdata <= {25'b0, r_cfg_interrupt_mmenable, ~r_cfg_command[10], r_cfg_interrupt_msixenable, r_cfg_interrupt_msienable, r_cfg_command[2]};
endcase
end
always @ (*)
begin
case(r_s_axi_araddr[7:2]) // synthesis parallel_case full_case
6'h00: r_nvme_reg_rdata <= {25'b0, r_nvme_csts_shst, r_nvme_csts_rdy, 1'b0, r_nvme_cc_shn, r_nvme_cc_en};
6'h01: r_nvme_reg_rdata <= {dma_tx_done_cnt, dma_rx_done_cnt, dma_tx_direct_done_cnt, dma_rx_direct_done_cnt};
6'h07: r_nvme_reg_rdata <= {19'b0, r_io_cq_irq_en[0], r_sq_valid[0], r_cq_valid[0]};
6'h08: r_nvme_reg_rdata <= {r_io_sq1_bs_addr[31:2], 2'b0};
6'h09: r_nvme_reg_rdata <= {r_io_sq1_size, 4'b0, r_io_sq1_cq_vec, r_sq_valid[1], 11'b0, r_io_sq1_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h0A: r_nvme_reg_rdata <= {r_io_sq2_bs_addr[31:2], 2'b0};
6'h0B: r_nvme_reg_rdata <= {r_io_sq2_size, 4'b0, r_io_sq2_cq_vec, r_sq_valid[2], 11'b0, r_io_sq2_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h0C: r_nvme_reg_rdata <= {r_io_sq3_bs_addr[31:2], 2'b0};
6'h0D: r_nvme_reg_rdata <= {r_io_sq3_size, 4'b0, r_io_sq3_cq_vec, r_sq_valid[3], 11'b0, r_io_sq3_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h0E: r_nvme_reg_rdata <= {r_io_sq4_bs_addr[31:2], 2'b0};
6'h0F: r_nvme_reg_rdata <= {r_io_sq4_size, 4'b0, r_io_sq4_cq_vec, r_sq_valid[4], 11'b0, r_io_sq4_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h10: r_nvme_reg_rdata <= {r_io_sq5_bs_addr[31:2], 2'b0};
6'h11: r_nvme_reg_rdata <= {r_io_sq5_size, 4'b0, r_io_sq5_cq_vec, r_sq_valid[5], 11'b0, r_io_sq5_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h12: r_nvme_reg_rdata <= {r_io_sq6_bs_addr[31:2], 2'b0};
6'h13: r_nvme_reg_rdata <= {r_io_sq6_size, 4'b0, r_io_sq6_cq_vec, r_sq_valid[6], 11'b0, r_io_sq6_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h14: r_nvme_reg_rdata <= {r_io_sq7_bs_addr[31:2], 2'b0};
6'h15: r_nvme_reg_rdata <= {r_io_sq7_size, 4'b0, r_io_sq7_cq_vec, r_sq_valid[7], 11'b0, r_io_sq7_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h16: r_nvme_reg_rdata <= {r_io_sq8_bs_addr[31:2], 2'b0};
6'h17: r_nvme_reg_rdata <= {r_io_sq8_size, 4'b0, r_io_sq8_cq_vec, r_sq_valid[8], 11'b0, r_io_sq8_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h18: r_nvme_reg_rdata <= {r_io_cq1_bs_addr[31:2], 2'b0};
6'h19: r_nvme_reg_rdata <= {r_io_cq1_size, 4'b0, r_io_cq_irq_en[1], r_io_cq1_iv, r_cq_valid[1], 11'b0, r_io_cq1_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h1A: r_nvme_reg_rdata <= {r_io_cq2_bs_addr[31:2], 2'b0};
6'h1B: r_nvme_reg_rdata <= {r_io_cq2_size, 4'b0, r_io_cq_irq_en[2], r_io_cq2_iv, r_cq_valid[2], 11'b0, r_io_cq2_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h1C: r_nvme_reg_rdata <= {r_io_cq3_bs_addr[31:2], 2'b0};
6'h1D: r_nvme_reg_rdata <= {r_io_cq3_size, 4'b0, r_io_cq_irq_en[3], r_io_cq3_iv, r_cq_valid[3], 11'b0, r_io_cq3_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h1E: r_nvme_reg_rdata <= {r_io_cq4_bs_addr[31:2], 2'b0};
6'h1F: r_nvme_reg_rdata <= {r_io_cq4_size, 4'b0, r_io_cq_irq_en[4], r_io_cq4_iv, r_cq_valid[4], 11'b0, r_io_cq4_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h20: r_nvme_reg_rdata <= {r_io_cq5_bs_addr[31:2], 2'b0};
6'h21: r_nvme_reg_rdata <= {r_io_cq5_size, 4'b0, r_io_cq_irq_en[5], r_io_cq5_iv, r_cq_valid[5], 11'b0, r_io_cq5_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h22: r_nvme_reg_rdata <= {r_io_cq6_bs_addr[31:2], 2'b0};
6'h23: r_nvme_reg_rdata <= {r_io_cq6_size, 4'b0, r_io_cq_irq_en[6], r_io_cq6_iv, r_cq_valid[6], 11'b0, r_io_cq6_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h24: r_nvme_reg_rdata <= {r_io_cq7_bs_addr[31:2], 2'b0};
6'h25: r_nvme_reg_rdata <= {r_io_cq7_size, 4'b0, r_io_cq_irq_en[7], r_io_cq7_iv, r_cq_valid[7], 11'b0, r_io_cq7_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h26: r_nvme_reg_rdata <= {r_io_cq8_bs_addr[31:2], 2'b0};
6'h27: r_nvme_reg_rdata <= {r_io_cq8_size, 4'b0, r_io_cq_irq_en[8], r_io_cq8_iv, r_cq_valid[8], 11'b0, r_io_cq8_bs_addr[C_PCIE_ADDR_WIDTH-1:32]};
endcase
end
always @ (*)
begin
case(r_s_axi_araddr[7:2]) // synthesis parallel_case full_case
6'h00: r_nvme_fifo_rdata <= 0;
6'h01: r_nvme_fifo_rdata <= {12'b0, r_cpl_sq_qid, r_cpl_cid};
6'h02: r_nvme_fifo_rdata <= r_cpl_specific;
6'h03: r_nvme_fifo_rdata <= {r_cpl_status, 1'b0, r_cql_type, 7'b0, r_hcmd_slot_tag};
6'h04: r_nvme_fifo_rdata <= {r_dma_cmd_dev_addr, 2'b0};
6'h05: r_nvme_fifo_rdata <= {28'b0, r_dma_cmd_pcie_addr[C_PCIE_ADDR_WIDTH-1:32]};
6'h06: r_nvme_fifo_rdata <= {r_dma_cmd_pcie_addr[31:2], 2'b0};
6'h07: r_nvme_fifo_rdata <= {r_dma_cmd_type, r_dma_cmd_dir, r_dma_cmd_hcmd_slot_tag, r_dma_cmd_4k_offset, 1'b0, r_dma_cmd_dev_len, 2'b0};
endcase
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_cntl_slave # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output rx_np_ok,
output rx_np_req,
input mreq_fifo_wr_en,
input [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output tx_cpld_req,
output [7:0] tx_cpld_tag,
output [15:0] tx_cpld_req_id,
output [11:2] tx_cpld_len,
output [11:0] tx_cpld_bc,
output [6:0] tx_cpld_laddr,
output [63:0] tx_cpld_data,
input tx_cpld_req_ack,
output nvme_cc_en,
output [1:0] nvme_cc_shn,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
output nvme_intms_ivms,
output nvme_intmc_ivmc,
input cq_irq_status,
input [8:0] sq_rst_n,
input [8:0] cq_rst_n,
output [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
output [7:0] admin_sq_size,
output [7:0] admin_cq_size,
output [7:0] admin_sq_tail_ptr,
output [7:0] io_sq1_tail_ptr,
output [7:0] io_sq2_tail_ptr,
output [7:0] io_sq3_tail_ptr,
output [7:0] io_sq4_tail_ptr,
output [7:0] io_sq5_tail_ptr,
output [7:0] io_sq6_tail_ptr,
output [7:0] io_sq7_tail_ptr,
output [7:0] io_sq8_tail_ptr,
output [7:0] admin_cq_head_ptr,
output [7:0] io_cq1_head_ptr,
output [7:0] io_cq2_head_ptr,
output [7:0] io_cq3_head_ptr,
output [7:0] io_cq4_head_ptr,
output [7:0] io_cq5_head_ptr,
output [7:0] io_cq6_head_ptr,
output [7:0] io_cq7_head_ptr,
output [7:0] io_cq8_head_ptr,
output [8:0] cq_head_update
);
wire w_mreq_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_mreq_fifo_rd_data;
wire w_mreq_fifo_empty_n;
pcie_cntl_reg # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_cntl_reg_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.rx_np_ok (),
.rx_np_req (rx_np_req),
.mreq_fifo_rd_en (w_mreq_fifo_rd_en),
.mreq_fifo_rd_data (w_mreq_fifo_rd_data),
.mreq_fifo_empty_n (w_mreq_fifo_empty_n),
.tx_cpld_req (tx_cpld_req),
.tx_cpld_tag (tx_cpld_tag),
.tx_cpld_req_id (tx_cpld_req_id),
.tx_cpld_len (tx_cpld_len),
.tx_cpld_bc (tx_cpld_bc),
.tx_cpld_laddr (tx_cpld_laddr),
.tx_cpld_data (tx_cpld_data),
.tx_cpld_req_ack (tx_cpld_req_ack),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.nvme_intms_ivms (nvme_intms_ivms),
.nvme_intmc_ivmc (nvme_intmc_ivmc),
.cq_irq_status (cq_irq_status),
.sq_rst_n (sq_rst_n),
.cq_rst_n (cq_rst_n),
.admin_sq_bs_addr (admin_sq_bs_addr),
.admin_cq_bs_addr (admin_cq_bs_addr),
.admin_sq_size (admin_sq_size),
.admin_cq_size (admin_cq_size),
.admin_sq_tail_ptr (admin_sq_tail_ptr),
.io_sq1_tail_ptr (io_sq1_tail_ptr),
.io_sq2_tail_ptr (io_sq2_tail_ptr),
.io_sq3_tail_ptr (io_sq3_tail_ptr),
.io_sq4_tail_ptr (io_sq4_tail_ptr),
.io_sq5_tail_ptr (io_sq5_tail_ptr),
.io_sq6_tail_ptr (io_sq6_tail_ptr),
.io_sq7_tail_ptr (io_sq7_tail_ptr),
.io_sq8_tail_ptr (io_sq8_tail_ptr),
.admin_cq_head_ptr (admin_cq_head_ptr),
.io_cq1_head_ptr (io_cq1_head_ptr),
.io_cq2_head_ptr (io_cq2_head_ptr),
.io_cq3_head_ptr (io_cq3_head_ptr),
.io_cq4_head_ptr (io_cq4_head_ptr),
.io_cq5_head_ptr (io_cq5_head_ptr),
.io_cq6_head_ptr (io_cq6_head_ptr),
.io_cq7_head_ptr (io_cq7_head_ptr),
.io_cq8_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update)
);
pcie_cntl_rx_fifo
pcie_cntl_rx_fifo_inst0(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
////////////////////////////////////////////////////////////////
//bram fifo write signals
.wr_en (mreq_fifo_wr_en),
.wr_data (mreq_fifo_wr_data),
.full_n (),
.almost_full_n (rx_np_ok),
////////////////////////////////////////////////////////////////
//bram fifo read signals
.rd_en (w_mreq_fifo_rd_en),
.rd_data (w_mreq_fifo_rd_data),
.empty_n (w_mreq_fifo_empty_n)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_cntl_slave # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output rx_np_ok,
output rx_np_req,
input mreq_fifo_wr_en,
input [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output tx_cpld_req,
output [7:0] tx_cpld_tag,
output [15:0] tx_cpld_req_id,
output [11:2] tx_cpld_len,
output [11:0] tx_cpld_bc,
output [6:0] tx_cpld_laddr,
output [63:0] tx_cpld_data,
input tx_cpld_req_ack,
output nvme_cc_en,
output [1:0] nvme_cc_shn,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
output nvme_intms_ivms,
output nvme_intmc_ivmc,
input cq_irq_status,
input [8:0] sq_rst_n,
input [8:0] cq_rst_n,
output [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
output [7:0] admin_sq_size,
output [7:0] admin_cq_size,
output [7:0] admin_sq_tail_ptr,
output [7:0] io_sq1_tail_ptr,
output [7:0] io_sq2_tail_ptr,
output [7:0] io_sq3_tail_ptr,
output [7:0] io_sq4_tail_ptr,
output [7:0] io_sq5_tail_ptr,
output [7:0] io_sq6_tail_ptr,
output [7:0] io_sq7_tail_ptr,
output [7:0] io_sq8_tail_ptr,
output [7:0] admin_cq_head_ptr,
output [7:0] io_cq1_head_ptr,
output [7:0] io_cq2_head_ptr,
output [7:0] io_cq3_head_ptr,
output [7:0] io_cq4_head_ptr,
output [7:0] io_cq5_head_ptr,
output [7:0] io_cq6_head_ptr,
output [7:0] io_cq7_head_ptr,
output [7:0] io_cq8_head_ptr,
output [8:0] cq_head_update
);
wire w_mreq_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_mreq_fifo_rd_data;
wire w_mreq_fifo_empty_n;
pcie_cntl_reg # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_cntl_reg_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.rx_np_ok (),
.rx_np_req (rx_np_req),
.mreq_fifo_rd_en (w_mreq_fifo_rd_en),
.mreq_fifo_rd_data (w_mreq_fifo_rd_data),
.mreq_fifo_empty_n (w_mreq_fifo_empty_n),
.tx_cpld_req (tx_cpld_req),
.tx_cpld_tag (tx_cpld_tag),
.tx_cpld_req_id (tx_cpld_req_id),
.tx_cpld_len (tx_cpld_len),
.tx_cpld_bc (tx_cpld_bc),
.tx_cpld_laddr (tx_cpld_laddr),
.tx_cpld_data (tx_cpld_data),
.tx_cpld_req_ack (tx_cpld_req_ack),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.nvme_intms_ivms (nvme_intms_ivms),
.nvme_intmc_ivmc (nvme_intmc_ivmc),
.cq_irq_status (cq_irq_status),
.sq_rst_n (sq_rst_n),
.cq_rst_n (cq_rst_n),
.admin_sq_bs_addr (admin_sq_bs_addr),
.admin_cq_bs_addr (admin_cq_bs_addr),
.admin_sq_size (admin_sq_size),
.admin_cq_size (admin_cq_size),
.admin_sq_tail_ptr (admin_sq_tail_ptr),
.io_sq1_tail_ptr (io_sq1_tail_ptr),
.io_sq2_tail_ptr (io_sq2_tail_ptr),
.io_sq3_tail_ptr (io_sq3_tail_ptr),
.io_sq4_tail_ptr (io_sq4_tail_ptr),
.io_sq5_tail_ptr (io_sq5_tail_ptr),
.io_sq6_tail_ptr (io_sq6_tail_ptr),
.io_sq7_tail_ptr (io_sq7_tail_ptr),
.io_sq8_tail_ptr (io_sq8_tail_ptr),
.admin_cq_head_ptr (admin_cq_head_ptr),
.io_cq1_head_ptr (io_cq1_head_ptr),
.io_cq2_head_ptr (io_cq2_head_ptr),
.io_cq3_head_ptr (io_cq3_head_ptr),
.io_cq4_head_ptr (io_cq4_head_ptr),
.io_cq5_head_ptr (io_cq5_head_ptr),
.io_cq6_head_ptr (io_cq6_head_ptr),
.io_cq7_head_ptr (io_cq7_head_ptr),
.io_cq8_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update)
);
pcie_cntl_rx_fifo
pcie_cntl_rx_fifo_inst0(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
////////////////////////////////////////////////////////////////
//bram fifo write signals
.wr_en (mreq_fifo_wr_en),
.wr_data (mreq_fifo_wr_data),
.full_n (),
.almost_full_n (rx_np_ok),
////////////////////////////////////////////////////////////////
//bram fifo read signals
.rd_en (w_mreq_fifo_rd_en),
.rd_data (w_mreq_fifo_rd_data),
.empty_n (w_mreq_fifo_empty_n)
);
endmodule |
module tx_buffer_inband
( //System
input wire usbclk, input wire bus_reset, input wire reset,
input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels,
//output transmit signals
output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,
output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
output wire [15:0] tx_i_2, output wire [15:0] tx_q_2,
output wire [15:0] tx_i_3, output wire [15:0] tx_q_3,
input wire txclk, input wire txstrobe, input wire WR,
input wire clear_status, output wire tx_empty, output wire [15:0] debugbus,
//command reader io
output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
input wire rx_WR_enabled,
//register io
output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr,
input wire [31:0] reg_data_out,
//input characteristic signals
input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2,
input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold,
output wire [1:0] tx_underrun,
//system stop
output wire stop, output wire [15:0] stop_time, output wire test_bit0, output wire test_bit1);
/* Debug paramters */
parameter STROBE_RATE_0 = 8'd1 ;
parameter STROBE_RATE_1 = 8'd2 ;
parameter NUM_CHAN = 2 ;
/* To generate channel readers */
genvar i ;
/* These will eventually be external register */
reg [31:0] adc_time ;
wire datapattern_err;
wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
wire [31:0] rssi [3:0];
assign rssi[0] = rssi_0;
assign rssi[1] = rssi_1;
assign rssi[2] = rssi_2;
assign rssi[3] = rssi_3;
always @(posedge txclk)
if (reset)
adc_time <= 0;
else if (txstrobe)
adc_time <= adc_time + 1;
/* Connections between tx_usb_fifo_reader and
cnannel/command processing blocks */
wire [31:0] tx_data_bus ;
wire [NUM_CHAN:0] chan_WR ;
wire [NUM_CHAN:0] chan_done ;
/* Connections between data block and the
FX2/TX chains */
wire [NUM_CHAN:0] chan_underrun;
wire [NUM_CHAN:0] chan_txempty;
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
wire [31:0] chan_fifodata [NUM_CHAN:0] ;
wire chan_pkt_waiting [NUM_CHAN:0] ;
wire chan_rdreq [NUM_CHAN:0] ;
wire chan_skip [NUM_CHAN:0] ;
wire chan_have_space [NUM_CHAN:0] ;
wire chan_txstrobe [NUM_CHAN-1:0] ;
wire [14:0] debug [NUM_CHAN:0];
/* Outputs to transmit chains */
wire [15:0] tx_i [NUM_CHAN-1:0] ;
wire [15:0] tx_q [NUM_CHAN-1:0] ;
/* TODO: Figure out how to write this genericly */
assign have_space = chan_have_space[0];// & chan_have_space[1];
assign tx_empty = chan_txempty[0];// & chan_txempty[1] ;
assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
assign datapattern_err = ((tx_i_0 != 16'h0000) || (tx_q_0 != 16'hffff)) && !tx_empty;
assign test_bit0 = datapattern_err;
/* Debug statement */
assign txstrobe_rate[0] = STROBE_RATE_0 ;
assign txstrobe_rate[1] = STROBE_RATE_1 ;
assign tx_q_2 = 16'b0 ;
assign tx_i_2 = 16'b0 ;
assign tx_q_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
wire [31:0] usbdata_final;
wire WR_final;
assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done,
chan_pkt_waiting[0], chan_pkt_waiting[1],
chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]};
tx_packer tx_usb_packer
(.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR),
.usbdata(usbdata), .reset(reset), .txclk(txclk),
.usbdata_final(usbdata_final), .WR_final(WR_final),
.test_bit0(), .test_bit1(test_bit1));
channel_demux channel_demuxer
(.usbdata_final(usbdata_final), .WR_final(WR_final),
.reset(reset), .txclk(txclk), .WR_channel(chan_WR),
.WR_done_channel(chan_done), .ram_data(tx_data_bus));
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_readers
assign tx_underrun[i] = chan_underrun[i];
channel_ram tx_data_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus),
.WR(chan_WR[i]), .WR_done(chan_done[i]),
.have_space(chan_have_space[i]), .dataout(chan_fifodata[i]),
.packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]),
.RD_done(chan_skip[i]));
chan_fifo_reader tx_chan_reader
(.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
.adc_time(adc_time), .samples_format(4'b0),
.tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
.skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
.fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
.tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
.threshhold(threshhold), .rssi_wait(rssi_wait));
end
endgenerate
channel_ram tx_cmd_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]),
.WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]),
.dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]),
.RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
cmd_reader tx_cmd_reader
(.reset(reset), .txclk(txclk), .adc_time(adc_time), .skip(chan_skip[NUM_CHAN]),
.rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
.pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
.rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
.reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr),
.reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time));
endmodule // tx_buffer
|
module tx_buffer_inband
( //System
input wire usbclk, input wire bus_reset, input wire reset,
input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels,
//output transmit signals
output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,
output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
output wire [15:0] tx_i_2, output wire [15:0] tx_q_2,
output wire [15:0] tx_i_3, output wire [15:0] tx_q_3,
input wire txclk, input wire txstrobe, input wire WR,
input wire clear_status, output wire tx_empty, output wire [15:0] debugbus,
//command reader io
output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
input wire rx_WR_enabled,
//register io
output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr,
input wire [31:0] reg_data_out,
//input characteristic signals
input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2,
input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold,
output wire [1:0] tx_underrun,
//system stop
output wire stop, output wire [15:0] stop_time, output wire test_bit0, output wire test_bit1);
/* Debug paramters */
parameter STROBE_RATE_0 = 8'd1 ;
parameter STROBE_RATE_1 = 8'd2 ;
parameter NUM_CHAN = 2 ;
/* To generate channel readers */
genvar i ;
/* These will eventually be external register */
reg [31:0] adc_time ;
wire datapattern_err;
wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
wire [31:0] rssi [3:0];
assign rssi[0] = rssi_0;
assign rssi[1] = rssi_1;
assign rssi[2] = rssi_2;
assign rssi[3] = rssi_3;
always @(posedge txclk)
if (reset)
adc_time <= 0;
else if (txstrobe)
adc_time <= adc_time + 1;
/* Connections between tx_usb_fifo_reader and
cnannel/command processing blocks */
wire [31:0] tx_data_bus ;
wire [NUM_CHAN:0] chan_WR ;
wire [NUM_CHAN:0] chan_done ;
/* Connections between data block and the
FX2/TX chains */
wire [NUM_CHAN:0] chan_underrun;
wire [NUM_CHAN:0] chan_txempty;
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
wire [31:0] chan_fifodata [NUM_CHAN:0] ;
wire chan_pkt_waiting [NUM_CHAN:0] ;
wire chan_rdreq [NUM_CHAN:0] ;
wire chan_skip [NUM_CHAN:0] ;
wire chan_have_space [NUM_CHAN:0] ;
wire chan_txstrobe [NUM_CHAN-1:0] ;
wire [14:0] debug [NUM_CHAN:0];
/* Outputs to transmit chains */
wire [15:0] tx_i [NUM_CHAN-1:0] ;
wire [15:0] tx_q [NUM_CHAN-1:0] ;
/* TODO: Figure out how to write this genericly */
assign have_space = chan_have_space[0];// & chan_have_space[1];
assign tx_empty = chan_txempty[0];// & chan_txempty[1] ;
assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
assign datapattern_err = ((tx_i_0 != 16'h0000) || (tx_q_0 != 16'hffff)) && !tx_empty;
assign test_bit0 = datapattern_err;
/* Debug statement */
assign txstrobe_rate[0] = STROBE_RATE_0 ;
assign txstrobe_rate[1] = STROBE_RATE_1 ;
assign tx_q_2 = 16'b0 ;
assign tx_i_2 = 16'b0 ;
assign tx_q_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
wire [31:0] usbdata_final;
wire WR_final;
assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done,
chan_pkt_waiting[0], chan_pkt_waiting[1],
chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]};
tx_packer tx_usb_packer
(.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR),
.usbdata(usbdata), .reset(reset), .txclk(txclk),
.usbdata_final(usbdata_final), .WR_final(WR_final),
.test_bit0(), .test_bit1(test_bit1));
channel_demux channel_demuxer
(.usbdata_final(usbdata_final), .WR_final(WR_final),
.reset(reset), .txclk(txclk), .WR_channel(chan_WR),
.WR_done_channel(chan_done), .ram_data(tx_data_bus));
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_readers
assign tx_underrun[i] = chan_underrun[i];
channel_ram tx_data_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus),
.WR(chan_WR[i]), .WR_done(chan_done[i]),
.have_space(chan_have_space[i]), .dataout(chan_fifodata[i]),
.packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]),
.RD_done(chan_skip[i]));
chan_fifo_reader tx_chan_reader
(.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
.adc_time(adc_time), .samples_format(4'b0),
.tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
.skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
.fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
.tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
.threshhold(threshhold), .rssi_wait(rssi_wait));
end
endgenerate
channel_ram tx_cmd_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]),
.WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]),
.dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]),
.RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
cmd_reader tx_cmd_reader
(.reset(reset), .txclk(txclk), .adc_time(adc_time), .skip(chan_skip[NUM_CHAN]),
.rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
.pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
.rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
.reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr),
.reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time));
endmodule // tx_buffer
|
module tx_buffer_inband
( //System
input wire usbclk, input wire bus_reset, input wire reset,
input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels,
//output transmit signals
output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,
output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
output wire [15:0] tx_i_2, output wire [15:0] tx_q_2,
output wire [15:0] tx_i_3, output wire [15:0] tx_q_3,
input wire txclk, input wire txstrobe, input wire WR,
input wire clear_status, output wire tx_empty, output wire [15:0] debugbus,
//command reader io
output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
input wire rx_WR_enabled,
//register io
output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr,
input wire [31:0] reg_data_out,
//input characteristic signals
input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2,
input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold,
output wire [1:0] tx_underrun,
//system stop
output wire stop, output wire [15:0] stop_time, output wire test_bit0, output wire test_bit1);
/* Debug paramters */
parameter STROBE_RATE_0 = 8'd1 ;
parameter STROBE_RATE_1 = 8'd2 ;
parameter NUM_CHAN = 2 ;
/* To generate channel readers */
genvar i ;
/* These will eventually be external register */
reg [31:0] adc_time ;
wire datapattern_err;
wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
wire [31:0] rssi [3:0];
assign rssi[0] = rssi_0;
assign rssi[1] = rssi_1;
assign rssi[2] = rssi_2;
assign rssi[3] = rssi_3;
always @(posedge txclk)
if (reset)
adc_time <= 0;
else if (txstrobe)
adc_time <= adc_time + 1;
/* Connections between tx_usb_fifo_reader and
cnannel/command processing blocks */
wire [31:0] tx_data_bus ;
wire [NUM_CHAN:0] chan_WR ;
wire [NUM_CHAN:0] chan_done ;
/* Connections between data block and the
FX2/TX chains */
wire [NUM_CHAN:0] chan_underrun;
wire [NUM_CHAN:0] chan_txempty;
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
wire [31:0] chan_fifodata [NUM_CHAN:0] ;
wire chan_pkt_waiting [NUM_CHAN:0] ;
wire chan_rdreq [NUM_CHAN:0] ;
wire chan_skip [NUM_CHAN:0] ;
wire chan_have_space [NUM_CHAN:0] ;
wire chan_txstrobe [NUM_CHAN-1:0] ;
wire [14:0] debug [NUM_CHAN:0];
/* Outputs to transmit chains */
wire [15:0] tx_i [NUM_CHAN-1:0] ;
wire [15:0] tx_q [NUM_CHAN-1:0] ;
/* TODO: Figure out how to write this genericly */
assign have_space = chan_have_space[0];// & chan_have_space[1];
assign tx_empty = chan_txempty[0];// & chan_txempty[1] ;
assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
assign datapattern_err = ((tx_i_0 != 16'h0000) || (tx_q_0 != 16'hffff)) && !tx_empty;
assign test_bit0 = datapattern_err;
/* Debug statement */
assign txstrobe_rate[0] = STROBE_RATE_0 ;
assign txstrobe_rate[1] = STROBE_RATE_1 ;
assign tx_q_2 = 16'b0 ;
assign tx_i_2 = 16'b0 ;
assign tx_q_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
wire [31:0] usbdata_final;
wire WR_final;
assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done,
chan_pkt_waiting[0], chan_pkt_waiting[1],
chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]};
tx_packer tx_usb_packer
(.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR),
.usbdata(usbdata), .reset(reset), .txclk(txclk),
.usbdata_final(usbdata_final), .WR_final(WR_final),
.test_bit0(), .test_bit1(test_bit1));
channel_demux channel_demuxer
(.usbdata_final(usbdata_final), .WR_final(WR_final),
.reset(reset), .txclk(txclk), .WR_channel(chan_WR),
.WR_done_channel(chan_done), .ram_data(tx_data_bus));
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_readers
assign tx_underrun[i] = chan_underrun[i];
channel_ram tx_data_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus),
.WR(chan_WR[i]), .WR_done(chan_done[i]),
.have_space(chan_have_space[i]), .dataout(chan_fifodata[i]),
.packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]),
.RD_done(chan_skip[i]));
chan_fifo_reader tx_chan_reader
(.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
.adc_time(adc_time), .samples_format(4'b0),
.tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
.skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
.fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
.tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
.threshhold(threshhold), .rssi_wait(rssi_wait));
end
endgenerate
channel_ram tx_cmd_packet_fifo
(.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]),
.WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]),
.dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]),
.RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
cmd_reader tx_cmd_reader
(.reset(reset), .txclk(txclk), .adc_time(adc_time), .skip(chan_skip[NUM_CHAN]),
.rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
.pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
.rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
.reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr),
.reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time));
endmodule // tx_buffer
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [7:0] admin_sq_size,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
output [7:0] admin_sq_head_ptr,
output [7:0] io_sq1_head_ptr,
output [7:0] io_sq2_head_ptr,
output [7:0] io_sq3_head_ptr,
output [7:0] io_sq4_head_ptr,
output [7:0] io_sq5_head_ptr,
output [7:0] io_sq6_head_ptr,
output [7:0] io_sq7_head_ptr,
output [7:0] io_sq8_head_ptr,
input hcmd_slot_rdy,
input [6:0] hcmd_slot_tag,
output hcmd_slot_alloc_en,
input [7:0] cpld_sq_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_sq_fifo_wr_data,
input cpld_sq_fifo_wr_en,
input cpld_sq_fifo_tag_last,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack,
output hcmd_table_wr_en,
output [8:0] hcmd_table_wr_addr,
output [C_PCIE_DATA_WIDTH-1:0] hcmd_table_wr_data,
output hcmd_cid_wr_en,
output [6:0] hcmd_cid_wr_addr,
output [19:0] hcmd_cid_wr_data,
output hcmd_prp_wr_en,
output [7:0] hcmd_prp_wr_addr,
output [44:0] hcmd_prp_wr_data,
output hcmd_nlb_wr0_en,
output [6:0] hcmd_nlb_wr0_addr,
output [18:0] hcmd_nlb_wr0_data,
input hcmd_nlb_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input hcmd_sq_rd_en,
output [18:0] hcmd_sq_rd_data,
output hcmd_sq_empty_n
);
wire w_arb_sq_rdy;
wire [3:0] w_sq_qid;
wire [C_PCIE_ADDR_WIDTH-1:2] w_hcmd_pcie_addr;
wire w_sq_hcmd_ack;
wire w_hcmd_sq_wr_en;
wire [18:0] w_hcmd_sq_wr_data;
wire w_hcmd_sq_full_n;
wire w_pcie_sq_cmd_fifo_wr_en;
wire [10:0] w_pcie_sq_cmd_fifo_wr_data;
wire w_pcie_sq_cmd_fifo_full_n;
wire w_pcie_sq_cmd_fifo_rd_en;
wire [10:0] w_pcie_sq_cmd_fifo_rd_data;
wire w_pcie_sq_cmd_fifo_empty_n;
wire w_pcie_sq_rx_tag_alloc;
wire [7:0] w_pcie_sq_rx_alloc_tag;
wire [6:4] w_pcie_sq_rx_tag_alloc_len;
wire w_pcie_sq_rx_tag_full_n;
wire w_pcie_sq_rx_fifo_wr_en;
wire [3:0] w_pcie_sq_rx_fifo_wr_addr;
wire [C_PCIE_DATA_WIDTH-1:0] w_pcie_sq_rx_fifo_wr_data;
wire [4:0] w_pcie_sq_rx_fifo_rear_full_addr;
wire [4:0] w_pcie_sq_rx_fifo_rear_addr;
wire w_pcie_sq_rx_fifo_full_n;
wire w_pcie_sq_rx_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_pcie_sq_rx_fifo_rd_data;
wire w_pcie_sq_rx_fifo_free_en;
wire [6:4] w_pcie_sq_rx_fifo_free_len;
wire w_pcie_sq_rx_fifo_empty_n;
pcie_hcmd_sq_fifo
pcie_hcmd_sq_fifo_inst0(
.wr_clk (pcie_user_clk),
.wr_rst_n (pcie_user_rst_n),
.wr_en (w_hcmd_sq_wr_en),
.wr_data (w_hcmd_sq_wr_data),
.full_n (w_hcmd_sq_full_n),
.rd_clk (cpu_bus_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (hcmd_sq_rd_en),
.rd_data (hcmd_sq_rd_data),
.empty_n (hcmd_sq_empty_n)
);
pcie_sq_cmd_fifo
pcie_sq_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_sq_cmd_fifo_wr_en),
.wr_data (w_pcie_sq_cmd_fifo_wr_data),
.full_n (w_pcie_sq_cmd_fifo_full_n),
.rd_en (w_pcie_sq_cmd_fifo_rd_en),
.rd_data (w_pcie_sq_cmd_fifo_rd_data),
.empty_n (w_pcie_sq_cmd_fifo_empty_n)
);
pcie_sq_rx_fifo
pcie_sq_rx_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_sq_rx_fifo_wr_en),
.wr_addr (w_pcie_sq_rx_fifo_wr_addr),
.wr_data (w_pcie_sq_rx_fifo_wr_data),
.rear_full_addr (w_pcie_sq_rx_fifo_rear_full_addr),
.rear_addr (w_pcie_sq_rx_fifo_rear_addr),
.alloc_len (w_pcie_sq_rx_tag_alloc_len),
.full_n (w_pcie_sq_rx_fifo_full_n),
.rd_en (w_pcie_sq_rx_fifo_rd_en),
.rd_data (w_pcie_sq_rx_fifo_rd_data),
.free_en (w_pcie_sq_rx_fifo_free_en),
.free_len (w_pcie_sq_rx_fifo_free_len),
.empty_n (w_pcie_sq_rx_fifo_empty_n)
);
pcie_sq_rx_tag
pcie_sq_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_pcie_sq_rx_tag_alloc),
.pcie_alloc_tag (w_pcie_sq_rx_alloc_tag),
.pcie_tag_alloc_len (w_pcie_sq_rx_tag_alloc_len),
.pcie_tag_full_n (w_pcie_sq_rx_tag_full_n),
.cpld_fifo_tag (cpld_sq_fifo_tag),
.cpld_fifo_wr_data (cpld_sq_fifo_wr_data),
.cpld_fifo_wr_en (cpld_sq_fifo_wr_en),
.cpld_fifo_tag_last (cpld_sq_fifo_tag_last),
.fifo_wr_en (w_pcie_sq_rx_fifo_wr_en),
.fifo_wr_addr (w_pcie_sq_rx_fifo_wr_addr),
.fifo_wr_data (w_pcie_sq_rx_fifo_wr_data),
.rear_full_addr (w_pcie_sq_rx_fifo_rear_full_addr),
.rear_addr (w_pcie_sq_rx_fifo_rear_addr)
);
pcie_hcmd_sq_arb
pcie_hcmd_sq_arb_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.sq_rst_n (sq_rst_n),
.sq_valid (sq_valid),
.admin_sq_size (admin_sq_size),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.admin_sq_bs_addr (admin_sq_bs_addr),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.admin_sq_tail_ptr (admin_sq_tail_ptr),
.io_sq1_tail_ptr (io_sq1_tail_ptr),
.io_sq2_tail_ptr (io_sq2_tail_ptr),
.io_sq3_tail_ptr (io_sq3_tail_ptr),
.io_sq4_tail_ptr (io_sq4_tail_ptr),
.io_sq5_tail_ptr (io_sq5_tail_ptr),
.io_sq6_tail_ptr (io_sq6_tail_ptr),
.io_sq7_tail_ptr (io_sq7_tail_ptr),
.io_sq8_tail_ptr (io_sq8_tail_ptr),
.arb_sq_rdy (w_arb_sq_rdy),
.sq_qid (w_sq_qid),
.hcmd_pcie_addr (w_hcmd_pcie_addr),
.sq_hcmd_ack (w_sq_hcmd_ack)
);
pcie_hcmd_sq_req # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_sq_req_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.arb_sq_rdy (w_arb_sq_rdy),
.sq_qid (w_sq_qid),
.hcmd_pcie_addr (w_hcmd_pcie_addr),
.sq_hcmd_ack (w_sq_hcmd_ack),
.hcmd_slot_rdy (hcmd_slot_rdy),
.hcmd_slot_tag (hcmd_slot_tag),
.hcmd_slot_alloc_en (hcmd_slot_alloc_en),
.pcie_sq_cmd_fifo_wr_en (w_pcie_sq_cmd_fifo_wr_en),
.pcie_sq_cmd_fifo_wr_data (w_pcie_sq_cmd_fifo_wr_data),
.pcie_sq_cmd_fifo_full_n (w_pcie_sq_cmd_fifo_full_n),
.pcie_sq_rx_tag_alloc (w_pcie_sq_rx_tag_alloc),
.pcie_sq_rx_alloc_tag (w_pcie_sq_rx_alloc_tag),
.pcie_sq_rx_tag_alloc_len (w_pcie_sq_rx_tag_alloc_len),
.pcie_sq_rx_tag_full_n (w_pcie_sq_rx_tag_full_n),
.pcie_sq_rx_fifo_full_n (w_pcie_sq_rx_fifo_full_n),
.tx_mrd_req (tx_mrd_req),
.tx_mrd_tag (tx_mrd_tag),
.tx_mrd_len (tx_mrd_len),
.tx_mrd_addr (tx_mrd_addr),
.tx_mrd_req_ack (tx_mrd_req_ack)
);
pcie_hcmd_sq_recv
pcie_hcmd_sq_recv_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_sq_cmd_fifo_rd_en (w_pcie_sq_cmd_fifo_rd_en),
.pcie_sq_cmd_fifo_rd_data (w_pcie_sq_cmd_fifo_rd_data),
.pcie_sq_cmd_fifo_empty_n (w_pcie_sq_cmd_fifo_empty_n),
.pcie_sq_rx_fifo_rd_en (w_pcie_sq_rx_fifo_rd_en),
.pcie_sq_rx_fifo_rd_data (w_pcie_sq_rx_fifo_rd_data),
.pcie_sq_rx_fifo_free_en (w_pcie_sq_rx_fifo_free_en),
.pcie_sq_rx_fifo_free_len (w_pcie_sq_rx_fifo_free_len),
.pcie_sq_rx_fifo_empty_n (w_pcie_sq_rx_fifo_empty_n),
.hcmd_table_wr_en (hcmd_table_wr_en),
.hcmd_table_wr_addr (hcmd_table_wr_addr),
.hcmd_table_wr_data (hcmd_table_wr_data),
.hcmd_cid_wr_en (hcmd_cid_wr_en),
.hcmd_cid_wr_addr (hcmd_cid_wr_addr),
.hcmd_cid_wr_data (hcmd_cid_wr_data),
.hcmd_prp_wr_en (hcmd_prp_wr_en),
.hcmd_prp_wr_addr (hcmd_prp_wr_addr),
.hcmd_prp_wr_data (hcmd_prp_wr_data),
.hcmd_nlb_wr0_en (hcmd_nlb_wr0_en),
.hcmd_nlb_wr0_addr (hcmd_nlb_wr0_addr),
.hcmd_nlb_wr0_data (hcmd_nlb_wr0_data),
.hcmd_nlb_wr0_rdy_n (hcmd_nlb_wr0_rdy_n),
.hcmd_sq_wr_en (w_hcmd_sq_wr_en),
.hcmd_sq_wr_data (w_hcmd_sq_wr_data),
.hcmd_sq_full_n (w_hcmd_sq_full_n),
.sq_rst_n (sq_rst_n),
.admin_sq_size (admin_sq_size),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.admin_sq_head_ptr (admin_sq_head_ptr),
.io_sq1_head_ptr (io_sq1_head_ptr),
.io_sq2_head_ptr (io_sq2_head_ptr),
.io_sq3_head_ptr (io_sq3_head_ptr),
.io_sq4_head_ptr (io_sq4_head_ptr),
.io_sq5_head_ptr (io_sq5_head_ptr),
.io_sq6_head_ptr (io_sq6_head_ptr),
.io_sq7_head_ptr (io_sq7_head_ptr),
.io_sq8_head_ptr (io_sq8_head_ptr)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [7:0] a,b;
wire [7:0] z;
mytop u0 ( a, b, clk, z );
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x\n", cyc, z);
if (cyc==1) begin
a <= 8'h07;
b <= 8'h20;
end
if (cyc==2) begin
a <= 8'h8a;
b <= 8'h12;
end
if (cyc==3) begin
if (z !== 8'hdf) $stop;
a <= 8'h71;
b <= 8'hb2;
end
if (cyc==4) begin
if (z !== 8'hed) $stop;
end
if (cyc==5) begin
if (z !== 8'h4d) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule // mytop
module inv(
input [ 7:0 ] a,
output [ 7:0 ] z
);
wire [7:0] z = ~a;
endmodule
module ftest(
input [ 7:0 ] a,
b, // Test legal syntax
input clk,
output [ 7:0 ] z
);
wire [7:0] zi;
reg [7:0] z;
inv u1 (.a(myadd(a,b)),
.z(zi));
always @ ( posedge clk ) begin
z <= myadd( a, zi );
end
function [ 7:0 ] myadd;
input [7:0] ina;
input [7:0] inb;
begin
myadd = ina + inb;
end
endfunction // myadd
endmodule // ftest
module mytop (
input [ 7:0 ] a,
b,
input clk,
output [ 7:0 ] z
);
ftest u0( a, b, clk, z );
endmodule // mytop
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [7:0] a,b;
wire [7:0] z;
mytop u0 ( a, b, clk, z );
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x\n", cyc, z);
if (cyc==1) begin
a <= 8'h07;
b <= 8'h20;
end
if (cyc==2) begin
a <= 8'h8a;
b <= 8'h12;
end
if (cyc==3) begin
if (z !== 8'hdf) $stop;
a <= 8'h71;
b <= 8'hb2;
end
if (cyc==4) begin
if (z !== 8'hed) $stop;
end
if (cyc==5) begin
if (z !== 8'h4d) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule // mytop
module inv(
input [ 7:0 ] a,
output [ 7:0 ] z
);
wire [7:0] z = ~a;
endmodule
module ftest(
input [ 7:0 ] a,
b, // Test legal syntax
input clk,
output [ 7:0 ] z
);
wire [7:0] zi;
reg [7:0] z;
inv u1 (.a(myadd(a,b)),
.z(zi));
always @ ( posedge clk ) begin
z <= myadd( a, zi );
end
function [ 7:0 ] myadd;
input [7:0] ina;
input [7:0] inb;
begin
myadd = ina + inb;
end
endfunction // myadd
endmodule // ftest
module mytop (
input [ 7:0 ] a,
b,
input clk,
output [ 7:0 ] z
);
ftest u0( a, b, clk, z );
endmodule // mytop
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (clk);
input clk;
reg [7:0] a,b;
wire [7:0] z;
mytop u0 ( a, b, clk, z );
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x\n", cyc, z);
if (cyc==1) begin
a <= 8'h07;
b <= 8'h20;
end
if (cyc==2) begin
a <= 8'h8a;
b <= 8'h12;
end
if (cyc==3) begin
if (z !== 8'hdf) $stop;
a <= 8'h71;
b <= 8'hb2;
end
if (cyc==4) begin
if (z !== 8'hed) $stop;
end
if (cyc==5) begin
if (z !== 8'h4d) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule // mytop
module inv(
input [ 7:0 ] a,
output [ 7:0 ] z
);
wire [7:0] z = ~a;
endmodule
module ftest(
input [ 7:0 ] a,
b, // Test legal syntax
input clk,
output [ 7:0 ] z
);
wire [7:0] zi;
reg [7:0] z;
inv u1 (.a(myadd(a,b)),
.z(zi));
always @ ( posedge clk ) begin
z <= myadd( a, zi );
end
function [ 7:0 ] myadd;
input [7:0] ina;
input [7:0] inb;
begin
myadd = ina + inb;
end
endfunction // myadd
endmodule // ftest
module mytop (
input [ 7:0 ] a,
b,
input clk,
output [ 7:0 ] z
);
ftest u0( a, b, clk, z );
endmodule // mytop
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [2:0] q; // From test of Test.v
// End of automatics
Test test (
// Outputs
.q (q[2:0]),
// Inputs
.clk (clk),
.reset_l (crc[0]),
.enable (crc[2]),
.q_var0 (crc[19:10]),
.q_var2 (crc[29:20]),
.q_var4 (crc[39:30]),
.q_var6 (crc[49:40])
/*AUTOINST*/);
// Aggregate outputs into a single result vector
wire [63:0] result = {61'h0,q};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h58b162c58d6e35ba
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
input clk,
input reset_l,
input enable,
input [ 9:0] q_var0,
input [ 9:0] q_var2,
input [ 9:0] q_var4,
input [ 9:0] q_var6,
output reg [2:0] q
);
reg [7:0] p1_r [6:0];
always @(posedge clk) begin
if (!reset_l) begin
p1_r[0] <= 'b0;
p1_r[1] <= 'b0;
p1_r[2] <= 'b0;
p1_r[3] <= 'b0;
p1_r[4] <= 'b0;
p1_r[5] <= 'b0;
p1_r[6] <= 'b0;
end
else if (enable) begin : pass1
match(q_var0, q_var2, q_var4, q_var6);
end
end
// verilator lint_off WIDTH
always @(posedge clk) begin : l
reg [10:0] bd;
reg [3:0] idx;
q = 0;
bd = 0;
for (idx=0; idx<7; idx=idx+1) begin
q = idx+1;
bd = bd + p1_r[idx];
end
end
task match;
input [9:0] p0, p1, p2, p3;
reg [9:0] p[3:0];
begin
p[0] = p0;
p[1] = p1;
p[2] = p2;
p[3] = p3;
p1_r[0] = p[0];
p1_r[1] = p[1];
end
endtask
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// ORPSoC Testbench UART Decoder ////
//// ////
//// Description ////
//// ORPSoC Testbench UART output decoder ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - jb, [email protected] ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// Receieves and decodes 8-bit, 1 stop bit, no parity UART signals.
`timescale 1ns/1ns
module uart_decoder(clk, uart_tx);
input clk;
input uart_tx;
// Default baud of 115200, period (ns)
parameter uart_baudrate_period_ns = 8680;
// Something to trigger the task
always @(posedge clk)
uart_decoder;
task uart_decoder;
reg [7:0] tx_byte;
begin
while (uart_tx !== 1'b1)
@(uart_tx);
// Wait for start bit
while (uart_tx !== 1'b0)
@(uart_tx);
#(uart_baudrate_period_ns+(uart_baudrate_period_ns/2));
tx_byte[0] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[1] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[2] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[3] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[4] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[5] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[6] = uart_tx;
#uart_baudrate_period_ns;
tx_byte[7] = uart_tx;
#uart_baudrate_period_ns;
//Check for stop bit
if (uart_tx !== 1'b1)
begin
// Wait for return to idle
while (uart_tx !== 1'b1)
@(uart_tx);
end
// display the char
$write("%c", tx_byte);
end
endtask // user_uart_read_byte
endmodule // uart_decoder
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
reg signed [20:0] longp; initial longp = 21'shbbccc;
reg signed [20:0] longn; initial longn = 21'shbbccc; initial longn[20]=1'b1;
reg signed [40:0] quadp; initial quadp = 41'sh1_bbbb_cccc;
reg signed [40:0] quadn; initial quadn = 41'sh1_bbbb_cccc; initial quadn[40]=1'b1;
reg signed [80:0] widep; initial widep = 81'shbc_1234_5678_1234_5678;
reg signed [80:0] widen; initial widen = 81'shbc_1234_5678_1234_5678; initial widen[40]=1'b1;
initial begin
// Display formatting
$display("[%0t] lp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
longp, longp, longp, longp, longp, longp);
$display("[%0t] ln %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
longn, longn, longn, longn, longn, longn);
$display("[%0t] qp %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
quadp, quadp, quadp, quadp, quadp, quadp);
$display("[%0t] qn %%x=%x %%x=%x %%o=%o %%b=%b %%0d=%0d %%d=%d", $time,
quadn, quadn, quadn, quadn, quadn, quadn);
$display("[%0t] wp %%x=%x %%x=%x %%o=%o %%b=%b", $time,
widep, widep, widep, widep);
$display("[%0t] wn %%x=%x %%x=%x %%o=%o %%b=%b", $time,
widen, widen, widen, widen);
$display;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2005,2006 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module io_pins
( inout wire [15:0] io_0, inout wire [15:0] io_1,
input wire [15:0] reg_0, input wire [15:0] reg_1,
input clock, input rx_reset, input tx_reset,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
reg [15:0] io_0_oe,io_1_oe;
bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
// Upper 16 bits are mask for lower 16
always @(posedge clock)
if(serial_strobe)
case(serial_addr)
`FR_OE_0 : io_0_oe
<= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_1 : io_1_oe
<= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
endmodule // io_pins
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2005,2006 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module io_pins
( inout wire [15:0] io_0, inout wire [15:0] io_1,
input wire [15:0] reg_0, input wire [15:0] reg_1,
input clock, input rx_reset, input tx_reset,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
reg [15:0] io_0_oe,io_1_oe;
bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
// Upper 16 bits are mask for lower 16
always @(posedge clock)
if(serial_strobe)
case(serial_addr)
`FR_OE_0 : io_0_oe
<= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_1 : io_1_oe
<= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
endmodule // io_pins
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2005,2006 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module io_pins
( inout wire [15:0] io_0, inout wire [15:0] io_1,
input wire [15:0] reg_0, input wire [15:0] reg_1,
input clock, input rx_reset, input tx_reset,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
reg [15:0] io_0_oe,io_1_oe;
bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
// Upper 16 bits are mask for lower 16
always @(posedge clock)
if(serial_strobe)
case(serial_addr)
`FR_OE_0 : io_0_oe
<= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_1 : io_1_oe
<= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
endmodule // io_pins
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_slot_mgt
(
input pcie_user_clk,
input pcie_user_rst_n,
output hcmd_slot_rdy,
output [6:0] hcmd_slot_tag,
input hcmd_slot_alloc_en,
input hcmd_slot_free_en,
input [6:0] hcmd_slot_invalid_tag
);
localparam S_RESET_SEARCH_SLOT = 5'b00001;
localparam S_SEARCH_L1_SLOT = 5'b00010;
localparam S_SEARCH_L2_SLOT = 5'b00100;
localparam S_GNT_VAILD_SLOT = 5'b01000;
localparam S_VAILD_SLOT = 5'b10000;
reg [4:0] cur_state;
reg [4:0] next_state;
reg [127:0] r_slot_valid;
reg [127:0] r_slot_search_mask;
reg [127:0] r_slot_valid_mask;
reg [6:0] r_slot_tag;
reg r_slot_rdy;
reg [15:0] r_slot_l1_valid;
wire [7:0] w_slot_l1_mask;
wire r_slot_l1_ok;
//wire [7:0] w_slot_l2_valid;
wire [127:0] w_slot_l2_mask;
wire w_slot_l2_ok;
reg r_slot_free_en;
reg [6:0] r_slot_invalid_tag;
reg [127:0] r_slot_invalid_mask;
wire [127:0] w_slot_invalid_mask;
assign hcmd_slot_rdy = r_slot_rdy;
assign hcmd_slot_tag = r_slot_tag;
assign w_slot_l1_mask = { r_slot_search_mask[95],
r_slot_search_mask[79],
r_slot_search_mask[63],
r_slot_search_mask[47],
r_slot_search_mask[31],
r_slot_search_mask[15],
r_slot_search_mask[127],
r_slot_search_mask[111]};
always @ (*)
begin
case(w_slot_l1_mask) // synthesis parallel_case full_case
8'b00000001: r_slot_l1_valid <= r_slot_valid[15:0];
8'b00000010: r_slot_l1_valid <= r_slot_valid[31:16];
8'b00000100: r_slot_l1_valid <= r_slot_valid[47:32];
8'b00001000: r_slot_l1_valid <= r_slot_valid[63:48];
8'b00010000: r_slot_l1_valid <= r_slot_valid[79:64];
8'b00100000: r_slot_l1_valid <= r_slot_valid[95:80];
8'b01000000: r_slot_l1_valid <= r_slot_valid[111:96];
8'b10000000: r_slot_l1_valid <= r_slot_valid[127:112];
endcase
end
assign r_slot_l1_ok = (r_slot_l1_valid != 16'hFFFF);
assign w_slot_l2_mask = {r_slot_search_mask[126:0], r_slot_search_mask[127]};
assign w_slot_l2_ok = ((r_slot_valid & w_slot_l2_mask) == 0);
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RESET_SEARCH_SLOT;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RESET_SEARCH_SLOT: begin
next_state <= S_SEARCH_L1_SLOT;
end
S_SEARCH_L1_SLOT: begin
if(r_slot_l1_ok == 1)
next_state <= S_SEARCH_L2_SLOT;
else
next_state <= S_SEARCH_L1_SLOT;
end
S_SEARCH_L2_SLOT: begin
if(w_slot_l2_ok == 1)
next_state <= S_GNT_VAILD_SLOT;
else
next_state <= S_SEARCH_L2_SLOT;
end
S_GNT_VAILD_SLOT: begin
if(hcmd_slot_alloc_en == 1)
next_state <= S_VAILD_SLOT;
else
next_state <= S_GNT_VAILD_SLOT;
end
S_VAILD_SLOT: begin
next_state <= S_RESET_SEARCH_SLOT;
end
default: begin
next_state <= S_RESET_SEARCH_SLOT;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_RESET_SEARCH_SLOT: begin
r_slot_search_mask[127:112] <= 0;
r_slot_search_mask[111] <= 1'b1;
r_slot_search_mask[110:0] <= 0;
r_slot_tag <= 7'h6F;
end
S_SEARCH_L1_SLOT: begin
r_slot_search_mask[111] <= w_slot_l1_mask[7];
r_slot_search_mask[95] <= w_slot_l1_mask[6];
r_slot_search_mask[79] <= w_slot_l1_mask[5];
r_slot_search_mask[63] <= w_slot_l1_mask[4];
r_slot_search_mask[47] <= w_slot_l1_mask[3];
r_slot_search_mask[31] <= w_slot_l1_mask[2];
r_slot_search_mask[15] <= w_slot_l1_mask[1];
r_slot_search_mask[127] <= w_slot_l1_mask[0];
r_slot_tag <= r_slot_tag + 16;
end
S_SEARCH_L2_SLOT: begin
r_slot_search_mask <= w_slot_l2_mask;
r_slot_tag <= r_slot_tag + 1;
end
S_GNT_VAILD_SLOT: begin
end
S_VAILD_SLOT: begin
end
default: begin
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_slot_valid <= 0;
end
else begin
r_slot_valid <= (r_slot_valid | r_slot_valid_mask) & r_slot_invalid_mask;
//r_slot_valid <= (r_slot_valid | r_slot_valid_mask);
end
end
always @ (*)
begin
case(cur_state)
S_RESET_SEARCH_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
S_SEARCH_L1_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
S_SEARCH_L2_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
S_GNT_VAILD_SLOT: begin
r_slot_rdy <= 1;
r_slot_valid_mask <= 0;
end
S_VAILD_SLOT: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= r_slot_search_mask;
end
default: begin
r_slot_rdy <= 0;
r_slot_valid_mask <= 0;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
r_slot_free_en <= hcmd_slot_free_en;
r_slot_invalid_tag <= hcmd_slot_invalid_tag;
if(r_slot_free_en == 1)
r_slot_invalid_mask <= w_slot_invalid_mask;
else
r_slot_invalid_mask <= {128{1'b1}};
end
genvar i;
generate
for(i = 0; i < 128; i = i + 1)
begin : INVALID_TAG
assign w_slot_invalid_mask[i] = (r_slot_invalid_tag != i);
end
endgenerate
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/);
// IEEE: integer_atom_type
byte d_byte;
shortint d_shortint;
int d_int;
longint d_longint;
integer d_integer;
time d_time;
chandle d_chandle;
// IEEE: integer_atom_type
bit d_bit;
logic d_logic;
reg d_reg;
bit [0:0] d_bit1;
logic [0:0] d_logic1;
reg [0:0] d_reg1;
bit d_bitz;
logic d_logicz;
reg d_regz;
// IEEE: non_integer_type
//UNSUP shortreal d_shortreal;
real d_real;
realtime d_realtime;
initial begin
// below errors might cause spurious warnings
// verilator lint_off WIDTH
d_bitz[0] = 1'b1; // Illegal range
d_logicz[0] = 1'b1; // Illegal range
d_regz[0] = 1'b1; // Illegal range
`ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now
d_chandle[0] = 1'b1; // Illegal
`endif
d_real[0] = 1'b1; // Illegal
d_realtime[0] = 1'b1; // Illegal
// verilator lint_on WIDTH
d_byte[0] = 1'b1; // OK
d_shortint[0] = 1'b1; // OK
d_int[0] = 1'b1; // OK
d_longint[0] = 1'b1; // OK
d_integer[0] = 1'b1; // OK
d_time[0] = 1'b1; // OK
d_bit1[0] = 1'b1; // OK
d_logic1[0] = 1'b1; // OK
d_reg1[0] = 1'b1; // OK
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/);
// IEEE: integer_atom_type
byte d_byte;
shortint d_shortint;
int d_int;
longint d_longint;
integer d_integer;
time d_time;
chandle d_chandle;
// IEEE: integer_atom_type
bit d_bit;
logic d_logic;
reg d_reg;
bit [0:0] d_bit1;
logic [0:0] d_logic1;
reg [0:0] d_reg1;
bit d_bitz;
logic d_logicz;
reg d_regz;
// IEEE: non_integer_type
//UNSUP shortreal d_shortreal;
real d_real;
realtime d_realtime;
initial begin
// below errors might cause spurious warnings
// verilator lint_off WIDTH
d_bitz[0] = 1'b1; // Illegal range
d_logicz[0] = 1'b1; // Illegal range
d_regz[0] = 1'b1; // Illegal range
`ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now
d_chandle[0] = 1'b1; // Illegal
`endif
d_real[0] = 1'b1; // Illegal
d_realtime[0] = 1'b1; // Illegal
// verilator lint_on WIDTH
d_byte[0] = 1'b1; // OK
d_shortint[0] = 1'b1; // OK
d_int[0] = 1'b1; // OK
d_longint[0] = 1'b1; // OK
d_integer[0] = 1'b1; // OK
d_time[0] = 1'b1; // OK
d_bit1[0] = 1'b1; // OK
d_logic1[0] = 1'b1; // OK
d_reg1[0] = 1'b1; // OK
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/);
// IEEE: integer_atom_type
byte d_byte;
shortint d_shortint;
int d_int;
longint d_longint;
integer d_integer;
time d_time;
chandle d_chandle;
// IEEE: integer_atom_type
bit d_bit;
logic d_logic;
reg d_reg;
bit [0:0] d_bit1;
logic [0:0] d_logic1;
reg [0:0] d_reg1;
bit d_bitz;
logic d_logicz;
reg d_regz;
// IEEE: non_integer_type
//UNSUP shortreal d_shortreal;
real d_real;
realtime d_realtime;
initial begin
// below errors might cause spurious warnings
// verilator lint_off WIDTH
d_bitz[0] = 1'b1; // Illegal range
d_logicz[0] = 1'b1; // Illegal range
d_regz[0] = 1'b1; // Illegal range
`ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now
d_chandle[0] = 1'b1; // Illegal
`endif
d_real[0] = 1'b1; // Illegal
d_realtime[0] = 1'b1; // Illegal
// verilator lint_on WIDTH
d_byte[0] = 1'b1; // OK
d_shortint[0] = 1'b1; // OK
d_int[0] = 1'b1; // OK
d_longint[0] = 1'b1; // OK
d_integer[0] = 1'b1; // OK
d_time[0] = 1'b1; // OK
d_bit1[0] = 1'b1; // OK
d_logic1[0] = 1'b1; // OK
d_reg1[0] = 1'b1; // OK
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_fc_cntl
(
//PCIe user clock
input pcie_user_clk,
input pcie_user_rst_n,
// Flow Control
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
input tx_cfg_req,
output tx_cfg_gnt,
input [5:0] tx_buf_av,
output tx_cpld_gnt,
output tx_mrd_gnt,
output tx_mwr_gnt
);
parameter P_RX_CONSTRAINT_FC_CPLD = 32;
parameter P_RX_CONSTRAINT_FC_CPLH = 8;
parameter P_TX_CONSTRAINT_FC_CPLD = 1;
parameter P_TX_CONSTRAINT_FC_CPLH = 1;
parameter P_TX_CONSTRAINT_FC_NPD = 1;
parameter P_TX_CONSTRAINT_FC_NPH = 1;
parameter P_TX_CONSTRAINT_FC_PD = 32;
parameter P_TX_CONSTRAINT_FC_PH = 1;
localparam S_RX_AVAILABLE_FC_SEL = 2'b01;
localparam S_TX_AVAILABLE_FC_SEL = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg [11:0] r_rx_available_fc_cpld;
reg [7:0] r_rx_available_fc_cplh;
reg [11:0] r_rx_available_fc_npd;
reg [7:0] r_rx_available_fc_nph;
reg [11:0] r_rx_available_fc_pd;
reg [7:0] r_rx_available_fc_ph;
reg [11:0] r_tx_available_fc_cpld;
reg [7:0] r_tx_available_fc_cplh;
reg [11:0] r_tx_available_fc_npd;
reg [7:0] r_tx_available_fc_nph;
reg [11:0] r_tx_available_fc_pd;
reg [7:0] r_tx_available_fc_ph;
wire w_rx_available_fc_cpld;
wire w_rx_available_fc_cplh;
wire w_tx_available_fc_cpld;
wire w_tx_available_fc_cplh;
wire w_tx_available_fc_npd;
wire w_tx_available_fc_nph;
wire w_tx_available_fc_pd;
wire w_tx_available_fc_ph;
reg [2:0] r_fc_sel;
reg [1:0] r_rd_fc_sel;
reg [1:0] r_rd_fc_sel_d1;
reg [1:0] r_rd_fc_sel_d2;
reg r_tx_cpld_gnt;
reg r_tx_mrd_gnt;
reg r_tx_mwr_gnt;
assign fc_sel = r_fc_sel;
assign tx_cfg_gnt = 1'b1;
assign tx_cpld_gnt = r_tx_cpld_gnt;
assign tx_mrd_gnt = r_tx_mrd_gnt;
assign tx_mwr_gnt = r_tx_mwr_gnt;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RX_AVAILABLE_FC_SEL;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
next_state <= S_TX_AVAILABLE_FC_SEL;
end
S_TX_AVAILABLE_FC_SEL: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
default: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 2'b01;
end
S_TX_AVAILABLE_FC_SEL: begin
r_fc_sel <= 3'b100;
r_rd_fc_sel <= 2'b10;
end
default: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 2'b00;
end
endcase
end
assign w_rx_available_fc_cpld = (r_rx_available_fc_cpld > P_RX_CONSTRAINT_FC_CPLD);
assign w_rx_available_fc_cplh = (r_rx_available_fc_cplh > P_RX_CONSTRAINT_FC_CPLH);
assign w_tx_available_fc_cpld = (r_tx_available_fc_cpld > P_TX_CONSTRAINT_FC_CPLD);
assign w_tx_available_fc_cplh = (r_tx_available_fc_cplh > P_TX_CONSTRAINT_FC_CPLH);
assign w_tx_available_fc_npd = (r_tx_available_fc_npd > P_TX_CONSTRAINT_FC_NPD);
assign w_tx_available_fc_nph = (r_tx_available_fc_nph > P_TX_CONSTRAINT_FC_NPH);
assign w_tx_available_fc_pd = (r_tx_available_fc_pd > P_TX_CONSTRAINT_FC_PD);
assign w_tx_available_fc_ph = (r_tx_available_fc_ph > P_TX_CONSTRAINT_FC_PH);
always @ (posedge pcie_user_clk)
begin
r_tx_cpld_gnt <= w_tx_available_fc_cpld & w_tx_available_fc_cplh;
r_tx_mrd_gnt <= (w_tx_available_fc_npd & w_tx_available_fc_nph) & (w_rx_available_fc_cpld & w_rx_available_fc_cplh);
r_tx_mwr_gnt <= w_tx_available_fc_pd & w_tx_available_fc_ph;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rd_fc_sel_d1 <= 0;
r_rd_fc_sel_d2 <= 0;
end
else begin
r_rd_fc_sel_d1 <= r_rd_fc_sel;
r_rd_fc_sel_d2 <= r_rd_fc_sel_d1;
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rx_available_fc_cpld <= 0;
r_rx_available_fc_cplh <= 0;
r_rx_available_fc_npd <= 0;
r_rx_available_fc_nph <= 0;
r_rx_available_fc_pd <= 0;
r_rx_available_fc_ph <= 0;
r_tx_available_fc_cpld <= 0;
r_tx_available_fc_cplh <= 0;
r_tx_available_fc_npd <= 0;
r_tx_available_fc_nph <= 0;
r_tx_available_fc_pd <= 0;
r_tx_available_fc_ph <= 0;
end
else begin
if(r_rd_fc_sel_d2[0] == 1) begin
r_rx_available_fc_cpld <= fc_cpld;
r_rx_available_fc_cplh <= fc_cplh;
r_rx_available_fc_npd <= fc_npd;
r_rx_available_fc_nph <= fc_nph;
r_rx_available_fc_pd <= fc_pd;
r_rx_available_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[1] == 1) begin
r_tx_available_fc_cpld <= fc_cpld;
r_tx_available_fc_cplh <= fc_cplh;
r_tx_available_fc_npd <= fc_npd;
r_tx_available_fc_nph <= fc_nph;
r_tx_available_fc_pd <= fc_pd;
r_tx_available_fc_ph <= fc_ph;
end
end
end
/*
parameter P_RX_AVAILABLE_FC_CPLD = 36;
parameter P_RX_AVAILABLE_FC_CPLH = 36;
parameter P_TX_AVAILABLE_FC_CPLD = 36;
parameter P_TX_AVAILABLE_FC_CPLH = 36;
parameter P_TX_AVAILABLE_FC_NPD = 36;
parameter P_TX_AVAILABLE_FC_NPH = 36;
parameter P_TX_AVAILABLE_FC_PD = 36;
parameter P_TX_AVAILABLE_FC_PH = 36;
reg [11:0] r_rx_available_fc_cpld;
reg [7:0] r_rx_available_fc_cplh;
reg [11:0] r_rx_available_fc_npd;
reg [7:0] r_rx_available_fc_nph;
reg [11:0] r_rx_available_fc_pd;
reg [7:0] r_rx_available_fc_ph;
reg [11:0] r_rx_limit_fc_cpld;
reg [7:0] r_rx_limit_fc_cplh;
reg [11:0] r_rx_limit_fc_npd;
reg [7:0] r_rx_limit_fc_nph;
reg [11:0] r_rx_limit_fc_pd;
reg [7:0] r_rx_limit_fc_ph;
reg [11:0] r_rx_consumed_fc_cpld;
reg [7:0] r_rx_consumed_fc_cplh;
reg [11:0] r_rx_consumed_fc_npd;
reg [7:0] r_rx_consumed_fc_nph;
reg [11:0] r_rx_consumed_fc_pd;
reg [7:0] r_rx_consumed_fc_ph;
reg [11:0] r_tx_available_fc_cpld;
reg [7:0] r_tx_available_fc_cplh;
reg [11:0] r_tx_available_fc_npd;
reg [7:0] r_tx_available_fc_nph;
reg [11:0] r_tx_available_fc_pd;
reg [7:0] r_tx_available_fc_ph;
reg [11:0] r_tx_limit_fc_cpld;
reg [7:0] r_tx_limit_fc_cplh;
reg [11:0] r_tx_limit_fc_npd;
reg [7:0] r_tx_limit_fc_nph;
reg [11:0] r_tx_limit_fc_pd;
reg [7:0] r_tx_limit_fc_ph;
reg [11:0] r_tx_consumed_fc_cpld;
reg [7:0] r_tx_consumed_fc_cplh;
reg [11:0] r_tx_consumed_fc_npd;
reg [7:0] r_tx_consumed_fc_nph;
reg [11:0] r_tx_consumed_fc_pd;
reg [7:0] r_tx_consumed_fc_ph;
reg [2:0] r_fc_sel;
reg [5:0] r_rd_fc_sel;
reg [5:0] r_rd_fc_sel_d1;
reg [5:0] r_rd_fc_sel_d2;
reg r_tx_cpld_gnt;
reg r_tx_mrd_gnt;
reg r_tx_mwr_gnt;
assign tx_cfg_gnt = 1'b1;
assign tx_cpld_gnt = r_tx_cpld_gnt;
assign tx_mrd_gnt = r_tx_mrd_gnt;
assign tx_mwr_gnt = r_tx_mwr_gnt;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RX_AVAILABLE_FC_SEL;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
next_state <= S_RX_LITMIT_FC_SEL;
end
S_RX_LITMIT_FC_SEL: begin
next_state <= S_RX_CONSUMED_FC_SEL;
end
S_RX_CONSUMED_FC_SEL: begin
next_state <= S_TX_AVAILABLE_FC_SEL;
end
S_TX_AVAILABLE_FC_SEL: begin
next_state <= S_TX_LITMIT_FC_SEL;
end
S_TX_LITMIT_FC_SEL: begin
next_state <= S_TX_CONSUMED_FC_SEL;
end
S_TX_CONSUMED_FC_SEL: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
default: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 6'b000001;
end
S_RX_LITMIT_FC_SEL: begin
r_fc_sel <= 3'b001;
r_rd_fc_sel <= 6'b000010;
end
S_RX_CONSUMED_FC_SEL: begin
r_fc_sel <= 3'b010;
r_rd_fc_sel <= 6'b000100;
end
S_TX_AVAILABLE_FC_SEL: begi
r_fc_sel <= 3'b100;
r_rd_fc_sel <= 6'b001000;
end
S_TX_LITMIT_FC_SEL: begin
r_fc_sel <= 3'b101;
r_rd_fc_sel <= 6'b010000;
end
S_TX_CONSUMED_FC_SEL: begin
r_fc_sel <= 3'b110;
r_rd_fc_sel <= 6'b100000;
end
default: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 6'b000000;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
r_tx_cpld_gnt;
r_tx_mrd_gnt;
r_tx_mwr_gnt;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rd_fc_sel_d1 <= 0;
r_rd_fc_sel_d2 <= 0;
end
else begin
r_rd_fc_sel_d1 <= r_rd_fc_sel;
r_rd_fc_sel_d2 <= r_rd_fc_sel_d1;
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rx_available_fc_cpld <= 0;
r_rx_available_fc_cplh <= 0;
r_rx_available_fc_npd <= 0;
r_rx_available_fc_nph <= 0;
r_rx_available_fc_pd <= 0;
r_rx_available_fc_ph <= 0;
r_rx_limit_fc_cpld <= 0;
r_rx_limit_fc_cplh <= 0;
r_rx_limit_fc_npd <= 0;
r_rx_limit_fc_nph <= 0;
r_rx_limit_fc_pd <= 0;
r_rx_limit_fc_ph <= 0;
r_rx_consumed_fc_cpld <= 0;
r_rx_consumed_fc_cplh <= 0;
r_rx_consumed_fc_npd <= 0;
r_rx_consumed_fc_nph <= 0;
r_rx_consumed_fc_pd <= 0;
r_rx_consumed_fc_ph <= 0;
r_tx_available_fc_cpld <= 0;
r_tx_available_fc_cplh <= 0;
r_tx_available_fc_npd <= 0;
r_tx_available_fc_nph <= 0;
r_tx_available_fc_pd <= 0;
r_tx_available_fc_ph <= 0;
r_tx_limit_fc_cpld <= 0;
r_tx_limit_fc_cplh <= 0;
r_tx_limit_fc_npd <= 0;
r_tx_limit_fc_nph <= 0;
r_tx_limit_fc_pd <= 0;
r_tx_limit_fc_ph <= 0;
r_tx_consumed_fc_cpld <= 0;
r_tx_consumed_fc_cplh <= 0;
r_tx_consumed_fc_npd <= 0;
r_tx_consumed_fc_nph <= 0;
r_tx_consumed_fc_pd <= 0;
r_tx_consumed_fc_ph <= 0;
end
else begin
if(r_rd_fc_sel_d2[0] == 1) begin
r_rx_available_fc_cpld <= fc_cpld;
r_rx_available_fc_cplh <= fc_cplh;
r_rx_available_fc_npd <= fc_npd;
r_rx_available_fc_nph <= fc_nph;
r_rx_available_fc_pd <= fc_pd;
r_rx_available_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[1] == 1) begin
r_rx_limit_fc_cpld <= fc_cpld;
r_rx_limit_fc_cplh <= fc_cplh;
r_rx_limit_fc_npd <= fc_npd;
r_rx_limit_fc_nph <= fc_nph;
r_rx_limit_fc_pd <= fc_pd;
r_rx_limit_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[2] == 1) begin
r_rx_consumed_fc_cpld <= fc_cpld;
r_rx_consumed_fc_cplh <= fc_cplh;
r_rx_consumed_fc_npd <= fc_npd;
r_rx_consumed_fc_nph <= fc_nph;
r_rx_consumed_fc_pd <= fc_pd;
r_rx_consumed_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[3] == 1) begin
r_tx_available_fc_cpld <= fc_cpld;
r_tx_available_fc_cplh <= fc_cplh;
r_tx_available_fc_npd <= fc_npd;
r_tx_available_fc_nph <= fc_nph;
r_tx_available_fc_pd <= fc_pd;
r_tx_available_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[4] == 1) begin
r_tx_limit_fc_cpld <= fc_cpld;
r_tx_limit_fc_cplh <= fc_cplh;
r_tx_limit_fc_npd <= fc_npd;
r_tx_limit_fc_nph <= fc_nph;
r_tx_limit_fc_pd <= fc_pd;
r_tx_limit_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[5] == 1) begin
r_tx_consumed_fc_cpld <= fc_cpld;
r_tx_consumed_fc_cplh <= fc_cplh;
r_tx_consumed_fc_npd <= fc_npd;
r_tx_consumed_fc_nph <= fc_nph;
r_tx_consumed_fc_pd <= fc_pd;
r_tx_consumed_fc_ph <= fc_ph;
end
end
end
*/
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_fc_cntl
(
//PCIe user clock
input pcie_user_clk,
input pcie_user_rst_n,
// Flow Control
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
input tx_cfg_req,
output tx_cfg_gnt,
input [5:0] tx_buf_av,
output tx_cpld_gnt,
output tx_mrd_gnt,
output tx_mwr_gnt
);
parameter P_RX_CONSTRAINT_FC_CPLD = 32;
parameter P_RX_CONSTRAINT_FC_CPLH = 8;
parameter P_TX_CONSTRAINT_FC_CPLD = 1;
parameter P_TX_CONSTRAINT_FC_CPLH = 1;
parameter P_TX_CONSTRAINT_FC_NPD = 1;
parameter P_TX_CONSTRAINT_FC_NPH = 1;
parameter P_TX_CONSTRAINT_FC_PD = 32;
parameter P_TX_CONSTRAINT_FC_PH = 1;
localparam S_RX_AVAILABLE_FC_SEL = 2'b01;
localparam S_TX_AVAILABLE_FC_SEL = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg [11:0] r_rx_available_fc_cpld;
reg [7:0] r_rx_available_fc_cplh;
reg [11:0] r_rx_available_fc_npd;
reg [7:0] r_rx_available_fc_nph;
reg [11:0] r_rx_available_fc_pd;
reg [7:0] r_rx_available_fc_ph;
reg [11:0] r_tx_available_fc_cpld;
reg [7:0] r_tx_available_fc_cplh;
reg [11:0] r_tx_available_fc_npd;
reg [7:0] r_tx_available_fc_nph;
reg [11:0] r_tx_available_fc_pd;
reg [7:0] r_tx_available_fc_ph;
wire w_rx_available_fc_cpld;
wire w_rx_available_fc_cplh;
wire w_tx_available_fc_cpld;
wire w_tx_available_fc_cplh;
wire w_tx_available_fc_npd;
wire w_tx_available_fc_nph;
wire w_tx_available_fc_pd;
wire w_tx_available_fc_ph;
reg [2:0] r_fc_sel;
reg [1:0] r_rd_fc_sel;
reg [1:0] r_rd_fc_sel_d1;
reg [1:0] r_rd_fc_sel_d2;
reg r_tx_cpld_gnt;
reg r_tx_mrd_gnt;
reg r_tx_mwr_gnt;
assign fc_sel = r_fc_sel;
assign tx_cfg_gnt = 1'b1;
assign tx_cpld_gnt = r_tx_cpld_gnt;
assign tx_mrd_gnt = r_tx_mrd_gnt;
assign tx_mwr_gnt = r_tx_mwr_gnt;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RX_AVAILABLE_FC_SEL;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
next_state <= S_TX_AVAILABLE_FC_SEL;
end
S_TX_AVAILABLE_FC_SEL: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
default: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 2'b01;
end
S_TX_AVAILABLE_FC_SEL: begin
r_fc_sel <= 3'b100;
r_rd_fc_sel <= 2'b10;
end
default: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 2'b00;
end
endcase
end
assign w_rx_available_fc_cpld = (r_rx_available_fc_cpld > P_RX_CONSTRAINT_FC_CPLD);
assign w_rx_available_fc_cplh = (r_rx_available_fc_cplh > P_RX_CONSTRAINT_FC_CPLH);
assign w_tx_available_fc_cpld = (r_tx_available_fc_cpld > P_TX_CONSTRAINT_FC_CPLD);
assign w_tx_available_fc_cplh = (r_tx_available_fc_cplh > P_TX_CONSTRAINT_FC_CPLH);
assign w_tx_available_fc_npd = (r_tx_available_fc_npd > P_TX_CONSTRAINT_FC_NPD);
assign w_tx_available_fc_nph = (r_tx_available_fc_nph > P_TX_CONSTRAINT_FC_NPH);
assign w_tx_available_fc_pd = (r_tx_available_fc_pd > P_TX_CONSTRAINT_FC_PD);
assign w_tx_available_fc_ph = (r_tx_available_fc_ph > P_TX_CONSTRAINT_FC_PH);
always @ (posedge pcie_user_clk)
begin
r_tx_cpld_gnt <= w_tx_available_fc_cpld & w_tx_available_fc_cplh;
r_tx_mrd_gnt <= (w_tx_available_fc_npd & w_tx_available_fc_nph) & (w_rx_available_fc_cpld & w_rx_available_fc_cplh);
r_tx_mwr_gnt <= w_tx_available_fc_pd & w_tx_available_fc_ph;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rd_fc_sel_d1 <= 0;
r_rd_fc_sel_d2 <= 0;
end
else begin
r_rd_fc_sel_d1 <= r_rd_fc_sel;
r_rd_fc_sel_d2 <= r_rd_fc_sel_d1;
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rx_available_fc_cpld <= 0;
r_rx_available_fc_cplh <= 0;
r_rx_available_fc_npd <= 0;
r_rx_available_fc_nph <= 0;
r_rx_available_fc_pd <= 0;
r_rx_available_fc_ph <= 0;
r_tx_available_fc_cpld <= 0;
r_tx_available_fc_cplh <= 0;
r_tx_available_fc_npd <= 0;
r_tx_available_fc_nph <= 0;
r_tx_available_fc_pd <= 0;
r_tx_available_fc_ph <= 0;
end
else begin
if(r_rd_fc_sel_d2[0] == 1) begin
r_rx_available_fc_cpld <= fc_cpld;
r_rx_available_fc_cplh <= fc_cplh;
r_rx_available_fc_npd <= fc_npd;
r_rx_available_fc_nph <= fc_nph;
r_rx_available_fc_pd <= fc_pd;
r_rx_available_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[1] == 1) begin
r_tx_available_fc_cpld <= fc_cpld;
r_tx_available_fc_cplh <= fc_cplh;
r_tx_available_fc_npd <= fc_npd;
r_tx_available_fc_nph <= fc_nph;
r_tx_available_fc_pd <= fc_pd;
r_tx_available_fc_ph <= fc_ph;
end
end
end
/*
parameter P_RX_AVAILABLE_FC_CPLD = 36;
parameter P_RX_AVAILABLE_FC_CPLH = 36;
parameter P_TX_AVAILABLE_FC_CPLD = 36;
parameter P_TX_AVAILABLE_FC_CPLH = 36;
parameter P_TX_AVAILABLE_FC_NPD = 36;
parameter P_TX_AVAILABLE_FC_NPH = 36;
parameter P_TX_AVAILABLE_FC_PD = 36;
parameter P_TX_AVAILABLE_FC_PH = 36;
reg [11:0] r_rx_available_fc_cpld;
reg [7:0] r_rx_available_fc_cplh;
reg [11:0] r_rx_available_fc_npd;
reg [7:0] r_rx_available_fc_nph;
reg [11:0] r_rx_available_fc_pd;
reg [7:0] r_rx_available_fc_ph;
reg [11:0] r_rx_limit_fc_cpld;
reg [7:0] r_rx_limit_fc_cplh;
reg [11:0] r_rx_limit_fc_npd;
reg [7:0] r_rx_limit_fc_nph;
reg [11:0] r_rx_limit_fc_pd;
reg [7:0] r_rx_limit_fc_ph;
reg [11:0] r_rx_consumed_fc_cpld;
reg [7:0] r_rx_consumed_fc_cplh;
reg [11:0] r_rx_consumed_fc_npd;
reg [7:0] r_rx_consumed_fc_nph;
reg [11:0] r_rx_consumed_fc_pd;
reg [7:0] r_rx_consumed_fc_ph;
reg [11:0] r_tx_available_fc_cpld;
reg [7:0] r_tx_available_fc_cplh;
reg [11:0] r_tx_available_fc_npd;
reg [7:0] r_tx_available_fc_nph;
reg [11:0] r_tx_available_fc_pd;
reg [7:0] r_tx_available_fc_ph;
reg [11:0] r_tx_limit_fc_cpld;
reg [7:0] r_tx_limit_fc_cplh;
reg [11:0] r_tx_limit_fc_npd;
reg [7:0] r_tx_limit_fc_nph;
reg [11:0] r_tx_limit_fc_pd;
reg [7:0] r_tx_limit_fc_ph;
reg [11:0] r_tx_consumed_fc_cpld;
reg [7:0] r_tx_consumed_fc_cplh;
reg [11:0] r_tx_consumed_fc_npd;
reg [7:0] r_tx_consumed_fc_nph;
reg [11:0] r_tx_consumed_fc_pd;
reg [7:0] r_tx_consumed_fc_ph;
reg [2:0] r_fc_sel;
reg [5:0] r_rd_fc_sel;
reg [5:0] r_rd_fc_sel_d1;
reg [5:0] r_rd_fc_sel_d2;
reg r_tx_cpld_gnt;
reg r_tx_mrd_gnt;
reg r_tx_mwr_gnt;
assign tx_cfg_gnt = 1'b1;
assign tx_cpld_gnt = r_tx_cpld_gnt;
assign tx_mrd_gnt = r_tx_mrd_gnt;
assign tx_mwr_gnt = r_tx_mwr_gnt;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RX_AVAILABLE_FC_SEL;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
next_state <= S_RX_LITMIT_FC_SEL;
end
S_RX_LITMIT_FC_SEL: begin
next_state <= S_RX_CONSUMED_FC_SEL;
end
S_RX_CONSUMED_FC_SEL: begin
next_state <= S_TX_AVAILABLE_FC_SEL;
end
S_TX_AVAILABLE_FC_SEL: begin
next_state <= S_TX_LITMIT_FC_SEL;
end
S_TX_LITMIT_FC_SEL: begin
next_state <= S_TX_CONSUMED_FC_SEL;
end
S_TX_CONSUMED_FC_SEL: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
default: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 6'b000001;
end
S_RX_LITMIT_FC_SEL: begin
r_fc_sel <= 3'b001;
r_rd_fc_sel <= 6'b000010;
end
S_RX_CONSUMED_FC_SEL: begin
r_fc_sel <= 3'b010;
r_rd_fc_sel <= 6'b000100;
end
S_TX_AVAILABLE_FC_SEL: begi
r_fc_sel <= 3'b100;
r_rd_fc_sel <= 6'b001000;
end
S_TX_LITMIT_FC_SEL: begin
r_fc_sel <= 3'b101;
r_rd_fc_sel <= 6'b010000;
end
S_TX_CONSUMED_FC_SEL: begin
r_fc_sel <= 3'b110;
r_rd_fc_sel <= 6'b100000;
end
default: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 6'b000000;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
r_tx_cpld_gnt;
r_tx_mrd_gnt;
r_tx_mwr_gnt;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rd_fc_sel_d1 <= 0;
r_rd_fc_sel_d2 <= 0;
end
else begin
r_rd_fc_sel_d1 <= r_rd_fc_sel;
r_rd_fc_sel_d2 <= r_rd_fc_sel_d1;
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rx_available_fc_cpld <= 0;
r_rx_available_fc_cplh <= 0;
r_rx_available_fc_npd <= 0;
r_rx_available_fc_nph <= 0;
r_rx_available_fc_pd <= 0;
r_rx_available_fc_ph <= 0;
r_rx_limit_fc_cpld <= 0;
r_rx_limit_fc_cplh <= 0;
r_rx_limit_fc_npd <= 0;
r_rx_limit_fc_nph <= 0;
r_rx_limit_fc_pd <= 0;
r_rx_limit_fc_ph <= 0;
r_rx_consumed_fc_cpld <= 0;
r_rx_consumed_fc_cplh <= 0;
r_rx_consumed_fc_npd <= 0;
r_rx_consumed_fc_nph <= 0;
r_rx_consumed_fc_pd <= 0;
r_rx_consumed_fc_ph <= 0;
r_tx_available_fc_cpld <= 0;
r_tx_available_fc_cplh <= 0;
r_tx_available_fc_npd <= 0;
r_tx_available_fc_nph <= 0;
r_tx_available_fc_pd <= 0;
r_tx_available_fc_ph <= 0;
r_tx_limit_fc_cpld <= 0;
r_tx_limit_fc_cplh <= 0;
r_tx_limit_fc_npd <= 0;
r_tx_limit_fc_nph <= 0;
r_tx_limit_fc_pd <= 0;
r_tx_limit_fc_ph <= 0;
r_tx_consumed_fc_cpld <= 0;
r_tx_consumed_fc_cplh <= 0;
r_tx_consumed_fc_npd <= 0;
r_tx_consumed_fc_nph <= 0;
r_tx_consumed_fc_pd <= 0;
r_tx_consumed_fc_ph <= 0;
end
else begin
if(r_rd_fc_sel_d2[0] == 1) begin
r_rx_available_fc_cpld <= fc_cpld;
r_rx_available_fc_cplh <= fc_cplh;
r_rx_available_fc_npd <= fc_npd;
r_rx_available_fc_nph <= fc_nph;
r_rx_available_fc_pd <= fc_pd;
r_rx_available_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[1] == 1) begin
r_rx_limit_fc_cpld <= fc_cpld;
r_rx_limit_fc_cplh <= fc_cplh;
r_rx_limit_fc_npd <= fc_npd;
r_rx_limit_fc_nph <= fc_nph;
r_rx_limit_fc_pd <= fc_pd;
r_rx_limit_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[2] == 1) begin
r_rx_consumed_fc_cpld <= fc_cpld;
r_rx_consumed_fc_cplh <= fc_cplh;
r_rx_consumed_fc_npd <= fc_npd;
r_rx_consumed_fc_nph <= fc_nph;
r_rx_consumed_fc_pd <= fc_pd;
r_rx_consumed_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[3] == 1) begin
r_tx_available_fc_cpld <= fc_cpld;
r_tx_available_fc_cplh <= fc_cplh;
r_tx_available_fc_npd <= fc_npd;
r_tx_available_fc_nph <= fc_nph;
r_tx_available_fc_pd <= fc_pd;
r_tx_available_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[4] == 1) begin
r_tx_limit_fc_cpld <= fc_cpld;
r_tx_limit_fc_cplh <= fc_cplh;
r_tx_limit_fc_npd <= fc_npd;
r_tx_limit_fc_nph <= fc_nph;
r_tx_limit_fc_pd <= fc_pd;
r_tx_limit_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[5] == 1) begin
r_tx_consumed_fc_cpld <= fc_cpld;
r_tx_consumed_fc_cplh <= fc_cplh;
r_tx_consumed_fc_npd <= fc_npd;
r_tx_consumed_fc_nph <= fc_nph;
r_tx_consumed_fc_pd <= fc_pd;
r_tx_consumed_fc_ph <= fc_ph;
end
end
end
*/
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_fc_cntl
(
//PCIe user clock
input pcie_user_clk,
input pcie_user_rst_n,
// Flow Control
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
input tx_cfg_req,
output tx_cfg_gnt,
input [5:0] tx_buf_av,
output tx_cpld_gnt,
output tx_mrd_gnt,
output tx_mwr_gnt
);
parameter P_RX_CONSTRAINT_FC_CPLD = 32;
parameter P_RX_CONSTRAINT_FC_CPLH = 8;
parameter P_TX_CONSTRAINT_FC_CPLD = 1;
parameter P_TX_CONSTRAINT_FC_CPLH = 1;
parameter P_TX_CONSTRAINT_FC_NPD = 1;
parameter P_TX_CONSTRAINT_FC_NPH = 1;
parameter P_TX_CONSTRAINT_FC_PD = 32;
parameter P_TX_CONSTRAINT_FC_PH = 1;
localparam S_RX_AVAILABLE_FC_SEL = 2'b01;
localparam S_TX_AVAILABLE_FC_SEL = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg [11:0] r_rx_available_fc_cpld;
reg [7:0] r_rx_available_fc_cplh;
reg [11:0] r_rx_available_fc_npd;
reg [7:0] r_rx_available_fc_nph;
reg [11:0] r_rx_available_fc_pd;
reg [7:0] r_rx_available_fc_ph;
reg [11:0] r_tx_available_fc_cpld;
reg [7:0] r_tx_available_fc_cplh;
reg [11:0] r_tx_available_fc_npd;
reg [7:0] r_tx_available_fc_nph;
reg [11:0] r_tx_available_fc_pd;
reg [7:0] r_tx_available_fc_ph;
wire w_rx_available_fc_cpld;
wire w_rx_available_fc_cplh;
wire w_tx_available_fc_cpld;
wire w_tx_available_fc_cplh;
wire w_tx_available_fc_npd;
wire w_tx_available_fc_nph;
wire w_tx_available_fc_pd;
wire w_tx_available_fc_ph;
reg [2:0] r_fc_sel;
reg [1:0] r_rd_fc_sel;
reg [1:0] r_rd_fc_sel_d1;
reg [1:0] r_rd_fc_sel_d2;
reg r_tx_cpld_gnt;
reg r_tx_mrd_gnt;
reg r_tx_mwr_gnt;
assign fc_sel = r_fc_sel;
assign tx_cfg_gnt = 1'b1;
assign tx_cpld_gnt = r_tx_cpld_gnt;
assign tx_mrd_gnt = r_tx_mrd_gnt;
assign tx_mwr_gnt = r_tx_mwr_gnt;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RX_AVAILABLE_FC_SEL;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
next_state <= S_TX_AVAILABLE_FC_SEL;
end
S_TX_AVAILABLE_FC_SEL: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
default: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 2'b01;
end
S_TX_AVAILABLE_FC_SEL: begin
r_fc_sel <= 3'b100;
r_rd_fc_sel <= 2'b10;
end
default: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 2'b00;
end
endcase
end
assign w_rx_available_fc_cpld = (r_rx_available_fc_cpld > P_RX_CONSTRAINT_FC_CPLD);
assign w_rx_available_fc_cplh = (r_rx_available_fc_cplh > P_RX_CONSTRAINT_FC_CPLH);
assign w_tx_available_fc_cpld = (r_tx_available_fc_cpld > P_TX_CONSTRAINT_FC_CPLD);
assign w_tx_available_fc_cplh = (r_tx_available_fc_cplh > P_TX_CONSTRAINT_FC_CPLH);
assign w_tx_available_fc_npd = (r_tx_available_fc_npd > P_TX_CONSTRAINT_FC_NPD);
assign w_tx_available_fc_nph = (r_tx_available_fc_nph > P_TX_CONSTRAINT_FC_NPH);
assign w_tx_available_fc_pd = (r_tx_available_fc_pd > P_TX_CONSTRAINT_FC_PD);
assign w_tx_available_fc_ph = (r_tx_available_fc_ph > P_TX_CONSTRAINT_FC_PH);
always @ (posedge pcie_user_clk)
begin
r_tx_cpld_gnt <= w_tx_available_fc_cpld & w_tx_available_fc_cplh;
r_tx_mrd_gnt <= (w_tx_available_fc_npd & w_tx_available_fc_nph) & (w_rx_available_fc_cpld & w_rx_available_fc_cplh);
r_tx_mwr_gnt <= w_tx_available_fc_pd & w_tx_available_fc_ph;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rd_fc_sel_d1 <= 0;
r_rd_fc_sel_d2 <= 0;
end
else begin
r_rd_fc_sel_d1 <= r_rd_fc_sel;
r_rd_fc_sel_d2 <= r_rd_fc_sel_d1;
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rx_available_fc_cpld <= 0;
r_rx_available_fc_cplh <= 0;
r_rx_available_fc_npd <= 0;
r_rx_available_fc_nph <= 0;
r_rx_available_fc_pd <= 0;
r_rx_available_fc_ph <= 0;
r_tx_available_fc_cpld <= 0;
r_tx_available_fc_cplh <= 0;
r_tx_available_fc_npd <= 0;
r_tx_available_fc_nph <= 0;
r_tx_available_fc_pd <= 0;
r_tx_available_fc_ph <= 0;
end
else begin
if(r_rd_fc_sel_d2[0] == 1) begin
r_rx_available_fc_cpld <= fc_cpld;
r_rx_available_fc_cplh <= fc_cplh;
r_rx_available_fc_npd <= fc_npd;
r_rx_available_fc_nph <= fc_nph;
r_rx_available_fc_pd <= fc_pd;
r_rx_available_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[1] == 1) begin
r_tx_available_fc_cpld <= fc_cpld;
r_tx_available_fc_cplh <= fc_cplh;
r_tx_available_fc_npd <= fc_npd;
r_tx_available_fc_nph <= fc_nph;
r_tx_available_fc_pd <= fc_pd;
r_tx_available_fc_ph <= fc_ph;
end
end
end
/*
parameter P_RX_AVAILABLE_FC_CPLD = 36;
parameter P_RX_AVAILABLE_FC_CPLH = 36;
parameter P_TX_AVAILABLE_FC_CPLD = 36;
parameter P_TX_AVAILABLE_FC_CPLH = 36;
parameter P_TX_AVAILABLE_FC_NPD = 36;
parameter P_TX_AVAILABLE_FC_NPH = 36;
parameter P_TX_AVAILABLE_FC_PD = 36;
parameter P_TX_AVAILABLE_FC_PH = 36;
reg [11:0] r_rx_available_fc_cpld;
reg [7:0] r_rx_available_fc_cplh;
reg [11:0] r_rx_available_fc_npd;
reg [7:0] r_rx_available_fc_nph;
reg [11:0] r_rx_available_fc_pd;
reg [7:0] r_rx_available_fc_ph;
reg [11:0] r_rx_limit_fc_cpld;
reg [7:0] r_rx_limit_fc_cplh;
reg [11:0] r_rx_limit_fc_npd;
reg [7:0] r_rx_limit_fc_nph;
reg [11:0] r_rx_limit_fc_pd;
reg [7:0] r_rx_limit_fc_ph;
reg [11:0] r_rx_consumed_fc_cpld;
reg [7:0] r_rx_consumed_fc_cplh;
reg [11:0] r_rx_consumed_fc_npd;
reg [7:0] r_rx_consumed_fc_nph;
reg [11:0] r_rx_consumed_fc_pd;
reg [7:0] r_rx_consumed_fc_ph;
reg [11:0] r_tx_available_fc_cpld;
reg [7:0] r_tx_available_fc_cplh;
reg [11:0] r_tx_available_fc_npd;
reg [7:0] r_tx_available_fc_nph;
reg [11:0] r_tx_available_fc_pd;
reg [7:0] r_tx_available_fc_ph;
reg [11:0] r_tx_limit_fc_cpld;
reg [7:0] r_tx_limit_fc_cplh;
reg [11:0] r_tx_limit_fc_npd;
reg [7:0] r_tx_limit_fc_nph;
reg [11:0] r_tx_limit_fc_pd;
reg [7:0] r_tx_limit_fc_ph;
reg [11:0] r_tx_consumed_fc_cpld;
reg [7:0] r_tx_consumed_fc_cplh;
reg [11:0] r_tx_consumed_fc_npd;
reg [7:0] r_tx_consumed_fc_nph;
reg [11:0] r_tx_consumed_fc_pd;
reg [7:0] r_tx_consumed_fc_ph;
reg [2:0] r_fc_sel;
reg [5:0] r_rd_fc_sel;
reg [5:0] r_rd_fc_sel_d1;
reg [5:0] r_rd_fc_sel_d2;
reg r_tx_cpld_gnt;
reg r_tx_mrd_gnt;
reg r_tx_mwr_gnt;
assign tx_cfg_gnt = 1'b1;
assign tx_cpld_gnt = r_tx_cpld_gnt;
assign tx_mrd_gnt = r_tx_mrd_gnt;
assign tx_mwr_gnt = r_tx_mwr_gnt;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RX_AVAILABLE_FC_SEL;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
next_state <= S_RX_LITMIT_FC_SEL;
end
S_RX_LITMIT_FC_SEL: begin
next_state <= S_RX_CONSUMED_FC_SEL;
end
S_RX_CONSUMED_FC_SEL: begin
next_state <= S_TX_AVAILABLE_FC_SEL;
end
S_TX_AVAILABLE_FC_SEL: begin
next_state <= S_TX_LITMIT_FC_SEL;
end
S_TX_LITMIT_FC_SEL: begin
next_state <= S_TX_CONSUMED_FC_SEL;
end
S_TX_CONSUMED_FC_SEL: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
default: begin
next_state <= S_RX_AVAILABLE_FC_SEL;
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RX_AVAILABLE_FC_SEL: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 6'b000001;
end
S_RX_LITMIT_FC_SEL: begin
r_fc_sel <= 3'b001;
r_rd_fc_sel <= 6'b000010;
end
S_RX_CONSUMED_FC_SEL: begin
r_fc_sel <= 3'b010;
r_rd_fc_sel <= 6'b000100;
end
S_TX_AVAILABLE_FC_SEL: begi
r_fc_sel <= 3'b100;
r_rd_fc_sel <= 6'b001000;
end
S_TX_LITMIT_FC_SEL: begin
r_fc_sel <= 3'b101;
r_rd_fc_sel <= 6'b010000;
end
S_TX_CONSUMED_FC_SEL: begin
r_fc_sel <= 3'b110;
r_rd_fc_sel <= 6'b100000;
end
default: begin
r_fc_sel <= 3'b000;
r_rd_fc_sel <= 6'b000000;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
r_tx_cpld_gnt;
r_tx_mrd_gnt;
r_tx_mwr_gnt;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rd_fc_sel_d1 <= 0;
r_rd_fc_sel_d2 <= 0;
end
else begin
r_rd_fc_sel_d1 <= r_rd_fc_sel;
r_rd_fc_sel_d2 <= r_rd_fc_sel_d1;
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_rx_available_fc_cpld <= 0;
r_rx_available_fc_cplh <= 0;
r_rx_available_fc_npd <= 0;
r_rx_available_fc_nph <= 0;
r_rx_available_fc_pd <= 0;
r_rx_available_fc_ph <= 0;
r_rx_limit_fc_cpld <= 0;
r_rx_limit_fc_cplh <= 0;
r_rx_limit_fc_npd <= 0;
r_rx_limit_fc_nph <= 0;
r_rx_limit_fc_pd <= 0;
r_rx_limit_fc_ph <= 0;
r_rx_consumed_fc_cpld <= 0;
r_rx_consumed_fc_cplh <= 0;
r_rx_consumed_fc_npd <= 0;
r_rx_consumed_fc_nph <= 0;
r_rx_consumed_fc_pd <= 0;
r_rx_consumed_fc_ph <= 0;
r_tx_available_fc_cpld <= 0;
r_tx_available_fc_cplh <= 0;
r_tx_available_fc_npd <= 0;
r_tx_available_fc_nph <= 0;
r_tx_available_fc_pd <= 0;
r_tx_available_fc_ph <= 0;
r_tx_limit_fc_cpld <= 0;
r_tx_limit_fc_cplh <= 0;
r_tx_limit_fc_npd <= 0;
r_tx_limit_fc_nph <= 0;
r_tx_limit_fc_pd <= 0;
r_tx_limit_fc_ph <= 0;
r_tx_consumed_fc_cpld <= 0;
r_tx_consumed_fc_cplh <= 0;
r_tx_consumed_fc_npd <= 0;
r_tx_consumed_fc_nph <= 0;
r_tx_consumed_fc_pd <= 0;
r_tx_consumed_fc_ph <= 0;
end
else begin
if(r_rd_fc_sel_d2[0] == 1) begin
r_rx_available_fc_cpld <= fc_cpld;
r_rx_available_fc_cplh <= fc_cplh;
r_rx_available_fc_npd <= fc_npd;
r_rx_available_fc_nph <= fc_nph;
r_rx_available_fc_pd <= fc_pd;
r_rx_available_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[1] == 1) begin
r_rx_limit_fc_cpld <= fc_cpld;
r_rx_limit_fc_cplh <= fc_cplh;
r_rx_limit_fc_npd <= fc_npd;
r_rx_limit_fc_nph <= fc_nph;
r_rx_limit_fc_pd <= fc_pd;
r_rx_limit_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[2] == 1) begin
r_rx_consumed_fc_cpld <= fc_cpld;
r_rx_consumed_fc_cplh <= fc_cplh;
r_rx_consumed_fc_npd <= fc_npd;
r_rx_consumed_fc_nph <= fc_nph;
r_rx_consumed_fc_pd <= fc_pd;
r_rx_consumed_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[3] == 1) begin
r_tx_available_fc_cpld <= fc_cpld;
r_tx_available_fc_cplh <= fc_cplh;
r_tx_available_fc_npd <= fc_npd;
r_tx_available_fc_nph <= fc_nph;
r_tx_available_fc_pd <= fc_pd;
r_tx_available_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[4] == 1) begin
r_tx_limit_fc_cpld <= fc_cpld;
r_tx_limit_fc_cplh <= fc_cplh;
r_tx_limit_fc_npd <= fc_npd;
r_tx_limit_fc_nph <= fc_nph;
r_tx_limit_fc_pd <= fc_pd;
r_tx_limit_fc_ph <= fc_ph;
end
if(r_rd_fc_sel_d2[5] == 1) begin
r_tx_consumed_fc_cpld <= fc_cpld;
r_tx_consumed_fc_cplh <= fc_cplh;
r_tx_consumed_fc_npd <= fc_npd;
r_tx_consumed_fc_nph <= fc_nph;
r_tx_consumed_fc_pd <= fc_pd;
r_tx_consumed_fc_ph <= fc_ph;
end
end
end
*/
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
q0, q1, q2, q3, q4, q5, q6a, q6b,
// Inputs
clk, d, rst0_n
);
input clk;
input d;
// OK -- from primary
input rst0_n;
output wire q0;
Flop flop0 (.q(q0), .rst_n(rst0_n), .clk(clk), .d(d));
// OK -- from flop
reg rst1_n;
always @ (posedge clk) rst1_n <= rst0_n;
output wire q1;
Flop flop1 (.q(q1), .rst_n(rst1_n), .clk(clk), .d(d));
// Bad - logic
wire rst2_bad_n = rst0_n | rst1_n;
output wire q2;
Flop flop2 (.q(q2), .rst_n(rst2_bad_n), .clk(clk), .d(d));
// Bad - logic in submodule
wire rst3_bad_n;
Sub sub (.z(rst3_bad_n), .a(rst0_n), .b(rst1_n));
output wire q3;
Flop flop3 (.q(q3), .rst_n(rst3_bad_n), .clk(clk), .d(d));
// OK - bit selection
reg [3:0] rst4_n;
always @ (posedge clk) rst4_n <= {4{rst0_n}};
output wire q4;
Flop flop4 (.q(q4), .rst_n(rst4_n[1]), .clk(clk), .d(d));
// Bad - logic, but waived
// verilator lint_off CDCRSTLOGIC
wire rst5_waive_n = rst0_n & rst1_n;
// verilator lint_on CDCRSTLOGIC
output wire q5;
Flop flop5 (.q(q5), .rst_n(rst5_waive_n), .clk(clk), .d(d));
// Bad - for graph test - logic feeds two signals, three destinations
wire rst6_bad_n = rst0_n ^ rst1_n;
wire rst6a_bad_n = rst6_bad_n ^ $c1("0"); // $c prevents optimization
wire rst6b_bad_n = rst6_bad_n ^ $c1("1");
output wire q6a;
output wire q6b;
Flop flop6a (.q(q6a), .rst_n(rst6a_bad_n), .clk(clk), .d(d));
Flop flop6v (.q(q6b), .rst_n(rst6b_bad_n), .clk(clk), .d(d));
initial begin
$display("%%Error: Not a runnable test");
$stop;
end
endmodule
module Flop (
input clk,
input d,
input rst_n,
output q);
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) q <= 1'b0;
else q <= d;
end
endmodule
module Sub (input a, b,
output z);
wire z = a|b;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t;
wire d1 = 1'b1;
wire d2 = 1'b1;
wire d3 = 1'b1;
wire o1,o2,o3;
add1 add1 (d1,o1);
add2 add2 (d2,o2);
`define ls left_side
`define rs right_side
`define noarg na//note extra space
`define thru(x) x
`define thruthru `ls `rs // Doesn't expand
`define msg(x,y) `"x: `\`"y`\`"`"
`define left(m,left) m // The 'left' as the variable name shouldn't match the "left" in the `" string
initial begin
//$display(`msg( \`, \`)); // Illegal
$display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side));
$display(`msg(left side,right side));
$display(`msg( left side , right side ));
$display(`msg( `ls , `rs ));
$display(`msg( `noarg , `rs ));
$display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs ));
$display(`msg(`noarg,`noarg`noarg));
$display(`msg( `thruthru , `thruthru )); // Results vary between simulators
$display(`left(`msg( left side , right side ), left_replaced));
//$display(`msg( `"tickquoted_left`", `"tickquoted_right`" )); // Syntax error
`ifndef VCS // Sim bug - wrong number of arguments, but we're right
$display(`msg(`thru(),)); // Empty
`endif
$display(`msg(`thru(left side),`thru(right side)));
$display(`msg( `thru( left side ) , `thru( right side ) ));
`ifndef NC
$display(`"standalone`");
`endif
`ifdef VERILATOR
// Illegal on some simulators, as the "..." crosses two lines
`define twoline first \
second
$display(`msg(twoline, `twoline));
`endif
$display("Line %0d File \"%s\"",`__LINE__,`__FILE__);
//$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal.
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
`define ADD_UP(a,c) \
wire tmp_``a = a; \
wire tmp_``c = tmp_``a + 1; \
assign c = tmp_``c ;
module add1 ( input wire d1, output wire o1);
`ADD_UP(d1,o1) // expansion is OK
endmodule
module add2 ( input wire d2, output wire o2);
`ADD_UP( d2 , o2 ) // expansion is bad
endmodule
// `ADD_UP( \d3 , \o3 ) // This really is illegal
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_dma_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 34,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 2;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_dma_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 34,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 2;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module sys_rst
(
input cpu_bus_clk,
input cpu_bus_rst_n,
input pcie_perst_n,
input user_reset_out,
input pcie_pl_hot_rst,
input pcie_user_logic_rst,
output pcie_sys_rst_n,
output pcie_user_rst_n
);
localparam LP_PCIE_RST_CNT_WIDTH = 9;
localparam LP_PCIE_RST_CNT = 380;
localparam LP_PCIE_HOT_RST_CNT = 50;
localparam S_RESET = 6'b000001;
localparam S_RESET_CNT = 6'b000010;
localparam S_HOT_RESET = 6'b000100;
localparam S_HOT_RESET_CNT = 6'b001000;
localparam S_HOT_RESET_WAIT = 6'b010000;
localparam S_IDLE = 6'b100000;
reg [5:0] cur_state;
reg [5:0] next_state;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_perst_n;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_perst_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_pl_hot_rst;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_pl_hot_rst_sync;
reg [LP_PCIE_RST_CNT_WIDTH-1:0] r_rst_cnt;
reg r_pcie_sys_rst_n;
reg r_pcie_hot_rst;
assign pcie_user_rst_n = ~(user_reset_out | r_pcie_hot_rst);
//assign pcie_user_rst_n = ~(user_reset_out);
assign pcie_sys_rst_n = r_pcie_sys_rst_n;
always @ (posedge cpu_bus_clk)
begin
r_pcie_perst_n_sync <= pcie_perst_n;
r_pcie_perst_n <= r_pcie_perst_n_sync;
r_pcie_pl_hot_rst_sync <= pcie_pl_hot_rst;
r_pcie_pl_hot_rst <= r_pcie_pl_hot_rst_sync;
end
always @ (posedge cpu_bus_clk or negedge cpu_bus_rst_n)
begin
if(cpu_bus_rst_n == 0)
cur_state <= S_RESET;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RESET: begin
next_state <= S_RESET_CNT;
end
S_RESET_CNT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_rst_cnt == 0)
next_state <= S_IDLE;
else
next_state <= S_RESET_CNT;
end
S_HOT_RESET: begin
next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_CNT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_rst_cnt == 0)
next_state <= S_HOT_RESET_WAIT;
else
next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_WAIT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_pcie_pl_hot_rst == 1)
next_state <= S_HOT_RESET_WAIT;
else
next_state <= S_IDLE;
end
S_IDLE: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_pcie_pl_hot_rst == 1 || pcie_user_logic_rst == 1)
next_state <= S_HOT_RESET;
else
next_state <= S_IDLE;
end
default: begin
next_state <= S_RESET;
end
endcase
end
always @ (posedge cpu_bus_clk)
begin
case(cur_state)
S_RESET: begin
r_rst_cnt <= LP_PCIE_RST_CNT;
end
S_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET: begin
r_rst_cnt <= LP_PCIE_HOT_RST_CNT;
end
S_HOT_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET_WAIT: begin
end
S_IDLE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RESET: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_RESET_CNT: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_HOT_RESET: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_CNT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_WAIT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_IDLE: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 0;
end
default: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
endcase
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module sys_rst
(
input cpu_bus_clk,
input cpu_bus_rst_n,
input pcie_perst_n,
input user_reset_out,
input pcie_pl_hot_rst,
input pcie_user_logic_rst,
output pcie_sys_rst_n,
output pcie_user_rst_n
);
localparam LP_PCIE_RST_CNT_WIDTH = 9;
localparam LP_PCIE_RST_CNT = 380;
localparam LP_PCIE_HOT_RST_CNT = 50;
localparam S_RESET = 6'b000001;
localparam S_RESET_CNT = 6'b000010;
localparam S_HOT_RESET = 6'b000100;
localparam S_HOT_RESET_CNT = 6'b001000;
localparam S_HOT_RESET_WAIT = 6'b010000;
localparam S_IDLE = 6'b100000;
reg [5:0] cur_state;
reg [5:0] next_state;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_perst_n;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_perst_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_pl_hot_rst;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_pl_hot_rst_sync;
reg [LP_PCIE_RST_CNT_WIDTH-1:0] r_rst_cnt;
reg r_pcie_sys_rst_n;
reg r_pcie_hot_rst;
assign pcie_user_rst_n = ~(user_reset_out | r_pcie_hot_rst);
//assign pcie_user_rst_n = ~(user_reset_out);
assign pcie_sys_rst_n = r_pcie_sys_rst_n;
always @ (posedge cpu_bus_clk)
begin
r_pcie_perst_n_sync <= pcie_perst_n;
r_pcie_perst_n <= r_pcie_perst_n_sync;
r_pcie_pl_hot_rst_sync <= pcie_pl_hot_rst;
r_pcie_pl_hot_rst <= r_pcie_pl_hot_rst_sync;
end
always @ (posedge cpu_bus_clk or negedge cpu_bus_rst_n)
begin
if(cpu_bus_rst_n == 0)
cur_state <= S_RESET;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RESET: begin
next_state <= S_RESET_CNT;
end
S_RESET_CNT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_rst_cnt == 0)
next_state <= S_IDLE;
else
next_state <= S_RESET_CNT;
end
S_HOT_RESET: begin
next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_CNT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_rst_cnt == 0)
next_state <= S_HOT_RESET_WAIT;
else
next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_WAIT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_pcie_pl_hot_rst == 1)
next_state <= S_HOT_RESET_WAIT;
else
next_state <= S_IDLE;
end
S_IDLE: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_pcie_pl_hot_rst == 1 || pcie_user_logic_rst == 1)
next_state <= S_HOT_RESET;
else
next_state <= S_IDLE;
end
default: begin
next_state <= S_RESET;
end
endcase
end
always @ (posedge cpu_bus_clk)
begin
case(cur_state)
S_RESET: begin
r_rst_cnt <= LP_PCIE_RST_CNT;
end
S_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET: begin
r_rst_cnt <= LP_PCIE_HOT_RST_CNT;
end
S_HOT_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET_WAIT: begin
end
S_IDLE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RESET: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_RESET_CNT: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_HOT_RESET: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_CNT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_WAIT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_IDLE: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 0;
end
default: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
endcase
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module sys_rst
(
input cpu_bus_clk,
input cpu_bus_rst_n,
input pcie_perst_n,
input user_reset_out,
input pcie_pl_hot_rst,
input pcie_user_logic_rst,
output pcie_sys_rst_n,
output pcie_user_rst_n
);
localparam LP_PCIE_RST_CNT_WIDTH = 9;
localparam LP_PCIE_RST_CNT = 380;
localparam LP_PCIE_HOT_RST_CNT = 50;
localparam S_RESET = 6'b000001;
localparam S_RESET_CNT = 6'b000010;
localparam S_HOT_RESET = 6'b000100;
localparam S_HOT_RESET_CNT = 6'b001000;
localparam S_HOT_RESET_WAIT = 6'b010000;
localparam S_IDLE = 6'b100000;
reg [5:0] cur_state;
reg [5:0] next_state;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_perst_n;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_perst_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_pl_hot_rst;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_pl_hot_rst_sync;
reg [LP_PCIE_RST_CNT_WIDTH-1:0] r_rst_cnt;
reg r_pcie_sys_rst_n;
reg r_pcie_hot_rst;
assign pcie_user_rst_n = ~(user_reset_out | r_pcie_hot_rst);
//assign pcie_user_rst_n = ~(user_reset_out);
assign pcie_sys_rst_n = r_pcie_sys_rst_n;
always @ (posedge cpu_bus_clk)
begin
r_pcie_perst_n_sync <= pcie_perst_n;
r_pcie_perst_n <= r_pcie_perst_n_sync;
r_pcie_pl_hot_rst_sync <= pcie_pl_hot_rst;
r_pcie_pl_hot_rst <= r_pcie_pl_hot_rst_sync;
end
always @ (posedge cpu_bus_clk or negedge cpu_bus_rst_n)
begin
if(cpu_bus_rst_n == 0)
cur_state <= S_RESET;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RESET: begin
next_state <= S_RESET_CNT;
end
S_RESET_CNT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_rst_cnt == 0)
next_state <= S_IDLE;
else
next_state <= S_RESET_CNT;
end
S_HOT_RESET: begin
next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_CNT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_rst_cnt == 0)
next_state <= S_HOT_RESET_WAIT;
else
next_state <= S_HOT_RESET_CNT;
end
S_HOT_RESET_WAIT: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_pcie_pl_hot_rst == 1)
next_state <= S_HOT_RESET_WAIT;
else
next_state <= S_IDLE;
end
S_IDLE: begin
if(r_pcie_perst_n == 0)
next_state <= S_RESET;
else if(r_pcie_pl_hot_rst == 1 || pcie_user_logic_rst == 1)
next_state <= S_HOT_RESET;
else
next_state <= S_IDLE;
end
default: begin
next_state <= S_RESET;
end
endcase
end
always @ (posedge cpu_bus_clk)
begin
case(cur_state)
S_RESET: begin
r_rst_cnt <= LP_PCIE_RST_CNT;
end
S_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET: begin
r_rst_cnt <= LP_PCIE_HOT_RST_CNT;
end
S_HOT_RESET_CNT: begin
r_rst_cnt <= r_rst_cnt - 1'b1;
end
S_HOT_RESET_WAIT: begin
end
S_IDLE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RESET: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_RESET_CNT: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
S_HOT_RESET: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_CNT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_HOT_RESET_WAIT: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 1;
end
S_IDLE: begin
r_pcie_sys_rst_n <= 1;
r_pcie_hot_rst <= 0;
end
default: begin
r_pcie_sys_rst_n <= 0;
r_pcie_hot_rst <= 0;
end
endcase
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_cq_check # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_msi_en,
input cq_rst_n,
input cq_valid,
input io_cq_irq_en,
input [7:0] cq_tail_ptr,
input [7:0] cq_head_ptr,
input cq_head_update,
output cq_legacy_irq_req,
output cq_msi_irq_req,
input cq_msi_irq_ack
);
localparam LP_CQ_IRQ_DELAY_TIME = 8'h01;
localparam S_IDLE = 4'b0001;
localparam S_CQ_MSI_IRQ_REQ = 4'b0010;
localparam S_CQ_MSI_HEAD_SET = 4'b0100;
localparam S_CQ_MSI_IRQ_TIMER = 4'b1000;
reg [3:0] cur_state;
reg [3:0] next_state;
reg [7:0] r_cq_tail_ptr;
reg [7:0] r_cq_msi_irq_head_ptr;
reg [7:0] r_irq_timer;
reg r_cq_legacy_irq_req;
reg r_cq_msi_irq_req;
wire w_cq_rst_n;
assign cq_legacy_irq_req = r_cq_legacy_irq_req;
assign cq_msi_irq_req = r_cq_msi_irq_req;
assign w_cq_rst_n = pcie_user_rst_n & cq_rst_n;
always @ (posedge pcie_user_clk)
begin
r_cq_tail_ptr <= cq_tail_ptr;
r_cq_legacy_irq_req <= ((cq_head_ptr != r_cq_tail_ptr) && ((cq_valid & io_cq_irq_en) == 1));
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n)
begin
if(w_cq_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(((r_cq_msi_irq_head_ptr != r_cq_tail_ptr) & (pcie_msi_en & cq_valid & io_cq_irq_en)) == 1)
next_state <= S_CQ_MSI_IRQ_REQ;
else
next_state <= S_IDLE;
end
S_CQ_MSI_IRQ_REQ: begin
if(cq_msi_irq_ack == 1)
next_state <= S_CQ_MSI_HEAD_SET;
else
next_state <= S_CQ_MSI_IRQ_REQ;
end
S_CQ_MSI_HEAD_SET: begin
/*
if(cq_head_update == 1 || (cq_head_ptr == r_cq_tail_ptr))
next_state <= S_CQ_MSI_IRQ_TIMER;
else
next_state <= S_CQ_MSI_HEAD_SET;
*/
next_state <= S_CQ_MSI_IRQ_TIMER;
end
S_CQ_MSI_IRQ_TIMER: begin
if(r_irq_timer == 0)
next_state <= S_IDLE;
else
next_state <= S_CQ_MSI_IRQ_TIMER;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CQ_MSI_IRQ_REQ: begin
end
S_CQ_MSI_HEAD_SET: begin
r_irq_timer <= LP_CQ_IRQ_DELAY_TIME;
end
S_CQ_MSI_IRQ_TIMER: begin
r_irq_timer <= r_irq_timer - 1;
end
default: begin
end
endcase
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n)
begin
if(w_cq_rst_n == 0) begin
r_cq_msi_irq_head_ptr <= 0;
end
else begin
case(cur_state)
S_IDLE: begin
if((pcie_msi_en & cq_valid & io_cq_irq_en) == 0)
r_cq_msi_irq_head_ptr <= r_cq_tail_ptr;
end
S_CQ_MSI_IRQ_REQ: begin
end
S_CQ_MSI_HEAD_SET: begin
r_cq_msi_irq_head_ptr <= r_cq_tail_ptr;
end
S_CQ_MSI_IRQ_TIMER: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_cq_msi_irq_req <= 0;
end
S_CQ_MSI_IRQ_REQ: begin
r_cq_msi_irq_req <= 1;
end
S_CQ_MSI_HEAD_SET: begin
r_cq_msi_irq_req <= 0;
end
S_CQ_MSI_IRQ_TIMER: begin
r_cq_msi_irq_req <= 0;
end
default: begin
r_cq_msi_irq_req <= 0;
end
endcase
end
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_cq_check # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_msi_en,
input cq_rst_n,
input cq_valid,
input io_cq_irq_en,
input [7:0] cq_tail_ptr,
input [7:0] cq_head_ptr,
input cq_head_update,
output cq_legacy_irq_req,
output cq_msi_irq_req,
input cq_msi_irq_ack
);
localparam LP_CQ_IRQ_DELAY_TIME = 8'h01;
localparam S_IDLE = 4'b0001;
localparam S_CQ_MSI_IRQ_REQ = 4'b0010;
localparam S_CQ_MSI_HEAD_SET = 4'b0100;
localparam S_CQ_MSI_IRQ_TIMER = 4'b1000;
reg [3:0] cur_state;
reg [3:0] next_state;
reg [7:0] r_cq_tail_ptr;
reg [7:0] r_cq_msi_irq_head_ptr;
reg [7:0] r_irq_timer;
reg r_cq_legacy_irq_req;
reg r_cq_msi_irq_req;
wire w_cq_rst_n;
assign cq_legacy_irq_req = r_cq_legacy_irq_req;
assign cq_msi_irq_req = r_cq_msi_irq_req;
assign w_cq_rst_n = pcie_user_rst_n & cq_rst_n;
always @ (posedge pcie_user_clk)
begin
r_cq_tail_ptr <= cq_tail_ptr;
r_cq_legacy_irq_req <= ((cq_head_ptr != r_cq_tail_ptr) && ((cq_valid & io_cq_irq_en) == 1));
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n)
begin
if(w_cq_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(((r_cq_msi_irq_head_ptr != r_cq_tail_ptr) & (pcie_msi_en & cq_valid & io_cq_irq_en)) == 1)
next_state <= S_CQ_MSI_IRQ_REQ;
else
next_state <= S_IDLE;
end
S_CQ_MSI_IRQ_REQ: begin
if(cq_msi_irq_ack == 1)
next_state <= S_CQ_MSI_HEAD_SET;
else
next_state <= S_CQ_MSI_IRQ_REQ;
end
S_CQ_MSI_HEAD_SET: begin
/*
if(cq_head_update == 1 || (cq_head_ptr == r_cq_tail_ptr))
next_state <= S_CQ_MSI_IRQ_TIMER;
else
next_state <= S_CQ_MSI_HEAD_SET;
*/
next_state <= S_CQ_MSI_IRQ_TIMER;
end
S_CQ_MSI_IRQ_TIMER: begin
if(r_irq_timer == 0)
next_state <= S_IDLE;
else
next_state <= S_CQ_MSI_IRQ_TIMER;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CQ_MSI_IRQ_REQ: begin
end
S_CQ_MSI_HEAD_SET: begin
r_irq_timer <= LP_CQ_IRQ_DELAY_TIME;
end
S_CQ_MSI_IRQ_TIMER: begin
r_irq_timer <= r_irq_timer - 1;
end
default: begin
end
endcase
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n)
begin
if(w_cq_rst_n == 0) begin
r_cq_msi_irq_head_ptr <= 0;
end
else begin
case(cur_state)
S_IDLE: begin
if((pcie_msi_en & cq_valid & io_cq_irq_en) == 0)
r_cq_msi_irq_head_ptr <= r_cq_tail_ptr;
end
S_CQ_MSI_IRQ_REQ: begin
end
S_CQ_MSI_HEAD_SET: begin
r_cq_msi_irq_head_ptr <= r_cq_tail_ptr;
end
S_CQ_MSI_IRQ_TIMER: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_cq_msi_irq_req <= 0;
end
S_CQ_MSI_IRQ_REQ: begin
r_cq_msi_irq_req <= 1;
end
S_CQ_MSI_HEAD_SET: begin
r_cq_msi_irq_req <= 0;
end
S_CQ_MSI_IRQ_TIMER: begin
r_cq_msi_irq_req <= 0;
end
default: begin
r_cq_msi_irq_req <= 0;
end
endcase
end
endmodule |
`timescale 1ns/1ps
module tx_packer
( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
input [15:0]usbdata,
// TX Side
input reset,
input txclk,
output reg [31:0] usbdata_final,
output reg WR_final,
output wire test_bit0,
output reg test_bit1
);
reg [8:0] write_count;
/* Fix FX2 bug */
always @(posedge usbclk)
begin
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR_fx2 & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR_fx2 ? write_count : 9'b0;
end
reg WR_fx2_fixed;
reg [15:0]usbdata_fixed;
always @(posedge usbclk)
begin
WR_fx2_fixed <= WR_fx2 & ~write_count[8];
usbdata_fixed <= usbdata;
end
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
reg word_complete ;
reg [15:0] usbdata_delayed ;
reg writing ;
wire [31:0] usbdata_packed ;
wire WR_packed ;
//////////////////////////////////////////////test code
// assign usbdata_xor = ((usbdata_fixed[15] ^ usbdata_fixed[14]) | (usbdata_fixed[13] ^ usbdata_fixed[12]) |
// (usbdata_fixed[11] ^ usbdata_fixed[10]) | (usbdata_fixed[9] ^ usbdata_fixed[8]) |
// (usbdata_fixed[7] ^ usbdata_fixed[6]) | (usbdata_fixed[5] ^ usbdata_fixed[4]) |
// (usbdata_fixed[3] ^ usbdata_fixed[2]) | (usbdata_fixed[1] ^ usbdata_fixed[0]) |
// (usbdata_fixed[15] ^ usbdata_fixed[11]) | (usbdata_fixed[7] ^ usbdata_fixed[3]) |
// (usbdata_fixed[13] ^ usbdata_fixed[9]) | (usbdata_fixed[5] ^ usbdata_fixed[1]) )
// & WR_fx2_fixed;
assign usbdata_xor = ((usbdata_fixed[15] & usbdata_fixed[14]) & (usbdata_fixed[13] & usbdata_fixed[12]) &
(usbdata_fixed[11] & usbdata_fixed[10]) & (usbdata_fixed[9] & usbdata_fixed[8]) &
(usbdata_fixed[7] & usbdata_fixed[6]) & (usbdata_fixed[5] & usbdata_fixed[4]) &
(usbdata_fixed[3] & usbdata_fixed[2]) & (usbdata_fixed[1] & usbdata_fixed[0]) &
WR_fx2_fixed);
assign test_bit0 = txclk ;
//always @(posedge usbclk)
// begin
// test_bit0 <= usbdata_xor;
// end
//////////////////////////////////////////////test code
always @(posedge usbclk)
begin
if (bus_reset)
begin
word_complete <= 0 ;
writing <= 0 ;
end
else if (WR_fx2_fixed)
begin
writing <= 1 ;
if (word_complete)
word_complete <= 0 ;
else
begin
usbdata_delayed <= usbdata_fixed ;
word_complete <= 1 ;
end
end
else
writing <= 0 ;
end
assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
assign WR_packed = word_complete & writing ;
/* Make sure data are sync with usbclk */
reg [31:0]usbdata_usbclk;
reg WR_usbclk;
always @(posedge usbclk)
begin
if (WR_packed)
usbdata_usbclk <= usbdata_packed;
WR_usbclk <= WR_packed;
end
/* Cross clock boundaries */
reg [31:0] usbdata_tx ;
reg WR_tx;
reg WR_1;
reg WR_2;
always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
always @(posedge txclk)
if (reset)
WR_1 <= 0;
else
WR_1 <= WR_usbclk;
always @(posedge txclk)
if (reset)
WR_2 <= 0;
else
WR_2 <= WR_1;
always @(posedge txclk)
begin
if (reset)
WR_tx <= 0;
else
WR_tx <= WR_1 & ~WR_2;
end
always @(posedge txclk)
begin
if (reset)
WR_final <= 0;
else
begin
WR_final <= WR_tx;
if (WR_tx)
usbdata_final <= usbdata_tx;
end
end
///////////////////test output
always @(posedge txclk)
begin
if (reset)
test_bit1 <= 0;
else if (!WR_final)
test_bit1 <= test_bit1;
else if ((usbdata_final == 32'hffff0000))
test_bit1 <= 0;
else
test_bit1 <= 1;
end
///////////////////////////////
// always @(posedge usbclk)
// begin
// if (bus_reset)
// begin
// test_bit0 <= 1'b0;
// end
// else if (usbdata_packed[0] ^ usbdata_packed[16])
// test_bit0 <= 1'b1;
// else
// test_bit0 <= 1'b0;
// end
// Test comparator for 16 bit hi & low data
// add new test bit
// wire [15:0] usbpkd_low;
// wire [15:0] usbpkd_hi;
//
// assign usbpkd_low = usbdata_delayed;
// assign usbpkd_hi = usbdata_fixed;
//
// always @(posedge usbclk)
// begin
// if (bus_reset)
// begin
// test_bit1 <= 1'b0;
// end
// else
// begin
// // test_bit1 <= (usbpkd_low === usbpkd_hi) ? 1'b1 : 1'b0;
// if (usbpkd_low == usbpkd_hi)
// test_bit1 <= 1'b1;
// else
// test_bit1 <= 1'b0;
// end
// end
endmodule
|
`timescale 1ns/1ps
module tx_packer
( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
input [15:0]usbdata,
// TX Side
input reset,
input txclk,
output reg [31:0] usbdata_final,
output reg WR_final,
output wire test_bit0,
output reg test_bit1
);
reg [8:0] write_count;
/* Fix FX2 bug */
always @(posedge usbclk)
begin
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR_fx2 & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR_fx2 ? write_count : 9'b0;
end
reg WR_fx2_fixed;
reg [15:0]usbdata_fixed;
always @(posedge usbclk)
begin
WR_fx2_fixed <= WR_fx2 & ~write_count[8];
usbdata_fixed <= usbdata;
end
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
reg word_complete ;
reg [15:0] usbdata_delayed ;
reg writing ;
wire [31:0] usbdata_packed ;
wire WR_packed ;
//////////////////////////////////////////////test code
// assign usbdata_xor = ((usbdata_fixed[15] ^ usbdata_fixed[14]) | (usbdata_fixed[13] ^ usbdata_fixed[12]) |
// (usbdata_fixed[11] ^ usbdata_fixed[10]) | (usbdata_fixed[9] ^ usbdata_fixed[8]) |
// (usbdata_fixed[7] ^ usbdata_fixed[6]) | (usbdata_fixed[5] ^ usbdata_fixed[4]) |
// (usbdata_fixed[3] ^ usbdata_fixed[2]) | (usbdata_fixed[1] ^ usbdata_fixed[0]) |
// (usbdata_fixed[15] ^ usbdata_fixed[11]) | (usbdata_fixed[7] ^ usbdata_fixed[3]) |
// (usbdata_fixed[13] ^ usbdata_fixed[9]) | (usbdata_fixed[5] ^ usbdata_fixed[1]) )
// & WR_fx2_fixed;
assign usbdata_xor = ((usbdata_fixed[15] & usbdata_fixed[14]) & (usbdata_fixed[13] & usbdata_fixed[12]) &
(usbdata_fixed[11] & usbdata_fixed[10]) & (usbdata_fixed[9] & usbdata_fixed[8]) &
(usbdata_fixed[7] & usbdata_fixed[6]) & (usbdata_fixed[5] & usbdata_fixed[4]) &
(usbdata_fixed[3] & usbdata_fixed[2]) & (usbdata_fixed[1] & usbdata_fixed[0]) &
WR_fx2_fixed);
assign test_bit0 = txclk ;
//always @(posedge usbclk)
// begin
// test_bit0 <= usbdata_xor;
// end
//////////////////////////////////////////////test code
always @(posedge usbclk)
begin
if (bus_reset)
begin
word_complete <= 0 ;
writing <= 0 ;
end
else if (WR_fx2_fixed)
begin
writing <= 1 ;
if (word_complete)
word_complete <= 0 ;
else
begin
usbdata_delayed <= usbdata_fixed ;
word_complete <= 1 ;
end
end
else
writing <= 0 ;
end
assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
assign WR_packed = word_complete & writing ;
/* Make sure data are sync with usbclk */
reg [31:0]usbdata_usbclk;
reg WR_usbclk;
always @(posedge usbclk)
begin
if (WR_packed)
usbdata_usbclk <= usbdata_packed;
WR_usbclk <= WR_packed;
end
/* Cross clock boundaries */
reg [31:0] usbdata_tx ;
reg WR_tx;
reg WR_1;
reg WR_2;
always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
always @(posedge txclk)
if (reset)
WR_1 <= 0;
else
WR_1 <= WR_usbclk;
always @(posedge txclk)
if (reset)
WR_2 <= 0;
else
WR_2 <= WR_1;
always @(posedge txclk)
begin
if (reset)
WR_tx <= 0;
else
WR_tx <= WR_1 & ~WR_2;
end
always @(posedge txclk)
begin
if (reset)
WR_final <= 0;
else
begin
WR_final <= WR_tx;
if (WR_tx)
usbdata_final <= usbdata_tx;
end
end
///////////////////test output
always @(posedge txclk)
begin
if (reset)
test_bit1 <= 0;
else if (!WR_final)
test_bit1 <= test_bit1;
else if ((usbdata_final == 32'hffff0000))
test_bit1 <= 0;
else
test_bit1 <= 1;
end
///////////////////////////////
// always @(posedge usbclk)
// begin
// if (bus_reset)
// begin
// test_bit0 <= 1'b0;
// end
// else if (usbdata_packed[0] ^ usbdata_packed[16])
// test_bit0 <= 1'b1;
// else
// test_bit0 <= 1'b0;
// end
// Test comparator for 16 bit hi & low data
// add new test bit
// wire [15:0] usbpkd_low;
// wire [15:0] usbpkd_hi;
//
// assign usbpkd_low = usbdata_delayed;
// assign usbpkd_hi = usbdata_fixed;
//
// always @(posedge usbclk)
// begin
// if (bus_reset)
// begin
// test_bit1 <= 1'b0;
// end
// else
// begin
// // test_bit1 <= (usbpkd_low === usbpkd_hi) ? 1'b1 : 1'b0;
// if (usbpkd_low == usbpkd_hi)
// test_bit1 <= 1'b1;
// else
// test_bit1 <= 1'b0;
// end
// end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
input [7:0] admin_sq_size,
input [7:0] admin_cq_size,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
input [7:0] cpld_sq_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_sq_fifo_wr_data,
input cpld_sq_fifo_wr_en,
input cpld_sq_fifo_tag_last,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack,
output [7:0] admin_cq_tail_ptr,
output [7:0] io_cq1_tail_ptr,
output [7:0] io_cq2_tail_ptr,
output [7:0] io_cq3_tail_ptr,
output [7:0] io_cq4_tail_ptr,
output [7:0] io_cq5_tail_ptr,
output [7:0] io_cq6_tail_ptr,
output [7:0] io_cq7_tail_ptr,
output [7:0] io_cq8_tail_ptr,
output tx_cq_mwr_req,
output [7:0] tx_cq_mwr_tag,
output [11:2] tx_cq_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_cq_mwr_addr,
input tx_cq_mwr_req_ack,
input tx_cq_mwr_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] tx_cq_mwr_rd_data,
input tx_cq_mwr_data_last,
input [7:0] hcmd_prp_rd_addr,
output [44:0] hcmd_prp_rd_data,
input hcmd_nlb_wr1_en,
input [6:0] hcmd_nlb_wr1_addr,
input [18:0] hcmd_nlb_wr1_data,
output hcmd_nlb_wr1_rdy_n,
input [6:0] hcmd_nlb_rd_addr,
output [18:0] hcmd_nlb_rd_data,
input hcmd_cq_wr0_en,
input [34:0] hcmd_cq_wr0_data0,
input [34:0] hcmd_cq_wr0_data1,
output hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input hcmd_sq_rd_en,
output [18:0] hcmd_sq_rd_data,
output hcmd_sq_empty_n,
input [10:0] hcmd_table_rd_addr,
output [31:0] hcmd_table_rd_data,
input hcmd_cq_wr1_en,
input [34:0] hcmd_cq_wr1_data0,
input [34:0] hcmd_cq_wr1_data1,
output hcmd_cq_wr1_rdy_n
);
wire w_hcmd_table_wr_en;
wire [8:0] w_hcmd_table_wr_addr;
wire [127:0] w_hcmd_table_wr_data;
wire w_hcmd_cid_wr_en;
wire [6:0] w_hcmd_cid_wr_addr;
wire [19:0] w_hcmd_cid_wr_data;
wire [6:0] w_hcmd_cid_rd_addr;
wire [19:0] w_hcmd_cid_rd_data;
wire w_hcmd_prp_wr_en;
wire [7:0] w_hcmd_prp_wr_addr;
wire [44:0] w_hcmd_prp_wr_data;
wire w_hcmd_nlb_wr0_en;
wire [6:0] w_hcmd_nlb_wr0_addr;
wire [18:0] w_hcmd_nlb_wr0_data;
wire w_hcmd_nlb_wr0_rdy_n;
wire w_hcmd_slot_rdy;
wire [6:0] w_hcmd_slot_tag;
wire w_hcmd_slot_alloc_en;
wire w_hcmd_slot_free_en;
wire [6:0] w_hcmd_slot_invalid_tag;
wire [7:0] w_admin_sq_head_ptr;
wire [7:0] w_io_sq1_head_ptr;
wire [7:0] w_io_sq2_head_ptr;
wire [7:0] w_io_sq3_head_ptr;
wire [7:0] w_io_sq4_head_ptr;
wire [7:0] w_io_sq5_head_ptr;
wire [7:0] w_io_sq6_head_ptr;
wire [7:0] w_io_sq7_head_ptr;
wire [7:0] w_io_sq8_head_ptr;
pcie_hcmd_table
pcie_hcmd_table_inst0(
.wr_clk (pcie_user_clk),
.wr_en (w_hcmd_table_wr_en),
.wr_addr (w_hcmd_table_wr_addr),
.wr_data (w_hcmd_table_wr_data),
.rd_clk (cpu_bus_clk),
.rd_addr (hcmd_table_rd_addr),
.rd_data (hcmd_table_rd_data)
);
pcie_hcmd_table_cid
pcie_hcmd_table_cid_isnt0(
.clk (pcie_user_clk),
.wr_en (w_hcmd_cid_wr_en),
.wr_addr (w_hcmd_cid_wr_addr),
.wr_data (w_hcmd_cid_wr_data),
.rd_addr (w_hcmd_cid_rd_addr),
.rd_data (w_hcmd_cid_rd_data)
);
pcie_hcmd_table_prp
pcie_hcmd_table_prp_isnt0(
.clk (pcie_user_clk),
.wr_en (w_hcmd_prp_wr_en),
.wr_addr (w_hcmd_prp_wr_addr),
.wr_data (w_hcmd_prp_wr_data),
.rd_addr (hcmd_prp_rd_addr),
.rd_data (hcmd_prp_rd_data)
);
pcie_hcmd_nlb
pcie_hcmd_nlb_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (w_hcmd_nlb_wr0_en),
.wr0_addr (w_hcmd_nlb_wr0_addr),
.wr0_data (w_hcmd_nlb_wr0_data),
.wr0_rdy_n (w_hcmd_nlb_wr0_rdy_n),
.wr1_en (hcmd_nlb_wr1_en),
.wr1_addr (hcmd_nlb_wr1_addr),
.wr1_data (hcmd_nlb_wr1_data),
.wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.rd_addr (hcmd_nlb_rd_addr),
.rd_data (hcmd_nlb_rd_data)
);
pcie_hcmd_slot_mgt
pcie_hcmd_slot_mgt_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.hcmd_slot_rdy (w_hcmd_slot_rdy),
.hcmd_slot_tag (w_hcmd_slot_tag),
.hcmd_slot_alloc_en (w_hcmd_slot_alloc_en),
.hcmd_slot_free_en (w_hcmd_slot_free_en),
.hcmd_slot_invalid_tag (w_hcmd_slot_invalid_tag)
);
pcie_hcmd_sq # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_sq_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.admin_sq_bs_addr (admin_sq_bs_addr),
.admin_sq_size (admin_sq_size),
.admin_sq_tail_ptr (admin_sq_tail_ptr),
.io_sq1_tail_ptr (io_sq1_tail_ptr),
.io_sq2_tail_ptr (io_sq2_tail_ptr),
.io_sq3_tail_ptr (io_sq3_tail_ptr),
.io_sq4_tail_ptr (io_sq4_tail_ptr),
.io_sq5_tail_ptr (io_sq5_tail_ptr),
.io_sq6_tail_ptr (io_sq6_tail_ptr),
.io_sq7_tail_ptr (io_sq7_tail_ptr),
.io_sq8_tail_ptr (io_sq8_tail_ptr),
.admin_sq_head_ptr (w_admin_sq_head_ptr),
.io_sq1_head_ptr (w_io_sq1_head_ptr),
.io_sq2_head_ptr (w_io_sq2_head_ptr),
.io_sq3_head_ptr (w_io_sq3_head_ptr),
.io_sq4_head_ptr (w_io_sq4_head_ptr),
.io_sq5_head_ptr (w_io_sq5_head_ptr),
.io_sq6_head_ptr (w_io_sq6_head_ptr),
.io_sq7_head_ptr (w_io_sq7_head_ptr),
.io_sq8_head_ptr (w_io_sq8_head_ptr),
.hcmd_slot_rdy (w_hcmd_slot_rdy),
.hcmd_slot_tag (w_hcmd_slot_tag),
.hcmd_slot_alloc_en (w_hcmd_slot_alloc_en),
.cpld_sq_fifo_tag (cpld_sq_fifo_tag),
.cpld_sq_fifo_wr_data (cpld_sq_fifo_wr_data),
.cpld_sq_fifo_wr_en (cpld_sq_fifo_wr_en),
.cpld_sq_fifo_tag_last (cpld_sq_fifo_tag_last),
.tx_mrd_req (tx_mrd_req),
.tx_mrd_tag (tx_mrd_tag),
.tx_mrd_len (tx_mrd_len),
.tx_mrd_addr (tx_mrd_addr),
.tx_mrd_req_ack (tx_mrd_req_ack),
.hcmd_table_wr_en (w_hcmd_table_wr_en),
.hcmd_table_wr_addr (w_hcmd_table_wr_addr),
.hcmd_table_wr_data (w_hcmd_table_wr_data),
.hcmd_cid_wr_en (w_hcmd_cid_wr_en),
.hcmd_cid_wr_addr (w_hcmd_cid_wr_addr),
.hcmd_cid_wr_data (w_hcmd_cid_wr_data),
.hcmd_prp_wr_en (w_hcmd_prp_wr_en),
.hcmd_prp_wr_addr (w_hcmd_prp_wr_addr),
.hcmd_prp_wr_data (w_hcmd_prp_wr_data),
.hcmd_nlb_wr0_en (w_hcmd_nlb_wr0_en),
.hcmd_nlb_wr0_addr (w_hcmd_nlb_wr0_addr),
.hcmd_nlb_wr0_data (w_hcmd_nlb_wr0_data),
.hcmd_nlb_wr0_rdy_n (w_hcmd_nlb_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.sq_rst_n (sq_rst_n),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n)
);
pcie_hcmd_cq # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_cq_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.hcmd_cid_rd_addr (w_hcmd_cid_rd_addr),
.hcmd_cid_rd_data (w_hcmd_cid_rd_data),
.admin_cq_bs_addr (admin_cq_bs_addr),
.admin_cq_size (admin_cq_size),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_sq_head_ptr (w_admin_sq_head_ptr),
.io_sq1_head_ptr (w_io_sq1_head_ptr),
.io_sq2_head_ptr (w_io_sq2_head_ptr),
.io_sq3_head_ptr (w_io_sq3_head_ptr),
.io_sq4_head_ptr (w_io_sq4_head_ptr),
.io_sq5_head_ptr (w_io_sq5_head_ptr),
.io_sq6_head_ptr (w_io_sq6_head_ptr),
.io_sq7_head_ptr (w_io_sq7_head_ptr),
.io_sq8_head_ptr (w_io_sq8_head_ptr),
.hcmd_slot_free_en (w_hcmd_slot_free_en),
.hcmd_slot_invalid_tag (w_hcmd_slot_invalid_tag),
.tx_cq_mwr_req (tx_cq_mwr_req),
.tx_cq_mwr_tag (tx_cq_mwr_tag),
.tx_cq_mwr_len (tx_cq_mwr_len),
.tx_cq_mwr_addr (tx_cq_mwr_addr),
.tx_cq_mwr_req_ack (tx_cq_mwr_req_ack),
.tx_cq_mwr_rd_en (tx_cq_mwr_rd_en),
.tx_cq_mwr_rd_data (tx_cq_mwr_rd_data),
.tx_cq_mwr_data_last (tx_cq_mwr_data_last),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.sq_valid (sq_valid),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n)
);
endmodule |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
input [7:0] admin_sq_size,
input [7:0] admin_cq_size,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
input [7:0] cpld_sq_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_sq_fifo_wr_data,
input cpld_sq_fifo_wr_en,
input cpld_sq_fifo_tag_last,
output tx_mrd_req,
output [7:0] tx_mrd_tag,
output [11:2] tx_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_mrd_addr,
input tx_mrd_req_ack,
output [7:0] admin_cq_tail_ptr,
output [7:0] io_cq1_tail_ptr,
output [7:0] io_cq2_tail_ptr,
output [7:0] io_cq3_tail_ptr,
output [7:0] io_cq4_tail_ptr,
output [7:0] io_cq5_tail_ptr,
output [7:0] io_cq6_tail_ptr,
output [7:0] io_cq7_tail_ptr,
output [7:0] io_cq8_tail_ptr,
output tx_cq_mwr_req,
output [7:0] tx_cq_mwr_tag,
output [11:2] tx_cq_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_cq_mwr_addr,
input tx_cq_mwr_req_ack,
input tx_cq_mwr_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] tx_cq_mwr_rd_data,
input tx_cq_mwr_data_last,
input [7:0] hcmd_prp_rd_addr,
output [44:0] hcmd_prp_rd_data,
input hcmd_nlb_wr1_en,
input [6:0] hcmd_nlb_wr1_addr,
input [18:0] hcmd_nlb_wr1_data,
output hcmd_nlb_wr1_rdy_n,
input [6:0] hcmd_nlb_rd_addr,
output [18:0] hcmd_nlb_rd_data,
input hcmd_cq_wr0_en,
input [34:0] hcmd_cq_wr0_data0,
input [34:0] hcmd_cq_wr0_data1,
output hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input hcmd_sq_rd_en,
output [18:0] hcmd_sq_rd_data,
output hcmd_sq_empty_n,
input [10:0] hcmd_table_rd_addr,
output [31:0] hcmd_table_rd_data,
input hcmd_cq_wr1_en,
input [34:0] hcmd_cq_wr1_data0,
input [34:0] hcmd_cq_wr1_data1,
output hcmd_cq_wr1_rdy_n
);
wire w_hcmd_table_wr_en;
wire [8:0] w_hcmd_table_wr_addr;
wire [127:0] w_hcmd_table_wr_data;
wire w_hcmd_cid_wr_en;
wire [6:0] w_hcmd_cid_wr_addr;
wire [19:0] w_hcmd_cid_wr_data;
wire [6:0] w_hcmd_cid_rd_addr;
wire [19:0] w_hcmd_cid_rd_data;
wire w_hcmd_prp_wr_en;
wire [7:0] w_hcmd_prp_wr_addr;
wire [44:0] w_hcmd_prp_wr_data;
wire w_hcmd_nlb_wr0_en;
wire [6:0] w_hcmd_nlb_wr0_addr;
wire [18:0] w_hcmd_nlb_wr0_data;
wire w_hcmd_nlb_wr0_rdy_n;
wire w_hcmd_slot_rdy;
wire [6:0] w_hcmd_slot_tag;
wire w_hcmd_slot_alloc_en;
wire w_hcmd_slot_free_en;
wire [6:0] w_hcmd_slot_invalid_tag;
wire [7:0] w_admin_sq_head_ptr;
wire [7:0] w_io_sq1_head_ptr;
wire [7:0] w_io_sq2_head_ptr;
wire [7:0] w_io_sq3_head_ptr;
wire [7:0] w_io_sq4_head_ptr;
wire [7:0] w_io_sq5_head_ptr;
wire [7:0] w_io_sq6_head_ptr;
wire [7:0] w_io_sq7_head_ptr;
wire [7:0] w_io_sq8_head_ptr;
pcie_hcmd_table
pcie_hcmd_table_inst0(
.wr_clk (pcie_user_clk),
.wr_en (w_hcmd_table_wr_en),
.wr_addr (w_hcmd_table_wr_addr),
.wr_data (w_hcmd_table_wr_data),
.rd_clk (cpu_bus_clk),
.rd_addr (hcmd_table_rd_addr),
.rd_data (hcmd_table_rd_data)
);
pcie_hcmd_table_cid
pcie_hcmd_table_cid_isnt0(
.clk (pcie_user_clk),
.wr_en (w_hcmd_cid_wr_en),
.wr_addr (w_hcmd_cid_wr_addr),
.wr_data (w_hcmd_cid_wr_data),
.rd_addr (w_hcmd_cid_rd_addr),
.rd_data (w_hcmd_cid_rd_data)
);
pcie_hcmd_table_prp
pcie_hcmd_table_prp_isnt0(
.clk (pcie_user_clk),
.wr_en (w_hcmd_prp_wr_en),
.wr_addr (w_hcmd_prp_wr_addr),
.wr_data (w_hcmd_prp_wr_data),
.rd_addr (hcmd_prp_rd_addr),
.rd_data (hcmd_prp_rd_data)
);
pcie_hcmd_nlb
pcie_hcmd_nlb_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (w_hcmd_nlb_wr0_en),
.wr0_addr (w_hcmd_nlb_wr0_addr),
.wr0_data (w_hcmd_nlb_wr0_data),
.wr0_rdy_n (w_hcmd_nlb_wr0_rdy_n),
.wr1_en (hcmd_nlb_wr1_en),
.wr1_addr (hcmd_nlb_wr1_addr),
.wr1_data (hcmd_nlb_wr1_data),
.wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.rd_addr (hcmd_nlb_rd_addr),
.rd_data (hcmd_nlb_rd_data)
);
pcie_hcmd_slot_mgt
pcie_hcmd_slot_mgt_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.hcmd_slot_rdy (w_hcmd_slot_rdy),
.hcmd_slot_tag (w_hcmd_slot_tag),
.hcmd_slot_alloc_en (w_hcmd_slot_alloc_en),
.hcmd_slot_free_en (w_hcmd_slot_free_en),
.hcmd_slot_invalid_tag (w_hcmd_slot_invalid_tag)
);
pcie_hcmd_sq # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_sq_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.admin_sq_bs_addr (admin_sq_bs_addr),
.admin_sq_size (admin_sq_size),
.admin_sq_tail_ptr (admin_sq_tail_ptr),
.io_sq1_tail_ptr (io_sq1_tail_ptr),
.io_sq2_tail_ptr (io_sq2_tail_ptr),
.io_sq3_tail_ptr (io_sq3_tail_ptr),
.io_sq4_tail_ptr (io_sq4_tail_ptr),
.io_sq5_tail_ptr (io_sq5_tail_ptr),
.io_sq6_tail_ptr (io_sq6_tail_ptr),
.io_sq7_tail_ptr (io_sq7_tail_ptr),
.io_sq8_tail_ptr (io_sq8_tail_ptr),
.admin_sq_head_ptr (w_admin_sq_head_ptr),
.io_sq1_head_ptr (w_io_sq1_head_ptr),
.io_sq2_head_ptr (w_io_sq2_head_ptr),
.io_sq3_head_ptr (w_io_sq3_head_ptr),
.io_sq4_head_ptr (w_io_sq4_head_ptr),
.io_sq5_head_ptr (w_io_sq5_head_ptr),
.io_sq6_head_ptr (w_io_sq6_head_ptr),
.io_sq7_head_ptr (w_io_sq7_head_ptr),
.io_sq8_head_ptr (w_io_sq8_head_ptr),
.hcmd_slot_rdy (w_hcmd_slot_rdy),
.hcmd_slot_tag (w_hcmd_slot_tag),
.hcmd_slot_alloc_en (w_hcmd_slot_alloc_en),
.cpld_sq_fifo_tag (cpld_sq_fifo_tag),
.cpld_sq_fifo_wr_data (cpld_sq_fifo_wr_data),
.cpld_sq_fifo_wr_en (cpld_sq_fifo_wr_en),
.cpld_sq_fifo_tag_last (cpld_sq_fifo_tag_last),
.tx_mrd_req (tx_mrd_req),
.tx_mrd_tag (tx_mrd_tag),
.tx_mrd_len (tx_mrd_len),
.tx_mrd_addr (tx_mrd_addr),
.tx_mrd_req_ack (tx_mrd_req_ack),
.hcmd_table_wr_en (w_hcmd_table_wr_en),
.hcmd_table_wr_addr (w_hcmd_table_wr_addr),
.hcmd_table_wr_data (w_hcmd_table_wr_data),
.hcmd_cid_wr_en (w_hcmd_cid_wr_en),
.hcmd_cid_wr_addr (w_hcmd_cid_wr_addr),
.hcmd_cid_wr_data (w_hcmd_cid_wr_data),
.hcmd_prp_wr_en (w_hcmd_prp_wr_en),
.hcmd_prp_wr_addr (w_hcmd_prp_wr_addr),
.hcmd_prp_wr_data (w_hcmd_prp_wr_data),
.hcmd_nlb_wr0_en (w_hcmd_nlb_wr0_en),
.hcmd_nlb_wr0_addr (w_hcmd_nlb_wr0_addr),
.hcmd_nlb_wr0_data (w_hcmd_nlb_wr0_data),
.hcmd_nlb_wr0_rdy_n (w_hcmd_nlb_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.sq_rst_n (sq_rst_n),
.sq_valid (sq_valid),
.io_sq1_size (io_sq1_size),
.io_sq2_size (io_sq2_size),
.io_sq3_size (io_sq3_size),
.io_sq4_size (io_sq4_size),
.io_sq5_size (io_sq5_size),
.io_sq6_size (io_sq6_size),
.io_sq7_size (io_sq7_size),
.io_sq8_size (io_sq8_size),
.io_sq1_bs_addr (io_sq1_bs_addr),
.io_sq2_bs_addr (io_sq2_bs_addr),
.io_sq3_bs_addr (io_sq3_bs_addr),
.io_sq4_bs_addr (io_sq4_bs_addr),
.io_sq5_bs_addr (io_sq5_bs_addr),
.io_sq6_bs_addr (io_sq6_bs_addr),
.io_sq7_bs_addr (io_sq7_bs_addr),
.io_sq8_bs_addr (io_sq8_bs_addr),
.hcmd_sq_rd_en (hcmd_sq_rd_en),
.hcmd_sq_rd_data (hcmd_sq_rd_data),
.hcmd_sq_empty_n (hcmd_sq_empty_n)
);
pcie_hcmd_cq # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_hcmd_cq_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.hcmd_cid_rd_addr (w_hcmd_cid_rd_addr),
.hcmd_cid_rd_data (w_hcmd_cid_rd_data),
.admin_cq_bs_addr (admin_cq_bs_addr),
.admin_cq_size (admin_cq_size),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_sq_head_ptr (w_admin_sq_head_ptr),
.io_sq1_head_ptr (w_io_sq1_head_ptr),
.io_sq2_head_ptr (w_io_sq2_head_ptr),
.io_sq3_head_ptr (w_io_sq3_head_ptr),
.io_sq4_head_ptr (w_io_sq4_head_ptr),
.io_sq5_head_ptr (w_io_sq5_head_ptr),
.io_sq6_head_ptr (w_io_sq6_head_ptr),
.io_sq7_head_ptr (w_io_sq7_head_ptr),
.io_sq8_head_ptr (w_io_sq8_head_ptr),
.hcmd_slot_free_en (w_hcmd_slot_free_en),
.hcmd_slot_invalid_tag (w_hcmd_slot_invalid_tag),
.tx_cq_mwr_req (tx_cq_mwr_req),
.tx_cq_mwr_tag (tx_cq_mwr_tag),
.tx_cq_mwr_len (tx_cq_mwr_len),
.tx_cq_mwr_addr (tx_cq_mwr_addr),
.tx_cq_mwr_req_ack (tx_cq_mwr_req_ack),
.tx_cq_mwr_rd_en (tx_cq_mwr_rd_en),
.tx_cq_mwr_rd_data (tx_cq_mwr_rd_data),
.tx_cq_mwr_data_last (tx_cq_mwr_data_last),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.io_sq1_cq_vec (io_sq1_cq_vec),
.io_sq2_cq_vec (io_sq2_cq_vec),
.io_sq3_cq_vec (io_sq3_cq_vec),
.io_sq4_cq_vec (io_sq4_cq_vec),
.io_sq5_cq_vec (io_sq5_cq_vec),
.io_sq6_cq_vec (io_sq6_cq_vec),
.io_sq7_cq_vec (io_sq7_cq_vec),
.io_sq8_cq_vec (io_sq8_cq_vec),
.sq_valid (sq_valid),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq1_size (io_cq1_size),
.io_cq2_size (io_cq2_size),
.io_cq3_size (io_cq3_size),
.io_cq4_size (io_cq4_size),
.io_cq5_size (io_cq5_size),
.io_cq6_size (io_cq6_size),
.io_cq7_size (io_cq7_size),
.io_cq8_size (io_cq8_size),
.io_cq1_bs_addr (io_cq1_bs_addr),
.io_cq2_bs_addr (io_cq2_bs_addr),
.io_cq3_bs_addr (io_cq3_bs_addr),
.io_cq4_bs_addr (io_cq4_bs_addr),
.io_cq5_bs_addr (io_cq5_bs_addr),
.io_cq6_bs_addr (io_cq6_bs_addr),
.io_cq7_bs_addr (io_cq7_bs_addr),
.io_cq8_bs_addr (io_cq8_bs_addr),
.hcmd_cq_wr1_en (hcmd_cq_wr1_en),
.hcmd_cq_wr1_data0 (hcmd_cq_wr1_data0),
.hcmd_cq_wr1_data1 (hcmd_cq_wr1_data1),
.hcmd_cq_wr1_rdy_n (hcmd_cq_wr1_rdy_n)
);
endmodule |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
niosii_nios2_gen2_0_cpu_debug_slave_tck the_niosii_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
niosii_nios2_gen2_0_cpu_debug_slave_sysclk the_niosii_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic niosii_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
niosii_nios2_gen2_0_cpu_debug_slave_tck the_niosii_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
niosii_nios2_gen2_0_cpu_debug_slave_sysclk the_niosii_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic niosii_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_nios2_gen2_0_cpu_debug_slave_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
niosii_nios2_gen2_0_cpu_debug_slave_tck the_niosii_nios2_gen2_0_cpu_debug_slave_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
niosii_nios2_gen2_0_cpu_debug_slave_sysclk the_niosii_nios2_gen2_0_cpu_debug_slave_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic niosii_nios2_gen2_0_cpu_debug_slave_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_auto_instance_index = "YES",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_instance_index = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_ir_width = 2,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_mfg_id = 70,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_action = "",
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_n_scan = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_sim_total_length = 0,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_type_id = 34,
// niosii_nios2_gen2_0_cpu_debug_slave_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
`include "def_pcie.vh"
module pcie_tx_arb # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] pcie_dev_id,
input tx_cpld_gnt,
input tx_mrd_gnt,
input tx_mwr_gnt,
input tx_cpld_req,
input [7:0] tx_cpld_tag,
input [15:0] tx_cpld_req_id,
input [11:2] tx_cpld_len,
input [11:0] tx_cpld_bc,
input [6:0] tx_cpld_laddr,
input [63:0] tx_cpld_data,
output tx_cpld_req_ack,
input tx_mrd0_req,
input [7:0] tx_mrd0_tag,
input [11:2] tx_mrd0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd0_addr,
output tx_mrd0_req_ack,
input tx_mrd1_req,
input [7:0] tx_mrd1_tag,
input [11:2] tx_mrd1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd1_addr,
output tx_mrd1_req_ack,
input tx_mrd2_req,
input [7:0] tx_mrd2_tag,
input [11:2] tx_mrd2_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd2_addr,
output tx_mrd2_req_ack,
input tx_mwr0_req,
input [7:0] tx_mwr0_tag,
input [11:2] tx_mwr0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr0_addr,
output tx_mwr0_req_ack,
input tx_mwr1_req,
input [7:0] tx_mwr1_tag,
input [11:2] tx_mwr1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr1_addr,
output tx_mwr1_req_ack,
output tx_arb_valid,
output [5:0] tx_arb_gnt,
output [2:0] tx_arb_type,
output [11:2] tx_pcie_len,
output [127:0] tx_pcie_head,
output [31:0] tx_cpld_udata,
input tx_arb_rdy
);
reg [5:0] r_tx_req;
reg [5:0] r_tx_req_en;
wire [5:0] w_tx_req_en;
wire [5:0] w_tx_req_gnt;
reg [5:0] r_tx_req_ack;
wire [5:0] w_tx_req_ack;
reg [2:0] r_tx_type;
reg [5:0] r_tx_arb;
reg [5:0] r_tx_arb_cur;
reg [2:0] r_tx_arb_type;
reg [31:0] r_tx_pcie_head0;
reg [31:0] r_tx_pcie_head1;
reg [31:0] r_tx_pcie_head2;
reg [31:0] r_tx_pcie_head3;
assign tx_arb_valid = (r_tx_arb_cur[5] | r_tx_arb_cur[4]) | (r_tx_arb_cur[3] | r_tx_arb_cur[2]) | (r_tx_arb_cur[1] | r_tx_arb_cur[0]);
assign tx_arb_gnt = r_tx_arb_cur;
assign tx_arb_type = r_tx_arb_type;
assign tx_pcie_len = r_tx_pcie_head0[9:0];
assign tx_pcie_head = {r_tx_pcie_head3, r_tx_pcie_head2, r_tx_pcie_head1, r_tx_pcie_head0};
assign tx_cpld_udata = tx_cpld_data[63:32];
assign tx_cpld_req_ack = r_tx_req_ack[0];
assign tx_mrd0_req_ack = r_tx_req_ack[1];
assign tx_mrd1_req_ack = r_tx_req_ack[2];
assign tx_mrd2_req_ack = r_tx_req_ack[3];
assign tx_mwr0_req_ack = r_tx_req_ack[4];
assign tx_mwr1_req_ack = r_tx_req_ack[5];
assign w_tx_req_ack[0] = tx_arb_rdy & r_tx_arb_cur[0];
assign w_tx_req_ack[1] = tx_arb_rdy & r_tx_arb_cur[1];
assign w_tx_req_ack[2] = tx_arb_rdy & r_tx_arb_cur[2];
assign w_tx_req_ack[3] = tx_arb_rdy & r_tx_arb_cur[3];
assign w_tx_req_ack[4] = tx_arb_rdy & r_tx_arb_cur[4];
assign w_tx_req_ack[5] = tx_arb_rdy & r_tx_arb_cur[5];
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_tx_req <= 0;
end
else begin
if(tx_cpld_req == 1)
r_tx_req[0] <= 1;
else if(w_tx_req_ack[0] == 1)
r_tx_req[0] <= 0;
if(tx_mrd0_req == 1)
r_tx_req[1] <= 1;
else if(w_tx_req_ack[1] == 1)
r_tx_req[1] <= 0;
if(tx_mrd1_req == 1)
r_tx_req[2] <= 1;
else if(w_tx_req_ack[2] == 1)
r_tx_req[2] <= 0;
if(tx_mrd2_req == 1)
r_tx_req[3] <= 1;
else if(w_tx_req_ack[3] == 1)
r_tx_req[3] <= 0;
if(tx_mwr0_req == 1)
r_tx_req[4] <= 1;
else if(w_tx_req_ack[4] == 1)
r_tx_req[4] <= 0;
if(tx_mwr1_req == 1)
r_tx_req[5] <= 1;
else if(w_tx_req_ack[5] == 1)
r_tx_req[5] <= 0;
end
end
always @ (*)
begin
if(tx_arb_rdy == 1)
r_tx_req_en <= r_tx_req & ~r_tx_arb_cur;
else
r_tx_req_en <= r_tx_req;
end
assign w_tx_req_gnt[0] = tx_cpld_gnt;
assign w_tx_req_gnt[1] = tx_mrd_gnt;
assign w_tx_req_gnt[2] = tx_mrd_gnt;
assign w_tx_req_gnt[3] = tx_mrd_gnt;
assign w_tx_req_gnt[4] = tx_mwr_gnt;
assign w_tx_req_gnt[5] = tx_mwr_gnt;
assign w_tx_req_en = r_tx_req_en & w_tx_req_gnt;
always @ (*)
begin
if(w_tx_req_en[0] == 1) begin
r_tx_type <= 3'b001;
r_tx_arb <= 6'b000001;
end
else if(w_tx_req_en[1] == 1) begin
r_tx_type <= 3'b010;
r_tx_arb <= 6'b000010;
end
else if(w_tx_req_en[2] == 1) begin
r_tx_type <= 3'b010;
r_tx_arb <= 6'b000100;
end
else if(w_tx_req_en[4] == 1) begin
r_tx_type <= 3'b100;
r_tx_arb <= 6'b010000;
end
else if(w_tx_req_en[3] == 1) begin
r_tx_type <= 3'b010;
r_tx_arb <= 6'b001000;
end
else if(w_tx_req_en[5] == 1) begin
r_tx_type <= 3'b100;
r_tx_arb <= 6'b100000;
end
else begin
r_tx_type <= 3'b000;
r_tx_arb <= 6'b000000;
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
r_tx_arb_cur <= 0;
else
r_tx_arb_cur <= r_tx_arb;
end
always @ (posedge pcie_user_clk)
begin
r_tx_arb_type <= r_tx_type;
r_tx_req_ack <= w_tx_req_ack;
end
always @ (*)
begin
case(r_tx_arb_cur) // synthesis parallel_case full_case
6'b000001: begin
r_tx_pcie_head0 <= {`D_CPLD_FMT, `D_CPLD_TYPE, 1'b0, `D_CPLD_TC, 1'b0, `D_CPLD_ATTR1, 1'b0, `D_CPLD_TH, `D_CPLD_TD, `D_CPLD_EP, `D_CPLD_ATTR2, `D_CPLD_AT, tx_cpld_len};
r_tx_pcie_head1 <= {pcie_dev_id, `D_CPLD_CS, `D_CPLD_BCM, tx_cpld_bc};
r_tx_pcie_head2 <= {tx_cpld_req_id, tx_cpld_tag, 1'b0, tx_cpld_laddr};
r_tx_pcie_head3 <= tx_cpld_data[31:0];
end
6'b000010: begin
r_tx_pcie_head0 <= {`D_MRD_FMT, `D_MRD_TYPE, 1'b0, `D_MRD_TC, 1'b0, `D_MRD_ATTR1, 1'b0, `D_MRD_TH, `D_MRD_TD, `D_MRD_EP, `D_MRD_ATTR2, `D_MRD_AT, tx_mrd0_len};
r_tx_pcie_head1 <= {pcie_dev_id, tx_mrd0_tag, `D_MRD_LAST_BE, `D_MRD_1ST_BE};
r_tx_pcie_head2 <= {28'b0, tx_mrd0_addr[C_PCIE_ADDR_WIDTH-1:32]};
r_tx_pcie_head3 <= {tx_mrd0_addr[31:2], 2'b0};
end
6'b000100: begin
r_tx_pcie_head0 <= {`D_MRD_FMT, `D_MRD_TYPE, 1'b0, `D_MRD_TC, 1'b0, `D_MRD_ATTR1, 1'b0, `D_MRD_TH, `D_MRD_TD, `D_MRD_EP, `D_MRD_ATTR2, `D_MRD_AT, tx_mrd1_len};
r_tx_pcie_head1 <= {pcie_dev_id, tx_mrd1_tag, `D_MRD_LAST_BE, `D_MRD_1ST_BE};
r_tx_pcie_head2 <= {28'b0, tx_mrd1_addr[C_PCIE_ADDR_WIDTH-1:32]};
r_tx_pcie_head3 <= {tx_mrd1_addr[31:2], 2'b0};
end
6'b001000: begin
r_tx_pcie_head0 <= {`D_MRD_FMT, `D_MRD_TYPE, 1'b0, `D_MRD_TC, 1'b0, `D_MRD_ATTR1, 1'b0, `D_MRD_TH, `D_MRD_TD, `D_MRD_EP, `D_MRD_ATTR2, `D_MRD_AT, tx_mrd2_len};
r_tx_pcie_head1 <= {pcie_dev_id, tx_mrd2_tag, `D_MRD_LAST_BE, `D_MRD_1ST_BE};
r_tx_pcie_head2 <= {28'b0, tx_mrd2_addr[C_PCIE_ADDR_WIDTH-1:32]};
r_tx_pcie_head3 <= {tx_mrd2_addr[31:2], 2'b0};
end
6'b010000: begin
r_tx_pcie_head0 <= {`D_MWR_FMT, `D_MWR_TYPE, 1'b0, `D_MWR_TC, 1'b0, `D_MWR_ATTR1, 1'b0, `D_MWR_TH, `D_MWR_TD, `D_MWR_EP, `D_MWR_ATTR2, `D_MWR_AT, tx_mwr0_len};
r_tx_pcie_head1 <= {pcie_dev_id, tx_mwr0_tag, `D_MWR_LAST_BE, `D_MWR_1ST_BE};
r_tx_pcie_head2 <= {28'b0, tx_mwr0_addr[C_PCIE_ADDR_WIDTH-1:32]};
r_tx_pcie_head3 <= {tx_mwr0_addr[31:2], 2'b0};
end
6'b100000: begin
r_tx_pcie_head0 <= {`D_MWR_FMT, `D_MWR_TYPE, 1'b0, `D_MWR_TC, 1'b0, `D_MWR_ATTR1, 1'b0, `D_MWR_TH, `D_MWR_TD, `D_MWR_EP, `D_MWR_ATTR2, `D_MWR_AT, tx_mwr1_len};
r_tx_pcie_head1 <= {pcie_dev_id, tx_mwr1_tag, `D_MWR_LAST_BE, `D_MWR_1ST_BE};
r_tx_pcie_head2 <= {28'b0, tx_mwr1_addr[C_PCIE_ADDR_WIDTH-1:32]};
r_tx_pcie_head3 <= {tx_mwr1_addr[31:2], 2'b0};
end
endcase
end
endmodule |
// soc_design_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_design_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
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