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/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 20:13:38 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1,
OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2, SIGN_FLAG_SHT2,
OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2,
SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n1037, n1038, n1039, n1040,
n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050,
n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060,
n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070,
n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080,
n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090,
n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100,
n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110,
n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120,
n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130,
n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140,
n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150,
n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190,
n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200,
n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1628, n1629, n1630, n1631, n1632,
n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642,
n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652,
n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662,
n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672,
n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682,
n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692,
n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1822, n1823, n1824,
DP_OP_15J75_123_4372_n11, DP_OP_15J75_123_4372_n10,
DP_OP_15J75_123_4372_n9, DP_OP_15J75_123_4372_n8,
DP_OP_15J75_123_4372_n7, DP_OP_15J75_123_4372_n6, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987,
n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997,
n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007,
n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017,
n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027,
n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037,
n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047,
n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057,
n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067,
n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077,
n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087,
n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097,
n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107,
n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117,
n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127,
n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137,
n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147,
n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157,
n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167,
n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177,
n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187,
n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197,
n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207,
n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217,
n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227,
n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237,
n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257,
n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267,
n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277,
n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287,
n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297,
n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307,
n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347,
n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357,
n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367,
n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377,
n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387,
n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397,
n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407,
n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417,
n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427,
n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437,
n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447,
n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457,
n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467,
n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477,
n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487,
n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497,
n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507,
n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517,
n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527,
n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537,
n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547,
n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557,
n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567,
n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577,
n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587,
n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597,
n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607,
n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617,
n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627,
n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637,
n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647,
n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657,
n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667,
n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677,
n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687,
n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697,
n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707,
n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717,
n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727,
n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737,
n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747,
n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757,
n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767,
n2768, n2769, n2770, n2771, n2773, n2774, n2775, n2776, n2777, n2778,
n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788,
n2789, n2790, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799,
n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809,
n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819,
n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829,
n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839,
n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849,
n2850, n2851, n2852, n2854, n2855, n2856, n2857, n2858, n2859, n2860,
n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870,
n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880,
n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890,
n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900,
n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910,
n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920,
n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930,
n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940,
n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950,
n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960,
n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970,
n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980,
n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990,
n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000,
n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010,
n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020,
n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030,
n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040,
n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050,
n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060,
n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070,
n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080,
n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090,
n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100,
n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122,
n3123, n3124, n3125, n3126, n3127, n3128, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143,
n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173,
n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183,
n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193,
n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203,
n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213,
n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223,
n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233,
n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243,
n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3530;
wire [1:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:0] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:1] DmP_mant_SHT1_SW;
wire [5:1] Shift_amount_SHT1_EWR;
wire [54:0] Raw_mant_NRM_SWR;
wire [34:0] Data_array_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [5:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:0] LZD_output_NRM2_EW;
wire [5:1] exp_rslt_NRM2_EW1;
wire [62:0] DMP_SFG;
wire [45:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_6_ ( .D(n1822), .CK(clk), .RN(n3507), .Q(
n1832), .QN(n1997) );
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n1819), .CK(clk), .RN(n3471), .QN(
n1865) );
DFFRXLTS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1751), .CK(clk), .RN(n3492), .Q(
intAS) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(n3468), .CK(clk), .RN(n3494), .Q(ready) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n1683), .CK(clk), .RN(n3486), .QN(
n1841) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n1669), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[20]), .QN(n3456) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n1668), .CK(clk), .RN(n3486), .Q(
Data_array_SWR[19]), .QN(n3455) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n1667), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[18]), .QN(n3457) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n1666), .CK(clk), .RN(n3478), .QN(
n1836) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n1665), .CK(clk), .RN(n3477), .QN(
n1834) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n1664), .CK(clk), .RN(n3477), .QN(
n1838) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n1663), .CK(clk), .RN(n3477), .QN(
n1837) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n1662), .CK(clk), .RN(n3517), .QN(
n1828) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n1661), .CK(clk), .RN(n3478), .QN(
n1869) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n1659), .CK(clk), .RN(n3478), .QN(
n1874) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1653), .CK(clk), .RN(n3478), .QN(
n1879) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1651), .CK(clk), .RN(n3478), .QN(
n1878) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1649), .CK(clk), .RN(n3477), .QN(
n1830) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1646), .CK(clk), .RN(n3517), .QN(
n1831) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1645), .CK(clk), .RN(n3477), .QN(
n1842) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1644), .CK(clk), .RN(n3478), .QN(
n1844) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1643), .CK(clk), .RN(n3477), .QN(
n1843) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1642), .CK(clk), .RN(n3477), .QN(
n1845) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1641), .CK(clk), .RN(n3477), .QN(
n1846) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1640), .CK(clk), .RN(n3494), .QN(
n1847) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1639), .CK(clk), .RN(n3477), .QN(
n1848) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1634), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[3]) );
DFFRXLTS SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n1676), .CK(clk), .RN(n3482), .QN(
n1839) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1625), .CK(clk), .RN(n3484),
.QN(n1840) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1624), .CK(clk), .RN(n3525),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1623), .CK(clk), .RN(n3496),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1622), .CK(clk), .RN(n3519),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1621), .CK(clk), .RN(n3484),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1620), .CK(clk), .RN(n3522),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1619), .CK(clk), .RN(n3514), .Q(
final_result_ieee[52]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1618), .CK(clk), .RN(n3508), .Q(
final_result_ieee[53]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1617), .CK(clk), .RN(n3514), .Q(
final_result_ieee[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1616), .CK(clk), .RN(n3508), .Q(
final_result_ieee[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1615), .CK(clk), .RN(n3484), .Q(
final_result_ieee[56]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1614), .CK(clk), .RN(n3521), .Q(
final_result_ieee[57]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1613), .CK(clk), .RN(n3511), .Q(
final_result_ieee[58]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1612), .CK(clk), .RN(n3484), .Q(
final_result_ieee[59]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1611), .CK(clk), .RN(n3521), .Q(
final_result_ieee[60]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1610), .CK(clk), .RN(n3510), .Q(
final_result_ieee[61]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1609), .CK(clk), .RN(n3511), .Q(
final_result_ieee[62]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1608), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1607), .CK(clk), .RN(n3513), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1606), .CK(clk), .RN(n3486), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1605), .CK(clk), .RN(n3482), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1604), .CK(clk), .RN(n3512), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1603), .CK(clk), .RN(n3485), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1602), .CK(clk), .RN(n3511), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1601), .CK(clk), .RN(n3511), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1600), .CK(clk), .RN(n3522), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1599), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1598), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1597), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1596), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1595), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1594), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1593), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1592), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1591), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1590), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1589), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1588), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1587), .CK(clk), .RN(n3480), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1586), .CK(clk), .RN(n3491), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1585), .CK(clk), .RN(n3483), .Q(
DMP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1584), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[24]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1583), .CK(clk), .RN(n3483), .Q(
DMP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1582), .CK(clk), .RN(n3511), .Q(
DMP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1581), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1580), .CK(clk), .RN(n3483), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1579), .CK(clk), .RN(n3488), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1578), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1577), .CK(clk), .RN(n3482), .Q(
DMP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1576), .CK(clk), .RN(n3491), .Q(
DMP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1575), .CK(clk), .RN(n3525), .Q(
DMP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_34_ ( .D(n1574), .CK(clk), .RN(n3530), .Q(
DMP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1573), .CK(clk), .RN(n3485), .Q(
DMP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1572), .CK(clk), .RN(n3530), .Q(
DMP_EXP_EWSW[36]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1571), .CK(clk), .RN(n3488), .Q(
DMP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_38_ ( .D(n1570), .CK(clk), .RN(n3530), .Q(
DMP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1569), .CK(clk), .RN(n3483), .Q(
DMP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1568), .CK(clk), .RN(n3511), .Q(
DMP_EXP_EWSW[40]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1567), .CK(clk), .RN(n3514), .Q(
DMP_EXP_EWSW[41]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1566), .CK(clk), .RN(n3518), .Q(
DMP_EXP_EWSW[42]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1565), .CK(clk), .RN(n3516), .Q(
DMP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1564), .CK(clk), .RN(n3503), .Q(
DMP_EXP_EWSW[44]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1563), .CK(clk), .RN(n3530), .Q(
DMP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1562), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[46]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1561), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1560), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[48]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1559), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_50_ ( .D(n1558), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1557), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[51]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1550), .CK(clk), .RN(n3506), .Q(
DMP_EXP_EWSW[58]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1549), .CK(clk), .RN(n3479), .Q(
DMP_EXP_EWSW[59]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1548), .CK(clk), .RN(n3503), .Q(
DMP_EXP_EWSW[60]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1547), .CK(clk), .RN(n3475), .Q(
DMP_EXP_EWSW[61]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1546), .CK(clk), .RN(n3497), .Q(
DMP_EXP_EWSW[62]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1545), .CK(clk), .RN(n3498), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1544), .CK(clk), .RN(n3492), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1543), .CK(clk), .RN(n3525), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1542), .CK(clk), .RN(n3505), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1541), .CK(clk), .RN(n3472), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1539), .CK(clk), .RN(n3506), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1538), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1536), .CK(clk), .RN(n3500), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1535), .CK(clk), .RN(n3517), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1534), .CK(clk), .RN(n3481), .Q(
DMP_SFG[2]), .QN(n3466) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1533), .CK(clk), .RN(n3496), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1532), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1530), .CK(clk), .RN(n3524), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1529), .CK(clk), .RN(n3499), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1528), .CK(clk), .RN(n3510), .QN(n1849) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1527), .CK(clk), .RN(n3500), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1526), .CK(clk), .RN(n3522), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1524), .CK(clk), .RN(n3518), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1523), .CK(clk), .RN(n3493), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1522), .CK(clk), .RN(n3515), .QN(n1880) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1521), .CK(clk), .RN(n3504), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1520), .CK(clk), .RN(n3482), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1518), .CK(clk), .RN(n3492), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1517), .CK(clk), .RN(n3524), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1515), .CK(clk), .RN(n3518), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1514), .CK(clk), .RN(n3483), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1512), .CK(clk), .RN(n3483), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1511), .CK(clk), .RN(n3483), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1509), .CK(clk), .RN(n3483), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1508), .CK(clk), .RN(n3483), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1506), .CK(clk), .RN(n3483), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1505), .CK(clk), .RN(n3483), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1503), .CK(clk), .RN(n3483), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1502), .CK(clk), .RN(n3510), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1500), .CK(clk), .RN(n3521), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1499), .CK(clk), .RN(n3484), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1497), .CK(clk), .RN(n3513), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1496), .CK(clk), .RN(n3512), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1494), .CK(clk), .RN(n3511), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1493), .CK(clk), .RN(n3510), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1491), .CK(clk), .RN(n3521), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1490), .CK(clk), .RN(n3508), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1488), .CK(clk), .RN(n3508), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1487), .CK(clk), .RN(n3480), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1485), .CK(clk), .RN(n3478), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1484), .CK(clk), .RN(n3477), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1482), .CK(clk), .RN(n3494), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1481), .CK(clk), .RN(n3487), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1479), .CK(clk), .RN(n3521), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1478), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1476), .CK(clk), .RN(n3522), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1475), .CK(clk), .RN(n3486), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1473), .CK(clk), .RN(n3485), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1472), .CK(clk), .RN(n3522), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1470), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1469), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1467), .CK(clk), .RN(n3522), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1466), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1464), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1463), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1461), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1460), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1458), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1457), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1455), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1454), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1452), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1451), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1449), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[31]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1448), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[31]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1446), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[32]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1445), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[32]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1443), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[33]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1442), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[33]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1440), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[34]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1439), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[34]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1437), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[35]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1436), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[35]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1434), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[36]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1433), .CK(clk), .RN(n3519), .Q(
DMP_SHT2_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1431), .CK(clk), .RN(n3488), .Q(
DMP_SHT1_EWSW[37]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1430), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[37]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1428), .CK(clk), .RN(n3489), .Q(
DMP_SHT1_EWSW[38]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1427), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[38]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1425), .CK(clk), .RN(n3489), .Q(
DMP_SHT1_EWSW[39]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1424), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[39]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1422), .CK(clk), .RN(n3489), .Q(
DMP_SHT1_EWSW[40]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1421), .CK(clk), .RN(n3489), .Q(
DMP_SHT2_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1419), .CK(clk), .RN(n3489), .Q(
DMP_SHT1_EWSW[41]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1418), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1416), .CK(clk), .RN(n3490), .Q(
DMP_SHT1_EWSW[42]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1415), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[42]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1413), .CK(clk), .RN(n3490), .Q(
DMP_SHT1_EWSW[43]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1412), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[43]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1410), .CK(clk), .RN(n3490), .Q(
DMP_SHT1_EWSW[44]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1409), .CK(clk), .RN(n3490), .Q(
DMP_SHT2_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1407), .CK(clk), .RN(n3490), .Q(
DMP_SHT1_EWSW[45]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1406), .CK(clk), .RN(n3523), .Q(
DMP_SHT2_EWSW[45]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1404), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[46]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1403), .CK(clk), .RN(n3523), .Q(
DMP_SHT2_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1401), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[47]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1400), .CK(clk), .RN(n3523), .Q(
DMP_SHT2_EWSW[47]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1398), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[48]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1397), .CK(clk), .RN(n3523), .Q(
DMP_SHT2_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1395), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[49]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1394), .CK(clk), .RN(n3487), .Q(
DMP_SHT2_EWSW[49]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1392), .CK(clk), .RN(n3523), .Q(
DMP_SHT1_EWSW[50]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1391), .CK(clk), .RN(n3516), .Q(
DMP_SHT2_EWSW[50]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1389), .CK(clk), .RN(n3491), .Q(
DMP_SHT1_EWSW[51]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1388), .CK(clk), .RN(n3530), .Q(
DMP_SHT2_EWSW[51]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1386), .CK(clk), .RN(n3523), .Q(
DMP_SHT1_EWSW[52]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1385), .CK(clk), .RN(n3530), .Q(
DMP_SHT2_EWSW[52]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1384), .CK(clk), .RN(n3520), .Q(
DMP_SFG[52]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1383), .CK(clk), .RN(n3491), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1381), .CK(clk), .RN(n3493), .Q(
DMP_SHT1_EWSW[53]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1380), .CK(clk), .RN(n3515), .Q(
DMP_SHT2_EWSW[53]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1379), .CK(clk), .RN(n3504), .Q(
DMP_SFG[53]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1378), .CK(clk), .RN(n3482), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1376), .CK(clk), .RN(n3492), .Q(
DMP_SHT1_EWSW[54]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1375), .CK(clk), .RN(n3485), .Q(
DMP_SHT2_EWSW[54]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1374), .CK(clk), .RN(n3518), .Q(
DMP_SFG[54]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1373), .CK(clk), .RN(n3493), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1371), .CK(clk), .RN(n3515), .Q(
DMP_SHT1_EWSW[55]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1370), .CK(clk), .RN(n3504), .Q(
DMP_SHT2_EWSW[55]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1369), .CK(clk), .RN(n3482), .Q(
DMP_SFG[55]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1368), .CK(clk), .RN(n3492), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1366), .CK(clk), .RN(n3515), .Q(
DMP_SHT1_EWSW[56]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1365), .CK(clk), .RN(n3504), .Q(
DMP_SHT2_EWSW[56]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1364), .CK(clk), .RN(n3482), .Q(
DMP_SFG[56]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1363), .CK(clk), .RN(n3492), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1361), .CK(clk), .RN(n3486), .Q(
DMP_SHT1_EWSW[57]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1360), .CK(clk), .RN(n3518), .Q(
DMP_SHT2_EWSW[57]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1359), .CK(clk), .RN(n3493), .Q(
DMP_SFG[57]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1358), .CK(clk), .RN(n3515), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1356), .CK(clk), .RN(n3504), .Q(
DMP_SHT1_EWSW[58]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1355), .CK(clk), .RN(n3482), .Q(
DMP_SHT2_EWSW[58]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1354), .CK(clk), .RN(n3492), .Q(
DMP_SFG[58]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1353), .CK(clk), .RN(n3501), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1351), .CK(clk), .RN(n3515), .Q(
DMP_SHT1_EWSW[59]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1350), .CK(clk), .RN(n3504), .Q(
DMP_SHT2_EWSW[59]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1349), .CK(clk), .RN(n3482), .Q(
DMP_SFG[59]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1348), .CK(clk), .RN(n3492), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1346), .CK(clk), .RN(n3478), .Q(
DMP_SHT1_EWSW[60]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1345), .CK(clk), .RN(n3515), .Q(
DMP_SHT2_EWSW[60]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1344), .CK(clk), .RN(n3493), .Q(
DMP_SFG[60]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1343), .CK(clk), .RN(n3504), .Q(
DMP_exp_NRM_EW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1341), .CK(clk), .RN(n3482), .Q(
DMP_SHT1_EWSW[61]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1340), .CK(clk), .RN(n3492), .Q(
DMP_SHT2_EWSW[61]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1339), .CK(clk), .RN(n3507), .Q(
DMP_SFG[61]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1338), .CK(clk), .RN(n3493), .Q(
DMP_exp_NRM_EW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1336), .CK(clk), .RN(n3510), .Q(
DMP_SHT1_EWSW[62]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1335), .CK(clk), .RN(n3517), .Q(
DMP_SHT2_EWSW[62]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1334), .CK(clk), .RN(n3487), .Q(
DMP_SFG[62]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1333), .CK(clk), .RN(n3523), .Q(
DMP_exp_NRM_EW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1331), .CK(clk), .RN(n3517), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1330), .CK(clk), .RN(n3523),
.QN(n1850) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1329), .CK(clk), .RN(n3487), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1327), .CK(clk), .RN(n3517), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n3487), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1323), .CK(clk), .RN(n3517), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1322), .CK(clk), .RN(n3489),
.QN(n1852) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1321), .CK(clk), .RN(n3488), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1320), .CK(clk), .RN(n3521),
.QN(n1851) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1319), .CK(clk), .RN(n3517), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1317), .CK(clk), .RN(n3490), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1316), .CK(clk), .RN(n3517),
.QN(n1884) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1315), .CK(clk), .RN(n3487), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1313), .CK(clk), .RN(n3523), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1311), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1309), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1307), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1306), .CK(clk), .RN(n3494),
.QN(n1891) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1305), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1303), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1301), .CK(clk), .RN(n3494), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1300), .CK(clk), .RN(n3494),
.QN(n1888) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1299), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1297), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1295), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1293), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1292), .CK(clk), .RN(n3495),
.QN(n1892) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1291), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1289), .CK(clk), .RN(n3495), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1288), .CK(clk), .RN(n3495),
.QN(n1893) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1287), .CK(clk), .RN(n3474), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1285), .CK(clk), .RN(n3473), .Q(
DmP_EXP_EWSW[23]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1283), .CK(clk), .RN(n3520), .Q(
DmP_EXP_EWSW[24]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1282), .CK(clk), .RN(n3513),
.QN(n1885) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1281), .CK(clk), .RN(n3512), .Q(
DmP_EXP_EWSW[25]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1279), .CK(clk), .RN(n3530), .Q(
DmP_EXP_EWSW[26]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1277), .CK(clk), .RN(n3524), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1275), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1273), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[29]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1272), .CK(clk), .RN(n3496),
.QN(n1894) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1271), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1269), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[31]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1267), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[32]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1265), .CK(clk), .RN(n3496), .Q(
DmP_EXP_EWSW[33]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1263), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1261), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[35]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1259), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[36]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1258), .CK(clk), .RN(n3497),
.QN(n1889) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1257), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[37]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1255), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[38]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1253), .CK(clk), .RN(n3497), .Q(
DmP_EXP_EWSW[39]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1251), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[40]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1250), .CK(clk), .RN(n3498),
.QN(n1881) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1249), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[41]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1246), .CK(clk), .RN(n3498),
.QN(n1882) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1245), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[43]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1243), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[44]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1242), .CK(clk), .RN(n3498),
.QN(n1883) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1241), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[45]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1239), .CK(clk), .RN(n3482), .Q(
DmP_EXP_EWSW[46]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1238), .CK(clk), .RN(n3486),
.QN(n1890) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_47_ ( .D(n1237), .CK(clk), .RN(n3523), .Q(
DmP_EXP_EWSW[47]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1235), .CK(clk), .RN(n3509), .Q(
DmP_EXP_EWSW[48]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1234), .CK(clk), .RN(n3488),
.QN(n1895) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1233), .CK(clk), .RN(n3516), .Q(
DmP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1231), .CK(clk), .RN(n3493), .Q(
DmP_EXP_EWSW[50]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1229), .CK(clk), .RN(n3516), .Q(
DmP_EXP_EWSW[51]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1221), .CK(clk), .RN(n3500), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1220), .CK(clk), .RN(n3495), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1219), .CK(clk), .RN(n3499), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1218), .CK(clk), .RN(n3500), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1217), .CK(clk), .RN(n3495), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1216), .CK(clk), .RN(n3499), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1215), .CK(clk), .RN(n3500),
.Q(ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1214), .CK(clk), .RN(n3496), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1213), .CK(clk), .RN(n3499), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1212), .CK(clk), .RN(n3500), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1210), .CK(clk), .RN(n3509), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1209), .CK(clk), .RN(n3499), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1208), .CK(clk), .RN(n3500), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1207), .CK(clk), .RN(n3495), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1206), .CK(clk), .RN(n3499),
.Q(SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1205), .CK(clk), .RN(n3500), .Q(
final_result_ieee[63]) );
DFFRXLTS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1185), .CK(clk), .RN(n3502),
.QN(n1855) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1161), .CK(clk), .RN(n3508),
.Q(LZD_output_NRM2_EW[5]), .QN(n3406) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1155), .CK(clk), .RN(n3514),
.Q(LZD_output_NRM2_EW[4]), .QN(n3403) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1151), .CK(clk), .RN(n3508),
.Q(LZD_output_NRM2_EW[1]), .QN(n3371) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1148), .CK(clk), .RN(n3508),
.Q(LZD_output_NRM2_EW[3]), .QN(n3394) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1141), .CK(clk), .RN(n3472), .QN(
n1875) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1137), .CK(clk), .RN(n3514),
.Q(LZD_output_NRM2_EW[2]), .QN(n3395) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1134), .CK(clk), .RN(n3476), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1133), .CK(clk), .RN(n3475), .Q(
final_result_ieee[42]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1128), .CK(clk), .RN(n3497), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1127), .CK(clk), .RN(n3476), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1126), .CK(clk), .RN(n3475), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n1125), .CK(clk), .RN(n3503), .Q(
final_result_ieee[36]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1124), .CK(clk), .RN(n3473), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1123), .CK(clk), .RN(n3505), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1121), .CK(clk), .RN(n3503), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n1120), .CK(clk), .RN(n3472), .Q(
final_result_ieee[40]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1119), .CK(clk), .RN(n3474), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1118), .CK(clk), .RN(n3506), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1117), .CK(clk), .RN(n3472), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n1116), .CK(clk), .RN(n3472), .Q(
final_result_ieee[38]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1115), .CK(clk), .RN(n3505), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1114), .CK(clk), .RN(n3505), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1113), .CK(clk), .RN(n3507), .Q(
final_result_ieee[41]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1112), .CK(clk), .RN(n3471), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1111), .CK(clk), .RN(n3469), .Q(
final_result_ieee[44]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1110), .CK(clk), .RN(n3507), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1109), .CK(clk), .RN(n3471), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1108), .CK(clk), .RN(n3469), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1107), .CK(clk), .RN(n3507), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n1106), .CK(clk), .RN(n3471), .Q(
final_result_ieee[39]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1105), .CK(clk), .RN(n3469), .Q(
final_result_ieee[43]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1104), .CK(clk), .RN(n3507), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1103), .CK(clk), .RN(n3471), .Q(
final_result_ieee[46]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1102), .CK(clk), .RN(n3469), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n1101), .CK(clk), .RN(n3514), .Q(
final_result_ieee[32]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1100), .CK(clk), .RN(n3508), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n1099), .CK(clk), .RN(n3530), .Q(
final_result_ieee[34]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1098), .CK(clk), .RN(n3514), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1097), .CK(clk), .RN(n3508), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1096), .CK(clk), .RN(n3530), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1095), .CK(clk), .RN(n3514), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n1094), .CK(clk), .RN(n3508), .Q(
final_result_ieee[37]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1093), .CK(clk), .RN(n3530), .Q(
final_result_ieee[45]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1092), .CK(clk), .RN(n3514), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n1091), .CK(clk), .RN(n3508), .Q(
final_result_ieee[33]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1090), .CK(clk), .RN(n3514), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1089), .CK(clk), .RN(n3509), .Q(
final_result_ieee[48]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1088), .CK(clk), .RN(n3509), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1087), .CK(clk), .RN(n3509), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1086), .CK(clk), .RN(n3509), .Q(
final_result_ieee[31]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1085), .CK(clk), .RN(n3509), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n1084), .CK(clk), .RN(n3509), .Q(
final_result_ieee[35]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1083), .CK(clk), .RN(n3509), .Q(
final_result_ieee[47]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1082), .CK(clk), .RN(n3509), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1081), .CK(clk), .RN(n3509), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1080), .CK(clk), .RN(n3509), .Q(
final_result_ieee[49]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1079), .CK(clk), .RN(n3509), .Q(
final_result_ieee[50]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1078), .CK(clk), .RN(n3509), .Q(
final_result_ieee[51]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1075), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[16]), .QN(n1989) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1074), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[17]), .QN(n1990) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1073), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[18]), .QN(n1992) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1072), .CK(clk), .RN(n3510), .Q(
DmP_mant_SFG_SWR[19]), .QN(n1993) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1071), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[20]), .QN(n1994) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1070), .CK(clk), .RN(n3484), .Q(
DmP_mant_SFG_SWR[21]), .QN(n1971) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1059), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[32]), .QN(n1973) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1058), .CK(clk), .RN(n3484), .Q(
DmP_mant_SFG_SWR[33]), .QN(n1974) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1057), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[34]), .QN(n1975) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1056), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[35]), .QN(n1976) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1055), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[36]), .QN(n1977) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1053), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[38]), .QN(n1981) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1048), .CK(clk), .RN(n3521),
.QN(n1856) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1047), .CK(clk), .RN(n3484),
.QN(n1859) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1045), .CK(clk), .RN(n3510),
.QN(n1864) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1044), .CK(clk), .RN(n3484),
.QN(n1866) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1043), .CK(clk), .RN(n3510),
.QN(n1867) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1042), .CK(clk), .RN(n3513),
.QN(n1868) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1041), .CK(clk), .RN(n3510),
.QN(n1870) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1040), .CK(clk), .RN(n3521),
.QN(n1871) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1039), .CK(clk), .RN(n3484),
.QN(n1876) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1038), .CK(clk), .RN(n3513),
.QN(n1877) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1037), .CK(clk), .RN(n3512),
.QN(n1886) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1760), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[55]), .QN(n3465) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1762), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[53]), .QN(n3464) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1135), .CK(clk), .RN(n3475), .Q(
Raw_mant_NRM_SWR[10]), .QN(n3460) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1192), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[26]), .QN(n3454) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1742), .CK(clk), .RN(n3530),
.Q(intDY_EWSW[7]), .QN(n3453) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1719), .CK(clk), .RN(n3514),
.Q(intDY_EWSW[30]), .QN(n3452) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1748), .CK(clk), .RN(n3511),
.Q(intDY_EWSW[1]), .QN(n3449) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1705), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[44]), .QN(n3445) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1713), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[36]), .QN(n3442) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1715), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[34]), .QN(n3441) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1711), .CK(clk), .RN(n3497),
.Q(intDY_EWSW[38]), .QN(n3440) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1710), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[39]), .QN(n3438) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1712), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[37]), .QN(n3437) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1814), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[1]), .QN(n3433) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1688), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[61]), .QN(n3432) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n1685), .CK(clk), .RN(n3517), .Q(
Data_array_SWR[34]), .QN(n3429) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1684), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[33]), .QN(n3428) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n1682), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[32]), .QN(n3427) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1733), .CK(clk), .RN(n3488),
.Q(intDY_EWSW[16]), .QN(n3425) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1701), .CK(clk), .RN(n3479),
.Q(intDY_EWSW[48]), .QN(n3422) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1717), .CK(clk), .RN(n3522),
.Q(intDY_EWSW[32]), .QN(n3421) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1721), .CK(clk), .RN(n3485),
.Q(intDY_EWSW[28]), .QN(n3420) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1745), .CK(clk), .RN(n3488),
.Q(intDY_EWSW[4]), .QN(n3413) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1728), .CK(clk), .RN(n3508),
.Q(intDY_EWSW[21]), .QN(n3411) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1736), .CK(clk), .RN(n3530),
.Q(intDY_EWSW[13]), .QN(n3410) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1739), .CK(clk), .RN(n3517),
.Q(intDY_EWSW[10]), .QN(n3408) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1756), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[59]), .QN(n3404) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1797), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[18]), .QN(n3402) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1789), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[26]), .QN(n3401) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1794), .CK(clk), .RN(n3469),
.Q(intDX_EWSW[21]), .QN(n3400) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1200), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[18]), .QN(n3399) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1199), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[19]), .QN(n3398) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1764), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[51]), .QN(n3397) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1183), .CK(clk), .RN(n3530), .Q(
Raw_mant_NRM_SWR[35]), .QN(n3396) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1758), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[57]), .QN(n3393) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1807), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[8]), .QN(n3392) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1766), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[49]), .QN(n3391) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1798), .CK(clk), .RN(n3469),
.Q(intDX_EWSW[17]), .QN(n3390) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1790), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[25]), .QN(n3389) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1770), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[45]), .QN(n3388) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1629), .CK(clk), .RN(n3479),
.Q(shift_value_SHT2_EWR[3]), .QN(n3386) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1802), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[13]), .QN(n3384) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1786), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[29]), .QN(n3383) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1774), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[41]), .QN(n3382) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1779), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[36]), .QN(n3381) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1793), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[22]), .QN(n3380) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1785), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[30]), .QN(n3379) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1795), .CK(clk), .RN(n3471),
.Q(intDX_EWSW[20]), .QN(n3378) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1787), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[28]), .QN(n3377) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1781), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[34]), .QN(n3375) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1773), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[42]), .QN(n3374) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1782), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[33]), .QN(n3373) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1812), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[3]), .QN(n3372) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1804), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[11]), .QN(n3369) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1801), .CK(clk), .RN(n3471),
.Q(intDX_EWSW[14]), .QN(n3368) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1803), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[12]), .QN(n3367) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1769), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[46]), .QN(n3366) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1628), .CK(clk), .RN(n3501),
.Q(shift_value_SHT2_EWR[4]), .QN(n3363) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1191), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[27]), .QN(n3362) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1761), .CK(clk), .RN(n3472),
.Q(intDX_EWSW[54]), .QN(n3358) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1718), .CK(clk), .RN(n3485),
.Q(intDY_EWSW[31]), .QN(n3348) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1734), .CK(clk), .RN(n3486),
.Q(intDY_EWSW[15]), .QN(n3346) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1714), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[35]), .QN(n3342) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1716), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[33]), .QN(n3341) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1720), .CK(clk), .RN(n3522),
.Q(intDY_EWSW[29]), .QN(n3339) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1744), .CK(clk), .RN(n3519),
.Q(intDY_EWSW[5]), .QN(n3334) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n3471), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n3332) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1146), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[7]), .QN(n3330) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1153), .CK(clk), .RN(n3504), .Q(
Raw_mant_NRM_SWR[2]), .QN(n3328) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1796), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[19]), .QN(n3325) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1788), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[27]), .QN(n3324) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1765), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[50]), .QN(n3322) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1792), .CK(clk), .RN(n3469),
.Q(intDX_EWSW[23]), .QN(n3321) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1784), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[31]), .QN(n3320) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1780), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[35]), .QN(n3319) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1772), .CK(clk), .RN(n3506),
.Q(intDX_EWSW[43]), .QN(n3318) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1142), .CK(clk), .RN(n3505), .Q(
Raw_mant_NRM_SWR[9]), .QN(n3317) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1800), .CK(clk), .RN(n3471),
.Q(intDX_EWSW[15]), .QN(n3316) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1759), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[56]), .QN(n3314) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1131), .CK(clk), .RN(n3476), .Q(
Raw_mant_NRM_SWR[8]), .QN(n3311) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1178), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[40]), .QN(n3364) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1176), .CK(clk), .RN(n3506), .Q(
Raw_mant_NRM_SWR[42]), .QN(n3365) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1144), .CK(clk), .RN(n3505), .Q(
Raw_mant_NRM_SWR[4]), .QN(n3323) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1687), .CK(clk), .RN(n3522),
.Q(intDY_EWSW[62]), .QN(n3448) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1704), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[45]), .QN(n3439) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1726), .CK(clk), .RN(n3508),
.Q(intDY_EWSW[23]), .QN(n3347) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1626), .CK(clk), .RN(n3492),
.Q(shift_value_SHT2_EWR[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1198), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1810), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1171), .CK(clk), .RN(n3473), .Q(
Raw_mant_NRM_SWR[47]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1195), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[23]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1189), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[29]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1194), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1159), .CK(clk), .RN(n3492), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1652), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n1657), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[15]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1152), .CK(clk), .RN(n3474), .Q(
Raw_mant_NRM_SWR[3]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1655), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1777), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[38]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n1660), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[17]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1771), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[44]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1768), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[47]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1179), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[39]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1778), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[37]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1763), .CK(clk), .RN(n3473),
.Q(intDX_EWSW[52]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1775), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[40]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1767), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[48]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1805), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[10]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1186), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[32]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1173), .CK(clk), .RN(n3506), .Q(
Raw_mant_NRM_SWR[45]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1808), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[7]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1799), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[16]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1783), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[32]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1813), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1791), .CK(clk), .RN(n3507),
.Q(intDX_EWSW[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1182), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[36]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1202), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1190), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[28]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1175), .CK(clk), .RN(n3473), .Q(
Raw_mant_NRM_SWR[43]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1203), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1654), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1149), .CK(clk), .RN(n3503), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1140), .CK(clk), .RN(n3506), .Q(
Raw_mant_NRM_SWR[6]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1180), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[38]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1169), .CK(clk), .RN(n3503), .Q(
Raw_mant_NRM_SWR[49]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1201), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n1670), .CK(clk), .RN(n3496), .Q(
Data_array_SWR[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1815), .CK(clk), .RN(n3471),
.Q(intDX_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1753), .CK(clk), .RN(n3520),
.Q(intDX_EWSW[62]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1754), .CK(clk), .RN(n3503),
.Q(intDX_EWSW[61]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1166), .CK(clk), .RN(n3480), .Q(
Raw_mant_NRM_SWR[52]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1824), .CK(clk), .RN(
n3469), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1193), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[25]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1177), .CK(clk), .RN(n3506), .Q(
Raw_mant_NRM_SWR[41]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1197), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n1678), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[28]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n1680), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[30]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n1672), .CK(clk), .RN(n3519), .Q(
Data_array_SWR[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n1671), .CK(clk), .RN(n3525), .Q(
Data_array_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n1673), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[24]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1630), .CK(clk), .RN(n3509),
.Q(shift_value_SHT2_EWR[2]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1188), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[30]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1181), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[37]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1510), .CK(clk), .RN(n3483), .Q(
DMP_SFG[10]) );
DFFSX4TS inst_ShiftRegister_Q_reg_5_ ( .D(n1978), .CK(clk), .SN(n3469), .Q(
n3463), .QN(n3528) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1513), .CK(clk), .RN(n3483), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1537), .CK(clk), .RN(n3524), .Q(
DMP_SFG[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1266), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[32]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1284), .CK(clk), .RN(n3481),
.Q(DmP_mant_SHT1_SW[23]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1302), .CK(clk), .RN(n3494),
.Q(DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1310), .CK(clk), .RN(n3494),
.Q(DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1260), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[35]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1270), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[30]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1274), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[28]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1278), .CK(clk), .RN(n3518),
.Q(DmP_mant_SHT1_SW[26]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1296), .CK(clk), .RN(n3495),
.Q(DmP_mant_SHT1_SW[17]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1752), .CK(clk), .RN(n3520),
.Q(intDX_EWSW[63]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1507), .CK(clk), .RN(n3483), .Q(
DMP_SFG[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1519), .CK(clk), .RN(n3493), .Q(
DMP_SFG[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1525), .CK(clk), .RN(n3504), .Q(
DMP_SFG[5]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1723), .CK(clk), .RN(n3514),
.Q(intDY_EWSW[26]), .QN(n3419) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1147), .CK(clk), .RN(n3503), .Q(
DmP_mant_SFG_SWR[5]) );
DFFSX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1873), .CK(clk), .SN(n3499), .Q(
n3467), .QN(n3526) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1290), .CK(clk), .RN(n3495),
.Q(DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1254), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[38]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1264), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[33]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1268), .CK(clk), .RN(n3496),
.Q(DmP_mant_SHT1_SW[31]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1276), .CK(clk), .RN(n3499),
.Q(DmP_mant_SHT1_SW[27]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1286), .CK(clk), .RN(n3474),
.Q(DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1294), .CK(clk), .RN(n3495),
.Q(DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1308), .CK(clk), .RN(n3494),
.Q(DmP_mant_SHT1_SW[11]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1516), .CK(clk), .RN(n3515), .Q(
DMP_SFG[8]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1227), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[52]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1298), .CK(clk), .RN(n3495),
.Q(DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1262), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[34]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1280), .CK(clk), .RN(n3518),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1304), .CK(clk), .RN(n3494),
.Q(DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1312), .CK(clk), .RN(n3517), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1318), .CK(clk), .RN(n3484), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1324), .CK(clk), .RN(n3517), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1638), .CK(clk), .RN(n3494), .Q(
Data_array_SWR[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1326), .CK(clk), .RN(n3519), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1314), .CK(clk), .RN(n3521), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1635), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1636), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1637), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[6]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1551), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[57]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1328), .CK(clk), .RN(n3490), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1060), .CK(clk), .RN(n3510), .Q(
DmP_mant_SFG_SWR[31]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1061), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[30]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1062), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[29]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1063), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[28]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1064), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1065), .CK(clk), .RN(n3484), .Q(
DmP_mant_SFG_SWR[26]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1066), .CK(clk), .RN(n3510), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1067), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[24]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1068), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1540), .CK(clk), .RN(n3479), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1132), .CK(clk), .RN(n3476), .Q(
DmP_mant_SFG_SWR[8]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1139), .CK(clk), .RN(n3506), .Q(
DmP_mant_SFG_SWR[9]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1143), .CK(clk), .RN(n3473), .Q(
DmP_mant_SFG_SWR[7]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1145), .CK(clk), .RN(n3506), .Q(
DmP_mant_SFG_SWR[4]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1150), .CK(clk), .RN(n3474), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1154), .CK(clk), .RN(n3515), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1046), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[45]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1157), .CK(clk), .RN(n3493), .Q(
DmP_mant_SFG_SWR[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1160), .CK(clk), .RN(n3504), .Q(
DmP_mant_SFG_SWR[1]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n1658), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1167), .CK(clk), .RN(n3518), .Q(
Raw_mant_NRM_SWR[51]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1387), .CK(clk), .RN(n3520), .Q(
DMP_SFG[51]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1390), .CK(clk), .RN(n3520), .Q(
DMP_SFG[50]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1393), .CK(clk), .RN(n3520), .Q(
DMP_SFG[49]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1396), .CK(clk), .RN(n3491), .Q(
DMP_SFG[48]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1399), .CK(clk), .RN(n3523), .Q(
DMP_SFG[47]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1402), .CK(clk), .RN(n3491), .Q(
DMP_SFG[46]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1405), .CK(clk), .RN(n3523), .Q(
DMP_SFG[45]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1408), .CK(clk), .RN(n3490), .Q(
DMP_SFG[44]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1411), .CK(clk), .RN(n3490), .Q(
DMP_SFG[43]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1414), .CK(clk), .RN(n3490), .Q(
DMP_SFG[42]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1417), .CK(clk), .RN(n3490), .Q(
DMP_SFG[41]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1420), .CK(clk), .RN(n3489), .Q(
DMP_SFG[40]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1423), .CK(clk), .RN(n3489), .Q(
DMP_SFG[39]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1468), .CK(clk), .RN(n3486), .Q(
DMP_SFG[24]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1471), .CK(clk), .RN(n3485), .Q(
DMP_SFG[23]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1474), .CK(clk), .RN(n3522), .Q(
DMP_SFG[22]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1477), .CK(clk), .RN(n3486), .Q(
DMP_SFG[21]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1480), .CK(clk), .RN(n3489), .Q(
DMP_SFG[20]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1483), .CK(clk), .RN(n3490), .Q(
DMP_SFG[19]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1486), .CK(clk), .RN(n3523), .Q(
DMP_SFG[18]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1489), .CK(clk), .RN(n3484), .Q(
DMP_SFG[17]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1492), .CK(clk), .RN(n3511), .Q(
DMP_SFG[16]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1495), .CK(clk), .RN(n3521), .Q(
DMP_SFG[15]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1498), .CK(clk), .RN(n3484), .Q(
DMP_SFG[14]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1501), .CK(clk), .RN(n3510), .Q(
DMP_SFG[13]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1504), .CK(clk), .RN(n3483), .Q(
DMP_SFG[12]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1632), .CK(clk), .RN(n3491), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1633), .CK(clk), .RN(n3525), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1631), .CK(clk), .RN(n3485), .Q(
Data_array_SWR[0]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1184), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[34]), .QN(n1887) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1731), .CK(clk), .RN(n3491),
.Q(intDY_EWSW[18]), .QN(n3416) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1730), .CK(clk), .RN(n3530),
.Q(intDY_EWSW[19]), .QN(n3336) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1170), .CK(clk), .RN(n3474), .Q(
Raw_mant_NRM_SWR[48]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1811), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[4]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1776), .CK(clk), .RN(n3474),
.Q(intDX_EWSW[39]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1806), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[9]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1187), .CK(clk), .RN(n3502), .Q(
Raw_mant_NRM_SWR[31]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1204), .CK(clk), .RN(n3500), .Q(
Raw_mant_NRM_SWR[14]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1648), .CK(clk), .RN(n3477), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1647), .CK(clk), .RN(n3523), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1650), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[10]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1165), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[53]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1809), .CK(clk), .RN(n3470),
.Q(intDX_EWSW[6]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1196), .CK(clk), .RN(n3501), .Q(
Raw_mant_NRM_SWR[22]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n1675), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[26]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n1677), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[27]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n1674), .CK(clk), .RN(n3488), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n1681), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[31]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n1679), .CK(clk), .RN(n3479), .Q(
Data_array_SWR[29]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1164), .CK(clk), .RN(n3492), .Q(
Raw_mant_NRM_SWR[54]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n1174), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[44]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1248), .CK(clk), .RN(n3498),
.Q(DmP_mant_SHT1_SW[41]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1244), .CK(clk), .RN(n3498),
.Q(DmP_mant_SHT1_SW[43]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1240), .CK(clk), .RN(n3498),
.Q(DmP_mant_SHT1_SW[45]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1232), .CK(clk), .RN(n3519),
.Q(DmP_mant_SHT1_SW[49]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1236), .CK(clk), .RN(n3520),
.Q(DmP_mant_SHT1_SW[47]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1256), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[37]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1252), .CK(clk), .RN(n3497),
.Q(DmP_mant_SHT1_SW[39]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1531), .CK(clk), .RN(n3481), .Q(
DMP_SFG[3]), .QN(n3461) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1228), .CK(clk), .RN(n3487),
.Q(DmP_mant_SHT1_SW[51]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1230), .CK(clk), .RN(n3516),
.Q(DmP_mant_SHT1_SW[50]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1136), .CK(clk), .RN(n3475), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1130), .CK(clk), .RN(n3498), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1122), .CK(clk), .RN(n3506), .Q(
DmP_mant_SFG_SWR[12]), .QN(n1986) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1741), .CK(clk), .RN(n3530),
.Q(intDY_EWSW[8]), .QN(n3414) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1377), .CK(clk), .RN(n3514), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1372), .CK(clk), .RN(n3493), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1367), .CK(clk), .RN(n3504), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1362), .CK(clk), .RN(n3515), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1357), .CK(clk), .RN(n3482), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1465), .CK(clk), .RN(n3522), .Q(
DMP_SFG[25]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1462), .CK(clk), .RN(n3522), .Q(
DMP_SFG[26]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1459), .CK(clk), .RN(n3522), .Q(
DMP_SFG[27]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1456), .CK(clk), .RN(n3522), .Q(
DMP_SFG[28]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1453), .CK(clk), .RN(n3487), .Q(
DMP_SFG[29]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1450), .CK(clk), .RN(n3487), .Q(
DMP_SFG[30]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1447), .CK(clk), .RN(n3487), .Q(
DMP_SFG[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1444), .CK(clk), .RN(n3487), .Q(
DMP_SFG[32]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1441), .CK(clk), .RN(n3487), .Q(
DMP_SFG[33]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1438), .CK(clk), .RN(n3487), .Q(
DMP_SFG[34]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1435), .CK(clk), .RN(n3487), .Q(
DMP_SFG[35]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1432), .CK(clk), .RN(n3487), .Q(
DMP_SFG[36]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1429), .CK(clk), .RN(n3489), .Q(
DMP_SFG[37]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1426), .CK(clk), .RN(n3489), .Q(
DMP_SFG[38]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1222), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[57]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1686), .CK(clk), .RN(n3525),
.Q(intDY_EWSW[63]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1077), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[14]), .QN(n1987) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1051), .CK(clk), .RN(n3512), .Q(
DmP_mant_SFG_SWR[40]), .QN(n1983) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1050), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[41]), .QN(n1984) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1076), .CK(clk), .RN(n3484), .Q(
DmP_mant_SFG_SWR[15]), .QN(n1988) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1069), .CK(clk), .RN(n3511), .Q(
DmP_mant_SFG_SWR[22]), .QN(n1972) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1054), .CK(clk), .RN(n3510), .Q(
DmP_mant_SFG_SWR[37]), .QN(n1979) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1052), .CK(clk), .RN(n3513), .Q(
DmP_mant_SFG_SWR[39]), .QN(n1982) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1049), .CK(clk), .RN(n3521), .Q(
DmP_mant_SFG_SWR[42]), .QN(n1985) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1158), .CK(clk), .RN(n3508),
.Q(LZD_output_NRM2_EW[0]), .QN(n1995) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1172), .CK(clk), .RN(n3505), .Q(
Raw_mant_NRM_SWR[46]), .QN(n3376) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1332), .CK(clk), .RN(n3482),
.Q(DMP_exp_NRM2_EW[10]), .QN(n3459) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1337), .CK(clk), .RN(n3492), .Q(
DMP_exp_NRM2_EW[9]), .QN(n3435) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1342), .CK(clk), .RN(n3480), .Q(
DMP_exp_NRM2_EW[8]), .QN(n3436) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1352), .CK(clk), .RN(n3493), .Q(
DMP_exp_NRM2_EW[6]), .QN(n3405) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1382), .CK(clk), .RN(n3530), .Q(
DMP_exp_NRM2_EW[0]), .QN(n3370) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1156), .CK(clk), .RN(n3515), .Q(
Raw_mant_NRM_SWR[0]), .QN(n3329) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1138), .CK(clk), .RN(n3525), .Q(
Raw_mant_NRM_SWR[11]), .QN(n3308) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1129), .CK(clk), .RN(n3476), .Q(
Raw_mant_NRM_SWR[12]), .QN(n3327) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1162), .CK(clk), .RN(n3482), .Q(
Raw_mant_NRM_SWR[13]), .QN(n3315) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1823), .CK(clk), .RN(
n3507), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n3431) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1556), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[52]), .QN(n3458) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1755), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[60]), .QN(n3385) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1757), .CK(clk), .RN(n3505),
.Q(intDX_EWSW[58]), .QN(n3326) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1691), .CK(clk), .RN(n3499),
.Q(intDY_EWSW[58]), .QN(n3424) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1692), .CK(clk), .RN(n3501),
.Q(intDY_EWSW[57]), .QN(n3409) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1709), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[40]), .QN(n3443) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1694), .CK(clk), .RN(n3479),
.Q(intDY_EWSW[55]), .QN(n3309) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1696), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[53]), .QN(n3313) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1693), .CK(clk), .RN(n3497),
.Q(intDY_EWSW[56]), .QN(n3310) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1699), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[50]), .QN(n3447) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1689), .CK(clk), .RN(n3498),
.Q(intDY_EWSW[60]), .QN(n3423) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1690), .CK(clk), .RN(n3524),
.Q(intDY_EWSW[59]), .QN(n3340) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1698), .CK(clk), .RN(n3503),
.Q(intDY_EWSW[51]), .QN(n3350) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1702), .CK(clk), .RN(n3476),
.Q(intDY_EWSW[47]), .QN(n3349) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1695), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[54]), .QN(n3312) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1700), .CK(clk), .RN(n3498),
.Q(intDY_EWSW[49]), .QN(n3430) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1707), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[42]), .QN(n3444) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1708), .CK(clk), .RN(n3492),
.Q(intDY_EWSW[41]), .QN(n3343) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1743), .CK(clk), .RN(n3487),
.Q(intDY_EWSW[6]), .QN(n3352) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1746), .CK(clk), .RN(n3488),
.Q(intDY_EWSW[3]), .QN(n3331) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1747), .CK(clk), .RN(n3520),
.Q(intDY_EWSW[2]), .QN(n3412) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1749), .CK(clk), .RN(n3520),
.Q(intDY_EWSW[0]), .QN(n3333) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1697), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[52]), .QN(n3434) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1703), .CK(clk), .RN(n3505),
.Q(intDY_EWSW[46]), .QN(n3446) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1706), .CK(clk), .RN(n3475),
.Q(intDY_EWSW[43]), .QN(n3344) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1552), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[56]), .QN(n3359) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1553), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[55]), .QN(n3354) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1554), .CK(clk), .RN(n3481), .Q(
DMP_EXP_EWSW[54]), .QN(n3355) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1555), .CK(clk), .RN(n3524), .Q(
DMP_EXP_EWSW[53]), .QN(n3351) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1225), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[54]), .QN(n3353) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1223), .CK(clk), .RN(n3500), .Q(
DmP_EXP_EWSW[56]), .QN(n3357) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1224), .CK(clk), .RN(n3530), .Q(
DmP_EXP_EWSW[55]), .QN(n3360) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1226), .CK(clk), .RN(n3499), .Q(
DmP_EXP_EWSW[53]), .QN(n3356) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1722), .CK(clk), .RN(n3525),
.Q(intDY_EWSW[27]), .QN(n3338) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1724), .CK(clk), .RN(n3517),
.Q(intDY_EWSW[25]), .QN(n3337) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1725), .CK(clk), .RN(n3514),
.Q(intDY_EWSW[24]), .QN(n3418) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1727), .CK(clk), .RN(n3500),
.Q(intDY_EWSW[22]), .QN(n3451) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1729), .CK(clk), .RN(n3489),
.Q(intDY_EWSW[20]), .QN(n3417) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1732), .CK(clk), .RN(n3523),
.Q(intDY_EWSW[17]), .QN(n3335) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1735), .CK(clk), .RN(n3491),
.Q(intDY_EWSW[14]), .QN(n3450) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1737), .CK(clk), .RN(n3484),
.Q(intDY_EWSW[12]), .QN(n3415) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1738), .CK(clk), .RN(n3523),
.Q(intDY_EWSW[11]), .QN(n3345) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1740), .CK(clk), .RN(n3510),
.Q(intDY_EWSW[9]), .QN(n3407) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1656), .CK(clk), .RN(n3478), .Q(
Data_array_SWR[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1247), .CK(clk), .RN(n3498), .Q(
DmP_EXP_EWSW[42]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1163), .CK(clk), .RN(n3477), .Q(
DmP_mant_SFG_SWR[13]), .QN(n1980) );
ADDFX1TS DP_OP_15J75_123_4372_U11 ( .A(n3371), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J75_123_4372_n11), .CO(DP_OP_15J75_123_4372_n10), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J75_123_4372_U10 ( .A(n3395), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J75_123_4372_n10), .CO(DP_OP_15J75_123_4372_n9), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J75_123_4372_U9 ( .A(n3394), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J75_123_4372_n9), .CO(DP_OP_15J75_123_4372_n8), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J75_123_4372_U8 ( .A(n3403), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J75_123_4372_n8), .CO(DP_OP_15J75_123_4372_n7), .S(
exp_rslt_NRM2_EW1[4]) );
ADDFX1TS DP_OP_15J75_123_4372_U7 ( .A(n3406), .B(DMP_exp_NRM2_EW[5]), .CI(
DP_OP_15J75_123_4372_n7), .CO(DP_OP_15J75_123_4372_n6), .S(
exp_rslt_NRM2_EW1[5]) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1347), .CK(clk), .RN(n3518), .Q(
DMP_exp_NRM2_EW[7]), .QN(n3426) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1168), .CK(clk), .RN(n3472), .Q(
Raw_mant_NRM_SWR[50]), .QN(n3387) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n1817), .CK(clk), .RN(n3469), .Q(
Shift_reg_FLAGS_7[1]), .QN(n1969) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1750), .CK(clk), .RN(n3521),
.Q(left_right_SHT2), .QN(n3361) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n1818), .CK(clk), .RN(n3469), .Q(
n1825), .QN(n3527) );
DFFSX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n1991), .CK(clk), .SN(n3471), .Q(
n3462), .QN(busy) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n1816), .CK(clk), .RN(n3507), .Q(
Shift_reg_FLAGS_7[0]), .QN(n1996) );
AOI222X1TS U1859 ( .A0(n2157), .A1(n3239), .B0(n3140), .B1(n3223), .C0(n3141), .C1(n3222), .Y(n3284) );
CMPR32X2TS U1860 ( .A(DMP_SFG[8]), .B(n3109), .C(n3108), .CO(n3101), .S(
n3110) );
CMPR32X2TS U1861 ( .A(n2981), .B(DMP_SFG[51]), .C(n2980), .CO(n2982), .S(
n2979) );
AOI222X1TS U1862 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n2673), .B0(n2707), .B1(
n1922), .C0(n2644), .C1(DmP_mant_SHT1_SW[11]), .Y(n2578) );
AOI222X1TS U1863 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n2673), .B0(n2707), .B1(
DmP_mant_SHT1_SW[13]), .C0(n2644), .C1(n1922), .Y(n2713) );
CMPR32X2TS U1864 ( .A(n2978), .B(DMP_SFG[50]), .C(n2977), .CO(n2980), .S(
n2976) );
CMPR32X2TS U1865 ( .A(n2975), .B(DMP_SFG[49]), .C(n2974), .CO(n2977), .S(
n2973) );
CMPR32X2TS U1866 ( .A(n2972), .B(DMP_SFG[48]), .C(n2971), .CO(n2974), .S(
n2001) );
CMPR32X2TS U1867 ( .A(n2969), .B(DMP_SFG[47]), .C(n2968), .CO(n2971), .S(
n2970) );
CMPR32X2TS U1868 ( .A(n2966), .B(DMP_SFG[46]), .C(n2965), .CO(n2968), .S(
n2967) );
CMPR32X2TS U1869 ( .A(n2963), .B(DMP_SFG[45]), .C(n2962), .CO(n2965), .S(
n2964) );
CMPR32X2TS U1870 ( .A(n2003), .B(DMP_SFG[44]), .C(n2002), .CO(n2962), .S(
n2004) );
CMPR32X2TS U1871 ( .A(n2960), .B(DMP_SFG[43]), .C(n2959), .CO(n2002), .S(
n2961) );
CMPR32X2TS U1872 ( .A(n2957), .B(DMP_SFG[42]), .C(n2956), .CO(n2959), .S(
n2958) );
CMPR32X2TS U1873 ( .A(n2954), .B(DMP_SFG[41]), .C(n2953), .CO(n2956), .S(
n2955) );
CMPR32X2TS U1874 ( .A(n2099), .B(DMP_SFG[17]), .C(n2098), .CO(n2898), .S(
n2100) );
CMPR32X2TS U1875 ( .A(n2096), .B(DMP_SFG[16]), .C(n2095), .CO(n2098), .S(
n2097) );
NOR2BX1TS U1876 ( .AN(n2762), .B(Raw_mant_NRM_SWR[34]), .Y(n2066) );
NOR2X1TS U1877 ( .A(n1857), .B(Raw_mant_NRM_SWR[35]), .Y(n2762) );
INVX4TS U1878 ( .A(n2554), .Y(n2570) );
OAI211XLTS U1879 ( .A0(n2596), .A1(n2570), .B0(n2595), .C0(n2594), .Y(n1656)
);
OAI211XLTS U1880 ( .A0(n2689), .A1(n2716), .B0(n2688), .C0(n2687), .Y(n1650)
);
OAI211XLTS U1881 ( .A0(n2629), .A1(n2716), .B0(n2564), .C0(n2563), .Y(n1637)
);
OAI211XLTS U1882 ( .A0(n2604), .A1(n2690), .B0(n2603), .C0(n2602), .Y(n1673)
);
OAI211XLTS U1883 ( .A0(n2682), .A1(n2716), .B0(n2660), .C0(n2659), .Y(n1670)
);
OAI211XLTS U1884 ( .A0(n2638), .A1(n2690), .B0(n2637), .C0(n2636), .Y(n1660)
);
OAI211XLTS U1885 ( .A0(n2725), .A1(n2670), .B0(n2552), .C0(n2551), .Y(n1682)
);
OAI211XLTS U1886 ( .A0(n2613), .A1(n2670), .B0(n2612), .C0(n2611), .Y(n1646)
);
OAI211XLTS U1887 ( .A0(n2617), .A1(n2570), .B0(n2598), .C0(n2597), .Y(n1665)
);
AOI2BB2XLTS U1888 ( .B0(Raw_mant_NRM_SWR[48]), .B1(n1826), .A0N(n2639),
.A1N(n2724), .Y(n2640) );
OAI211X1TS U1889 ( .A0(n2639), .A1(n2670), .B0(n2543), .C0(n2542), .Y(n1638)
);
AO22X1TS U1890 ( .A0(n3090), .A1(n2984), .B0(n3088), .B1(
Raw_mant_NRM_SWR[54]), .Y(n1164) );
INVX4TS U1891 ( .A(n1854), .Y(n1914) );
OR2X2TS U1892 ( .A(n2548), .B(n2777), .Y(n1854) );
NOR3X2TS U1893 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .C(n2058),
.Y(n2084) );
ADDFX1TS U1894 ( .A(n2009), .B(DMP_SFG[40]), .CI(n2008), .CO(n2953), .S(
n2010) );
NOR3X4TS U1895 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[7]), .C(n2055),
.Y(n2728) );
ADDFX1TS U1896 ( .A(n2951), .B(DMP_SFG[39]), .CI(n2950), .CO(n2008), .S(
n2952) );
NOR2X2TS U1897 ( .A(Raw_mant_NRM_SWR[10]), .B(n2027), .Y(n2727) );
ADDFX1TS U1898 ( .A(n2006), .B(DMP_SFG[38]), .CI(n2005), .CO(n2950), .S(
n2007) );
ADDFX1TS U1899 ( .A(n2948), .B(DMP_SFG[37]), .CI(n2947), .CO(n2005), .S(
n2949) );
ADDFX1TS U1900 ( .A(n2945), .B(DMP_SFG[36]), .CI(n2944), .CO(n2947), .S(
n2946) );
ADDFX1TS U1901 ( .A(n2942), .B(DMP_SFG[35]), .CI(n2941), .CO(n2944), .S(
n2943) );
ADDFX1TS U1902 ( .A(n2939), .B(DMP_SFG[34]), .CI(n2938), .CO(n2941), .S(
n2940) );
OAI211XLTS U1903 ( .A0(n1857), .A1(n3396), .B0(n2082), .C0(n2081), .Y(n2083)
);
ADDFX1TS U1904 ( .A(n2184), .B(DMP_SFG[33]), .CI(n2183), .CO(n2938), .S(
n2185) );
NOR2BX2TS U1905 ( .AN(n2053), .B(Raw_mant_NRM_SWR[15]), .Y(n2760) );
ADDFX1TS U1906 ( .A(n2936), .B(DMP_SFG[32]), .CI(n2935), .CO(n2183), .S(
n2937) );
ADDFX1TS U1907 ( .A(n2933), .B(DMP_SFG[31]), .CI(n2932), .CO(n2935), .S(
n2934) );
ADDFX1TS U1908 ( .A(n2930), .B(DMP_SFG[30]), .CI(n2929), .CO(n2932), .S(
n2931) );
INVX1TS U1909 ( .A(n2067), .Y(n2759) );
NAND2XLTS U1910 ( .A(n1857), .B(n1966), .Y(n1963) );
ADDFX1TS U1911 ( .A(n2927), .B(DMP_SFG[29]), .CI(n2926), .CO(n2929), .S(
n2928) );
ADDFX1TS U1912 ( .A(n2924), .B(DMP_SFG[28]), .CI(n2923), .CO(n2926), .S(
n2925) );
ADDFX1TS U1913 ( .A(n2920), .B(DMP_SFG[27]), .CI(n2919), .CO(n2923), .S(
n2922) );
ADDFX1TS U1914 ( .A(n2917), .B(DMP_SFG[26]), .CI(n2916), .CO(n2919), .S(
n2918) );
ADDFX1TS U1915 ( .A(n2133), .B(DMP_SFG[25]), .CI(n2132), .CO(n2916), .S(
n2134) );
ADDFX1TS U1916 ( .A(n2102), .B(DMP_SFG[24]), .CI(n2101), .CO(n2132), .S(
n2103) );
ADDFX1TS U1917 ( .A(n2914), .B(DMP_SFG[23]), .CI(n2913), .CO(n2101), .S(
n2915) );
ADDFX1TS U1918 ( .A(n2911), .B(DMP_SFG[22]), .CI(n2910), .CO(n2913), .S(
n2912) );
ADDFX1TS U1919 ( .A(n2908), .B(DMP_SFG[21]), .CI(n2907), .CO(n2910), .S(
n2909) );
ADDFX1TS U1920 ( .A(n2905), .B(DMP_SFG[20]), .CI(n2904), .CO(n2907), .S(
n2906) );
ADDFX1TS U1921 ( .A(n2902), .B(DMP_SFG[19]), .CI(n2901), .CO(n2904), .S(
n2903) );
ADDFX1TS U1922 ( .A(n2899), .B(DMP_SFG[18]), .CI(n2898), .CO(n2901), .S(
n2900) );
CLKINVX1TS U1923 ( .A(n2047), .Y(n2048) );
BUFX3TS U1924 ( .A(n2336), .Y(n2365) );
ADDFX1TS U1925 ( .A(n2896), .B(DMP_SFG[15]), .CI(n2895), .CO(n2095), .S(
n2897) );
ADDFX1TS U1926 ( .A(n2893), .B(DMP_SFG[14]), .CI(n2892), .CO(n2895), .S(
n2894) );
OAI211X1TS U1927 ( .A0(DMP_SFG[11]), .A1(n1896), .B0(DMP_SFG[10]), .C0(n3133), .Y(n2000) );
CLKINVX6TS U1928 ( .A(n2549), .Y(n2623) );
NOR2X2TS U1929 ( .A(Raw_mant_NRM_SWR[48]), .B(n2011), .Y(n2080) );
INVX3TS U1930 ( .A(n3117), .Y(n2142) );
CLKINVX6TS U1931 ( .A(n3232), .Y(n2127) );
CLKINVX6TS U1932 ( .A(n2128), .Y(n2159) );
NAND2X4TS U1933 ( .A(n1913), .B(n1996), .Y(n2852) );
INVX1TS U1934 ( .A(n2732), .Y(n2734) );
CLKBUFX2TS U1935 ( .A(Data_array_SWR[20]), .Y(n1935) );
CLKBUFX2TS U1936 ( .A(Data_array_SWR[18]), .Y(n1934) );
NOR2X6TS U1937 ( .A(shift_value_SHT2_EWR[2]), .B(n3386), .Y(n3080) );
OAI211X1TS U1938 ( .A0(n2709), .A1(n2724), .B0(n2676), .C0(n2675), .Y(n1676)
);
OAI211X1TS U1939 ( .A0(n2691), .A1(n2570), .B0(n2681), .C0(n2680), .Y(n1666)
);
OAI211X1TS U1940 ( .A0(n2608), .A1(n2690), .B0(n2600), .C0(n2599), .Y(n1671)
);
OAI211X1TS U1941 ( .A0(n2706), .A1(n2716), .B0(n2705), .C0(n2704), .Y(n1654)
);
OAI211X1TS U1942 ( .A0(n2698), .A1(n2716), .B0(n2697), .C0(n2696), .Y(n1641)
);
OAI211X1TS U1943 ( .A0(n2664), .A1(n2570), .B0(n2654), .C0(n2653), .Y(n1659)
);
OAI211X1TS U1944 ( .A0(n2634), .A1(n2690), .B0(n2633), .C0(n2632), .Y(n1681)
);
OAI211X1TS U1945 ( .A0(n2716), .A1(n2652), .B0(n2651), .C0(n2650), .Y(n1683)
);
OAI211X1TS U1946 ( .A0(n2702), .A1(n2570), .B0(n2701), .C0(n2700), .Y(n1663)
);
OAI211X1TS U1947 ( .A0(n2647), .A1(n2690), .B0(n2646), .C0(n2645), .Y(n1664)
);
OAI211X1TS U1948 ( .A0(n2607), .A1(n2670), .B0(n2606), .C0(n2605), .Y(n1651)
);
OAI211X1TS U1949 ( .A0(n2717), .A1(n2716), .B0(n2715), .C0(n2714), .Y(n1645)
);
OAI211X1TS U1950 ( .A0(n2586), .A1(n2690), .B0(n2585), .C0(n2584), .Y(n1677)
);
OAI211X1TS U1951 ( .A0(n2635), .A1(n2690), .B0(n2619), .C0(n2618), .Y(n1662)
);
OAI211X1TS U1952 ( .A0(n2699), .A1(n2716), .B0(n2666), .C0(n2665), .Y(n1661)
);
OAI211X1TS U1953 ( .A0(n2720), .A1(n2570), .B0(n2711), .C0(n2710), .Y(n1678)
);
OAI211X1TS U1954 ( .A0(n2686), .A1(n2716), .B0(n2663), .C0(n2662), .Y(n1648)
);
OAI211X1TS U1955 ( .A0(n2703), .A1(n2716), .B0(n2669), .C0(n2668), .Y(n1652)
);
OAI211X1TS U1956 ( .A0(n2685), .A1(n2716), .B0(n2684), .C0(n2683), .Y(n1672)
);
OAI211X1TS U1957 ( .A0(n2674), .A1(n2716), .B0(n2672), .C0(n2671), .Y(n1674)
);
OAI211X1TS U1958 ( .A0(n2626), .A1(n2670), .B0(n2625), .C0(n2624), .Y(n1655)
);
OAI211X1TS U1959 ( .A0(n2622), .A1(n2670), .B0(n2621), .C0(n2620), .Y(n1653)
);
OAI211X1TS U1960 ( .A0(n2694), .A1(n2724), .B0(n2693), .C0(n2692), .Y(n1668)
);
OAI211X1TS U1961 ( .A0(n2614), .A1(n2690), .B0(n2610), .C0(n2609), .Y(n1669)
);
OAI211X1TS U1962 ( .A0(n2658), .A1(n2570), .B0(n2657), .C0(n2656), .Y(n1657)
);
OAI211X1TS U1963 ( .A0(n2583), .A1(n2690), .B0(n2580), .C0(n2579), .Y(n1679)
);
OAI211X1TS U1964 ( .A0(n2601), .A1(n2690), .B0(n2572), .C0(n2571), .Y(n1675)
);
OAI211X1TS U1965 ( .A0(n2578), .A1(n2670), .B0(n2577), .C0(n2576), .Y(n1644)
);
OAI211X1TS U1966 ( .A0(n2589), .A1(n2716), .B0(n2566), .C0(n2565), .Y(n1647)
);
OAI211X1TS U1967 ( .A0(n2713), .A1(n2716), .B0(n2556), .C0(n2555), .Y(n1643)
);
BUFX4TS U1968 ( .A(n2570), .Y(n2724) );
OAI211X1TS U1969 ( .A0(n2642), .A1(n2716), .B0(n2561), .C0(n2560), .Y(n1634)
);
OAI211X1TS U1970 ( .A0(n2593), .A1(n2670), .B0(n2547), .C0(n2546), .Y(n1635)
);
OAI211X1TS U1971 ( .A0(n2539), .A1(n2670), .B0(n2538), .C0(n2537), .Y(n1632)
);
OAI211X1TS U1972 ( .A0(n2575), .A1(n2716), .B0(n2569), .C0(n2568), .Y(n1640)
);
INVX4TS U1973 ( .A(n1854), .Y(n1826) );
AND2X4TS U1974 ( .A(n2548), .B(n2667), .Y(n2559) );
OAI211X2TS U1975 ( .A0(Raw_mant_NRM_SWR[29]), .A1(n2766), .B0(n2062), .C0(
n2061), .Y(n2548) );
AOI222X1TS U1976 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2673), .B0(n2623), .B1(
DmP_mant_SHT1_SW[25]), .C0(n2644), .C1(n1921), .Y(n2655) );
AOI222X1TS U1977 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2673), .B0(n2623), .B1(
DmP_mant_SHT1_SW[16]), .C0(n2644), .C1(n1920), .Y(n2661) );
AOI222X1TS U1978 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2631), .B0(n2707), .B1(
DmP_mant_SHT1_SW[9]), .C0(n2630), .C1(DmP_mant_SHT1_SW[8]), .Y(n2695)
);
AOI222X1TS U1979 ( .A0(Raw_mant_NRM_SWR[39]), .A1(n2673), .B0(n2677), .B1(
DmP_mant_SHT1_SW[14]), .C0(n2644), .C1(DmP_mant_SHT1_SW[13]), .Y(n2613) );
AOI222X1TS U1980 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n2631), .B0(n2707), .B1(
DmP_mant_SHT1_SW[3]), .C0(n2630), .C1(DmP_mant_SHT1_SW[2]), .Y(n2593)
);
AOI222X1TS U1981 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n2678), .B0(
Raw_mant_NRM_SWR[16]), .B1(n2667), .C0(n2623), .C1(n1918), .Y(n2691)
);
AOI222X1TS U1982 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[39]), .C0(n2644), .C1(DmP_mant_SHT1_SW[38]), .Y(n2608) );
AOI222X1TS U1983 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n2678), .B0(
Raw_mant_NRM_SWR[14]), .B1(n2087), .C0(n2623), .C1(
DmP_mant_SHT1_SW[38]), .Y(n2694) );
AOI222X1TS U1984 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2673), .B0(
Raw_mant_NRM_SWR[6]), .B1(n2087), .C0(n2707), .C1(n1917), .Y(n2709) );
AOI222X1TS U1985 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[31]), .B1(n2708), .C0(n2623), .C1(
DmP_mant_SHT1_SW[22]), .Y(n2703) );
AOI222X1TS U1986 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2667), .B0(n1950), .B1(
n2708), .C0(n2623), .C1(DmP_mant_SHT1_SW[20]), .Y(n2689) );
AOI222X1TS U1987 ( .A0(Raw_mant_NRM_SWR[46]), .A1(n2631), .B0(n2677), .B1(
n1924), .C0(n2630), .C1(DmP_mant_SHT1_SW[6]), .Y(n2629) );
AOI222X1TS U1988 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2678), .B0(n2707), .B1(
DmP_mant_SHT1_SW[30]), .C0(n2630), .C1(n1919), .Y(n2635) );
AOI222X1TS U1989 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[32]), .C0(n2630), .C1(DmP_mant_SHT1_SW[31]), .Y(n2647) );
AOI222X1TS U1990 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n2678), .B0(n2707), .B1(
DmP_mant_SHT1_SW[34]), .C0(n2630), .C1(DmP_mant_SHT1_SW[33]), .Y(n2679) );
AOI222X1TS U1991 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2631), .B0(n2707), .B1(
DmP_mant_SHT1_SW[6]), .C0(n2644), .C1(n1923), .Y(n2639) );
AOI222X1TS U1992 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n2678), .B0(
Raw_mant_NRM_SWR[23]), .B1(n2667), .C0(n2707), .C1(n1919), .Y(n2664)
);
AOI222X1TS U1993 ( .A0(Raw_mant_NRM_SWR[35]), .A1(n2673), .B0(
Raw_mant_NRM_SWR[34]), .B1(n2087), .C0(n2707), .C1(
DmP_mant_SHT1_SW[18]), .Y(n2686) );
AOI222X1TS U1994 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n2631), .B0(n2677), .B1(
n1925), .C0(n2557), .C1(DmP_mant_SHT1_SW[3]), .Y(n2642) );
NAND3X1TS U1995 ( .A(n2084), .B(Raw_mant_NRM_SWR[1]), .C(n3328), .Y(n2736)
);
INVX1TS U1996 ( .A(n2728), .Y(n2729) );
AO21X1TS U1997 ( .A0(n3311), .A1(n3330), .B0(n2055), .Y(n2056) );
NAND3X1TS U1998 ( .A(n2020), .B(n2041), .C(n2746), .Y(n2021) );
NAND2X2TS U1999 ( .A(n2727), .B(n3317), .Y(n2055) );
NAND2X2TS U2000 ( .A(n2726), .B(n3308), .Y(n2027) );
NOR2X2TS U2001 ( .A(Raw_mant_NRM_SWR[12]), .B(n2771), .Y(n2726) );
OAI211X1TS U2002 ( .A0(n3362), .A1(n2072), .B0(n2071), .C0(n2737), .Y(n2073)
);
NAND2X2TS U2003 ( .A(n2070), .B(n3315), .Y(n2771) );
INVX1TS U2004 ( .A(n2043), .Y(n2060) );
NOR2X2TS U2005 ( .A(Raw_mant_NRM_SWR[16]), .B(n2043), .Y(n2053) );
NAND2X2TS U2006 ( .A(n2732), .B(n2733), .Y(n2043) );
CLKAND2X2TS U2007 ( .A(n1964), .B(n1965), .Y(n1966) );
NAND2BX2TS U2008 ( .AN(Raw_mant_NRM_SWR[21]), .B(n2014), .Y(n2067) );
NOR3BX2TS U2009 ( .AN(n2024), .B(Raw_mant_NRM_SWR[23]), .C(
Raw_mant_NRM_SWR[22]), .Y(n2014) );
NAND2XLTS U2010 ( .A(n2024), .B(Raw_mant_NRM_SWR[22]), .Y(n2768) );
NOR2BX2TS U2011 ( .AN(n2046), .B(Raw_mant_NRM_SWR[24]), .Y(n2024) );
NAND2XLTS U2012 ( .A(Raw_mant_NRM_SWR[25]), .B(n2019), .Y(n2746) );
OR2X4TS U2013 ( .A(n2884), .B(n2876), .Y(n2146) );
NOR2X2TS U2014 ( .A(Raw_mant_NRM_SWR[26]), .B(n2026), .Y(n2019) );
INVX1TS U2015 ( .A(n2748), .Y(n2065) );
NAND2BX2TS U2016 ( .AN(Raw_mant_NRM_SWR[30]), .B(n2025), .Y(n2748) );
NOR3X2TS U2017 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .C(
n2064), .Y(n2025) );
INVX1TS U2018 ( .A(n2064), .Y(n2761) );
NAND2BX2TS U2019 ( .AN(n1950), .B(n2066), .Y(n2064) );
BUFX4TS U2020 ( .A(n2384), .Y(n1827) );
OR2X2TS U2021 ( .A(Raw_mant_NRM_SWR[36]), .B(n2047), .Y(n1857) );
NAND2X1TS U2022 ( .A(n2013), .B(n2745), .Y(n2047) );
NAND2X2TS U2023 ( .A(n2873), .B(n2326), .Y(n2336) );
OAI32X4TS U2024 ( .A0(n3128), .A1(n3127), .A2(n3126), .B0(n3232), .B1(n3128),
.Y(n3155) );
ADDFX1TS U2025 ( .A(DMP_SFG[13]), .B(n2890), .CI(n2889), .CO(n2892), .S(
n2891) );
ADDFX1TS U2026 ( .A(DMP_SFG[12]), .B(n2887), .CI(n2886), .CO(n2889), .S(
n2888) );
NOR2X6TS U2027 ( .A(left_right_SHT2), .B(n2127), .Y(n2156) );
INVX4TS U2028 ( .A(n2648), .Y(n2644) );
CLKINVX3TS U2029 ( .A(n3201), .Y(n2168) );
CLKBUFX2TS U2030 ( .A(Data_array_SWR[19]), .Y(n1936) );
INVX6TS U2031 ( .A(rst), .Y(n3530) );
NOR2BX2TS U2032 ( .AN(n2760), .B(Raw_mant_NRM_SWR[14]), .Y(n2070) );
NAND2X2TS U2033 ( .A(n2728), .B(n2731), .Y(n2058) );
AOI2BB2XLTS U2034 ( .B0(n3075), .B1(DmP_mant_SFG_SWR[25]), .A0N(
DmP_mant_SFG_SWR[25]), .A1N(n3076), .Y(n2914) );
AOI2BB2XLTS U2035 ( .B0(n3075), .B1(DmP_mant_SFG_SWR[28]), .A0N(
DmP_mant_SFG_SWR[28]), .A1N(n3076), .Y(n2917) );
NOR3X1TS U2036 ( .A(Raw_mant_NRM_SWR[44]), .B(Raw_mant_NRM_SWR[46]), .C(
Raw_mant_NRM_SWR[45]), .Y(n2023) );
AOI222X1TS U2037 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n2708), .B0(n2707), .B1(
DmP_mant_SHT1_SW[49]), .C0(n2644), .C1(n1916), .Y(n2634) );
AOI222X1TS U2038 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n2708), .B0(n2677), .B1(
DmP_mant_SHT1_SW[47]), .C0(n2644), .C1(n1917), .Y(n2583) );
AOI222X1TS U2039 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2708), .B0(n2707), .B1(
DmP_mant_SHT1_SW[45]), .C0(n2644), .C1(n1928), .Y(n2586) );
AOI2BB2XLTS U2040 ( .B0(n1999), .B1(DmP_mant_SFG_SWR[30]), .A0N(
DmP_mant_SFG_SWR[30]), .A1N(n3075), .Y(n2924) );
AOI222X1TS U2041 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[43]), .C0(n2644), .C1(n1929), .Y(n2601) );
AOI222X1TS U2042 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n2678), .B0(n2707), .B1(
DmP_mant_SHT1_SW[41]), .C0(n2644), .C1(n1930), .Y(n2604) );
AOI222X1TS U2043 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n2708), .B0(
Raw_mant_NRM_SWR[4]), .B1(n2087), .C0(n2677), .C1(n1916), .Y(n2720) );
AOI222X1TS U2044 ( .A0(Raw_mant_NRM_SWR[28]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[29]), .B1(n2708), .C0(n2677), .C1(n1921), .Y(n2706)
);
AOI222X1TS U2045 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[28]), .C0(n2630), .C1(DmP_mant_SHT1_SW[27]), .Y(n2638) );
AOI2BB2XLTS U2046 ( .B0(n1999), .B1(DmP_mant_SFG_SWR[24]), .A0N(
DmP_mant_SFG_SWR[24]), .A1N(n3075), .Y(n2911) );
AOI2BB2XLTS U2047 ( .B0(n1999), .B1(DmP_mant_SFG_SWR[27]), .A0N(
DmP_mant_SFG_SWR[27]), .A1N(n3075), .Y(n2133) );
AOI222X1TS U2048 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n2678), .B0(
Raw_mant_NRM_SWR[2]), .B1(n2667), .C0(DmP_mant_SHT1_SW[50]), .C1(n2707), .Y(n2725) );
AOI222X1TS U2049 ( .A0(Raw_mant_NRM_SWR[41]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[42]), .B1(n2708), .C0(n2677), .C1(
DmP_mant_SHT1_SW[11]), .Y(n2698) );
AOI222X1TS U2050 ( .A0(Raw_mant_NRM_SWR[37]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[38]), .B1(n2708), .C0(n2623), .C1(n1920), .Y(n2717)
);
AOI222X1TS U2051 ( .A0(Raw_mant_NRM_SWR[34]), .A1(n2673), .B0(n2707), .B1(
n1938), .C0(n2630), .C1(DmP_mant_SHT1_SW[18]), .Y(n2607) );
AOI222X1TS U2052 ( .A0(Raw_mant_NRM_SWR[32]), .A1(n2673), .B0(n2677), .B1(
n1937), .C0(n2630), .C1(DmP_mant_SHT1_SW[20]), .Y(n2622) );
AOI222X1TS U2053 ( .A0(Raw_mant_NRM_SWR[30]), .A1(n2673), .B0(n2677), .B1(
DmP_mant_SHT1_SW[23]), .C0(n2630), .C1(DmP_mant_SHT1_SW[22]), .Y(n2626) );
AOI222X1TS U2054 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[26]), .B1(n2708), .C0(n2677), .C1(
DmP_mant_SHT1_SW[27]), .Y(n2658) );
AOI222X1TS U2055 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n2087), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2708), .C0(n2707), .C1(
DmP_mant_SHT1_SW[31]), .Y(n2699) );
AOI222X1TS U2056 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n2087), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2708), .C0(n2677), .C1(
DmP_mant_SHT1_SW[33]), .Y(n2702) );
CLKINVX6TS U2057 ( .A(n2810), .Y(n2719) );
NAND2BXLTS U2058 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n2221) );
NAND2X1TS U2059 ( .A(n2023), .B(n2080), .Y(n2012) );
NAND2BXLTS U2060 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2269) );
AO22XLTS U2061 ( .A0(n3336), .A1(intDX_EWSW[19]), .B0(n3416), .B1(
intDX_EWSW[18]), .Y(n1872) );
NOR2BX2TS U2062 ( .AN(n2075), .B(Raw_mant_NRM_SWR[42]), .Y(n2015) );
NAND2BXLTS U2063 ( .AN(intDY_EWSW[62]), .B(intDX_EWSW[62]), .Y(n2266) );
NAND2BXLTS U2064 ( .AN(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n2264) );
AOI31XLTS U2065 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n2733), .A2(n3399), .B0(
n2083), .Y(n2085) );
AOI211X1TS U2066 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1898), .B0(n3047),
.C0(n3046), .Y(n3244) );
AOI211X1TS U2067 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1899), .B0(n3063),
.C0(n3062), .Y(n3214) );
AO21XLTS U2068 ( .A0(n1957), .A1(n3125), .B0(n3104), .Y(n1833) );
OAI31X1TS U2069 ( .A0(n2765), .A1(n2764), .A2(Raw_mant_NRM_SWR[48]), .B0(
n2763), .Y(n2767) );
NAND4X1TS U2070 ( .A(n2052), .B(n2051), .C(n2050), .D(n2049), .Y(n2756) );
OAI21XLTS U2071 ( .A0(Raw_mant_NRM_SWR[35]), .A1(Raw_mant_NRM_SWR[36]), .B0(
n2048), .Y(n2049) );
AOI2BB2XLTS U2072 ( .B0(n3075), .B1(DmP_mant_SFG_SWR[31]), .A0N(
DmP_mant_SFG_SWR[31]), .A1N(n3076), .Y(n2927) );
AOI222X1TS U2073 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2673), .B0(n2623), .B1(
DmP_mant_SHT1_SW[26]), .C0(n2630), .C1(DmP_mant_SHT1_SW[25]), .Y(n2596) );
AOI2BB2XLTS U2074 ( .B0(n3076), .B1(DmP_mant_SFG_SWR[29]), .A0N(
DmP_mant_SFG_SWR[29]), .A1N(n1999), .Y(n2920) );
AOI2BB2XLTS U2075 ( .B0(n3076), .B1(DmP_mant_SFG_SWR[23]), .A0N(
DmP_mant_SFG_SWR[23]), .A1N(n1999), .Y(n2908) );
AOI222X1TS U2076 ( .A0(n3036), .A1(DMP_SFG[1]), .B0(n3036), .B1(n3035), .C0(
DMP_SFG[1]), .C1(n3035), .Y(n3064) );
BUFX4TS U2077 ( .A(n2793), .Y(n2804) );
AOI2BB2XLTS U2078 ( .B0(n3076), .B1(DmP_mant_SFG_SWR[26]), .A0N(
DmP_mant_SFG_SWR[26]), .A1N(n1999), .Y(n2102) );
OAI211X1TS U2079 ( .A0(n1858), .A1(n3197), .B0(n3196), .C0(n3195), .Y(n3272)
);
OAI211X1TS U2080 ( .A0(n1858), .A1(n3242), .B0(n3193), .C0(n3192), .Y(n3264)
);
OAI211X1TS U2081 ( .A0(n3153), .A1(n3197), .B0(n3152), .C0(n3151), .Y(n3271)
);
OAI211X1TS U2082 ( .A0(n3153), .A1(n3242), .B0(n3147), .C0(n3146), .Y(n3265)
);
OAI211X1TS U2083 ( .A0(n1897), .A1(n3197), .B0(n3144), .C0(n3143), .Y(n3269)
);
OAI211X1TS U2084 ( .A0(n1897), .A1(n3242), .B0(n3139), .C0(n3138), .Y(n3267)
);
AO22XLTS U2085 ( .A0(n2760), .A1(Raw_mant_NRM_SWR[14]), .B0(
Raw_mant_NRM_SWR[20]), .B1(n2759), .Y(n2775) );
NAND4XLTS U2086 ( .A(n2086), .B(n2769), .C(n2031), .D(n2050), .Y(n2032) );
NAND4BXLTS U2087 ( .AN(n2738), .B(n2737), .C(n2736), .D(n2735), .Y(n2739) );
OAI31X1TS U2088 ( .A0(Raw_mant_NRM_SWR[16]), .A1(Raw_mant_NRM_SWR[14]), .A2(
n2734), .B0(n2733), .Y(n2735) );
BUFX4TS U2089 ( .A(n3462), .Y(n2859) );
BUFX6TS U2090 ( .A(n1933), .Y(n2386) );
AOI222X1TS U2091 ( .A0(Raw_mant_NRM_SWR[43]), .A1(n2673), .B0(n2707), .B1(
DmP_mant_SHT1_SW[10]), .C0(n2630), .C1(DmP_mant_SHT1_SW[9]), .Y(n2575)
);
AOI222X1TS U2092 ( .A0(Raw_mant_NRM_SWR[36]), .A1(n2673), .B0(n2623), .B1(
DmP_mant_SHT1_SW[17]), .C0(n2630), .C1(DmP_mant_SHT1_SW[16]), .Y(n2589) );
AOI222X1TS U2093 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[35]), .C0(n2630), .C1(DmP_mant_SHT1_SW[34]), .Y(n2617) );
NAND3XLTS U2094 ( .A(Raw_mant_NRM_SWR[0]), .B(n2777), .C(n2549), .Y(n2652)
);
AO22XLTS U2095 ( .A0(n2808), .A1(Data_Y[63]), .B0(n2807), .B1(intDY_EWSW[63]), .Y(n1686) );
AO22XLTS U2096 ( .A0(n3297), .A1(DMP_SHT2_EWSW[38]), .B0(n2861), .B1(
DMP_SFG[38]), .Y(n1426) );
AO22XLTS U2097 ( .A0(n3292), .A1(DMP_SHT2_EWSW[37]), .B0(n2861), .B1(
DMP_SFG[37]), .Y(n1429) );
AO22XLTS U2098 ( .A0(n2858), .A1(DMP_SHT2_EWSW[36]), .B0(n2857), .B1(
DMP_SFG[36]), .Y(n1432) );
AO22XLTS U2099 ( .A0(n3297), .A1(DMP_SHT2_EWSW[35]), .B0(n2857), .B1(
DMP_SFG[35]), .Y(n1435) );
AO22XLTS U2100 ( .A0(n3292), .A1(DMP_SHT2_EWSW[34]), .B0(n2857), .B1(
DMP_SFG[34]), .Y(n1438) );
AO22XLTS U2101 ( .A0(n2858), .A1(DMP_SHT2_EWSW[33]), .B0(n2857), .B1(
DMP_SFG[33]), .Y(n1441) );
AO22XLTS U2102 ( .A0(n3297), .A1(DMP_SHT2_EWSW[32]), .B0(n2857), .B1(
DMP_SFG[32]), .Y(n1444) );
AO22XLTS U2103 ( .A0(n3292), .A1(DMP_SHT2_EWSW[31]), .B0(n2857), .B1(
DMP_SFG[31]), .Y(n1447) );
AO22XLTS U2104 ( .A0(n2858), .A1(DMP_SHT2_EWSW[30]), .B0(n2857), .B1(
DMP_SFG[30]), .Y(n1450) );
AO22XLTS U2105 ( .A0(n3292), .A1(DMP_SHT2_EWSW[29]), .B0(n2857), .B1(
DMP_SFG[29]), .Y(n1453) );
AO22XLTS U2106 ( .A0(n3297), .A1(DMP_SHT2_EWSW[28]), .B0(n2857), .B1(
DMP_SFG[28]), .Y(n1456) );
AO22XLTS U2107 ( .A0(n2858), .A1(DMP_SHT2_EWSW[27]), .B0(n2857), .B1(
DMP_SFG[27]), .Y(n1459) );
AO22XLTS U2108 ( .A0(n3297), .A1(DMP_SHT2_EWSW[26]), .B0(n2857), .B1(
DMP_SFG[26]), .Y(n1462) );
AO22XLTS U2109 ( .A0(n3292), .A1(DMP_SHT2_EWSW[25]), .B0(n2857), .B1(
DMP_SFG[25]), .Y(n1465) );
AO22XLTS U2110 ( .A0(n3261), .A1(n3154), .B0(n3130), .B1(
DmP_mant_SFG_SWR[11]), .Y(n1130) );
AO22XLTS U2111 ( .A0(n3261), .A1(n3113), .B0(n3130), .B1(
DmP_mant_SFG_SWR[10]), .Y(n1136) );
AO22XLTS U2112 ( .A0(n2880), .A1(DmP_EXP_EWSW[50]), .B0(n2877), .B1(
DmP_mant_SHT1_SW[50]), .Y(n1230) );
AO22XLTS U2113 ( .A0(n2880), .A1(DmP_EXP_EWSW[51]), .B0(n2877), .B1(
DmP_mant_SHT1_SW[51]), .Y(n1228) );
AO22XLTS U2114 ( .A0(n2880), .A1(DmP_EXP_EWSW[39]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[39]), .Y(n1252) );
AO22XLTS U2115 ( .A0(n2880), .A1(DmP_EXP_EWSW[37]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[37]), .Y(n1256) );
AO22XLTS U2116 ( .A0(n2880), .A1(DmP_EXP_EWSW[47]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[47]), .Y(n1236) );
AO22XLTS U2117 ( .A0(n2880), .A1(DmP_EXP_EWSW[49]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[49]), .Y(n1232) );
AO22XLTS U2118 ( .A0(n2880), .A1(DmP_EXP_EWSW[45]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[45]), .Y(n1240) );
AO22XLTS U2119 ( .A0(n2880), .A1(DmP_EXP_EWSW[43]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[43]), .Y(n1244) );
AO22XLTS U2120 ( .A0(n2880), .A1(DmP_EXP_EWSW[41]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[41]), .Y(n1248) );
AO22XLTS U2121 ( .A0(n1825), .A1(n2958), .B0(n3088), .B1(
Raw_mant_NRM_SWR[44]), .Y(n1174) );
AOI2BB2XLTS U2122 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1914), .A0N(n2634), .A1N(
n2570), .Y(n2579) );
AOI2BB2XLTS U2123 ( .B0(Raw_mant_NRM_SWR[3]), .B1(n1914), .A0N(n2649), .A1N(
n2724), .Y(n2632) );
AOI2BB2XLTS U2124 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[43]), .A0N(n2685),
.A1N(n2670), .Y(n2671) );
AOI2BB2XLTS U2125 ( .B0(Raw_mant_NRM_SWR[7]), .B1(n1914), .A0N(n2583), .A1N(
n2724), .Y(n2584) );
AOI2BB2XLTS U2126 ( .B0(Raw_mant_NRM_SWR[9]), .B1(n1914), .A0N(n2586), .A1N(
n2570), .Y(n2571) );
AO22XLTS U2127 ( .A0(n3090), .A1(n2906), .B0(n2921), .B1(
Raw_mant_NRM_SWR[22]), .Y(n1196) );
AO22XLTS U2128 ( .A0(n2805), .A1(Data_X[6]), .B0(n2797), .B1(intDX_EWSW[6]),
.Y(n1809) );
AO22XLTS U2129 ( .A0(n1825), .A1(n2979), .B0(n3088), .B1(
Raw_mant_NRM_SWR[53]), .Y(n1165) );
AOI2BB2XLTS U2130 ( .B0(n2721), .B1(n1938), .A0N(n2686), .A1N(n2719), .Y(
n2687) );
AOI2BB2XLTS U2131 ( .B0(n2718), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2717),
.A1N(n2719), .Y(n2565) );
AOI2BB2XLTS U2132 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[17]), .A0N(n2661),
.A1N(n2719), .Y(n2662) );
AO22XLTS U2133 ( .A0(n1825), .A1(n2928), .B0(n3088), .B1(
Raw_mant_NRM_SWR[31]), .Y(n1187) );
AO22XLTS U2134 ( .A0(n2805), .A1(Data_X[9]), .B0(n2797), .B1(intDX_EWSW[9]),
.Y(n1806) );
AO22XLTS U2135 ( .A0(n2793), .A1(Data_X[39]), .B0(n2795), .B1(intDX_EWSW[39]), .Y(n1776) );
AO22XLTS U2136 ( .A0(n2805), .A1(Data_X[4]), .B0(n2803), .B1(intDX_EWSW[4]),
.Y(n1811) );
AO22XLTS U2137 ( .A0(n3090), .A1(n2967), .B0(n3088), .B1(
Raw_mant_NRM_SWR[48]), .Y(n1170) );
AOI2BB2XLTS U2138 ( .B0(n2718), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2706),
.A1N(n2719), .Y(n2594) );
AO22XLTS U2139 ( .A0(n2858), .A1(DMP_SHT2_EWSW[12]), .B0(n2864), .B1(
DMP_SFG[12]), .Y(n1504) );
AO22XLTS U2140 ( .A0(n3297), .A1(DMP_SHT2_EWSW[13]), .B0(n2864), .B1(
DMP_SFG[13]), .Y(n1501) );
AO22XLTS U2141 ( .A0(n3297), .A1(DMP_SHT2_EWSW[14]), .B0(n2861), .B1(
DMP_SFG[14]), .Y(n1498) );
AO22XLTS U2142 ( .A0(n3292), .A1(DMP_SHT2_EWSW[15]), .B0(n2857), .B1(
DMP_SFG[15]), .Y(n1495) );
AO22XLTS U2143 ( .A0(n3292), .A1(DMP_SHT2_EWSW[16]), .B0(n3307), .B1(
DMP_SFG[16]), .Y(n1492) );
AO22XLTS U2144 ( .A0(n2858), .A1(DMP_SHT2_EWSW[17]), .B0(n3298), .B1(
DMP_SFG[17]), .Y(n1489) );
AO22XLTS U2145 ( .A0(n3297), .A1(DMP_SHT2_EWSW[18]), .B0(n2852), .B1(
DMP_SFG[18]), .Y(n1486) );
AO22XLTS U2146 ( .A0(n3292), .A1(DMP_SHT2_EWSW[19]), .B0(n2852), .B1(
DMP_SFG[19]), .Y(n1483) );
AO22XLTS U2147 ( .A0(n2858), .A1(DMP_SHT2_EWSW[20]), .B0(n2852), .B1(
DMP_SFG[20]), .Y(n1480) );
AO22XLTS U2148 ( .A0(n3297), .A1(DMP_SHT2_EWSW[21]), .B0(n2861), .B1(
DMP_SFG[21]), .Y(n1477) );
AO22XLTS U2149 ( .A0(n3292), .A1(DMP_SHT2_EWSW[22]), .B0(n2857), .B1(
DMP_SFG[22]), .Y(n1474) );
AO22XLTS U2150 ( .A0(n2858), .A1(DMP_SHT2_EWSW[23]), .B0(n3130), .B1(
DMP_SFG[23]), .Y(n1471) );
AO22XLTS U2151 ( .A0(n3297), .A1(DMP_SHT2_EWSW[24]), .B0(n2861), .B1(
DMP_SFG[24]), .Y(n1468) );
AO22XLTS U2152 ( .A0(n3306), .A1(DMP_SHT2_EWSW[39]), .B0(n2861), .B1(
DMP_SFG[39]), .Y(n1423) );
AO22XLTS U2153 ( .A0(n3306), .A1(DMP_SHT2_EWSW[40]), .B0(n2861), .B1(
DMP_SFG[40]), .Y(n1420) );
AO22XLTS U2154 ( .A0(n3306), .A1(DMP_SHT2_EWSW[41]), .B0(n2861), .B1(
DMP_SFG[41]), .Y(n1417) );
AO22XLTS U2155 ( .A0(n3306), .A1(DMP_SHT2_EWSW[42]), .B0(n2861), .B1(
DMP_SFG[42]), .Y(n1414) );
AO22XLTS U2156 ( .A0(n3306), .A1(DMP_SHT2_EWSW[43]), .B0(n2861), .B1(
DMP_SFG[43]), .Y(n1411) );
AO22XLTS U2157 ( .A0(n3306), .A1(DMP_SHT2_EWSW[44]), .B0(n2861), .B1(
DMP_SFG[44]), .Y(n1408) );
AO22XLTS U2158 ( .A0(n3306), .A1(DMP_SHT2_EWSW[45]), .B0(n2861), .B1(
DMP_SFG[45]), .Y(n1405) );
AO22XLTS U2159 ( .A0(n3306), .A1(DMP_SHT2_EWSW[46]), .B0(n2861), .B1(
DMP_SFG[46]), .Y(n1402) );
AO22XLTS U2160 ( .A0(n3306), .A1(DMP_SHT2_EWSW[47]), .B0(n2861), .B1(
DMP_SFG[47]), .Y(n1399) );
AO22XLTS U2161 ( .A0(n3306), .A1(DMP_SHT2_EWSW[48]), .B0(n3130), .B1(
DMP_SFG[48]), .Y(n1396) );
AO22XLTS U2162 ( .A0(n3306), .A1(DMP_SHT2_EWSW[49]), .B0(n2864), .B1(
DMP_SFG[49]), .Y(n1393) );
AO22XLTS U2163 ( .A0(n3306), .A1(DMP_SHT2_EWSW[50]), .B0(n3295), .B1(
DMP_SFG[50]), .Y(n1390) );
AO22XLTS U2164 ( .A0(n3306), .A1(DMP_SHT2_EWSW[51]), .B0(n2852), .B1(
DMP_SFG[51]), .Y(n1387) );
AO22XLTS U2165 ( .A0(n3024), .A1(n2973), .B0(n3088), .B1(
Raw_mant_NRM_SWR[51]), .Y(n1167) );
OAI211XLTS U2166 ( .A0(n2596), .A1(n2670), .B0(n2582), .C0(n2581), .Y(n1658)
);
AOI2BB2XLTS U2167 ( .B0(Raw_mant_NRM_SWR[26]), .B1(n1826), .A0N(n2638),
.A1N(n2724), .Y(n2581) );
AO22XLTS U2168 ( .A0(n3261), .A1(n3001), .B0(n3130), .B1(DmP_mant_SFG_SWR[1]), .Y(n1160) );
AO22XLTS U2169 ( .A0(n3261), .A1(n3010), .B0(n3130), .B1(DmP_mant_SFG_SWR[0]), .Y(n1157) );
AO22XLTS U2170 ( .A0(n3261), .A1(n3246), .B0(n3307), .B1(DmP_mant_SFG_SWR[2]), .Y(n1154) );
AO22XLTS U2171 ( .A0(n3306), .A1(DMP_SHT2_EWSW[0]), .B0(n3307), .B1(
DMP_SFG[0]), .Y(n1540) );
AO22XLTS U2172 ( .A0(n2866), .A1(DmP_EXP_EWSW[8]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[8]), .Y(n1314) );
AO22XLTS U2173 ( .A0(n2868), .A1(DmP_EXP_EWSW[3]), .B0(n2865), .B1(
DmP_mant_SHT1_SW[3]), .Y(n1324) );
AO22XLTS U2174 ( .A0(n2866), .A1(DmP_EXP_EWSW[6]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1318) );
AO22XLTS U2175 ( .A0(n2867), .A1(DmP_EXP_EWSW[9]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[9]), .Y(n1312) );
AO22XLTS U2176 ( .A0(n2867), .A1(DmP_EXP_EWSW[13]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1304) );
AO22XLTS U2177 ( .A0(n2868), .A1(DmP_EXP_EWSW[25]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[25]), .Y(n1280) );
AO22XLTS U2178 ( .A0(n2878), .A1(DmP_EXP_EWSW[34]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[34]), .Y(n1262) );
AOI222X1TS U2179 ( .A0(n1827), .A1(intDX_EWSW[52]), .B0(DmP_EXP_EWSW[52]),
.B1(n1933), .C0(intDY_EWSW[52]), .C1(n2431), .Y(n2337) );
AO22XLTS U2180 ( .A0(n3297), .A1(DMP_SHT2_EWSW[8]), .B0(n2864), .B1(
DMP_SFG[8]), .Y(n1516) );
AO22XLTS U2181 ( .A0(n2868), .A1(DmP_EXP_EWSW[11]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[11]), .Y(n1308) );
AO22XLTS U2182 ( .A0(n2866), .A1(DmP_EXP_EWSW[18]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[18]), .Y(n1294) );
AO22XLTS U2183 ( .A0(n2867), .A1(DmP_EXP_EWSW[22]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[22]), .Y(n1286) );
AO22XLTS U2184 ( .A0(n2878), .A1(DmP_EXP_EWSW[27]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[27]), .Y(n1276) );
AO22XLTS U2185 ( .A0(n2878), .A1(DmP_EXP_EWSW[31]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[31]), .Y(n1268) );
AO22XLTS U2186 ( .A0(n2878), .A1(DmP_EXP_EWSW[33]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[33]), .Y(n1264) );
AO22XLTS U2187 ( .A0(n2880), .A1(DmP_EXP_EWSW[38]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[38]), .Y(n1254) );
AO22XLTS U2188 ( .A0(n2858), .A1(DMP_SHT2_EWSW[5]), .B0(n2864), .B1(
DMP_SFG[5]), .Y(n1525) );
AO22XLTS U2189 ( .A0(n3292), .A1(DMP_SHT2_EWSW[7]), .B0(n2864), .B1(
DMP_SFG[7]), .Y(n1519) );
AO22XLTS U2190 ( .A0(n2858), .A1(DMP_SHT2_EWSW[11]), .B0(n2864), .B1(
DMP_SFG[11]), .Y(n1507) );
AO22XLTS U2191 ( .A0(n2794), .A1(Data_X[63]), .B0(n2807), .B1(intDX_EWSW[63]), .Y(n1752) );
AO22XLTS U2192 ( .A0(n3528), .A1(DmP_EXP_EWSW[17]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[17]), .Y(n1296) );
AO22XLTS U2193 ( .A0(n3528), .A1(DmP_EXP_EWSW[26]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[26]), .Y(n1278) );
AO22XLTS U2194 ( .A0(n2878), .A1(DmP_EXP_EWSW[28]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[28]), .Y(n1274) );
AO22XLTS U2195 ( .A0(n2878), .A1(DmP_EXP_EWSW[30]), .B0(n2870), .B1(
DmP_mant_SHT1_SW[30]), .Y(n1270) );
AO22XLTS U2196 ( .A0(n2878), .A1(DmP_EXP_EWSW[35]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[35]), .Y(n1260) );
AO22XLTS U2197 ( .A0(n2867), .A1(DmP_EXP_EWSW[10]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[10]), .Y(n1310) );
AO22XLTS U2198 ( .A0(n2868), .A1(DmP_EXP_EWSW[14]), .B0(n2879), .B1(
DmP_mant_SHT1_SW[14]), .Y(n1302) );
AO22XLTS U2199 ( .A0(n2867), .A1(DmP_EXP_EWSW[23]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[23]), .Y(n1284) );
AO22XLTS U2200 ( .A0(n2878), .A1(DmP_EXP_EWSW[32]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[32]), .Y(n1266) );
AO22XLTS U2201 ( .A0(n3297), .A1(DMP_SHT2_EWSW[1]), .B0(n2864), .B1(
DMP_SFG[1]), .Y(n1537) );
AO22XLTS U2202 ( .A0(n3292), .A1(DMP_SHT2_EWSW[9]), .B0(n2864), .B1(
DMP_SFG[9]), .Y(n1513) );
AO22XLTS U2203 ( .A0(n3292), .A1(DMP_SHT2_EWSW[10]), .B0(n2864), .B1(
DMP_SFG[10]), .Y(n1510) );
AO22XLTS U2204 ( .A0(n3136), .A1(n2943), .B0(n3088), .B1(
Raw_mant_NRM_SWR[37]), .Y(n1181) );
AO22XLTS U2205 ( .A0(n1825), .A1(n2925), .B0(n3134), .B1(
Raw_mant_NRM_SWR[30]), .Y(n1188) );
AOI2BB2XLTS U2206 ( .B0(Raw_mant_NRM_SWR[11]), .B1(n1914), .A0N(n2601),
.A1N(n2724), .Y(n2602) );
AOI2BB2XLTS U2207 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1914), .A0N(n2604),
.A1N(n2724), .Y(n2599) );
AOI2BB2XLTS U2208 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[41]), .A0N(n2682),
.A1N(n2719), .Y(n2683) );
OAI211XLTS U2209 ( .A0(n2725), .A1(n2724), .B0(n2723), .C0(n2722), .Y(n1680)
);
AOI2BB2XLTS U2210 ( .B0(DmP_mant_SHT1_SW[49]), .B1(n2721), .A0N(n2720),
.A1N(n2719), .Y(n2722) );
AOI2BB2XLTS U2211 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[47]), .A0N(n2709),
.A1N(n2719), .Y(n2710) );
AO22XLTS U2212 ( .A0(n3136), .A1(n2903), .B0(n2921), .B1(
Raw_mant_NRM_SWR[21]), .Y(n1197) );
AO22XLTS U2213 ( .A0(n1825), .A1(n2952), .B0(n3527), .B1(
Raw_mant_NRM_SWR[41]), .Y(n1177) );
AO22XLTS U2214 ( .A0(n3024), .A1(n2915), .B0(n2921), .B1(
Raw_mant_NRM_SWR[25]), .Y(n1193) );
AO22XLTS U2215 ( .A0(n3024), .A1(n2976), .B0(n3088), .B1(
Raw_mant_NRM_SWR[52]), .Y(n1166) );
AO22XLTS U2216 ( .A0(n2794), .A1(Data_X[61]), .B0(n2807), .B1(intDX_EWSW[61]), .Y(n1754) );
AO22XLTS U2217 ( .A0(n2794), .A1(Data_X[62]), .B0(n2795), .B1(intDX_EWSW[62]), .Y(n1753) );
AO22XLTS U2218 ( .A0(n2794), .A1(Data_X[0]), .B0(n2807), .B1(intDX_EWSW[0]),
.Y(n1815) );
AOI2BB2XLTS U2219 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[39]), .A0N(n2694),
.A1N(n2719), .Y(n2659) );
AO22XLTS U2220 ( .A0(n1825), .A1(n2897), .B0(n2921), .B1(
Raw_mant_NRM_SWR[17]), .Y(n1201) );
AO22XLTS U2221 ( .A0(n3024), .A1(n2970), .B0(n3088), .B1(
Raw_mant_NRM_SWR[49]), .Y(n1169) );
AO22XLTS U2222 ( .A0(n1825), .A1(n2946), .B0(n3088), .B1(
Raw_mant_NRM_SWR[38]), .Y(n1180) );
AO22XLTS U2223 ( .A0(n3090), .A1(n3089), .B0(n3088), .B1(Raw_mant_NRM_SWR[6]), .Y(n1140) );
AOI2BB2XLTS U2224 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[23]), .A0N(n2703),
.A1N(n2719), .Y(n2704) );
AO22XLTS U2225 ( .A0(n3024), .A1(n2891), .B0(n2921), .B1(
Raw_mant_NRM_SWR[15]), .Y(n1203) );
AO22XLTS U2226 ( .A0(n3136), .A1(n2955), .B0(n3088), .B1(
Raw_mant_NRM_SWR[43]), .Y(n1175) );
AO22XLTS U2227 ( .A0(n3090), .A1(n2918), .B0(n2921), .B1(
Raw_mant_NRM_SWR[28]), .Y(n1190) );
AO22XLTS U2228 ( .A0(n3024), .A1(n2894), .B0(n2921), .B1(
Raw_mant_NRM_SWR[16]), .Y(n1202) );
AO22XLTS U2229 ( .A0(n3090), .A1(n2940), .B0(n3088), .B1(
Raw_mant_NRM_SWR[36]), .Y(n1182) );
AO22XLTS U2230 ( .A0(n2796), .A1(Data_X[24]), .B0(n2131), .B1(intDX_EWSW[24]), .Y(n1791) );
AO22XLTS U2231 ( .A0(n2805), .A1(Data_X[2]), .B0(n2806), .B1(intDX_EWSW[2]),
.Y(n1813) );
AO22XLTS U2232 ( .A0(n2794), .A1(Data_X[32]), .B0(n2795), .B1(intDX_EWSW[32]), .Y(n1783) );
AO22XLTS U2233 ( .A0(n2796), .A1(Data_X[16]), .B0(n2800), .B1(intDX_EWSW[16]), .Y(n1799) );
AO22XLTS U2234 ( .A0(n2805), .A1(Data_X[7]), .B0(n2800), .B1(intDX_EWSW[7]),
.Y(n1808) );
AO22XLTS U2235 ( .A0(n3090), .A1(n2961), .B0(n3088), .B1(
Raw_mant_NRM_SWR[45]), .Y(n1173) );
AO22XLTS U2236 ( .A0(n3024), .A1(n2931), .B0(n3088), .B1(
Raw_mant_NRM_SWR[32]), .Y(n1186) );
AO22XLTS U2237 ( .A0(n2805), .A1(Data_X[10]), .B0(n2802), .B1(intDX_EWSW[10]), .Y(n1805) );
AO22XLTS U2238 ( .A0(n2794), .A1(Data_X[48]), .B0(n2807), .B1(intDX_EWSW[48]), .Y(n1767) );
AO22XLTS U2239 ( .A0(n2793), .A1(Data_X[40]), .B0(n2795), .B1(intDX_EWSW[40]), .Y(n1775) );
AO22XLTS U2240 ( .A0(n2798), .A1(Data_X[52]), .B0(n2807), .B1(intDX_EWSW[52]), .Y(n1763) );
AO22XLTS U2241 ( .A0(n2798), .A1(Data_X[37]), .B0(n2795), .B1(intDX_EWSW[37]), .Y(n1778) );
AO22XLTS U2242 ( .A0(n1825), .A1(n2949), .B0(n3088), .B1(
Raw_mant_NRM_SWR[39]), .Y(n1179) );
AO22XLTS U2243 ( .A0(n2794), .A1(Data_X[47]), .B0(n2807), .B1(intDX_EWSW[47]), .Y(n1768) );
AO22XLTS U2244 ( .A0(n2793), .A1(Data_X[44]), .B0(n2795), .B1(intDX_EWSW[44]), .Y(n1771) );
AOI2BB2XLTS U2245 ( .B0(Raw_mant_NRM_SWR[24]), .B1(n1826), .A0N(n2635),
.A1N(n2724), .Y(n2636) );
AO22XLTS U2246 ( .A0(n2793), .A1(Data_X[38]), .B0(n2795), .B1(intDX_EWSW[38]), .Y(n1777) );
AOI2BB2XLTS U2247 ( .B0(Raw_mant_NRM_SWR[29]), .B1(n1826), .A0N(n2655),
.A1N(n2724), .Y(n2624) );
AOI2BB2XLTS U2248 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[26]), .A0N(n2655),
.A1N(n2670), .Y(n2656) );
AOI2BB2XLTS U2249 ( .B0(n2721), .B1(n1937), .A0N(n2689), .A1N(n2719), .Y(
n2668) );
AO22XLTS U2250 ( .A0(n3024), .A1(n2922), .B0(n2921), .B1(
Raw_mant_NRM_SWR[29]), .Y(n1189) );
AO22XLTS U2251 ( .A0(n3090), .A1(n2909), .B0(n2921), .B1(
Raw_mant_NRM_SWR[23]), .Y(n1195) );
AO22XLTS U2252 ( .A0(n1825), .A1(n2964), .B0(n3088), .B1(
Raw_mant_NRM_SWR[47]), .Y(n1171) );
AO22XLTS U2253 ( .A0(n2805), .A1(Data_X[5]), .B0(n2806), .B1(intDX_EWSW[5]),
.Y(n1810) );
AO22XLTS U2254 ( .A0(n3090), .A1(n2900), .B0(n2921), .B1(
Raw_mant_NRM_SWR[20]), .Y(n1198) );
OAI222X1TS U2255 ( .A0(n2874), .A1(n3464), .B0(n3356), .B1(n2873), .C0(n3313), .C1(n2872), .Y(n1226) );
AO22XLTS U2256 ( .A0(n2790), .A1(n3136), .B0(n2792), .B1(n1913), .Y(n1818)
);
AO22XLTS U2257 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[42]), .B0(n3090), .B1(
n2010), .Y(n1176) );
AO22XLTS U2258 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[40]), .B0(n3090), .B1(
n2007), .Y(n1178) );
AO22XLTS U2259 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[46]), .B0(n3136), .B1(
n2004), .Y(n1172) );
AO22XLTS U2260 ( .A0(n3088), .A1(Raw_mant_NRM_SWR[50]), .B0(n1825), .B1(
n2001), .Y(n1168) );
AO22XLTS U2261 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[35]), .B0(n3024), .B1(
n2185), .Y(n1183) );
OAI21XLTS U2262 ( .A0(n2690), .A1(n2652), .B0(n2534), .Y(n1685) );
AO22XLTS U2263 ( .A0(n3253), .A1(n3301), .B0(final_result_ieee[51]), .B1(
n3225), .Y(n1078) );
AO22XLTS U2264 ( .A0(n3253), .A1(n3300), .B0(final_result_ieee[50]), .B1(
n3240), .Y(n1079) );
AO22XLTS U2265 ( .A0(n3253), .A1(n3299), .B0(final_result_ieee[49]), .B1(
n3225), .Y(n1080) );
AO22XLTS U2266 ( .A0(n3253), .A1(n3246), .B0(final_result_ieee[0]), .B1(
n3240), .Y(n1081) );
AO22XLTS U2267 ( .A0(n3253), .A1(n3245), .B0(final_result_ieee[1]), .B1(
n3225), .Y(n1082) );
AO22XLTS U2268 ( .A0(n3253), .A1(n3294), .B0(final_result_ieee[47]), .B1(
n3240), .Y(n1083) );
AO22XLTS U2269 ( .A0(n3253), .A1(n3215), .B0(final_result_ieee[3]), .B1(
n3225), .Y(n1088) );
AO22XLTS U2270 ( .A0(n3253), .A1(n3296), .B0(final_result_ieee[48]), .B1(
n3240), .Y(n1089) );
AO22XLTS U2271 ( .A0(n3253), .A1(n3212), .B0(final_result_ieee[2]), .B1(
n3225), .Y(n1090) );
AO22XLTS U2272 ( .A0(n3253), .A1(n3290), .B0(final_result_ieee[45]), .B1(
n3240), .Y(n1093) );
AO22XLTS U2273 ( .A0(n3253), .A1(n3272), .B0(final_result_ieee[29]), .B1(
n3240), .Y(n1096) );
AO22XLTS U2274 ( .A0(n3253), .A1(n3264), .B0(final_result_ieee[21]), .B1(
n3225), .Y(n1097) );
AO22XLTS U2275 ( .A0(n3253), .A1(n3187), .B0(final_result_ieee[5]), .B1(
n3240), .Y(n1098) );
AO22XLTS U2276 ( .A0(n3253), .A1(n3291), .B0(final_result_ieee[46]), .B1(
n3225), .Y(n1103) );
AO22XLTS U2277 ( .A0(n3172), .A1(n3171), .B0(final_result_ieee[4]), .B1(
n3240), .Y(n1104) );
AO22XLTS U2278 ( .A0(n3172), .A1(n3288), .B0(final_result_ieee[43]), .B1(
n3225), .Y(n1105) );
AO22XLTS U2279 ( .A0(n3172), .A1(n3270), .B0(final_result_ieee[27]), .B1(
n3240), .Y(n1108) );
AO22XLTS U2280 ( .A0(n3172), .A1(n3266), .B0(final_result_ieee[23]), .B1(
n3225), .Y(n1109) );
AO22XLTS U2281 ( .A0(n3172), .A1(n3160), .B0(final_result_ieee[7]), .B1(
n3240), .Y(n1110) );
AO22XLTS U2282 ( .A0(n3172), .A1(n3289), .B0(final_result_ieee[44]), .B1(
n3225), .Y(n1111) );
AO22XLTS U2283 ( .A0(n3172), .A1(n3157), .B0(final_result_ieee[6]), .B1(
n3240), .Y(n1112) );
AO22XLTS U2284 ( .A0(n3172), .A1(n3154), .B0(final_result_ieee[9]), .B1(
n3225), .Y(n1114) );
AO22XLTS U2285 ( .A0(n3172), .A1(n3271), .B0(final_result_ieee[28]), .B1(
n3240), .Y(n1117) );
AO22XLTS U2286 ( .A0(n3172), .A1(n3269), .B0(final_result_ieee[26]), .B1(
n3225), .Y(n1123) );
AO22XLTS U2287 ( .A0(n3172), .A1(n3267), .B0(final_result_ieee[24]), .B1(
n3240), .Y(n1124) );
AO22XLTS U2288 ( .A0(n3172), .A1(n3287), .B0(final_result_ieee[42]), .B1(
n3225), .Y(n1133) );
AO22XLTS U2289 ( .A0(n3253), .A1(n3113), .B0(final_result_ieee[8]), .B1(
n3240), .Y(n1134) );
AO22XLTS U2290 ( .A0(n3024), .A1(n2934), .B0(n3088), .B1(n1950), .Y(n1185)
);
AO22XLTS U2291 ( .A0(n2880), .A1(DmP_EXP_EWSW[48]), .B0(n2870), .B1(n1916),
.Y(n1234) );
AO22XLTS U2292 ( .A0(n2880), .A1(DmP_EXP_EWSW[46]), .B0(n2870), .B1(n1917),
.Y(n1238) );
AO22XLTS U2293 ( .A0(n2880), .A1(DmP_EXP_EWSW[44]), .B0(n2870), .B1(n1928),
.Y(n1242) );
AO22XLTS U2294 ( .A0(n2880), .A1(DmP_EXP_EWSW[42]), .B0(n2870), .B1(n1929),
.Y(n1246) );
AO22XLTS U2295 ( .A0(n2880), .A1(DmP_EXP_EWSW[40]), .B0(n2870), .B1(n1930),
.Y(n1250) );
AO22XLTS U2296 ( .A0(n2880), .A1(DmP_EXP_EWSW[36]), .B0(n2869), .B1(n1918),
.Y(n1258) );
AO22XLTS U2297 ( .A0(n2880), .A1(DmP_EXP_EWSW[29]), .B0(n2869), .B1(n1919),
.Y(n1272) );
AO22XLTS U2298 ( .A0(n3528), .A1(DmP_EXP_EWSW[21]), .B0(n2869), .B1(n1937),
.Y(n1288) );
AO22XLTS U2299 ( .A0(n2866), .A1(DmP_EXP_EWSW[19]), .B0(n2869), .B1(n1938),
.Y(n1292) );
AO22XLTS U2300 ( .A0(n2868), .A1(DmP_EXP_EWSW[15]), .B0(n2865), .B1(n1920),
.Y(n1300) );
AO22XLTS U2301 ( .A0(n2866), .A1(DmP_EXP_EWSW[12]), .B0(n2879), .B1(n1922),
.Y(n1306) );
AO22XLTS U2302 ( .A0(n2868), .A1(DmP_EXP_EWSW[7]), .B0(n2879), .B1(n1924),
.Y(n1316) );
AO22XLTS U2303 ( .A0(n2867), .A1(DmP_EXP_EWSW[5]), .B0(n2865), .B1(n1923),
.Y(n1320) );
AO22XLTS U2304 ( .A0(n2866), .A1(DmP_EXP_EWSW[4]), .B0(n2865), .B1(n1925),
.Y(n1322) );
AO22XLTS U2305 ( .A0(n2858), .A1(DMP_SHT2_EWSW[6]), .B0(n2864), .B1(n1931),
.Y(n1522) );
AO22XLTS U2306 ( .A0(n3292), .A1(DMP_SHT2_EWSW[4]), .B0(n2864), .B1(n1932),
.Y(n1528) );
AO22XLTS U2307 ( .A0(n2848), .A1(n2822), .B0(n2877), .B1(n1926), .Y(n1625)
);
AOI2BB2XLTS U2308 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[45]), .A0N(n2674),
.A1N(n2719), .Y(n2675) );
OAI211XLTS U2309 ( .A0(n2629), .A1(n2670), .B0(n2628), .C0(n2627), .Y(n1639)
);
AOI2BB2XLTS U2310 ( .B0(Raw_mant_NRM_SWR[45]), .B1(n1826), .A0N(n2695),
.A1N(n2724), .Y(n2627) );
AOI2BB2XLTS U2311 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2695),
.A1N(n2719), .Y(n2696) );
OAI211XLTS U2312 ( .A0(n2575), .A1(n2690), .B0(n2574), .C0(n2573), .Y(n1642)
);
AOI2BB2XLTS U2313 ( .B0(Raw_mant_NRM_SWR[42]), .B1(n1826), .A0N(n2578),
.A1N(n2570), .Y(n2573) );
AOI2BB2XLTS U2314 ( .B0(n2718), .B1(DmP_mant_SHT1_SW[10]), .A0N(n2698),
.A1N(n2719), .Y(n2555) );
AOI2BB2XLTS U2315 ( .B0(Raw_mant_NRM_SWR[40]), .B1(n1826), .A0N(n2613),
.A1N(n2570), .Y(n2576) );
AOI2BB2XLTS U2316 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[14]), .A0N(n2713),
.A1N(n2719), .Y(n2714) );
AOI2BB2XLTS U2317 ( .B0(Raw_mant_NRM_SWR[38]), .B1(n1826), .A0N(n2661),
.A1N(n2724), .Y(n2611) );
OAI211XLTS U2318 ( .A0(n2589), .A1(n2670), .B0(n2588), .C0(n2587), .Y(n1649)
);
AOI2BB2XLTS U2319 ( .B0(Raw_mant_NRM_SWR[35]), .B1(n1826), .A0N(n2607),
.A1N(n2724), .Y(n2587) );
AOI2BB2XLTS U2320 ( .B0(n1950), .B1(n1826), .A0N(n2622), .A1N(n2724), .Y(
n2605) );
AOI2BB2XLTS U2321 ( .B0(Raw_mant_NRM_SWR[31]), .B1(n1826), .A0N(n2626),
.A1N(n2724), .Y(n2620) );
AOI2BB2XLTS U2322 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[28]), .A0N(n2658),
.A1N(n2690), .Y(n2653) );
AOI2BB2XLTS U2323 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[30]), .A0N(n2664),
.A1N(n2670), .Y(n2665) );
AOI2BB2XLTS U2324 ( .B0(Raw_mant_NRM_SWR[22]), .B1(n1826), .A0N(n2647),
.A1N(n2724), .Y(n2618) );
AOI2BB2XLTS U2325 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2699),
.A1N(n2719), .Y(n2700) );
AOI2BB2XLTS U2326 ( .B0(Raw_mant_NRM_SWR[20]), .B1(n1914), .A0N(n2679),
.A1N(n2724), .Y(n2645) );
AOI2BB2XLTS U2327 ( .B0(n2718), .B1(DmP_mant_SHT1_SW[32]), .A0N(n2702),
.A1N(n2719), .Y(n2597) );
AOI2BB2XLTS U2328 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[35]), .A0N(n2679),
.A1N(n2719), .Y(n2680) );
OAI211XLTS U2329 ( .A0(n2617), .A1(n2690), .B0(n2616), .C0(n2615), .Y(n1667)
);
AOI2BB2XLTS U2330 ( .B0(Raw_mant_NRM_SWR[17]), .B1(n1914), .A0N(n2614),
.A1N(n2724), .Y(n2615) );
AOI2BB2XLTS U2331 ( .B0(n2721), .B1(DmP_mant_SHT1_SW[37]), .A0N(n2691),
.A1N(n2690), .Y(n2692) );
AOI2BB2XLTS U2332 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1914), .A0N(n2608),
.A1N(n2724), .Y(n2609) );
AOI2BB1XLTS U2333 ( .A0N(n2649), .A1N(n2690), .B0(n2721), .Y(n2650) );
AO22XLTS U2334 ( .A0(n2792), .A1(n2851), .B0(n2790), .B1(n1913), .Y(n1819)
);
OR2X1TS U2335 ( .A(n1872), .B(n1835), .Y(n1829) );
OR2X1TS U2336 ( .A(n1960), .B(n1961), .Y(n1835) );
AO22X1TS U2337 ( .A0(n1999), .A1(DmP_mant_SFG_SWR[13]), .B0(n1980), .B1(
n3037), .Y(n1853) );
OR2X1TS U2338 ( .A(n1967), .B(n1968), .Y(n1858) );
OA22X1TS U2339 ( .A0(shift_value_SHT2_EWR[4]), .A1(n2174), .B0(n3429), .B1(
n3058), .Y(n1860) );
OA22X1TS U2340 ( .A0(shift_value_SHT2_EWR[4]), .A1(n3210), .B0(n3427), .B1(
n3058), .Y(n1861) );
OA22X1TS U2341 ( .A0(shift_value_SHT2_EWR[4]), .A1(n3178), .B0(n3249), .B1(
n3058), .Y(n1862) );
OA22X1TS U2342 ( .A0(shift_value_SHT2_EWR[4]), .A1(n3220), .B0(n3428), .B1(
n3058), .Y(n1863) );
AOI22X1TS U2343 ( .A0(n3307), .A1(n3075), .B0(n2858), .B1(OP_FLAG_SHT2), .Y(
n1873) );
CLKINVX6TS U2344 ( .A(n1832), .Y(n1933) );
BUFX3TS U2345 ( .A(n3486), .Y(n3500) );
INVX4TS U2346 ( .A(n3527), .Y(n3024) );
CLKINVX6TS U2347 ( .A(n3298), .Y(n3261) );
OAI221X1TS U2348 ( .A0(n3338), .A1(intDX_EWSW[27]), .B0(n3419), .B1(
intDX_EWSW[26]), .C0(n2493), .Y(n2496) );
NOR2XLTS U2349 ( .A(n3464), .B(intDY_EWSW[53]), .Y(n2187) );
AOI222X4TS U2350 ( .A0(n2180), .A1(n3303), .B0(n2179), .B1(n3222), .C0(n3009), .C1(n3221), .Y(n3263) );
AOI222X1TS U2351 ( .A0(n2180), .A1(n3239), .B0(n2179), .B1(n2156), .C0(n3009), .C1(n3223), .Y(n3273) );
AOI222X4TS U2352 ( .A0(n3179), .A1(n3239), .B0(n3181), .B1(n2156), .C0(n3182), .C1(n3223), .Y(n3275) );
AOI222X1TS U2353 ( .A0(n3179), .A1(n3361), .B0(n3181), .B1(n3222), .C0(n3182), .C1(n3221), .Y(n3260) );
AOI222X4TS U2354 ( .A0(n3224), .A1(n3239), .B0(n3230), .B1(n2156), .C0(n3231), .C1(n3223), .Y(n3274) );
AOI222X1TS U2355 ( .A0(n3224), .A1(n3303), .B0(n3230), .B1(n3222), .C0(n3231), .C1(n3221), .Y(n3262) );
NAND4X1TS U2356 ( .A(n2086), .B(n2770), .C(n2085), .D(n2736), .Y(n2088) );
OAI21X1TS U2357 ( .A0(n3455), .A1(n3117), .B0(n3091), .Y(n3092) );
OAI211X1TS U2358 ( .A0(n2744), .A1(n2742), .B0(n2041), .C0(n2040), .Y(n2042)
);
NAND2X4TS U2359 ( .A(n2778), .B(Shift_reg_FLAGS_7[0]), .Y(n2784) );
CLKINVX6TS U2360 ( .A(n2799), .Y(n2795) );
BUFX4TS U2361 ( .A(n3516), .Y(n3489) );
BUFX4TS U2362 ( .A(n3525), .Y(n3519) );
BUFX4TS U2363 ( .A(n3516), .Y(n3487) );
BUFX4TS U2364 ( .A(n3499), .Y(n3488) );
INVX2TS U2365 ( .A(n1853), .Y(n1896) );
INVX2TS U2366 ( .A(n1833), .Y(n1897) );
AOI21X2TS U2367 ( .A0(n1956), .A1(n3125), .B0(n3118), .Y(n3153) );
OAI21X1TS U2368 ( .A0(n3457), .A1(n3117), .B0(n3116), .Y(n3118) );
BUFX4TS U2369 ( .A(n3492), .Y(n3498) );
BUFX4TS U2370 ( .A(n3510), .Y(n3522) );
BUFX4TS U2371 ( .A(n3511), .Y(n3486) );
BUFX4TS U2372 ( .A(n3510), .Y(n3485) );
BUFX4TS U2373 ( .A(n3508), .Y(n3495) );
BUFX4TS U2374 ( .A(n3508), .Y(n3480) );
BUFX4TS U2375 ( .A(n3519), .Y(n3494) );
BUFX4TS U2376 ( .A(n3519), .Y(n3517) );
BUFX4TS U2377 ( .A(n3516), .Y(n3490) );
BUFX4TS U2378 ( .A(n3472), .Y(n3491) );
BUFX4TS U2379 ( .A(n3516), .Y(n3523) );
BUFX4TS U2380 ( .A(n3514), .Y(n3496) );
BUFX4TS U2381 ( .A(n3514), .Y(n3509) );
BUFX4TS U2382 ( .A(n3492), .Y(n3497) );
BUFX4TS U2383 ( .A(n3482), .Y(n3483) );
CLKINVX6TS U2384 ( .A(n3056), .Y(n3115) );
BUFX4TS U2385 ( .A(n3485), .Y(n3479) );
BUFX4TS U2386 ( .A(n3485), .Y(n3525) );
BUFX4TS U2387 ( .A(n3481), .Y(n3492) );
BUFX4TS U2388 ( .A(n3509), .Y(n3482) );
BUFX3TS U2389 ( .A(n3480), .Y(n3518) );
BUFX4TS U2390 ( .A(n3530), .Y(n3508) );
BUFX4TS U2391 ( .A(n3530), .Y(n3514) );
BUFX4TS U2392 ( .A(n3491), .Y(n3478) );
BUFX4TS U2393 ( .A(n3491), .Y(n3477) );
BUFX4TS U2394 ( .A(n3517), .Y(n3501) );
BUFX4TS U2395 ( .A(n3522), .Y(n3499) );
XNOR2X2TS U2396 ( .A(DMP_exp_NRM2_EW[8]), .B(n2113), .Y(n2782) );
INVX2TS U2397 ( .A(n1863), .Y(n1898) );
INVX2TS U2398 ( .A(n1862), .Y(n1899) );
XNOR2X2TS U2399 ( .A(DMP_exp_NRM2_EW[0]), .B(n1995), .Y(n2779) );
XNOR2X2TS U2400 ( .A(DMP_exp_NRM2_EW[9]), .B(n2116), .Y(n2783) );
INVX2TS U2401 ( .A(n1860), .Y(n1900) );
INVX2TS U2402 ( .A(n1861), .Y(n1901) );
BUFX4TS U2403 ( .A(n3525), .Y(n3503) );
BUFX4TS U2404 ( .A(n3486), .Y(n3505) );
BUFX4TS U2405 ( .A(n3522), .Y(n3506) );
BUFX4TS U2406 ( .A(n3525), .Y(n3472) );
XNOR2X2TS U2407 ( .A(DMP_exp_NRM2_EW[6]), .B(DP_OP_15J75_123_4372_n6), .Y(
n2780) );
BUFX6TS U2408 ( .A(n2426), .Y(n2455) );
CLKINVX6TS U2409 ( .A(n3468), .Y(n3240) );
CLKINVX6TS U2410 ( .A(n3468), .Y(n3225) );
INVX2TS U2411 ( .A(n1886), .Y(n1902) );
INVX2TS U2412 ( .A(n1877), .Y(n1903) );
INVX2TS U2413 ( .A(n1876), .Y(n1904) );
INVX2TS U2414 ( .A(n1871), .Y(n1905) );
INVX2TS U2415 ( .A(n1870), .Y(n1906) );
INVX2TS U2416 ( .A(n1868), .Y(n1907) );
INVX2TS U2417 ( .A(n1867), .Y(n1908) );
INVX2TS U2418 ( .A(n1866), .Y(n1909) );
INVX2TS U2419 ( .A(n1864), .Y(n1910) );
INVX2TS U2420 ( .A(n1859), .Y(n1911) );
INVX2TS U2421 ( .A(n1856), .Y(n1912) );
INVX2TS U2422 ( .A(n1865), .Y(n1913) );
CLKINVX6TS U2423 ( .A(n2796), .Y(n2807) );
AOI2BB2X2TS U2424 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n3526), .A0N(n2986),
.A1N(DmP_mant_SFG_SWR[11]), .Y(n3099) );
INVX2TS U2425 ( .A(n1875), .Y(n1915) );
CLKINVX6TS U2426 ( .A(n3527), .Y(n3136) );
INVX4TS U2427 ( .A(n3527), .Y(n3090) );
INVX2TS U2428 ( .A(n1895), .Y(n1916) );
INVX2TS U2429 ( .A(n1890), .Y(n1917) );
INVX2TS U2430 ( .A(n1889), .Y(n1918) );
INVX2TS U2431 ( .A(n1894), .Y(n1919) );
INVX2TS U2432 ( .A(n1888), .Y(n1920) );
AOI222X1TS U2433 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n2631), .B0(
DmP_mant_SHT1_SW[50]), .B1(n2644), .C0(n2623), .C1(
DmP_mant_SHT1_SW[51]), .Y(n2649) );
INVX2TS U2434 ( .A(n1885), .Y(n1921) );
INVX2TS U2435 ( .A(n1891), .Y(n1922) );
INVX2TS U2436 ( .A(n1851), .Y(n1923) );
INVX2TS U2437 ( .A(n1884), .Y(n1924) );
INVX2TS U2438 ( .A(n1852), .Y(n1925) );
INVX2TS U2439 ( .A(n1840), .Y(n1926) );
CLKINVX6TS U2440 ( .A(n3307), .Y(n3306) );
BUFX6TS U2441 ( .A(n3295), .Y(n3307) );
INVX2TS U2442 ( .A(n1850), .Y(n1927) );
INVX2TS U2443 ( .A(n1883), .Y(n1928) );
INVX2TS U2444 ( .A(n1882), .Y(n1929) );
INVX2TS U2445 ( .A(n1881), .Y(n1930) );
CLKINVX3TS U2446 ( .A(n2386), .Y(n2873) );
CLKINVX6TS U2447 ( .A(n2859), .Y(n2851) );
BUFX4TS U2448 ( .A(n2623), .Y(n2707) );
BUFX4TS U2449 ( .A(n2623), .Y(n2677) );
BUFX6TS U2450 ( .A(n2063), .Y(n2815) );
BUFX4TS U2451 ( .A(n3516), .Y(n3521) );
BUFX4TS U2452 ( .A(n3499), .Y(n3484) );
BUFX4TS U2453 ( .A(n3516), .Y(n3510) );
BUFX4TS U2454 ( .A(n3499), .Y(n3511) );
BUFX3TS U2455 ( .A(n3518), .Y(n3516) );
INVX2TS U2456 ( .A(n1880), .Y(n1931) );
INVX2TS U2457 ( .A(n1849), .Y(n1932) );
CLKBUFX2TS U2458 ( .A(n1997), .Y(n2845) );
INVX4TS U2459 ( .A(n2798), .Y(n2803) );
INVX4TS U2460 ( .A(n2798), .Y(n2806) );
CLKINVX3TS U2461 ( .A(n2877), .Y(n2850) );
CLKINVX3TS U2462 ( .A(n2877), .Y(n2848) );
BUFX4TS U2463 ( .A(n3481), .Y(n3475) );
BUFX3TS U2464 ( .A(n3517), .Y(n3524) );
CLKINVX6TS U2465 ( .A(left_right_SHT2), .Y(n3303) );
BUFX6TS U2466 ( .A(left_right_SHT2), .Y(n3239) );
INVX4TS U2467 ( .A(n2648), .Y(n2630) );
CLKINVX6TS U2468 ( .A(n3298), .Y(n3285) );
BUFX4TS U2469 ( .A(n2386), .Y(n2453) );
BUFX4TS U2470 ( .A(n2386), .Y(n2442) );
NOR2X8TS U2471 ( .A(n2716), .B(n2648), .Y(n2721) );
INVX3TS U2472 ( .A(n2859), .Y(n2882) );
BUFX4TS U2473 ( .A(n2811), .Y(n2819) );
CLKINVX6TS U2474 ( .A(n2336), .Y(n2435) );
INVX3TS U2475 ( .A(n2859), .Y(n2862) );
INVX3TS U2476 ( .A(n2842), .Y(n2456) );
INVX3TS U2477 ( .A(n2842), .Y(n2449) );
AOI222X4TS U2478 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n2678), .B0(n2677), .B1(
DmP_mant_SHT1_SW[37]), .C0(n2630), .C1(n1918), .Y(n2614) );
INVX2TS U2479 ( .A(n1893), .Y(n1937) );
INVX2TS U2480 ( .A(n1892), .Y(n1938) );
INVX2TS U2481 ( .A(n1848), .Y(n1939) );
INVX2TS U2482 ( .A(n1847), .Y(n1940) );
INVX2TS U2483 ( .A(n1846), .Y(n1941) );
INVX2TS U2484 ( .A(n1845), .Y(n1942) );
AOI211X1TS U2485 ( .A0(n2034), .A1(Raw_mant_NRM_SWR[44]), .B0(
Raw_mant_NRM_SWR[48]), .C0(Raw_mant_NRM_SWR[47]), .Y(n2037) );
NOR4X2TS U2486 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .C(
Raw_mant_NRM_SWR[52]), .D(Raw_mant_NRM_SWR[51]), .Y(n2763) );
AOI22X2TS U2487 ( .A0(n1948), .A1(n2159), .B0(Data_array_SWR[29]), .B1(n3189), .Y(n3173) );
AOI22X2TS U2488 ( .A0(Data_array_SWR[34]), .A1(n2159), .B0(
Data_array_SWR[31]), .B1(n3189), .Y(n3213) );
INVX2TS U2489 ( .A(n1839), .Y(n1943) );
INVX2TS U2490 ( .A(n1844), .Y(n1944) );
INVX2TS U2491 ( .A(n1843), .Y(n1945) );
INVX2TS U2492 ( .A(n1831), .Y(n1946) );
INVX2TS U2493 ( .A(n1842), .Y(n1947) );
INVX2TS U2494 ( .A(n1841), .Y(n1948) );
OAI221X1TS U2495 ( .A0(n3453), .A1(intDX_EWSW[7]), .B0(n3352), .B1(
intDX_EWSW[6]), .C0(n2513), .Y(n2520) );
INVX2TS U2496 ( .A(n1836), .Y(n1949) );
INVX2TS U2497 ( .A(n1855), .Y(n1950) );
INVX2TS U2498 ( .A(n1830), .Y(n1951) );
INVX2TS U2499 ( .A(n1838), .Y(n1952) );
INVX2TS U2500 ( .A(n1834), .Y(n1953) );
INVX2TS U2501 ( .A(n1837), .Y(n1954) );
OAI221XLTS U2502 ( .A0(n3407), .A1(intDX_EWSW[9]), .B0(n3425), .B1(
intDX_EWSW[16]), .C0(n2508), .Y(n2509) );
AOI221X1TS U2503 ( .A0(n3440), .A1(intDX_EWSW[38]), .B0(intDX_EWSW[39]),
.B1(n3438), .C0(n2485), .Y(n2488) );
INVX2TS U2504 ( .A(n1828), .Y(n1955) );
AOI222X1TS U2505 ( .A0(intDX_EWSW[4]), .A1(n3413), .B0(intDX_EWSW[5]), .B1(
n3334), .C0(n2213), .C1(n2212), .Y(n2214) );
OAI221X1TS U2506 ( .A0(n3410), .A1(intDX_EWSW[13]), .B0(n3413), .B1(
intDX_EWSW[4]), .C0(n2506), .Y(n2511) );
INVX2TS U2507 ( .A(n1874), .Y(n1956) );
INVX2TS U2508 ( .A(n1869), .Y(n1957) );
INVX2TS U2509 ( .A(n1878), .Y(n1958) );
INVX2TS U2510 ( .A(n1879), .Y(n1959) );
NOR2XLTS U2511 ( .A(n3416), .B(intDX_EWSW[18]), .Y(n1960) );
NOR2XLTS U2512 ( .A(n3336), .B(intDX_EWSW[19]), .Y(n1961) );
NAND2X1TS U2513 ( .A(n1962), .B(n1963), .Y(n2752) );
INVX1TS U2514 ( .A(n2749), .Y(n1964) );
INVX2TS U2515 ( .A(n2750), .Y(n1965) );
NAND2X1TS U2516 ( .A(n1887), .B(n1966), .Y(n1962) );
OAI31X1TS U2517 ( .A0(n2745), .A1(n2744), .A2(n2743), .B0(n2766), .Y(n2750)
);
OAI221X1TS U2518 ( .A0(n3409), .A1(intDX_EWSW[57]), .B0(n3310), .B1(
intDX_EWSW[56]), .C0(n2463), .Y(n2470) );
OAI211XLTS U2519 ( .A0(n2593), .A1(n2570), .B0(n2592), .C0(n2591), .Y(n1633)
);
NOR4X2TS U2520 ( .A(n2188), .B(n2256), .C(n2268), .D(n2260), .Y(n2313) );
NOR2XLTS U2521 ( .A(n3125), .B(n3070), .Y(n1967) );
NOR2XLTS U2522 ( .A(Data_array_SWR[16]), .B(n3070), .Y(n1968) );
OAI211X2TS U2523 ( .A0(intDY_EWSW[20]), .A1(n3378), .B0(n2499), .C0(n2204),
.Y(n2242) );
OAI211X2TS U2524 ( .A0(intDY_EWSW[12]), .A1(n3367), .B0(n2505), .C0(n2205),
.Y(n2233) );
OAI211X2TS U2525 ( .A0(intDY_EWSW[28]), .A1(n3377), .B0(n2491), .C0(n2195),
.Y(n2250) );
XNOR2X2TS U2526 ( .A(DMP_exp_NRM2_EW[10]), .B(n2120), .Y(n2785) );
AOI2BB2X2TS U2527 ( .B0(DmP_mant_SFG_SWR[3]), .B1(n3526), .A0N(n3075), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n3035) );
AOI2BB2X2TS U2528 ( .B0(DmP_mant_SFG_SWR[7]), .B1(n3526), .A0N(n3076), .A1N(
DmP_mant_SFG_SWR[7]), .Y(n3050) );
AOI2BB2X2TS U2529 ( .B0(DmP_mant_SFG_SWR[9]), .B1(n1999), .A0N(n3076), .A1N(
DmP_mant_SFG_SWR[9]), .Y(n3098) );
OAI211XLTS U2530 ( .A0(n2642), .A1(n2670), .B0(n2641), .C0(n2640), .Y(n1636)
);
CLKINVX6TS U2531 ( .A(n3467), .Y(n2986) );
BUFX4TS U2532 ( .A(Shift_reg_FLAGS_7[0]), .Y(n3468) );
BUFX4TS U2533 ( .A(n3513), .Y(n3507) );
AOI222X1TS U2534 ( .A0(n2157), .A1(n3303), .B0(n3140), .B1(n3221), .C0(n3141), .C1(n2156), .Y(n3145) );
AOI222X1TS U2535 ( .A0(n2178), .A1(n3303), .B0(n3148), .B1(n3221), .C0(n3149), .C1(n2156), .Y(n3254) );
AOI222X4TS U2536 ( .A0(n2182), .A1(n3361), .B0(n3163), .B1(n3221), .C0(n3164), .C1(n2156), .Y(n2985) );
AOI222X1TS U2537 ( .A0(n3204), .A1(n3303), .B0(n3203), .B1(n3221), .C0(n3202), .C1(n2156), .Y(n3255) );
AOI222X1TS U2538 ( .A0(n2182), .A1(n3239), .B0(n3163), .B1(n3223), .C0(n3164), .C1(n3222), .Y(n3283) );
AOI222X4TS U2539 ( .A0(n2178), .A1(n3239), .B0(n3148), .B1(n3223), .C0(n3149), .C1(n3222), .Y(n3282) );
AOI222X4TS U2540 ( .A0(n3204), .A1(n3239), .B0(n3203), .B1(n3223), .C0(n3202), .C1(n3222), .Y(n3281) );
BUFX4TS U2541 ( .A(n2145), .Y(n3222) );
BUFX4TS U2542 ( .A(n2798), .Y(n2808) );
BUFX6TS U2543 ( .A(n2799), .Y(n2798) );
INVX3TS U2544 ( .A(n3221), .Y(n3197) );
INVX3TS U2545 ( .A(n3223), .Y(n3242) );
XOR2X1TS U2546 ( .A(DMP_SFG[11]), .B(n2990), .Y(n2991) );
AOI222X4TS U2547 ( .A0(DMP_SFG[9]), .A1(n3099), .B0(DMP_SFG[9]), .B1(n2987),
.C0(n3099), .C1(n2987), .Y(n3131) );
OAI31XLTS U2548 ( .A0(n2847), .A1(n2532), .A2(n2874), .B0(n2531), .Y(n1543)
);
INVX3TS U2549 ( .A(n2395), .Y(n2874) );
INVX3TS U2550 ( .A(n2859), .Y(n2863) );
INVX4TS U2551 ( .A(n3463), .Y(n2880) );
INVX4TS U2552 ( .A(n3295), .Y(n2858) );
BUFX3TS U2553 ( .A(n2852), .Y(n3295) );
INVX2TS U2554 ( .A(n1969), .Y(n1970) );
NAND2X2TS U2555 ( .A(n2088), .B(Shift_reg_FLAGS_7[1]), .Y(n2777) );
NAND2X1TS U2556 ( .A(Shift_reg_FLAGS_7[1]), .B(n2548), .Y(n2776) );
NOR2X1TS U2557 ( .A(Raw_mant_NRM_SWR[37]), .B(Raw_mant_NRM_SWR[38]), .Y(
n2745) );
NAND2X2TS U2558 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n3117) );
AOI22X2TS U2559 ( .A0(Data_array_SWR[30]), .A1(n3115), .B0(
Data_array_SWR[33]), .B1(n3125), .Y(n3243) );
AOI22X2TS U2560 ( .A0(Data_array_SWR[28]), .A1(n3115), .B0(
Data_array_SWR[32]), .B1(n3125), .Y(n3205) );
AOI32X1TS U2561 ( .A0(Raw_mant_NRM_SWR[39]), .A1(n2015), .A2(n3364), .B0(
Raw_mant_NRM_SWR[41]), .B1(n2015), .Y(n2016) );
NAND2BX1TS U2562 ( .AN(Raw_mant_NRM_SWR[41]), .B(n2015), .Y(n2744) );
NOR2BX2TS U2563 ( .AN(n2019), .B(Raw_mant_NRM_SWR[25]), .Y(n2046) );
NOR2X2TS U2564 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3431), .Y(n2786) );
OAI221X1TS U2565 ( .A0(n3432), .A1(intDX_EWSW[61]), .B0(n3423), .B1(
intDX_EWSW[60]), .C0(n2465), .Y(n2468) );
OAI221XLTS U2566 ( .A0(n3333), .A1(intDX_EWSW[0]), .B0(n3414), .B1(
intDX_EWSW[8]), .C0(n2516), .Y(n2517) );
NOR2X1TS U2567 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .Y(n2731)
);
OAI2BB2XLTS U2568 ( .B0(n2058), .B1(n3323), .A0N(n2728), .A1N(
Raw_mant_NRM_SWR[6]), .Y(n2022) );
AOI32X1TS U2569 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n2728), .A2(n3323), .B0(
Raw_mant_NRM_SWR[5]), .B1(n2728), .Y(n2017) );
NOR2BX2TS U2570 ( .AN(n2018), .B(Raw_mant_NRM_SWR[43]), .Y(n2075) );
NOR3X2TS U2571 ( .A(Raw_mant_NRM_SWR[28]), .B(Raw_mant_NRM_SWR[29]), .C(
n2748), .Y(n2045) );
AOI211X1TS U2572 ( .A0(n2060), .A1(Raw_mant_NRM_SWR[16]), .B0(n2756), .C0(
n2740), .Y(n2061) );
OAI221XLTS U2573 ( .A0(n3335), .A1(intDX_EWSW[17]), .B0(n3418), .B1(
intDX_EWSW[24]), .C0(n2501), .Y(n2502) );
OAI221X1TS U2574 ( .A0(n3331), .A1(intDX_EWSW[3]), .B0(n3412), .B1(
intDX_EWSW[2]), .C0(n2515), .Y(n2518) );
OAI221X1TS U2575 ( .A0(n3337), .A1(intDX_EWSW[25]), .B0(n3421), .B1(
intDX_EWSW[32]), .C0(n2494), .Y(n2495) );
AOI211XLTS U2576 ( .A0(intDX_EWSW[16]), .A1(n3425), .B0(n2237), .C0(n2243),
.Y(n2234) );
OAI221X1TS U2577 ( .A0(n3408), .A1(intDX_EWSW[10]), .B0(n3415), .B1(
intDX_EWSW[12]), .C0(n2507), .Y(n2510) );
OAI221X1TS U2578 ( .A0(n3411), .A1(intDX_EWSW[21]), .B0(n3422), .B1(
intDX_EWSW[48]), .C0(n2500), .Y(n2503) );
AOI211X1TS U2579 ( .A0(intDX_EWSW[52]), .A1(n3434), .B0(n2187), .C0(n2302),
.Y(n2304) );
AOI221X1TS U2580 ( .A0(n3434), .A1(intDX_EWSW[52]), .B0(intDX_EWSW[53]),
.B1(n3313), .C0(n2461), .Y(n2473) );
AOI222X1TS U2581 ( .A0(n2435), .A1(intDX_EWSW[52]), .B0(DMP_EXP_EWSW[52]),
.B1(n1933), .C0(intDY_EWSW[52]), .C1(n1827), .Y(n2338) );
NOR3X1TS U2582 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[39]), .C(
n2744), .Y(n2013) );
NOR2X2TS U2583 ( .A(Raw_mant_NRM_SWR[40]), .B(Raw_mant_NRM_SWR[39]), .Y(
n2742) );
AOI211X2TS U2584 ( .A0(intDX_EWSW[44]), .A1(n3445), .B0(n2270), .C0(n2279),
.Y(n2277) );
AOI21X2TS U2585 ( .A0(Data_array_SWR[17]), .A1(n3125), .B0(n3092), .Y(n3168)
);
OAI31X1TS U2586 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2741), .A2(
Raw_mant_NRM_SWR[24]), .B0(n2046), .Y(n2051) );
NOR2X1TS U2587 ( .A(Raw_mant_NRM_SWR[47]), .B(n2012), .Y(n2018) );
OAI221XLTS U2588 ( .A0(n3334), .A1(intDX_EWSW[5]), .B0(n3420), .B1(
intDX_EWSW[28]), .C0(n2514), .Y(n2519) );
NOR3X2TS U2589 ( .A(Raw_mant_NRM_SWR[19]), .B(Raw_mant_NRM_SWR[20]), .C(
n2067), .Y(n2733) );
AO22XLTS U2590 ( .A0(n2792), .A1(n2453), .B0(n2877), .B1(n2790), .Y(n1978)
);
AO22XLTS U2591 ( .A0(n2792), .A1(n2877), .B0(n2859), .B1(n2790), .Y(n1991)
);
OAI21XLTS U2592 ( .A0(intDX_EWSW[1]), .A1(n3449), .B0(intDX_EWSW[0]), .Y(
n2208) );
NOR2XLTS U2593 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[45]), .Y(
n2034) );
OAI21XLTS U2594 ( .A0(intDY_EWSW[33]), .A1(n3373), .B0(intDY_EWSW[32]), .Y(
n2287) );
NOR2XLTS U2595 ( .A(Raw_mant_NRM_SWR[52]), .B(Raw_mant_NRM_SWR[51]), .Y(
n2036) );
NOR2XLTS U2596 ( .A(n2270), .B(intDX_EWSW[44]), .Y(n2271) );
OAI21XLTS U2597 ( .A0(intDY_EWSW[29]), .A1(n3383), .B0(intDY_EWSW[28]), .Y(
n2194) );
OAI21XLTS U2598 ( .A0(n3457), .A1(n3056), .B0(n3055), .Y(n3057) );
NOR2XLTS U2599 ( .A(n2115), .B(n2783), .Y(n2118) );
INVX2TS U2600 ( .A(n2035), .Y(n2765) );
OAI21XLTS U2601 ( .A0(n3456), .A1(n3117), .B0(n3103), .Y(n3104) );
OAI211XLTS U2602 ( .A0(n3168), .A1(n2127), .B0(n3094), .C0(n3093), .Y(n3095)
);
NOR2XLTS U2603 ( .A(n2326), .B(n1933), .Y(n2327) );
OAI2BB1X1TS U2604 ( .A0N(Shift_amount_SHT1_EWR[1]), .A1N(n1969), .B0(n2776),
.Y(n2533) );
OAI21XLTS U2605 ( .A0(DmP_EXP_EWSW[55]), .A1(n3354), .B0(n2834), .Y(n2831)
);
OAI21XLTS U2606 ( .A0(n3021), .A1(DMP_SFG[0]), .B0(n3034), .Y(n3022) );
OAI21XLTS U2607 ( .A0(n3445), .A1(n2871), .B0(n2374), .Y(n1243) );
OAI21XLTS U2608 ( .A0(n3437), .A1(n2871), .B0(n2375), .Y(n1257) );
OAI21XLTS U2609 ( .A0(n3452), .A1(n2872), .B0(n2331), .Y(n1271) );
OAI21XLTS U2610 ( .A0(n3347), .A1(n2872), .B0(n2363), .Y(n1285) );
OAI21XLTS U2611 ( .A0(n3340), .A1(n2451), .B0(n2406), .Y(n1549) );
OAI21XLTS U2612 ( .A0(n3343), .A1(n2451), .B0(n2438), .Y(n1567) );
OAI21XLTS U2613 ( .A0(n3338), .A1(n2433), .B0(n2421), .Y(n1581) );
OAI21XLTS U2614 ( .A0(n3410), .A1(n2433), .B0(n2417), .Y(n1595) );
OAI21XLTS U2615 ( .A0(n3333), .A1(n2874), .B0(n2392), .Y(n1608) );
BUFX4TS U2616 ( .A(n3467), .Y(n3037) );
INVX4TS U2617 ( .A(n3467), .Y(n3075) );
INVX4TS U2618 ( .A(n3295), .Y(n3292) );
NOR2XLTS U2619 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1998) );
AOI32X4TS U2620 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1998), .B1(n3431), .Y(n2792)
);
BUFX4TS U2621 ( .A(n2386), .Y(n2529) );
BUFX3TS U2622 ( .A(n3463), .Y(n2877) );
INVX2TS U2623 ( .A(n2792), .Y(n2790) );
BUFX4TS U2624 ( .A(n3527), .Y(n3088) );
AOI2BB2XLTS U2625 ( .B0(n1906), .B1(n2986), .A0N(n2986), .A1N(n1906), .Y(
n2972) );
AOI2BB2XLTS U2626 ( .B0(n1907), .B1(n2986), .A0N(n2986), .A1N(n1907), .Y(
n2969) );
AOI2BB2XLTS U2627 ( .B0(n1908), .B1(n2986), .A0N(n2986), .A1N(n1908), .Y(
n2966) );
AOI2BB2XLTS U2628 ( .B0(n1909), .B1(n2986), .A0N(n2986), .A1N(n1909), .Y(
n2963) );
AOI2BB2XLTS U2629 ( .B0(n1910), .B1(n2986), .A0N(n2986), .A1N(n1910), .Y(
n2003) );
INVX4TS U2630 ( .A(n3467), .Y(n3076) );
AOI2BB2XLTS U2631 ( .B0(DmP_mant_SFG_SWR[45]), .B1(n3076), .A0N(n1999),
.A1N(DmP_mant_SFG_SWR[45]), .Y(n2960) );
AOI2BB2XLTS U2632 ( .B0(n1911), .B1(n3075), .A0N(n2986), .A1N(n1911), .Y(
n2957) );
AOI2BB2XLTS U2633 ( .B0(n1912), .B1(n3076), .A0N(n2986), .A1N(n1912), .Y(
n2954) );
INVX4TS U2634 ( .A(n3467), .Y(n1999) );
AOI22X1TS U2635 ( .A0(n1999), .A1(DmP_mant_SFG_SWR[42]), .B0(n1985), .B1(
n3037), .Y(n2009) );
AOI22X1TS U2636 ( .A0(n3075), .A1(DmP_mant_SFG_SWR[41]), .B0(n1984), .B1(
n3037), .Y(n2951) );
AOI22X1TS U2637 ( .A0(n3076), .A1(DmP_mant_SFG_SWR[40]), .B0(n1983), .B1(
n3037), .Y(n2006) );
AOI22X1TS U2638 ( .A0(n1999), .A1(DmP_mant_SFG_SWR[39]), .B0(n1982), .B1(
n3037), .Y(n2948) );
AOI22X1TS U2639 ( .A0(DmP_mant_SFG_SWR[38]), .A1(n3526), .B0(n3037), .B1(
n1981), .Y(n2945) );
AOI22X1TS U2640 ( .A0(DmP_mant_SFG_SWR[37]), .A1(n3526), .B0(n3037), .B1(
n1979), .Y(n2942) );
AOI22X1TS U2641 ( .A0(DmP_mant_SFG_SWR[36]), .A1(n3526), .B0(n3037), .B1(
n1977), .Y(n2939) );
AOI22X1TS U2642 ( .A0(DmP_mant_SFG_SWR[35]), .A1(n3526), .B0(n3037), .B1(
n1976), .Y(n2184) );
AOI22X1TS U2643 ( .A0(DmP_mant_SFG_SWR[34]), .A1(n3526), .B0(n3037), .B1(
n1975), .Y(n2936) );
AOI22X1TS U2644 ( .A0(DmP_mant_SFG_SWR[33]), .A1(n3526), .B0(n3037), .B1(
n1974), .Y(n2933) );
AOI22X1TS U2645 ( .A0(DmP_mant_SFG_SWR[32]), .A1(n3526), .B0(n3037), .B1(
n1973), .Y(n2930) );
AOI22X1TS U2646 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n3526), .B0(n3467), .B1(
n1972), .Y(n2905) );
AOI22X1TS U2647 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n3075), .B0(n3037), .B1(
n1971), .Y(n2902) );
AOI22X1TS U2648 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n3076), .B0(n3467), .B1(
n1994), .Y(n2899) );
AOI22X1TS U2649 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n1999), .B0(n3467), .B1(
n1993), .Y(n2099) );
AOI22X1TS U2650 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n3075), .B0(n3467), .B1(
n1992), .Y(n2096) );
AOI22X1TS U2651 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n3076), .B0(n3037), .B1(
n1990), .Y(n2896) );
AOI22X1TS U2652 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n1999), .B0(n3037), .B1(
n1989), .Y(n2893) );
AOI22X1TS U2653 ( .A0(n3075), .A1(DmP_mant_SFG_SWR[15]), .B0(n1988), .B1(
n3037), .Y(n2890) );
AOI22X1TS U2654 ( .A0(n3076), .A1(DmP_mant_SFG_SWR[14]), .B0(n1987), .B1(
n3037), .Y(n2887) );
AOI22X2TS U2655 ( .A0(DmP_mant_SFG_SWR[12]), .A1(n3526), .B0(n3467), .B1(
n1986), .Y(n3133) );
OAI2BB1X1TS U2656 ( .A0N(n1896), .A1N(DMP_SFG[11]), .B0(n2000), .Y(n2886) );
BUFX4TS U2657 ( .A(n3527), .Y(n3134) );
NOR2X1TS U2658 ( .A(Shift_reg_FLAGS_7[1]), .B(n2882), .Y(n2063) );
BUFX4TS U2659 ( .A(n2815), .Y(n2712) );
NOR2X2TS U2660 ( .A(Shift_reg_FLAGS_7[1]), .B(n2859), .Y(n2818) );
AOI22X1TS U2661 ( .A0(n2712), .A1(shift_value_SHT2_EWR[3]), .B0(n2818), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n2033) );
NOR2X1TS U2662 ( .A(Raw_mant_NRM_SWR[18]), .B(Raw_mant_NRM_SWR[17]), .Y(
n2732) );
NOR2X1TS U2663 ( .A(Raw_mant_NRM_SWR[50]), .B(Raw_mant_NRM_SWR[49]), .Y(
n2035) );
NAND2X1TS U2664 ( .A(n2035), .B(n2763), .Y(n2011) );
NAND2X2TS U2665 ( .A(n2045), .B(n3362), .Y(n2026) );
NAND2X1TS U2666 ( .A(Raw_mant_NRM_SWR[21]), .B(n2014), .Y(n2751) );
OAI211X1TS U2667 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n2017), .B0(n2751), .C0(
n2016), .Y(n2074) );
AOI32X1TS U2668 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n2727), .A2(n3311), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2727), .Y(n2020) );
NAND2X1TS U2669 ( .A(Raw_mant_NRM_SWR[43]), .B(n2018), .Y(n2041) );
AOI21X1TS U2670 ( .A0(n2024), .A1(Raw_mant_NRM_SWR[23]), .B0(n2021), .Y(
n2086) );
OAI31X1TS U2671 ( .A0(Raw_mant_NRM_SWR[42]), .A1(n2022), .A2(
Raw_mant_NRM_SWR[40]), .B0(n2075), .Y(n2769) );
NOR3BX1TS U2672 ( .AN(n2080), .B(n2023), .C(Raw_mant_NRM_SWR[47]), .Y(n2030)
);
OAI2BB1X1TS U2673 ( .A0N(n2025), .A1N(Raw_mant_NRM_SWR[30]), .B0(n2768), .Y(
n2757) );
OAI2BB2XLTS U2674 ( .B0(n3454), .B1(n2026), .A0N(Raw_mant_NRM_SWR[24]),
.A1N(n2046), .Y(n2029) );
OAI22X1TS U2675 ( .A0(n3311), .A1(n2055), .B0(n3460), .B1(n2027), .Y(n2028)
);
NOR4X1TS U2676 ( .A(n2030), .B(n2757), .C(n2029), .D(n2028), .Y(n2031) );
OAI21X1TS U2677 ( .A0(Raw_mant_NRM_SWR[19]), .A1(Raw_mant_NRM_SWR[20]), .B0(
n2759), .Y(n2050) );
OAI21X1TS U2678 ( .A0(n2074), .A1(n2032), .B0(Shift_reg_FLAGS_7[1]), .Y(
n2758) );
NAND2X1TS U2679 ( .A(n2033), .B(n2758), .Y(n1629) );
NAND2X1TS U2680 ( .A(n2065), .B(Raw_mant_NRM_SWR[28]), .Y(n2766) );
OR2X1TS U2681 ( .A(Raw_mant_NRM_SWR[54]), .B(Raw_mant_NRM_SWR[53]), .Y(n2038) );
OAI32X1TS U2682 ( .A0(n2038), .A1(n2037), .A2(n2765), .B0(n2036), .B1(n2038),
.Y(n2039) );
INVX2TS U2683 ( .A(n2039), .Y(n2040) );
INVX2TS U2684 ( .A(n2042), .Y(n2062) );
OR2X1TS U2685 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .Y(n2044) );
AOI22X1TS U2686 ( .A0(Raw_mant_NRM_SWR[27]), .A1(n2045), .B0(n2761), .B1(
n2044), .Y(n2052) );
INVX2TS U2687 ( .A(n2084), .Y(n2753) );
NOR4X2TS U2688 ( .A(Raw_mant_NRM_SWR[1]), .B(Raw_mant_NRM_SWR[2]), .C(n2753),
.D(n3329), .Y(n2741) );
NOR2XLTS U2689 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[3]), .Y(n2059)
);
NAND2X1TS U2690 ( .A(Raw_mant_NRM_SWR[15]), .B(n2053), .Y(n2081) );
AOI32X1TS U2691 ( .A0(n2081), .A1(n3308), .A2(n3327), .B0(n2771), .B1(n2081),
.Y(n2054) );
INVX2TS U2692 ( .A(n2054), .Y(n2057) );
OAI211X1TS U2693 ( .A0(n2059), .A1(n2058), .B0(n2057), .C0(n2056), .Y(n2740)
);
BUFX3TS U2694 ( .A(n2063), .Y(n2811) );
NOR2BX4TS U2695 ( .AN(n2533), .B(n2811), .Y(n2554) );
OR2X1TS U2696 ( .A(Raw_mant_NRM_SWR[28]), .B(n2748), .Y(n2072) );
NOR3BX1TS U2697 ( .AN(Raw_mant_NRM_SWR[31]), .B(Raw_mant_NRM_SWR[32]), .C(
n2064), .Y(n2069) );
AOI22X1TS U2698 ( .A0(n1950), .A1(n2066), .B0(n2065), .B1(
Raw_mant_NRM_SWR[29]), .Y(n2747) );
OAI31X1TS U2699 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n3398), .A2(n2067), .B0(
n2747), .Y(n2068) );
AOI211X1TS U2700 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2080), .B0(n2069), .C0(
n2068), .Y(n2071) );
NAND2X1TS U2701 ( .A(Raw_mant_NRM_SWR[13]), .B(n2070), .Y(n2737) );
AOI211X1TS U2702 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n2726), .B0(n2074), .C0(
n2073), .Y(n2770) );
NAND4XLTS U2703 ( .A(n2742), .B(n2075), .C(Raw_mant_NRM_SWR[37]), .D(n3365),
.Y(n2078) );
AOI21X1TS U2704 ( .A0(Raw_mant_NRM_SWR[49]), .A1(n3387), .B0(
Raw_mant_NRM_SWR[51]), .Y(n2076) );
AOI2BB1XLTS U2705 ( .A0N(Raw_mant_NRM_SWR[52]), .A1N(n2076), .B0(
Raw_mant_NRM_SWR[53]), .Y(n2077) );
OAI22X1TS U2706 ( .A0(Raw_mant_NRM_SWR[38]), .A1(n2078), .B0(
Raw_mant_NRM_SWR[54]), .B1(n2077), .Y(n2079) );
AOI31XLTS U2707 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n2080), .A2(n3376), .B0(
n2079), .Y(n2082) );
INVX2TS U2708 ( .A(n2777), .Y(n2087) );
INVX4TS U2709 ( .A(n2777), .Y(n2667) );
NAND2X1TS U2710 ( .A(n1926), .B(n1969), .Y(n2549) );
AOI22X1TS U2711 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n2667), .B0(n2623), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2090) );
NOR2X2TS U2712 ( .A(n1969), .B(n2088), .Y(n2553) );
BUFX3TS U2713 ( .A(n2553), .Y(n2631) );
NOR2X1TS U2714 ( .A(Shift_reg_FLAGS_7[1]), .B(n1926), .Y(n2557) );
INVX2TS U2715 ( .A(n2557), .Y(n2648) );
AOI22X1TS U2716 ( .A0(Raw_mant_NRM_SWR[52]), .A1(n2631), .B0(n2644), .B1(
n1927), .Y(n2089) );
NAND2X1TS U2717 ( .A(n2090), .B(n2089), .Y(n2590) );
AOI22X1TS U2718 ( .A0(n2815), .A1(Data_array_SWR[0]), .B0(n2554), .B1(n2590),
.Y(n2092) );
AOI22X1TS U2719 ( .A0(Raw_mant_NRM_SWR[54]), .A1(n2631), .B0(
Raw_mant_NRM_SWR[53]), .B1(n1914), .Y(n2091) );
NAND2X1TS U2720 ( .A(n2092), .B(n2091), .Y(n1631) );
BUFX3TS U2721 ( .A(n3499), .Y(n3493) );
BUFX3TS U2722 ( .A(n3518), .Y(n3520) );
BUFX3TS U2723 ( .A(n3485), .Y(n3512) );
BUFX3TS U2724 ( .A(n3516), .Y(n3513) );
BUFX3TS U2725 ( .A(n3495), .Y(n3515) );
BUFX3TS U2726 ( .A(n3519), .Y(n3481) );
BUFX3TS U2727 ( .A(n3512), .Y(n3504) );
BUFX3TS U2728 ( .A(n3512), .Y(n3469) );
BUFX3TS U2729 ( .A(n3530), .Y(n3502) );
BUFX3TS U2730 ( .A(n3525), .Y(n3474) );
BUFX3TS U2731 ( .A(n3481), .Y(n3476) );
BUFX3TS U2732 ( .A(n3491), .Y(n3473) );
BUFX3TS U2733 ( .A(n3520), .Y(n3471) );
BUFX3TS U2734 ( .A(n3473), .Y(n3470) );
AO22XLTS U2735 ( .A0(n1970), .A1(ZERO_FLAG_NRM), .B0(n1969), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n1215) );
AO22XLTS U2736 ( .A0(n1970), .A1(SIGN_FLAG_NRM), .B0(n1969), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n1206) );
BUFX4TS U2737 ( .A(n3527), .Y(n2921) );
AO22XLTS U2738 ( .A0(n1825), .A1(DMP_SFG[57]), .B0(n2921), .B1(
DMP_exp_NRM_EW[5]), .Y(n1358) );
AO22XLTS U2739 ( .A0(n3090), .A1(DMP_SFG[56]), .B0(n2921), .B1(
DMP_exp_NRM_EW[4]), .Y(n1363) );
AO22XLTS U2740 ( .A0(n1825), .A1(ZERO_FLAG_SFG), .B0(n2921), .B1(
ZERO_FLAG_NRM), .Y(n1216) );
AO22XLTS U2741 ( .A0(n3090), .A1(DMP_SFG[59]), .B0(n2921), .B1(
DMP_exp_NRM_EW[7]), .Y(n1348) );
AO22XLTS U2742 ( .A0(n3136), .A1(DMP_SFG[60]), .B0(n2921), .B1(
DMP_exp_NRM_EW[8]), .Y(n1343) );
AO22XLTS U2743 ( .A0(n1825), .A1(DMP_SFG[58]), .B0(n2921), .B1(
DMP_exp_NRM_EW[6]), .Y(n1353) );
AO22XLTS U2744 ( .A0(n3024), .A1(DMP_SFG[62]), .B0(n2921), .B1(
DMP_exp_NRM_EW[10]), .Y(n1333) );
AO22XLTS U2745 ( .A0(n1825), .A1(DMP_SFG[55]), .B0(n2921), .B1(
DMP_exp_NRM_EW[3]), .Y(n1368) );
AO22XLTS U2746 ( .A0(n3024), .A1(SIGN_FLAG_SFG), .B0(n2921), .B1(
SIGN_FLAG_NRM), .Y(n1207) );
AOI2BB2X1TS U2747 ( .B0(n1915), .B1(n3075), .A0N(n2986), .A1N(n1915), .Y(
n3087) );
OAI211XLTS U2748 ( .A0(DMP_SFG[5]), .A1(n3050), .B0(n1932), .C0(n3087), .Y(
n2093) );
OAI2BB1X1TS U2749 ( .A0N(n3050), .A1N(DMP_SFG[5]), .B0(n2093), .Y(n3074) );
AOI2BB2X1TS U2750 ( .B0(DmP_mant_SFG_SWR[8]), .B1(n1999), .A0N(n3075), .A1N(
DmP_mant_SFG_SWR[8]), .Y(n3096) );
AO22XLTS U2751 ( .A0(n3527), .A1(Raw_mant_NRM_SWR[8]), .B0(n3136), .B1(n2094), .Y(n1131) );
AO22XLTS U2752 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[18]), .B0(n3136), .B1(
n2097), .Y(n1200) );
AO22XLTS U2753 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[19]), .B0(n3136), .B1(
n2100), .Y(n1199) );
AO22XLTS U2754 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[26]), .B0(n1825), .B1(
n2103), .Y(n1192) );
INVX2TS U2755 ( .A(DP_OP_15J75_123_4372_n6), .Y(n2104) );
NAND2X1TS U2756 ( .A(n3405), .B(n2104), .Y(n2110) );
INVX2TS U2757 ( .A(n2110), .Y(n2105) );
NAND2X1TS U2758 ( .A(n3426), .B(n2105), .Y(n2113) );
NOR2XLTS U2759 ( .A(n2779), .B(exp_rslt_NRM2_EW1[1]), .Y(n2108) );
INVX2TS U2760 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n2107) );
INVX2TS U2761 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n2106) );
NAND4BXLTS U2762 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n2108), .C(n2107), .D(n2106), .Y(n2109) );
NOR2XLTS U2763 ( .A(n2109), .B(exp_rslt_NRM2_EW1[5]), .Y(n2112) );
XNOR2X1TS U2764 ( .A(DMP_exp_NRM2_EW[7]), .B(n2110), .Y(n2781) );
INVX2TS U2765 ( .A(n2781), .Y(n2124) );
INVX2TS U2766 ( .A(n2780), .Y(n2111) );
NAND4BXLTS U2767 ( .AN(n2782), .B(n2112), .C(n2124), .D(n2111), .Y(n2115) );
INVX2TS U2768 ( .A(n2113), .Y(n2114) );
NAND2X1TS U2769 ( .A(n3436), .B(n2114), .Y(n2116) );
INVX2TS U2770 ( .A(n2116), .Y(n2117) );
NAND2X1TS U2771 ( .A(n3435), .B(n2117), .Y(n2120) );
NOR2BX1TS U2772 ( .AN(n2118), .B(n2785), .Y(n2119) );
INVX2TS U2773 ( .A(n2119), .Y(n2778) );
INVX2TS U2774 ( .A(n2778), .Y(n2884) );
INVX2TS U2775 ( .A(n2120), .Y(n2121) );
CLKAND2X2TS U2776 ( .A(n3459), .B(n2121), .Y(n2126) );
NAND4XLTS U2777 ( .A(exp_rslt_NRM2_EW1[3]), .B(exp_rslt_NRM2_EW1[2]), .C(
n2779), .D(exp_rslt_NRM2_EW1[1]), .Y(n2122) );
NAND4BXLTS U2778 ( .AN(n2122), .B(n2780), .C(exp_rslt_NRM2_EW1[5]), .D(
exp_rslt_NRM2_EW1[4]), .Y(n2123) );
NOR3BXLTS U2779 ( .AN(n2782), .B(n2124), .C(n2123), .Y(n2125) );
NAND4XLTS U2780 ( .A(n2783), .B(n2126), .C(n2785), .D(n2125), .Y(n2883) );
NAND2X1TS U2781 ( .A(n3468), .B(n2883), .Y(n2876) );
INVX4TS U2782 ( .A(n2146), .Y(n3172) );
NAND2X1TS U2783 ( .A(shift_value_SHT2_EWR[2]), .B(n3386), .Y(n2128) );
NOR2X1TS U2784 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n2158) );
INVX2TS U2785 ( .A(n2158), .Y(n3056) );
AOI222X4TS U2786 ( .A0(Data_array_SWR[28]), .A1(n2159), .B0(
Data_array_SWR[25]), .B1(n3115), .C0(Data_array_SWR[32]), .C1(n3080),
.Y(n3156) );
NOR2X2TS U2787 ( .A(n3363), .B(shift_value_SHT2_EWR[5]), .Y(n3232) );
NAND2BX2TS U2788 ( .AN(shift_value_SHT2_EWR[5]), .B(n3363), .Y(n2152) );
NOR2BX1TS U2789 ( .AN(n3080), .B(n2152), .Y(n2147) );
BUFX3TS U2790 ( .A(n2147), .Y(n3198) );
NOR2X1TS U2791 ( .A(n3056), .B(n2152), .Y(n2996) );
BUFX3TS U2792 ( .A(n2996), .Y(n3229) );
AOI22X1TS U2793 ( .A0(n1949), .A1(n3198), .B0(Data_array_SWR[16]), .B1(n3229), .Y(n2130) );
NOR2X1TS U2794 ( .A(n2152), .B(n3117), .Y(n2135) );
BUFX3TS U2795 ( .A(n2135), .Y(n3180) );
NOR2X1TS U2796 ( .A(n2152), .B(n2128), .Y(n2136) );
CLKBUFX3TS U2797 ( .A(n2136), .Y(n3122) );
AOI22X1TS U2798 ( .A0(Data_array_SWR[21]), .A1(n3180), .B0(n1955), .B1(n3122), .Y(n2129) );
OAI211X1TS U2799 ( .A0(n3156), .A1(n2127), .B0(n2130), .C0(n2129), .Y(n3268)
);
AO22XLTS U2800 ( .A0(n3172), .A1(n3268), .B0(final_result_ieee[25]), .B1(
n3240), .Y(n1115) );
AOI22X1TS U2801 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n2786), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n3332), .Y(n2789) );
NAND2X1TS U2802 ( .A(beg_OP), .B(n2789), .Y(n2131) );
INVX2TS U2803 ( .A(n2131), .Y(n2799) );
BUFX4TS U2804 ( .A(n2799), .Y(n2793) );
AO22XLTS U2805 ( .A0(n2793), .A1(Data_X[42]), .B0(n2795), .B1(intDX_EWSW[42]), .Y(n1773) );
AO22XLTS U2806 ( .A0(n2793), .A1(Data_X[41]), .B0(n2795), .B1(intDX_EWSW[41]), .Y(n1774) );
AO22XLTS U2807 ( .A0(n2798), .A1(Data_X[34]), .B0(n2795), .B1(intDX_EWSW[34]), .Y(n1781) );
AO22XLTS U2808 ( .A0(n2793), .A1(Data_X[43]), .B0(n2795), .B1(intDX_EWSW[43]), .Y(n1772) );
AO22XLTS U2809 ( .A0(n2798), .A1(Data_X[35]), .B0(n2795), .B1(intDX_EWSW[35]), .Y(n1780) );
AO22XLTS U2810 ( .A0(n2798), .A1(Data_X[36]), .B0(n2795), .B1(intDX_EWSW[36]), .Y(n1779) );
AO22XLTS U2811 ( .A0(n2803), .A1(intDY_EWSW[55]), .B0(n2793), .B1(Data_Y[55]), .Y(n1694) );
AO22XLTS U2812 ( .A0(n2803), .A1(intDY_EWSW[40]), .B0(n2794), .B1(Data_Y[40]), .Y(n1709) );
AO22XLTS U2813 ( .A0(n2806), .A1(intDY_EWSW[57]), .B0(n2793), .B1(Data_Y[57]), .Y(n1692) );
AO22XLTS U2814 ( .A0(n2806), .A1(intDY_EWSW[58]), .B0(n2793), .B1(Data_Y[58]), .Y(n1691) );
AO22XLTS U2815 ( .A0(n2806), .A1(intDY_EWSW[53]), .B0(n2793), .B1(Data_Y[53]), .Y(n1696) );
AO22XLTS U2816 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[27]), .B0(n3024), .B1(
n2134), .Y(n1191) );
AO22XLTS U2817 ( .A0(n2803), .A1(intDY_EWSW[41]), .B0(n2808), .B1(Data_Y[41]), .Y(n1708) );
AO22XLTS U2818 ( .A0(n2803), .A1(intDY_EWSW[42]), .B0(n2808), .B1(Data_Y[42]), .Y(n1707) );
AOI222X4TS U2819 ( .A0(Data_array_SWR[30]), .A1(n2159), .B0(n1943), .B1(
n3115), .C0(Data_array_SWR[33]), .C1(n3080), .Y(n3169) );
NAND2X2TS U2820 ( .A(n3363), .B(shift_value_SHT2_EWR[5]), .Y(n3201) );
BUFX3TS U2821 ( .A(n2135), .Y(n3228) );
AOI22X1TS U2822 ( .A0(Data_array_SWR[11]), .A1(n3198), .B0(
Data_array_SWR[14]), .B1(n3228), .Y(n2138) );
BUFX3TS U2823 ( .A(n2136), .Y(n3227) );
AOI22X1TS U2824 ( .A0(Data_array_SWR[9]), .A1(n3227), .B0(n1944), .B1(n3229),
.Y(n2137) );
OAI211X1TS U2825 ( .A0(n3169), .A1(n3201), .B0(n2138), .C0(n2137), .Y(n2182)
);
AOI22X1TS U2826 ( .A0(Data_array_SWR[30]), .A1(n3080), .B0(
Data_array_SWR[33]), .B1(n2142), .Y(n2140) );
BUFX4TS U2827 ( .A(n2159), .Y(n3125) );
INVX4TS U2828 ( .A(n3056), .Y(n3189) );
AOI22X1TS U2829 ( .A0(n1943), .A1(n3125), .B0(Data_array_SWR[23]), .B1(n3189), .Y(n2139) );
NAND2X2TS U2830 ( .A(n2140), .B(n2139), .Y(n3163) );
NOR2XLTS U2831 ( .A(n2152), .B(left_right_SHT2), .Y(n2141) );
BUFX3TS U2832 ( .A(n2141), .Y(n3223) );
BUFX3TS U2833 ( .A(n2142), .Y(n3054) );
BUFX4TS U2834 ( .A(n3080), .Y(n3188) );
AOI22X1TS U2835 ( .A0(Data_array_SWR[23]), .A1(n3054), .B0(n1936), .B1(n3188), .Y(n2144) );
AOI22X1TS U2836 ( .A0(n1952), .A1(n3125), .B0(Data_array_SWR[17]), .B1(n3189), .Y(n2143) );
NAND2X1TS U2837 ( .A(n2144), .B(n2143), .Y(n3164) );
NOR2XLTS U2838 ( .A(n3361), .B(n2127), .Y(n2145) );
OAI2BB2XLTS U2839 ( .B0(n3283), .B1(n2146), .A0N(final_result_ieee[39]),
.A1N(n1996), .Y(n1106) );
AOI222X4TS U2840 ( .A0(n1948), .A1(n3188), .B0(Data_array_SWR[29]), .B1(
n2159), .C0(Data_array_SWR[26]), .C1(n3189), .Y(n3137) );
BUFX3TS U2841 ( .A(n2147), .Y(n3226) );
AOI22X1TS U2842 ( .A0(n1945), .A1(n3229), .B0(n1958), .B1(n3226), .Y(n2149)
);
AOI22X1TS U2843 ( .A0(Data_array_SWR[8]), .A1(n3227), .B0(Data_array_SWR[13]), .B1(n3228), .Y(n2148) );
OAI211X1TS U2844 ( .A0(n3137), .A1(n3201), .B0(n2149), .C0(n2148), .Y(n2157)
);
AOI22X1TS U2845 ( .A0(Data_array_SWR[34]), .A1(n2142), .B0(
Data_array_SWR[31]), .B1(n3188), .Y(n2151) );
AOI22X1TS U2846 ( .A0(Data_array_SWR[27]), .A1(n2159), .B0(
Data_array_SWR[24]), .B1(n3115), .Y(n2150) );
NAND2X2TS U2847 ( .A(n2151), .B(n2150), .Y(n3140) );
NOR2XLTS U2848 ( .A(n3361), .B(n2152), .Y(n2153) );
BUFX3TS U2849 ( .A(n2153), .Y(n3221) );
AOI22X1TS U2850 ( .A0(Data_array_SWR[22]), .A1(n2142), .B0(n1934), .B1(n3080), .Y(n2155) );
AOI22X1TS U2851 ( .A0(n1954), .A1(n2159), .B0(n1956), .B1(n3115), .Y(n2154)
);
NAND2X1TS U2852 ( .A(n2155), .B(n2154), .Y(n3141) );
OAI2BB2XLTS U2853 ( .B0(n3145), .B1(n2146), .A0N(final_result_ieee[10]),
.A1N(n1996), .Y(n1121) );
OAI2BB2XLTS U2854 ( .B0(n3284), .B1(n2146), .A0N(final_result_ieee[40]),
.A1N(n1996), .Y(n1120) );
AOI222X4TS U2855 ( .A0(Data_array_SWR[34]), .A1(n3080), .B0(
Data_array_SWR[31]), .B1(n2159), .C0(Data_array_SWR[27]), .C1(n2158),
.Y(n3158) );
AOI22X1TS U2856 ( .A0(n1947), .A1(n3229), .B0(n1959), .B1(n3226), .Y(n2161)
);
AOI22X1TS U2857 ( .A0(Data_array_SWR[15]), .A1(n3180), .B0(n1951), .B1(n3227), .Y(n2160) );
OAI211X1TS U2858 ( .A0(n3158), .A1(n3201), .B0(n2161), .C0(n2160), .Y(n2178)
);
AOI22X1TS U2859 ( .A0(n1948), .A1(n3054), .B0(Data_array_SWR[29]), .B1(n3188), .Y(n2163) );
AOI22X1TS U2860 ( .A0(Data_array_SWR[26]), .A1(n2159), .B0(
Data_array_SWR[22]), .B1(n3189), .Y(n2162) );
NAND2X2TS U2861 ( .A(n2163), .B(n2162), .Y(n3148) );
AOI22X1TS U2862 ( .A0(Data_array_SWR[24]), .A1(n3054), .B0(n1935), .B1(n3080), .Y(n2165) );
AOI22X1TS U2863 ( .A0(n1957), .A1(n3115), .B0(n1953), .B1(n3125), .Y(n2164)
);
NAND2X1TS U2864 ( .A(n2165), .B(n2164), .Y(n3149) );
OAI2BB2XLTS U2865 ( .B0(n3282), .B1(n2146), .A0N(final_result_ieee[38]),
.A1N(n1996), .Y(n1116) );
AOI22X1TS U2866 ( .A0(Data_array_SWR[31]), .A1(n2142), .B0(
Data_array_SWR[27]), .B1(n3188), .Y(n2166) );
OAI21XLTS U2867 ( .A0(n3456), .A1(n3056), .B0(n2166), .Y(n2167) );
AOI21X1TS U2868 ( .A0(Data_array_SWR[24]), .A1(n3125), .B0(n2167), .Y(n2174)
);
AOI22X1TS U2869 ( .A0(Data_array_SWR[15]), .A1(n3227), .B0(n1959), .B1(n3229), .Y(n2171) );
NAND2X1TS U2870 ( .A(n3115), .B(n2168), .Y(n3216) );
OAI2BB2XLTS U2871 ( .B0(n3429), .B1(n3216), .A0N(n1957), .A1N(n3226), .Y(
n2169) );
AOI21X1TS U2872 ( .A0(n1953), .A1(n3228), .B0(n2169), .Y(n2170) );
OAI211X1TS U2873 ( .A0(n2174), .A1(n2127), .B0(n2171), .C0(n2170), .Y(n2180)
);
INVX2TS U2874 ( .A(n3173), .Y(n2179) );
AOI22X1TS U2875 ( .A0(Data_array_SWR[26]), .A1(n3054), .B0(
Data_array_SWR[22]), .B1(n3188), .Y(n2173) );
AOI22X1TS U2876 ( .A0(n1954), .A1(n3115), .B0(n1934), .B1(n3125), .Y(n2172)
);
NAND2X1TS U2877 ( .A(n2173), .B(n2172), .Y(n3009) );
OAI2BB2XLTS U2878 ( .B0(n3273), .B1(n2146), .A0N(final_result_ieee[30]),
.A1N(n1996), .Y(n1127) );
NOR2X2TS U2879 ( .A(shift_value_SHT2_EWR[5]), .B(n3303), .Y(n3236) );
NAND2X1TS U2880 ( .A(shift_value_SHT2_EWR[4]), .B(n3189), .Y(n3058) );
AOI22X1TS U2881 ( .A0(Data_array_SWR[13]), .A1(n3198), .B0(n1958), .B1(n3227), .Y(n2177) );
AOI22X1TS U2882 ( .A0(n1956), .A1(n3180), .B0(Data_array_SWR[8]), .B1(n3229),
.Y(n2176) );
AOI22X1TS U2883 ( .A0(n3232), .A1(n3009), .B0(n2168), .B1(n2179), .Y(n2175)
);
NAND3XLTS U2884 ( .A(n2177), .B(n2176), .C(n2175), .Y(n2181) );
AOI22X1TS U2885 ( .A0(n3236), .A1(n1900), .B0(n3303), .B1(n2181), .Y(n3256)
);
OAI2BB2XLTS U2886 ( .B0(n3256), .B1(n2146), .A0N(final_result_ieee[14]),
.A1N(n1996), .Y(n1126) );
OAI2BB2XLTS U2887 ( .B0(n3254), .B1(n2146), .A0N(final_result_ieee[12]),
.A1N(n1996), .Y(n1119) );
OAI2BB2XLTS U2888 ( .B0(n3263), .B1(n2146), .A0N(final_result_ieee[20]),
.A1N(n1996), .Y(n1128) );
NOR2X2TS U2889 ( .A(shift_value_SHT2_EWR[5]), .B(left_right_SHT2), .Y(n3237)
);
AOI22X1TS U2890 ( .A0(n3239), .A1(n2181), .B0(n3237), .B1(n1900), .Y(n3280)
);
OAI2BB2XLTS U2891 ( .B0(n3280), .B1(n2146), .A0N(final_result_ieee[36]),
.A1N(n1996), .Y(n1125) );
OAI2BB2XLTS U2892 ( .B0(n2985), .B1(n2146), .A0N(final_result_ieee[11]),
.A1N(n1996), .Y(n1107) );
AO22XLTS U2893 ( .A0(n2803), .A1(intDY_EWSW[46]), .B0(n2804), .B1(Data_Y[46]), .Y(n1703) );
AO22XLTS U2894 ( .A0(n2803), .A1(intDY_EWSW[43]), .B0(n2804), .B1(Data_Y[43]), .Y(n1706) );
AO22XLTS U2895 ( .A0(n2806), .A1(intDY_EWSW[45]), .B0(n2804), .B1(Data_Y[45]), .Y(n1704) );
AO22XLTS U2896 ( .A0(n2803), .A1(intDY_EWSW[44]), .B0(n2804), .B1(Data_Y[44]), .Y(n1705) );
BUFX4TS U2897 ( .A(n2793), .Y(n2796) );
AO22XLTS U2898 ( .A0(n2803), .A1(intDY_EWSW[50]), .B0(n2796), .B1(Data_Y[50]), .Y(n1699) );
AO22XLTS U2899 ( .A0(n2806), .A1(intDY_EWSW[56]), .B0(n2796), .B1(Data_Y[56]), .Y(n1693) );
BUFX3TS U2900 ( .A(n2793), .Y(n2801) );
AO22XLTS U2901 ( .A0(n2803), .A1(intDY_EWSW[51]), .B0(n2801), .B1(Data_Y[51]), .Y(n1698) );
AO22XLTS U2902 ( .A0(n2806), .A1(intDY_EWSW[59]), .B0(n2801), .B1(Data_Y[59]), .Y(n1690) );
AO22XLTS U2903 ( .A0(n2806), .A1(intDY_EWSW[62]), .B0(n2801), .B1(Data_Y[62]), .Y(n1687) );
AO22XLTS U2904 ( .A0(n2806), .A1(intDY_EWSW[60]), .B0(n2801), .B1(Data_Y[60]), .Y(n1689) );
AO22XLTS U2905 ( .A0(n2803), .A1(intDY_EWSW[47]), .B0(n2801), .B1(Data_Y[47]), .Y(n1702) );
AO22XLTS U2906 ( .A0(n2806), .A1(intDY_EWSW[61]), .B0(n2801), .B1(Data_Y[61]), .Y(n1688) );
AO22XLTS U2907 ( .A0(n2803), .A1(intDY_EWSW[48]), .B0(n2801), .B1(Data_Y[48]), .Y(n1701) );
AO22XLTS U2908 ( .A0(n2806), .A1(intDX_EWSW[1]), .B0(n2801), .B1(Data_X[1]),
.Y(n1814) );
INVX4TS U2909 ( .A(n2804), .Y(n2802) );
AO22XLTS U2910 ( .A0(n2793), .A1(Data_X[13]), .B0(n2802), .B1(intDX_EWSW[13]), .Y(n1802) );
INVX4TS U2911 ( .A(n2796), .Y(n2800) );
AO22XLTS U2912 ( .A0(n2793), .A1(Data_X[14]), .B0(n2800), .B1(intDX_EWSW[14]), .Y(n1801) );
OAI21XLTS U2913 ( .A0(n2882), .A1(n3303), .B0(n1969), .Y(n1750) );
AOI2BB2XLTS U2914 ( .B0(beg_OP), .B1(n3332), .A0N(n3332), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n2186) );
NAND3XLTS U2915 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n3332), .C(
n3431), .Y(n2787) );
OAI21XLTS U2916 ( .A0(n2786), .A1(n2186), .B0(n2787), .Y(n1823) );
OAI22X1TS U2917 ( .A0(n3465), .A1(intDY_EWSW[55]), .B0(intDY_EWSW[54]), .B1(
n3358), .Y(n2302) );
NOR2BX1TS U2918 ( .AN(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n2188) );
NOR2X1TS U2919 ( .A(n3393), .B(intDY_EWSW[57]), .Y(n2256) );
NAND2X1TS U2920 ( .A(n3432), .B(intDX_EWSW[61]), .Y(n2262) );
OAI211X1TS U2921 ( .A0(intDY_EWSW[60]), .A1(n3385), .B0(n2266), .C0(n2262),
.Y(n2268) );
NAND2BXLTS U2922 ( .AN(intDY_EWSW[59]), .B(intDX_EWSW[59]), .Y(n2258) );
OAI21X1TS U2923 ( .A0(intDY_EWSW[58]), .A1(n3326), .B0(n2258), .Y(n2260) );
NOR2X1TS U2924 ( .A(n3391), .B(intDY_EWSW[49]), .Y(n2305) );
NAND2BXLTS U2925 ( .AN(intDY_EWSW[51]), .B(intDX_EWSW[51]), .Y(n2307) );
OAI21X1TS U2926 ( .A0(intDY_EWSW[50]), .A1(n3322), .B0(n2307), .Y(n2311) );
AOI211X1TS U2927 ( .A0(intDX_EWSW[48]), .A1(n3422), .B0(n2305), .C0(n2311),
.Y(n2189) );
NAND3X1TS U2928 ( .A(n2304), .B(n2313), .C(n2189), .Y(n2321) );
NOR2BX1TS U2929 ( .AN(intDX_EWSW[39]), .B(intDY_EWSW[39]), .Y(n2296) );
AOI21X1TS U2930 ( .A0(intDX_EWSW[38]), .A1(n3440), .B0(n2296), .Y(n2295) );
NAND2X1TS U2931 ( .A(n3437), .B(intDX_EWSW[37]), .Y(n2284) );
OAI211X1TS U2932 ( .A0(intDY_EWSW[36]), .A1(n3381), .B0(n2295), .C0(n2284),
.Y(n2286) );
NOR2X1TS U2933 ( .A(n3388), .B(intDY_EWSW[45]), .Y(n2270) );
OAI21X1TS U2934 ( .A0(intDY_EWSW[46]), .A1(n3366), .B0(n2269), .Y(n2279) );
OA22X1TS U2935 ( .A0(n3374), .A1(intDY_EWSW[42]), .B0(n3318), .B1(
intDY_EWSW[43]), .Y(n2275) );
NAND2BXLTS U2936 ( .AN(intDY_EWSW[41]), .B(intDX_EWSW[41]), .Y(n2191) );
NAND2BXLTS U2937 ( .AN(intDY_EWSW[40]), .B(intDX_EWSW[40]), .Y(n2190) );
NAND4XLTS U2938 ( .A(n2277), .B(n2275), .C(n2191), .D(n2190), .Y(n2319) );
NAND2BXLTS U2939 ( .AN(intDY_EWSW[32]), .B(intDX_EWSW[32]), .Y(n2192) );
OA22X1TS U2940 ( .A0(n3375), .A1(intDY_EWSW[34]), .B0(n3319), .B1(
intDY_EWSW[35]), .Y(n2290) );
OAI211XLTS U2941 ( .A0(n3373), .A1(intDY_EWSW[33]), .B0(n2192), .C0(n2290),
.Y(n2193) );
NOR4X1TS U2942 ( .A(n2321), .B(n2286), .C(n2319), .D(n2193), .Y(n2325) );
OA22X1TS U2943 ( .A0(n3379), .A1(intDY_EWSW[30]), .B0(n3320), .B1(
intDY_EWSW[31]), .Y(n2491) );
OAI2BB2XLTS U2944 ( .B0(intDX_EWSW[28]), .B1(n2194), .A0N(intDY_EWSW[29]),
.A1N(n3383), .Y(n2203) );
NAND2BXLTS U2945 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n2197) );
OAI21X1TS U2946 ( .A0(intDY_EWSW[26]), .A1(n3401), .B0(n2197), .Y(n2251) );
NAND2BXLTS U2947 ( .AN(intDY_EWSW[29]), .B(intDX_EWSW[29]), .Y(n2195) );
NOR2X1TS U2948 ( .A(n3389), .B(intDY_EWSW[25]), .Y(n2248) );
NOR2XLTS U2949 ( .A(n2248), .B(intDX_EWSW[24]), .Y(n2196) );
AOI22X1TS U2950 ( .A0(n2196), .A1(intDY_EWSW[24]), .B0(intDY_EWSW[25]), .B1(
n3389), .Y(n2199) );
AOI32X1TS U2951 ( .A0(n3401), .A1(n2197), .A2(intDY_EWSW[26]), .B0(
intDY_EWSW[27]), .B1(n3324), .Y(n2198) );
OAI32X1TS U2952 ( .A0(n2251), .A1(n2250), .A2(n2199), .B0(n2198), .B1(n2250),
.Y(n2202) );
OAI21XLTS U2953 ( .A0(intDY_EWSW[31]), .A1(n3320), .B0(intDY_EWSW[30]), .Y(
n2200) );
OAI2BB2XLTS U2954 ( .B0(intDX_EWSW[30]), .B1(n2200), .A0N(intDY_EWSW[31]),
.A1N(n3320), .Y(n2201) );
AOI211X1TS U2955 ( .A0(n2491), .A1(n2203), .B0(n2202), .C0(n2201), .Y(n2255)
);
OA22X1TS U2956 ( .A0(n3380), .A1(intDY_EWSW[22]), .B0(n3321), .B1(
intDY_EWSW[23]), .Y(n2499) );
NAND2BXLTS U2957 ( .AN(intDY_EWSW[21]), .B(intDX_EWSW[21]), .Y(n2204) );
OA22X1TS U2958 ( .A0(n3368), .A1(intDY_EWSW[14]), .B0(n3316), .B1(
intDY_EWSW[15]), .Y(n2505) );
NAND2BXLTS U2959 ( .AN(intDY_EWSW[13]), .B(intDX_EWSW[13]), .Y(n2205) );
OAI2BB1X1TS U2960 ( .A0N(n3334), .A1N(intDX_EWSW[5]), .B0(intDY_EWSW[4]),
.Y(n2206) );
OAI22X1TS U2961 ( .A0(intDX_EWSW[4]), .A1(n2206), .B0(n3334), .B1(
intDX_EWSW[5]), .Y(n2216) );
OAI2BB1X1TS U2962 ( .A0N(n3453), .A1N(intDX_EWSW[7]), .B0(intDY_EWSW[6]),
.Y(n2207) );
OAI22X1TS U2963 ( .A0(intDX_EWSW[6]), .A1(n2207), .B0(n3453), .B1(
intDX_EWSW[7]), .Y(n2215) );
NAND2BXLTS U2964 ( .AN(intDY_EWSW[2]), .B(intDX_EWSW[2]), .Y(n2210) );
AOI2BB2XLTS U2965 ( .B0(intDX_EWSW[1]), .B1(n3449), .A0N(intDY_EWSW[0]),
.A1N(n2208), .Y(n2209) );
OAI211XLTS U2966 ( .A0(n3372), .A1(intDY_EWSW[3]), .B0(n2210), .C0(n2209),
.Y(n2213) );
OAI21XLTS U2967 ( .A0(intDY_EWSW[3]), .A1(n3372), .B0(intDY_EWSW[2]), .Y(
n2211) );
AOI2BB2XLTS U2968 ( .B0(intDY_EWSW[3]), .B1(n3372), .A0N(intDX_EWSW[2]),
.A1N(n2211), .Y(n2212) );
AOI22X1TS U2969 ( .A0(intDX_EWSW[7]), .A1(n3453), .B0(intDX_EWSW[6]), .B1(
n3352), .Y(n2513) );
OAI32X1TS U2970 ( .A0(n2216), .A1(n2215), .A2(n2214), .B0(n2513), .B1(n2215),
.Y(n2232) );
NAND2BXLTS U2971 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n2220) );
NOR2X1TS U2972 ( .A(n3369), .B(intDY_EWSW[11]), .Y(n2218) );
AOI21X1TS U2973 ( .A0(intDX_EWSW[10]), .A1(n3408), .B0(n2218), .Y(n2223) );
OAI211XLTS U2974 ( .A0(intDY_EWSW[8]), .A1(n3392), .B0(n2220), .C0(n2223),
.Y(n2231) );
OAI21XLTS U2975 ( .A0(intDY_EWSW[13]), .A1(n3384), .B0(intDY_EWSW[12]), .Y(
n2217) );
OAI2BB2XLTS U2976 ( .B0(intDX_EWSW[12]), .B1(n2217), .A0N(intDY_EWSW[13]),
.A1N(n3384), .Y(n2229) );
NOR2XLTS U2977 ( .A(n2218), .B(intDX_EWSW[10]), .Y(n2219) );
AOI22X1TS U2978 ( .A0(intDY_EWSW[11]), .A1(n3369), .B0(intDY_EWSW[10]), .B1(
n2219), .Y(n2225) );
NAND3XLTS U2979 ( .A(n3392), .B(n2220), .C(intDY_EWSW[8]), .Y(n2222) );
AOI21X1TS U2980 ( .A0(n2222), .A1(n2221), .B0(n2233), .Y(n2224) );
OAI2BB2XLTS U2981 ( .B0(n2225), .B1(n2233), .A0N(n2224), .A1N(n2223), .Y(
n2228) );
OAI21XLTS U2982 ( .A0(intDY_EWSW[15]), .A1(n3316), .B0(intDY_EWSW[14]), .Y(
n2226) );
OAI2BB2XLTS U2983 ( .B0(intDX_EWSW[14]), .B1(n2226), .A0N(intDY_EWSW[15]),
.A1N(n3316), .Y(n2227) );
AOI211X1TS U2984 ( .A0(n2505), .A1(n2229), .B0(n2228), .C0(n2227), .Y(n2230)
);
OAI31X1TS U2985 ( .A0(n2233), .A1(n2232), .A2(n2231), .B0(n2230), .Y(n2235)
);
NOR2X1TS U2986 ( .A(n3390), .B(intDY_EWSW[17]), .Y(n2237) );
NAND2BXLTS U2987 ( .AN(intDY_EWSW[19]), .B(intDX_EWSW[19]), .Y(n2239) );
OAI21X1TS U2988 ( .A0(intDY_EWSW[18]), .A1(n3402), .B0(n2239), .Y(n2243) );
NAND3BXLTS U2989 ( .AN(n2242), .B(n2235), .C(n2234), .Y(n2254) );
OAI21XLTS U2990 ( .A0(intDY_EWSW[21]), .A1(n3400), .B0(intDY_EWSW[20]), .Y(
n2236) );
OAI2BB2XLTS U2991 ( .B0(intDX_EWSW[20]), .B1(n2236), .A0N(intDY_EWSW[21]),
.A1N(n3400), .Y(n2247) );
NOR2XLTS U2992 ( .A(n2237), .B(intDX_EWSW[16]), .Y(n2238) );
AOI22X1TS U2993 ( .A0(n2238), .A1(intDY_EWSW[16]), .B0(intDY_EWSW[17]), .B1(
n3390), .Y(n2241) );
AOI32X1TS U2994 ( .A0(n3402), .A1(n2239), .A2(intDY_EWSW[18]), .B0(
intDY_EWSW[19]), .B1(n3325), .Y(n2240) );
OAI32X1TS U2995 ( .A0(n2243), .A1(n2242), .A2(n2241), .B0(n2240), .B1(n2242),
.Y(n2246) );
OAI21XLTS U2996 ( .A0(intDY_EWSW[23]), .A1(n3321), .B0(intDY_EWSW[22]), .Y(
n2244) );
OAI2BB2XLTS U2997 ( .B0(intDX_EWSW[22]), .B1(n2244), .A0N(intDY_EWSW[23]),
.A1N(n3321), .Y(n2245) );
AOI211X1TS U2998 ( .A0(n2499), .A1(n2247), .B0(n2246), .C0(n2245), .Y(n2253)
);
NOR2BX1TS U2999 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n2249) );
OR4X2TS U3000 ( .A(n2251), .B(n2250), .C(n2249), .D(n2248), .Y(n2252) );
AOI32X1TS U3001 ( .A0(n2255), .A1(n2254), .A2(n2253), .B0(n2252), .B1(n2255),
.Y(n2324) );
NOR2XLTS U3002 ( .A(n2256), .B(intDX_EWSW[56]), .Y(n2257) );
AOI22X1TS U3003 ( .A0(intDY_EWSW[57]), .A1(n3393), .B0(intDY_EWSW[56]), .B1(
n2257), .Y(n2261) );
AOI32X1TS U3004 ( .A0(n3326), .A1(n2258), .A2(intDY_EWSW[58]), .B0(
intDY_EWSW[59]), .B1(n3404), .Y(n2259) );
OA21XLTS U3005 ( .A0(n2261), .A1(n2260), .B0(n2259), .Y(n2267) );
NAND3XLTS U3006 ( .A(n3385), .B(n2262), .C(intDY_EWSW[60]), .Y(n2263) );
OAI211XLTS U3007 ( .A0(intDX_EWSW[61]), .A1(n3432), .B0(n2264), .C0(n2263),
.Y(n2265) );
OAI2BB2XLTS U3008 ( .B0(n2268), .B1(n2267), .A0N(n2266), .A1N(n2265), .Y(
n2323) );
NOR2BX1TS U3009 ( .AN(n2269), .B(intDX_EWSW[46]), .Y(n2283) );
AOI22X1TS U3010 ( .A0(intDY_EWSW[45]), .A1(n3388), .B0(intDY_EWSW[44]), .B1(
n2271), .Y(n2280) );
OAI21XLTS U3011 ( .A0(intDY_EWSW[41]), .A1(n3382), .B0(intDY_EWSW[40]), .Y(
n2272) );
OAI2BB2XLTS U3012 ( .B0(intDX_EWSW[40]), .B1(n2272), .A0N(intDY_EWSW[41]),
.A1N(n3382), .Y(n2276) );
OAI21XLTS U3013 ( .A0(intDY_EWSW[43]), .A1(n3318), .B0(intDY_EWSW[42]), .Y(
n2273) );
OAI2BB2XLTS U3014 ( .B0(intDX_EWSW[42]), .B1(n2273), .A0N(intDY_EWSW[43]),
.A1N(n3318), .Y(n2274) );
AOI32X1TS U3015 ( .A0(n2277), .A1(n2276), .A2(n2275), .B0(n2274), .B1(n2277),
.Y(n2278) );
OAI21XLTS U3016 ( .A0(n2280), .A1(n2279), .B0(n2278), .Y(n2282) );
NOR2BX1TS U3017 ( .AN(intDY_EWSW[47]), .B(intDX_EWSW[47]), .Y(n2281) );
AOI211XLTS U3018 ( .A0(intDY_EWSW[46]), .A1(n2283), .B0(n2282), .C0(n2281),
.Y(n2320) );
NAND3XLTS U3019 ( .A(n3381), .B(n2284), .C(intDY_EWSW[36]), .Y(n2285) );
OAI21XLTS U3020 ( .A0(intDX_EWSW[37]), .A1(n3437), .B0(n2285), .Y(n2294) );
INVX2TS U3021 ( .A(n2286), .Y(n2292) );
OAI2BB2XLTS U3022 ( .B0(intDX_EWSW[32]), .B1(n2287), .A0N(intDY_EWSW[33]),
.A1N(n3373), .Y(n2291) );
OAI21XLTS U3023 ( .A0(intDY_EWSW[35]), .A1(n3319), .B0(intDY_EWSW[34]), .Y(
n2288) );
OAI2BB2XLTS U3024 ( .B0(intDX_EWSW[34]), .B1(n2288), .A0N(intDY_EWSW[35]),
.A1N(n3319), .Y(n2289) );
AOI32X1TS U3025 ( .A0(n2292), .A1(n2291), .A2(n2290), .B0(n2289), .B1(n2292),
.Y(n2293) );
OAI2BB1X1TS U3026 ( .A0N(n2295), .A1N(n2294), .B0(n2293), .Y(n2300) );
NOR2BX1TS U3027 ( .AN(intDY_EWSW[39]), .B(intDX_EWSW[39]), .Y(n2299) );
NOR3X1TS U3028 ( .A(n3440), .B(n2296), .C(intDX_EWSW[38]), .Y(n2298) );
INVX2TS U3029 ( .A(n2321), .Y(n2297) );
OAI31X1TS U3030 ( .A0(n2300), .A1(n2299), .A2(n2298), .B0(n2297), .Y(n2318)
);
OAI21XLTS U3031 ( .A0(intDY_EWSW[53]), .A1(n3464), .B0(intDY_EWSW[52]), .Y(
n2301) );
AOI2BB2XLTS U3032 ( .B0(intDY_EWSW[53]), .B1(n3464), .A0N(intDX_EWSW[52]),
.A1N(n2301), .Y(n2303) );
NOR2XLTS U3033 ( .A(n2303), .B(n2302), .Y(n2316) );
INVX2TS U3034 ( .A(n2304), .Y(n2310) );
NOR2XLTS U3035 ( .A(n2305), .B(intDX_EWSW[48]), .Y(n2306) );
AOI22X1TS U3036 ( .A0(intDY_EWSW[49]), .A1(n3391), .B0(intDY_EWSW[48]), .B1(
n2306), .Y(n2309) );
AOI32X1TS U3037 ( .A0(n3322), .A1(n2307), .A2(intDY_EWSW[50]), .B0(
intDY_EWSW[51]), .B1(n3397), .Y(n2308) );
OAI32X1TS U3038 ( .A0(n2311), .A1(n2310), .A2(n2309), .B0(n2308), .B1(n2310),
.Y(n2315) );
OAI21XLTS U3039 ( .A0(intDY_EWSW[55]), .A1(n3465), .B0(intDY_EWSW[54]), .Y(
n2312) );
OAI2BB2XLTS U3040 ( .B0(intDX_EWSW[54]), .B1(n2312), .A0N(intDY_EWSW[55]),
.A1N(n3465), .Y(n2314) );
OAI31X1TS U3041 ( .A0(n2316), .A1(n2315), .A2(n2314), .B0(n2313), .Y(n2317)
);
OAI221XLTS U3042 ( .A0(n2321), .A1(n2320), .B0(n2319), .B1(n2318), .C0(n2317), .Y(n2322) );
AOI211X1TS U3043 ( .A0(n2325), .A1(n2324), .B0(n2323), .C0(n2322), .Y(n2326)
);
CLKBUFX2TS U3044 ( .A(n2327), .Y(n2384) );
AOI22X1TS U3045 ( .A0(intDX_EWSW[10]), .A1(n1827), .B0(DmP_EXP_EWSW[10]),
.B1(n2442), .Y(n2328) );
OAI21XLTS U3046 ( .A0(n3408), .A1(n2365), .B0(n2328), .Y(n1311) );
AOI22X1TS U3047 ( .A0(intDX_EWSW[22]), .A1(n1827), .B0(DmP_EXP_EWSW[22]),
.B1(n2453), .Y(n2329) );
OAI21XLTS U3048 ( .A0(n3451), .A1(n2336), .B0(n2329), .Y(n1287) );
BUFX3TS U3049 ( .A(n2336), .Y(n2842) );
BUFX4TS U3050 ( .A(n2842), .Y(n2871) );
AOI22X1TS U3051 ( .A0(intDX_EWSW[26]), .A1(n2384), .B0(DmP_EXP_EWSW[26]),
.B1(n2442), .Y(n2330) );
OAI21XLTS U3052 ( .A0(n3419), .A1(n2871), .B0(n2330), .Y(n1279) );
BUFX4TS U3053 ( .A(n2842), .Y(n2872) );
AOI22X1TS U3054 ( .A0(intDX_EWSW[30]), .A1(n1827), .B0(DmP_EXP_EWSW[30]),
.B1(n2442), .Y(n2331) );
AOI22X1TS U3055 ( .A0(DmP_EXP_EWSW[57]), .A1(n2442), .B0(intDX_EWSW[57]),
.B1(n1827), .Y(n2332) );
OAI21XLTS U3056 ( .A0(n3409), .A1(n2872), .B0(n2332), .Y(n1222) );
AOI22X1TS U3057 ( .A0(intDX_EWSW[28]), .A1(n2384), .B0(DmP_EXP_EWSW[28]),
.B1(n2386), .Y(n2333) );
OAI21XLTS U3058 ( .A0(n3420), .A1(n2872), .B0(n2333), .Y(n1275) );
AOI22X1TS U3059 ( .A0(intDX_EWSW[7]), .A1(n1827), .B0(DmP_EXP_EWSW[7]), .B1(
n2386), .Y(n2334) );
OAI21XLTS U3060 ( .A0(n3453), .A1(n2365), .B0(n2334), .Y(n1317) );
AOI22X1TS U3061 ( .A0(intDX_EWSW[8]), .A1(n1827), .B0(DmP_EXP_EWSW[8]), .B1(
n2453), .Y(n2335) );
OAI21XLTS U3062 ( .A0(n3414), .A1(n2365), .B0(n2335), .Y(n1315) );
INVX4TS U3063 ( .A(n2336), .Y(n2431) );
INVX2TS U3064 ( .A(n2337), .Y(n1227) );
INVX2TS U3065 ( .A(n2338), .Y(n1556) );
BUFX4TS U3066 ( .A(n1827), .Y(n2373) );
AOI22X1TS U3067 ( .A0(intDX_EWSW[15]), .A1(n2373), .B0(DmP_EXP_EWSW[15]),
.B1(n2442), .Y(n2339) );
OAI21XLTS U3068 ( .A0(n3346), .A1(n2365), .B0(n2339), .Y(n1301) );
BUFX4TS U3069 ( .A(n1827), .Y(n2380) );
AOI22X1TS U3070 ( .A0(intDX_EWSW[14]), .A1(n2380), .B0(DmP_EXP_EWSW[14]),
.B1(n2453), .Y(n2340) );
OAI21XLTS U3071 ( .A0(n3450), .A1(n2365), .B0(n2340), .Y(n1303) );
AOI22X1TS U3072 ( .A0(intDX_EWSW[12]), .A1(n2380), .B0(DmP_EXP_EWSW[12]),
.B1(n2453), .Y(n2341) );
OAI21XLTS U3073 ( .A0(n3415), .A1(n2365), .B0(n2341), .Y(n1307) );
AOI22X1TS U3074 ( .A0(intDX_EWSW[51]), .A1(n2373), .B0(DmP_EXP_EWSW[51]),
.B1(n2529), .Y(n2342) );
OAI21XLTS U3075 ( .A0(n3350), .A1(n2842), .B0(n2342), .Y(n1229) );
AOI22X1TS U3076 ( .A0(intDX_EWSW[49]), .A1(n2373), .B0(DmP_EXP_EWSW[49]),
.B1(n2529), .Y(n2343) );
OAI21XLTS U3077 ( .A0(n3430), .A1(n2842), .B0(n2343), .Y(n1233) );
AOI22X1TS U3078 ( .A0(intDX_EWSW[50]), .A1(n2373), .B0(DmP_EXP_EWSW[50]),
.B1(n2529), .Y(n2344) );
OAI21XLTS U3079 ( .A0(n3447), .A1(n2842), .B0(n2344), .Y(n1231) );
AOI22X1TS U3080 ( .A0(intDX_EWSW[35]), .A1(n2380), .B0(DmP_EXP_EWSW[35]),
.B1(n2386), .Y(n2345) );
OAI21XLTS U3081 ( .A0(n3342), .A1(n2872), .B0(n2345), .Y(n1261) );
AOI22X1TS U3082 ( .A0(intDX_EWSW[42]), .A1(n2373), .B0(DmP_EXP_EWSW[42]),
.B1(n2453), .Y(n2346) );
OAI21XLTS U3083 ( .A0(n3444), .A1(n2871), .B0(n2346), .Y(n1247) );
AOI22X1TS U3084 ( .A0(intDX_EWSW[34]), .A1(n2380), .B0(DmP_EXP_EWSW[34]),
.B1(n2386), .Y(n2347) );
OAI21XLTS U3085 ( .A0(n3441), .A1(n2872), .B0(n2347), .Y(n1263) );
AOI22X1TS U3086 ( .A0(intDX_EWSW[45]), .A1(n2373), .B0(DmP_EXP_EWSW[45]),
.B1(n2529), .Y(n2348) );
OAI21XLTS U3087 ( .A0(n3439), .A1(n2871), .B0(n2348), .Y(n1241) );
AOI22X1TS U3088 ( .A0(intDX_EWSW[41]), .A1(n2380), .B0(DmP_EXP_EWSW[41]),
.B1(n2386), .Y(n2349) );
OAI21XLTS U3089 ( .A0(n3343), .A1(n2871), .B0(n2349), .Y(n1249) );
AOI22X1TS U3090 ( .A0(intDX_EWSW[31]), .A1(n2380), .B0(DmP_EXP_EWSW[31]),
.B1(n2386), .Y(n2350) );
OAI21XLTS U3091 ( .A0(n3348), .A1(n2872), .B0(n2350), .Y(n1269) );
AOI22X1TS U3092 ( .A0(intDX_EWSW[43]), .A1(n2373), .B0(DmP_EXP_EWSW[43]),
.B1(n2442), .Y(n2351) );
OAI21XLTS U3093 ( .A0(n3344), .A1(n2871), .B0(n2351), .Y(n1245) );
AOI22X1TS U3094 ( .A0(intDX_EWSW[29]), .A1(n2373), .B0(DmP_EXP_EWSW[29]),
.B1(n2386), .Y(n2352) );
OAI21XLTS U3095 ( .A0(n3339), .A1(n2872), .B0(n2352), .Y(n1273) );
AOI22X1TS U3096 ( .A0(intDX_EWSW[25]), .A1(n2380), .B0(DmP_EXP_EWSW[25]),
.B1(n2845), .Y(n2353) );
OAI21XLTS U3097 ( .A0(n3337), .A1(n2871), .B0(n2353), .Y(n1281) );
AOI22X1TS U3098 ( .A0(intDX_EWSW[33]), .A1(n2380), .B0(DmP_EXP_EWSW[33]),
.B1(n2386), .Y(n2354) );
OAI21XLTS U3099 ( .A0(n3341), .A1(n2872), .B0(n2354), .Y(n1265) );
AOI22X1TS U3100 ( .A0(intDX_EWSW[27]), .A1(n2373), .B0(DmP_EXP_EWSW[27]),
.B1(n2453), .Y(n2355) );
OAI21XLTS U3101 ( .A0(n3338), .A1(n2872), .B0(n2355), .Y(n1277) );
AOI22X1TS U3102 ( .A0(intDX_EWSW[36]), .A1(n2380), .B0(DmP_EXP_EWSW[36]),
.B1(n2386), .Y(n2356) );
OAI21XLTS U3103 ( .A0(n3442), .A1(n2871), .B0(n2356), .Y(n1259) );
AOI22X1TS U3104 ( .A0(intDX_EWSW[46]), .A1(n2373), .B0(DmP_EXP_EWSW[46]),
.B1(n1933), .Y(n2357) );
OAI21XLTS U3105 ( .A0(n3446), .A1(n2871), .B0(n2357), .Y(n1239) );
AOI22X1TS U3106 ( .A0(intDX_EWSW[18]), .A1(n2373), .B0(DmP_EXP_EWSW[18]),
.B1(n2442), .Y(n2358) );
OAI21XLTS U3107 ( .A0(n3416), .A1(n2872), .B0(n2358), .Y(n1295) );
AOI22X1TS U3108 ( .A0(intDX_EWSW[19]), .A1(n2380), .B0(DmP_EXP_EWSW[19]),
.B1(n2845), .Y(n2359) );
OAI21XLTS U3109 ( .A0(n3336), .A1(n2871), .B0(n2359), .Y(n1293) );
AOI22X1TS U3110 ( .A0(intDX_EWSW[17]), .A1(n2380), .B0(DmP_EXP_EWSW[17]),
.B1(n2453), .Y(n2360) );
OAI21XLTS U3111 ( .A0(n3335), .A1(n2872), .B0(n2360), .Y(n1297) );
AOI22X1TS U3112 ( .A0(intDX_EWSW[21]), .A1(n2373), .B0(DmP_EXP_EWSW[21]),
.B1(n1933), .Y(n2361) );
OAI21XLTS U3113 ( .A0(n3411), .A1(n2872), .B0(n2361), .Y(n1289) );
AOI22X1TS U3114 ( .A0(intDX_EWSW[20]), .A1(n2373), .B0(DmP_EXP_EWSW[20]),
.B1(n2529), .Y(n2362) );
OAI21XLTS U3115 ( .A0(n3417), .A1(n2871), .B0(n2362), .Y(n1291) );
AOI22X1TS U3116 ( .A0(intDX_EWSW[23]), .A1(n2373), .B0(DmP_EXP_EWSW[23]),
.B1(n2453), .Y(n2363) );
AOI22X1TS U3117 ( .A0(intDX_EWSW[16]), .A1(n2380), .B0(DmP_EXP_EWSW[16]),
.B1(n2845), .Y(n2364) );
OAI21XLTS U3118 ( .A0(n3425), .A1(n2365), .B0(n2364), .Y(n1299) );
AOI22X1TS U3119 ( .A0(intDX_EWSW[24]), .A1(n2380), .B0(DmP_EXP_EWSW[24]),
.B1(n2529), .Y(n2366) );
OAI21XLTS U3120 ( .A0(n3418), .A1(n2872), .B0(n2366), .Y(n1283) );
AOI22X1TS U3121 ( .A0(intDX_EWSW[48]), .A1(n2373), .B0(DmP_EXP_EWSW[48]),
.B1(n2453), .Y(n2367) );
OAI21XLTS U3122 ( .A0(n3422), .A1(n2842), .B0(n2367), .Y(n1235) );
AOI22X1TS U3123 ( .A0(intDX_EWSW[32]), .A1(n2380), .B0(DmP_EXP_EWSW[32]),
.B1(n2386), .Y(n2368) );
OAI21XLTS U3124 ( .A0(n3421), .A1(n2872), .B0(n2368), .Y(n1267) );
AOI22X1TS U3125 ( .A0(intDX_EWSW[39]), .A1(n2373), .B0(DmP_EXP_EWSW[39]),
.B1(n2386), .Y(n2369) );
OAI21XLTS U3126 ( .A0(n3438), .A1(n2871), .B0(n2369), .Y(n1253) );
AOI22X1TS U3127 ( .A0(intDX_EWSW[47]), .A1(n2373), .B0(DmP_EXP_EWSW[47]),
.B1(n2442), .Y(n2370) );
OAI21XLTS U3128 ( .A0(n3349), .A1(n2871), .B0(n2370), .Y(n1237) );
AOI22X1TS U3129 ( .A0(intDX_EWSW[40]), .A1(n2380), .B0(DmP_EXP_EWSW[40]),
.B1(n2386), .Y(n2371) );
OAI21XLTS U3130 ( .A0(n3443), .A1(n2871), .B0(n2371), .Y(n1251) );
AOI22X1TS U3131 ( .A0(intDX_EWSW[38]), .A1(n2380), .B0(DmP_EXP_EWSW[38]),
.B1(n2386), .Y(n2372) );
OAI21XLTS U3132 ( .A0(n3440), .A1(n2871), .B0(n2372), .Y(n1255) );
AOI22X1TS U3133 ( .A0(intDX_EWSW[44]), .A1(n2373), .B0(DmP_EXP_EWSW[44]),
.B1(n1933), .Y(n2374) );
AOI22X1TS U3134 ( .A0(intDX_EWSW[37]), .A1(n2380), .B0(DmP_EXP_EWSW[37]),
.B1(n2386), .Y(n2375) );
AOI22X1TS U3135 ( .A0(intDX_EWSW[5]), .A1(n1827), .B0(DmP_EXP_EWSW[5]), .B1(
n2453), .Y(n2376) );
OAI21XLTS U3136 ( .A0(n3334), .A1(n2365), .B0(n2376), .Y(n1321) );
AOI22X1TS U3137 ( .A0(intDX_EWSW[4]), .A1(n1827), .B0(DmP_EXP_EWSW[4]), .B1(
n2442), .Y(n2377) );
OAI21XLTS U3138 ( .A0(n3413), .A1(n2365), .B0(n2377), .Y(n1323) );
AOI22X1TS U3139 ( .A0(intDX_EWSW[1]), .A1(n1827), .B0(DmP_EXP_EWSW[1]), .B1(
n2453), .Y(n2378) );
OAI21XLTS U3140 ( .A0(n3449), .A1(n2872), .B0(n2378), .Y(n1329) );
AOI22X1TS U3141 ( .A0(intDX_EWSW[9]), .A1(n1827), .B0(DmP_EXP_EWSW[9]), .B1(
n2442), .Y(n2379) );
OAI21XLTS U3142 ( .A0(n3407), .A1(n2365), .B0(n2379), .Y(n1313) );
AOI22X1TS U3143 ( .A0(intDX_EWSW[13]), .A1(n2380), .B0(DmP_EXP_EWSW[13]),
.B1(n2453), .Y(n2381) );
OAI21XLTS U3144 ( .A0(n3410), .A1(n2365), .B0(n2381), .Y(n1305) );
AOI22X1TS U3145 ( .A0(intDX_EWSW[11]), .A1(n1827), .B0(DmP_EXP_EWSW[11]),
.B1(n2442), .Y(n2382) );
OAI21XLTS U3146 ( .A0(n3345), .A1(n2365), .B0(n2382), .Y(n1309) );
AOI22X1TS U3147 ( .A0(intDX_EWSW[6]), .A1(n2384), .B0(DmP_EXP_EWSW[6]), .B1(
n2442), .Y(n2383) );
OAI21XLTS U3148 ( .A0(n3352), .A1(n2365), .B0(n2383), .Y(n1319) );
AOI22X1TS U3149 ( .A0(intDX_EWSW[3]), .A1(n2384), .B0(DmP_EXP_EWSW[3]), .B1(
n2442), .Y(n2385) );
OAI21XLTS U3150 ( .A0(n3331), .A1(n2336), .B0(n2385), .Y(n1325) );
AOI22X1TS U3151 ( .A0(intDX_EWSW[0]), .A1(n1827), .B0(DmP_EXP_EWSW[0]), .B1(
n2453), .Y(n2387) );
OAI21XLTS U3152 ( .A0(n3333), .A1(n2336), .B0(n2387), .Y(n1331) );
AOI22X1TS U3153 ( .A0(intDX_EWSW[2]), .A1(n1827), .B0(DmP_EXP_EWSW[2]), .B1(
n2529), .Y(n2388) );
OAI21XLTS U3154 ( .A0(n3412), .A1(n2336), .B0(n2388), .Y(n1327) );
CLKBUFX2TS U3155 ( .A(n1827), .Y(n2395) );
AOI22X1TS U3156 ( .A0(intDX_EWSW[58]), .A1(n2449), .B0(DMP_EXP_EWSW[58]),
.B1(n2529), .Y(n2389) );
OAI21XLTS U3157 ( .A0(n3424), .A1(n2874), .B0(n2389), .Y(n1550) );
AOI22X1TS U3158 ( .A0(intDX_EWSW[60]), .A1(n2449), .B0(DMP_EXP_EWSW[60]),
.B1(n2529), .Y(n2390) );
OAI21XLTS U3159 ( .A0(n3423), .A1(n2874), .B0(n2390), .Y(n1548) );
AOI22X1TS U3160 ( .A0(intDX_EWSW[62]), .A1(n2456), .B0(DMP_EXP_EWSW[62]),
.B1(n2845), .Y(n2391) );
OAI21XLTS U3161 ( .A0(n3448), .A1(n2874), .B0(n2391), .Y(n1546) );
AOI22X1TS U3162 ( .A0(intDX_EWSW[0]), .A1(n2431), .B0(DMP_EXP_EWSW[0]), .B1(
n1933), .Y(n2392) );
INVX4TS U3163 ( .A(n2395), .Y(n2433) );
AOI22X1TS U3164 ( .A0(intDX_EWSW[7]), .A1(n2435), .B0(DMP_EXP_EWSW[7]), .B1(
n1933), .Y(n2393) );
OAI21XLTS U3165 ( .A0(n3453), .A1(n2433), .B0(n2393), .Y(n1601) );
INVX4TS U3166 ( .A(n2395), .Y(n2451) );
CLKBUFX2TS U3167 ( .A(n2529), .Y(n2426) );
AOI22X1TS U3168 ( .A0(intDX_EWSW[10]), .A1(n2435), .B0(DMP_EXP_EWSW[10]),
.B1(n2455), .Y(n2394) );
OAI21XLTS U3169 ( .A0(n3408), .A1(n2451), .B0(n2394), .Y(n1598) );
INVX4TS U3170 ( .A(n2395), .Y(n2458) );
AOI22X1TS U3171 ( .A0(intDX_EWSW[31]), .A1(n2456), .B0(DMP_EXP_EWSW[31]),
.B1(n2455), .Y(n2396) );
OAI21XLTS U3172 ( .A0(n3348), .A1(n2458), .B0(n2396), .Y(n1577) );
AOI22X1TS U3173 ( .A0(intDX_EWSW[38]), .A1(n2456), .B0(DMP_EXP_EWSW[38]),
.B1(n2453), .Y(n2397) );
OAI21XLTS U3174 ( .A0(n3440), .A1(n2458), .B0(n2397), .Y(n1570) );
AOI22X1TS U3175 ( .A0(intDX_EWSW[30]), .A1(n2431), .B0(DMP_EXP_EWSW[30]),
.B1(n2455), .Y(n2398) );
OAI21XLTS U3176 ( .A0(n3452), .A1(n2458), .B0(n2398), .Y(n1578) );
AOI22X1TS U3177 ( .A0(intDX_EWSW[4]), .A1(n2435), .B0(DMP_EXP_EWSW[4]), .B1(
n1933), .Y(n2399) );
OAI21XLTS U3178 ( .A0(n3413), .A1(n2451), .B0(n2399), .Y(n1604) );
AOI22X1TS U3179 ( .A0(intDX_EWSW[16]), .A1(n2435), .B0(DMP_EXP_EWSW[16]),
.B1(n2455), .Y(n2400) );
OAI21XLTS U3180 ( .A0(n3425), .A1(n2433), .B0(n2400), .Y(n1592) );
AOI22X1TS U3181 ( .A0(intDX_EWSW[37]), .A1(n2456), .B0(DMP_EXP_EWSW[37]),
.B1(n2455), .Y(n2401) );
OAI21XLTS U3182 ( .A0(n3437), .A1(n2458), .B0(n2401), .Y(n1571) );
AOI22X1TS U3183 ( .A0(intDX_EWSW[61]), .A1(n2449), .B0(DMP_EXP_EWSW[61]),
.B1(n2529), .Y(n2402) );
OAI21XLTS U3184 ( .A0(n3432), .A1(n2451), .B0(n2402), .Y(n1547) );
AOI22X1TS U3185 ( .A0(intDX_EWSW[1]), .A1(n2435), .B0(DMP_EXP_EWSW[1]), .B1(
n1933), .Y(n2403) );
OAI21XLTS U3186 ( .A0(n3449), .A1(n2458), .B0(n2403), .Y(n1607) );
AOI22X1TS U3187 ( .A0(intDX_EWSW[23]), .A1(n2431), .B0(DMP_EXP_EWSW[23]),
.B1(n2455), .Y(n2404) );
OAI21XLTS U3188 ( .A0(n3347), .A1(n2433), .B0(n2404), .Y(n1585) );
AOI22X1TS U3189 ( .A0(intDX_EWSW[5]), .A1(n2435), .B0(DMP_EXP_EWSW[5]), .B1(
n1933), .Y(n2405) );
OAI21XLTS U3190 ( .A0(n3334), .A1(n2458), .B0(n2405), .Y(n1603) );
AOI22X1TS U3191 ( .A0(intDX_EWSW[59]), .A1(n2449), .B0(DMP_EXP_EWSW[59]),
.B1(n2453), .Y(n2406) );
AOI22X1TS U3192 ( .A0(intDX_EWSW[22]), .A1(n2431), .B0(DMP_EXP_EWSW[22]),
.B1(n2455), .Y(n2407) );
OAI21XLTS U3193 ( .A0(n3451), .A1(n2433), .B0(n2407), .Y(n1586) );
AOI22X1TS U3194 ( .A0(intDX_EWSW[14]), .A1(n2435), .B0(DMP_EXP_EWSW[14]),
.B1(n2386), .Y(n2408) );
OAI21XLTS U3195 ( .A0(n3450), .A1(n2458), .B0(n2408), .Y(n1594) );
AOI22X1TS U3196 ( .A0(intDX_EWSW[15]), .A1(n2435), .B0(DMP_EXP_EWSW[15]),
.B1(n2455), .Y(n2409) );
OAI21XLTS U3197 ( .A0(n3346), .A1(n2433), .B0(n2409), .Y(n1593) );
AOI22X1TS U3198 ( .A0(intDX_EWSW[44]), .A1(n2449), .B0(DMP_EXP_EWSW[44]),
.B1(n2442), .Y(n2410) );
OAI21XLTS U3199 ( .A0(n3445), .A1(n2451), .B0(n2410), .Y(n1564) );
AOI22X1TS U3200 ( .A0(intDX_EWSW[48]), .A1(n2449), .B0(DMP_EXP_EWSW[48]),
.B1(n2442), .Y(n2411) );
OAI21XLTS U3201 ( .A0(n3422), .A1(n2451), .B0(n2411), .Y(n1560) );
AOI22X1TS U3202 ( .A0(intDX_EWSW[6]), .A1(n2435), .B0(DMP_EXP_EWSW[6]), .B1(
n1933), .Y(n2412) );
OAI21XLTS U3203 ( .A0(n3352), .A1(n2433), .B0(n2412), .Y(n1602) );
AOI22X1TS U3204 ( .A0(intDX_EWSW[11]), .A1(n2435), .B0(DMP_EXP_EWSW[11]),
.B1(n2455), .Y(n2413) );
OAI21XLTS U3205 ( .A0(n3345), .A1(n2458), .B0(n2413), .Y(n1597) );
AOI22X1TS U3206 ( .A0(intDX_EWSW[3]), .A1(n2435), .B0(DMP_EXP_EWSW[3]), .B1(
n1933), .Y(n2414) );
OAI21XLTS U3207 ( .A0(n3331), .A1(n2433), .B0(n2414), .Y(n1605) );
AOI22X1TS U3208 ( .A0(intDX_EWSW[2]), .A1(n2435), .B0(DMP_EXP_EWSW[2]), .B1(
n1933), .Y(n2415) );
OAI21XLTS U3209 ( .A0(n3412), .A1(n2451), .B0(n2415), .Y(n1606) );
AOI22X1TS U3210 ( .A0(intDX_EWSW[8]), .A1(n2435), .B0(DMP_EXP_EWSW[8]), .B1(
n2426), .Y(n2416) );
OAI21XLTS U3211 ( .A0(n3414), .A1(n2451), .B0(n2416), .Y(n1600) );
AOI22X1TS U3212 ( .A0(intDX_EWSW[13]), .A1(n2435), .B0(DMP_EXP_EWSW[13]),
.B1(n2426), .Y(n2417) );
AOI22X1TS U3213 ( .A0(intDX_EWSW[12]), .A1(n2435), .B0(DMP_EXP_EWSW[12]),
.B1(n2426), .Y(n2418) );
OAI21XLTS U3214 ( .A0(n3415), .A1(n2458), .B0(n2418), .Y(n1596) );
AOI22X1TS U3215 ( .A0(intDX_EWSW[18]), .A1(n2435), .B0(DMP_EXP_EWSW[18]),
.B1(n2455), .Y(n2419) );
OAI21XLTS U3216 ( .A0(n3416), .A1(n2433), .B0(n2419), .Y(n1590) );
AOI22X1TS U3217 ( .A0(intDX_EWSW[9]), .A1(n2435), .B0(DMP_EXP_EWSW[9]), .B1(
n1933), .Y(n2420) );
OAI21XLTS U3218 ( .A0(n3407), .A1(n2451), .B0(n2420), .Y(n1599) );
AOI22X1TS U3219 ( .A0(intDX_EWSW[27]), .A1(n2431), .B0(DMP_EXP_EWSW[27]),
.B1(n2455), .Y(n2421) );
AOI22X1TS U3220 ( .A0(intDX_EWSW[17]), .A1(n2435), .B0(DMP_EXP_EWSW[17]),
.B1(n2455), .Y(n2422) );
OAI21XLTS U3221 ( .A0(n3335), .A1(n2433), .B0(n2422), .Y(n1591) );
AOI22X1TS U3222 ( .A0(intDX_EWSW[19]), .A1(n2431), .B0(DMP_EXP_EWSW[19]),
.B1(n2455), .Y(n2423) );
OAI21XLTS U3223 ( .A0(n3336), .A1(n2433), .B0(n2423), .Y(n1589) );
AOI22X1TS U3224 ( .A0(intDX_EWSW[24]), .A1(n2431), .B0(DMP_EXP_EWSW[24]),
.B1(n2455), .Y(n2424) );
OAI21XLTS U3225 ( .A0(n3418), .A1(n2433), .B0(n2424), .Y(n1584) );
AOI22X1TS U3226 ( .A0(intDX_EWSW[20]), .A1(n2431), .B0(DMP_EXP_EWSW[20]),
.B1(n2426), .Y(n2425) );
OAI21XLTS U3227 ( .A0(n3417), .A1(n2433), .B0(n2425), .Y(n1588) );
AOI22X1TS U3228 ( .A0(intDX_EWSW[21]), .A1(n2431), .B0(DMP_EXP_EWSW[21]),
.B1(n2426), .Y(n2427) );
OAI21XLTS U3229 ( .A0(n3411), .A1(n2433), .B0(n2427), .Y(n1587) );
AOI22X1TS U3230 ( .A0(intDX_EWSW[29]), .A1(n2431), .B0(DMP_EXP_EWSW[29]),
.B1(n2455), .Y(n2428) );
OAI21XLTS U3231 ( .A0(n3339), .A1(n2458), .B0(n2428), .Y(n1579) );
AOI22X1TS U3232 ( .A0(intDX_EWSW[28]), .A1(n2431), .B0(DMP_EXP_EWSW[28]),
.B1(n2455), .Y(n2429) );
OAI21XLTS U3233 ( .A0(n3420), .A1(n2433), .B0(n2429), .Y(n1580) );
AOI22X1TS U3234 ( .A0(intDX_EWSW[25]), .A1(n2431), .B0(DMP_EXP_EWSW[25]),
.B1(n2529), .Y(n2430) );
OAI21XLTS U3235 ( .A0(n3337), .A1(n2433), .B0(n2430), .Y(n1583) );
AOI22X1TS U3236 ( .A0(intDX_EWSW[26]), .A1(n2431), .B0(DMP_EXP_EWSW[26]),
.B1(n2455), .Y(n2432) );
OAI21XLTS U3237 ( .A0(n3419), .A1(n2433), .B0(n2432), .Y(n1582) );
AOI22X1TS U3238 ( .A0(intDX_EWSW[32]), .A1(n2456), .B0(DMP_EXP_EWSW[32]),
.B1(n2455), .Y(n2434) );
OAI21XLTS U3239 ( .A0(n3421), .A1(n2458), .B0(n2434), .Y(n1576) );
AOI22X1TS U3240 ( .A0(DMP_EXP_EWSW[57]), .A1(n2386), .B0(intDX_EWSW[57]),
.B1(n2435), .Y(n2436) );
OAI21XLTS U3241 ( .A0(n3409), .A1(n2451), .B0(n2436), .Y(n1551) );
AOI22X1TS U3242 ( .A0(intDX_EWSW[49]), .A1(n2449), .B0(DMP_EXP_EWSW[49]),
.B1(n1933), .Y(n2437) );
OAI21XLTS U3243 ( .A0(n3430), .A1(n2451), .B0(n2437), .Y(n1559) );
AOI22X1TS U3244 ( .A0(intDX_EWSW[41]), .A1(n2456), .B0(DMP_EXP_EWSW[41]),
.B1(n2453), .Y(n2438) );
AOI22X1TS U3245 ( .A0(intDX_EWSW[46]), .A1(n2449), .B0(DMP_EXP_EWSW[46]),
.B1(n2442), .Y(n2439) );
OAI21XLTS U3246 ( .A0(n3446), .A1(n2451), .B0(n2439), .Y(n1562) );
AOI22X1TS U3247 ( .A0(intDX_EWSW[39]), .A1(n2456), .B0(DMP_EXP_EWSW[39]),
.B1(n2442), .Y(n2440) );
OAI21XLTS U3248 ( .A0(n3438), .A1(n2458), .B0(n2440), .Y(n1569) );
AOI22X1TS U3249 ( .A0(intDX_EWSW[42]), .A1(n2456), .B0(DMP_EXP_EWSW[42]),
.B1(n1933), .Y(n2441) );
OAI21XLTS U3250 ( .A0(n3444), .A1(n2451), .B0(n2441), .Y(n1566) );
AOI22X1TS U3251 ( .A0(intDX_EWSW[50]), .A1(n2449), .B0(DMP_EXP_EWSW[50]),
.B1(n2529), .Y(n2443) );
OAI21XLTS U3252 ( .A0(n3447), .A1(n2458), .B0(n2443), .Y(n1558) );
AOI22X1TS U3253 ( .A0(intDX_EWSW[33]), .A1(n2456), .B0(DMP_EXP_EWSW[33]),
.B1(n2845), .Y(n2444) );
OAI21XLTS U3254 ( .A0(n3341), .A1(n2458), .B0(n2444), .Y(n1575) );
AOI22X1TS U3255 ( .A0(intDX_EWSW[43]), .A1(n2449), .B0(DMP_EXP_EWSW[43]),
.B1(n2529), .Y(n2445) );
OAI21XLTS U3256 ( .A0(n3344), .A1(n2451), .B0(n2445), .Y(n1565) );
AOI22X1TS U3257 ( .A0(intDX_EWSW[51]), .A1(n2449), .B0(DMP_EXP_EWSW[51]),
.B1(n2529), .Y(n2446) );
OAI21XLTS U3258 ( .A0(n3350), .A1(n2451), .B0(n2446), .Y(n1557) );
AOI22X1TS U3259 ( .A0(intDX_EWSW[35]), .A1(n2456), .B0(DMP_EXP_EWSW[35]),
.B1(n2455), .Y(n2447) );
OAI21XLTS U3260 ( .A0(n3342), .A1(n2458), .B0(n2447), .Y(n1573) );
AOI22X1TS U3261 ( .A0(intDX_EWSW[47]), .A1(n2449), .B0(DMP_EXP_EWSW[47]),
.B1(n2529), .Y(n2448) );
OAI21XLTS U3262 ( .A0(n3349), .A1(n2451), .B0(n2448), .Y(n1561) );
AOI22X1TS U3263 ( .A0(intDX_EWSW[45]), .A1(n2456), .B0(DMP_EXP_EWSW[45]),
.B1(n2453), .Y(n2450) );
OAI21XLTS U3264 ( .A0(n3439), .A1(n2451), .B0(n2450), .Y(n1563) );
AOI22X1TS U3265 ( .A0(intDX_EWSW[36]), .A1(n2456), .B0(DMP_EXP_EWSW[36]),
.B1(n2442), .Y(n2452) );
OAI21XLTS U3266 ( .A0(n3442), .A1(n2458), .B0(n2452), .Y(n1572) );
AOI22X1TS U3267 ( .A0(intDX_EWSW[40]), .A1(n2449), .B0(DMP_EXP_EWSW[40]),
.B1(n2529), .Y(n2454) );
OAI21XLTS U3268 ( .A0(n3443), .A1(n2458), .B0(n2454), .Y(n1568) );
AOI22X1TS U3269 ( .A0(intDX_EWSW[34]), .A1(n2456), .B0(DMP_EXP_EWSW[34]),
.B1(n2455), .Y(n2457) );
OAI21XLTS U3270 ( .A0(n3441), .A1(n2458), .B0(n2457), .Y(n1574) );
AOI22X1TS U3271 ( .A0(n3345), .A1(intDX_EWSW[11]), .B0(n3430), .B1(
intDX_EWSW[49]), .Y(n2459) );
OAI221XLTS U3272 ( .A0(n3345), .A1(intDX_EWSW[11]), .B0(n3430), .B1(
intDX_EWSW[49]), .C0(n2459), .Y(n2460) );
AOI221X1TS U3273 ( .A0(intDY_EWSW[1]), .A1(n3433), .B0(n3449), .B1(
intDX_EWSW[1]), .C0(n2460), .Y(n2474) );
OAI22X1TS U3274 ( .A0(n3434), .A1(intDX_EWSW[52]), .B0(n3313), .B1(
intDX_EWSW[53]), .Y(n2461) );
OAI22X1TS U3275 ( .A0(n3447), .A1(intDX_EWSW[50]), .B0(n3350), .B1(
intDX_EWSW[51]), .Y(n2462) );
AOI221X1TS U3276 ( .A0(n3447), .A1(intDX_EWSW[50]), .B0(intDX_EWSW[51]),
.B1(n3350), .C0(n2462), .Y(n2472) );
AOI22X1TS U3277 ( .A0(n3409), .A1(intDX_EWSW[57]), .B0(n3310), .B1(
intDX_EWSW[56]), .Y(n2463) );
AOI22X1TS U3278 ( .A0(n3309), .A1(intDX_EWSW[55]), .B0(n3312), .B1(
intDX_EWSW[54]), .Y(n2464) );
OAI221XLTS U3279 ( .A0(n3309), .A1(intDX_EWSW[55]), .B0(n3312), .B1(
intDX_EWSW[54]), .C0(n2464), .Y(n2469) );
AOI22X1TS U3280 ( .A0(n3432), .A1(intDX_EWSW[61]), .B0(n3423), .B1(
intDX_EWSW[60]), .Y(n2465) );
AOI22X1TS U3281 ( .A0(n3340), .A1(intDX_EWSW[59]), .B0(n3424), .B1(
intDX_EWSW[58]), .Y(n2466) );
OAI221XLTS U3282 ( .A0(n3340), .A1(intDX_EWSW[59]), .B0(n3424), .B1(
intDX_EWSW[58]), .C0(n2466), .Y(n2467) );
NOR4X1TS U3283 ( .A(n2470), .B(n2469), .C(n2468), .D(n2467), .Y(n2471) );
NAND4XLTS U3284 ( .A(n2474), .B(n2473), .C(n2472), .D(n2471), .Y(n2528) );
OAI22X1TS U3285 ( .A0(n3444), .A1(intDX_EWSW[42]), .B0(n3344), .B1(
intDX_EWSW[43]), .Y(n2475) );
AOI221X1TS U3286 ( .A0(n3444), .A1(intDX_EWSW[42]), .B0(intDX_EWSW[43]),
.B1(n3344), .C0(n2475), .Y(n2482) );
OAI22X1TS U3287 ( .A0(n3443), .A1(intDX_EWSW[40]), .B0(n3343), .B1(
intDX_EWSW[41]), .Y(n2476) );
AOI221X1TS U3288 ( .A0(n3443), .A1(intDX_EWSW[40]), .B0(intDX_EWSW[41]),
.B1(n3343), .C0(n2476), .Y(n2481) );
OAI22X1TS U3289 ( .A0(n3446), .A1(intDX_EWSW[46]), .B0(n3349), .B1(
intDX_EWSW[47]), .Y(n2477) );
AOI221X1TS U3290 ( .A0(n3446), .A1(intDX_EWSW[46]), .B0(intDX_EWSW[47]),
.B1(n3349), .C0(n2477), .Y(n2480) );
OAI22X1TS U3291 ( .A0(n3445), .A1(intDX_EWSW[44]), .B0(n3439), .B1(
intDX_EWSW[45]), .Y(n2478) );
AOI221X1TS U3292 ( .A0(n3445), .A1(intDX_EWSW[44]), .B0(intDX_EWSW[45]),
.B1(n3439), .C0(n2478), .Y(n2479) );
NAND4XLTS U3293 ( .A(n2482), .B(n2481), .C(n2480), .D(n2479), .Y(n2527) );
OAI22X1TS U3294 ( .A0(n3441), .A1(intDX_EWSW[34]), .B0(n3342), .B1(
intDX_EWSW[35]), .Y(n2483) );
AOI221X1TS U3295 ( .A0(n3441), .A1(intDX_EWSW[34]), .B0(intDX_EWSW[35]),
.B1(n3342), .C0(n2483), .Y(n2490) );
OAI22X1TS U3296 ( .A0(n3448), .A1(intDX_EWSW[62]), .B0(n3341), .B1(
intDX_EWSW[33]), .Y(n2484) );
AOI221X1TS U3297 ( .A0(n3448), .A1(intDX_EWSW[62]), .B0(intDX_EWSW[33]),
.B1(n3341), .C0(n2484), .Y(n2489) );
OAI22X1TS U3298 ( .A0(n3440), .A1(intDX_EWSW[38]), .B0(n3438), .B1(
intDX_EWSW[39]), .Y(n2485) );
OAI22X1TS U3299 ( .A0(n3442), .A1(intDX_EWSW[36]), .B0(n3437), .B1(
intDX_EWSW[37]), .Y(n2486) );
AOI221X1TS U3300 ( .A0(n3442), .A1(intDX_EWSW[36]), .B0(intDX_EWSW[37]),
.B1(n3437), .C0(n2486), .Y(n2487) );
NAND4XLTS U3301 ( .A(n2490), .B(n2489), .C(n2488), .D(n2487), .Y(n2526) );
OAI221XLTS U3302 ( .A0(n3348), .A1(intDX_EWSW[31]), .B0(n3452), .B1(
intDX_EWSW[30]), .C0(n2491), .Y(n2498) );
AOI22X1TS U3303 ( .A0(n3339), .A1(intDX_EWSW[29]), .B0(n3417), .B1(
intDX_EWSW[20]), .Y(n2492) );
OAI221XLTS U3304 ( .A0(n3339), .A1(intDX_EWSW[29]), .B0(n3417), .B1(
intDX_EWSW[20]), .C0(n2492), .Y(n2497) );
AOI22X1TS U3305 ( .A0(n3338), .A1(intDX_EWSW[27]), .B0(n3419), .B1(
intDX_EWSW[26]), .Y(n2493) );
AOI22X1TS U3306 ( .A0(n3337), .A1(intDX_EWSW[25]), .B0(n3421), .B1(
intDX_EWSW[32]), .Y(n2494) );
NOR4X1TS U3307 ( .A(n2495), .B(n2497), .C(n2496), .D(n2498), .Y(n2524) );
OAI221XLTS U3308 ( .A0(n3347), .A1(intDX_EWSW[23]), .B0(n3451), .B1(
intDX_EWSW[22]), .C0(n2499), .Y(n2504) );
AOI22X1TS U3309 ( .A0(n3411), .A1(intDX_EWSW[21]), .B0(n3422), .B1(
intDX_EWSW[48]), .Y(n2500) );
AOI22X1TS U3310 ( .A0(n3335), .A1(intDX_EWSW[17]), .B0(n3418), .B1(
intDX_EWSW[24]), .Y(n2501) );
NOR4X1TS U3311 ( .A(n2503), .B(n2504), .C(n1829), .D(n2502), .Y(n2523) );
OAI221XLTS U3312 ( .A0(n3346), .A1(intDX_EWSW[15]), .B0(n3450), .B1(
intDX_EWSW[14]), .C0(n2505), .Y(n2512) );
AOI22X1TS U3313 ( .A0(n3410), .A1(intDX_EWSW[13]), .B0(n3413), .B1(
intDX_EWSW[4]), .Y(n2506) );
AOI22X1TS U3314 ( .A0(n3408), .A1(intDX_EWSW[10]), .B0(n3415), .B1(
intDX_EWSW[12]), .Y(n2507) );
AOI22X1TS U3315 ( .A0(n3407), .A1(intDX_EWSW[9]), .B0(n3425), .B1(
intDX_EWSW[16]), .Y(n2508) );
NOR4X1TS U3316 ( .A(n2511), .B(n2512), .C(n2510), .D(n2509), .Y(n2522) );
AOI22X1TS U3317 ( .A0(n3334), .A1(intDX_EWSW[5]), .B0(n3420), .B1(
intDX_EWSW[28]), .Y(n2514) );
AOI22X1TS U3318 ( .A0(n3331), .A1(intDX_EWSW[3]), .B0(n3412), .B1(
intDX_EWSW[2]), .Y(n2515) );
AOI22X1TS U3319 ( .A0(n3333), .A1(intDX_EWSW[0]), .B0(n3414), .B1(
intDX_EWSW[8]), .Y(n2516) );
NOR4X1TS U3320 ( .A(n2520), .B(n2519), .C(n2518), .D(n2517), .Y(n2521) );
NAND4XLTS U3321 ( .A(n2524), .B(n2523), .C(n2522), .D(n2521), .Y(n2525) );
NOR4X1TS U3322 ( .A(n2528), .B(n2527), .C(n2526), .D(n2525), .Y(n2847) );
CLKXOR2X2TS U3323 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n2844) );
INVX2TS U3324 ( .A(n2844), .Y(n2532) );
OAI21XLTS U3325 ( .A0(n2532), .A1(n1933), .B0(n2871), .Y(n2530) );
AOI22X1TS U3326 ( .A0(intDX_EWSW[63]), .A1(n2530), .B0(SIGN_FLAG_EXP), .B1(
n2529), .Y(n2531) );
NOR2X4TS U3327 ( .A(n2533), .B(n2811), .Y(n2810) );
BUFX4TS U3328 ( .A(n2719), .Y(n2690) );
NOR2X8TS U3329 ( .A(n2648), .B(n2719), .Y(n2718) );
AOI21X1TS U3330 ( .A0(n2811), .A1(Data_array_SWR[34]), .B0(n2718), .Y(n2534)
);
AOI22X1TS U3331 ( .A0(Raw_mant_NRM_SWR[53]), .A1(n2631), .B0(n2677), .B1(
n1927), .Y(n2539) );
BUFX4TS U3332 ( .A(n2719), .Y(n2670) );
AOI22X1TS U3333 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n2667), .B0(n2623), .B1(
DmP_mant_SHT1_SW[2]), .Y(n2536) );
AOI22X1TS U3334 ( .A0(Raw_mant_NRM_SWR[51]), .A1(n2631), .B0(n2644), .B1(
DmP_mant_SHT1_SW[1]), .Y(n2535) );
NAND2X1TS U3335 ( .A(n2536), .B(n2535), .Y(n2558) );
AOI22X1TS U3336 ( .A0(n2815), .A1(Data_array_SWR[1]), .B0(n2554), .B1(n2558),
.Y(n2538) );
NAND2X1TS U3337 ( .A(Raw_mant_NRM_SWR[52]), .B(n1914), .Y(n2537) );
AOI22X1TS U3338 ( .A0(Raw_mant_NRM_SWR[44]), .A1(n2667), .B0(n2623), .B1(
DmP_mant_SHT1_SW[8]), .Y(n2541) );
AOI22X1TS U3339 ( .A0(Raw_mant_NRM_SWR[45]), .A1(n2631), .B0(n2644), .B1(
n1924), .Y(n2540) );
NAND2X1TS U3340 ( .A(n2541), .B(n2540), .Y(n2567) );
AOI22X1TS U3341 ( .A0(n2712), .A1(Data_array_SWR[7]), .B0(n2554), .B1(n2567),
.Y(n2543) );
NAND2X1TS U3342 ( .A(Raw_mant_NRM_SWR[46]), .B(n1914), .Y(n2542) );
AOI22X1TS U3343 ( .A0(Raw_mant_NRM_SWR[47]), .A1(n2667), .B0(n2623), .B1(
n1923), .Y(n2545) );
AOI22X1TS U3344 ( .A0(Raw_mant_NRM_SWR[48]), .A1(n2631), .B0(n2644), .B1(
n1925), .Y(n2544) );
NAND2X1TS U3345 ( .A(n2545), .B(n2544), .Y(n2562) );
AOI22X1TS U3346 ( .A0(n2819), .A1(Data_array_SWR[4]), .B0(n2554), .B1(n2562),
.Y(n2547) );
NAND2X1TS U3347 ( .A(Raw_mant_NRM_SWR[49]), .B(n1826), .Y(n2546) );
BUFX3TS U3348 ( .A(n2553), .Y(n2678) );
BUFX3TS U3349 ( .A(n2559), .Y(n2643) );
AOI22X1TS U3350 ( .A0(n2811), .A1(Data_array_SWR[32]), .B0(
Raw_mant_NRM_SWR[0]), .B1(n2643), .Y(n2552) );
AOI22X1TS U3351 ( .A0(n2631), .A1(Raw_mant_NRM_SWR[1]), .B0(
DmP_mant_SHT1_SW[51]), .B1(n1969), .Y(n2550) );
NAND2X1TS U3352 ( .A(n2550), .B(n2549), .Y(n2809) );
AOI22X1TS U3353 ( .A0(n2554), .A1(n2809), .B0(DmP_mant_SHT1_SW[49]), .B1(
n2718), .Y(n2551) );
BUFX3TS U3354 ( .A(n2553), .Y(n2673) );
BUFX4TS U3355 ( .A(n2570), .Y(n2716) );
AOI22X1TS U3356 ( .A0(n2712), .A1(n1945), .B0(Raw_mant_NRM_SWR[39]), .B1(
n2559), .Y(n2556) );
BUFX4TS U3357 ( .A(n2553), .Y(n2708) );
AOI22X1TS U3358 ( .A0(n2815), .A1(Data_array_SWR[3]), .B0(n2810), .B1(n2558),
.Y(n2561) );
NAND2X1TS U3359 ( .A(Raw_mant_NRM_SWR[48]), .B(n2643), .Y(n2560) );
AOI22X1TS U3360 ( .A0(n2819), .A1(Data_array_SWR[6]), .B0(n2810), .B1(n2562),
.Y(n2564) );
NAND2X1TS U3361 ( .A(Raw_mant_NRM_SWR[45]), .B(n2559), .Y(n2563) );
AOI22X1TS U3362 ( .A0(n2712), .A1(Data_array_SWR[8]), .B0(
Raw_mant_NRM_SWR[35]), .B1(n2559), .Y(n2566) );
AOI22X1TS U3363 ( .A0(n2712), .A1(n1940), .B0(n2810), .B1(n2567), .Y(n2569)
);
NAND2X1TS U3364 ( .A(Raw_mant_NRM_SWR[42]), .B(n2559), .Y(n2568) );
AOI22X1TS U3365 ( .A0(n2815), .A1(Data_array_SWR[26]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n2643), .Y(n2572) );
AOI22X1TS U3366 ( .A0(n2712), .A1(n1942), .B0(Raw_mant_NRM_SWR[40]), .B1(
n2559), .Y(n2574) );
AOI22X1TS U3367 ( .A0(n2712), .A1(n1944), .B0(Raw_mant_NRM_SWR[38]), .B1(
n2559), .Y(n2577) );
AOI22X1TS U3368 ( .A0(n2811), .A1(Data_array_SWR[29]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n2559), .Y(n2580) );
AOI22X1TS U3369 ( .A0(n2819), .A1(Data_array_SWR[16]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n2643), .Y(n2582) );
AOI22X1TS U3370 ( .A0(n2815), .A1(Data_array_SWR[27]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n2643), .Y(n2585) );
AOI22X1TS U3371 ( .A0(n2712), .A1(n1951), .B0(n1950), .B1(n2559), .Y(n2588)
);
AOI22X1TS U3372 ( .A0(n2712), .A1(Data_array_SWR[2]), .B0(n2810), .B1(n2590),
.Y(n2592) );
NAND2X1TS U3373 ( .A(Raw_mant_NRM_SWR[49]), .B(n2559), .Y(n2591) );
AOI22X1TS U3374 ( .A0(n2819), .A1(Data_array_SWR[14]), .B0(
Raw_mant_NRM_SWR[26]), .B1(n2559), .Y(n2595) );
AOI22X1TS U3375 ( .A0(n2819), .A1(n1953), .B0(Raw_mant_NRM_SWR[17]), .B1(
n2643), .Y(n2598) );
AOI22X1TS U3376 ( .A0(n2815), .A1(Data_array_SWR[22]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n2643), .Y(n2600) );
AOI22X1TS U3377 ( .A0(n2815), .A1(Data_array_SWR[24]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2643), .Y(n2603) );
AOI22X1TS U3378 ( .A0(n2712), .A1(n1958), .B0(Raw_mant_NRM_SWR[31]), .B1(
n2559), .Y(n2606) );
AOI22X1TS U3379 ( .A0(n2815), .A1(n1935), .B0(Raw_mant_NRM_SWR[13]), .B1(
n2643), .Y(n2610) );
AOI22X1TS U3380 ( .A0(n2712), .A1(n1946), .B0(Raw_mant_NRM_SWR[36]), .B1(
n2559), .Y(n2612) );
AOI22X1TS U3381 ( .A0(n2815), .A1(n1934), .B0(Raw_mant_NRM_SWR[15]), .B1(
n2643), .Y(n2616) );
AOI22X1TS U3382 ( .A0(n2819), .A1(n1955), .B0(Raw_mant_NRM_SWR[20]), .B1(
n2643), .Y(n2619) );
AOI22X1TS U3383 ( .A0(n2712), .A1(n1959), .B0(Raw_mant_NRM_SWR[29]), .B1(
n2559), .Y(n2621) );
AOI22X1TS U3384 ( .A0(n2819), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n2559), .Y(n2625) );
AOI22X1TS U3385 ( .A0(n2815), .A1(n1939), .B0(Raw_mant_NRM_SWR[43]), .B1(
n2559), .Y(n2628) );
AOI22X1TS U3386 ( .A0(n2811), .A1(Data_array_SWR[31]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n2559), .Y(n2633) );
AOI22X1TS U3387 ( .A0(n2819), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[22]), .B1(n2643), .Y(n2637) );
AOI22X1TS U3388 ( .A0(n2815), .A1(Data_array_SWR[5]), .B0(
Raw_mant_NRM_SWR[46]), .B1(n2559), .Y(n2641) );
AOI22X1TS U3389 ( .A0(n2819), .A1(n1952), .B0(Raw_mant_NRM_SWR[18]), .B1(
n2643), .Y(n2646) );
AOI22X1TS U3390 ( .A0(n2811), .A1(n1948), .B0(Raw_mant_NRM_SWR[1]), .B1(
n1826), .Y(n2651) );
AOI22X1TS U3391 ( .A0(n2819), .A1(n1956), .B0(n2718), .B1(
DmP_mant_SHT1_SW[26]), .Y(n2654) );
AOI22X1TS U3392 ( .A0(n2819), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[27]), .B1(n1914), .Y(n2657) );
AOI222X1TS U3393 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n2087), .B0(
Raw_mant_NRM_SWR[13]), .B1(n2708), .C0(n2623), .C1(n1930), .Y(n2682)
);
AOI22X1TS U3394 ( .A0(n2815), .A1(Data_array_SWR[21]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[37]), .Y(n2660) );
AOI22X1TS U3395 ( .A0(n2712), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[36]), .B1(n1914), .Y(n2663) );
AOI22X1TS U3396 ( .A0(n2819), .A1(n1957), .B0(n2718), .B1(
DmP_mant_SHT1_SW[28]), .Y(n2666) );
AOI22X1TS U3397 ( .A0(n2712), .A1(Data_array_SWR[11]), .B0(n2718), .B1(n1938), .Y(n2669) );
AOI222X1TS U3398 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n2087), .B0(
Raw_mant_NRM_SWR[9]), .B1(n2708), .C0(n2623), .C1(n1928), .Y(n2674) );
AOI22X1TS U3399 ( .A0(n2815), .A1(Data_array_SWR[25]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[41]), .Y(n2672) );
AOI222X1TS U3400 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n2667), .B0(
Raw_mant_NRM_SWR[11]), .B1(n2708), .C0(n2623), .C1(n1929), .Y(n2685)
);
AOI22X1TS U3401 ( .A0(n2815), .A1(n1943), .B0(n2718), .B1(
DmP_mant_SHT1_SW[43]), .Y(n2676) );
AOI22X1TS U3402 ( .A0(n2815), .A1(n1949), .B0(Raw_mant_NRM_SWR[18]), .B1(
n1914), .Y(n2681) );
AOI22X1TS U3403 ( .A0(n2815), .A1(Data_array_SWR[23]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[39]), .Y(n2684) );
AOI22X1TS U3404 ( .A0(n2712), .A1(Data_array_SWR[10]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[17]), .Y(n2688) );
AOI22X1TS U3405 ( .A0(n2815), .A1(n1936), .B0(n2718), .B1(
DmP_mant_SHT1_SW[35]), .Y(n2693) );
AOI22X1TS U3406 ( .A0(n2712), .A1(n1941), .B0(Raw_mant_NRM_SWR[43]), .B1(
n1826), .Y(n2697) );
AOI22X1TS U3407 ( .A0(n2819), .A1(n1954), .B0(n2718), .B1(
DmP_mant_SHT1_SW[30]), .Y(n2701) );
AOI22X1TS U3408 ( .A0(n2819), .A1(Data_array_SWR[12]), .B0(n2718), .B1(n1937), .Y(n2705) );
AOI22X1TS U3409 ( .A0(n2815), .A1(Data_array_SWR[28]), .B0(n2718), .B1(
DmP_mant_SHT1_SW[45]), .Y(n2711) );
AOI22X1TS U3410 ( .A0(n2712), .A1(n1947), .B0(Raw_mant_NRM_SWR[39]), .B1(
n1914), .Y(n2715) );
AOI22X1TS U3411 ( .A0(n2811), .A1(Data_array_SWR[30]), .B0(
DmP_mant_SHT1_SW[47]), .B1(n2718), .Y(n2723) );
NAND2X1TS U3412 ( .A(n3370), .B(LZD_output_NRM2_EW[0]), .Y(
DP_OP_15J75_123_4372_n11) );
MX2X1TS U3413 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1332) );
MX2X1TS U3414 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1337) );
MX2X1TS U3415 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1342) );
MX2X1TS U3416 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1347) );
MX2X1TS U3417 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1352) );
MX2X1TS U3418 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1357) );
MX2X1TS U3419 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n1970),
.Y(n1362) );
MX2X1TS U3420 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n1970),
.Y(n1367) );
MX2X1TS U3421 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n1970),
.Y(n1372) );
MX2X1TS U3422 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n1970),
.Y(n1377) );
MX2X1TS U3423 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n1382) );
AOI22X1TS U3424 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n2727), .B0(
Raw_mant_NRM_SWR[10]), .B1(n2726), .Y(n2730) );
AOI32X1TS U3425 ( .A0(n2731), .A1(n2730), .A2(n3328), .B0(n2729), .B1(n2730),
.Y(n2738) );
OAI31X1TS U3426 ( .A0(n2741), .A1(n2740), .A2(n2739), .B0(
Shift_reg_FLAGS_7[1]), .Y(n2820) );
OAI2BB1X1TS U3427 ( .A0N(LZD_output_NRM2_EW[5]), .A1N(n1969), .B0(n2820),
.Y(n1161) );
NOR2XLTS U3428 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[1]), .Y(n2754)
);
INVX2TS U3429 ( .A(n2742), .Y(n2743) );
OAI211XLTS U3430 ( .A0(n3454), .A1(n2748), .B0(n2747), .C0(n2746), .Y(n2749)
);
OAI211XLTS U3431 ( .A0(n2754), .A1(n2753), .B0(n2752), .C0(n2751), .Y(n2755)
);
OAI31X1TS U3432 ( .A0(n2757), .A1(n2756), .A2(n2755), .B0(
Shift_reg_FLAGS_7[1]), .Y(n2816) );
OAI2BB1X1TS U3433 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n1969), .B0(n2816),
.Y(n1155) );
OAI2BB1X1TS U3434 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n1969), .B0(n2758),
.Y(n1148) );
AO22XLTS U3435 ( .A0(n2762), .A1(Raw_mant_NRM_SWR[34]), .B0(
Raw_mant_NRM_SWR[32]), .B1(n2761), .Y(n2764) );
OAI211XLTS U3436 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n2768), .B0(n2767), .C0(
n2766), .Y(n2774) );
OAI211XLTS U3437 ( .A0(n3327), .A1(n2771), .B0(n2770), .C0(n2769), .Y(n2773)
);
OAI31X1TS U3438 ( .A0(n2775), .A1(n2774), .A2(n2773), .B0(
Shift_reg_FLAGS_7[1]), .Y(n2813) );
OAI2BB1X1TS U3439 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1969), .B0(n2813),
.Y(n1137) );
OAI2BB1X1TS U3440 ( .A0N(LZD_output_NRM2_EW[1]), .A1N(n1969), .B0(n2776),
.Y(n1151) );
OAI2BB1X1TS U3441 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n1969), .B0(n2777),
.Y(n1158) );
OA22X1TS U3442 ( .A0(n2784), .A1(n2779), .B0(n3468), .B1(
final_result_ieee[52]), .Y(n1619) );
OA22X1TS U3443 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[1]), .B0(n3468), .B1(
final_result_ieee[53]), .Y(n1618) );
OA22X1TS U3444 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[2]), .B0(n3468), .B1(
final_result_ieee[54]), .Y(n1617) );
OA22X1TS U3445 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[3]), .B0(n3468), .B1(
final_result_ieee[55]), .Y(n1616) );
OA22X1TS U3446 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[4]), .B0(n3468), .B1(
final_result_ieee[56]), .Y(n1615) );
OA22X1TS U3447 ( .A0(n2784), .A1(exp_rslt_NRM2_EW1[5]), .B0(n3468), .B1(
final_result_ieee[57]), .Y(n1614) );
OA22X1TS U3448 ( .A0(n2784), .A1(n2780), .B0(n3468), .B1(
final_result_ieee[58]), .Y(n1613) );
OA22X1TS U3449 ( .A0(n2784), .A1(n2781), .B0(n3468), .B1(
final_result_ieee[59]), .Y(n1612) );
OA22X1TS U3450 ( .A0(n2784), .A1(n2782), .B0(n3468), .B1(
final_result_ieee[60]), .Y(n1611) );
OA22X1TS U3451 ( .A0(n2784), .A1(n2783), .B0(n3468), .B1(
final_result_ieee[61]), .Y(n1610) );
INVX4TS U3452 ( .A(n2146), .Y(n3253) );
AO22XLTS U3453 ( .A0(n3253), .A1(n2785), .B0(n3225), .B1(
final_result_ieee[62]), .Y(n1609) );
INVX2TS U3454 ( .A(n2786), .Y(n2788) );
AOI22X1TS U3455 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n2788), .B1(n3332), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U3456 ( .A(n2788), .B(n2787), .Y(n1824) );
AO22XLTS U3457 ( .A0(n2790), .A1(n2873), .B0(n2792), .B1(n2789), .Y(n1822)
);
AOI22X1TS U3458 ( .A0(n2792), .A1(n3134), .B0(n1969), .B1(n2790), .Y(n1817)
);
AOI22X1TS U3459 ( .A0(n2792), .A1(n1969), .B0(n3240), .B1(n2790), .Y(n1816)
);
BUFX4TS U3460 ( .A(n2799), .Y(n2794) );
BUFX3TS U3461 ( .A(n2793), .Y(n2805) );
AO22XLTS U3462 ( .A0(n2799), .A1(Data_X[3]), .B0(n2806), .B1(intDX_EWSW[3]),
.Y(n1812) );
INVX4TS U3463 ( .A(n2796), .Y(n2797) );
AO22XLTS U3464 ( .A0(n2805), .A1(Data_X[8]), .B0(n2802), .B1(intDX_EWSW[8]),
.Y(n1807) );
AO22XLTS U3465 ( .A0(n2805), .A1(Data_X[11]), .B0(n2800), .B1(intDX_EWSW[11]), .Y(n1804) );
AO22XLTS U3466 ( .A0(n2805), .A1(Data_X[12]), .B0(n2797), .B1(intDX_EWSW[12]), .Y(n1803) );
AO22XLTS U3467 ( .A0(n2794), .A1(Data_X[15]), .B0(n2802), .B1(intDX_EWSW[15]), .Y(n1800) );
AO22XLTS U3468 ( .A0(n2796), .A1(Data_X[17]), .B0(n2797), .B1(intDX_EWSW[17]), .Y(n1798) );
AO22XLTS U3469 ( .A0(n2796), .A1(Data_X[18]), .B0(n2802), .B1(intDX_EWSW[18]), .Y(n1797) );
AO22XLTS U3470 ( .A0(n2796), .A1(Data_X[19]), .B0(n2803), .B1(intDX_EWSW[19]), .Y(n1796) );
AO22XLTS U3471 ( .A0(n2796), .A1(Data_X[20]), .B0(n2806), .B1(intDX_EWSW[20]), .Y(n1795) );
AO22XLTS U3472 ( .A0(n2796), .A1(Data_X[21]), .B0(n2800), .B1(intDX_EWSW[21]), .Y(n1794) );
AO22XLTS U3473 ( .A0(n2796), .A1(Data_X[22]), .B0(n2797), .B1(intDX_EWSW[22]), .Y(n1793) );
AO22XLTS U3474 ( .A0(n2796), .A1(Data_X[23]), .B0(n2131), .B1(intDX_EWSW[23]), .Y(n1792) );
AO22XLTS U3475 ( .A0(n2796), .A1(Data_X[25]), .B0(n2800), .B1(intDX_EWSW[25]), .Y(n1790) );
AO22XLTS U3476 ( .A0(n2805), .A1(Data_X[26]), .B0(n2797), .B1(intDX_EWSW[26]), .Y(n1789) );
AO22XLTS U3477 ( .A0(n2794), .A1(Data_X[27]), .B0(n2803), .B1(intDX_EWSW[27]), .Y(n1788) );
AO22XLTS U3478 ( .A0(n2794), .A1(Data_X[28]), .B0(n2806), .B1(intDX_EWSW[28]), .Y(n1787) );
AO22XLTS U3479 ( .A0(n2794), .A1(Data_X[29]), .B0(n2803), .B1(intDX_EWSW[29]), .Y(n1786) );
AO22XLTS U3480 ( .A0(n2794), .A1(Data_X[30]), .B0(n2795), .B1(intDX_EWSW[30]), .Y(n1785) );
AO22XLTS U3481 ( .A0(n2794), .A1(Data_X[31]), .B0(n2802), .B1(intDX_EWSW[31]), .Y(n1784) );
AO22XLTS U3482 ( .A0(n2794), .A1(Data_X[33]), .B0(n2795), .B1(intDX_EWSW[33]), .Y(n1782) );
AO22XLTS U3483 ( .A0(n2793), .A1(Data_X[45]), .B0(n2807), .B1(intDX_EWSW[45]), .Y(n1770) );
AO22XLTS U3484 ( .A0(n2793), .A1(Data_X[46]), .B0(n2807), .B1(intDX_EWSW[46]), .Y(n1769) );
AO22XLTS U3485 ( .A0(n2794), .A1(Data_X[49]), .B0(n2807), .B1(intDX_EWSW[49]), .Y(n1766) );
AO22XLTS U3486 ( .A0(n2798), .A1(Data_X[50]), .B0(n2807), .B1(intDX_EWSW[50]), .Y(n1765) );
AO22XLTS U3487 ( .A0(n2798), .A1(Data_X[51]), .B0(n2807), .B1(intDX_EWSW[51]), .Y(n1764) );
AO22XLTS U3488 ( .A0(n2797), .A1(intDX_EWSW[53]), .B0(n2808), .B1(Data_X[53]), .Y(n1762) );
AO22XLTS U3489 ( .A0(n2797), .A1(intDX_EWSW[54]), .B0(n2808), .B1(Data_X[54]), .Y(n1761) );
AO22XLTS U3490 ( .A0(n2797), .A1(intDX_EWSW[55]), .B0(n2808), .B1(Data_X[55]), .Y(n1760) );
AO22XLTS U3491 ( .A0(n2797), .A1(intDX_EWSW[56]), .B0(n2808), .B1(Data_X[56]), .Y(n1759) );
AO22XLTS U3492 ( .A0(n2798), .A1(Data_X[57]), .B0(n2807), .B1(intDX_EWSW[57]), .Y(n1758) );
AO22XLTS U3493 ( .A0(n2798), .A1(Data_X[58]), .B0(n2807), .B1(intDX_EWSW[58]), .Y(n1757) );
AO22XLTS U3494 ( .A0(n2798), .A1(Data_X[59]), .B0(n2807), .B1(intDX_EWSW[59]), .Y(n1756) );
AO22XLTS U3495 ( .A0(n2798), .A1(Data_X[60]), .B0(n2807), .B1(intDX_EWSW[60]), .Y(n1755) );
AO22XLTS U3496 ( .A0(n2794), .A1(add_subt), .B0(n2795), .B1(intAS), .Y(n1751) );
AO22XLTS U3497 ( .A0(n2795), .A1(intDY_EWSW[0]), .B0(n2808), .B1(Data_Y[0]),
.Y(n1749) );
AO22XLTS U3498 ( .A0(n2795), .A1(intDY_EWSW[1]), .B0(n2808), .B1(Data_Y[1]),
.Y(n1748) );
AO22XLTS U3499 ( .A0(n2807), .A1(intDY_EWSW[2]), .B0(n2808), .B1(Data_Y[2]),
.Y(n1747) );
AO22XLTS U3500 ( .A0(n2795), .A1(intDY_EWSW[3]), .B0(n2808), .B1(Data_Y[3]),
.Y(n1746) );
AO22XLTS U3501 ( .A0(n2807), .A1(intDY_EWSW[4]), .B0(n2808), .B1(Data_Y[4]),
.Y(n1745) );
AO22XLTS U3502 ( .A0(n2807), .A1(intDY_EWSW[5]), .B0(n2808), .B1(Data_Y[5]),
.Y(n1744) );
AO22XLTS U3503 ( .A0(n2807), .A1(intDY_EWSW[6]), .B0(n2808), .B1(Data_Y[6]),
.Y(n1743) );
AO22XLTS U3504 ( .A0(n2795), .A1(intDY_EWSW[7]), .B0(n2808), .B1(Data_Y[7]),
.Y(n1742) );
AO22XLTS U3505 ( .A0(n2797), .A1(intDY_EWSW[8]), .B0(n2796), .B1(Data_Y[8]),
.Y(n1741) );
AO22XLTS U3506 ( .A0(n2797), .A1(intDY_EWSW[9]), .B0(n2798), .B1(Data_Y[9]),
.Y(n1740) );
AO22XLTS U3507 ( .A0(n2797), .A1(intDY_EWSW[10]), .B0(n2798), .B1(Data_Y[10]), .Y(n1739) );
AO22XLTS U3508 ( .A0(n2797), .A1(intDY_EWSW[11]), .B0(n2798), .B1(Data_Y[11]), .Y(n1738) );
AO22XLTS U3509 ( .A0(n2797), .A1(intDY_EWSW[12]), .B0(n2804), .B1(Data_Y[12]), .Y(n1737) );
AO22XLTS U3510 ( .A0(n2797), .A1(intDY_EWSW[13]), .B0(n2796), .B1(Data_Y[13]), .Y(n1736) );
AO22XLTS U3511 ( .A0(n2797), .A1(intDY_EWSW[14]), .B0(n2796), .B1(Data_Y[14]), .Y(n1735) );
AO22XLTS U3512 ( .A0(n2797), .A1(intDY_EWSW[15]), .B0(n2798), .B1(Data_Y[15]), .Y(n1734) );
AO22XLTS U3513 ( .A0(n2800), .A1(intDY_EWSW[16]), .B0(n2804), .B1(Data_Y[16]), .Y(n1733) );
AO22XLTS U3514 ( .A0(n2800), .A1(intDY_EWSW[17]), .B0(n2798), .B1(Data_Y[17]), .Y(n1732) );
AO22XLTS U3515 ( .A0(n2800), .A1(intDY_EWSW[18]), .B0(n2804), .B1(Data_Y[18]), .Y(n1731) );
AO22XLTS U3516 ( .A0(n2800), .A1(intDY_EWSW[19]), .B0(n2798), .B1(Data_Y[19]), .Y(n1730) );
AO22XLTS U3517 ( .A0(n2800), .A1(intDY_EWSW[20]), .B0(n2808), .B1(Data_Y[20]), .Y(n1729) );
AO22XLTS U3518 ( .A0(n2800), .A1(intDY_EWSW[21]), .B0(n2804), .B1(Data_Y[21]), .Y(n1728) );
AO22XLTS U3519 ( .A0(n2800), .A1(intDY_EWSW[22]), .B0(n2804), .B1(Data_Y[22]), .Y(n1727) );
AO22XLTS U3520 ( .A0(n2800), .A1(intDY_EWSW[23]), .B0(n2804), .B1(Data_Y[23]), .Y(n1726) );
AO22XLTS U3521 ( .A0(n2800), .A1(intDY_EWSW[24]), .B0(n2804), .B1(Data_Y[24]), .Y(n1725) );
AO22XLTS U3522 ( .A0(n2800), .A1(intDY_EWSW[25]), .B0(n2804), .B1(Data_Y[25]), .Y(n1724) );
AO22XLTS U3523 ( .A0(n2800), .A1(intDY_EWSW[26]), .B0(n2799), .B1(Data_Y[26]), .Y(n1723) );
AO22XLTS U3524 ( .A0(n2800), .A1(intDY_EWSW[27]), .B0(n2804), .B1(Data_Y[27]), .Y(n1722) );
AO22XLTS U3525 ( .A0(n2802), .A1(intDY_EWSW[28]), .B0(n2801), .B1(Data_Y[28]), .Y(n1721) );
AO22XLTS U3526 ( .A0(n2802), .A1(intDY_EWSW[29]), .B0(n2801), .B1(Data_Y[29]), .Y(n1720) );
AO22XLTS U3527 ( .A0(n2802), .A1(intDY_EWSW[30]), .B0(n2804), .B1(Data_Y[30]), .Y(n1719) );
AO22XLTS U3528 ( .A0(n2802), .A1(intDY_EWSW[31]), .B0(n2801), .B1(Data_Y[31]), .Y(n1718) );
AO22XLTS U3529 ( .A0(n2802), .A1(intDY_EWSW[32]), .B0(n2801), .B1(Data_Y[32]), .Y(n1717) );
AO22XLTS U3530 ( .A0(n2802), .A1(intDY_EWSW[33]), .B0(n2801), .B1(Data_Y[33]), .Y(n1716) );
AO22XLTS U3531 ( .A0(n2802), .A1(intDY_EWSW[34]), .B0(n2794), .B1(Data_Y[34]), .Y(n1715) );
AO22XLTS U3532 ( .A0(n2802), .A1(intDY_EWSW[35]), .B0(n2808), .B1(Data_Y[35]), .Y(n1714) );
AO22XLTS U3533 ( .A0(n2802), .A1(intDY_EWSW[36]), .B0(n2794), .B1(Data_Y[36]), .Y(n1713) );
AO22XLTS U3534 ( .A0(n2802), .A1(intDY_EWSW[37]), .B0(n2801), .B1(Data_Y[37]), .Y(n1712) );
AO22XLTS U3535 ( .A0(n2802), .A1(intDY_EWSW[38]), .B0(n2805), .B1(Data_Y[38]), .Y(n1711) );
AO22XLTS U3536 ( .A0(n2802), .A1(intDY_EWSW[39]), .B0(n2799), .B1(Data_Y[39]), .Y(n1710) );
AO22XLTS U3537 ( .A0(n2803), .A1(intDY_EWSW[49]), .B0(n2805), .B1(Data_Y[49]), .Y(n1700) );
AO22XLTS U3538 ( .A0(n2806), .A1(intDY_EWSW[52]), .B0(n2804), .B1(Data_Y[52]), .Y(n1697) );
AO22XLTS U3539 ( .A0(n2806), .A1(intDY_EWSW[54]), .B0(n2805), .B1(Data_Y[54]), .Y(n1695) );
AOI22X1TS U3540 ( .A0(n2811), .A1(Data_array_SWR[33]), .B0(n2810), .B1(n2809), .Y(n2812) );
OAI2BB1X1TS U3541 ( .A0N(Raw_mant_NRM_SWR[0]), .A1N(n1826), .B0(n2812), .Y(
n1684) );
AOI22X1TS U3542 ( .A0(n2819), .A1(shift_value_SHT2_EWR[2]), .B0(
Shift_amount_SHT1_EWR[2]), .B1(n2818), .Y(n2814) );
NAND2X1TS U3543 ( .A(n2814), .B(n2813), .Y(n1630) );
AOI22X1TS U3544 ( .A0(n2815), .A1(shift_value_SHT2_EWR[4]), .B0(n2818), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n2817) );
NAND2X1TS U3545 ( .A(n2817), .B(n2816), .Y(n1628) );
AOI22X1TS U3546 ( .A0(n2819), .A1(shift_value_SHT2_EWR[5]), .B0(n2818), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n2821) );
NAND2X1TS U3547 ( .A(n2821), .B(n2820), .Y(n1626) );
NAND2X1TS U3548 ( .A(DmP_EXP_EWSW[52]), .B(n3458), .Y(n2826) );
OAI21XLTS U3549 ( .A0(DmP_EXP_EWSW[52]), .A1(n3458), .B0(n2826), .Y(n2822)
);
NAND2X1TS U3550 ( .A(DmP_EXP_EWSW[53]), .B(n3351), .Y(n2825) );
OAI21XLTS U3551 ( .A0(DmP_EXP_EWSW[53]), .A1(n3351), .B0(n2825), .Y(n2823)
);
XNOR2X1TS U3552 ( .A(n2826), .B(n2823), .Y(n2824) );
BUFX3TS U3553 ( .A(n2877), .Y(n2849) );
AO22XLTS U3554 ( .A0(n2848), .A1(n2824), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n1624) );
AOI22X1TS U3555 ( .A0(DMP_EXP_EWSW[53]), .A1(n3356), .B0(n2826), .B1(n2825),
.Y(n2829) );
NOR2X1TS U3556 ( .A(n3353), .B(DMP_EXP_EWSW[54]), .Y(n2830) );
AOI21X1TS U3557 ( .A0(DMP_EXP_EWSW[54]), .A1(n3353), .B0(n2830), .Y(n2827)
);
XNOR2X1TS U3558 ( .A(n2829), .B(n2827), .Y(n2828) );
AO22XLTS U3559 ( .A0(n2848), .A1(n2828), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n1623) );
OAI22X1TS U3560 ( .A0(n2830), .A1(n2829), .B0(DmP_EXP_EWSW[54]), .B1(n3355),
.Y(n2833) );
NAND2X1TS U3561 ( .A(DmP_EXP_EWSW[55]), .B(n3354), .Y(n2834) );
XNOR2X1TS U3562 ( .A(n2833), .B(n2831), .Y(n2832) );
AO22XLTS U3563 ( .A0(n2848), .A1(n2832), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n1622) );
AOI22X1TS U3564 ( .A0(DMP_EXP_EWSW[55]), .A1(n3360), .B0(n2834), .B1(n2833),
.Y(n2837) );
NOR2X1TS U3565 ( .A(n3357), .B(DMP_EXP_EWSW[56]), .Y(n2838) );
AOI21X1TS U3566 ( .A0(DMP_EXP_EWSW[56]), .A1(n3357), .B0(n2838), .Y(n2835)
);
XNOR2X1TS U3567 ( .A(n2837), .B(n2835), .Y(n2836) );
AO22XLTS U3568 ( .A0(n2848), .A1(n2836), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n1621) );
OAI22X1TS U3569 ( .A0(n2838), .A1(n2837), .B0(DmP_EXP_EWSW[56]), .B1(n3359),
.Y(n2840) );
XNOR2X1TS U3570 ( .A(DmP_EXP_EWSW[57]), .B(DMP_EXP_EWSW[57]), .Y(n2839) );
XOR2XLTS U3571 ( .A(n2840), .B(n2839), .Y(n2841) );
AO22XLTS U3572 ( .A0(n2848), .A1(n2841), .B0(n2849), .B1(
Shift_amount_SHT1_EWR[5]), .Y(n1620) );
OAI222X1TS U3573 ( .A0(n2842), .A1(n3464), .B0(n3351), .B1(n2873), .C0(n3313), .C1(n2874), .Y(n1555) );
OAI222X1TS U3574 ( .A0(n2842), .A1(n3358), .B0(n3355), .B1(n2873), .C0(n3312), .C1(n2874), .Y(n1554) );
OAI222X1TS U3575 ( .A0(n2842), .A1(n3465), .B0(n3354), .B1(n2873), .C0(n3309), .C1(n2874), .Y(n1553) );
OAI222X1TS U3576 ( .A0(n2871), .A1(n3314), .B0(n3359), .B1(n2873), .C0(n3310), .C1(n2874), .Y(n1552) );
OAI21XLTS U3577 ( .A0(n2844), .A1(intDX_EWSW[63]), .B0(n2873), .Y(n2843) );
AOI21X1TS U3578 ( .A0(n2844), .A1(intDX_EWSW[63]), .B0(n2843), .Y(n2846) );
AO21XLTS U3579 ( .A0(OP_FLAG_EXP), .A1(n1997), .B0(n2846), .Y(n1545) );
AO22XLTS U3580 ( .A0(n2847), .A1(n2846), .B0(ZERO_FLAG_EXP), .B1(n1933), .Y(
n1544) );
AO22XLTS U3581 ( .A0(n2848), .A1(DMP_EXP_EWSW[0]), .B0(n2849), .B1(
DMP_SHT1_EWSW[0]), .Y(n1542) );
AO22XLTS U3582 ( .A0(n2851), .A1(DMP_SHT1_EWSW[0]), .B0(n3462), .B1(
DMP_SHT2_EWSW[0]), .Y(n1541) );
AO22XLTS U3583 ( .A0(n2848), .A1(DMP_EXP_EWSW[1]), .B0(n2849), .B1(
DMP_SHT1_EWSW[1]), .Y(n1539) );
AO22XLTS U3584 ( .A0(n2851), .A1(DMP_SHT1_EWSW[1]), .B0(n2859), .B1(
DMP_SHT2_EWSW[1]), .Y(n1538) );
INVX2TS U3585 ( .A(n3295), .Y(n2854) );
BUFX3TS U3586 ( .A(n3295), .Y(n2864) );
AO22XLTS U3587 ( .A0(n2848), .A1(DMP_EXP_EWSW[2]), .B0(n2849), .B1(
DMP_SHT1_EWSW[2]), .Y(n1536) );
AO22XLTS U3588 ( .A0(n2851), .A1(DMP_SHT1_EWSW[2]), .B0(n2859), .B1(
DMP_SHT2_EWSW[2]), .Y(n1535) );
INVX4TS U3589 ( .A(n3295), .Y(n3297) );
AO22XLTS U3590 ( .A0(n2852), .A1(DMP_SFG[2]), .B0(n2858), .B1(
DMP_SHT2_EWSW[2]), .Y(n1534) );
AO22XLTS U3591 ( .A0(n2848), .A1(DMP_EXP_EWSW[3]), .B0(n2849), .B1(
DMP_SHT1_EWSW[3]), .Y(n1533) );
AO22XLTS U3592 ( .A0(n2851), .A1(DMP_SHT1_EWSW[3]), .B0(n2859), .B1(
DMP_SHT2_EWSW[3]), .Y(n1532) );
CLKBUFX2TS U3593 ( .A(n2852), .Y(n3279) );
BUFX4TS U3594 ( .A(n3279), .Y(n3293) );
AO22XLTS U3595 ( .A0(n3293), .A1(DMP_SFG[3]), .B0(n2854), .B1(
DMP_SHT2_EWSW[3]), .Y(n1531) );
AO22XLTS U3596 ( .A0(n2848), .A1(DMP_EXP_EWSW[4]), .B0(n2849), .B1(
DMP_SHT1_EWSW[4]), .Y(n1530) );
AO22XLTS U3597 ( .A0(n2851), .A1(DMP_SHT1_EWSW[4]), .B0(n2859), .B1(
DMP_SHT2_EWSW[4]), .Y(n1529) );
AO22XLTS U3598 ( .A0(n2848), .A1(DMP_EXP_EWSW[5]), .B0(n2849), .B1(
DMP_SHT1_EWSW[5]), .Y(n1527) );
AO22XLTS U3599 ( .A0(n2851), .A1(DMP_SHT1_EWSW[5]), .B0(n2859), .B1(
DMP_SHT2_EWSW[5]), .Y(n1526) );
AO22XLTS U3600 ( .A0(n2850), .A1(DMP_EXP_EWSW[6]), .B0(n2849), .B1(
DMP_SHT1_EWSW[6]), .Y(n1524) );
AO22XLTS U3601 ( .A0(n2851), .A1(DMP_SHT1_EWSW[6]), .B0(n2859), .B1(
DMP_SHT2_EWSW[6]), .Y(n1523) );
AO22XLTS U3602 ( .A0(n2850), .A1(DMP_EXP_EWSW[7]), .B0(n2849), .B1(
DMP_SHT1_EWSW[7]), .Y(n1521) );
AO22XLTS U3603 ( .A0(n2851), .A1(DMP_SHT1_EWSW[7]), .B0(n2859), .B1(
DMP_SHT2_EWSW[7]), .Y(n1520) );
AO22XLTS U3604 ( .A0(n2850), .A1(DMP_EXP_EWSW[8]), .B0(n2849), .B1(
DMP_SHT1_EWSW[8]), .Y(n1518) );
AO22XLTS U3605 ( .A0(n2851), .A1(DMP_SHT1_EWSW[8]), .B0(n2859), .B1(
DMP_SHT2_EWSW[8]), .Y(n1517) );
BUFX3TS U3606 ( .A(n3463), .Y(n2855) );
BUFX3TS U3607 ( .A(n2855), .Y(n2856) );
AO22XLTS U3608 ( .A0(n2850), .A1(DMP_EXP_EWSW[9]), .B0(n2856), .B1(
DMP_SHT1_EWSW[9]), .Y(n1515) );
AO22XLTS U3609 ( .A0(n2851), .A1(DMP_SHT1_EWSW[9]), .B0(n2859), .B1(
DMP_SHT2_EWSW[9]), .Y(n1514) );
AO22XLTS U3610 ( .A0(n2850), .A1(DMP_EXP_EWSW[10]), .B0(n2855), .B1(
DMP_SHT1_EWSW[10]), .Y(n1512) );
AO22XLTS U3611 ( .A0(n2851), .A1(DMP_SHT1_EWSW[10]), .B0(n2859), .B1(
DMP_SHT2_EWSW[10]), .Y(n1511) );
AO22XLTS U3612 ( .A0(n2850), .A1(DMP_EXP_EWSW[11]), .B0(n2855), .B1(
DMP_SHT1_EWSW[11]), .Y(n1509) );
AO22XLTS U3613 ( .A0(n2851), .A1(DMP_SHT1_EWSW[11]), .B0(n3462), .B1(
DMP_SHT2_EWSW[11]), .Y(n1508) );
AO22XLTS U3614 ( .A0(n2850), .A1(DMP_EXP_EWSW[12]), .B0(n2856), .B1(
DMP_SHT1_EWSW[12]), .Y(n1506) );
AO22XLTS U3615 ( .A0(n2851), .A1(DMP_SHT1_EWSW[12]), .B0(n3462), .B1(
DMP_SHT2_EWSW[12]), .Y(n1505) );
AO22XLTS U3616 ( .A0(n2850), .A1(DMP_EXP_EWSW[13]), .B0(n2856), .B1(
DMP_SHT1_EWSW[13]), .Y(n1503) );
AO22XLTS U3617 ( .A0(n2851), .A1(DMP_SHT1_EWSW[13]), .B0(n3462), .B1(
DMP_SHT2_EWSW[13]), .Y(n1502) );
AO22XLTS U3618 ( .A0(n2850), .A1(DMP_EXP_EWSW[14]), .B0(n3463), .B1(
DMP_SHT1_EWSW[14]), .Y(n1500) );
AO22XLTS U3619 ( .A0(n2851), .A1(DMP_SHT1_EWSW[14]), .B0(n3462), .B1(
DMP_SHT2_EWSW[14]), .Y(n1499) );
BUFX3TS U3620 ( .A(n3307), .Y(n2861) );
AO22XLTS U3621 ( .A0(n2850), .A1(DMP_EXP_EWSW[15]), .B0(n2855), .B1(
DMP_SHT1_EWSW[15]), .Y(n1497) );
AO22XLTS U3622 ( .A0(n2851), .A1(DMP_SHT1_EWSW[15]), .B0(n3462), .B1(
DMP_SHT2_EWSW[15]), .Y(n1496) );
BUFX3TS U3623 ( .A(n3307), .Y(n2857) );
AO22XLTS U3624 ( .A0(n2850), .A1(DMP_EXP_EWSW[16]), .B0(n2855), .B1(
DMP_SHT1_EWSW[16]), .Y(n1494) );
AO22XLTS U3625 ( .A0(n2851), .A1(DMP_SHT1_EWSW[16]), .B0(n3462), .B1(
DMP_SHT2_EWSW[16]), .Y(n1493) );
AO22XLTS U3626 ( .A0(n2850), .A1(DMP_EXP_EWSW[17]), .B0(n2855), .B1(
DMP_SHT1_EWSW[17]), .Y(n1491) );
AO22XLTS U3627 ( .A0(n2851), .A1(DMP_SHT1_EWSW[17]), .B0(n3462), .B1(
DMP_SHT2_EWSW[17]), .Y(n1490) );
INVX4TS U3628 ( .A(n2877), .Y(n2866) );
AO22XLTS U3629 ( .A0(n2866), .A1(DMP_EXP_EWSW[18]), .B0(n2855), .B1(
DMP_SHT1_EWSW[18]), .Y(n1488) );
AO22XLTS U3630 ( .A0(n2851), .A1(DMP_SHT1_EWSW[18]), .B0(n3462), .B1(
DMP_SHT2_EWSW[18]), .Y(n1487) );
AO22XLTS U3631 ( .A0(n2866), .A1(DMP_EXP_EWSW[19]), .B0(n2855), .B1(
DMP_SHT1_EWSW[19]), .Y(n1485) );
AO22XLTS U3632 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n3462), .B1(
DMP_SHT2_EWSW[19]), .Y(n1484) );
AO22XLTS U3633 ( .A0(n2866), .A1(DMP_EXP_EWSW[20]), .B0(n2855), .B1(
DMP_SHT1_EWSW[20]), .Y(n1482) );
AO22XLTS U3634 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n3462), .B1(
DMP_SHT2_EWSW[20]), .Y(n1481) );
AO22XLTS U3635 ( .A0(n2866), .A1(DMP_EXP_EWSW[21]), .B0(n2855), .B1(
DMP_SHT1_EWSW[21]), .Y(n1479) );
AO22XLTS U3636 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n3462), .B1(
DMP_SHT2_EWSW[21]), .Y(n1478) );
AO22XLTS U3637 ( .A0(n2866), .A1(DMP_EXP_EWSW[22]), .B0(n2855), .B1(
DMP_SHT1_EWSW[22]), .Y(n1476) );
AO22XLTS U3638 ( .A0(busy), .A1(DMP_SHT1_EWSW[22]), .B0(n3462), .B1(
DMP_SHT2_EWSW[22]), .Y(n1475) );
AO22XLTS U3639 ( .A0(n2866), .A1(DMP_EXP_EWSW[23]), .B0(n2855), .B1(
DMP_SHT1_EWSW[23]), .Y(n1473) );
AO22XLTS U3640 ( .A0(busy), .A1(DMP_SHT1_EWSW[23]), .B0(n3462), .B1(
DMP_SHT2_EWSW[23]), .Y(n1472) );
BUFX3TS U3641 ( .A(n3295), .Y(n3130) );
AO22XLTS U3642 ( .A0(n2866), .A1(DMP_EXP_EWSW[24]), .B0(n2855), .B1(
DMP_SHT1_EWSW[24]), .Y(n1470) );
BUFX4TS U3643 ( .A(n3462), .Y(n2860) );
AO22XLTS U3644 ( .A0(busy), .A1(DMP_SHT1_EWSW[24]), .B0(n2860), .B1(
DMP_SHT2_EWSW[24]), .Y(n1469) );
AO22XLTS U3645 ( .A0(n2866), .A1(DMP_EXP_EWSW[25]), .B0(n2855), .B1(
DMP_SHT1_EWSW[25]), .Y(n1467) );
AO22XLTS U3646 ( .A0(busy), .A1(DMP_SHT1_EWSW[25]), .B0(n2860), .B1(
DMP_SHT2_EWSW[25]), .Y(n1466) );
AO22XLTS U3647 ( .A0(n2866), .A1(DMP_EXP_EWSW[26]), .B0(n2856), .B1(
DMP_SHT1_EWSW[26]), .Y(n1464) );
AO22XLTS U3648 ( .A0(busy), .A1(DMP_SHT1_EWSW[26]), .B0(n2860), .B1(
DMP_SHT2_EWSW[26]), .Y(n1463) );
AO22XLTS U3649 ( .A0(n2866), .A1(DMP_EXP_EWSW[27]), .B0(n2856), .B1(
DMP_SHT1_EWSW[27]), .Y(n1461) );
AO22XLTS U3650 ( .A0(n2862), .A1(DMP_SHT1_EWSW[27]), .B0(n2860), .B1(
DMP_SHT2_EWSW[27]), .Y(n1460) );
AO22XLTS U3651 ( .A0(n2866), .A1(DMP_EXP_EWSW[28]), .B0(n2856), .B1(
DMP_SHT1_EWSW[28]), .Y(n1458) );
AO22XLTS U3652 ( .A0(n2862), .A1(DMP_SHT1_EWSW[28]), .B0(n2860), .B1(
DMP_SHT2_EWSW[28]), .Y(n1457) );
AO22XLTS U3653 ( .A0(n2866), .A1(DMP_EXP_EWSW[29]), .B0(n2856), .B1(
DMP_SHT1_EWSW[29]), .Y(n1455) );
AO22XLTS U3654 ( .A0(n2862), .A1(DMP_SHT1_EWSW[29]), .B0(n2860), .B1(
DMP_SHT2_EWSW[29]), .Y(n1454) );
INVX4TS U3655 ( .A(n2877), .Y(n2868) );
AO22XLTS U3656 ( .A0(n2868), .A1(DMP_EXP_EWSW[30]), .B0(n2856), .B1(
DMP_SHT1_EWSW[30]), .Y(n1452) );
AO22XLTS U3657 ( .A0(n2862), .A1(DMP_SHT1_EWSW[30]), .B0(n2860), .B1(
DMP_SHT2_EWSW[30]), .Y(n1451) );
AO22XLTS U3658 ( .A0(n2868), .A1(DMP_EXP_EWSW[31]), .B0(n2856), .B1(
DMP_SHT1_EWSW[31]), .Y(n1449) );
AO22XLTS U3659 ( .A0(n2862), .A1(DMP_SHT1_EWSW[31]), .B0(n2860), .B1(
DMP_SHT2_EWSW[31]), .Y(n1448) );
AO22XLTS U3660 ( .A0(n2868), .A1(DMP_EXP_EWSW[32]), .B0(n2856), .B1(
DMP_SHT1_EWSW[32]), .Y(n1446) );
AO22XLTS U3661 ( .A0(n2862), .A1(DMP_SHT1_EWSW[32]), .B0(n2860), .B1(
DMP_SHT2_EWSW[32]), .Y(n1445) );
AO22XLTS U3662 ( .A0(n2868), .A1(DMP_EXP_EWSW[33]), .B0(n2856), .B1(
DMP_SHT1_EWSW[33]), .Y(n1443) );
AO22XLTS U3663 ( .A0(n2862), .A1(DMP_SHT1_EWSW[33]), .B0(n2860), .B1(
DMP_SHT2_EWSW[33]), .Y(n1442) );
AO22XLTS U3664 ( .A0(n2868), .A1(DMP_EXP_EWSW[34]), .B0(n2856), .B1(
DMP_SHT1_EWSW[34]), .Y(n1440) );
AO22XLTS U3665 ( .A0(n2862), .A1(DMP_SHT1_EWSW[34]), .B0(n2860), .B1(
DMP_SHT2_EWSW[34]), .Y(n1439) );
AO22XLTS U3666 ( .A0(n2868), .A1(DMP_EXP_EWSW[35]), .B0(n2856), .B1(
DMP_SHT1_EWSW[35]), .Y(n1437) );
AO22XLTS U3667 ( .A0(n2862), .A1(DMP_SHT1_EWSW[35]), .B0(n2860), .B1(
DMP_SHT2_EWSW[35]), .Y(n1436) );
AO22XLTS U3668 ( .A0(n2868), .A1(DMP_EXP_EWSW[36]), .B0(n2856), .B1(
DMP_SHT1_EWSW[36]), .Y(n1434) );
AO22XLTS U3669 ( .A0(n2862), .A1(DMP_SHT1_EWSW[36]), .B0(n2860), .B1(
DMP_SHT2_EWSW[36]), .Y(n1433) );
BUFX3TS U3670 ( .A(n3463), .Y(n2865) );
AO22XLTS U3671 ( .A0(n2868), .A1(DMP_EXP_EWSW[37]), .B0(n3463), .B1(
DMP_SHT1_EWSW[37]), .Y(n1431) );
AO22XLTS U3672 ( .A0(n2862), .A1(DMP_SHT1_EWSW[37]), .B0(n2860), .B1(
DMP_SHT2_EWSW[37]), .Y(n1430) );
AO22XLTS U3673 ( .A0(n2868), .A1(DMP_EXP_EWSW[38]), .B0(n3463), .B1(
DMP_SHT1_EWSW[38]), .Y(n1428) );
AO22XLTS U3674 ( .A0(n2862), .A1(DMP_SHT1_EWSW[38]), .B0(n2860), .B1(
DMP_SHT2_EWSW[38]), .Y(n1427) );
AO22XLTS U3675 ( .A0(n2868), .A1(DMP_EXP_EWSW[39]), .B0(n3463), .B1(
DMP_SHT1_EWSW[39]), .Y(n1425) );
AO22XLTS U3676 ( .A0(n2862), .A1(DMP_SHT1_EWSW[39]), .B0(n2860), .B1(
DMP_SHT2_EWSW[39]), .Y(n1424) );
AO22XLTS U3677 ( .A0(n2868), .A1(DMP_EXP_EWSW[40]), .B0(n3463), .B1(
DMP_SHT1_EWSW[40]), .Y(n1422) );
AO22XLTS U3678 ( .A0(n2863), .A1(DMP_SHT1_EWSW[40]), .B0(n2860), .B1(
DMP_SHT2_EWSW[40]), .Y(n1421) );
AO22XLTS U3679 ( .A0(n2868), .A1(DMP_EXP_EWSW[41]), .B0(n3463), .B1(
DMP_SHT1_EWSW[41]), .Y(n1419) );
AO22XLTS U3680 ( .A0(n2863), .A1(DMP_SHT1_EWSW[41]), .B0(n2860), .B1(
DMP_SHT2_EWSW[41]), .Y(n1418) );
INVX4TS U3681 ( .A(n2865), .Y(n2867) );
AO22XLTS U3682 ( .A0(n2867), .A1(DMP_EXP_EWSW[42]), .B0(n3463), .B1(
DMP_SHT1_EWSW[42]), .Y(n1416) );
AO22XLTS U3683 ( .A0(n2863), .A1(DMP_SHT1_EWSW[42]), .B0(n2860), .B1(
DMP_SHT2_EWSW[42]), .Y(n1415) );
AO22XLTS U3684 ( .A0(n2867), .A1(DMP_EXP_EWSW[43]), .B0(n3463), .B1(
DMP_SHT1_EWSW[43]), .Y(n1413) );
AO22XLTS U3685 ( .A0(n2863), .A1(DMP_SHT1_EWSW[43]), .B0(n2860), .B1(
DMP_SHT2_EWSW[43]), .Y(n1412) );
AO22XLTS U3686 ( .A0(n2867), .A1(DMP_EXP_EWSW[44]), .B0(n3463), .B1(
DMP_SHT1_EWSW[44]), .Y(n1410) );
BUFX4TS U3687 ( .A(n3462), .Y(n2881) );
AO22XLTS U3688 ( .A0(n2863), .A1(DMP_SHT1_EWSW[44]), .B0(n2881), .B1(
DMP_SHT2_EWSW[44]), .Y(n1409) );
AO22XLTS U3689 ( .A0(n2867), .A1(DMP_EXP_EWSW[45]), .B0(n3463), .B1(
DMP_SHT1_EWSW[45]), .Y(n1407) );
AO22XLTS U3690 ( .A0(n2863), .A1(DMP_SHT1_EWSW[45]), .B0(n2881), .B1(
DMP_SHT2_EWSW[45]), .Y(n1406) );
AO22XLTS U3691 ( .A0(n2867), .A1(DMP_EXP_EWSW[46]), .B0(n3463), .B1(
DMP_SHT1_EWSW[46]), .Y(n1404) );
AO22XLTS U3692 ( .A0(n2863), .A1(DMP_SHT1_EWSW[46]), .B0(n2881), .B1(
DMP_SHT2_EWSW[46]), .Y(n1403) );
AO22XLTS U3693 ( .A0(n2867), .A1(DMP_EXP_EWSW[47]), .B0(n3463), .B1(
DMP_SHT1_EWSW[47]), .Y(n1401) );
AO22XLTS U3694 ( .A0(n2863), .A1(DMP_SHT1_EWSW[47]), .B0(n2881), .B1(
DMP_SHT2_EWSW[47]), .Y(n1400) );
BUFX4TS U3695 ( .A(n2877), .Y(n2879) );
AO22XLTS U3696 ( .A0(n2867), .A1(DMP_EXP_EWSW[48]), .B0(n2879), .B1(
DMP_SHT1_EWSW[48]), .Y(n1398) );
AO22XLTS U3697 ( .A0(n2863), .A1(DMP_SHT1_EWSW[48]), .B0(n2881), .B1(
DMP_SHT2_EWSW[48]), .Y(n1397) );
AO22XLTS U3698 ( .A0(n2867), .A1(DMP_EXP_EWSW[49]), .B0(n2879), .B1(
DMP_SHT1_EWSW[49]), .Y(n1395) );
AO22XLTS U3699 ( .A0(n2863), .A1(DMP_SHT1_EWSW[49]), .B0(n2881), .B1(
DMP_SHT2_EWSW[49]), .Y(n1394) );
AO22XLTS U3700 ( .A0(n2867), .A1(DMP_EXP_EWSW[50]), .B0(n2879), .B1(
DMP_SHT1_EWSW[50]), .Y(n1392) );
AO22XLTS U3701 ( .A0(n2862), .A1(DMP_SHT1_EWSW[50]), .B0(n2881), .B1(
DMP_SHT2_EWSW[50]), .Y(n1391) );
AO22XLTS U3702 ( .A0(n2867), .A1(DMP_EXP_EWSW[51]), .B0(n2879), .B1(
DMP_SHT1_EWSW[51]), .Y(n1389) );
AO22XLTS U3703 ( .A0(n2863), .A1(DMP_SHT1_EWSW[51]), .B0(n2881), .B1(
DMP_SHT2_EWSW[51]), .Y(n1388) );
AO22XLTS U3704 ( .A0(n2867), .A1(DMP_EXP_EWSW[52]), .B0(n2879), .B1(
DMP_SHT1_EWSW[52]), .Y(n1386) );
AO22XLTS U3705 ( .A0(n2863), .A1(DMP_SHT1_EWSW[52]), .B0(n2881), .B1(
DMP_SHT2_EWSW[52]), .Y(n1385) );
CLKBUFX2TS U3706 ( .A(n2852), .Y(n3298) );
AO22XLTS U3707 ( .A0(n3261), .A1(DMP_SHT2_EWSW[52]), .B0(n3295), .B1(
DMP_SFG[52]), .Y(n1384) );
AO22XLTS U3708 ( .A0(n3136), .A1(DMP_SFG[52]), .B0(n3088), .B1(
DMP_exp_NRM_EW[0]), .Y(n1383) );
AO22XLTS U3709 ( .A0(n2867), .A1(DMP_EXP_EWSW[53]), .B0(n2879), .B1(
DMP_SHT1_EWSW[53]), .Y(n1381) );
AO22XLTS U3710 ( .A0(n2863), .A1(DMP_SHT1_EWSW[53]), .B0(n3462), .B1(
DMP_SHT2_EWSW[53]), .Y(n1380) );
AO22XLTS U3711 ( .A0(n3261), .A1(DMP_SHT2_EWSW[53]), .B0(n3295), .B1(
DMP_SFG[53]), .Y(n1379) );
AO22XLTS U3712 ( .A0(n3136), .A1(DMP_SFG[53]), .B0(n3527), .B1(
DMP_exp_NRM_EW[1]), .Y(n1378) );
AO22XLTS U3713 ( .A0(n3528), .A1(DMP_EXP_EWSW[54]), .B0(n2879), .B1(
DMP_SHT1_EWSW[54]), .Y(n1376) );
AO22XLTS U3714 ( .A0(n2863), .A1(DMP_SHT1_EWSW[54]), .B0(n3462), .B1(
DMP_SHT2_EWSW[54]), .Y(n1375) );
AO22XLTS U3715 ( .A0(n3261), .A1(DMP_SHT2_EWSW[54]), .B0(n3295), .B1(
DMP_SFG[54]), .Y(n1374) );
AO22XLTS U3716 ( .A0(n3024), .A1(DMP_SFG[54]), .B0(n3527), .B1(
DMP_exp_NRM_EW[2]), .Y(n1373) );
AO22XLTS U3717 ( .A0(n3528), .A1(DMP_EXP_EWSW[55]), .B0(n2879), .B1(
DMP_SHT1_EWSW[55]), .Y(n1371) );
AO22XLTS U3718 ( .A0(n2882), .A1(DMP_SHT1_EWSW[55]), .B0(n2881), .B1(
DMP_SHT2_EWSW[55]), .Y(n1370) );
AO22XLTS U3719 ( .A0(n3261), .A1(DMP_SHT2_EWSW[55]), .B0(n3130), .B1(
DMP_SFG[55]), .Y(n1369) );
AO22XLTS U3720 ( .A0(n3528), .A1(DMP_EXP_EWSW[56]), .B0(n2879), .B1(
DMP_SHT1_EWSW[56]), .Y(n1366) );
AO22XLTS U3721 ( .A0(n2882), .A1(DMP_SHT1_EWSW[56]), .B0(n2881), .B1(
DMP_SHT2_EWSW[56]), .Y(n1365) );
AO22XLTS U3722 ( .A0(n3261), .A1(DMP_SHT2_EWSW[56]), .B0(n2864), .B1(
DMP_SFG[56]), .Y(n1364) );
AO22XLTS U3723 ( .A0(n3528), .A1(DMP_EXP_EWSW[57]), .B0(n2879), .B1(
DMP_SHT1_EWSW[57]), .Y(n1361) );
AO22XLTS U3724 ( .A0(n2882), .A1(DMP_SHT1_EWSW[57]), .B0(n2881), .B1(
DMP_SHT2_EWSW[57]), .Y(n1360) );
AO22XLTS U3725 ( .A0(n3261), .A1(DMP_SHT2_EWSW[57]), .B0(n3130), .B1(
DMP_SFG[57]), .Y(n1359) );
AO22XLTS U3726 ( .A0(n3528), .A1(DMP_EXP_EWSW[58]), .B0(n2865), .B1(
DMP_SHT1_EWSW[58]), .Y(n1356) );
AO22XLTS U3727 ( .A0(n2882), .A1(DMP_SHT1_EWSW[58]), .B0(n2881), .B1(
DMP_SHT2_EWSW[58]), .Y(n1355) );
AO22XLTS U3728 ( .A0(n3261), .A1(DMP_SHT2_EWSW[58]), .B0(n2864), .B1(
DMP_SFG[58]), .Y(n1354) );
AO22XLTS U3729 ( .A0(n3528), .A1(DMP_EXP_EWSW[59]), .B0(n2865), .B1(
DMP_SHT1_EWSW[59]), .Y(n1351) );
AO22XLTS U3730 ( .A0(n2882), .A1(DMP_SHT1_EWSW[59]), .B0(n2881), .B1(
DMP_SHT2_EWSW[59]), .Y(n1350) );
AO22XLTS U3731 ( .A0(n3261), .A1(DMP_SHT2_EWSW[59]), .B0(n3130), .B1(
DMP_SFG[59]), .Y(n1349) );
AO22XLTS U3732 ( .A0(n3528), .A1(DMP_EXP_EWSW[60]), .B0(n2865), .B1(
DMP_SHT1_EWSW[60]), .Y(n1346) );
AO22XLTS U3733 ( .A0(n2882), .A1(DMP_SHT1_EWSW[60]), .B0(n2881), .B1(
DMP_SHT2_EWSW[60]), .Y(n1345) );
AO22XLTS U3734 ( .A0(n3261), .A1(DMP_SHT2_EWSW[60]), .B0(n3130), .B1(
DMP_SFG[60]), .Y(n1344) );
AO22XLTS U3735 ( .A0(n3528), .A1(DMP_EXP_EWSW[61]), .B0(n2865), .B1(
DMP_SHT1_EWSW[61]), .Y(n1341) );
AO22XLTS U3736 ( .A0(n2882), .A1(DMP_SHT1_EWSW[61]), .B0(n2881), .B1(
DMP_SHT2_EWSW[61]), .Y(n1340) );
AO22XLTS U3737 ( .A0(n3261), .A1(DMP_SHT2_EWSW[61]), .B0(n3130), .B1(
DMP_SFG[61]), .Y(n1339) );
AO22XLTS U3738 ( .A0(n3090), .A1(DMP_SFG[61]), .B0(n2921), .B1(
DMP_exp_NRM_EW[9]), .Y(n1338) );
AO22XLTS U3739 ( .A0(n3528), .A1(DMP_EXP_EWSW[62]), .B0(n2865), .B1(
DMP_SHT1_EWSW[62]), .Y(n1336) );
AO22XLTS U3740 ( .A0(n2882), .A1(DMP_SHT1_EWSW[62]), .B0(n2881), .B1(
DMP_SHT2_EWSW[62]), .Y(n1335) );
AO22XLTS U3741 ( .A0(n3261), .A1(DMP_SHT2_EWSW[62]), .B0(n3130), .B1(
DMP_SFG[62]), .Y(n1334) );
AO22XLTS U3742 ( .A0(n3528), .A1(DmP_EXP_EWSW[0]), .B0(n2865), .B1(n1927),
.Y(n1330) );
AO22XLTS U3743 ( .A0(n3528), .A1(DmP_EXP_EWSW[1]), .B0(n2865), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1328) );
AO22XLTS U3744 ( .A0(n3528), .A1(DmP_EXP_EWSW[2]), .B0(n2865), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1326) );
AO22XLTS U3745 ( .A0(n3528), .A1(DmP_EXP_EWSW[16]), .B0(n2865), .B1(
DmP_mant_SHT1_SW[16]), .Y(n1298) );
BUFX3TS U3746 ( .A(n3463), .Y(n2870) );
BUFX4TS U3747 ( .A(n2870), .Y(n2869) );
AO22XLTS U3748 ( .A0(n3528), .A1(DmP_EXP_EWSW[20]), .B0(n2869), .B1(
DmP_mant_SHT1_SW[20]), .Y(n1290) );
AO22XLTS U3749 ( .A0(n3528), .A1(DmP_EXP_EWSW[24]), .B0(n2869), .B1(n1921),
.Y(n1282) );
INVX2TS U3750 ( .A(n3463), .Y(n2878) );
OAI222X1TS U3751 ( .A0(n2874), .A1(n3358), .B0(n3353), .B1(n2873), .C0(n3312), .C1(n2871), .Y(n1225) );
OAI222X1TS U3752 ( .A0(n2874), .A1(n3465), .B0(n3360), .B1(n2873), .C0(n3309), .C1(n2872), .Y(n1224) );
OAI222X1TS U3753 ( .A0(n2874), .A1(n3314), .B0(n3357), .B1(n2873), .C0(n3310), .C1(n2872), .Y(n1223) );
NAND2X1TS U3754 ( .A(n3468), .B(n2884), .Y(n2875) );
OAI2BB1X1TS U3755 ( .A0N(underflow_flag), .A1N(n3225), .B0(n2875), .Y(n1221)
);
OA21XLTS U3756 ( .A0(n3468), .A1(overflow_flag), .B0(n2876), .Y(n1220) );
AO22XLTS U3757 ( .A0(n2878), .A1(ZERO_FLAG_EXP), .B0(n3463), .B1(
ZERO_FLAG_SHT1), .Y(n1219) );
AO22XLTS U3758 ( .A0(n2882), .A1(ZERO_FLAG_SHT1), .B0(n2881), .B1(
ZERO_FLAG_SHT2), .Y(n1218) );
AO22XLTS U3759 ( .A0(n3261), .A1(ZERO_FLAG_SHT2), .B0(n3130), .B1(
ZERO_FLAG_SFG), .Y(n1217) );
AO22XLTS U3760 ( .A0(n3468), .A1(ZERO_FLAG_SHT1SHT2), .B0(n3225), .B1(
zero_flag), .Y(n1214) );
AO22XLTS U3761 ( .A0(n2878), .A1(OP_FLAG_EXP), .B0(n2877), .B1(OP_FLAG_SHT1),
.Y(n1213) );
AO22XLTS U3762 ( .A0(n2882), .A1(OP_FLAG_SHT1), .B0(n2881), .B1(OP_FLAG_SHT2), .Y(n1212) );
AO22XLTS U3763 ( .A0(n2880), .A1(SIGN_FLAG_EXP), .B0(n2879), .B1(
SIGN_FLAG_SHT1), .Y(n1210) );
AO22XLTS U3764 ( .A0(n2882), .A1(SIGN_FLAG_SHT1), .B0(n2881), .B1(
SIGN_FLAG_SHT2), .Y(n1209) );
AO22XLTS U3765 ( .A0(n3261), .A1(SIGN_FLAG_SHT2), .B0(n3130), .B1(
SIGN_FLAG_SFG), .Y(n1208) );
OAI211XLTS U3766 ( .A0(n2884), .A1(SIGN_FLAG_SHT1SHT2), .B0(n3468), .C0(
n2883), .Y(n2885) );
OAI2BB1X1TS U3767 ( .A0N(final_result_ieee[63]), .A1N(n3225), .B0(n2885),
.Y(n1205) );
AO22XLTS U3768 ( .A0(n3527), .A1(Raw_mant_NRM_SWR[14]), .B0(n3090), .B1(
n2888), .Y(n1204) );
AO22XLTS U3769 ( .A0(n3134), .A1(Raw_mant_NRM_SWR[24]), .B0(n3136), .B1(
n2912), .Y(n1194) );
AO22XLTS U3770 ( .A0(n3527), .A1(Raw_mant_NRM_SWR[34]), .B0(n3136), .B1(
n2937), .Y(n1184) );
AOI2BB2XLTS U3771 ( .B0(n1905), .B1(n1999), .A0N(n2986), .A1N(n1905), .Y(
n2975) );
AOI2BB2XLTS U3772 ( .B0(n1904), .B1(n3076), .A0N(n2986), .A1N(n1904), .Y(
n2978) );
AOI2BB2XLTS U3773 ( .B0(n1903), .B1(n1999), .A0N(n2986), .A1N(n1903), .Y(
n2981) );
AOI2BB2XLTS U3774 ( .B0(n1902), .B1(n3076), .A0N(n2986), .A1N(n1902), .Y(
n2983) );
XNOR2X1TS U3775 ( .A(n2983), .B(n2982), .Y(n2984) );
AOI22X1TS U3776 ( .A0(n3285), .A1(n2985), .B0(n3293), .B1(n1980), .Y(n1163)
);
AOI2BB2X1TS U3777 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n2986), .A0N(n2986),
.A1N(DmP_mant_SFG_SWR[10]), .Y(n3109) );
CLKAND2X2TS U3778 ( .A(n3109), .B(DMP_SFG[8]), .Y(n2987) );
INVX2TS U3779 ( .A(n3131), .Y(n2988) );
AOI222X1TS U3780 ( .A0(n3133), .A1(n2988), .B0(n3133), .B1(DMP_SFG[10]),
.C0(n2988), .C1(DMP_SFG[10]), .Y(n2989) );
XOR2XLTS U3781 ( .A(n1896), .B(n2989), .Y(n2990) );
AOI22X1TS U3782 ( .A0(n3090), .A1(n2991), .B0(n3315), .B1(n3134), .Y(n1162)
);
AOI22X1TS U3783 ( .A0(n1943), .A1(n3054), .B0(Data_array_SWR[23]), .B1(n3188), .Y(n2993) );
AOI22X1TS U3784 ( .A0(n1936), .A1(n2159), .B0(n1952), .B1(n3189), .Y(n2992)
);
NAND2X1TS U3785 ( .A(n2993), .B(n2992), .Y(n3231) );
AOI22X1TS U3786 ( .A0(Data_array_SWR[14]), .A1(n3080), .B0(
Data_array_SWR[17]), .B1(n2142), .Y(n2995) );
AOI22X1TS U3787 ( .A0(Data_array_SWR[11]), .A1(n2159), .B0(Data_array_SWR[9]), .B1(n3189), .Y(n2994) );
AOI21X1TS U3788 ( .A0(n2995), .A1(n2994), .B0(n2127), .Y(n3000) );
NAND2X1TS U3789 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[5]),
.Y(n3018) );
BUFX3TS U3790 ( .A(n2996), .Y(n3247) );
AOI22X1TS U3791 ( .A0(n1944), .A1(n3228), .B0(Data_array_SWR[1]), .B1(n3247),
.Y(n2998) );
AOI22X1TS U3792 ( .A0(n1940), .A1(n3198), .B0(Data_array_SWR[5]), .B1(n3227),
.Y(n2997) );
OAI211XLTS U3793 ( .A0(n3243), .A1(n3018), .B0(n2998), .C0(n2997), .Y(n2999)
);
AOI211X1TS U3794 ( .A0(n2168), .A1(n3231), .B0(n3000), .C0(n2999), .Y(n3251)
);
NAND2X1TS U3795 ( .A(left_right_SHT2), .B(n3247), .Y(n3033) );
OAI22X1TS U3796 ( .A0(n3239), .A1(n3251), .B0(n3428), .B1(n3033), .Y(n3001)
);
AOI2BB2XLTS U3797 ( .B0(DmP_mant_SFG_SWR[1]), .B1(n3467), .A0N(n3037), .A1N(
DmP_mant_SFG_SWR[1]), .Y(n3002) );
AOI2BB2XLTS U3798 ( .B0(n3090), .B1(n3002), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n1825), .Y(n1159) );
AOI22X1TS U3799 ( .A0(n1956), .A1(n3054), .B0(Data_array_SWR[13]), .B1(n3188), .Y(n3004) );
AOI22X1TS U3800 ( .A0(Data_array_SWR[8]), .A1(n3115), .B0(n1958), .B1(n3125),
.Y(n3003) );
AOI21X1TS U3801 ( .A0(n3004), .A1(n3003), .B0(n2127), .Y(n3008) );
AOI22X1TS U3802 ( .A0(n1945), .A1(n3180), .B0(Data_array_SWR[0]), .B1(n3247),
.Y(n3006) );
AOI22X1TS U3803 ( .A0(n1939), .A1(n3198), .B0(Data_array_SWR[4]), .B1(n3122),
.Y(n3005) );
OAI211XLTS U3804 ( .A0(n3173), .A1(n3018), .B0(n3006), .C0(n3005), .Y(n3007)
);
AOI211X1TS U3805 ( .A0(n2168), .A1(n3009), .B0(n3008), .C0(n3007), .Y(n3304)
);
OAI22X1TS U3806 ( .A0(n3239), .A1(n3304), .B0(n3429), .B1(n3033), .Y(n3010)
);
AOI2BB2XLTS U3807 ( .B0(DmP_mant_SFG_SWR[0]), .B1(n3467), .A0N(n3467), .A1N(
DmP_mant_SFG_SWR[0]), .Y(n3011) );
AOI22X1TS U3808 ( .A0(n1825), .A1(n3011), .B0(n3329), .B1(n3134), .Y(n1156)
);
AOI22X1TS U3809 ( .A0(Data_array_SWR[27]), .A1(n3054), .B0(
Data_array_SWR[24]), .B1(n3188), .Y(n3013) );
AOI22X1TS U3810 ( .A0(n1953), .A1(n3115), .B0(n1935), .B1(n3125), .Y(n3012)
);
NAND2X1TS U3811 ( .A(n3013), .B(n3012), .Y(n3182) );
AOI22X1TS U3812 ( .A0(n1957), .A1(n3054), .B0(Data_array_SWR[15]), .B1(n3188), .Y(n3015) );
AOI22X1TS U3813 ( .A0(n1959), .A1(n2159), .B0(n1951), .B1(n3189), .Y(n3014)
);
AOI21X1TS U3814 ( .A0(n3015), .A1(n3014), .B0(n2127), .Y(n3020) );
AOI22X1TS U3815 ( .A0(n1947), .A1(n3180), .B0(Data_array_SWR[2]), .B1(n3247),
.Y(n3017) );
AOI22X1TS U3816 ( .A0(n1941), .A1(n3198), .B0(Data_array_SWR[6]), .B1(n3122),
.Y(n3016) );
OAI211XLTS U3817 ( .A0(n3213), .A1(n3018), .B0(n3017), .C0(n3016), .Y(n3019)
);
AOI211X1TS U3818 ( .A0(n2168), .A1(n3182), .B0(n3020), .C0(n3019), .Y(n3250)
);
INVX2TS U3819 ( .A(n1948), .Y(n3249) );
OAI22X1TS U3820 ( .A0(n3239), .A1(n3250), .B0(n3249), .B1(n3033), .Y(n3246)
);
AOI2BB2X1TS U3821 ( .B0(DmP_mant_SFG_SWR[2]), .B1(n3526), .A0N(n3075), .A1N(
DmP_mant_SFG_SWR[2]), .Y(n3021) );
NAND2X1TS U3822 ( .A(n3021), .B(DMP_SFG[0]), .Y(n3034) );
AOI22X1TS U3823 ( .A0(n3024), .A1(n3022), .B0(n3328), .B1(n3134), .Y(n1153)
);
XNOR2X1TS U3824 ( .A(DMP_SFG[1]), .B(n3034), .Y(n3023) );
XNOR2X1TS U3825 ( .A(n3023), .B(n3035), .Y(n3025) );
AOI2BB2XLTS U3826 ( .B0(n1825), .B1(n3025), .A0N(Raw_mant_NRM_SWR[3]), .A1N(
n3136), .Y(n1152) );
AOI22X1TS U3827 ( .A0(Data_array_SWR[28]), .A1(n3054), .B0(
Data_array_SWR[25]), .B1(n3188), .Y(n3026) );
OAI2BB1X1TS U3828 ( .A0N(Data_array_SWR[21]), .A1N(n3125), .B0(n3026), .Y(
n3027) );
AOI21X1TS U3829 ( .A0(n1949), .A1(n3115), .B0(n3027), .Y(n3210) );
AO22XLTS U3830 ( .A0(Data_array_SWR[7]), .A1(n3122), .B0(Data_array_SWR[3]),
.B1(n3247), .Y(n3032) );
AOI22X1TS U3831 ( .A0(n1955), .A1(n3054), .B0(Data_array_SWR[16]), .B1(n3188), .Y(n3030) );
AOI22X1TS U3832 ( .A0(n1946), .A1(n3180), .B0(n1942), .B1(n3226), .Y(n3029)
);
AOI22X1TS U3833 ( .A0(Data_array_SWR[12]), .A1(n2159), .B0(
Data_array_SWR[10]), .B1(n3189), .Y(n3028) );
AOI32X1TS U3834 ( .A0(n3030), .A1(n3029), .A2(n3028), .B0(n2127), .B1(n3029),
.Y(n3031) );
AOI211X1TS U3835 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1901), .B0(n3032),
.C0(n3031), .Y(n3248) );
OAI22X1TS U3836 ( .A0(left_right_SHT2), .A1(n3248), .B0(n3427), .B1(n3033),
.Y(n3245) );
AO22XLTS U3837 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[3]), .B0(n2854), .B1(n3245), .Y(n1150) );
AOI2BB2X1TS U3838 ( .B0(DmP_mant_SFG_SWR[4]), .B1(n3467), .A0N(n3467), .A1N(
DmP_mant_SFG_SWR[4]), .Y(n3065) );
INVX2TS U3839 ( .A(n3034), .Y(n3036) );
AOI2BB2X2TS U3840 ( .B0(DmP_mant_SFG_SWR[5]), .B1(n3467), .A0N(n3037), .A1N(
DmP_mant_SFG_SWR[5]), .Y(n3049) );
AOI2BB2XLTS U3841 ( .B0(DMP_SFG[3]), .B1(n3049), .A0N(n3049), .A1N(
DMP_SFG[3]), .Y(n3038) );
XNOR2X1TS U3842 ( .A(n3039), .B(n3038), .Y(n3040) );
AOI2BB2XLTS U3843 ( .B0(n3024), .B1(n3040), .A0N(Raw_mant_NRM_SWR[5]), .A1N(
n3136), .Y(n1149) );
AOI22X1TS U3844 ( .A0(Data_array_SWR[30]), .A1(n3054), .B0(n1943), .B1(n3188), .Y(n3041) );
OAI21XLTS U3845 ( .A0(n3455), .A1(n3056), .B0(n3041), .Y(n3042) );
AOI21X1TS U3846 ( .A0(Data_array_SWR[23]), .A1(n3125), .B0(n3042), .Y(n3220)
);
AO22XLTS U3847 ( .A0(n1940), .A1(n3122), .B0(Data_array_SWR[5]), .B1(n3247),
.Y(n3047) );
AOI22X1TS U3848 ( .A0(n1952), .A1(n3054), .B0(Data_array_SWR[17]), .B1(n3188), .Y(n3045) );
AOI22X1TS U3849 ( .A0(Data_array_SWR[9]), .A1(n3180), .B0(n1944), .B1(n3226),
.Y(n3044) );
AOI22X1TS U3850 ( .A0(Data_array_SWR[11]), .A1(n3115), .B0(
Data_array_SWR[14]), .B1(n3125), .Y(n3043) );
AOI32X1TS U3851 ( .A0(n3045), .A1(n3044), .A2(n3043), .B0(n2127), .B1(n3044),
.Y(n3046) );
OAI22X1TS U3852 ( .A0(n3243), .A1(n3197), .B0(n3239), .B1(n3244), .Y(n3215)
);
AO22XLTS U3853 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[5]), .B0(n3297), .B1(n3215), .Y(n1147) );
NAND2BXLTS U3854 ( .AN(n3065), .B(DMP_SFG[2]), .Y(n3048) );
AOI222X1TS U3855 ( .A0(n3461), .A1(n3049), .B0(n3461), .B1(n3048), .C0(n3049), .C1(n3048), .Y(n3086) );
XNOR2X1TS U3856 ( .A(DMP_SFG[5]), .B(n3050), .Y(n3051) );
XOR2X1TS U3857 ( .A(n3052), .B(n3051), .Y(n3053) );
AOI22X1TS U3858 ( .A0(n3136), .A1(n3053), .B0(n3330), .B1(n3134), .Y(n1146)
);
AOI22X1TS U3859 ( .A0(Data_array_SWR[29]), .A1(n3054), .B0(
Data_array_SWR[26]), .B1(n3188), .Y(n3055) );
AOI21X1TS U3860 ( .A0(Data_array_SWR[22]), .A1(n3125), .B0(n3057), .Y(n3178)
);
AO22XLTS U3861 ( .A0(n1939), .A1(n3122), .B0(Data_array_SWR[4]), .B1(n3247),
.Y(n3063) );
AOI22X1TS U3862 ( .A0(n1954), .A1(n2142), .B0(n1956), .B1(n3080), .Y(n3061)
);
AOI22X1TS U3863 ( .A0(Data_array_SWR[8]), .A1(n3180), .B0(n1945), .B1(n3226),
.Y(n3060) );
AOI22X1TS U3864 ( .A0(Data_array_SWR[13]), .A1(n2159), .B0(n1958), .B1(n3189), .Y(n3059) );
AOI32X1TS U3865 ( .A0(n3061), .A1(n3060), .A2(n3059), .B0(n2127), .B1(n3060),
.Y(n3062) );
OAI22X1TS U3866 ( .A0(left_right_SHT2), .A1(n3214), .B0(n3213), .B1(n3197),
.Y(n3212) );
AO22XLTS U3867 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[4]), .B0(n2854), .B1(n3212), .Y(n1145) );
CMPR32X2TS U3868 ( .A(n3466), .B(n3065), .C(n3064), .CO(n3039), .S(n3066) );
AOI22X1TS U3869 ( .A0(n3136), .A1(n3066), .B0(n3323), .B1(n3134), .Y(n1144)
);
AOI22X1TS U3870 ( .A0(Data_array_SWR[28]), .A1(n3080), .B0(
Data_array_SWR[32]), .B1(n2142), .Y(n3068) );
AOI22X1TS U3871 ( .A0(Data_array_SWR[25]), .A1(n2159), .B0(
Data_array_SWR[21]), .B1(n3189), .Y(n3067) );
NAND2X2TS U3872 ( .A(n3068), .B(n3067), .Y(n3203) );
AOI22X1TS U3873 ( .A0(Data_array_SWR[12]), .A1(n3115), .B0(n1949), .B1(n2142), .Y(n3069) );
OAI2BB1X1TS U3874 ( .A0N(n1955), .A1N(n3080), .B0(n3069), .Y(n3070) );
AOI22X1TS U3875 ( .A0(n1946), .A1(n3198), .B0(n1942), .B1(n3122), .Y(n3072)
);
AOI22X1TS U3876 ( .A0(Data_array_SWR[10]), .A1(n3180), .B0(Data_array_SWR[7]), .B1(n3247), .Y(n3071) );
OAI211XLTS U3877 ( .A0(n1858), .A1(n2127), .B0(n3072), .C0(n3071), .Y(n3073)
);
AOI21X1TS U3878 ( .A0(n2168), .A1(n3203), .B0(n3073), .Y(n3206) );
OAI22X1TS U3879 ( .A0(left_right_SHT2), .A1(n3206), .B0(n3205), .B1(n3197),
.Y(n3187) );
AO22XLTS U3880 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[7]), .B0(n3292), .B1(n3187), .Y(n1143) );
CMPR32X2TS U3881 ( .A(n1931), .B(n3074), .C(n3096), .CO(n3078), .S(n2094) );
XNOR2X1TS U3882 ( .A(DMP_SFG[7]), .B(n3098), .Y(n3077) );
XOR2X1TS U3883 ( .A(n3078), .B(n3077), .Y(n3079) );
AOI22X1TS U3884 ( .A0(n3136), .A1(n3079), .B0(n3317), .B1(n3134), .Y(n1142)
);
AO22XLTS U3885 ( .A0(n1941), .A1(n3122), .B0(Data_array_SWR[6]), .B1(n3247),
.Y(n3085) );
AOI22X1TS U3886 ( .A0(n1957), .A1(n3080), .B0(n1953), .B1(n2142), .Y(n3083)
);
AOI22X1TS U3887 ( .A0(n1947), .A1(n3198), .B0(n1951), .B1(n3228), .Y(n3082)
);
AOI22X1TS U3888 ( .A0(Data_array_SWR[15]), .A1(n2159), .B0(n1959), .B1(n3189), .Y(n3081) );
AOI32X1TS U3889 ( .A0(n3083), .A1(n3082), .A2(n3081), .B0(n2127), .B1(n3082),
.Y(n3084) );
AOI211X1TS U3890 ( .A0(shift_value_SHT2_EWR[5]), .A1(n1900), .B0(n3085),
.C0(n3084), .Y(n3174) );
OAI22X1TS U3891 ( .A0(n3239), .A1(n3174), .B0(n3173), .B1(n3197), .Y(n3171)
);
AO22XLTS U3892 ( .A0(n3307), .A1(n1915), .B0(n3292), .B1(n3171), .Y(n1141)
);
CMPR32X2TS U3893 ( .A(n1932), .B(n3087), .C(n3086), .CO(n3052), .S(n3089) );
AOI22X1TS U3894 ( .A0(Data_array_SWR[14]), .A1(n3115), .B0(n1952), .B1(n3188), .Y(n3091) );
AOI22X1TS U3895 ( .A0(Data_array_SWR[9]), .A1(n3198), .B0(n1944), .B1(n3122),
.Y(n3094) );
AOI22X1TS U3896 ( .A0(Data_array_SWR[11]), .A1(n3180), .B0(n1940), .B1(n3247), .Y(n3093) );
AOI21X1TS U3897 ( .A0(n2168), .A1(n3163), .B0(n3095), .Y(n3170) );
OAI22X1TS U3898 ( .A0(n3239), .A1(n3170), .B0(n3169), .B1(n3197), .Y(n3160)
);
AO22XLTS U3899 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[9]), .B0(n2854), .B1(n3160), .Y(n1139) );
OAI211XLTS U3900 ( .A0(DMP_SFG[7]), .A1(n3098), .B0(n1931), .C0(n3096), .Y(
n3097) );
OAI2BB1X1TS U3901 ( .A0N(n3098), .A1N(DMP_SFG[7]), .B0(n3097), .Y(n3108) );
XNOR2X1TS U3902 ( .A(DMP_SFG[9]), .B(n3099), .Y(n3100) );
XOR2X1TS U3903 ( .A(n3101), .B(n3100), .Y(n3102) );
AOI22X1TS U3904 ( .A0(n3136), .A1(n3102), .B0(n3308), .B1(n3134), .Y(n1138)
);
AOI22X1TS U3905 ( .A0(n1953), .A1(n3080), .B0(Data_array_SWR[15]), .B1(n3115), .Y(n3103) );
AOI22X1TS U3906 ( .A0(n1947), .A1(n3227), .B0(n1951), .B1(n3226), .Y(n3106)
);
AOI22X1TS U3907 ( .A0(n1941), .A1(n3229), .B0(n1959), .B1(n3228), .Y(n3105)
);
OAI211XLTS U3908 ( .A0(n1897), .A1(n2127), .B0(n3106), .C0(n3105), .Y(n3107)
);
AOI21X1TS U3909 ( .A0(n2168), .A1(n3140), .B0(n3107), .Y(n3114) );
OAI22X1TS U3910 ( .A0(n3239), .A1(n3114), .B0(n3137), .B1(n3197), .Y(n3113)
);
AO22XLTS U3911 ( .A0(n3527), .A1(Raw_mant_NRM_SWR[10]), .B0(n3136), .B1(
n3110), .Y(n1135) );
OAI22X1TS U3912 ( .A0(n3114), .A1(n3303), .B0(n3137), .B1(n3242), .Y(n3287)
);
AOI22X1TS U3913 ( .A0(n1954), .A1(n3188), .B0(Data_array_SWR[13]), .B1(n3115), .Y(n3116) );
AOI22X1TS U3914 ( .A0(Data_array_SWR[8]), .A1(n3198), .B0(n1945), .B1(n3122),
.Y(n3120) );
AOI22X1TS U3915 ( .A0(n1958), .A1(n3180), .B0(n1939), .B1(n3247), .Y(n3119)
);
OAI211XLTS U3916 ( .A0(n3153), .A1(n2127), .B0(n3120), .C0(n3119), .Y(n3121)
);
AOI21X1TS U3917 ( .A0(n2168), .A1(n3148), .B0(n3121), .Y(n3159) );
OAI22X1TS U3918 ( .A0(n3239), .A1(n3159), .B0(n3158), .B1(n3197), .Y(n3157)
);
AO22XLTS U3919 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[8]), .B0(n2858), .B1(n3157), .Y(n1132) );
AOI22X1TS U3920 ( .A0(Data_array_SWR[10]), .A1(n3198), .B0(n1946), .B1(n3122), .Y(n3124) );
AOI22X1TS U3921 ( .A0(Data_array_SWR[12]), .A1(n3180), .B0(n1942), .B1(n3229), .Y(n3123) );
OAI211X1TS U3922 ( .A0(n3156), .A1(n3201), .B0(n3124), .C0(n3123), .Y(n3128)
);
AO22XLTS U3923 ( .A0(Data_array_SWR[21]), .A1(n2142), .B0(n1949), .B1(n3080),
.Y(n3127) );
AO22XLTS U3924 ( .A0(n1955), .A1(n3125), .B0(Data_array_SWR[16]), .B1(n3189),
.Y(n3126) );
OAI22X1TS U3925 ( .A0(n3239), .A1(n3155), .B0(n3156), .B1(n3197), .Y(n3154)
);
XNOR2X1TS U3926 ( .A(DMP_SFG[10]), .B(n3131), .Y(n3132) );
XNOR2X1TS U3927 ( .A(n3133), .B(n3132), .Y(n3135) );
AOI22X1TS U3928 ( .A0(n1825), .A1(n3135), .B0(n3327), .B1(n3134), .Y(n1129)
);
INVX2TS U3929 ( .A(n3137), .Y(n3142) );
AOI22X1TS U3930 ( .A0(n3221), .A1(n3141), .B0(n3222), .B1(n3142), .Y(n3139)
);
NAND2X1TS U3931 ( .A(n2156), .B(n3140), .Y(n3138) );
AOI22X1TS U3932 ( .A0(n3223), .A1(n3141), .B0(n3222), .B1(n3140), .Y(n3144)
);
NAND2X1TS U3933 ( .A(n2156), .B(n3142), .Y(n3143) );
AOI22X1TS U3934 ( .A0(n3285), .A1(n3145), .B0(n1986), .B1(n3293), .Y(n1122)
);
INVX2TS U3935 ( .A(n3158), .Y(n3150) );
AOI22X1TS U3936 ( .A0(n3221), .A1(n3149), .B0(n3222), .B1(n3150), .Y(n3147)
);
NAND2X1TS U3937 ( .A(n2156), .B(n3148), .Y(n3146) );
AO22XLTS U3938 ( .A0(n3172), .A1(n3265), .B0(final_result_ieee[22]), .B1(
n3225), .Y(n1118) );
AOI22X1TS U3939 ( .A0(n3223), .A1(n3149), .B0(n3222), .B1(n3148), .Y(n3152)
);
NAND2X1TS U3940 ( .A(n2156), .B(n3150), .Y(n3151) );
OAI22X1TS U3941 ( .A0(n3156), .A1(n3242), .B0(n3155), .B1(n3303), .Y(n3286)
);
AO22XLTS U3942 ( .A0(n3172), .A1(n3286), .B0(final_result_ieee[41]), .B1(
n3240), .Y(n1113) );
OAI22X1TS U3943 ( .A0(n3159), .A1(n3361), .B0(n3158), .B1(n3242), .Y(n3289)
);
INVX2TS U3944 ( .A(n3169), .Y(n3165) );
AOI22X1TS U3945 ( .A0(n3221), .A1(n3164), .B0(n3222), .B1(n3165), .Y(n3162)
);
NAND2X1TS U3946 ( .A(n2156), .B(n3163), .Y(n3161) );
OAI211X1TS U3947 ( .A0(n3168), .A1(n3242), .B0(n3162), .C0(n3161), .Y(n3266)
);
AOI22X1TS U3948 ( .A0(n3223), .A1(n3164), .B0(n3222), .B1(n3163), .Y(n3167)
);
NAND2X1TS U3949 ( .A(n2156), .B(n3165), .Y(n3166) );
OAI211X1TS U3950 ( .A0(n3168), .A1(n3197), .B0(n3167), .C0(n3166), .Y(n3270)
);
OAI22X1TS U3951 ( .A0(n3170), .A1(n3361), .B0(n3169), .B1(n3242), .Y(n3288)
);
OAI22X1TS U3952 ( .A0(n3174), .A1(n3303), .B0(n3173), .B1(n3242), .Y(n3291)
);
AOI22X1TS U3953 ( .A0(Data_array_SWR[13]), .A1(n3227), .B0(n1958), .B1(n3247), .Y(n3177) );
OAI2BB2XLTS U3954 ( .B0(n3249), .B1(n3216), .A0N(n1956), .A1N(n3226), .Y(
n3175) );
AOI21X1TS U3955 ( .A0(n1954), .A1(n3228), .B0(n3175), .Y(n3176) );
OAI211X1TS U3956 ( .A0(n3178), .A1(n2127), .B0(n3177), .C0(n3176), .Y(n3179)
);
INVX2TS U3957 ( .A(n3213), .Y(n3181) );
BUFX3TS U3958 ( .A(n2146), .Y(n3241) );
OAI2BB2XLTS U3959 ( .B0(n3260), .B1(n3241), .A0N(final_result_ieee[18]),
.A1N(n1996), .Y(n1102) );
OAI2BB2XLTS U3960 ( .B0(n3275), .B1(n3241), .A0N(final_result_ieee[32]),
.A1N(n1996), .Y(n1101) );
AOI22X1TS U3961 ( .A0(Data_array_SWR[15]), .A1(n3198), .B0(n1959), .B1(n3227), .Y(n3185) );
AOI22X1TS U3962 ( .A0(n1957), .A1(n3180), .B0(n1951), .B1(n3229), .Y(n3184)
);
AOI22X1TS U3963 ( .A0(n3232), .A1(n3182), .B0(n2168), .B1(n3181), .Y(n3183)
);
NAND3XLTS U3964 ( .A(n3185), .B(n3184), .C(n3183), .Y(n3186) );
AOI22X1TS U3965 ( .A0(n3236), .A1(n1899), .B0(n3303), .B1(n3186), .Y(n3258)
);
OAI2BB2XLTS U3966 ( .B0(n3258), .B1(n3241), .A0N(final_result_ieee[16]),
.A1N(n1996), .Y(n1100) );
AOI22X1TS U3967 ( .A0(n3239), .A1(n3186), .B0(n3237), .B1(n1899), .Y(n3277)
);
OAI2BB2XLTS U3968 ( .B0(n3277), .B1(n3241), .A0N(final_result_ieee[34]),
.A1N(n1996), .Y(n1099) );
AOI22X1TS U3969 ( .A0(Data_array_SWR[25]), .A1(n2142), .B0(
Data_array_SWR[21]), .B1(n3188), .Y(n3191) );
AOI22X1TS U3970 ( .A0(n1949), .A1(n2159), .B0(n1955), .B1(n3189), .Y(n3190)
);
NAND2X1TS U3971 ( .A(n3191), .B(n3190), .Y(n3202) );
INVX2TS U3972 ( .A(n3205), .Y(n3194) );
AOI22X1TS U3973 ( .A0(n3221), .A1(n3202), .B0(n3222), .B1(n3194), .Y(n3193)
);
NAND2X1TS U3974 ( .A(n2156), .B(n3203), .Y(n3192) );
AOI22X1TS U3975 ( .A0(n3223), .A1(n3202), .B0(n3222), .B1(n3203), .Y(n3196)
);
NAND2X1TS U3976 ( .A(n2156), .B(n3194), .Y(n3195) );
AOI22X1TS U3977 ( .A0(Data_array_SWR[12]), .A1(n3198), .B0(n1946), .B1(n3229), .Y(n3200) );
AOI22X1TS U3978 ( .A0(Data_array_SWR[10]), .A1(n3227), .B0(
Data_array_SWR[16]), .B1(n3228), .Y(n3199) );
OAI211X1TS U3979 ( .A0(n3205), .A1(n3201), .B0(n3200), .C0(n3199), .Y(n3204)
);
OAI2BB2XLTS U3980 ( .B0(n3255), .B1(n3241), .A0N(final_result_ieee[13]),
.A1N(n3225), .Y(n1095) );
OAI2BB2XLTS U3981 ( .B0(n3281), .B1(n3241), .A0N(final_result_ieee[37]),
.A1N(n1996), .Y(n1094) );
OAI22X1TS U3982 ( .A0(n3206), .A1(n3303), .B0(n3205), .B1(n3242), .Y(n3290)
);
AOI22X1TS U3983 ( .A0(Data_array_SWR[12]), .A1(n3227), .B0(
Data_array_SWR[10]), .B1(n3229), .Y(n3209) );
OAI2BB2XLTS U3984 ( .B0(n3427), .B1(n3216), .A0N(Data_array_SWR[16]), .A1N(
n3226), .Y(n3207) );
AOI21X1TS U3985 ( .A0(n1955), .A1(n3228), .B0(n3207), .Y(n3208) );
OAI211X1TS U3986 ( .A0(n3210), .A1(n2127), .B0(n3209), .C0(n3208), .Y(n3211)
);
AOI22X1TS U3987 ( .A0(n3236), .A1(n1901), .B0(n3303), .B1(n3211), .Y(n3259)
);
OAI2BB2XLTS U3988 ( .B0(n3259), .B1(n3241), .A0N(final_result_ieee[17]),
.A1N(n3240), .Y(n1092) );
AOI22X1TS U3989 ( .A0(n3239), .A1(n3211), .B0(n3237), .B1(n1901), .Y(n3276)
);
OAI2BB2XLTS U3990 ( .B0(n3276), .B1(n3241), .A0N(final_result_ieee[33]),
.A1N(n1996), .Y(n1091) );
OAI22X1TS U3991 ( .A0(n3214), .A1(n3303), .B0(n3213), .B1(n3242), .Y(n3296)
);
AOI22X1TS U3992 ( .A0(Data_array_SWR[11]), .A1(n3229), .B0(
Data_array_SWR[14]), .B1(n3227), .Y(n3219) );
OAI2BB2XLTS U3993 ( .B0(n3428), .B1(n3216), .A0N(Data_array_SWR[17]), .A1N(
n3226), .Y(n3217) );
AOI21X1TS U3994 ( .A0(n1952), .A1(n3228), .B0(n3217), .Y(n3218) );
OAI211X1TS U3995 ( .A0(n3220), .A1(n2127), .B0(n3219), .C0(n3218), .Y(n3224)
);
INVX2TS U3996 ( .A(n3243), .Y(n3230) );
OAI2BB2XLTS U3997 ( .B0(n3262), .B1(n3241), .A0N(final_result_ieee[19]),
.A1N(n3225), .Y(n1087) );
OAI2BB2XLTS U3998 ( .B0(n3274), .B1(n3241), .A0N(final_result_ieee[31]),
.A1N(n1996), .Y(n1086) );
AOI22X1TS U3999 ( .A0(Data_array_SWR[11]), .A1(n3227), .B0(
Data_array_SWR[14]), .B1(n3226), .Y(n3235) );
AOI22X1TS U4000 ( .A0(Data_array_SWR[9]), .A1(n3229), .B0(Data_array_SWR[17]), .B1(n3228), .Y(n3234) );
AOI22X1TS U4001 ( .A0(n3232), .A1(n3231), .B0(n2168), .B1(n3230), .Y(n3233)
);
NAND3XLTS U4002 ( .A(n3235), .B(n3234), .C(n3233), .Y(n3238) );
AOI22X1TS U4003 ( .A0(n3236), .A1(n1898), .B0(n3303), .B1(n3238), .Y(n3257)
);
OAI2BB2XLTS U4004 ( .B0(n3257), .B1(n3241), .A0N(final_result_ieee[15]),
.A1N(n1996), .Y(n1085) );
AOI22X1TS U4005 ( .A0(n3239), .A1(n3238), .B0(n3237), .B1(n1898), .Y(n3278)
);
OAI2BB2XLTS U4006 ( .B0(n3278), .B1(n3241), .A0N(final_result_ieee[35]),
.A1N(n3240), .Y(n1084) );
OAI22X1TS U4007 ( .A0(n3244), .A1(n3303), .B0(n3243), .B1(n3242), .Y(n3294)
);
NAND2X1TS U4008 ( .A(n3247), .B(n3303), .Y(n3302) );
OAI22X1TS U4009 ( .A0(n3248), .A1(n3361), .B0(n3427), .B1(n3302), .Y(n3299)
);
OAI22X1TS U4010 ( .A0(n3250), .A1(n3361), .B0(n3249), .B1(n3302), .Y(n3300)
);
OAI22X1TS U4011 ( .A0(n3251), .A1(n3361), .B0(n3428), .B1(n3302), .Y(n3301)
);
AOI22X1TS U4012 ( .A0(n3285), .A1(n3254), .B0(n1987), .B1(n2852), .Y(n1077)
);
AOI22X1TS U4013 ( .A0(n3285), .A1(n3255), .B0(n3293), .B1(n1988), .Y(n1076)
);
AOI22X1TS U4014 ( .A0(n3285), .A1(n3256), .B0(n3293), .B1(n1989), .Y(n1075)
);
AOI22X1TS U4015 ( .A0(n3285), .A1(n3257), .B0(n3293), .B1(n1990), .Y(n1074)
);
AOI22X1TS U4016 ( .A0(n3285), .A1(n3258), .B0(n3293), .B1(n1992), .Y(n1073)
);
AOI22X1TS U4017 ( .A0(n3285), .A1(n3259), .B0(n3293), .B1(n1993), .Y(n1072)
);
AOI22X1TS U4018 ( .A0(n3285), .A1(n3260), .B0(n2852), .B1(n1994), .Y(n1071)
);
AOI22X1TS U4019 ( .A0(n3285), .A1(n3262), .B0(n3279), .B1(n1971), .Y(n1070)
);
AOI22X1TS U4020 ( .A0(n3285), .A1(n3263), .B0(n1972), .B1(n2852), .Y(n1069)
);
AO22XLTS U4021 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[23]), .B0(n2858), .B1(
n3264), .Y(n1068) );
AO22XLTS U4022 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[24]), .B0(n2854), .B1(
n3265), .Y(n1067) );
AO22XLTS U4023 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[25]), .B0(n3297), .B1(
n3266), .Y(n1066) );
AO22XLTS U4024 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[26]), .B0(n2854), .B1(
n3267), .Y(n1065) );
AO22XLTS U4025 ( .A0(n3307), .A1(DmP_mant_SFG_SWR[27]), .B0(n3292), .B1(
n3268), .Y(n1064) );
AO22XLTS U4026 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[28]), .B0(n2854), .B1(
n3269), .Y(n1063) );
AO22XLTS U4027 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[29]), .B0(n3297), .B1(
n3270), .Y(n1062) );
AO22XLTS U4028 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[30]), .B0(n2854), .B1(
n3271), .Y(n1061) );
AO22XLTS U4029 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[31]), .B0(n2854), .B1(
n3272), .Y(n1060) );
AOI22X1TS U4030 ( .A0(n3285), .A1(n3273), .B0(n2852), .B1(n1973), .Y(n1059)
);
AOI22X1TS U4031 ( .A0(n3285), .A1(n3274), .B0(n3279), .B1(n1974), .Y(n1058)
);
AOI22X1TS U4032 ( .A0(n3285), .A1(n3275), .B0(n3279), .B1(n1975), .Y(n1057)
);
AOI22X1TS U4033 ( .A0(n3285), .A1(n3276), .B0(n2852), .B1(n1976), .Y(n1056)
);
AOI22X1TS U4034 ( .A0(n3285), .A1(n3277), .B0(n3279), .B1(n1977), .Y(n1055)
);
AOI22X1TS U4035 ( .A0(n3261), .A1(n3278), .B0(n1979), .B1(n3298), .Y(n1054)
);
AOI22X1TS U4036 ( .A0(n3285), .A1(n3280), .B0(n3279), .B1(n1981), .Y(n1053)
);
AOI22X1TS U4037 ( .A0(n3285), .A1(n3281), .B0(n2852), .B1(n1982), .Y(n1052)
);
AOI22X1TS U4038 ( .A0(n3261), .A1(n3282), .B0(n1983), .B1(n3298), .Y(n1051)
);
AOI22X1TS U4039 ( .A0(n3285), .A1(n3283), .B0(n1984), .B1(n2852), .Y(n1050)
);
AOI22X1TS U4040 ( .A0(n3285), .A1(n3284), .B0(n2852), .B1(n1985), .Y(n1049)
);
AO22XLTS U4041 ( .A0(n3293), .A1(n1912), .B0(n3297), .B1(n3286), .Y(n1048)
);
AO22XLTS U4042 ( .A0(n3293), .A1(n1911), .B0(n2858), .B1(n3287), .Y(n1047)
);
AO22XLTS U4043 ( .A0(n3293), .A1(DmP_mant_SFG_SWR[45]), .B0(n2858), .B1(
n3288), .Y(n1046) );
AO22XLTS U4044 ( .A0(n3293), .A1(n1910), .B0(n3306), .B1(n3289), .Y(n1045)
);
AO22XLTS U4045 ( .A0(n3293), .A1(n1909), .B0(n3292), .B1(n3290), .Y(n1044)
);
AO22XLTS U4046 ( .A0(n3293), .A1(n1908), .B0(n3297), .B1(n3291), .Y(n1043)
);
AO22XLTS U4047 ( .A0(n3295), .A1(n1907), .B0(n3306), .B1(n3294), .Y(n1042)
);
AO22XLTS U4048 ( .A0(n3298), .A1(n1906), .B0(n2858), .B1(n3296), .Y(n1041)
);
AO22XLTS U4049 ( .A0(n3307), .A1(n1905), .B0(n3306), .B1(n3299), .Y(n1040)
);
AO22XLTS U4050 ( .A0(n2852), .A1(n1904), .B0(n3306), .B1(n3300), .Y(n1039)
);
AO22XLTS U4051 ( .A0(n2852), .A1(n1903), .B0(n3306), .B1(n3301), .Y(n1038)
);
OAI22X1TS U4052 ( .A0(n3304), .A1(n3303), .B0(n3429), .B1(n3302), .Y(n3305)
);
AO22XLTS U4053 ( .A0(n3307), .A1(n1902), .B0(n3306), .B1(n3305), .Y(n1037)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk30.tcl_ETAIIN16Q4_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__OR4BB_PP_BLACKBOX_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4BB_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2I_BLACKBOX_V
`define SKY130_FD_SC_MS__MUX2I_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux2i (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2I_BLACKBOX_V
|
`include "register_file.v"
`define SIZE_DECODE_REG 64
`define DATA_SIZE_8 2'b00
`define DATA_SIZE_16 2'b01
`define DATA_SIZE_32 2'b10
`define DIR_L2R 2'b00
`define DIR_R2L 2'b01
`define DIR_NOP 2'b10
module decoder(
input i_clk,
input i_reset,
input i_ready,
input[31:0] i_data,
output[1:0] o_instr_size);
string mnemonic;
reg[31:0] opcode;
reg[1:0] instr_size;
assign o_instr_size = instr_size;
reg[`SIZE_DECODE_REG-1:0] decode_reg;
reg[`SIZE_DECODE_REG-1:0] decode_tmp_reg;
reg[`SIZE_DECODE_REG-1:0] decode_hold_reg;
reg[3:0] count_bytes_in_hold_reg;
reg[3:0] count_bytes_in_decode_reg;
reg[3:0] count_bytes_instr;
reg[2:0] count_bytes_in_prefix;
reg[2:0] data_size;
reg[2:0] direction;
reg[3:0] minRequiredBytes;
reg isImmediate;
reg hasStartAddress;
reg isRegImplicit;
reg[2:0] implicitRegVal;
reg[31:0] last_address;
reg process_modrm;
string non_modrm = "";
initial begin
decode_reg = `SIZE_DECODE_REG'b0;
decode_tmp_reg = `SIZE_DECODE_REG'b0;
decode_hold_reg = `SIZE_DECODE_REG'b0;
count_bytes_in_hold_reg = 4'h0;
count_bytes_in_decode_reg = 4'h0;
count_bytes_instr = 4'h0;
count_bytes_in_prefix = 3'b0;
data_size = `DATA_SIZE_32;
direction = `DIR_L2R;
isImmediate = 1'b0;
hasStartAddress = 1'b0;
isRegImplicit = 1'b0;
implicitRegVal = 3'b000;
end
always @(i_reset or i_data) begin
if (i_reset) begin
decode_reg = `SIZE_DECODE_REG'b0;
decode_tmp_reg = `SIZE_DECODE_REG'b0;
decode_hold_reg = `SIZE_DECODE_REG'b0;
count_bytes_in_hold_reg = 4'h0;
count_bytes_in_decode_reg = 4'h0;
count_bytes_instr = 4'h0;
count_bytes_in_prefix = 3'b0;
data_size = `DATA_SIZE_32;
direction = `DIR_R2L;
isImmediate = 1'b0;
hasStartAddress = 1'b0;
isRegImplicit = 1'b0;
implicitRegVal = 3'b000;
end
if (!i_reset && i_ready && !hasStartAddress) begin
hasStartAddress <= 1'b1;
last_address <= i_data;
$display("Got address");
end
if (!i_reset && i_ready && hasStartAddress) begin
decode_tmp_reg = i_data;
decode_reg = (decode_hold_reg | (decode_tmp_reg<<(8*count_bytes_in_hold_reg)));
decode_hold_reg = decode_reg; // keep a copy here.
count_bytes_in_decode_reg = count_bytes_in_hold_reg + 4; // Every time we get a 32 bit input from memory
count_bytes_in_hold_reg = count_bytes_in_decode_reg;
count_bytes_instr = 4'h0;
count_bytes_in_prefix = 3'b0;
process_modrm = 1'b1;
non_modrm = "";
direction = `DIR_R2L;
isImmediate = 1'b0;
isRegImplicit = 1'b0;
implicitRegVal = 3'b000;
/******* Start of Prefix Decoding ********/
if (decode_reg[7:0] == 8'hf0) begin // LOCK
count_bytes_in_prefix = 1;
end
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
if ((decode_reg[7:0] == 8'hf3) || (decode_reg[7:0] == 8'hf2)) begin // String prefixes
count_bytes_in_prefix = count_bytes_in_prefix + 1;
end
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
case(decode_reg[7:0]) //Segment override TODO: Not handling segment override for now
8'h2e: count_bytes_in_prefix = count_bytes_in_prefix + 1; // CS
8'h36: count_bytes_in_prefix = count_bytes_in_prefix + 1; // SS
8'h3e: count_bytes_in_prefix = count_bytes_in_prefix + 1; // DS
8'h26: count_bytes_in_prefix = count_bytes_in_prefix + 1; // ES
8'h64: count_bytes_in_prefix = count_bytes_in_prefix + 1; // FS
8'h65: count_bytes_in_prefix = count_bytes_in_prefix + 1; // GS
endcase
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
if (decode_reg[7:0] == 8'h66) begin // Operand Override
count_bytes_in_prefix = count_bytes_in_prefix + 1;
data_size = `DATA_SIZE_16;
end
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
if (decode_reg[7:0] == 8'h67) begin // Address Override TODO: Not supporting this
count_bytes_in_prefix = count_bytes_in_prefix + 1;
end
decode_reg = (decode_hold_reg >> (8*count_bytes_in_prefix));
/******* End of Prefix Decoding ********/
count_bytes_instr = count_bytes_in_prefix;
if (count_bytes_instr < count_bytes_in_decode_reg) begin // We start the decoding only if we have enough bytes in decode reg
if (decode_reg[7:0] == 8'h0f) begin // 2 Byte opcode
count_bytes_instr = count_bytes_instr + 1;
decode_reg = (decode_hold_reg >> (8*count_bytes_instr));
//TODO: Decode 2 byte opcode..not doing this for now
end
else begin // 1 byte opcode
if ((decode_reg[7:0] == 8'h00) ||
(decode_reg[7:0] == 8'h01) ||
(decode_reg[7:0] == 8'h02) ||
(decode_reg[7:0] == 8'h03) ||
(decode_reg[7:0] == 8'h04) ||
(decode_reg[7:0] == 8'h05) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "add";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h28) ||
(decode_reg[7:0] == 8'h29) ||
(decode_reg[7:0] == 8'h2a) ||
(decode_reg[7:0] == 8'h2b) ||
(decode_reg[7:0] == 8'h2c) ||
(decode_reg[7:0] == 8'h2d) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "sub";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h20) ||
(decode_reg[7:0] == 8'h21) ||
(decode_reg[7:0] == 8'h22) ||
(decode_reg[7:0] == 8'h23) ||
(decode_reg[7:0] == 8'h24) ||
(decode_reg[7:0] == 8'h25) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "and";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h3a) ||
(decode_reg[7:0] == 8'h3b) ||
(decode_reg[7:0] == 8'h3c) ||
(decode_reg[7:0] == 8'h3d) ||
(decode_reg[7:0] == 8'h38) ||
(decode_reg[7:0] == 8'h39) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "cmp";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h30) ||
(decode_reg[7:0] == 8'h31) ||
(decode_reg[7:0] == 8'h32) ||
(decode_reg[7:0] == 8'h33) ||
(decode_reg[7:0] == 8'h34) ||
(decode_reg[7:0] == 8'h35) ||
(decode_reg[7:0] == 8'h80) ||
(decode_reg[7:0] == 8'h81) ||
(decode_reg[7:0] == 8'h83)) begin
mnemonic = "xor";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h86) ||
(decode_reg[7:0] == 8'h87) ||
(decode_reg[7:0] == 8'h90) ||
(decode_reg[7:0] == 8'h91)) begin
mnemonic = "xchg";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h07) ||
(decode_reg[7:0] == 8'h17) ||
(decode_reg[7:0] == 8'h1f) ||
(decode_reg[7:0] == 8'h58) ||
(decode_reg[7:0] == 8'h8f) ||
(decode_reg[7:0] == 8'h0f) ||
(decode_reg[7:4] == 4'h5 && decode_reg[3] == 1'b1)) begin
mnemonic = "pop";// TODO: Some opcode handline is missing here
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[7:4] == 4'h5 && decode_reg[3] == 1'b1) begin
isRegImplicit = 1'b1;
implicitRegVal = decode_reg[2:0];
minRequiredBytes = count_bytes_instr;
end
else if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
else if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
else if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'h0e) ||
(decode_reg[7:0] == 8'h16) ||
(decode_reg[7:0] == 8'h1e) ||
(decode_reg[7:0] == 8'h06) ||
(decode_reg[7:0] == 8'h0f) ||
(decode_reg[7:0] == 8'h68) ||
(decode_reg[7:0] == 8'h6A) ||
(decode_reg[7:4] == 4'h5 && decode_reg[3] == 1'b0)) begin
mnemonic = "push";// TODO: Some opcode handline is missing here
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[7:4] == 4'h5 && decode_reg[3] == 1'b0) begin
isRegImplicit = 1'b1;
implicitRegVal = decode_reg[2:0];
minRequiredBytes = count_bytes_instr;
end
else if (decode_reg[7:0] == 8'h68) begin
count_bytes_instr = count_bytes_instr + 4;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
$sformat(non_modrm, "$0x%x", decode_reg[39:8]);
end
end
else if (decode_reg[7:0] == 8'h6A) begin
count_bytes_instr = count_bytes_instr + 2;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
$sformat(non_modrm, "$0x%x", decode_reg[23:8]);
end
end
end
else if ((decode_reg[7:0] == 8'hfe) ||
(decode_reg[7:0] == 8'h48)) begin
mnemonic = "dec";// TODO: Some opcode handline is missing here
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'hf6) ||
(decode_reg[7:0] == 8'hf7)) begin
mnemonic = "div";// TODO: Some opcode handline is missing here
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'ha0) ||
(decode_reg[7:0] == 8'ha1) ||
(decode_reg[7:0] == 8'ha2) ||
(decode_reg[7:0] == 8'ha3) ||
(decode_reg[7:0] == 8'hb0) ||
(decode_reg[7:0] == 8'hb8) ||
(decode_reg[7:0] == 8'hc6) ||
(decode_reg[7:0] == 8'hc7) ||
(decode_reg[7:0] == 8'h8a) ||
(decode_reg[7:0] == 8'h8b) ||
(decode_reg[7:0] == 8'h8c) ||
(decode_reg[7:0] == 8'h8e) ||
(decode_reg[7:0] == 8'h88) ||
(decode_reg[7:0] == 8'h89)) begin
mnemonic = "mov";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
/*if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end*/
end
else if (decode_reg[7:0] == 8'h8d) begin
mnemonic = "lea";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
else if ((decode_reg[7:0] == 8'he8) ||
(decode_reg[7:0] == 8'hff) ||
(decode_reg[7:0] == 8'h9a)) begin
mnemonic = "call";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[7:0] == 8'he8) begin
count_bytes_instr = count_bytes_instr + 4;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
$sformat(non_modrm, "$0x%x", decode_reg[39:8]);
end
end
else begin
if (decode_reg[0] == 0) begin // 8 bit operands
data_size = `DATA_SIZE_8;
end
if (decode_reg[1] == 1) begin // Destination operand is register
direction = `DIR_R2L;
end
if (decode_reg[7] == 1) begin // Immediate operand
isImmediate = 1'b1;
end
end
end
else if ((decode_reg[7:0] == 8'hea) ||
(decode_reg[7:0] == 8'heb) ||
(decode_reg[7:0] == 8'he9)) begin
mnemonic = "jmp"; // TODO: handle 8/16/32 bit jmp for now all are 32
count_bytes_instr = count_bytes_instr + 1;
count_bytes_instr = count_bytes_instr + 4;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
$sformat(non_modrm, "$0x%x", decode_reg[39:8]);
end
end
else if ((decode_reg[7:0] == 8'hc2) ||
(decode_reg[7:0] == 8'hc3) ||
(decode_reg[7:0] == 8'hca) ||
(decode_reg[7:0] == 8'hcb)) begin
mnemonic = "ret";
count_bytes_instr = count_bytes_instr + 1;
if (decode_reg[7:0] == 8'hc3 || decode_reg[7:0] == 8'hcb) begin
end
else begin
count_bytes_instr = count_bytes_instr + 2; // 2 byte immediate
$sformat(non_modrm, "$0x%x", decode_reg[23:8]);
end
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
end
else if (decode_reg[7:0] == 8'hf4) begin
mnemonic = "hlt";
count_bytes_instr = count_bytes_instr + 1;
minRequiredBytes = count_bytes_instr;
process_modrm = 1'b0;
end
else begin
$display("Unidentified instr %x", decode_reg);
end
if (isRegImplicit == 1'b1) begin
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
display(last_address, get_code(decode_reg, minRequiredBytes), mnemonic, get_reg(implicitRegVal));
prepare_for_next_instr(decode_reg, decode_hold_reg, minRequiredBytes, count_bytes_in_hold_reg, count_bytes_in_decode_reg, last_address);
end
end
else if (process_modrm) begin
if (count_bytes_instr < count_bytes_in_decode_reg) begin // This means it has the mod/rm byte
minRequiredBytes = (count_bytes_instr + 1 + instruction_length(decode_reg[15:8], data_size, direction, isImmediate));
if (minRequiredBytes <= count_bytes_in_decode_reg) begin
display(last_address, get_code(decode_reg, minRequiredBytes), mnemonic, decode_mod_reg_rm(decode_reg, data_size, direction, isImmediate));
prepare_for_next_instr(decode_reg, decode_hold_reg, minRequiredBytes, count_bytes_in_hold_reg, count_bytes_in_decode_reg, last_address);
end
end
end
else begin
if (count_bytes_instr <= count_bytes_in_decode_reg) begin
display(last_address, get_code(decode_reg, minRequiredBytes), mnemonic, non_modrm);
prepare_for_next_instr(decode_reg, decode_hold_reg, minRequiredBytes, count_bytes_in_hold_reg, count_bytes_in_decode_reg, last_address);
end
end
$display("decode reg curr val %x", decode_reg);
end
end
end
else begin
instr_size <= 1'bx;
end
end
// Shift data in decode register by appropriate bytes and tranfer the same to the hold register to be processed with next instruction
// and simulataneously update the respective byte counters.
task prepare_for_next_instr(
inout[`SIZE_DECODE_REG - 1: 0] decode_reg,
inout[`SIZE_DECODE_REG - 1: 0] decode_hold_reg,
reg[3:0] minRequiredBytes,
inout[3:0] count_bytes_in_hold_reg,
inout[3:0] count_bytes_in_decode_reg,
inout[31:0] last_address);
decode_reg = (decode_hold_reg >> (8*minRequiredBytes));
decode_hold_reg = decode_reg;
count_bytes_in_decode_reg = count_bytes_in_hold_reg - minRequiredBytes; // No need to do this only need to update the hold reg count val
count_bytes_in_hold_reg = count_bytes_in_decode_reg;
last_address = last_address + minRequiredBytes;
endtask
task display(
input[31:0] instr_address,
string bytes,
string opcode,
string operands);
$display("%x:\t%-24s\t %-5s %s", last_address, bytes, opcode, operands);
endtask
function string get_code(input[`SIZE_DECODE_REG-1:0] data, reg[3:0] num_bytes);
string result = "";
string tmpStr = "";
reg[3:0] byte_index;
reg[`SIZE_DECODE_REG-1:0] tmp;
result = "";
for (byte_index = 0; byte_index < num_bytes; byte_index = byte_index + 1) begin
tmp = data >> (byte_index * 8);
tmpStr = result;
$sformat(result, "%s %x", tmpStr, tmp[7:0]);
end
return result;
endfunction
//TODO: Not supporting immediate data mode for 00, 01 and 10 cases
function string decode_mod_reg_rm(input[63:0] data, reg[1:0] data_size, reg[1:0] direction, reg isImmediate); // Assuming instr length 1 byte and 1 byte for mod-rm and max 4 byte displacement
string result = "";
string srcImmediate = "";
case(data[15:14]) // Mod bits
2'b00: begin // Indirect addressing mode
if (data[10:8] == 3'b100) begin // SIB Addressing mode
if (data[23:22] > 0) // scaling present, TODO - verify 32 but displacement
$sformat(result, "%s, (%s, %s*%d+%x)", get_reg(data[13:11], data_size), get_reg(data[18:16], data_size), get_reg(data[21:19], data_size), get_scale(data[23:22]), data[55:24]);
else
$sformat(result, "%s, (%s, %s+%x)", get_reg(data[13:11], data_size), get_reg(data[18:16], data_size), get_reg(data[21:19], data_size), data[55:24]);
end
else if (data[10:8] == 3'b101) begin // Displacement mode
$sformat(result, "%x", data[47:16]);
end
else begin
result = {"(", get_reg(data[10:8], data_size), ")", ", ", get_reg(data[13:11], data_size)};
end
end
2'b01: begin // Same as above but with 8 bit displacement
if (data[10:8] == 3'b100) begin // SIB Addressing mode
if (data[23:22] > 0) // scaling present
$sformat(result, "%s, (%s,%s*%d+%x)", get_reg(data[13:11], data_size), get_reg(data[18:16], data_size), get_reg(data[21:19], data_size), get_scale(data[23:22]), data[31:24]);
else
$sformat(result, "%s, (%s, %s+%x)", get_reg(data[13:11], data_size), get_reg(data[18:16], data_size), get_reg(data[21:19], data_size), data[31:24]);
end
else if (data[10:8] == 3'b101) begin // Displacement mode
$sformat(result, "%x", data[23:16]);
end
else begin
result = {"(", get_reg(data[10:8], data_size), ")", ", ", get_reg(data[13:11], data_size)};
end
end
2'b10: begin // 32-bit Displacement will be added to reg directly, TODO - Verify 32 bit displacement
$sformat(result, "(%s+%x)", get_reg(data[10:8], data_size), data[47:16]);
end
2'b11: begin // Direct addressing
if (isImmediate == 1'b0) begin
result = {get_reg(data[13:11], data_size), ", ", get_reg(data[10:8], data_size)};
end
else begin
if (data_size == `DATA_SIZE_8 || direction == 1'b1) begin
$sformat(srcImmediate, "$0x%x", data[23:16]); // 8 bit immediate data
end
else if (data_size == `DATA_SIZE_16)
$sformat(srcImmediate, "$0x%x", data[31:16]); // 16 bit immediate data
else
$sformat(srcImmediate, "$0x%x", data[47:16]); // 32 bit immediate data
result = {srcImmediate, ",", get_reg(data[10:8], data_size)};
end
end
endcase
return result;
endfunction
function [3:0] get_scale(input[1:0] scale_bits); // Scale value corresponding to scale bits
case(scale_bits)
2'b00: get_scale = 4'h1;
2'b01: get_scale = 4'h2;
2'b10: get_scale = 4'h4;
2'b11: get_scale = 4'h8;
endcase
endfunction
function [3:0] instruction_length(input[7:0] modrm, reg[1:0] data_size, reg[1:0] direction, reg isImmediate); // nstruction length apart from prefix, opcode and mod/rm length
reg[3:0] count_sib = 0;
reg[3:0] count_displacement = 0;
reg[3:0] count_immediate = 0;
count_sib = 0;
count_displacement = 0;
count_immediate = 0;
case(modrm[7:6]) // mod bits
2'b00: begin
if (modrm[2:0] == 3'b100) begin
count_sib = 31'd1;
count_displacement = 31'd4;
end
else if (modrm[2:0] == 3'b101) begin
count_displacement = 31'd4;
end
end
2'b01: begin
if (modrm[2:0] == 3'b100) begin
count_sib = 31'd1;
count_displacement = 31'd1;
end
else if (modrm[2:0] == 3'b101) begin
count_displacement = 31'd1;
end
end
2'b10: begin
count_displacement = 31'd4;
end
2'b11: begin
if (isImmediate == 1'b1) begin
if (data_size == `DATA_SIZE_8 || direction == 1'b1) begin
count_immediate = 1;
end
else if (data_size == `DATA_SIZE_16)
count_immediate = 2;
else
count_immediate = 4;
end
end
endcase
instruction_length = count_sib + count_displacement + count_immediate;
endfunction
function string get_reg(input[2:0] code, input[1:0] data_size = `DATA_SIZE_32);
case (code)
3'b000: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%al";
else if (data_size == `DATA_SIZE_16)
get_reg = "%ax";
else
get_reg = "%eax";
end
3'b001: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%cl";
else if (data_size == `DATA_SIZE_16)
get_reg = "%cx";
else
get_reg = "%ecx";
end
3'b010: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%dl";
else if (data_size == `DATA_SIZE_16)
get_reg = "%dx";
else
get_reg = "%edx";
end
3'b011: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%bl";
else if (data_size == `DATA_SIZE_16)
get_reg = "%bx";
else
get_reg = "%ebx";
end
3'b100: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%ah";
else if (data_size == `DATA_SIZE_16)
get_reg = "%sp";
else
get_reg = "%esp";
end
3'b101: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%ch";
else if (data_size == `DATA_SIZE_16)
get_reg = "%bp";
else
get_reg = "%ebp";
end
3'b110: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%dh";
else if (data_size == `DATA_SIZE_16)
get_reg = "%si";
else
get_reg = "%esi";
end
3'b111: begin
if (data_size == `DATA_SIZE_8)
get_reg = "%bh";
else if (data_size == `DATA_SIZE_16)
get_reg = "%di";
else
get_reg = "%edi";
end
endcase
endfunction
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: t_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.2 Build 209 09/17/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module t_ram (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q);
input aclr;
input clock;
input [26:0] data;
input [14:0] rdaddress;
input rden;
input [14:0] wraddress;
input wren;
output [26:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clock;
tri1 rden;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [26:0] sub_wire0;
wire [26:0] q = sub_wire0[26:0];
altsyncram altsyncram_component (
.aclr0 (aclr),
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.rden_b (rden),
.wren_a (wren),
.q_b (sub_wire0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({27{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "CLEAR0",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
/*
`ifdef MODEL_TECH
altsyncram_component.init_file = "../sim/t_ram_test.hex",
`endif //MODEL_TECH
*/
altsyncram_component.intended_device_family = "Arria V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 20480,
altsyncram_component.numwords_b = 20480,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "CLEAR0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.rdcontrol_reg_b = "CLOCK0",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 15,
altsyncram_component.widthad_b = 15,
altsyncram_component.width_a = 27,
altsyncram_component.width_b = 27,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "1"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "552960"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "27"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "27"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "27"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "27"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "CLEAR0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "20480"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "20480"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "27"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "27"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 27 0 INPUT NODEFVAL "data[26..0]"
// Retrieval info: USED_PORT: q 0 0 27 0 OUTPUT NODEFVAL "q[26..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 15 0 INPUT NODEFVAL "rdaddress[14..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: USED_PORT: wraddress 0 0 15 0 INPUT NODEFVAL "wraddress[14..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @address_a 0 0 15 0 wraddress 0 0 15 0
// Retrieval info: CONNECT: @address_b 0 0 15 0 rdaddress 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 27 0 data 0 0 27 0
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 27 0 @q_b 0 0 27 0
// Retrieval info: GEN_FILE: TYPE_NORMAL t_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL t_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL t_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL t_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL t_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL t_ram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1 ns / 1 ps
module axi_slave_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 11
)
(
// Users to add ports here
// Passthrough signals
output wire S_AXI_ACLK,
output wire S_AXI_ARESETN,
output wire [C_S00_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
output wire [2 : 0] S_AXI_AWPROT,
output wire S_AXI_AWVALID,
input wire S_AXI_AWREADY,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
output wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
output wire S_AXI_WVALID,
input wire S_AXI_WREADY,
input wire [1 : 0] S_AXI_BRESP,
input wire S_AXI_BVALID,
output wire S_AXI_BREADY,
output wire [C_S00_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
output wire [2 : 0] S_AXI_ARPROT,
output wire S_AXI_ARVALID,
input wire S_AXI_ARREADY,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
input wire [1 : 0] S_AXI_RRESP,
input wire S_AXI_RVALID,
output wire S_AXI_RREADY,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Add user logic here
assign S_AXI_ACLK = s00_axi_aclk;
assign S_AXI_ARESETN = s00_axi_aresetn;
assign S_AXI_AWADDR = s00_axi_awaddr;
assign S_AXI_AWPROT = s00_axi_awprot;
assign S_AXI_AWVALID = s00_axi_awvalid;
assign s00_axi_awready = S_AXI_AWREADY;
assign S_AXI_WDATA = s00_axi_wdata;
assign S_AXI_WSTRB = s00_axi_wstrb;
assign S_AXI_WVALID = s00_axi_wvalid;
assign s00_axi_wready = S_AXI_WREADY;
assign s00_axi_bresp = S_AXI_BRESP;
assign s00_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s00_axi_bready;
assign S_AXI_ARADDR = s00_axi_araddr;
assign S_AXI_ARPROT = s00_axi_arprot;
assign S_AXI_ARVALID = s00_axi_arvalid;
assign s00_axi_arready = S_AXI_ARREADY;
assign s00_axi_rdata = S_AXI_RDATA;
assign s00_axi_rresp = S_AXI_RRESP;
assign s00_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s00_axi_rready;
// User logic ends
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4B_2_V
`define SKY130_FD_SC_MS__NAND4B_2_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4b_2 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4b_2 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4B_2_V
|
/*
* SBN machine with hardwired FSM control
* (c) Volker Strumpen
*
* modified to halt execution
* if result address is C all fff's
* i.e. ff for fwidth=8
* by Martin Polak
*/
module sbn (clk, state, PC, a, b);
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
input clk;
output [2:0] state;
output [fwidth-1:0] PC;
output [dwidth-1:0] a, b;
parameter iwidth = 4 * fwidth;
reg [iwidth-1:0] imem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] dmem[0:((1<<fwidth)-1)];
reg [dwidth-1:0] X, Y;
reg [fwidth-1:0] PC;
reg [iwidth-1:0] IR;
wire [iwidth-1:0] insn;
wire [dwidth-1:0] data, asubb;
wire [fwidth-1:0] addr, PCp1, A, B, C, D;
wire altb, stp;
reg [1:0] da;
reg [2:0] state, nextstate;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
parameter S6 = 3'b111;
// datapath
assign insn = imem[PC];
assign data = dmem[addr];
assign a = X; // for monitoring
assign b = Y; // for monitoring
assign asubb = X - Y;
assign altb = asubb[dwidth-1];
assign PCp1 = PC + 1;
assign A = IR[(4*fwidth-1):(3*fwidth)];
assign B = IR[(3*fwidth-1):(2*fwidth)];
assign C = IR[(2*fwidth-1):fwidth];
assign D = IR[fwidth-1:0];
assign stp = (C == ~{fwidth{1'b0}}) ? 1 : 0;
assign addr = (da == 2'b00) ? A : ((da == 2'b01) ? B : C);
always @ (posedge clk)
case (state) // action at end of state cycle
S0: begin
IR <= insn;
da <= 2'b00;
end
S1: begin
X <= data;
da <= 2'b01;
end
S2: begin
Y <= data;
da <= 2'b10;
end
S3: begin
dmem[addr] <= asubb;
$display("mw:DMEM,%h,%h", addr, asubb);
end
S4: PC <= D;
S5: PC <= PCp1;
S6: begin
// $display("program caused halt with value %d\n",asubb);
$finish;
end
endcase
// state register
always @ (posedge clk)
state <= nextstate;
// next state logic
always @ (state or altb or stp)
case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: if (stp ) nextstate = S6;
else nextstate = S3;
S3: if (altb) nextstate = S4;
else nextstate = S5;
default: nextstate = S0;
endcase
initial begin
$readmemh(%PROG%, imem);
$readmemh(%DATA%, dmem);
PC = 0;
state = 0;
$monitor("%d:%b:%h,%h,%h,%h,%h,%h,%h,%h,%h,%h,%h,%h",
$time, clk, PC, X, Y, A, B, C, D, insn, addr, asubb, PCp1, PC);
end // initial begin
endmodule
module top;
parameter fwidth = 8; // field width of sbn operand
parameter dwidth = 32;
parameter maximum = %MAX_STEPS%;
parameter maxmone = maximum - 1;
parameter step = 10;
reg clk;
wire [2:0] state;
wire [fwidth-1:0] pc;
wire [dwidth-1:0] a, b;
sbn #(fwidth,dwidth) mach1 (clk, state, pc, a, b);
initial begin
$display("=== start ===");
clk = 0;
#maxmone $display("=== end ===");
#1 $finish;
end
always
#step clk = ~clk;
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: uart_fifo_64x128.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module uart_fifo_64x128 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] q = sub_wire0[7:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 8,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_64x128_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
(** * PE: Partial Evaluation *)
(* Chapter written and maintained by Chung-chieh Shan *)
(** The [Equiv] chapter introduced constant folding as an example of a
program transformation and proved that it preserves the meaning of
programs. Constant folding operates on manifest constants such as
[ANum] expressions. For example, it simplifies the command [Y ::=
APlus (ANum 3) (ANum 1)] to the command [Y ::= ANum 4]. However,
it does not propagate known constants along data flow. For
example, it does not simplify the sequence
X ::= ANum 3;; Y ::= APlus (AId X) (ANum 1)
to
X ::= ANum 3;; Y ::= ANum 4
because it forgets that [X] is [3] by the time it gets to [Y].
We might naturally want to enhance constant folding so that it
propagates known constants and uses them to simplify programs.
Doing so constitutes a rudimentary form of _partial evaluation_.
As we will see, partial evaluation is so called because it is like
running a program, except only part of the program can be
evaluated because only part of the input to the program is known.
For example, we can only simplify the program
X ::= ANum 3;; Y ::= AMinus (APlus (AId X) (ANum 1)) (AId Y)
to
X ::= ANum 3;; Y ::= AMinus (ANum 4) (AId Y)
without knowing the initial value of [Y]. *)
Require Import Coq.Bool.Bool.
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import Coq.omega.Omega.
Require Import Coq.Logic.FunctionalExtensionality.
Require Import Coq.Lists.List.
Import ListNotations.
Require Import SfLib.
Require Import Maps.
Require Import Imp.
(* ################################################################# *)
(** * Generalizing Constant Folding *)
(** The starting point of partial evaluation is to represent our
partial knowledge about the state. For example, between the two
assignments above, the partial evaluator may know only that [X] is
[3] and nothing about any other variable. *)
(* ================================================================= *)
(** ** Partial States *)
(** Conceptually speaking, we can think of such partial states as the
type [id -> option nat] (as opposed to the type [id -> nat] of
concrete, full states). However, in addition to looking up and
updating the values of individual variables in a partial state, we
may also want to compare two partial states to see if and where
they differ, to handle conditional control flow. It is not possible
to compare two arbitrary functions in this way, so we represent
partial states in a more concrete format: as a list of [id * nat]
pairs. *)
Definition pe_state := list (id * nat).
(** The idea is that a variable [id] appears in the list if and only
if we know its current [nat] value. The [pe_lookup] function thus
interprets this concrete representation. (If the same variable
[id] appears multiple times in the list, the first occurrence
wins, but we will define our partial evaluator to never construct
such a [pe_state].) *)
Fixpoint pe_lookup (pe_st : pe_state) (V:id) : option nat :=
match pe_st with
| [] => None
| (V',n')::pe_st => if beq_id V V' then Some n'
else pe_lookup pe_st V
end.
(** For example, [empty_pe_state] represents complete ignorance about
every variable -- the function that maps every [id] to [None]. *)
Definition empty_pe_state : pe_state := [].
(** More generally, if the [list] representing a [pe_state] does not
contain some [id], then that [pe_state] must map that [id] to
[None]. Before we prove this fact, we first define a useful
tactic for reasoning with [id] equality. The tactic
compare V V'
means to reason by cases over [beq_id V V'].
In the case where [V = V'], the tactic
substitutes [V] for [V'] throughout. *)
Tactic Notation "compare" ident(i) ident(j) :=
let H := fresh "Heq" i j in
destruct (beq_idP i j);
[ subst j | ].
Theorem pe_domain: forall pe_st V n,
pe_lookup pe_st V = Some n ->
In V (map (@fst _ _) pe_st).
Proof. intros pe_st V n H. induction pe_st as [| [V' n'] pe_st].
- (* [] *) inversion H.
- (* :: *) simpl in H. simpl. compare V V'; auto. Qed.
(** In what follows, we will make heavy use of the [In] property from
the standard library, also defined in [Logic.v]: *)
Print In.
(* ===> Fixpoint In {A:Type} (a: A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end
: forall A : Type, A -> list A -> Prop *)
(** Besides the various lemmas about [In] that we've already come
across, the following one (taken from the standard library) will
also be useful: *)
Check filter_In.
(* ===> filter_In : forall (A : Type) (f : A -> bool) (x : A) (l : list A),
In x (filter f l) <-> In x l /\ f x = true *)
(** If a type [A] has an operator [beq] for testing equality of its
elements, we can compute a boolean [inb beq a l] for testing
whether [In a l] holds or not. *)
Fixpoint inb {A : Type} (beq : A -> A -> bool) (a : A) (l : list A) :=
match l with
| [] => false
| a'::l' => beq a a' || inb beq a l'
end.
(** It is easy to relate [inb] to [In] with the [reflect] property: *)
Lemma inbP : forall A : Type, forall beq : A->A->bool,
(forall a1 a2, reflect (a1 = a2) (beq a1 a2)) ->
forall a l, reflect (In a l) (inb beq a l).
Proof.
intros A beq beqP a l.
induction l as [|a' l' IH].
- constructor. intros [].
- simpl. destruct (beqP a a').
+ subst. constructor. left. reflexivity.
+ simpl. destruct IH; constructor.
* right. trivial.
* intros [H1 | H2]; congruence.
Qed.
(* ================================================================= *)
(** ** Arithmetic Expressions *)
(** Partial evaluation of [aexp] is straightforward -- it is basically
the same as constant folding, [fold_constants_aexp], except that
sometimes the partial state tells us the current value of a
variable and we can replace it by a constant expression. *)
Fixpoint pe_aexp (pe_st : pe_state) (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => match pe_lookup pe_st i with (* <----- NEW *)
| Some n => ANum n
| None => AId i
end
| APlus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
(** This partial evaluator folds constants but does not apply the
associativity of addition. *)
Example test_pe_aexp1:
pe_aexp [(X,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (ANum 4) (AId Y).
Proof. reflexivity. Qed.
Example text_pe_aexp2:
pe_aexp [(Y,3)] (APlus (APlus (AId X) (ANum 1)) (AId Y))
= APlus (APlus (AId X) (ANum 1)) (ANum 3).
Proof. reflexivity. Qed.
(** Now, in what sense is [pe_aexp] correct? It is reasonable to
define the correctness of [pe_aexp] as follows: whenever a full
state [st:state] is _consistent_ with a partial state
[pe_st:pe_state] (in other words, every variable to which [pe_st]
assigns a value is assigned the same value by [st]), evaluating
[a] and evaluating [pe_aexp pe_st a] in [st] yields the same
result. This statement is indeed true. *)
Definition pe_consistent (st:state) (pe_st:pe_state) :=
forall V n, Some n = pe_lookup pe_st V -> st V = n.
Theorem pe_aexp_correct_weak: forall st pe_st, pe_consistent st pe_st ->
forall a, aeval st a = aeval st (pe_aexp pe_st a).
Proof. unfold pe_consistent. intros st pe_st H a.
induction a; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound,
the only interesting case is AId *)
- (* AId *)
remember (pe_lookup pe_st i) as l. destruct l.
+ (* Some *) rewrite H with (n:=n) by apply Heql. reflexivity.
+ (* None *) reflexivity.
Qed.
(** However, we will soon want our partial evaluator to remove
assignments. For example, it will simplify
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to just
Y ::= AMinus (ANum 3) (AId Y);; X ::= ANum 4
by delaying the assignment to [X] until the end. To accomplish
this simplification, we need the result of partial evaluating
pe_aexp [(X,3)] (AMinus (AId X) (AId Y))
to be equal to [AMinus (ANum 3) (AId Y)] and _not_ the original
expression [AMinus (AId X) (AId Y)]. After all, it would be
incorrect, not just inefficient, to transform
X ::= ANum 3;; Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
to
Y ::= AMinus (AId X) (AId Y);; X ::= ANum 4
even though the output expressions [AMinus (ANum 3) (AId Y)] and
[AMinus (AId X) (AId Y)] both satisfy the correctness criterion
that we just proved. Indeed, if we were to just define [pe_aexp
pe_st a = a] then the theorem [pe_aexp_correct'] would already
trivially hold.
Instead, we want to prove that the [pe_aexp] is correct in a
stronger sense: evaluating the expression produced by partial
evaluation ([aeval st (pe_aexp pe_st a)]) must not depend on those
parts of the full state [st] that are already specified in the
partial state [pe_st]. To be more precise, let us define a
function [pe_override], which updates [st] with the contents of
[pe_st]. In other words, [pe_override] carries out the
assignments listed in [pe_st] on top of [st]. *)
Fixpoint pe_update (st:state) (pe_st:pe_state) : state :=
match pe_st with
| [] => st
| (V,n)::pe_st => t_update (pe_update st pe_st) V n
end.
Example test_pe_update:
pe_update (t_update empty_state Y 1) [(X,3);(Z,2)]
= t_update (t_update (t_update empty_state Y 1) Z 2) X 3.
Proof. reflexivity. Qed.
(** Although [pe_update] operates on a concrete [list] representing
a [pe_state], its behavior is defined entirely by the [pe_lookup]
interpretation of the [pe_state]. *)
Theorem pe_update_correct: forall st pe_st V0,
pe_update st pe_st V0 =
match pe_lookup pe_st V0 with
| Some n => n
| None => st V0
end.
Proof. intros. induction pe_st as [| [V n] pe_st]. reflexivity.
simpl in *. unfold t_update.
compare V0 V; auto. rewrite <- beq_id_refl; auto. rewrite false_beq_id; auto. Qed.
(** We can relate [pe_consistent] to [pe_update] in two ways.
First, overriding a state with a partial state always gives a
state that is consistent with the partial state. Second, if a
state is already consistent with a partial state, then overriding
the state with the partial state gives the same state. *)
Theorem pe_update_consistent: forall st pe_st,
pe_consistent (pe_update st pe_st) pe_st.
Proof. intros st pe_st V n H. rewrite pe_update_correct.
destruct (pe_lookup pe_st V); inversion H. reflexivity. Qed.
Theorem pe_consistent_update: forall st pe_st,
pe_consistent st pe_st -> forall V, st V = pe_update st pe_st V.
Proof. intros st pe_st H V. rewrite pe_update_correct.
remember (pe_lookup pe_st V) as l. destruct l; auto. Qed.
(** Now we can state and prove that [pe_aexp] is correct in the
stronger sense that will help us define the rest of the partial
evaluator.
Intuitively, running a program using partial evaluation is a
two-stage process. In the first, _static_ stage, we partially
evaluate the given program with respect to some partial state to
get a _residual_ program. In the second, _dynamic_ stage, we
evaluate the residual program with respect to the rest of the
state. This dynamic state provides values for those variables
that are unknown in the static (partial) state. Thus, the
residual program should be equivalent to _prepending_ the
assignments listed in the partial state to the original program. *)
Theorem pe_aexp_correct: forall (pe_st:pe_state) (a:aexp) (st:state),
aeval (pe_update st pe_st) a = aeval st (pe_aexp pe_st a).
Proof.
intros pe_st a st.
induction a; simpl;
try reflexivity;
try (destruct (pe_aexp pe_st a1);
destruct (pe_aexp pe_st a2);
rewrite IHa1; rewrite IHa2; reflexivity).
(* Compared to fold_constants_aexp_sound, the only
interesting case is AId. *)
rewrite pe_update_correct. destruct (pe_lookup pe_st i); reflexivity.
Qed.
(* ================================================================= *)
(** ** Boolean Expressions *)
(** The partial evaluation of boolean expressions is similar. In
fact, it is entirely analogous to the constant folding of boolean
expressions, because our language has no boolean variables. *)
Fixpoint pe_bexp (pe_st : pe_state) (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') => BEq a1' a2'
end
| BLe a1 a2 =>
match (pe_aexp pe_st a1, pe_aexp pe_st a2) with
| (ANum n1, ANum n2) => if leb n1 n2 then BTrue else BFalse
| (a1', a2') => BLe a1' a2'
end
| BNot b1 =>
match (pe_bexp pe_st b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (pe_bexp pe_st b1, pe_bexp pe_st b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example test_pe_bexp1:
pe_bexp [(X,3)] (BNot (BLe (AId X) (ANum 3)))
= BFalse.
Proof. reflexivity. Qed.
Example test_pe_bexp2: forall b,
b = BNot (BLe (AId X) (APlus (AId X) (ANum 1))) ->
pe_bexp [] b = b.
Proof. intros b H. rewrite -> H. reflexivity. Qed.
(** The correctness of [pe_bexp] is analogous to the correctness of
[pe_aexp] above. *)
Theorem pe_bexp_correct: forall (pe_st:pe_state) (b:bexp) (st:state),
beval (pe_update st pe_st) b = beval st (pe_bexp pe_st b).
Proof.
intros pe_st b st.
induction b; simpl;
try reflexivity;
try (remember (pe_aexp pe_st a) as a';
remember (pe_aexp pe_st a0) as a0';
assert (Ha: aeval (pe_update st pe_st) a = aeval st a');
assert (Ha0: aeval (pe_update st pe_st) a0 = aeval st a0');
try (subst; apply pe_aexp_correct);
destruct a'; destruct a0'; rewrite Ha; rewrite Ha0;
simpl; try destruct (beq_nat n n0);
try destruct (leb n n0); reflexivity);
try (destruct (pe_bexp pe_st b); rewrite IHb; reflexivity);
try (destruct (pe_bexp pe_st b1);
destruct (pe_bexp pe_st b2);
rewrite IHb1; rewrite IHb2; reflexivity).
Qed.
(* ################################################################# *)
(** * Partial Evaluation of Commands, Without Loops *)
(** What about the partial evaluation of commands? The analogy
between partial evaluation and full evaluation continues: Just as
full evaluation of a command turns an initial state into a final
state, partial evaluation of a command turns an initial partial
state into a final partial state. The difference is that, because
the state is partial, some parts of the command may not be
executable at the static stage. Therefore, just as [pe_aexp]
returns a residual [aexp] and [pe_bexp] returns a residual [bexp]
above, partially evaluating a command yields a residual command.
Another way in which our partial evaluator is similar to a full
evaluator is that it does not terminate on all commands. It is
not hard to build a partial evaluator that terminates on all
commands; what is hard is building a partial evaluator that
terminates on all commands yet automatically performs desired
optimizations such as unrolling loops. Often a partial evaluator
can be coaxed into terminating more often and performing more
optimizations by writing the source program differently so that
the separation between static and dynamic information becomes more
apparent. Such coaxing is the art of _binding-time improvement_.
The binding time of a variable tells when its value is known --
either "static", or "dynamic."
Anyway, for now we will just live with the fact that our partial
evaluator is not a total function from the source command and the
initial partial state to the residual command and the final
partial state. To model this non-termination, just as with the
full evaluation of commands, we use an inductively defined
relation. We write
c1 / st \\ c1' / st'
to mean that partially evaluating the source command [c1] in the
initial partial state [st] yields the residual command [c1'] and
the final partial state [st']. For example, we want something like
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] \\ (Y ::= AMult (AId Z) (ANum 6)) / [(X,3)]
to hold. The assignment to [X] appears in the final partial state,
not the residual command. *)
(* ================================================================= *)
(** ** Assignment *)
(** Let's start by considering how to partially evaluate an
assignment. The two assignments in the source program above needs
to be treated differently. The first assignment [X ::= ANum 3],
is _static_: its right-hand-side is a constant (more generally,
simplifies to a constant), so we should update our partial state
at [X] to [3] and produce no residual code. (Actually, we produce
a residual [SKIP].) The second assignment [Y ::= AMult (AId Z)
(APlus (AId X) (AId X))] is _dynamic_: its right-hand-side does
not simplify to a constant, so we should leave it in the residual
code and remove [Y], if present, from our partial state. To
implement these two cases, we define the functions [pe_add] and
[pe_remove]. Like [pe_update] above, these functions operate on
a concrete [list] representing a [pe_state], but the theorems
[pe_add_correct] and [pe_remove_correct] specify their behavior by
the [pe_lookup] interpretation of the [pe_state]. *)
Fixpoint pe_remove (pe_st:pe_state) (V:id) : pe_state :=
match pe_st with
| [] => []
| (V',n')::pe_st => if beq_id V V' then pe_remove pe_st V
else (V',n') :: pe_remove pe_st V
end.
Theorem pe_remove_correct: forall pe_st V V0,
pe_lookup (pe_remove pe_st V) V0
= if beq_id V V0 then None else pe_lookup pe_st V0.
Proof. intros pe_st V V0. induction pe_st as [| [V' n'] pe_st].
- (* [] *) destruct (beq_id V V0); reflexivity.
- (* :: *) simpl. compare V V'.
+ (* equal *) rewrite IHpe_st.
destruct (beq_idP V V0). reflexivity.
rewrite false_beq_id; auto.
+ (* not equal *) simpl. compare V0 V'.
* (* equal *) rewrite false_beq_id; auto.
* (* not equal *) rewrite IHpe_st. reflexivity.
Qed.
Definition pe_add (pe_st:pe_state) (V:id) (n:nat) : pe_state :=
(V,n) :: pe_remove pe_st V.
Theorem pe_add_correct: forall pe_st V n V0,
pe_lookup (pe_add pe_st V n) V0
= if beq_id V V0 then Some n else pe_lookup pe_st V0.
Proof. intros pe_st V n V0. unfold pe_add. simpl.
compare V V0.
- (* equal *) rewrite <- beq_id_refl; auto.
- (* not equal *) rewrite pe_remove_correct.
repeat rewrite false_beq_id; auto.
Qed.
(** We will use the two theorems below to show that our partial
evaluator correctly deals with dynamic assignments and static
assignments, respectively. *)
Theorem pe_update_update_remove: forall st pe_st V n,
t_update (pe_update st pe_st) V n =
pe_update (t_update st V n) (pe_remove pe_st V).
Proof. intros st pe_st V n. apply functional_extensionality.
intros V0. unfold t_update. rewrite !pe_update_correct.
rewrite pe_remove_correct. destruct (beq_id V V0); reflexivity.
Qed.
Theorem pe_update_update_add: forall st pe_st V n,
t_update (pe_update st pe_st) V n =
pe_update st (pe_add pe_st V n).
Proof. intros st pe_st V n. apply functional_extensionality. intros V0.
unfold t_update. rewrite !pe_update_correct. rewrite pe_add_correct.
destruct (beq_id V V0); reflexivity. Qed.
(* ================================================================= *)
(** ** Conditional *)
(** Trickier than assignments to partially evaluate is the
conditional, [IFB b1 THEN c1 ELSE c2 FI]. If [b1] simplifies to
[BTrue] or [BFalse] then it's easy: we know which branch will be
taken, so just take that branch. If [b1] does not simplify to a
constant, then we need to take both branches, and the final
partial state may differ between the two branches!
The following program illustrates the difficulty:
X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI
Suppose the initial partial state is empty. We don't know
statically how [Y] compares to [4], so we must partially evaluate
both branches of the (outer) conditional. On the [THEN] branch,
we know that [Y] is set to [4] and can even use that knowledge to
simplify the code somewhat. On the [ELSE] branch, we still don't
know the exact value of [Y] at the end. What should the final
partial state and residual program be?
One way to handle such a dynamic conditional is to take the
intersection of the final partial states of the two branches. In
this example, we take the intersection of [(Y,4),(X,3)] and
[(X,3)], so the overall final partial state is [(X,3)]. To
compensate for forgetting that [Y] is [4], we need to add an
assignment [Y ::= ANum 4] to the end of the [THEN] branch. So,
the residual program will be something like
SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
SKIP;;
SKIP;;
Y ::= ANum 4
ELSE SKIP FI
Programming this case in Coq calls for several auxiliary
functions: we need to compute the intersection of two [pe_state]s
and turn their difference into sequences of assignments.
First, we show how to compute whether two [pe_state]s to disagree
at a given variable. In the theorem [pe_disagree_domain], we
prove that two [pe_state]s can only disagree at variables that
appear in at least one of them. *)
Definition pe_disagree_at (pe_st1 pe_st2 : pe_state) (V:id) : bool :=
match pe_lookup pe_st1 V, pe_lookup pe_st2 V with
| Some x, Some y => negb (beq_nat x y)
| None, None => false
| _, _ => true
end.
Theorem pe_disagree_domain: forall (pe_st1 pe_st2 : pe_state) (V:id),
true = pe_disagree_at pe_st1 pe_st2 V ->
In V (map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2).
Proof. unfold pe_disagree_at. intros pe_st1 pe_st2 V H.
apply in_app_iff.
remember (pe_lookup pe_st1 V) as lookup1.
destruct lookup1 as [n1|]. left. apply pe_domain with n1. auto.
remember (pe_lookup pe_st2 V) as lookup2.
destruct lookup2 as [n2|]. right. apply pe_domain with n2. auto.
inversion H. Qed.
(** We define the [pe_compare] function to list the variables where
two given [pe_state]s disagree. This list is exact, according to
the theorem [pe_compare_correct]: a variable appears on the list
if and only if the two given [pe_state]s disagree at that
variable. Furthermore, we use the [pe_unique] function to
eliminate duplicates from the list. *)
Fixpoint pe_unique (l : list id) : list id :=
match l with
| [] => []
| x::l =>
x :: filter (fun y => if beq_id x y then false else true) (pe_unique l)
end.
Theorem pe_unique_correct: forall l x,
In x l <-> In x (pe_unique l).
Proof. intros l x. induction l as [| h t]. reflexivity.
simpl in *. split.
- (* -> *)
intros. inversion H; clear H.
left. assumption.
destruct (beq_idP h x).
left. assumption.
right. apply filter_In. split.
apply IHt. assumption.
rewrite false_beq_id; auto.
- (* <- *)
intros. inversion H; clear H.
left. assumption.
apply filter_In in H0. inversion H0. right. apply IHt. assumption.
Qed.
Definition pe_compare (pe_st1 pe_st2 : pe_state) : list id :=
pe_unique (filter (pe_disagree_at pe_st1 pe_st2)
(map (@fst _ _) pe_st1 ++ map (@fst _ _) pe_st2)).
Theorem pe_compare_correct: forall pe_st1 pe_st2 V,
pe_lookup pe_st1 V = pe_lookup pe_st2 V <->
~ In V (pe_compare pe_st1 pe_st2).
Proof. intros pe_st1 pe_st2 V.
unfold pe_compare. rewrite <- pe_unique_correct. rewrite filter_In.
split; intros Heq.
- (* -> *)
intro. destruct H. unfold pe_disagree_at in H0. rewrite Heq in H0.
destruct (pe_lookup pe_st2 V).
rewrite <- beq_nat_refl in H0. inversion H0.
inversion H0.
- (* <- *)
assert (Hagree: pe_disagree_at pe_st1 pe_st2 V = false).
{ (* Proof of assertion *)
remember (pe_disagree_at pe_st1 pe_st2 V) as disagree.
destruct disagree; [| reflexivity].
apply pe_disagree_domain in Heqdisagree.
exfalso. apply Heq. split. assumption. reflexivity. }
unfold pe_disagree_at in Hagree.
destruct (pe_lookup pe_st1 V) as [n1|];
destruct (pe_lookup pe_st2 V) as [n2|];
try reflexivity; try solve by inversion.
rewrite negb_false_iff in Hagree.
apply beq_nat_true in Hagree. subst. reflexivity. Qed.
(** The intersection of two partial states is the result of removing
from one of them all the variables where the two disagree. We
define the function [pe_removes], in terms of [pe_remove] above,
to perform such a removal of a whole list of variables at once.
The theorem [pe_compare_removes] testifies that the [pe_lookup]
interpretation of the result of this intersection operation is the
same no matter which of the two partial states we remove the
variables from. Because [pe_update] only depends on the
[pe_lookup] interpretation of partial states, [pe_update] also
does not care which of the two partial states we remove the
variables from; that theorem [pe_compare_update] is used in the
correctness proof shortly. *)
Fixpoint pe_removes (pe_st:pe_state) (ids : list id) : pe_state :=
match ids with
| [] => pe_st
| V::ids => pe_remove (pe_removes pe_st ids) V
end.
Theorem pe_removes_correct: forall pe_st ids V,
pe_lookup (pe_removes pe_st ids) V =
if inb beq_id V ids then None else pe_lookup pe_st V.
Proof. intros pe_st ids V. induction ids as [| V' ids]. reflexivity.
simpl. rewrite pe_remove_correct. rewrite IHids.
compare V' V.
- rewrite <- beq_id_refl. reflexivity.
- rewrite false_beq_id; try congruence. reflexivity.
Qed.
Theorem pe_compare_removes: forall pe_st1 pe_st2 V,
pe_lookup (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) V =
pe_lookup (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)) V.
Proof.
intros pe_st1 pe_st2 V. rewrite !pe_removes_correct.
destruct (inbP _ _ beq_idP V (pe_compare pe_st1 pe_st2)).
- reflexivity.
- apply pe_compare_correct. auto. Qed.
Theorem pe_compare_update: forall pe_st1 pe_st2 st,
pe_update st (pe_removes pe_st1 (pe_compare pe_st1 pe_st2)) =
pe_update st (pe_removes pe_st2 (pe_compare pe_st1 pe_st2)).
Proof. intros. apply functional_extensionality. intros V.
rewrite !pe_update_correct. rewrite pe_compare_removes. reflexivity.
Qed.
(** Finally, we define an [assign] function to turn the difference
between two partial states into a sequence of assignment commands.
More precisely, [assign pe_st ids] generates an assignment command
for each variable listed in [ids]. *)
Fixpoint assign (pe_st : pe_state) (ids : list id) : com :=
match ids with
| [] => SKIP
| V::ids => match pe_lookup pe_st V with
| Some n => (assign pe_st ids;; V ::= ANum n)
| None => assign pe_st ids
end
end.
(** The command generated by [assign] always terminates, because it is
just a sequence of assignments. The (total) function [assigned]
below computes the effect of the command on the (dynamic state).
The theorem [assign_removes] then confirms that the generated
assignments perfectly compensate for removing the variables from
the partial state. *)
Definition assigned (pe_st:pe_state) (ids : list id) (st:state) : state :=
fun V => if inb beq_id V ids then
match pe_lookup pe_st V with
| Some n => n
| None => st V
end
else st V.
Theorem assign_removes: forall pe_st ids st,
pe_update st pe_st =
pe_update (assigned pe_st ids st) (pe_removes pe_st ids).
Proof. intros pe_st ids st. apply functional_extensionality. intros V.
rewrite !pe_update_correct. rewrite pe_removes_correct. unfold assigned.
destruct (inbP _ _ beq_idP V ids); destruct (pe_lookup pe_st V); reflexivity.
Qed.
Lemma ceval_extensionality: forall c st st1 st2,
c / st \\ st1 -> (forall V, st1 V = st2 V) -> c / st \\ st2.
Proof. intros c st st1 st2 H Heq.
apply functional_extensionality in Heq. rewrite <- Heq. apply H. Qed.
Theorem eval_assign: forall pe_st ids st,
assign pe_st ids / st \\ assigned pe_st ids st.
Proof. intros pe_st ids st. induction ids as [| V ids]; simpl.
- (* [] *) eapply ceval_extensionality. apply E_Skip. reflexivity.
- (* V::ids *)
remember (pe_lookup pe_st V) as lookup. destruct lookup.
+ (* Some *) eapply E_Seq. apply IHids. unfold assigned. simpl.
eapply ceval_extensionality. apply E_Ass. simpl. reflexivity.
intros V0. unfold t_update. compare V V0.
* (* equal *) rewrite <- Heqlookup. rewrite <- beq_id_refl. reflexivity.
* (* not equal *) rewrite false_beq_id; simpl; congruence.
+ (* None *) eapply ceval_extensionality. apply IHids.
unfold assigned. intros V0. simpl. compare V V0.
* (* equal *) rewrite <- Heqlookup.
rewrite <- beq_id_refl.
destruct (inbP _ _ beq_idP V ids); reflexivity.
* (* not equal *) rewrite false_beq_id; simpl; congruence.
Qed.
(* ================================================================= *)
(** ** The Partial Evaluation Relation *)
(** At long last, we can define a partial evaluator for commands
without loops, as an inductive relation! The inequality
conditions in [PE_AssDynamic] and [PE_If] are just to keep the
partial evaluator deterministic; they are not required for
correctness. *)
Reserved Notation "c1 '/' st '\\' c1' '/' st'"
(at level 40, st at level 39, c1' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st \\ SKIP / pe_st
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st \\ SKIP / pe_add pe_st l n1
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st \\ (l ::= a1') / pe_remove pe_st l
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2',
c1 / pe_st \\ c1' / pe_st' ->
c2 / pe_st' \\ c2' / pe_st'' ->
(c1 ;; c2) / pe_st \\ (c1' ;; c2') / pe_st''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c1' / pe_st'
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st \\ c2' / pe_st' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c2' / pe_st'
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st \\ c1' / pe_st1 ->
c2 / pe_st \\ c2' / pe_st2 ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
where "c1 '/' st '\\' c1' '/' st'" := (pe_com c1 st c1' st').
Hint Constructors pe_com.
Hint Constructors ceval.
(* ================================================================= *)
(** ** Examples *)
(** Below are some examples of using the partial evaluator. To make
the [pe_com] relation actually usable for automatic partial
evaluation, we would need to define more automation tactics in
Coq. That is not hard to do, but it is not needed here. *)
Example pe_example1:
(X ::= ANum 3 ;; Y ::= AMult (AId Z) (APlus (AId X) (AId X)))
/ [] \\ (SKIP;; Y ::= AMult (AId Z) (ANum 6)) / [(X,3)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_AssDynamic. reflexivity. intros n H. inversion H. Qed.
Example pe_example2:
(X ::= ANum 3 ;; IFB BLe (AId X) (ANum 4) THEN X ::= ANum 4 ELSE SKIP FI)
/ [] \\ (SKIP;; SKIP) / [(X,4)].
Proof. eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_IfTrue. reflexivity.
eapply PE_AssStatic. reflexivity. Qed.
Example pe_example3:
(X ::= ANum 3;;
IFB BLe (AId Y) (ANum 4) THEN
Y ::= ANum 4;;
IFB BEq (AId X) (AId Y) THEN Y ::= ANum 999 ELSE SKIP FI
ELSE SKIP FI) / []
\\ (SKIP;;
IFB BLe (AId Y) (ANum 4) THEN
(SKIP;; SKIP);; (SKIP;; Y ::= ANum 4)
ELSE SKIP;; SKIP FI)
/ [(X,3)].
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
eapply PE_If; intuition eauto; try solve by inversion.
econstructor. eapply PE_AssStatic. reflexivity.
eapply PE_IfFalse. reflexivity. econstructor.
reflexivity. reflexivity. Qed.
(* ================================================================= *)
(** ** Correctness of Partial Evaluation *)
(** Finally let's prove that this partial evaluator is correct! *)
Reserved Notation "c' '/' pe_st' '/' st '\\' st''"
(at level 40, pe_st' at level 39, st at level 39).
Inductive pe_ceval
(c':com) (pe_st':pe_state) (st:state) (st'':state) : Prop :=
| pe_ceval_intro : forall st',
c' / st \\ st' ->
pe_update st' pe_st' = st'' ->
c' / pe_st' / st \\ st''
where "c' '/' pe_st' '/' st '\\' st''" := (pe_ceval c' pe_st' st st'').
Hint Constructors pe_ceval.
Theorem pe_com_complete:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c / pe_update st pe_st \\ st'') ->
(c' / pe_st' / st \\ st'').
Proof. intros c pe_st pe_st' c' Hpe.
induction Hpe; intros st st'' Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
- (* PE_AssStatic *) econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_add.
rewrite -> H. reflexivity.
- (* PE_AssDynamic *) econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_remove.
reflexivity.
- (* PE_Seq *)
edestruct IHHpe1. eassumption. subst.
edestruct IHHpe2. eassumption.
eauto.
- (* PE_If *) inversion Heval; subst.
+ (* E'IfTrue *) edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption.
+ (* E_IfFalse *) edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_update.
rewrite <- assign_removes. eassumption.
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c' / pe_st' / st \\ st'') ->
(c / pe_update st pe_st \\ st'').
Proof. intros c pe_st pe_st' c' Hpe.
induction Hpe;
intros st st'' [st' Heval Heq];
try (inversion Heval; []; subst); auto.
- (* PE_AssStatic *) rewrite <- pe_update_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
- (* PE_AssDynamic *) rewrite <- pe_update_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
- (* PE_Seq *) eapply E_Seq; eauto.
- (* PE_IfTrue *) apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
- (* PE_IfFalse *) apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity. eauto.
- (* PE_If *)
inversion Heval; subst; inversion H7;
(eapply ceval_deterministic in H8; [| apply eval_assign]); subst.
+ (* E_IfTrue *)
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
+ (* E_IfFalse *)
rewrite -> pe_compare_update.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
rewrite <- assign_removes. eauto.
Qed.
(** The main theorem. Thanks to David Menendez for this formulation! *)
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' ->
forall st st'',
(c / pe_update st pe_st \\ st'') <->
(c' / pe_st' / st \\ st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
- (* -> *) apply pe_com_complete. apply H.
- (* <- *) apply pe_com_sound. apply H.
Qed.
(* ################################################################# *)
(** * Partial Evaluation of Loops *)
(** It may seem straightforward at first glance to extend the partial
evaluation relation [pe_com] above to loops. Indeed, many loops
are easy to deal with. Considered this repeated-squaring loop,
for example:
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END
If we know neither [X] nor [Y] statically, then the entire loop is
dynamic and the residual command should be the same. If we know
[X] but not [Y], then the loop can be unrolled all the way and the
residual command should be, for example,
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y);;
Y ::= AMult (AId Y) (AId Y)
if [X] is initially [3] (and finally [0]). In general, a loop is
easy to partially evaluate if the final partial state of the loop
body is equal to the initial state, or if its guard condition is
static.
But there are other loops for which it is hard to express the
residual program we want in Imp. For example, take this program
for checking whether [Y] is even or odd:
X ::= ANum 0;;
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
X ::= AMinus (ANum 1) (AId X)
END
The value of [X] alternates between [0] and [1] during the loop.
Ideally, we would like to unroll this loop, not all the way but
_two-fold_, into something like
WHILE BLe (ANum 1) (AId Y) DO
Y ::= AMinus (AId Y) (ANum 1);;
IF BLe (ANum 1) (AId Y) THEN
Y ::= AMinus (AId Y) (ANum 1)
ELSE
X ::= ANum 1;; EXIT
FI
END;;
X ::= ANum 0
Unfortunately, there is no [EXIT] command in Imp. Without
extending the range of control structures available in our
language, the best we can do is to repeat loop-guard tests or add
flag variables. Neither option is terribly attractive.
Still, as a digression, below is an attempt at performing partial
evaluation on Imp commands. We add one more command argument
[c''] to the [pe_com] relation, which keeps track of a loop to
roll up. *)
Module Loop.
Reserved Notation "c1 '/' st '\\' c1' '/' st' '/' c''"
(at level 40, st at level 39, c1' at level 39, st' at level 39).
Inductive pe_com : com -> pe_state -> com -> pe_state -> com -> Prop :=
| PE_Skip : forall pe_st,
SKIP / pe_st \\ SKIP / pe_st / SKIP
| PE_AssStatic : forall pe_st a1 n1 l,
pe_aexp pe_st a1 = ANum n1 ->
(l ::= a1) / pe_st \\ SKIP / pe_add pe_st l n1 / SKIP
| PE_AssDynamic : forall pe_st a1 a1' l,
pe_aexp pe_st a1 = a1' ->
(forall n, a1' <> ANum n) ->
(l ::= a1) / pe_st \\ (l ::= a1') / pe_remove pe_st l / SKIP
| PE_Seq : forall pe_st pe_st' pe_st'' c1 c2 c1' c2' c'',
c1 / pe_st \\ c1' / pe_st' / SKIP ->
c2 / pe_st' \\ c2' / pe_st'' / c'' ->
(c1 ;; c2) / pe_st \\ (c1' ;; c2') / pe_st'' / c''
| PE_IfTrue : forall pe_st pe_st' b1 c1 c2 c1' c'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c1' / pe_st' / c''
| PE_IfFalse : forall pe_st pe_st' b1 c1 c2 c2' c'',
pe_bexp pe_st b1 = BFalse ->
c2 / pe_st \\ c2' / pe_st' / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st \\ c2' / pe_st' / c''
| PE_If : forall pe_st pe_st1 pe_st2 b1 c1 c2 c1' c2' c'',
pe_bexp pe_st b1 <> BTrue ->
pe_bexp pe_st b1 <> BFalse ->
c1 / pe_st \\ c1' / pe_st1 / c'' ->
c2 / pe_st \\ c2' / pe_st2 / c'' ->
(IFB b1 THEN c1 ELSE c2 FI) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1' ;; assign pe_st1 (pe_compare pe_st1 pe_st2)
ELSE c2' ;; assign pe_st2 (pe_compare pe_st1 pe_st2) FI)
/ pe_removes pe_st1 (pe_compare pe_st1 pe_st2)
/ c''
| PE_WhileEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 = BFalse ->
(WHILE b1 DO c1 END) / pe_st \\ SKIP / pe_st / SKIP
| PE_WhileLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' \\ c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(WHILE b1 DO c1 END) / pe_st \\ (c1';;c2') / pe_st'' / c2''
| PE_While : forall pe_st pe_st' pe_st'' b1 c1 c1' c2' c2'',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st' \\ c2' / pe_st'' / c2'' ->
pe_compare pe_st pe_st'' <> [] ->
(c2'' = SKIP \/ c2'' = WHILE b1 DO c1 END) ->
(WHILE b1 DO c1 END) / pe_st
\\ (IFB pe_bexp pe_st b1
THEN c1';; c2';; assign pe_st'' (pe_compare pe_st pe_st'')
ELSE assign pe_st (pe_compare pe_st pe_st'') FI)
/ pe_removes pe_st (pe_compare pe_st pe_st'')
/ c2''
| PE_WhileFixedEnd : forall pe_st b1 c1,
pe_bexp pe_st b1 <> BFalse ->
(WHILE b1 DO c1 END) / pe_st \\ SKIP / pe_st / (WHILE b1 DO c1 END)
| PE_WhileFixedLoop : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 = BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
\\ c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
\\ (WHILE BTrue DO SKIP END) / pe_st / SKIP
(* Because we have an infinite loop, we should actually
start to throw away the rest of the program:
(WHILE b1 DO c1 END) / pe_st
\\ SKIP / pe_st / (WHILE BTrue DO SKIP END) *)
| PE_WhileFixed : forall pe_st pe_st' pe_st'' b1 c1 c1' c2',
pe_bexp pe_st b1 <> BFalse ->
pe_bexp pe_st b1 <> BTrue ->
c1 / pe_st \\ c1' / pe_st' / SKIP ->
(WHILE b1 DO c1 END) / pe_st'
\\ c2' / pe_st'' / (WHILE b1 DO c1 END) ->
pe_compare pe_st pe_st'' = [] ->
(WHILE b1 DO c1 END) / pe_st
\\ (WHILE pe_bexp pe_st b1 DO c1';; c2' END) / pe_st / SKIP
where "c1 '/' st '\\' c1' '/' st' '/' c''" := (pe_com c1 st c1' st' c'').
Hint Constructors pe_com.
(* ================================================================= *)
(** ** Examples *)
Ltac step i :=
(eapply i; intuition eauto; try solve by inversion);
repeat (try eapply PE_Seq;
try (eapply PE_AssStatic; simpl; reflexivity);
try (eapply PE_AssDynamic;
[ simpl; reflexivity
| intuition eauto; solve by inversion ])).
Definition square_loop: com :=
WHILE BLe (ANum 1) (AId X) DO
Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1)
END.
Example pe_loop_example1:
square_loop / []
\\ (WHILE BLe (ANum 1) (AId X) DO
(Y ::= AMult (AId Y) (AId Y);;
X ::= AMinus (AId X) (ANum 1));; SKIP
END) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
step PE_WhileFixed. step PE_WhileFixedEnd. reflexivity.
reflexivity. reflexivity. Qed.
Example pe_loop_example2:
(X ::= ANum 3;; square_loop) / []
\\ (SKIP;;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
(Y ::= AMult (AId Y) (AId Y);; SKIP);;
SKIP) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileLoop.
step PE_WhileEnd.
inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example3:
(Z ::= ANum 3;; subtract_slowly) / []
\\ (SKIP;;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
IFB BNot (BEq (AId X) (ANum 0)) THEN
(SKIP;; X ::= AMinus (AId X) (ANum 1));;
WHILE BNot (BEq (AId X) (ANum 0)) DO
(SKIP;; X ::= AMinus (AId X) (ANum 1));; SKIP
END;;
SKIP;; Z ::= ANum 0
ELSE SKIP;; Z ::= ANum 1 FI;; SKIP
ELSE SKIP;; Z ::= ANum 2 FI;; SKIP
ELSE SKIP;; Z ::= ANum 3 FI) / [] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_While.
step PE_While.
step PE_While.
step PE_WhileFixed.
step PE_WhileFixedEnd.
reflexivity. inversion H. inversion H. inversion H.
reflexivity. reflexivity. Qed.
Example pe_loop_example4:
(X ::= ANum 0;;
WHILE BLe (AId X) (ANum 2) DO
X ::= AMinus (ANum 1) (AId X)
END) / [] \\ (SKIP;; WHILE BTrue DO SKIP END) / [(X,0)] / SKIP.
Proof. erewrite f_equal2 with (f := fun c st => _ / _ \\ c / st / SKIP).
eapply PE_Seq. eapply PE_AssStatic. reflexivity.
step PE_WhileFixedLoop.
step PE_WhileLoop.
step PE_WhileFixedEnd.
inversion H. reflexivity. reflexivity. reflexivity. Qed.
(* ================================================================= *)
(** ** Correctness *)
(** Because this partial evaluator can unroll a loop n-fold where n is
a (finite) integer greater than one, in order to show it correct
we need to perform induction not structurally on dynamic
evaluation but on the number of times dynamic evaluation enters a
loop body. *)
Reserved Notation "c1 '/' st '\\' st' '#' n"
(at level 40, st at level 39, st' at level 39).
Inductive ceval_count : com -> state -> state -> nat -> Prop :=
| E'Skip : forall st,
SKIP / st \\ st # 0
| E'Ass : forall st a1 n l,
aeval st a1 = n ->
(l ::= a1) / st \\ (t_update st l n) # 0
| E'Seq : forall c1 c2 st st' st'' n1 n2,
c1 / st \\ st' # n1 ->
c2 / st' \\ st'' # n2 ->
(c1 ;; c2) / st \\ st'' # (n1 + n2)
| E'IfTrue : forall st st' b1 c1 c2 n,
beval st b1 = true ->
c1 / st \\ st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st' # n
| E'IfFalse : forall st st' b1 c1 c2 n,
beval st b1 = false ->
c2 / st \\ st' # n ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st' # n
| E'WhileEnd : forall b1 st c1,
beval st b1 = false ->
(WHILE b1 DO c1 END) / st \\ st # 0
| E'WhileLoop : forall st st' st'' b1 c1 n1 n2,
beval st b1 = true ->
c1 / st \\ st' # n1 ->
(WHILE b1 DO c1 END) / st' \\ st'' # n2 ->
(WHILE b1 DO c1 END) / st \\ st'' # S (n1 + n2)
where "c1 '/' st '\\' st' # n" := (ceval_count c1 st st' n).
Hint Constructors ceval_count.
Theorem ceval_count_complete: forall c st st',
c / st \\ st' -> exists n, c / st \\ st' # n.
Proof. intros c st st' Heval.
induction Heval;
try inversion IHHeval1;
try inversion IHHeval2;
try inversion IHHeval;
eauto. Qed.
Theorem ceval_count_sound: forall c st st' n,
c / st \\ st' # n -> c / st \\ st'.
Proof. intros c st st' n Heval. induction Heval; eauto. Qed.
Theorem pe_compare_nil_lookup: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall V, pe_lookup pe_st1 V = pe_lookup pe_st2 V.
Proof. intros pe_st1 pe_st2 H V.
apply (pe_compare_correct pe_st1 pe_st2 V).
rewrite H. intro. inversion H0. Qed.
Theorem pe_compare_nil_update: forall pe_st1 pe_st2,
pe_compare pe_st1 pe_st2 = [] ->
forall st, pe_update st pe_st1 = pe_update st pe_st2.
Proof. intros pe_st1 pe_st2 H st.
apply functional_extensionality. intros V.
rewrite !pe_update_correct.
apply pe_compare_nil_lookup with (V:=V) in H.
rewrite H. reflexivity. Qed.
Reserved Notation "c' '/' pe_st' '/' c'' '/' st '\\' st'' '#' n"
(at level 40, pe_st' at level 39, c'' at level 39,
st at level 39, st'' at level 39).
Inductive pe_ceval_count (c':com) (pe_st':pe_state) (c'':com)
(st:state) (st'':state) (n:nat) : Prop :=
| pe_ceval_count_intro : forall st' n',
c' / st \\ st' ->
c'' / pe_update st' pe_st' \\ st'' # n' ->
n' <= n ->
c' / pe_st' / c'' / st \\ st'' # n
where "c' '/' pe_st' '/' c'' '/' st '\\' st'' '#' n" :=
(pe_ceval_count c' pe_st' c'' st st'' n).
Hint Constructors pe_ceval_count.
Lemma pe_ceval_count_le: forall c' pe_st' c'' st st'' n n',
n' <= n ->
c' / pe_st' / c'' / st \\ st'' # n' ->
c' / pe_st' / c'' / st \\ st'' # n.
Proof. intros c' pe_st' c'' st st'' n n' Hle H. inversion H.
econstructor; try eassumption. omega. Qed.
Theorem pe_com_complete:
forall c pe_st pe_st' c' c'', c / pe_st \\ c' / pe_st' / c'' ->
forall st st'' n,
(c / pe_update st pe_st \\ st'' # n) ->
(c' / pe_st' / c'' / st \\ st'' # n).
Proof. intros c pe_st pe_st' c' c'' Hpe.
induction Hpe; intros st st'' n Heval;
try (inversion Heval; subst;
try (rewrite -> pe_bexp_correct, -> H in *; solve by inversion);
[]);
eauto.
- (* PE_AssStatic *) econstructor. econstructor.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_add.
rewrite -> H. apply E'Skip. auto.
- (* PE_AssDynamic *) econstructor. econstructor. reflexivity.
rewrite -> pe_aexp_correct. rewrite <- pe_update_update_remove.
apply E'Skip. auto.
- (* PE_Seq *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
- (* PE_If *) inversion Heval; subst.
+ (* E'IfTrue *) edestruct IHHpe1. eassumption.
econstructor. apply E_IfTrue. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite <- assign_removes. eassumption. eassumption.
+ (* E_IfFalse *) edestruct IHHpe2. eassumption.
econstructor. apply E_IfFalse. rewrite <- pe_bexp_correct. assumption.
eapply E_Seq. eassumption. apply eval_assign.
rewrite -> pe_compare_update.
rewrite <- assign_removes. eassumption. eassumption.
- (* PE_WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor; eauto. omega.
- (* PE_While *) inversion Heval; subst.
+ (* E_WhileEnd *) econstructor. apply E_IfFalse.
rewrite <- pe_bexp_correct. assumption.
apply eval_assign.
rewrite <- assign_removes. inversion H2; subst; auto.
auto.
+ (* E_WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
econstructor. apply E_IfTrue.
rewrite <- pe_bexp_correct. assumption.
repeat eapply E_Seq; eauto. apply eval_assign.
rewrite -> pe_compare_update, <- assign_removes. eassumption.
omega.
- (* PE_WhileFixedLoop *) exfalso.
generalize dependent (S (n1 + n2)). intros n.
clear - H H0 IHHpe1 IHHpe2. generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
+ (* E'WhileEnd *) rewrite pe_bexp_correct, H in H7. inversion H7.
+ (* E'WhileLoop *)
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_update _ _ H0) in H7.
apply H1 in H7; [| omega]. inversion H7.
- (* PE_WhileFixed *) generalize dependent st.
induction n using lt_wf_ind; intros st Heval. inversion Heval; subst.
+ (* E'WhileEnd *) rewrite pe_bexp_correct in H8. eauto.
+ (* E'WhileLoop *) rewrite pe_bexp_correct in H5.
edestruct IHHpe1 as [? ? ? Hskip ?]. eassumption.
inversion Hskip. subst.
edestruct IHHpe2. eassumption.
rewrite <- (pe_compare_nil_update _ _ H1) in H8.
apply H2 in H8; [| omega]. inversion H8.
econstructor; [ eapply E_WhileLoop; eauto | eassumption | omega].
Qed.
Theorem pe_com_sound:
forall c pe_st pe_st' c' c'', c / pe_st \\ c' / pe_st' / c'' ->
forall st st'' n,
(c' / pe_st' / c'' / st \\ st'' # n) ->
(c / pe_update st pe_st \\ st'').
Proof. intros c pe_st pe_st' c' c'' Hpe.
induction Hpe;
intros st st'' n [st' n' Heval Heval' Hle];
try (inversion Heval; []; subst);
try (inversion Heval'; []; subst); eauto.
- (* PE_AssStatic *) rewrite <- pe_update_update_add. apply E_Ass.
rewrite -> pe_aexp_correct. rewrite -> H. reflexivity.
- (* PE_AssDynamic *) rewrite <- pe_update_update_remove. apply E_Ass.
rewrite <- pe_aexp_correct. reflexivity.
- (* PE_Seq *) eapply E_Seq; eauto.
- (* PE_IfTrue *) apply E_IfTrue.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
- (* PE_IfFalse *) apply E_IfFalse.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe. eauto.
- (* PE_If *) inversion Heval; subst; inversion H7; subst; clear H7.
+ (* E_IfTrue *)
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
apply E_IfTrue. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
+ (* E_IfFalse *)
eapply ceval_deterministic in H8; [| apply eval_assign]. subst.
rewrite -> pe_compare_update in Heval'.
rewrite <- assign_removes in Heval'.
apply E_IfFalse. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe2. eauto.
- (* PE_WhileEnd *) apply E_WhileEnd.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
- (* PE_WhileLoop *) eapply E_WhileLoop.
rewrite -> pe_bexp_correct. rewrite -> H. reflexivity.
eapply IHHpe1. eauto. eapply IHHpe2. eauto.
- (* PE_While *) inversion Heval; subst.
+ (* E_IfTrue *)
inversion H9. subst. clear H9.
inversion H10. subst. clear H10.
eapply ceval_deterministic in H11; [| apply eval_assign]. subst.
rewrite -> pe_compare_update in Heval'.
rewrite <- assign_removes in Heval'.
eapply E_WhileLoop. rewrite -> pe_bexp_correct. assumption.
eapply IHHpe1. eauto.
eapply IHHpe2. eauto.
+ (* E_IfFalse *) apply ceval_count_sound in Heval'.
eapply ceval_deterministic in H9; [| apply eval_assign]. subst.
rewrite <- assign_removes in Heval'.
inversion H2; subst.
* (* c2'' = SKIP *) inversion Heval'. subst. apply E_WhileEnd.
rewrite -> pe_bexp_correct. assumption.
* (* c2'' = WHILE b1 DO c1 END *) assumption.
- (* PE_WhileFixedEnd *) eapply ceval_count_sound. apply Heval'.
- (* PE_WhileFixedLoop *)
apply loop_never_stops in Heval. inversion Heval.
- (* PE_WhileFixed *)
clear - H1 IHHpe1 IHHpe2 Heval.
remember (WHILE pe_bexp pe_st b1 DO c1';; c2' END) as c'.
induction Heval;
inversion Heqc'; subst; clear Heqc'.
+ (* E_WhileEnd *) apply E_WhileEnd.
rewrite pe_bexp_correct. assumption.
+ (* E_WhileLoop *)
assert (IHHeval2' := IHHeval2 (refl_equal _)).
apply ceval_count_complete in IHHeval2'. inversion IHHeval2'.
clear IHHeval1 IHHeval2 IHHeval2'.
inversion Heval1. subst.
eapply E_WhileLoop. rewrite pe_bexp_correct. assumption. eauto.
eapply IHHpe2. econstructor. eassumption.
rewrite <- (pe_compare_nil_update _ _ H1). eassumption. apply le_n.
Qed.
Corollary pe_com_correct:
forall c pe_st pe_st' c', c / pe_st \\ c' / pe_st' / SKIP ->
forall st st'',
(c / pe_update st pe_st \\ st'') <->
(exists st', c' / st \\ st' /\ pe_update st' pe_st' = st'').
Proof. intros c pe_st pe_st' c' H st st''. split.
- (* -> *) intros Heval.
apply ceval_count_complete in Heval. inversion Heval as [n Heval'].
apply pe_com_complete with (st:=st) (st'':=st'') (n:=n) in H.
inversion H as [? ? ? Hskip ?]. inversion Hskip. subst. eauto.
assumption.
- (* <- *) intros [st' [Heval Heq]]. subst st''.
eapply pe_com_sound in H. apply H.
econstructor. apply Heval. apply E'Skip. apply le_n.
Qed.
End Loop.
(* ################################################################# *)
(** * Partial Evaluation of Flowchart Programs *)
(** Instead of partially evaluating [WHILE] loops directly, the
standard approach to partially evaluating imperative programs is
to convert them into _flowcharts_. In other words, it turns out
that adding labels and jumps to our language makes it much easier
to partially evaluate. The result of partially evaluating a
flowchart is a residual flowchart. If we are lucky, the jumps in
the residual flowchart can be converted back to [WHILE] loops, but
that is not possible in general; we do not pursue it here. *)
(* ================================================================= *)
(** ** Basic blocks *)
(** A flowchart is made of _basic blocks_, which we represent with the
inductive type [block]. A basic block is a sequence of
assignments (the constructor [Assign]), concluding with a
conditional jump (the constructor [If]) or an unconditional jump
(the constructor [Goto]). The destinations of the jumps are
specified by _labels_, which can be of any type. Therefore, we
parameterize the [block] type by the type of labels. *)
Inductive block (Label:Type) : Type :=
| Goto : Label -> block Label
| If : bexp -> Label -> Label -> block Label
| Assign : id -> aexp -> block Label -> block Label.
Arguments Goto {Label} _.
Arguments If {Label} _ _ _.
Arguments Assign {Label} _ _ _.
(** We use the "even or odd" program, expressed above in Imp, as our
running example. Converting this program into a flowchart turns
out to require 4 labels, so we define the following type. *)
Inductive parity_label : Type :=
| entry : parity_label
| loop : parity_label
| body : parity_label
| done : parity_label.
(** The following [block] is the basic block found at the [body] label
of the example program. *)
Definition parity_body : block parity_label :=
Assign Y (AMinus (AId Y) (ANum 1))
(Assign X (AMinus (ANum 1) (AId X))
(Goto loop)).
(** To evaluate a basic block, given an initial state, is to compute
the final state and the label to jump to next. Because basic
blocks do not _contain_ loops or other control structures,
evaluation of basic blocks is a total function -- we don't need to
worry about non-termination. *)
Fixpoint keval {L:Type} (st:state) (k : block L) : state * L :=
match k with
| Goto l => (st, l)
| If b l1 l2 => (st, if beval st b then l1 else l2)
| Assign i a k => keval (t_update st i (aeval st a)) k
end.
Example keval_example:
keval empty_state parity_body
= (t_update (t_update empty_state Y 0) X 1, loop).
Proof. reflexivity. Qed.
(* ================================================================= *)
(** ** Flowchart programs *)
(** A flowchart program is simply a lookup function that maps labels
to basic blocks. Actually, some labels are _halting states_ and
do not map to any basic block. So, more precisely, a flowchart
[program] whose labels are of type [L] is a function from [L] to
[option (block L)]. *)
Definition program (L:Type) : Type := L -> option (block L).
Definition parity : program parity_label := fun l =>
match l with
| entry => Some (Assign X (ANum 0) (Goto loop))
| loop => Some (If (BLe (ANum 1) (AId Y)) body done)
| body => Some parity_body
| done => None (* halt *)
end.
(** Unlike a basic block, a program may not terminate, so we model the
evaluation of programs by an inductive relation [peval] rather
than a recursive function. *)
Inductive peval {L:Type} (p : program L)
: state -> L -> state -> L -> Prop :=
| E_None: forall st l,
p l = None ->
peval p st l st l
| E_Some: forall st l k st' l' st'' l'',
p l = Some k ->
keval st k = (st', l') ->
peval p st' l' st'' l'' ->
peval p st l st'' l''.
Example parity_eval: peval parity empty_state entry empty_state done.
Proof. erewrite f_equal with (f := fun st => peval _ _ _ st _).
eapply E_Some. reflexivity. reflexivity.
eapply E_Some. reflexivity. reflexivity.
apply E_None. reflexivity.
apply functional_extensionality. intros i. rewrite t_update_same; auto.
Qed.
(* ================================================================= *)
(** ** Partial Evaluation of Basic Blocks and Flowchart Programs *)
(** Partial evaluation changes the label type in a systematic way: if
the label type used to be [L], it becomes [pe_state * L]. So the
same label in the original program may be unfolded, or blown up,
into multiple labels by being paired with different partial
states. For example, the label [loop] in the [parity] program
will become two labels: [([(X,0)], loop)] and [([(X,1)], loop)].
This change of label type is reflected in the types of [pe_block]
and [pe_program] defined presently. *)
Fixpoint pe_block {L:Type} (pe_st:pe_state) (k : block L)
: block (pe_state * L) :=
match k with
| Goto l => Goto (pe_st, l)
| If b l1 l2 =>
match pe_bexp pe_st b with
| BTrue => Goto (pe_st, l1)
| BFalse => Goto (pe_st, l2)
| b' => If b' (pe_st, l1) (pe_st, l2)
end
| Assign i a k =>
match pe_aexp pe_st a with
| ANum n => pe_block (pe_add pe_st i n) k
| a' => Assign i a' (pe_block (pe_remove pe_st i) k)
end
end.
Example pe_block_example:
pe_block [(X,0)] parity_body
= Assign Y (AMinus (AId Y) (ANum 1)) (Goto ([(X,1)], loop)).
Proof. reflexivity. Qed.
Theorem pe_block_correct: forall (L:Type) st pe_st k st' pe_st' (l':L),
keval st (pe_block pe_st k) = (st', (pe_st', l')) ->
keval (pe_update st pe_st) k = (pe_update st' pe_st', l').
Proof. intros. generalize dependent pe_st. generalize dependent st.
induction k as [l | b l1 l2 | i a k];
intros st pe_st H.
- (* Goto *) inversion H; reflexivity.
- (* If *)
replace (keval st (pe_block pe_st (If b l1 l2)))
with (keval st (If (pe_bexp pe_st b) (pe_st, l1) (pe_st, l2)))
in H by (simpl; destruct (pe_bexp pe_st b); reflexivity).
simpl in *. rewrite pe_bexp_correct.
destruct (beval st (pe_bexp pe_st b)); inversion H; reflexivity.
- (* Assign *)
simpl in *. rewrite pe_aexp_correct.
destruct (pe_aexp pe_st a); simpl;
try solve [rewrite pe_update_update_add; apply IHk; apply H];
solve [rewrite pe_update_update_remove; apply IHk; apply H].
Qed.
Definition pe_program {L:Type} (p : program L)
: program (pe_state * L) :=
fun pe_l => match pe_l with (pe_st, l) =>
option_map (pe_block pe_st) (p l)
end.
Inductive pe_peval {L:Type} (p : program L)
(st:state) (pe_st:pe_state) (l:L) (st'o:state) (l':L) : Prop :=
| pe_peval_intro : forall st' pe_st',
peval (pe_program p) st (pe_st, l) st' (pe_st', l') ->
pe_update st' pe_st' = st'o ->
pe_peval p st pe_st l st'o l'.
Theorem pe_program_correct:
forall (L:Type) (p : program L) st pe_st l st'o l',
peval p (pe_update st pe_st) l st'o l' <->
pe_peval p st pe_st l st'o l'.
Proof. intros.
split.
- (* -> *) intros Heval.
remember (pe_update st pe_st) as sto.
generalize dependent pe_st. generalize dependent st.
induction Heval as
[ sto l Hlookup | sto l k st'o l' st''o l'' Hlookup Hkeval Heval ];
intros st pe_st Heqsto; subst sto.
+ (* E_None *) eapply pe_peval_intro. apply E_None.
simpl. rewrite Hlookup. reflexivity. reflexivity.
+ (* E_Some *)
remember (keval st (pe_block pe_st k)) as x.
destruct x as [st' [pe_st' l'_]].
symmetry in Heqx. erewrite pe_block_correct in Hkeval by apply Heqx.
inversion Hkeval. subst st'o l'_. clear Hkeval.
edestruct IHHeval. reflexivity. subst st''o. clear IHHeval.
eapply pe_peval_intro; [| reflexivity]. eapply E_Some; eauto.
simpl. rewrite Hlookup. reflexivity.
- (* <- *) intros [st' pe_st' Heval Heqst'o].
remember (pe_st, l) as pe_st_l.
remember (pe_st', l') as pe_st'_l'.
generalize dependent pe_st. generalize dependent l.
induction Heval as
[ st [pe_st_ l_] Hlookup
| st [pe_st_ l_] pe_k st' [pe_st'_ l'_] st'' [pe_st'' l'']
Hlookup Hkeval Heval ];
intros l pe_st Heqpe_st_l;
inversion Heqpe_st_l; inversion Heqpe_st'_l'; repeat subst.
+ (* E_None *) apply E_None. simpl in Hlookup.
destruct (p l'); [ solve [ inversion Hlookup ] | reflexivity ].
+ (* E_Some *)
simpl in Hlookup. remember (p l) as k.
destruct k as [k|]; inversion Hlookup; subst.
eapply E_Some; eauto. apply pe_block_correct. apply Hkeval.
Qed.
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
module BRAMFIFO
#(
parameter p1width = 32,
parameter p2depth = 1024,
parameter p3cntr_width = 10
)
(
input CLK,
input RST_N,
input [p1width-1:0] D_IN,
output [p1width-1:0] D_OUT,
input ENQ,
input DEQ,
output EMPTY_N,
output FULL_N,
output [p3cntr_width-1:0] COUNT,
input CLR
);
reg [p3cntr_width-1:0] wptr, wptr_d, wptr_p1; // reg
reg [p3cntr_width-1:0] rptr, rptr_d, rptr_p1; // reg
reg [p3cntr_width-1:0] dcount, dcount_d; // reg
(* ram_style = "block" *) reg [p1width-1:0] mem [p2depth-1:0];
reg [p1width-1:0] mem_d; // comb
reg [p1width-1:0] dout_r; // register
reg inhibit, inhibit_d;
reg mem_wen; // comb
reg nempty, nempty_d;
reg nfull, nfull_d;
always@(posedge CLK) begin
if(RST_N && !CLR) begin
wptr <= wptr_d;
rptr <= rptr_d;
nfull <= nfull_d;
nempty <= nempty_d;
inhibit <= inhibit_d;
dcount <= dcount_d;
if(mem_wen) mem[wptr] <= D_IN;
end
else begin
rptr <= {p3cntr_width{1'b0}};
wptr <= {p3cntr_width{1'b0}};
nfull <= 1'b1;
nempty <= 1'b0;
inhibit <= 1'b0;
dcount <= {p3cntr_width{1'b0}};
end
end
always@(*) begin
wptr_d = wptr;
rptr_d = rptr;
nfull_d = nfull;
nempty_d = nempty;
mem_wen = 1'b0;
inhibit_d = 1'b0;
wptr_p1 = (wptr + 1) % p2depth;
rptr_p1 = (rptr + 1) % p2depth;
dcount_d = dcount;
if(ENQ) begin
wptr_d = wptr_p1;
mem_wen = 1'b1;
end
if(DEQ) begin
rptr_d = rptr_p1;
end
if(ENQ && DEQ) begin
nfull_d = nfull;
nempty_d = nempty;
if(wptr == rptr) inhibit_d = 1'b1;
end
else if(DEQ && !ENQ) begin
nfull_d = 1'b1;
nempty_d = rptr_p1 != wptr;
dcount_d = dcount-1;
end
else if(ENQ && !DEQ) begin
nfull_d = wptr_p1 != rptr;
nempty_d = 1'b1;
dcount_d = dcount+1;
end
end
assign D_OUT = mem[rptr];
assign EMPTY_N = nempty && !inhibit;
assign FULL_N = nfull;
assign COUNT = dcount;
//synopsys translate off
always@(negedge CLK) begin
if(RST_N) begin
if(ENQ && !FULL_N) begin
$display("ERROR, enqueuing to full BRAMFIFO");
$finish(0);
end
if(DEQ && !EMPTY_N) begin
$display("ERROR, dequeuing to empty BRAMFIFO");
$finish(0);
end
end
end
//synopsys translate on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBP_TB_V
`define SKY130_FD_SC_HD__DFBBP_TB_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfbbp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SET_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 RESET_B = 1'b1;
#200 SET_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 RESET_B = 1'b0;
#340 SET_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SET_B = 1'b1;
#540 RESET_B = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SET_B = 1'bx;
#680 RESET_B = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__dfbbp dut (.D(D), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_2_V
`define SKY130_FD_SC_LS__FILL_DIODE_2_V
/**
* fill_diode: Fill diode.
*
* Verilog wrapper for fill_diode with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill_diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_diode_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fill_diode base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_diode_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fill_diode base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_2_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:29:41 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_1/zynq_design_1_rst_ps7_0_100M_1_stub.v
// Design : zynq_design_1_rst_ps7_0_100M_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2017.2" *)
module zynq_design_1_rst_ps7_0_100M_1(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c2,
locked);
input inclk0;
output c0;
output c2;
output locked;
wire [5:0] sub_wire0;
wire sub_wire3;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire2 = sub_wire0[2:2];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c2 = sub_wire2;
wire locked = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk2_divide_by = 10,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 13,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.gate_lock_signal = "NO",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "300.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "65.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "13"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_wave*.jpg FALSE FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
* ECP5 PicoRV32 demo
*
* Copyright (C) 2017 Clifford Wolf <[email protected]>
* Copyright (C) 2018 David Shah <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
`ifdef PICORV32_V
`error "attosoc.v must be read before picorv32.v!"
`endif
`define PICORV32_REGS picosoc_regs
module attosoc (
input clk,
input reset,
output reg [7:0] led
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
if (reset)
reset_cnt <= 0;
else
reset_cnt <= reset_cnt + !resetn;
end
parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // ROM at 0x0
parameter integer ROM_WORDS = 64;
reg [31:0] rom [0:ROM_WORDS-1];
wire [31:0] rom_rdata = rom[mem_addr[31:2]];
initial $readmemh("firmware.hex", rom);
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire rom_ready = mem_valid && mem_addr[31:24] == 8'h00;
wire iomem_valid;
wire iomem_ready;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_rdata;
assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
assign iomem_ready = 1'b1;
assign iomem_wstrb = mem_wstrb;
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
wire [31:0] spimemio_cfgreg_do;
always @(posedge clk)
if (iomem_valid && iomem_wstrb[0])
led <= iomem_wdata[7:0];
assign mem_ready = (iomem_valid && iomem_ready) || rom_ready;
assign mem_rdata = rom_rdata;
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h 0000_0000),
.BARREL_SHIFTER(0),
.COMPRESSED_ISA(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0),
.ENABLE_IRQ(0),
.ENABLE_IRQ_QREGS(0),
.ENABLE_COUNTERS(0),
.TWO_STAGE_SHIFT(0),
.ENABLE_REGS_16_31(0)
) cpu (
.clk (clk ),
.resetn (resetn ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
endmodule
// Implementation note:
// Replace the following two modules with wrappers for your SRAM cells.
module picosoc_regs (
input clk, wen,
input [5:0] waddr,
input [5:0] raddr1,
input [5:0] raddr2,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] regs [0:31];
always @(posedge clk)
if (wen) regs[waddr[4:0]] <= wdata;
assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_SYMBOL_V
`define SKY130_FD_SC_HS__OR3_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_SYMBOL_V
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream Ethernet FCS checker (64 bit datapath)
*/
module axis_eth_fcs_check_64
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [63:0] s_axis_tdata,
input wire [7:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire s_axis_tuser,
/*
* AXI output
*/
output wire [63:0] m_axis_tdata,
output wire [7:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire m_axis_tuser,
/*
* Status
*/
output wire busy,
output wire error_bad_fcs
);
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_PAYLOAD = 2'd1,
STATE_LAST = 2'd2;
reg [1:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg shift_in;
reg shift_reset;
reg [7:0] last_cycle_tkeep_reg = 8'd0, last_cycle_tkeep_next;
reg last_cycle_tuser_reg = 1'b0, last_cycle_tuser_next;
reg [63:0] s_axis_tdata_d0 = 64'd0;
reg [7:0] s_axis_tkeep_d0 = 8'd0;
reg s_axis_tvalid_d0 = 1'b0;
reg s_axis_tuser_d0 = 1'b0;
reg busy_reg = 1'b0;
reg error_bad_fcs_reg = 1'b0, error_bad_fcs_next;
reg s_axis_tready_reg = 1'b0, s_axis_tready_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
reg [31:0] crc_state3 = 32'hFFFFFFFF;
wire [31:0] crc_next0;
wire [31:0] crc_next1;
wire [31:0] crc_next2;
wire [31:0] crc_next3;
wire [31:0] crc_next7;
wire crc_valid0 = crc_next0 == ~32'h2144df1c;
wire crc_valid1 = crc_next1 == ~32'h2144df1c;
wire crc_valid2 = crc_next2 == ~32'h2144df1c;
wire crc_valid3 = crc_next3 == ~32'h2144df1c;
// internal datapath
reg [63:0] m_axis_tdata_int;
reg [7:0] m_axis_tkeep_int;
reg m_axis_tvalid_int;
reg m_axis_tready_int_reg = 1'b0;
reg m_axis_tlast_int;
reg m_axis_tuser_int;
wire m_axis_tready_int_early;
assign s_axis_tready = s_axis_tready_reg;
assign busy = busy_reg;
assign error_bad_fcs = error_bad_fcs_reg;
wire last_cycle = state_reg == STATE_LAST;
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(8),
.STYLE("AUTO")
)
eth_crc_8 (
.data_in(last_cycle ? s_axis_tdata_d0[39:32] : s_axis_tdata[7:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next0)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(16),
.STYLE("AUTO")
)
eth_crc_16 (
.data_in(last_cycle ? s_axis_tdata_d0[47:32] : s_axis_tdata[15:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next1)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(24),
.STYLE("AUTO")
)
eth_crc_24 (
.data_in(last_cycle ? s_axis_tdata_d0[55:32] : s_axis_tdata[23:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next2)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(32),
.STYLE("AUTO")
)
eth_crc_32 (
.data_in(last_cycle ? s_axis_tdata_d0[63:32] : s_axis_tdata[31:0]),
.state_in(last_cycle ? crc_state3 : crc_state),
.data_out(),
.state_out(crc_next3)
);
lfsr #(
.LFSR_WIDTH(32),
.LFSR_POLY(32'h4c11db7),
.LFSR_CONFIG("GALOIS"),
.LFSR_FEED_FORWARD(0),
.REVERSE(1),
.DATA_WIDTH(64),
.STYLE("AUTO")
)
eth_crc_64 (
.data_in(s_axis_tdata[63:0]),
.state_in(crc_state),
.data_out(),
.state_out(crc_next7)
);
always @* begin
state_next = STATE_IDLE;
reset_crc = 1'b0;
update_crc = 1'b0;
shift_in = 1'b0;
shift_reset = 1'b0;
last_cycle_tkeep_next = last_cycle_tkeep_reg;
last_cycle_tuser_next = last_cycle_tuser_reg;
s_axis_tready_next = 1'b0;
m_axis_tdata_int = 64'd0;
m_axis_tkeep_int = 8'd0;
m_axis_tvalid_int = 1'b0;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
error_bad_fcs_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
s_axis_tready_next = m_axis_tready_int_early;
reset_crc = 1'b1;
m_axis_tdata_int = s_axis_tdata_d0;
m_axis_tkeep_int = s_axis_tkeep_d0;
m_axis_tvalid_int = s_axis_tvalid_d0 && s_axis_tvalid;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
shift_in = 1'b1;
reset_crc = 1'b0;
update_crc = 1'b1;
if (s_axis_tlast) begin
if (s_axis_tkeep[7:4] == 0) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = s_axis_tuser;
m_axis_tkeep_int = {s_axis_tkeep[3:0], 4'b1111};
if ((s_axis_tkeep[3:0] == 4'b0001 && crc_valid0) ||
(s_axis_tkeep[3:0] == 4'b0011 && crc_valid1) ||
(s_axis_tkeep[3:0] == 4'b0111 && crc_valid2) ||
(s_axis_tkeep[3:0] == 4'b1111 && crc_valid3)) begin
// CRC valid
end else begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
last_cycle_tkeep_next = {4'b0000, s_axis_tkeep[7:4]};
last_cycle_tuser_next = s_axis_tuser;
s_axis_tready_next = 1'b0;
state_next = STATE_LAST;
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// transfer payload
s_axis_tready_next = m_axis_tready_int_early;
m_axis_tdata_int = s_axis_tdata_d0;
m_axis_tkeep_int = s_axis_tkeep_d0;
m_axis_tvalid_int = s_axis_tvalid_d0 && s_axis_tvalid;
m_axis_tlast_int = 1'b0;
m_axis_tuser_int = 1'b0;
if (s_axis_tready && s_axis_tvalid) begin
shift_in = 1'b1;
update_crc = 1'b1;
if (s_axis_tlast) begin
if (s_axis_tkeep[7:4] == 0) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = s_axis_tuser;
m_axis_tkeep_int = {s_axis_tkeep[3:0], 4'b1111};
if ((s_axis_tkeep[3:0] == 4'b0001 && crc_valid0) ||
(s_axis_tkeep[3:0] == 4'b0011 && crc_valid1) ||
(s_axis_tkeep[3:0] == 4'b0111 && crc_valid2) ||
(s_axis_tkeep[3:0] == 4'b1111 && crc_valid3)) begin
// CRC valid
end else begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
last_cycle_tkeep_next = {4'b0000, s_axis_tkeep[7:4]};
last_cycle_tuser_next = s_axis_tuser;
s_axis_tready_next = 1'b0;
state_next = STATE_LAST;
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
state_next = STATE_PAYLOAD;
end
end
STATE_LAST: begin
// last cycle
s_axis_tready_next = 1'b0;
m_axis_tdata_int = s_axis_tdata_d0;
m_axis_tkeep_int = last_cycle_tkeep_reg;
m_axis_tvalid_int = s_axis_tvalid_d0;
m_axis_tlast_int = 1'b1;
m_axis_tuser_int = last_cycle_tuser_reg;
if ((s_axis_tkeep_d0[7:4] == 4'b0001 && crc_valid0) ||
(s_axis_tkeep_d0[7:4] == 4'b0011 && crc_valid1) ||
(s_axis_tkeep_d0[7:4] == 4'b0111 && crc_valid2) ||
(s_axis_tkeep_d0[7:4] == 4'b1111 && crc_valid3)) begin
// CRC valid
end else begin
m_axis_tuser_int = 1'b1;
error_bad_fcs_next = 1'b1;
end
if (m_axis_tready_int_reg) begin
shift_reset = 1'b1;
reset_crc = 1'b1;
s_axis_tready_next = m_axis_tready_int_early;
state_next = STATE_IDLE;
end else begin
state_next = STATE_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_axis_tready_reg <= 1'b0;
busy_reg <= 1'b0;
error_bad_fcs_reg <= 1'b0;
s_axis_tvalid_d0 <= 1'b0;
crc_state <= 32'hFFFFFFFF;
crc_state3 <= 32'hFFFFFFFF;
end else begin
state_reg <= state_next;
s_axis_tready_reg <= s_axis_tready_next;
busy_reg <= state_next != STATE_IDLE;
error_bad_fcs_reg <= error_bad_fcs_next;
// datapath
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
crc_state3 <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next7;
crc_state3 <= crc_next3;
end
if (shift_reset) begin
s_axis_tvalid_d0 <= 1'b0;
end else if (shift_in) begin
s_axis_tvalid_d0 <= s_axis_tvalid;
end
end
last_cycle_tkeep_reg <= last_cycle_tkeep_next;
last_cycle_tuser_reg <= last_cycle_tuser_next;
if (shift_in) begin
s_axis_tdata_d0 <= s_axis_tdata;
s_axis_tkeep_d0 <= s_axis_tkeep;
s_axis_tuser_d0 <= s_axis_tuser;
end
end
// output datapath logic
reg [63:0] m_axis_tdata_reg = 64'd0;
reg [7:0] m_axis_tkeep_reg = 8'd0;
reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
reg m_axis_tlast_reg = 1'b0;
reg m_axis_tuser_reg = 1'b0;
reg [63:0] temp_m_axis_tdata_reg = 64'd0;
reg [7:0] temp_m_axis_tkeep_reg = 8'd0;
reg temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
reg temp_m_axis_tlast_reg = 1'b0;
reg temp_m_axis_tuser_reg = 1'b0;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = m_axis_tkeep_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = m_axis_tlast_reg;
assign m_axis_tuser = m_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_axis_tvalid_next = m_axis_tvalid_reg;
temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_tready_int_reg) begin
// input is ready
if (m_axis_tready || !m_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_tvalid_next = m_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_tready) begin
// input is not ready, but output is ready
m_axis_tvalid_next = temp_m_axis_tvalid_reg;
temp_m_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_tvalid_reg <= 1'b0;
m_axis_tready_int_reg <= 1'b0;
temp_m_axis_tvalid_reg <= 1'b0;
end else begin
m_axis_tvalid_reg <= m_axis_tvalid_next;
m_axis_tready_int_reg <= m_axis_tready_int_early;
temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_tdata_reg <= m_axis_tdata_int;
m_axis_tkeep_reg <= m_axis_tkeep_int;
m_axis_tlast_reg <= m_axis_tlast_int;
m_axis_tuser_reg <= m_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_axis_tdata_reg <= temp_m_axis_tdata_reg;
m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
m_axis_tlast_reg <= temp_m_axis_tlast_reg;
m_axis_tuser_reg <= temp_m_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_tdata_reg <= m_axis_tdata_int;
temp_m_axis_tkeep_reg <= m_axis_tkeep_int;
temp_m_axis_tlast_reg <= m_axis_tlast_int;
temp_m_axis_tuser_reg <= m_axis_tuser_int;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFBBP_TB_V
`define SKY130_FD_SC_HDLL__SDFBBP_TB_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfbbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 SET_B = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 D = 1'b1;
#220 RESET_B = 1'b1;
#240 SCD = 1'b1;
#260 SCE = 1'b1;
#280 SET_B = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 D = 1'b0;
#400 RESET_B = 1'b0;
#420 SCD = 1'b0;
#440 SCE = 1'b0;
#460 SET_B = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 SET_B = 1'b1;
#660 SCE = 1'b1;
#680 SCD = 1'b1;
#700 RESET_B = 1'b1;
#720 D = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 SET_B = 1'bx;
#840 SCE = 1'bx;
#860 SCD = 1'bx;
#880 RESET_B = 1'bx;
#900 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__sdfbbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFBBP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FA_BEHAVIORAL_V
`define SKY130_FD_SC_MS__FA_BEHAVIORAL_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT;
wire or2_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT , or1_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out);
buf buf1 (SUM , or2_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FA_BEHAVIORAL_V |
/******************************************************************************/
/* Test Bench for FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
`include "user_logic.v"
`include "sorter.v"
/******************************************************************************/
module tb_USER_LOGIC();
reg CLK, RST;
wire chnl_rx_clk;
wire chnl_rx;
wire chnl_rx_ack;
wire chnl_rx_last;
wire [31:0] chnl_rx_len;
wire [30:0] chnl_rx_off;
wire [128-1:0] chnl_rx_data;
wire chnl_rx_data_valid;
wire chnl_rx_data_ren;
wire chnl_tx_clk;
wire chnl_tx;
wire chnl_tx_ack;
wire chnl_tx_last;
wire [31:0] chnl_tx_len;
wire [30:0] chnl_tx_off;
wire [128-1:0] chnl_tx_data;
wire chnl_tx_data_vaild;
wire chnl_tx_data_ren = 1;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
reg sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase_a==0) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase_a==1) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase_a==2) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase_a==3) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase_a==4) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase_a==5) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase_a==6) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase_a==7) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase_a==8) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase_a==9) ? cnt9 + 1 : cnt9;
reg [31:0] rslt_cnt;
always @(posedge CLK) begin
if (RST) begin
rslt_cnt <= 0;
end else begin
if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4;
end
end
always @(posedge CLK) begin
if (RST) sortdone <= 0;
else if (rslt_cnt == `SORT_ELM) sortdone <= 1;
end
// Debug Info
always @(posedge CLK) begin
if (!RST) begin
$write("%d|%d|Pa%dPb%d|%d%d%d|%d", cnt[19:0], u.core.elem_a, u.core.phase_a[2:0], u.core.phase_b[2:0], u.core.iter_done_a, u.core.pchange_a, u.core.irst_a, u.core.ecnt_a);
$write("|");
if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" ");
// $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero);
// if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" ");
$write("|");
$write("(%d)", u.core.state);
$write("| %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d| %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d|",
u.core.im00_a.imf.cnt, u.core.im01_a.imf.cnt, u.core.im02_a.imf.cnt, u.core.im03_a.imf.cnt,
u.core.im04_a.imf.cnt, u.core.im05_a.imf.cnt, u.core.im06_a.imf.cnt, u.core.im07_a.imf.cnt,
u.core.im08_a.imf.cnt, u.core.im09_a.imf.cnt, u.core.im10_a.imf.cnt, u.core.im11_a.imf.cnt,
u.core.im12_a.imf.cnt, u.core.im13_a.imf.cnt, u.core.im14_a.imf.cnt, u.core.im15_a.imf.cnt,
u.core.im00_b.imf.cnt, u.core.im01_b.imf.cnt, u.core.im02_b.imf.cnt, u.core.im03_b.imf.cnt,
u.core.im04_b.imf.cnt, u.core.im05_b.imf.cnt, u.core.im06_b.imf.cnt, u.core.im07_b.imf.cnt,
u.core.im08_b.imf.cnt, u.core.im09_b.imf.cnt, u.core.im10_b.imf.cnt, u.core.im11_b.imf.cnt,
u.core.im12_b.imf.cnt, u.core.im13_b.imf.cnt, u.core.im14_b.imf.cnt, u.core.im15_b.imf.cnt);
if (u.core.im00_b.imf.cnt > 128) begin $write("\noverflow at im00_b"); $finish(); end
if (u.core.im01_b.imf.cnt > 128) begin $write("\noverflow at im01_b"); $finish(); end
if (u.core.im02_b.imf.cnt > 128) begin $write("\noverflow at im02_b"); $finish(); end
if (u.core.im03_b.imf.cnt > 128) begin $write("\noverflow at im03_b"); $finish(); end
if (u.core.im04_b.imf.cnt > 128) begin $write("\noverflow at im04_b"); $finish(); end
if (u.core.im05_b.imf.cnt > 128) begin $write("\noverflow at im05_b"); $finish(); end
if (u.core.im06_b.imf.cnt > 128) begin $write("\noverflow at im06_b"); $finish(); end
if (u.core.im07_b.imf.cnt > 128) begin $write("\noverflow at im07_b"); $finish(); end
if (u.core.im08_b.imf.cnt > 128) begin $write("\noverflow at im08_b"); $finish(); end
if (u.core.im09_b.imf.cnt > 128) begin $write("\noverflow at im09_b"); $finish(); end
if (u.core.im10_b.imf.cnt > 128) begin $write("\noverflow at im10_b"); $finish(); end
if (u.core.im11_b.imf.cnt > 128) begin $write("\noverflow at im11_b"); $finish(); end
if (u.core.im12_b.imf.cnt > 128) begin $write("\noverflow at im12_b"); $finish(); end
if (u.core.im13_b.imf.cnt > 128) begin $write("\noverflow at im13_b"); $finish(); end
if (u.core.im14_b.imf.cnt > 128) begin $write("\noverflow at im14_b"); $finish(); end
if (u.core.im15_b.imf.cnt > 128) begin $write("\noverflow at im15_b"); $finish(); end
$write(" ");
if (u.core.F01_deq_a) $write("%08x %08x %08x %08x ", u.core.F01_dot_a[127:96], u.core.F01_dot_a[95:64], u.core.F01_dot_a[63:32], u.core.F01_dot_a[31:0]); else $write(" ");
if (u.core.F01_deq_b) $write("%08x %08x %08x %08x ", u.core.F01_dot_b[127:96], u.core.F01_dot_b[95:64], u.core.F01_dot_b[63:32], u.core.F01_dot_b[31:0]); else $write(" ");
// $write("| ");
// $write("%d", u.core.dcnt);
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
// checking the result
generate
if (`INITTYPE=="sorted" || `INITTYPE=="reverse") begin
reg [`MERGW-1:0] check_cnt;
always @(posedge CLK) begin
if (RST) begin
check_cnt[31 : 0] <= 1;
check_cnt[63 :32] <= 2;
check_cnt[95 :64] <= 3;
check_cnt[127:96] <= 4;
end else begin
if (chnl_tx_data_vaild) begin
if (check_cnt != chnl_tx_data) begin
$write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt[31 : 0] <= check_cnt[31 : 0] + 4;
check_cnt[63 :32] <= check_cnt[63 :32] + 4;
check_cnt[95 :64] <= check_cnt[95 :64] + 4;
check_cnt[127:96] <= check_cnt[127:96] + 4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (chnl_tx_data_vaild) begin
$fwrite(fp, "%08x\n", chnl_tx_data[31:0]);
$fwrite(fp, "%08x\n", chnl_tx_data[63:32]);
$fwrite(fp, "%08x\n", chnl_tx_data[95:64]);
$fwrite(fp, "%08x\n", chnl_tx_data[127:96]);
$fflush();
end
if (sortdone) $fclose(fp);
end
end else begin
always @(posedge CLK) begin
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.vh\n");
$finish();
end
end
endgenerate
// Show the elapsed cycles
always @(posedge CLK) begin
if(sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
// Stub modules
/**********************************************************************************************/
Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len);
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
/***** Core Module Instantiation *****/
/**********************************************************************************************/
USER_LOGIC u(CLK,
RST,
chnl_rx_clk,
chnl_rx,
chnl_rx_ack,
chnl_rx_last,
chnl_rx_len,
chnl_rx_off,
chnl_rx_data,
chnl_rx_data_valid,
chnl_rx_data_ren,
chnl_tx_clk,
chnl_tx,
chnl_tx_ack,
chnl_tx_last,
chnl_tx_len,
chnl_tx_off,
chnl_tx_data,
chnl_tx_data_vaild,
chnl_tx_data_ren,
d_busy, // DRAM busy
d_din, // DRAM data in
d_w, // DRAM write flag
d_dout, // DRAM data out
d_douten, // DRAM data out enable
d_req, // DRAM REQ access request (read/write)
d_initadr, // DRAM REQ initial address for the access
d_blocks // DRAM REQ the number of blocks per one access
);
endmodule
/**************************************************************************************************/
/***** Xorshift *****/
/**************************************************************************************************/
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule
/**************************************************************************************************/
module Host_to_FPGA(input wire CLK,
input wire RST,
input wire ren,
output reg chnl_rx,
output wire [`MERGW-1:0] dot,
output wire doten,
output wire [31:0] length);
reg rst_buf; always @(posedge CLK) rst_buf <= RST;
wire enq;
wire deq;
wire [`MERGW-1:0] din;
wire emp;
wire ful;
wire [4:0] cnt;
reg [`SORTW-1:0] i_d,i_c,i_b,i_a;
reg onetime;
reg [31:0] enqcnt;
reg enqstop;
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
reg [1:0] selector;
wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,r01,r00} :
(selector == 1) ? {r07,r06,r05,r04} :
(selector == 2) ? {r11,r10,r09,r08} :
(selector == 3) ? {r15,r14,r13,r12} : 0;
SRL_FIFO #(4, `MERGW) fifo(CLK, rst_buf, enq, deq, din, dot, emp, ful, cnt);
assign enq = (!enqstop && !ful);
assign deq = (ren && !emp);
assign din = (`INITTYPE=="xorshift") ? din_xorshift : {i_d,i_c,i_b,i_a};
assign doten = deq;
assign length = `SORT_ELM;
always @(posedge CLK) begin
if (rst_buf) begin
chnl_rx <= 0;
onetime <= 1;
end else begin
chnl_rx <= onetime;
onetime <= 0;
end
end
always @(posedge CLK) begin
if (rst_buf) enqcnt <= 0;
else if (enq) enqcnt <= enqcnt + 4;
end
always @(posedge CLK) begin
if (rst_buf) enqstop <= 0;
else if (enq && (enqcnt == `SORT_ELM-4)) enqstop <= 1;
end
always @(posedge CLK) begin
if (rst_buf) selector <= 0;
else if (enq) selector <= selector + 1;
end
generate
if (`INITTYPE=="sorted") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
end else begin
if (enq) begin
i_a <= i_a+4;
i_b <= i_b+4;
i_c <= i_c+4;
i_d <= i_d+4;
end
end
end
end else if (`INITTYPE=="reverse") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= `SORT_ELM;
i_b <= `SORT_ELM-1;
i_c <= `SORT_ELM-2;
i_d <= `SORT_ELM-3;
end else begin
if (enq) begin
i_a <= i_a-4;
i_b <= i_b-4;
i_c <= i_c-4;
i_d <= i_d-4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST, (enq && selector == 0), r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST, (enq && selector == 0), r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST, (enq && selector == 0), r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST, (enq && selector == 0), r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST, (enq && selector == 1), r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST, (enq && selector == 1), r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST, (enq && selector == 1), r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST, (enq && selector == 1), r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST, (enq && selector == 2), r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST, (enq && selector == 2), r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST, (enq && selector == 2), r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST, (enq && selector == 2), r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST, (enq && selector == 3), r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST, (enq && selector == 3), r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST, (enq && selector == 3), r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST, (enq && selector == 3), r15);
end
endgenerate
endmodule
/**************************************************************************************************/
module DRAM(input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211O_2_V
`define SKY130_FD_SC_HDLL__A211O_2_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a211o_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a211o_2 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211O_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SREGSBP_BEHAVIORAL_PP_V
/**
* sregsbp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sregsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire set ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire ASYNC_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (set , ASYNC_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, set, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( ASYNC_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( ASYNC === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGSBP_BEHAVIORAL_PP_V |
//
// Copyright (c) 2012-2013 Jonathan Woodruff
// Copyright (c) 2013-2014 Bjoern A. Zeeb
// Copyright (c) 2014 A. Theodore Markettos
// Copyright (c) 2014 Alex Horsman
// All rights reserved.
//
// This software was developed by SRI International and the University of
// Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
// ("CTSRD"), as part of the DARPA CRASH research programme.
//
// This software was developed by SRI International and the University of
// Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249
// ("MRC2"), as part of the DARPA MRC research programme.
//
// @BERI_LICENSE_HEADER_START@
//
// Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
// license agreements. See the NOTICE file distributed with this work for
// additional information regarding copyright ownership. BERI licenses this
// file to you under the BERI Hardware-Software License, Version 1.0 (the
// "License"); you may not use this file except in compliance with the
// License. You may obtain a copy of the License at:
//
// http://www.beri-open-systems.org/legal/license-1-0.txt
//
// Unless required by applicable law or agreed to in writing, Work distributed
// under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// @BERI_LICENSE_HEADER_END@
//
`define ENABLE_LED
`define ENABLE_BUTTONS
`define ENABLE_ETHERNET
//`define ENABLE_SDCARD
//`define ENABLE_UART
`define ENABLE_DDR2_1
`define ENABLE_DIP
`define ENABLE_SLIDE
`define ENABLE_SEG
`define ENABLE_TEMP
`define ENABLE_CSENSE
`define ENABLE_FLASH
//`define ENABLE_SSRAM
`define ENABLE_USB
`define ENABLE_HDMI
//`define ENABLE_MTL
`ifndef ENABLE_DDR2_1
`ifndef ENABLE_DDR2_2
`define DISABLE_TERMINATION
`endif
`endif
`ifndef ENABLE_FLASH
`ifndef ENABLE_SSRAM
`define DISABLE_FSM
`endif
`endif
module DE4_BERI (
////// clock inputs
//input GCLKIN,
//output GCLKOUT_FPGA,
//inout [2:0] MAX_CONF_D,
//output [2:0] MAX_PLL_D,
input OSC_50_Bank2,
input OSC_50_Bank3,
input OSC_50_Bank4,
input OSC_50_Bank5,
input OSC_50_Bank6,
//input OSC_50_Bank7,
//input PLL_CLKIN_p,
`ifdef ENABLE_LED
output [7:0] LED, // 8x LEDs
`endif
`ifdef ENABLE_BUTTONS
input [3:0] BUTTON, // 4x buttons
`endif
input CPU_RESET_n,
//inout EXT_IO,
`ifdef ENABLE_ETHERNET
////// Ethernet MAC x 4
input [3:0] ETH_INT_n,
output [3:0] ETH_MDC,
inout [3:0] ETH_MDIO,
output ETH_RST_n,
input [3:0] ETH_RX_p,
output [3:0] ETH_TX_p,
`endif
`ifdef ENABLE_SDCARD
////// SD card socket
output SD_CLK,
inout SD_CMD,
inout [3:0] SD_DAT,
input SD_WP_n,
`endif
`ifdef ENABLE_UART
////// UART
output UART_TXD,
input UART_CTS,
input UART_RXD,
output UART_RTS,
`endif
`ifdef ENABLE_DDR2_1
////// DDR2 SODIMM 1
output [15:0] M1_DDR2_addr,
output [2:0] M1_DDR2_ba,
output M1_DDR2_cas_n,
output [1:0] M1_DDR2_cke,
inout [1:0] M1_DDR2_clk,
inout [1:0] M1_DDR2_clk_n,
output [1:0] M1_DDR2_cs_n,
output [7:0] M1_DDR2_dm,
inout [63:0] M1_DDR2_dq,
inout [7:0] M1_DDR2_dqs,
inout [7:0] M1_DDR2_dqsn,
output [1:0] M1_DDR2_odt,
output M1_DDR2_ras_n,
output [1:0] M1_DDR2_SA,
output M1_DDR2_SCL,
inout M1_DDR2_SDA,
output M1_DDR2_we_n,
`endif
`ifdef ENABLE_DDR2_2
////// DDR2 SODIMM 2
output [15:0] M2_DDR2_addr,
output [2:0] M2_DDR2_ba,
output M2_DDR2_cas_n,
output [1:0] M2_DDR2_cke,
inout [1:0] M2_DDR2_clk,
inout [1:0] M2_DDR2_clk_n,
output [1:0] M2_DDR2_cs_n,
output [7:0] M2_DDR2_dm,
inout [63:0] M2_DDR2_dq,
inout [7:0] M2_DDR2_dqs,
inout [7:0] M2_DDR2_dqsn,
output [1:0] M2_DDR2_odt,
output M2_DDR2_ras_n,
output [1:0] M2_DDR2_SA,
output M2_DDR2_SCL,
inout M2_DDR2_SDA,
output M2_DDR2_we_n,
`endif
`ifndef DISABLE_TERMINATION
// termination for DDR2 DIMMs
input termination_blk0_rup_pad,
input termination_blk0_rdn_pad,
`endif
`ifdef ENABLE_DIP
input [7:0] SW, // 8x DIP switches
`endif
`ifdef ENABLE_SLIDE
input [3:0] SLIDE_SW, // 4x slide switches
`endif
`ifdef ENABLE_SEG
// 2x 7-segment displays
output [6:0] SEG0_D,
output SEG0_DP,
output [6:0] SEG1_D,
output SEG1_DP,
`endif
`ifdef ENABLE_TEMP
// temperature sensors
input TEMP_INT_n,
output TEMP_SMCLK,
inout TEMP_SMDAT,
`endif
`ifdef ENABLE_CSENSE
// current sensors
output CSENSE_ADC_FO,
output [1:0] CSENSE_CS_n,
output CSENSE_SCK,
output CSENSE_SDI,
input CSENSE_SDO,
`endif
output FAN_CTRL, // fan control
`ifndef DISABLE_FSM
// flash and SRAM shared data bus
output [25:1] FSM_A,
inout [15:0] FSM_D,
`endif
`ifdef ENABLE_FLASH
// Flash memory
output FLASH_ADV_n,
output FLASH_CE_n,
output FLASH_CLK,
output FLASH_OE_n,
output FLASH_RESET_n,
input FLASH_RYBY_n,
output FLASH_WE_n,
`endif
`ifdef ENABLE_SSRAM
// synchronous SRAM
output SSRAM_ADV,
output SSRAM_BWA_n,
output SSRAM_BWB_n,
output SSRAM_CE_n,
output SSRAM_CKE_n,
output SSRAM_CLK,
output SSRAM_OE_n,
output SSRAM_WE_n,
`endif
// HSMC port A and B
`ifdef ENABLE_HDMI
// HDMI interface board on HSMC port A
//inout HDMI_SDA,
//output HDMI_SCL,
output [11:0] HDMI_TX_RD,
output [11:0] HDMI_TX_GD,
inout HDMI_TX_PCSCL,
inout HDMI_TX_PCSDA,
output HDMI_TX_RST_N,
input HDMI_TX_INT_N,
output [3:0] HDMI_TX_DSD_L,
output [3:0] HDMI_TX_DSD_R,
output [11:0] HDMI_TX_BD,
output HDMI_TX_PCLK,
output HDMI_TX_DCLK,
output HDMI_TX_SCK,
output HDMI_TX_WS,
output HDMI_TX_MCLK,
output [3:0] HDMI_TX_I2S,
output HDMI_TX_DE,
output HDMI_TX_VS,
output HDMI_TX_HS,
output HDMI_TX_SPDIF,
inout HDMI_TX_CEC,
`endif
// GPIO port 0
input [31:0] GPIO0_D,
`ifdef ENABLE_USB
output [17:1] OTG_A,
output OTG_CS_n,
inout [31:0] OTG_D,
output OTG_DC_DACK,
input OTG_DC_DREQ,
input OTG_DC_IRQ,
output OTG_HC_DACK,
input OTG_HC_DREQ,
input OTG_HC_IRQ,
output OTG_OE_n,
output OTG_RESET_n,
output OTG_WE_n
`endif
`ifdef ENABLE_MTL
// GPIO port 1 connect to MTL capacitive touch screen
output mtl_dclk,
output [7:0] mtl_r,
output [7:0] mtl_g,
output [7:0] mtl_b,
output mtl_hsd,
output mtl_vsd,
output mtl_touch_i2cscl,
inout mtl_touch_i2csda,
input mtl_touch_int
`endif
`ifdef ENABLE_PCIE
,
//PCI Express
input PCIE_PREST_n,
input PCIE_REFCLK_p,
//input HSMA_REFCLK_p,
input [3:0] PCIE_RX_p,
input PCIE_SMBCLK,
inout PCIE_SMBDAT,
output [3:0] PCIE_TX_p,
output PCIE_WAKE_n
`endif
);
wire global_reset_n;
wire enet_reset_n;
//// Ethernet
wire enet_mdc;
wire enet_mdio_in;
wire enet_mdio_oen;
wire enet_mdio_out;
wire enet_refclk_125MHz;
wire lvds_rxp;
wire lvds_txp;
wire enet1_mdc;
wire enet1_mdio_in;
wire enet1_mdio_oen;
wire enet1_mdio_out;
wire lvds_rxp1;
wire lvds_txp1;
// Assign outputs that are not used to 0
//assign MAX_PLL_D = 3'b0;
//assign ETH_MDC[3:1] = 3'b0;
assign M1_DDR2_SA = 1'b0;
assign CSENSE_CS_n = 1'b0;
assign CSENSE_ADC_FO = 1'b0;
assign CSENSE_SCK = 1'b0;
assign CSENSE_SDI = 1'b0;
//assign GCLKOUT_FPGA = 1'b0;
assign M1_DDR2_SCL = 1'b0;
//// Ethernet
assign ETH_RST_n = rstn;
assign ETH_TX_p[3:2] = 2'b0;
assign lvds_rxp = ETH_RX_p[0];
assign ETH_TX_p[0] = lvds_txp;
assign lvds_rxp1 = ETH_RX_p[1];
assign ETH_TX_p[1] = lvds_txp1;
assign enet_mdio_in = ETH_MDIO[0];
assign enet1_mdio_in = ETH_MDIO[1];
assign ETH_MDIO[0] = (!enet_mdio_oen ? enet_mdio_out : 1'bz);
assign ETH_MDIO[1] = (!enet1_mdio_oen ? enet1_mdio_out : 1'bz);
// Allow the other two tri-state interfaces to float.
assign ETH_MDIO[2] = 1'bz;
assign ETH_MDIO[3] = 1'bz;
assign ETH_MDC[0] = enet_mdc;
assign ETH_MDC[1] = enet1_mdc;
// Set unused interface clocks to high.
assign ETH_MDC[2] = 1'b1;
assign ETH_MDC[3] = 1'b1;
wire clk100;
wire [7:0] LED_n;
assign LED = ~LED_n;
reg [31:0] LED_reg;
//assign LED = LED_reg[31:24];
always @(posedge HDMI_TX_PCLK)
begin
LED_reg <= LED_reg + 1;
end
// === Ethernet clock PLL
pll_125 pll_125_ins (
.inclk0(OSC_50_Bank2),
.c0(enet_refclk_125MHz)
);
// === System clock PLL
wire qsys_sysclk;
wire qsys_50_clk;
assign qsys_50_clk = OSC_50_Bank6;
`ifdef ENABLE_PCIE
wire clk125;
//PCI Express clock
pll_125 pll_125_pcie (
.inclk0(OSC_50_Bank2),
.c0(clk125)
);
assign reconfig_clk = OSC_50_Bank3;
wire reconfig_fromgxb;
wire reconfig_togxb;
wire reconfig_busy;
altgx_reconfig altgx_reconfig_pcie (
.reconfig_clk(reconfig_clk),
.reconfig_fromgxb(reconfig_fromgxb),
.busy(reconfig_busy),
.reconfig_togxb(reconfig_togxb)
);
`endif
wire qsys_sysreset_n;
//wire sramClk;
assign SSRAM_CLK = qsys_sysclk;
(* keep = 1 *) wire clk27;
display_pll display_pll_ins (
.inclk0(OSC_50_Bank2),
.c0(clk27)
);
// synchronize reset signal
reg rstn, rstn_metastable;
always @(posedge qsys_50_clk)
begin
rstn_metastable <= CPU_RESET_n && GPIO0_D[2];
rstn <= rstn_metastable;
end
reg rstn100, rstn100_metastable;
always @(posedge qsys_sysclk)
begin
rstn100_metastable <= CPU_RESET_n && GPIO0_D[2];
rstn100 <= rstn100_metastable;
end
(* noprune *) reg rstn27;
reg rstn27sample;
always @(posedge clk27)
begin
rstn27sample <= rstn;
rstn27 <= rstn27sample;
end
reg [7:0] SW_P;
always @(posedge qsys_50_clk) SW_P <= ~SW; // positive version of DIP switches
assign SEG1_DP = ~1'b0;
assign SEG0_DP = ~1'b0;
reg [3:0] slide_sw_metastable, slide_sw_sync;
always @(posedge qsys_50_clk)
begin
slide_sw_metastable <= SLIDE_SW;
slide_sw_sync <= slide_sw_metastable;
end
// assign PCIE_WAKE_n = 1'b0;
// assign PCIE_SMBDATA = 1'bz;
/* signals for the old Terasic resistive touch screen (currently unused)
wire [7:0] vga_R, vga_G, vga_B;
wire vga_DEN, vga_HD, vga_VD;
assign vga_DEN = 1'b0;
assign vga_HD = 1'b0;
assign vga_VD = 1'b0;
assign vga_R = 8'd0;
assign vga_G = 8'd0;
assign vga_B = 8'd0;
assign lcdtouchLTM_R = vga_R;
assign lcdtouchLTM_G = vga_G;
assign lcdtouchLTM_B = vga_B;
assign lcdtouchLTM_DEN = vga_DEN;
assign lcdtouchLTM_HD = vga_HD;
assign lcdtouchLTM_VD = vga_VD;
assign lcdtouchLTM_GREST = rstn27;
assign lcdtouchLTM_NCLK = clk27;
assign lcdtouchLTM_SCEN = 1'b1;
assign lcdtouchLTM_ADC_DCLK = 1'b1;
assign lcdtouchLTM_ADC_DIN = 1'b1;*/
// clock for multitouch screen
assign mtl_dclk = clk27;
(* keep = 1 *) wire ssram_data_outen;
(* keep = 1 *) wire [15:0] ssram_data_out;
// instantiate the touch screen controller provided by Terasic (encrypted block)
reg touch_ready_0;
reg [9:0] touch_x1_0, touch_x2_0;
reg [8:0] touch_y1_0, touch_y2_0;
reg [1:0] touch_count_0;
reg [7:0] touch_gesture_0;
reg touch_ready_1;
reg [9:0] touch_x1_1, touch_x2_1;
reg [8:0] touch_y1_1, touch_y2_1;
reg [1:0] touch_count_1;
reg [7:0] touch_gesture_1;
wire touch_ready_2;
wire [9:0] touch_x1_2, touch_x2_2;
wire [8:0] touch_y1_2, touch_y2_2;
wire [1:0] touch_count_2;
wire [7:0] touch_gesture_2;
// i2c_touch_config touch(
// .iCLK(qsys_50_clk),
// .iRSTN(rstn),
// .iTRIG(!mtl_touch_int), // note that this signal is inverted
// .oREADY(touch_ready_2),
// .oREG_X1(touch_x1_2),
// .oREG_Y1(touch_y1_2),
// .oREG_X2(touch_x2_2),
// .oREG_Y2(touch_y2_2),
// .oREG_TOUCH_COUNT(touch_count_2),
// .oREG_GESTURE(touch_gesture_2),
// .I2C_SCLK(mtl_touch_i2cscl),
// .I2C_SDAT(mtl_touch_i2csda));
// synchronize signals to qsys system clock
always @(posedge qsys_sysclk)
begin
touch_ready_1 <= touch_ready_2;
touch_x1_1 <= touch_x1_2;
touch_y1_1 <= touch_y1_2;
touch_x2_1 <= touch_x2_2;
touch_y2_1 <= touch_y2_2;
touch_count_1 <= touch_count_2;
touch_gesture_1 <= touch_gesture_2;
touch_ready_0 <= touch_ready_1;
touch_x1_0 <= touch_x1_1;
touch_y1_0 <= touch_y1_1;
touch_x2_0 <= touch_x2_1;
touch_y2_0 <= touch_y2_1;
touch_count_0 <= touch_count_1;
touch_gesture_0 <= touch_gesture_1;
end
// touch screen controller end
wire i2c_scl_oe_n;
wire i2c_scl_o;
wire i2c_scl_i = HDMI_TX_PCSCL;
wire i2c_sda_oe_n;
wire i2c_sda_o;
wire i2c_sda_i = HDMI_TX_PCSDA;
// tristate buffers
assign HDMI_TX_PCSCL = i2c_scl_oe_n==1'b0 ? i2c_scl_o : 1'bz;
assign HDMI_TX_PCSDA = i2c_sda_oe_n==1'b0 ? i2c_sda_o : 1'bz;
//wire gen_sck;
//wire gen_i2s;
//wire gen_ws;
assign HDMI_TX_SCK = 1'b0;
assign HDMI_TX_I2S = 4'b0;//{gen_i2s, gen_i2s, gen_i2s, gen_i2s};
assign HDMI_TX_WS = 1'b0;//gen_ws;
wire [31:0] otg_dout;
assign OTG_D = (!OTG_CS_n & OTG_OE_n) ? otg_dout : 32'hzzzzzzzz;
wire [16:0] otg_a_temp;
assign OTG_A[17:1] = otg_a_temp[16:0];
DE4_SOC DE4_SOC_inst(
// 1) global signals:
.clk_50_clk(qsys_50_clk),
.clk_50_ddr_clk(OSC_50_Bank4),
.clk_125_clk(enet_refclk_125MHz),
.reset_reset_n(rstn),
.sysclk_clk(qsys_sysclk),
//.sysreset_reset_n(qsys_sysreset_n),
.leds_external_connection_export(LED_n),
// the_ddr2
.ddr2_global_reset_reset_n(),
.memory_mem_cke (M1_DDR2_cke), // ddr2.cke
.memory_mem_ck_n (M1_DDR2_clk_n), // .ck_n
.memory_mem_cas_n (M1_DDR2_cas_n), // .cas_n
.memory_mem_dq (M1_DDR2_dq), // .dq
.memory_mem_dqs (M1_DDR2_dqs), // .dqs
.memory_mem_odt (M1_DDR2_odt), // .odt
.memory_mem_cs_n (M1_DDR2_cs_n), // .cs_n
.memory_mem_ba (M1_DDR2_ba), // .ba
.memory_mem_dm (M1_DDR2_dm), // .dm
.memory_mem_we_n (M1_DDR2_we_n), // .we_n
.memory_mem_dqs_n (M1_DDR2_dqsn), // .dqs_n
.memory_mem_ras_n (M1_DDR2_ras_n), // .ras_n
.memory_mem_ck (M1_DDR2_clk), // .ck
.memory_mem_a (M1_DDR2_addr), // .a
.oct_rup (termination_blk0_rup_pad), // .oct_rup
.oct_rdn (termination_blk0_rdn_pad), // .oct_rdn
// ddr2 psd i2c
// .out_port_from_the_ddr2_i2c_scl(M1_DDR2_SCL),
// .out_port_from_the_ddr2_i2c_sa(M1_DDR2_SA),
// .bidir_port_to_and_from_the_ddr2_i2c_sda(M1_DDR2_SDA)
// ---------------------------------------------------------------------
// MAC (TSE) 0
.mac_mac_mdio_mdc (enet_mdc), // mac_mac_mdio.mdc
.mac_mac_mdio_mdio_in (enet_mdio_in), // .mdio_in
.mac_mac_mdio_mdio_out (enet_mdio_out), // .mdio_out
.mac_mac_mdio_mdio_oen (enet_mdio_oen), // .mdio_oen
//.mac_mac_misc_xon_gen, (/* input */) // mac_mac_misc.xon_gen
//.mac_mac_misc_xoff_gen, (/* input */) // .xoff_gen
//.mac_mac_misc_magic_wakeup, (/* output */) // .magic_wakeup
//.mac_mac_misc_magic_sleep_n, (/* input */) // .magic_sleep_n
//.mac_mac_misc_ff_tx_crc_fwd, (/* input */) // .ff_tx_crc_fwd
//.mac_mac_misc_ff_tx_septy, (/* output */) // .ff_tx_septy
//.mac_mac_misc_tx_ff_uflow, (/* output */) // .tx_ff_uflow
//.mac_mac_misc_ff_tx_a_full, (/* output */) // .ff_tx_a_full
//.mac_mac_misc_ff_tx_a_empty, (/* output */) // .ff_tx_a_empty
//.mac_mac_misc_rx_err_stat, (/* output[17:0] */) // .rx_err_stat
//.mac_mac_misc_rx_frm_type, (/* output[3:0] */) // .rx_frm_type
//.mac_mac_misc_ff_rx_dsav, (/* output */) // .ff_rx_dsav
//.mac_mac_misc_ff_rx_a_full, (/* output */) // .ff_rx_a_full
//.mac_mac_misc_ff_rx_a_empty, (/* output */) // .ff_rx_a_empty
//.mac_status_led_crs, (/* output */) // mac_status_led.crs
//.mac_status_led_link, (/* output */) // .link
//.mac_status_led_col, (/* output */) // .col
//.mac_status_led_an, (/* output */) // .an
//.mac_status_led_char_err, (/* output */) // .char_err
//.mac_status_led_disp_err, (/* output */) // .disp_err
//.mac_serdes_control_export, (/* output */) // mac_serdes_control.export
.mac_serial_txp (lvds_txp), // mac_serial.txp
.mac_serial_rxp (lvds_rxp), // .rxp
// ---------------------------------------------------------------------
// MAC (TSE) 1
.mac1_mac_mdio_mdc (enet1_mdc), // mac1_mac_mdio.mdc
.mac1_mac_mdio_mdio_in (enet1_mdio_in), // .mdio_in
.mac1_mac_mdio_mdio_out (enet1_mdio_out), // .mdio_out
.mac1_mac_mdio_mdio_oen (enet1_mdio_oen), // .mdio_oen
//.mac1_mac_misc_xon_gen, ( input ) // mac1_mac_misc.xon_gen
//.mac1_mac_misc_xoff_gen, ( input ) // .xoff_gen
//.mac1_mac_misc_magic_wakeup, ( output ) // .magic_wakeup
//.mac1_mac_misc_magic_sleep_n, ( input ) // .magic_sleep_n
//.mac1_mac_misc_ff_tx_crc_fwd, ( input ) // .ff_tx_crc_fwd
//.mac1_mac_misc_ff_tx_septy, ( output ) // .ff_tx_septy
//.mac1_mac_misc_tx_ff_uflow, ( output ) // .tx_ff_uflow
//.mac1_mac_misc_ff_tx_a_full, ( output ) // .ff_tx_a_full
//.mac1_mac_misc_ff_tx_a_empty, ( output ) // .ff_tx_a_empty
//.mac1_mac_misc_rx_err_stat, ( output[17:0] ) // .rx_err_stat
//.mac1_mac_misc_rx_frm_type, ( output[3:0] ) // .rx_frm_type
//.mac1_mac_misc_ff_rx_dsav, ( output ) // .ff_rx_dsav
//.mac1_mac_misc_ff_rx_a_full, ( output ) // .ff_rx_a_full
//.mac1_mac_misc_ff_rx_a_empty, ( output ) // .ff_rx_a_empty
//.mac1_status_led_crs, ( output ) // mac1_status_led.crs
//.mac1_status_led_link, ( output ) // .link
//.mac1_status_led_col, ( output ) // .col
//.mac1_status_led_an, ( output ) // .an
//.mac1_status_led_char_err, ( output ) // .char_err
//.mac1_status_led_disp_err, ( output ) // .disp_err
//.mac1_serdes_control_export, ( output ) // mac1_serdes_control.export
.mac1_serial_txp (lvds_txp1), // mac1_serial.txp
.mac1_serial_rxp (lvds_rxp1), // .rxp
// ---------------------------------------------------------------------/
`ifdef ENABLE_SDCARD
.sd_b_SD_cmd (SD_CMD), // sd.b_SD_cmd
.sd_b_SD_dat (SD_DAT[0]), // .b_SD_dat
.sd_b_SD_dat3 (SD_DAT[3]), // .b_SD_dat3
.sd_o_SD_clock (SD_CLK), // .o_SD_clock
`endif
`ifdef ENABLE_SSRAM
.mem_ssram_adv (SSRAM_ADV), // fbssram_1.ssram_adv
.mem_ssram_bwa_n (SSRAM_BWA_n), // .ssram_bwa_n
.mem_ssram_bwb_n (SSRAM_BWB_n), // .ssram_bwb_n
.mem_ssram_ce_n (SSRAM_CE_n), // .ssram_ce_n
.mem_ssram_cke_n (SSRAM_CKE_n), // .ssram_cke_n
.mem_ssram_oe_n (SSRAM_OE_n), // .ssram_oe_n
.mem_ssram_we_n (SSRAM_WE_n), // .ssram_we_n
.mem_fsm_a (FSM_A), // .fsm_a
.mem_fsm_d_out (ssram_data_out), // .fsm_d_out
.mem_fsm_d_in (FSM_D), // .fsm_d_in
.mem_fsm_dout_req (ssram_data_outen), // .fsm_dout_req
.mem_flash_adv_n (FLASH_ADV_n),
.mem_flash_ce_n (FLASH_CE_n),
.mem_flash_clk (FLASH_CLK),
.mem_flash_oe_n (FLASH_OE_n),
.mem_flash_we_n (FLASH_WE_n),
.touch_x1 (touch_x1_0), // .touch_x1
.touch_y1 (touch_y1_0), // .touch_y1
.touch_x2 (touch_x2_0), // .touch_x2
.touch_y2 (touch_y2_0), // .touch_y2
.touch_count_gesture ({touch_count_0,touch_gesture_0}), // .touch_count_gesture
.touch_touch_valid (touch_ready_0), // .touch_touch_valid
// .sram_clk_clk (SSRAM_CLK)
// .display_clk_clk (clk27),
/*.coe_hdmi_r(HDMI_TX_RD),
.coe_hdmi_g(HDMI_TX_GD),
.coe_hdmi_b(HDMI_TX_BD),
.coe_hdmi_hsd(HDMI_TX_HS),
.coe_hdmi_vsd(HDMI_TX_VS),
.coe_hdmi_de(HDMI_TX_DE),*/
.coe_tpadlcd_mtl_r(mtl_r),
.coe_tpadlcd_mtl_g(mtl_g),
.coe_tpadlcd_mtl_b(mtl_b),
.coe_tpadlcd_mtl_hsd(mtl_hsd),
.coe_tpadlcd_mtl_vsd(mtl_vsd),
.clk_27_clk (clk27),
.coe_i2c_scl_i (i2c_scl_i),
.coe_i2c_scl_o (i2c_scl_o),
.coe_i2c_scl_oe_n (i2c_scl_oe_n),
.coe_i2c_sda_i (i2c_sda_i),
.coe_i2c_sda_o (i2c_sda_o),
.coe_i2c_sda_oe_n (i2c_sda_oe_n),
.hdmi_tx_reset_n_external_connection_export (HDMI_TX_RST_N),
// .i2s_tx_conduit_end_sck (gen_sck), // i2s_tx_conduit_end.sck
// .i2s_tx_conduit_end_ws (gen_ws), // .ws
// .i2s_tx_conduit_end_sd (gen_i2s),
`endif
.usb_coe_cs_n (OTG_CS_n), // usb.coe_cs_n
.usb_coe_rd_n (OTG_OE_n), // .coe_rd_n
.usb_coe_din (OTG_D), // .coe_din
.usb_coe_dout (otg_dout), // .coe_dout
.usb_coe_a (otg_a_temp), // .coe_a
.usb_coe_dc_irq_in (OTG_DC_IRQ), // .coe_dc_irq_in
.usb_coe_hc_irq_in (OTG_HC_IRQ), // .coe_hc_irq_in
//.usb_coe_dc_dreq_in (OTG_DC_DREQ), // .coe_dc_dreq_in
//.usb_coe_hc_dreq_in (OTG_HC_DREQ), // .coe_hc_dreq_in
//.usb_coe_dc_dack (OTG_DC_DACK), // .coe_dc_dack
//.usb_coe_hc_dack (OTG_HC_DACK), // .coe_hc_dack
.usb_coe_wr_n (OTG_WE_n), // .coe_wr_n
.fan_fan_on_pwm (FAN_CTRL), //
.fan_temp_lower_seg_n (SEG0_D), // .temp_lower_seg_n
.fan_temp_upper_seg_n (SEG1_D), // .temp_upper_seg_n.
.switches_export ({SLIDE_SW[3:0], BUTTON[3:0], SW_P[7:0]}),
`ifdef ENABLE_UART
.rs232_stx_pad_o (UART_TXD), // rs232.stx_pad_o
.rs232_srx_pad_i (UART_RXD), // .srx_pad_i
.rs232_rts_pad_o (UART_RTS), // .rts_pad_o
.rs232_cts_pad_i (UART_CTS), // .cts_pad_i
.rs232_dtr_pad_o (), // .dtr_pad_o
// I have no idea what these should be by default. Should see Simon's example project.
.rs232_dsr_pad_i (1'b1), // .dsr_pad_i
.rs232_ri_pad_i (1'b1), // .ri_pad_i
.rs232_dcd_pad_i (1'b1), // .dcd_pad_i
`endif
`ifdef ENABLE_HDMI
.hdmi_vid_clock_clk (HDMI_TX_PCLK), // hdmi_vid_clock.clk
.hdmi_ref_clock_clk (OSC_50_Bank5), // hdmi_ref_clock.clk
.hdmi_r (HDMI_TX_RD), // hdmi.r
.hdmi_g (HDMI_TX_GD), // .g
.hdmi_b (HDMI_TX_BD), // .b
.hdmi_hsd (HDMI_TX_HS), // .hsd
.hdmi_vsd (HDMI_TX_VS), // .vsd
.hdmi_de (HDMI_TX_DE)
`endif
`ifdef ENABLE_PCIE
,
.pciexpressstream_0_refclk_export (PCIE_REFCLK_p),
.pciexpressstream_0_fixedclk_clk (clk125),
.pciexpressstream_0_cal_blk_clk_clk (reconfig_clk),
.pciexpressstream_0_reconfig_gxbclk_clk (reconfig_clk),
.pciexpressstream_0_reconfig_togxb_data (reconfig_togxb),
.pciexpressstream_0_reconfig_fromgxb_0_data (reconfig_fromgxb),
.pciexpressstream_0_reconfig_busy_busy_altgxb_reconfig (reconfig_busy),
.pciexpressstream_0_pcie_rstn_export (PCIE_PREST_n),
.pciexpressstream_0_rx_in_rx_datain_0 (PCIE_RX_p[0]),
.pciexpressstream_0_rx_in_rx_datain_1 (PCIE_RX_p[1]),
.pciexpressstream_0_rx_in_rx_datain_2 (PCIE_RX_p[2]),
.pciexpressstream_0_rx_in_rx_datain_3 (PCIE_RX_p[3]),
.pciexpressstream_0_tx_out_tx_dataout_0 (PCIE_TX_p[0]),
.pciexpressstream_0_tx_out_tx_dataout_1 (PCIE_TX_p[1]),
.pciexpressstream_0_tx_out_tx_dataout_2 (PCIE_TX_p[2]),
.pciexpressstream_0_tx_out_tx_dataout_3 (PCIE_TX_p[3])
`endif
);
// handle USB (OTG) reset signal
assign OTG_RESET_n = rstn100;
// handle unused flash reset signal
assign FLASH_RESET_n = rstn100;
// handle tristate ssram data bus
assign FSM_D = ssram_data_outen ? ssram_data_out : 16'bzzzzzzzzzzzzzzzz;
endmodule
|
(** printing \2/ $\cup$ #∪# *)
(** printing <2= $\subseteq$ #⊆# *)
(** printing forall $\forall$ #∀# *)
(** printing -> $\rightarrow$ #→# *)
(** printing /\ $\land$ #∧# *)
Require Import Setoid Program.
Require Import paco.
(** * Illustrating the [paco] library
This tutorial shows how to use our [paco] library to reason about
coinductive predicates in Coq. By coinductive predicates we mean
objects that one can define using [CoInductive] and whose type
ends in [Prop]. The library implements _parameterized
coinduction_, as described in our draft paper entitled #<a
href=" http://plv.mpi-sws.org/paco/"># _The Power of
Parameterization in Coinductive Proof_ #</a>#.
How does parameterized coinduction compare to Coq's existing
support for coinductive proofs?
For proofs by _induction_, Coq provides a tactic called [fix], but
proofs done directly with [fix] are required to satisfy a
_syntactic guardedness_ criterion. Fortunately, Coq also
generates induction _lemmas_ for every inductive definition, which
eliminate the need to ever use the low-level [fix] tactic and
worry about guardedness. For proofs by coinduction, Coq provides
a tactic [cofix] analogous to [fix], i.e., also based on a
syntactic guardedness criterion. However, Coq does not generate
any lemmas for coinductive definitions. Consequently, to reason
about such definitions, the user must use the low-level [cofix]
tactic. Due to its syntactic nature, [cofix] is problematic in
several ways (please see the paper linked above for detailed
discussion of these points):
- It is non-compositional.
- It is inefficient.
- It is not user-friendly.
- It interacts poorly with builtin automation tactics.
The [paco] library provides a tactic, [pcofix], which can be seen
as a replacement for Coq's builtin [cofix] tactic (in the case of
predicates) that does not involve any syntactic guardedness
criterion and thus avoids all of these problems. In addition,
like Coq's [cofix], [pcofix] provides built-in support for
_incremental_ proofs, i.e., proofs in which the coinduction
hypothesis is extended gradually as the proof progresses.
We believe this combination of compositionality, incrementality,
robustness, and ease of use makes [pcofix] a superior alternative
to [cofix] for proofs about coinductive predicates.
The rest of this tutorial illustrates the use of the [paco]
library with the help of three examples.
*)(* *)
(** ** Example: stream equality
The first example involves streams of natural numbers and an
equality thereon. We prove a particular equality via [cofix], and
then explain how that proof can be turned into one via [pcofix].
*)
(** We start by defining a type of streams of natural numbers.
*)
CoInductive stream :=
| cons : nat -> stream -> stream.
(** The following, seemingly useless, lemma is a common trick for
working with corecursive terms such as our streams. (It will be
used in the example proofs.) For details, see for instance #<a
href="http://adam.chlipala.net/cpdt/html/Coinductive.html">Adam
Chlipala's book on Certified Programming with Dependent
Types</a>#.
*)
Definition sunf s :=
match s with cons n s' => cons n s' end.
Lemma sunf_eq : forall s, s = sunf s.
Proof.
destruct s; auto.
Qed.
(** In order to state our example equality, we define an enumeration
stream and a map operation for streams.
*)
CoFixpoint enumerate n : stream :=
cons n (enumerate (S n)).
CoFixpoint map f s : stream :=
match s with cons n s' => cons (f n) (map f s') end.
(** *** A proof using [cofix]
We will now prove, using [cofix], that for any [n] the stream
[enumerate n] is equal to the stream [cons n (map S (enumerate n))].
*)
(** First, we define an equality [seq] on streams. Usually, one would
do this as follows.
[CoInductive seq : stream -> stream -> Prop :=] #<br>#
[ | seq_fold : forall n s1 s2 (R : seq s1 s2), seq (cons n s1) (cons n s2).]
Instead, we define the generating function, [seq_gen], beforehand,
and then define [seq] as its greatest fixed point using
[CoInductive]. The reason is simply that we need [seq_gen] later
when using [paco]. If applying parameterized coinduction to an
existing development where the generating function is not
explicit, it can always easily be made explicit.
Note that, albeit the use of [Inductive], the definition
of [seq_gen] is not recursive.
*)
Inductive seq_gen seq : stream -> stream -> Prop :=
| _seq_gen : forall n s1 s2 (R : seq s1 s2 : Prop), seq_gen seq (cons n s1) (cons n s2).
Hint Constructors seq_gen.
CoInductive seq : stream -> stream -> Prop :=
| seq_fold : forall s1 s2, seq_gen seq s1 s2 -> seq s1 s2.
(** Second, we do the actual proof.
*)
Theorem example : forall n, seq (enumerate n) (cons n (map S (enumerate n))).
Proof.
cofix CIH.
intros; apply seq_fold.
pattern (enumerate n) at 1; rewrite sunf_eq; simpl.
constructor.
rewrite (sunf_eq (enumerate n)); simpl.
rewrite (sunf_eq (map _ _)); simpl.
apply CIH.
Qed.
(** _Note_: One might want to eliminate the use of [pattern] in the
proof script by replacing the corresponding line with the
following:
[rewrite sunf_eq at 1; simpl.]
However, doing so will result in an invalid proof (rejected at
[Qed]-time). The reason is that the proof term created by
[rewrite] ... [at 1] involves some lemmas from the [Setoid]
library. Like most lemmas, these are opaque, so guardedness
checking cannot inspect their proofs and thus fails. This is a
great example of two of the previously mentioned problems with the
[cofix] approach, namely lack of compositionality and poor
interaction with standard tactics.
*)(* *)
(** *** A proof using our [pcofix]
We will now do the same proof, but using the [paco] library. We
first simply show the new (but equivalent) definition of stream
equality and the new proof of the example, and then explain what
is going on behind the scenes. In both, we use [paco] constructs
with suffix "2" because we are dealing with predicates of arity 2
here.
_Note_: [Paco] supports predicates of arity up to 8. Also, it
supports up to three mutually coinductive predicates (see the last
example of this tutorial). In either case, extending this is just
a matter of copy and paste.
We also have to prove monotonicity of the generating function
[seq_gen], which can be discharged by the tactic [pmonauto], and
register it in the Hint databse [paco].
_Remark_: Unlike [CoInductive], [paco] does not care whether the
generating function is given in a _strictly positive_ syntactic
form; all that matters is that the function is monotone. More
specifically, [paco2 f] is well defined for an arbitrary generating
function [f] regardless of whether it is monotone or not. However,
in order to ensure that [paco2 f bot2] is the greatest fixed point
of [f], we need monotonicity of [f].
*)
Definition seq' s1 s2 := paco2 seq_gen bot2 s1 s2.
Hint Unfold seq'.
Lemma seq_gen_mon: monotone2 seq_gen. Proof. pmonauto. Qed.
Hint Resolve seq_gen_mon : paco.
Theorem example' : forall n, seq' (enumerate n) (cons n (map S (enumerate n))).
Proof.
pcofix CIH.
intros; pfold.
rewrite sunf_eq at 1; simpl.
constructor.
rewrite (sunf_eq (enumerate n)); simpl.
rewrite (sunf_eq (map _ _)); simpl.
right; apply CIH.
Qed.
(** Observe that the proof script is essentially the same as before
(this is no accident). The main change is the use of [pcofix]
instead of [cofix], which allows us to avoid any syntactic
guardedness checking at [Qed]-time. As a minor benefit of that,
we are able to use [rewrite] ... [at 1], which we could not do
before. *)
(** **** How it works:
To understand [seq'] and the proof of [example'], we have to
explain some background. Given a monotone function [f], we call
[paco2 f] the _parameterized_ greatest fixed point of [f]. For a
relation [r], [paco2 f r] is defined as the greatest fixed point
of the function [fun x => f (x \2/ r)]. Clearly, [paco2 f bot2]
(where [bot2] is the empty relation) is just the ordinary greatest
fixed point of [f].
Let us look at our example domain to understand better. A proof
of [paco2 seq_gen r s1 s2] can be seen as a proof of [r <2= seq ->
seq s1 s2], where the use of the premise is guarded
_semantically_, rather than syntactically. More precisely, [paco2
seq_gen r] relates two streams iff their heads are equal and their
tails are either related by [r] or again related by [paco2 seq_gen
r]. Compare this to [seq], the ordinary greatest fixed point of
[seq_gen], which relates two streams iff their heads are equal and
their tails are again related by [seq]. This should also make it
clear why our definition of [seq'] is equivalent to [seq].
To fold and unfold parameterized fixed points, we provide two
tactics:
- [pfold] : when the conclusion is [paco2 f r] for some [f] and
[r], [pfold] converts it to [f (paco2 f r \2/ r)]
- [punfold H] : when the hypothesis [H] is [paco2 f r] for some
[f] and [r], [punfold H] converts it to [f (paco2 f r \2/ r)]
Other useful lemmas are:
- [paco2_mon f : monotone2 (paco2 f)]
- [paco2_mult f : forall r, paco2 f (paco2 f r) <2= paco2 f r]
- [paco2_mult_strong f : forall r, paco2 f (paco2 f r \2/ r) <2= paco2 f r]
We will see an example involving [paco2_mult] in a moment. But
first let us have another look at the proof scripts of [example]
and [example']. In the former, after calling [cofix], the proof
state is as follows:
[CIH : forall n : nat, seq (enumerate n) (cons n (map S (enumerate n)))] #<br>#
[============================] #<br>#
[forall n : nat, seq (enumerate n) (cons n (map S (enumerate n)))] #<br>#
In this state, the hypothesis precisely matches the conclusion,
and there is nothing preventing one from simply concluding the
goal directly. Of course, if one were to do that, one's "proof"
would be subsequently rejected by [Qed] for failing to obey
syntactic guardedness.
Calling [pcofix] results in a similar state, except that the added
hypothesis [CIH] now governs a fresh relation variable [r], which
represents the current coinduction hypothesis relating [enumerate n]
and [cons n (map S (enumerate n))] for all [n]. The new goal
then says that, in proving the two streams equal, we can use [r]
coinductively, but only in a semantically guarded position,
i.e. after unfolding [paco2 seq_gen r]. In particular, one
_cannot_ apply [CIH] immediately to "solve" the goal:
[r : stream -> stream -> Prop] #<br>#
[CIH : forall n : nat, r (enumerate n) (cons n (map S (enumerate n)))] #<br>#
[============================] #<br>#
[forall n : nat, paco2 seq_gen r (enumerate n) (cons n (map S (enumerate n)))] #<br>#
The remaining differences between the proof scripts of [example]
and [example'] are as follows. First, let us examine [example].
After applying [seq_fold] and unfolding [enumerate n] in the proof
of [example], we have the following goal:
[CIH : forall n : nat, seq (enumerate n) (cons n (map S (enumerate n)))] #<br>#
[n : nat] #<br>#
[============================] #<br>#
[seq_gen seq (cons n (enumerate (S n))) (cons n (map S (enumerate n)))] #<br>#
By the definition of [seq_gen] and unfolding [map S (enumerate n)],
this reduces to showing
[CIH : forall n : nat, seq (enumerate n) (cons n (map S (enumerate n)))] #<br>#
[n : nat] #<br>#
[============================] #<br>#
[seq (enumerate (S n)) (cons (S n) (map S (enumerate (S n))))] #<br>#
which follows directly by applying the coinduction hypothesis [CIH].
In the case of [example'], the proof is slightly different.
First, we use the tactic [pfold] rather than [apply seq_fold],
simply because we now reason about [seq'] rather than [seq].
After applying [pfold] and unfolding [enumerate n], we have:
[r : stream -> stream -> Prop] #<br>#
[CIH : forall n : nat, r (enumerate n) (cons n (map S (enumerate n)))] #<br>#
[n : nat] #<br>#
[============================] #<br>#
[seq_gen (paco2 seq_gen r \2/ r) (cons n (enumerate (S n))) (cons n (map S (enumerate n)))] #<br>#
As you see, the relation [r] appears in the argument of
[seq_gen]. Thus by definition of [seq_gen] and unfolding [map S
(enumerate n)], we need to show [enumerate (S n)] and [cons (S n)
(map S (enumerate (S n)))] are related by either [paco2 seq_gen r]
or [r]:
[r : stream -> stream -> Prop] #<br>#
[CIH : forall n : nat, r (enumerate n) (cons n (map S (enumerate n)))] #<br>#
[n : nat] #<br>#
[============================] #<br>#
[paco2 seq_gen r (enumerate (S n)) (cons (S n) (map S (enumerate (S n))))] #<br>#
[ \/ r (enumerate (S n)) (cons (S n) (map S (enumerate (S n))))] #<br>#
As the coinduction hypothesis gives us that they are related by [r],
we first have to select the [right] disjunct, before we apply
[CIH].
Summing up, the two proofs are very similar, but in the one using
[paco], the guardedness of the coinduction is guaranteed at every
step by the way the proof is constructed, rather than by a
syntactic check of the whole proof term after the fact.
*)(* *)
(** *** Another example
Before moving on to the second part, we briefly demonstrate the
use of the tactics [punfold] and [pclearbot].
*)(* *)
(** Here is a proof for [seq].
*)
Theorem seq_cons : forall n1 n2 s1 s2 (SEQ : seq (cons n1 s1) (cons n2 s2)),
n1 = n2 /\ seq s1 s2.
Proof.
intros.
inversion_clear SEQ; rename H into SEQ.
inversion_clear SEQ; auto.
Qed.
(** And here is the corresponding proof for [seq'].
Note that the tactic [pclearbot] simplifies all hypotheses of the form [P \/
bot{n}] to [P].
*)
Theorem seq'_cons : forall n1 n2 s1 s2 (SEQ : seq' (cons n1 s1) (cons n2 s2)),
n1 = n2 /\ seq' s1 s2.
Proof.
intros.
punfold SEQ.
inversion_clear SEQ; pclearbot; auto.
Qed.
(** We also provide two tactics [pdestruct] and [pinversion].
They are simply defined as follows:
- [pdestruct H] := [punfold H; destruct H; pclearbot]
- [pinversion H] := [punfold H; inversion H; pclearbot]
Using this the proof of the above theorem [seq'_cons] can be
simplified as [intros; pinversion SEQ; auto.]
*)(* *)
(** ** Example: infinite tree equality
The second example involves infinite binary trees of natural
numbers and an equality thereon. We prove two particular
equalities via [cofix] in an incremental fashion, and then show
how these proofs can be done just as easily via [pcofix].
We then show how, using [pcofix], the proofs can additionally
be modularly decomposed.
*)
(** As before, we first define the coinductive type and the unfolding
trick.
*)
CoInductive inftree :=
| node : nat -> inftree -> inftree -> inftree.
Definition tunf t : inftree :=
match t with node n tl tr => node n tl tr end.
Lemma tunf_eq : forall t, t = tunf t.
Proof.
destruct t; auto.
Qed.
(** In order to state our example equalities, we define the following
four trees.
*)
CoFixpoint one : inftree := node 1 one two
with two : inftree := node 2 one two.
CoFixpoint eins : inftree := node 1 eins (node 2 eins zwei)
with zwei : inftree := node 2 eins zwei.
(** *** Incremental proofs using [cofix]
As before, we define the tree equality as the greatest fixed point
of its generating function.
*)
Inductive teq_gen teq : inftree -> inftree -> Prop :=
| _teq_gen : forall n t1l t1r t2l t2r (Rl : teq t1l t2l : Prop) (Rr : teq t1r t2r),
teq_gen teq (node n t1l t1r) (node n t2l t2r).
Hint Constructors teq_gen.
CoInductive teq t1 t2 : Prop :=
| teq_fold (IN : teq_gen teq t1 t2).
(** We now prove, using [cofix], that [one] equals [eins] and,
separately, that [two] equals [zwei]. Note the nested use of
[cofix] in either proof script, which lets us strengthen the
coinductive hypothesis in the middle of the proof. For instance,
in the proof [teq_one], we start out with the coinductive
hypothesis that [one] and [eins] are equal ([CIH]). Later on, we
use [cofix] again to additionally assume that [two] and [zwei] are
equal ([CIH']). This is a prime example of _incremental_ proof:
we start with no coinductive assumptions, and we progressively add
more coinductive assumptions as the proof progresses.
*)
Theorem teq_one : teq one eins.
Proof.
cofix CIH.
apply teq_fold.
rewrite (tunf_eq one), (tunf_eq eins); simpl.
constructor; auto.
apply teq_fold.
rewrite (tunf_eq two); simpl.
constructor; auto.
cofix CIH'.
apply teq_fold.
rewrite (tunf_eq two), (tunf_eq zwei); simpl.
constructor; auto.
Qed.
Theorem teq_two : teq two zwei.
Proof.
cofix CIH.
apply teq_fold.
rewrite (tunf_eq two), (tunf_eq zwei); simpl.
constructor; auto.
cofix CIH'.
apply teq_fold.
rewrite (tunf_eq one), (tunf_eq eins); simpl.
constructor; auto.
apply teq_fold.
rewrite (tunf_eq two); simpl.
constructor; auto.
Qed.
(** *** Incremental proofs using our [pcofix]
As before, we can easily turn the above [cofix]-proofs into
[pcofix]-proofs.
*)
Definition teq' t1 t2 := paco2 teq_gen bot2 t1 t2.
Hint Unfold teq'.
Lemma teq_gen_mon: monotone2 teq_gen. Proof. pmonauto. Qed.
Hint Resolve teq_gen_mon : paco.
Theorem teq'_one : teq' one eins.
Proof.
pcofix CIH.
pfold.
rewrite (tunf_eq one), (tunf_eq eins); simpl.
constructor; auto.
left; pfold.
rewrite (tunf_eq two); simpl.
constructor; auto.
left; pcofix CIH'.
pfold.
rewrite (tunf_eq two), (tunf_eq zwei); simpl.
constructor; auto.
Qed.
Theorem teq'_two : teq' two zwei.
Proof.
pcofix CIH.
pfold.
rewrite (tunf_eq two), (tunf_eq zwei); simpl.
constructor; auto.
left; pcofix CIH'.
pfold.
rewrite (tunf_eq one), (tunf_eq eins); simpl.
constructor; auto.
left; pfold.
rewrite (tunf_eq two); simpl.
constructor; auto.
Qed.
(** *** Pseudo-compositional proofs using [cofix]
It is easy to see that the proofs of [teq_one] and [teq_two] are
essentially the same. We can avoid duplicating some work by
decomposing the proofs as follows.
First we prove that [teq two zwei] holds under the coinductive
assumption [teq one eins]. This is basically the second part of
the proof of [teq_one] (and the first part of the proof of
[teq_two]). Then we prove the converse, i.e., that [teq one
eins] holds under the coinductive assumption [teq two zwei].
This is basically the first part of the proof of [teq_one] (and
the second part of the proof of [teq_two]).
The issue is that there seems to be no way to express these two
properties. The best we can do is prove [teq two zwei -> teq one
eins] and [teq one eins -> teq two zwei], and make sure that in
these proofs any use of the assumption is syntactically guarded.
For instance, we are not allowed to prove [teq two zwei -> teq
one eins] by inspecting [teq two zwei] and extracting [teq one
eins] from that (see the proof of [teq_two_one_bad] below).
Although a valid proof of that goal by itself, it could not be
composed later to yield a proof of [teq one eins] or [teq two
zwei] (see the aborted theorem [teq_eins_bad] below).
Moreover, both lemmas must then be made transparent by using
[Defined] instead of [Qed] at the end, such that, when composing
them to prove [teq one eins] or [teq two zwei], guardedness
checking can inspect their proof terms. In other words, [cofix]
is not properly compositional.
*)
Lemma teq_two_one_bad : teq two zwei -> teq one eins.
Proof.
intros; rewrite (tunf_eq two), (tunf_eq zwei) in H.
destruct H; inversion IN; auto.
Defined.
Lemma teq_two_one : teq two zwei -> teq one eins.
Proof.
intros; cofix CIH.
apply teq_fold.
rewrite (tunf_eq one), (tunf_eq eins); simpl.
constructor; auto.
apply teq_fold.
rewrite (tunf_eq two); simpl.
constructor; auto.
Defined.
Lemma teq_one_two : teq one eins -> teq two zwei.
Proof.
intros; cofix CIH.
apply teq_fold.
rewrite (tunf_eq two), (tunf_eq zwei); simpl.
constructor; auto.
Defined.
Theorem teq_eins : teq one eins.
Proof.
cofix CIH.
apply teq_two_one, teq_one_two, CIH.
Qed.
Theorem teq_zwei : teq two zwei.
Proof.
cofix CIH.
apply teq_one_two, teq_two_one, CIH.
Qed.
(** The following proof would fail guardedness checking at [Qed]-time,
because in the proof of the lemma [teq_two_one_bad] the
assumption is used "too early".
*)
Theorem teq_eins_bad : teq one eins.
Proof.
cofix CIH.
apply teq_two_one_bad, teq_one_two, CIH.
Abort.
(** *** Compositional proofs using our [pcofix]
Using parameterized coinduction, we can state the actual desired
lemmas as follows and prove them using [pcofix] (again, only
minimal changes to the previous proof scripts are required).
Observe that (i) the earlier "wrong" proof of [teq two zwei -> teq
one eins] ([teq_two_one_bad]) is _not_ a proof of the
corresponding lemma here, and (ii) we are not forced to make the
lemmas transparent.
*)
Lemma teq'_two_one : forall r,
(r two zwei : Prop) -> paco2 teq_gen r one eins.
Proof.
intros; pcofix CIH.
pfold.
rewrite (tunf_eq one), (tunf_eq eins); simpl.
constructor; auto.
left; pfold.
rewrite (tunf_eq two); simpl.
constructor; auto.
Qed.
Lemma teq'_one_two : forall r,
(r one eins : Prop) -> paco2 teq_gen r two zwei.
Proof.
intros; pcofix CIH.
pfold.
rewrite (tunf_eq two), (tunf_eq zwei); simpl.
constructor; auto.
Qed.
(** We now compose them with the help of the lemma [paco2_mult]:
- [paco2_mult f : paco2 f (paco2 f r) <2= paco2 f r]
The tactic [pmult] applies [paco{n}_mult] to the conclusion
for an appropriate [n].
*)
Theorem teq'_eins : teq' one eins.
Proof.
pcofix CIH.
pmult; apply teq'_two_one, teq'_one_two, CIH.
Qed.
Theorem teq'_zwei : teq' two zwei.
Proof.
pcofix CIH.
pmult; apply teq'_one_two, teq'_two_one, CIH.
Qed.
(** ** Example: mutual coinduction
The third and last example shows that [paco] also works for mutual
coinduction. Here, the mutuality involves two predicates.
*)(* *)
(** We define two generating functions (using the [inftree] type from
before).
*)
Inductive eqone_gen eqone eqtwo : inftree -> Prop :=
| _eqone_gen : forall tl tr (EQL : eqone tl : Prop) (EQR : eqtwo tr : Prop),
eqone_gen eqone eqtwo (node 1 tl tr).
Inductive eqtwo_gen eqone eqtwo : inftree -> Prop :=
| _eqtwo_gen : forall tl tr (EQL : eqone tl : Prop) (EQR : eqtwo tr : Prop),
eqtwo_gen eqone eqtwo (node 2 tl tr).
Hint Constructors eqone_gen eqtwo_gen.
(** *** A proof via [cofix]
Using these, we now define two mutually coinductive predicates
[eqone] and [eqtwo]. It is easy to see intuitively that they
contain all trees that are equal to [one] and [two] from above,
respectively. We then prove that [eqone] contains [eins].
*)
CoInductive eqone (t : inftree) : Prop :=
| eqone_fold (EQ : eqone_gen eqone eqtwo t)
with eqtwo (t : inftree) : Prop :=
| eqtwo_fold (EQ : eqtwo_gen eqone eqtwo t).
Lemma eqone_eins : eqone eins.
Proof.
cofix CIH0; apply eqone_fold.
rewrite tunf_eq; simpl; constructor.
apply CIH0.
cofix CIH1; apply eqtwo_fold.
constructor.
apply CIH0.
rewrite tunf_eq; apply CIH1.
Qed.
(** *** A proof via [pcofix]
To define the [paco] versions of [eqone] and [eqtwo], we apply
the two constructors [paco1_2_0] and [paco1_2_1], respectively ("1"
because we are dealing with unary predicates). Again, the
translation of the lemma and of its proof is almost trivial.
*)
Definition eqone' t := paco1_2_0 eqone_gen eqtwo_gen bot1 bot1 t.
Definition eqtwo' t := paco1_2_1 eqone_gen eqtwo_gen bot1 bot1 t.
Hint Unfold eqone' eqtwo'.
Lemma eqone_gen_mon: monotone1_2 eqone_gen. Proof. pmonauto. Qed.
Lemma eqtwo_gen_mon: monotone1_2 eqtwo_gen. Proof. pmonauto. Qed.
Hint Resolve eqone_gen_mon eqtwo_gen_mon : paco.
Lemma eqone'_eins: eqone' eins.
Proof.
pcofix CIH0; pfold.
rewrite tunf_eq; simpl; constructor.
right; apply CIH0.
left; pcofix CIH1; pfold.
constructor.
right; apply CIH0.
right; rewrite tunf_eq; apply CIH1.
Qed.
(** _Remark_: For three mutually coinductive predicates, the
constructors are [paco{n}_3_0], [paco{n}_3_1], and [paco{n}_3_2].
*)
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
rx_ref_clk_p,
rx_ref_clk_n,
rx_sysref_p,
rx_sysref_n,
rx_sync_p,
rx_sync_n,
rx_data_p,
rx_data_n,
adc_oen,
adc_sela,
adc_selb,
adc_s0,
adc_s1,
adc_resetb,
adc_agc1,
adc_agc2,
adc_agc3,
adc_agc4,
spi_csn,
spi_clk,
spi_mosi,
spi_miso);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input rx_ref_clk_p;
input rx_ref_clk_n;
output rx_sysref_p;
output rx_sysref_n;
output rx_sync_p;
output rx_sync_n;
input [ 1:0] rx_data_p;
input [ 1:0] rx_data_n;
inout adc_oen;
inout adc_sela;
inout adc_selb;
inout adc_s0;
inout adc_s1;
inout adc_resetb;
inout adc_agc1;
inout adc_agc2;
inout adc_agc3;
inout adc_agc4;
output spi_csn;
output spi_clk;
output spi_mosi;
input spi_miso;
// internal registers
reg adc_dwr = 'd0;
reg [63:0] adc_ddata = 'd0;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
wire adc_clk;
wire adc_enable_a;
wire [31:0] adc_data_a;
wire adc_enable_b;
wire [31:0] adc_data_b;
// pack & unpack here
always @(posedge adc_clk) begin
case ({adc_enable_b, adc_enable_a})
2'b11: begin
adc_dwr <= 1'b1;
adc_ddata[63:48] <= adc_data_b[31:16];
adc_ddata[47:32] <= adc_data_a[31:16];
adc_ddata[31:16] <= adc_data_b[15: 0];
adc_ddata[15: 0] <= adc_data_a[15: 0];
end
2'b10: begin
adc_dwr <= ~adc_dwr;
adc_ddata[63:48] <= adc_data_b[31:16];
adc_ddata[47:32] <= adc_data_b[15: 0];
adc_ddata[31:16] <= adc_ddata[63:48];
adc_ddata[15: 0] <= adc_ddata[47:32];
end
2'b01: begin
adc_dwr <= ~adc_dwr;
adc_ddata[63:48] <= adc_data_a[31:16];
adc_ddata[47:32] <= adc_data_a[15: 0];
adc_ddata[31:16] <= adc_ddata[63:48];
adc_ddata[15: 0] <= adc_ddata[47:32];
end
default: begin
adc_dwr <= 1'b0;
adc_ddata[63:48] <= 16'd0;
adc_ddata[47:32] <= 16'd0;
adc_ddata[31:16] <= 16'd0;
adc_ddata[15: 0] <= 16'd0;
end
endcase
end
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
OBUFDS i_obufds_rx_sysref (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
assign spi_csn = spi0_csn[0];
assign spi_clk = spi0_clk;
assign spi_mosi = spi0_mosi;
assign spi0_miso = spi_miso;
ad_iobuf #(.DATA_WIDTH(10)) i_iobuf (
.dio_t (gpio_t[41:32]),
.dio_i (gpio_o[41:32]),
.dio_o (gpio_i[41:32]),
.dio_p ({ adc_oen,
adc_sela,
adc_selb,
adc_s0,
adc_s1,
adc_resetb,
adc_agc1,
adc_agc2,
adc_agc3,
adc_agc4}));
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.adc_clk (adc_clk),
.adc_data_a (adc_data_a),
.adc_data_b (adc_data_b),
.adc_ddata (adc_ddata),
.adc_dsync (1'b1),
.adc_dwr (adc_dwr),
.adc_enable_a (adc_enable_a),
.adc_enable_b (adc_enable_b),
.adc_valid_a (),
.adc_valid_b (),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.11.2013 10:48:44
// Design Name:
// Module Name: tcp_ip_wrapper
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tcp_ip_wrapper (
input aclk,
input aresetn,
input[47:0] myMacAddress,
input[31:0] inputIpAddress,
input dhcpEnable,
output[31:0] ipAddressout,
output[15:0] regSessionCount,
output[15:0] relSessionCount,
// Debug signals for the session lookup //
output upd_req_TVALID_out,
output upd_req_TREADY_out,
output upd_req_TDATA_out,
output upd_rsp_TVALID_out,
output upd_rsp_TREADY_out,
// network interface streams
output AXI_M_Stream_TVALID,
input AXI_M_Stream_TREADY,
output[63:0] AXI_M_Stream_TDATA,
output[7:0] AXI_M_Stream_TKEEP,
output AXI_M_Stream_TLAST,
input AXI_S_Stream_TVALID,
output AXI_S_Stream_TREADY,
input[63:0] AXI_S_Stream_TDATA,
input[7:0] AXI_S_Stream_TKEEP,
input AXI_S_Stream_TLAST,
// Debug streams
output[7:0] axi_debug1_tkeep,
output[63:0] axi_debug1_tdata,
output axi_debug1_tvalid,
output axi_debug1_tready,
output axi_debug1_tlast,
output[7:0] axi_debug2_tkeep,
output[63:0] axi_debug2_tdata,
output axi_debug2_tvalid,
output axi_debug2_tready,
output axi_debug2_tlast,
// memory rx cmd streams
output m_axis_rxread_cmd_TVALID,
input m_axis_rxread_cmd_TREADY,
output[71:0] m_axis_rxread_cmd_TDATA,
output m_axis_rxwrite_cmd_TVALID,
input m_axis_rxwrite_cmd_TREADY,
output[71:0] m_axis_rxwrite_cmd_TDATA,
// memory rx sts streams
//input s_axis_rxread_sts_TVALID,
//output s_axis_rxread_sts_TREADY,
//input[7:0] s_axis_rxread_sts_TDATA,
input s_axis_rxwrite_sts_TVALID,
output s_axis_rxwrite_sts_TREADY,
input[7:0] s_axis_rxwrite_sts_TDATA,
// memory rx data streams - Read status signals are not used
input s_axis_rxread_data_TVALID,
output s_axis_rxread_data_TREADY,
input[63:0] s_axis_rxread_data_TDATA,
input[7:0] s_axis_rxread_data_TKEEP,
input s_axis_rxread_data_TLAST,
output m_axis_rxwrite_data_TVALID,
input m_axis_rxwrite_data_TREADY,
output[63:0] m_axis_rxwrite_data_TDATA,
output[7:0] m_axis_rxwrite_data_TKEEP,
output m_axis_rxwrite_data_TLAST,
// memory tx cmd streams
output m_axis_txread_cmd_TVALID,
input m_axis_txread_cmd_TREADY,
output[71:0] m_axis_txread_cmd_TDATA,
output m_axis_txwrite_cmd_TVALID,
input m_axis_txwrite_cmd_TREADY,
output[71:0] m_axis_txwrite_cmd_TDATA,
// memory tx sts streams - Read status signals are not used
//input s_axis_txread_sts_TVALID,
//output s_axis_txread_sts_TREADY,
//input[7:0] s_axis_txread_sts_TDATA,
input s_axis_txwrite_sts_TVALID,
output s_axis_txwrite_sts_TREADY,
input[7:0] s_axis_txwrite_sts_TDATA,
// memory tx data streams
input s_axis_txread_data_TVALID,
output s_axis_txread_data_TREADY,
input[63:0] s_axis_txread_data_TDATA,
input[7:0] s_axis_txread_data_TKEEP,
input s_axis_txread_data_TLAST,
output m_axis_txwrite_data_TVALID,
input m_axis_txwrite_data_TREADY,
output[63:0] m_axis_txwrite_data_TDATA,
output[7:0] m_axis_txwrite_data_TKEEP,
output m_axis_txwrite_data_TLAST,
//application interface streams
output m_axis_listen_port_status_TVALID,
input m_axis_listen_port_status_TREADY,
output[7:0] m_axis_listen_port_status_TDATA,
output m_axis_notifications_TVALID,
input m_axis_notifications_TREADY,
output[87:0] m_axis_notifications_TDATA,
output m_axis_open_status_TVALID,
input m_axis_open_status_TREADY,
output[23:0] m_axis_open_status_TDATA,
output m_axis_rx_data_TVALID,
input m_axis_rx_data_TREADY,
output[63:0] m_axis_rx_data_TDATA,
output[7:0] m_axis_rx_data_TKEEP,
output m_axis_rx_data_TLAST,
output m_axis_rx_metadata_TVALID,
input m_axis_rx_metadata_TREADY,
output[15:0] m_axis_rx_metadata_TDATA,
output m_axis_tx_status_TVALID,
input m_axis_tx_status_TREADY,
output[23:0] m_axis_tx_status_TDATA,
input s_axis_listen_port_TVALID,
output s_axis_listen_port_TREADY,
input[15:0] s_axis_listen_port_TDATA,
//input s_axis_close_port_TVALID,
//output s_axis_close_port_TREADY,
//input[15:0] s_axis_close_port_TDATA,
input s_axis_close_connection_TVALID,
output s_axis_close_connection_TREADY,
input[15:0] s_axis_close_connection_TDATA,
input s_axis_open_connection_TVALID,
output s_axis_open_connection_TREADY,
input[47:0] s_axis_open_connection_TDATA,
input s_axis_read_package_TVALID,
output s_axis_read_package_TREADY,
input[31:0] s_axis_read_package_TDATA,
input s_axis_tx_data_TVALID,
output s_axis_tx_data_TREADY,
input[63:0] s_axis_tx_data_TDATA,
input[7:0] s_axis_tx_data_TKEEP,
input s_axis_tx_data_TLAST,
input s_axis_tx_metadata_TVALID,
output s_axis_tx_metadata_TREADY,
input[15:0] s_axis_tx_metadata_TDATA, //change to 15?
// Session Counter Output //
output[15:0] regSessionCount_V,
output regSessionCount_V_ap_vld,
// UDP App Mux to UDP Loopback signals //
output lbPortOpenReplyIn_TVALID, // output wire portOpenReplyIn_TVALID
input lbPortOpenReplyIn_TREADY, // input wire portOpenReplyIn_TREADY
output[7:0] lbPortOpenReplyIn_TDATA, // output wire [7 : 0] portOpenReplyIn_TDATA
input lbRequestPortOpenOut_TVALID, // input wire requestPortOpenOut_TVALID
output lbRequestPortOpenOut_TREADY, // output wire requestPortOpenOut_TREADY
input[15:0] lbRequestPortOpenOut_TDATA, // input wire [15 : 0] requestPortOpenOut_TDATA
output lbRxDataIn_TVALID, // output wire rxDataIn_TVALID
input lbRxDataIn_TREADY, // input wire rxDataIn_TREADY
output[63:0] lbRxDataIn_TDATA, // output wire [63 : 0] rxDataIn_TDATA
output[7:0] lbRxDataIn_TKEEP, // output wire [7 : 0] rxDataIn_TKEEP
output lbRxDataIn_TLAST, // output wire [0 : 0] rxDataIn_TLAST
output lbRxMetadataIn_TVALID, // output wire rxMetadataIn_TVALID
input lbRxMetadataIn_TREADY, // input wire rxMetadataIn_TREADY
output[95:0] lbRxMetadataIn_TDATA, // output wire [95 : 0] rxMetadataIn_TDATA
input lbTxDataOut_TVALID, // input wire txDataOut_TVALID
output lbTxDataOut_TREADY, // output wire txDataOut_TREADY
input[63:0] lbTxDataOut_TDATA, // input wire [63 : 0] txDataOut_TDATA
input[7:0] lbTxDataOut_TKEEP, // input wire [7 : 0] txDataOut_TKEEP
input lbTxDataOut_TLAST, // input wire [0 : 0] txDataOut_TLAST
input lbTxLengthOut_TVALID, // input wire txLengthOut_TVALID
output lbTxLengthOut_TREADY, // output wire txLengthOut_TREADY
input[15:0] lbTxLengthOut_TDATA, // input wire [15 : 0] txLengthOut_TDATA
input lbTxMetadataOut_TVALID, // input wire txMetadataOut_TVALID
output lbTxMetadataOut_TREADY, // output wire txMetadataOut_TREADY
input[95:0] lbTxMetadataOut_TDATA, // input wire [95 : 0] txMetadataOut_TDATA
// Debug signals //
output[99:0] metadataFifo_din, // [99:0]
output metadataFifo_full,
output metadataFifo_write,
output[15:0] metadataHandlerFifo_din, // [15:0]
output metadataHandlerFifo_full,
output metadataHandlerFifo_write
////////////////////
);
// IP Handler Outputs
wire axi_iph_to_arp_slice_tvalid;
wire axi_iph_to_arp_slice_tready;
wire[63:0] axi_iph_to_arp_slice_tdata;
wire[7:0] axi_iph_to_arp_slice_tkeep;
wire axi_iph_to_arp_slice_tlast;
wire axi_iph_to_icmp_slice_tvalid;
wire axi_iph_to_icmp_slice_tready;
wire[63:0] axi_iph_to_icmp_slice_tdata;
wire[7:0] axi_iph_to_icmp_slice_tkeep;
wire axi_iph_to_icmp_slice_tlast;
//Slice connections on RX path
wire axi_arp_slice_to_arp_tvalid;
wire axi_arp_slice_to_arp_tready;
wire[63:0] axi_arp_slice_to_arp_tdata;
wire[7:0] axi_arp_slice_to_arp_tkeep;
wire axi_arp_slice_to_arp_tlast;
wire axi_icmp_slice_to_icmp_tvalid;
wire axi_icmp_slice_to_icmp_tready;
wire[63:0] axi_icmp_slice_to_icmp_tdata;
wire[7:0] axi_icmp_slice_to_icmp_tkeep;
wire axi_icmp_slice_to_icmp_tlast;
wire axi_iph_to_toe_tvalid;
wire axi_iph_to_toe_tready;
wire[63:0] axi_iph_to_toe_tdata;
wire[7:0] axi_iph_to_toe_tkeep;
wire axi_iph_to_toe_tlast;
// MAC-IP Encode Inputs
wire axi_intercon_to_mie_tvalid;
wire axi_intercon_to_mie_tready;
wire[63:0] axi_intercon_to_mie_tdata;
wire[7:0] axi_intercon_to_mie_tkeep;
wire axi_intercon_to_mie_tlast;
wire axi_mie_to_intercon_tvalid;
wire axi_mie_to_intercon_tready;
wire[63:0] axi_mie_to_intercon_tdata;
wire[7:0] axi_mie_to_intercon_tkeep;
wire axi_mie_to_intercon_tlast;
//Slice connections on RX path
wire axi_arp_to_arp_slice_tvalid;
wire axi_arp_to_arp_slice_tready;
wire[63:0] axi_arp_to_arp_slice_tdata;
wire[7:0] axi_arp_to_arp_slice_tkeep;
wire axi_arp_to_arp_slice_tlast;
wire axi_icmp_to_icmp_slice_tvalid;
wire axi_icmp_to_icmp_slice_tready;
wire[63:0] axi_icmp_to_icmp_slice_tdata;
wire[7:0] axi_icmp_to_icmp_slice_tkeep;
wire axi_icmp_to_icmp_slice_tlast;
wire axi_udp_to_merge_tvalid;
wire axi_udp_to_merge_tready;
wire[63:0] axi_udp_to_merge_tdata;
wire[7:0] axi_udp_to_merge_tkeep;
wire axi_udp_to_merge_tlast;
wire axi_iph_to_udp_tvalid;
wire axi_iph_to_udp_tready;
wire[63:0] axi_iph_to_udp_tdata;
wire[7:0] axi_iph_to_udp_tkeep;
wire axi_iph_to_udp_tlast;
wire axis_udp_to_icmp_tready;
wire axis_udp_to_icmp_tvalid;
wire[63:0] axis_udp_to_icmp_tdata;
wire[7:0] axis_udp_to_icmp_tkeep;
wire axis_udp_to_icmp_tlast;
wire axis_ttl_to_icmp_tready;
wire axis_ttl_to_icmp_tvalid;
wire[63:0] axis_ttl_to_icmp_tdata;
wire[7:0] axis_ttl_to_icmp_tkeep;
wire axis_ttl_to_icmp_tlast;
/// TOE Outputs ///
wire axi_toe_to_toe_slice_tvalid; // output AXI_M_Stream_TVALID
wire axi_toe_to_toe_slice_tready; // input AXI_M_Stream_TREADY
wire[63:0] axi_toe_to_toe_slice_tdata; // output [63 : 0] AXI_M_Stream_TDATA
wire[7:0] axi_toe_to_toe_slice_tkeep; // output [7 : 0] AXI_M_Stream_TSTRB
wire axi_toe_to_toe_slice_tlast; // output [0 : 0] AXI_M_Stream_TLAST
/// UDP-to-App Mux Signals ///
wire udp2muxRxDataIn_TVALID;
wire udp2muxRxDataIn_TREADY;
wire[63:0] udp2muxRxDataIn_TDATA;
wire udp2muxRxDataIn_TLAST;
wire[7:0] udp2muxRxDataIn_TKEEP;
wire mux2dhcpRxDataIn_TVALID;
wire mux2dhcpRxDataIn_TREADY;
wire[63:0] mux2dhcpRxDataIn_TDATA;
wire mux2dhcpRxDataIn_TLAST;
wire[7:0] mux2dhcpRxDataIn_TKEEP;
/// Rx Side Metadata
wire udp2muxRxMetadataIn_V_TVALID;
wire udp2muxRxMetadataIn_V_TREADY;
wire[95:0] udp2muxRxMetadataIn_V_TDATA;
wire mux2dhcpRxMetadataIn_V_TVALID;
wire mux2dhcpRxMetadataIn_V_TREADY;
wire[95:0] mux2dhcpRxMetadataIn_V_TDATA;
/// Signals for opening ports ///
wire mux2udp_requestPortOpenOut_V_TVALID;
wire mux2udp_requestPortOpenOut_V_TREADY;
wire[15:0] mux2udp_requestPortOpenOut_V_TDATA; // OK
wire udp2mux_portOpenReplyIn_V_V_TVALID;
wire udp2mux_portOpenReplyIn_V_V_TREADY;
wire[7:0] udp2mux_portOpenReplyIn_V_V_TDATA; // OK
wire dhcp2mux_requestPortOpenOut_V_TVALID;
wire dhcp2mux_requestPortOpenOut_V_TREADY;
wire[15:0] dhcp2mux_requestPortOpenOut_V_TDATA;
wire mux2dhcp_portOpenReplyIn_V_V_TVALID;
wire mux2dhcp_portOpenReplyIn_V_V_TREADY;
wire[7:0] mux2dhcp_portOpenReplyIn_V_V_TDATA;
wire mcd_to_shim_TVALID;
wire mcd_to_shim_TREADY;
wire[63:0] mcd_to_shim_TDATA;
wire[7:0] mcd_to_shim_TKEEP;
wire mcd_to_shim_TLAST;
wire[111:0] mcd_to_shim_TUSER;
/// Signals for connecting the data i/o's to the mux
wire dhcp2mux_TVALID;
wire dhcp2mux_TREADY;
wire[63:0] dhcp2mux_TDATA;
wire[7:0] dhcp2mux_TKEEP;
wire dhcp2mux_TLAST;
wire mux2udp_TVALID;
wire mux2udp_TREADY;
wire[63:0] mux2udp_TDATA;
wire[7:0] mux2udp_TKEEP;
wire mux2udp_TLAST;
//// Tx Side Metadata
wire mux2udpTxMetadataOut_V_TVALID;
wire mux2udpTxMetadataOut_V_TREADY;
wire[95:0] mux2udpTxMetadataOut_V_TDATA;
wire dhcp2muxTxMetadataOut_V_TVALID;
wire dhcp2muxTxMetadataOut_V_TREADY;
wire[95:0] dhcp2muxTxMetadataOut_V_TDATA;
/// Tx Side Packet Length
wire mux2udpTxLengthOut_V_V_TVALID;
wire mux2udpTxLengthOut_V_V_TREADY;
wire[15:0] mux2udpTxLengthOut_V_V_TDATA;
wire dhcp2muxTxLengthOut_V_V_TVALID;
wire dhcp2muxTxLengthOut_V_V_TREADY;
wire[15:0] dhcp2muxTxLengthOut_V_V_TDATA;
// TCP Offload SmartCAM signals //
wire upd_req_TVALID;
wire upd_req_TREADY;
wire[111:0] upd_req_TDATA; //(1 + 1 + 14 + 96) - 1 = 111
wire upd_rsp_TVALID;
wire upd_rsp_TREADY;
wire[15:0] upd_rsp_TDATA;
wire ins_req_TVALID;
wire ins_req_TREADY;
wire[111:0] ins_req_TDATA;
wire del_req_TVALID;
wire del_req_TREADY;
wire[111:0] del_req_TDATA;
wire lup_req_TVALID;
wire lup_req_TREADY;
wire[97:0] lup_req_TDATA; //should be 96, also wrong in SmartCam
wire lup_rsp_TVALID;
wire lup_rsp_TREADY;
wire[15:0] lup_rsp_TDATA;
// DHCP Client IP address output //
wire[31:0] dhcpAddressOut;
// because read status is not used
assign axis_rxread_sts_TREADY = 1'b1;
assign axis_txread_sts_TREADY = 1'b1;
toe_ip toe_inst (
// Data output
.m_axis_tcp_data_TVALID(axi_toe_to_toe_slice_tvalid), // output AXI_M_Stream_TVALID
.m_axis_tcp_data_TREADY(axi_toe_to_toe_slice_tready), // input AXI_M_Stream_TREADY
.m_axis_tcp_data_TDATA(axi_toe_to_toe_slice_tdata), // output [63 : 0] AXI_M_Stream_TDATA
.m_axis_tcp_data_TKEEP(axi_toe_to_toe_slice_tkeep), // output [7 : 0] AXI_M_Stream_TSTRB
.m_axis_tcp_data_TLAST(axi_toe_to_toe_slice_tlast), // output [0 : 0] AXI_M_Stream_TLAST
// Data input
.s_axis_tcp_data_TVALID(axi_iph_to_toe_tvalid), // input AXI_S_Stream_TVALID
.s_axis_tcp_data_TREADY(axi_iph_to_toe_tready), // output AXI_S_Stream_TREADY
.s_axis_tcp_data_TDATA(axi_iph_to_toe_tdata), // input [63 : 0] AXI_S_Stream_TDATA
.s_axis_tcp_data_TKEEP(axi_iph_to_toe_tkeep), // input [7 : 0] AXI_S_Stream_TKEEP
.s_axis_tcp_data_TLAST(axi_iph_to_toe_tlast), // input [0 : 0] AXI_S_Stream_TLAST
// rx read commands
.m_axis_rxread_cmd_TVALID(m_axis_rxread_cmd_TVALID),
.m_axis_rxread_cmd_TREADY(m_axis_rxread_cmd_TREADY),
.m_axis_rxread_cmd_TDATA(m_axis_rxread_cmd_TDATA),
// rx write commands
.m_axis_rxwrite_cmd_TVALID(m_axis_rxwrite_cmd_TVALID),
.m_axis_rxwrite_cmd_TREADY(m_axis_rxwrite_cmd_TREADY),
.m_axis_rxwrite_cmd_TDATA(m_axis_rxwrite_cmd_TDATA),
// rx write status
.s_axis_rxwrite_sts_TVALID(s_axis_rxwrite_sts_TVALID),
.s_axis_rxwrite_sts_TREADY(s_axis_rxwrite_sts_TREADY),
.s_axis_rxwrite_sts_TDATA(s_axis_rxwrite_sts_TDATA),
// rx buffer read path
.s_axis_rxread_data_TVALID(s_axis_rxread_data_TVALID),
.s_axis_rxread_data_TREADY(s_axis_rxread_data_TREADY),
.s_axis_rxread_data_TDATA(s_axis_rxread_data_TDATA),
.s_axis_rxread_data_TKEEP(s_axis_rxread_data_TKEEP),
.s_axis_rxread_data_TLAST(s_axis_rxread_data_TLAST),
// rx buffer write path
.m_axis_rxwrite_data_TVALID(m_axis_rxwrite_data_TVALID),
.m_axis_rxwrite_data_TREADY(m_axis_rxwrite_data_TREADY),
.m_axis_rxwrite_data_TDATA(m_axis_rxwrite_data_TDATA),
.m_axis_rxwrite_data_TKEEP(m_axis_rxwrite_data_TKEEP),
.m_axis_rxwrite_data_TLAST(m_axis_rxwrite_data_TLAST),
// tx read commands
.m_axis_txread_cmd_TVALID(m_axis_txread_cmd_TVALID),
.m_axis_txread_cmd_TREADY(m_axis_txread_cmd_TREADY),
.m_axis_txread_cmd_TDATA(m_axis_txread_cmd_TDATA),
//tx write commands
.m_axis_txwrite_cmd_TVALID(m_axis_txwrite_cmd_TVALID),
.m_axis_txwrite_cmd_TREADY(m_axis_txwrite_cmd_TREADY),
.m_axis_txwrite_cmd_TDATA(m_axis_txwrite_cmd_TDATA),
// tx write status
.s_axis_txwrite_sts_TVALID(s_axis_txwrite_sts_TVALID),
.s_axis_txwrite_sts_TREADY(s_axis_txwrite_sts_TREADY),
.s_axis_txwrite_sts_TDATA(s_axis_txwrite_sts_TDATA),
// tx read path
.s_axis_txread_data_TVALID(s_axis_txread_data_TVALID),
.s_axis_txread_data_TREADY(s_axis_txread_data_TREADY),
.s_axis_txread_data_TDATA(s_axis_txread_data_TDATA),
.s_axis_txread_data_TKEEP(s_axis_txread_data_TKEEP),
.s_axis_txread_data_TLAST(s_axis_txread_data_TLAST),
// tx write path
.m_axis_txwrite_data_TVALID(m_axis_txwrite_data_TVALID),
.m_axis_txwrite_data_TREADY(m_axis_txwrite_data_TREADY),
.m_axis_txwrite_data_TDATA(m_axis_txwrite_data_TDATA),
.m_axis_txwrite_data_TKEEP(m_axis_txwrite_data_TKEEP),
.m_axis_txwrite_data_TLAST(m_axis_txwrite_data_TLAST),
/// SmartCAM I/F ///
.m_axis_session_upd_req_TVALID(upd_req_TVALID),
.m_axis_session_upd_req_TREADY(upd_req_TREADY),
.m_axis_session_upd_req_TDATA(upd_req_TDATA),
//.m_axis_session_del_req_TVALID(del_req_TVALID), // output m_axis_session_del_req_TVALID
//.m_axis_session_del_req_TREADY(del_req_TREADY), // input m_axis_session_del_req_TREADY
//.m_axis_session_del_req_TDATA(del_req_TDATA), // output [111 : 0] m_axis_session_del_req_TDATA
//.m_axis_session_ins_req_TVALID(ins_req_TVALID), // output m_axis_session_ins_req_TVALID
//.m_axis_session_ins_req_TREADY(ins_req_TREADY), // input m_axis_session_ins_req_TREADY
//.m_axis_session_ins_req_TDATA(ins_req_TDATA), // output [111 : 0] m_axis_session_ins_req_TDATA
.s_axis_session_upd_rsp_TVALID(upd_rsp_TVALID),
.s_axis_session_upd_rsp_TREADY(upd_rsp_TREADY),
.s_axis_session_upd_rsp_TDATA(upd_rsp_TDATA),
.m_axis_session_lup_req_TVALID(lup_req_TVALID),
.m_axis_session_lup_req_TREADY(lup_req_TREADY),
.m_axis_session_lup_req_TDATA(lup_req_TDATA),
.s_axis_session_lup_rsp_TVALID(lup_rsp_TVALID),
.s_axis_session_lup_rsp_TREADY(lup_rsp_TREADY),
.s_axis_session_lup_rsp_TDATA(lup_rsp_TDATA),
/* Application Interface */
// listen&close port
.s_axis_listen_port_req_TVALID(s_axis_listen_port_TVALID),
.s_axis_listen_port_req_TREADY(s_axis_listen_port_TREADY),
.s_axis_listen_port_req_TDATA(s_axis_listen_port_TDATA),
.m_axis_listen_port_rsp_TVALID(m_axis_listen_port_status_TVALID),
.m_axis_listen_port_rsp_TREADY(m_axis_listen_port_status_TREADY),
.m_axis_listen_port_rsp_TDATA(m_axis_listen_port_status_TDATA),
//.s_axis_close_port_TVALID(s_axis_close_port_TVALID),
//.s_axis_close_port_TREADY(s_axis_close_port_TREADY),
//.s_axis_close_port_TDATA(s_axis_close_port_TDATA),
// notification & read request
.m_axis_notification_TVALID(m_axis_notifications_TVALID),
.m_axis_notification_TREADY(m_axis_notifications_TREADY),
.m_axis_notification_TDATA(m_axis_notifications_TDATA),
.s_axis_rx_data_req_TVALID(s_axis_read_package_TVALID),
.s_axis_rx_data_req_TREADY(s_axis_read_package_TREADY),
.s_axis_rx_data_req_TDATA(s_axis_read_package_TDATA),
// open&close connection
.s_axis_open_conn_req_TVALID(s_axis_open_connection_TVALID),
.s_axis_open_conn_req_TREADY(s_axis_open_connection_TREADY),
.s_axis_open_conn_req_TDATA(s_axis_open_connection_TDATA),
.m_axis_open_conn_rsp_TVALID(m_axis_open_status_TVALID),
.m_axis_open_conn_rsp_TREADY(m_axis_open_status_TREADY),
.m_axis_open_conn_rsp_TDATA(m_axis_open_status_TDATA),
.s_axis_close_conn_req_TVALID(s_axis_close_connection_TVALID),//axis_close_connection_TVALID
.s_axis_close_conn_req_TREADY(s_axis_close_connection_TREADY),
.s_axis_close_conn_req_TDATA(s_axis_close_connection_TDATA),
// rx data
.m_axis_rx_data_rsp_metadata_TVALID(m_axis_rx_metadata_TVALID),
.m_axis_rx_data_rsp_metadata_TREADY(m_axis_rx_metadata_TREADY),
.m_axis_rx_data_rsp_metadata_TDATA(m_axis_rx_metadata_TDATA),
.m_axis_rx_data_rsp_TVALID(m_axis_rx_data_TVALID),
.m_axis_rx_data_rsp_TREADY(m_axis_rx_data_TREADY),
.m_axis_rx_data_rsp_TDATA(m_axis_rx_data_TDATA),
.m_axis_rx_data_rsp_TKEEP(m_axis_rx_data_TKEEP),
.m_axis_rx_data_rsp_TLAST(m_axis_rx_data_TLAST),
// tx data
.s_axis_tx_data_req_metadata_TVALID(s_axis_tx_metadata_TVALID),
.s_axis_tx_data_req_metadata_TREADY(s_axis_tx_metadata_TREADY),
.s_axis_tx_data_req_metadata_TDATA(s_axis_tx_metadata_TDATA),
.s_axis_tx_data_req_TVALID(s_axis_tx_data_TVALID),
.s_axis_tx_data_req_TREADY(s_axis_tx_data_TREADY),
.s_axis_tx_data_req_TDATA(s_axis_tx_data_TDATA),
.s_axis_tx_data_req_TKEEP(s_axis_tx_data_TKEEP),
.s_axis_tx_data_req_TLAST(s_axis_tx_data_TLAST),
.m_axis_tx_data_rsp_TVALID(m_axis_tx_status_TVALID),
.m_axis_tx_data_rsp_TREADY(m_axis_tx_status_TREADY),
.m_axis_tx_data_rsp_TDATA(m_axis_tx_status_TDATA),
// Debug signals //
//.rxEng2eventEng_data(rxEng2eventEng_data),
//.rxEng2eventEng_write(rxEng2eventEng_write),
//.rxEng2eventEng_full(rxEng2eventEng_full),
//.eventEng2txEng_data(eventEng2txEng_data),
//.eventEng2txEng_write(eventEng2txEng_write),
//.eventEng2txEng_full(eventEng2txEng_full),
//.metadataFifo_din(metadataFifo_din),
//.metadataFifo_full(metadataFifo_full),
//.metadataFifo_write(metadataFifo_write),
//.metadataHandlerFifo_din(metadataHandlerFifo_din),
//.metadataHandlerFifo_full(metadataHandlerFifo_full),
//.metadataHandlerFifo_write(metadataHandlerFifo_write),
////////////////////
.regIpAddress_V(32'h01010101), // input wire [31 : 0] regIpAddress_V
.relSessionCount_V(relSessionCount), // output wire [15 : 0] relSessionCount_V
.regSessionCount_V(regSessionCount), // output wire [15 : 0] regSessionCount_V
.aclk(aclk), // input aclk
.aresetn(aresetn) // input aresetn
);
SmartCamCtl SmartCamCtl_inst
(
.clk(aclk),
.rst(~aresetn),
.led0(sc_led0),
.led1(sc_led1),
.cam_ready(cam_ready),
.lup_req_valid(lup_req_TVALID),
.lup_req_ready(lup_req_TREADY),
.lup_req_din(lup_req_TDATA),
.lup_rsp_valid(lup_rsp_TVALID),
.lup_rsp_ready(lup_rsp_TREADY),
.lup_rsp_dout(lup_rsp_TDATA),
.upd_req_valid(upd_req_TVALID),
.upd_req_ready(upd_req_TREADY),
.upd_req_din(upd_req_TDATA),
.upd_rsp_valid(upd_rsp_TVALID),
.upd_rsp_ready(upd_rsp_TREADY),
.upd_rsp_dout(upd_rsp_TDATA),
.debug()
);
// UDP Offload Engine
udp_0 myUDP (
.inputPathInData_TVALID(axi_iph_to_udp_tvalid), // input wire inputPathInData_TVALID
.inputPathInData_TREADY(axi_iph_to_udp_tready), // output wire inputPathInData_TREADY
.inputPathInData_TDATA(axi_iph_to_udp_tdata), // input wire [63 : 0] inputPathInData_TDATA
.inputPathInData_TKEEP(axi_iph_to_udp_tkeep), // input wire [7 : 0] inputPathInData_TKEEP
.inputPathInData_TLAST(axi_iph_to_udp_tlast), // input wire [0 : 0] inputPathInData_TLAST
.inputpathOutData_TVALID(udp2muxRxDataIn_TVALID), // output wire inputpathOutData_V_TVALID
.inputpathOutData_TREADY(udp2muxRxDataIn_TREADY), // input wire inputpathOutData_V_TREADY
.inputpathOutData_TDATA(udp2muxRxDataIn_TDATA), // output wire [63 : 0] inputpathOutData_V_TDATA
.inputpathOutData_TKEEP(udp2muxRxDataIn_TKEEP), // output wire [7:0]
.inputpathOutData_TLAST(udp2muxRxDataIn_TLAST), // output wire
.openPort_TVALID(mux2udp_requestPortOpenOut_V_TVALID), // input wire openPort_V_TVALID
.openPort_TREADY(mux2udp_requestPortOpenOut_V_TREADY), // output wire openPort_V_TREADY
.openPort_TDATA(mux2udp_requestPortOpenOut_V_TDATA), // input wire [7 : 0] openPort_V_TDATA
.confirmPortStatus_TVALID(udp2mux_portOpenReplyIn_V_V_TVALID), // output wire confirmPortStatus_V_V_TVALID
.confirmPortStatus_TREADY(udp2mux_portOpenReplyIn_V_V_TREADY), // input wire confirmPortStatus_V_V_TREADY
.confirmPortStatus_TDATA(udp2mux_portOpenReplyIn_V_V_TDATA), // output wire [15 : 0] confirmPortStatus_V_V_TDATA
.inputPathOutputMetadata_TVALID(udp2muxRxMetadataIn_V_TVALID), // output wire inputPathOutputMetadata_V_TVALID
.inputPathOutputMetadata_TREADY(udp2muxRxMetadataIn_V_TREADY), // input wire inputPathOutputMetadata_V_TREADY
.inputPathOutputMetadata_TDATA(udp2muxRxMetadataIn_V_TDATA), // output wire [95 : 0] inputPathOutputMetadata_V_TDATA
.portRelease_TVALID(1'b0), // input wire portRelease_V_V_TVALID
.portRelease_TREADY(), // output wire portRelease_V_V_TREADY
.portRelease_TDATA(15'b0), // input wire [15 : 0] portRelease_V_V_TDATA
.outputPathInData_TVALID(mux2udp_TVALID), // input wire outputPathInData_V_TVALID
.outputPathInData_TREADY(mux2udp_TREADY), // output wire outputPathInData_V_TREADY
.outputPathInData_TDATA(mux2udp_TDATA), // input wire [71 : 0] outputPathInData_V_TDATA
.outputPathInData_TKEEP(mux2udp_TKEEP), // input wire [7 : 0] outputPathInData_TKEEP
.outputPathInData_TLAST(mux2udp_TLAST), // input wire [0 : 0] outputPathInData_TLAST
.outputPathOutData_TVALID(axi_udp_to_merge_tvalid), // output wire outputPathOutData_TVALID
.outputPathOutData_TREADY(axi_udp_to_merge_tready), // input wire outputPathOutData_TREADY
.outputPathOutData_TDATA(axi_udp_to_merge_tdata), // output wire [63 : 0] outputPathOutData_TDATA
.outputPathOutData_TKEEP(axi_udp_to_merge_tkeep), // output wire [7 : 0] outputPathOutData_TKEEP
.outputPathOutData_TLAST(axi_udp_to_merge_tlast), // output wire [0 : 0] outputPathOutData_TLAST
.outputPathInMetadata_TVALID(mux2udpTxMetadataOut_V_TVALID), // input wire outputPathInMetadata_V_TVALID
.outputPathInMetadata_TREADY(mux2udpTxMetadataOut_V_TREADY), // output wire outputPathInMetadata_V_TREADY
.outputPathInMetadata_TDATA(mux2udpTxMetadataOut_V_TDATA), // input wire [95 : 0] outputPathInMetadata_V_TDATA
.outputpathInLength_TVALID(mux2udpTxLengthOut_V_V_TVALID), // input wire outputpathInLength_V_V_TVALID
.outputpathInLength_TREADY(mux2udpTxLengthOut_V_V_TREADY), // output wire outputpathInLength_V_V_TREADY
.outputpathInLength_TDATA(mux2udpTxLengthOut_V_V_TDATA), // input wire [15 : 0] outputpathInLength_V_V_TDATA
.inputPathPortUnreachable_TVALID(axis_udp_to_icmp_tvalid), // output wire inputPathPortUnreachable_TVALID
.inputPathPortUnreachable_TREADY(axis_udp_to_icmp_tready), // input wire inputPathPortUnreachable_TREADY
.inputPathPortUnreachable_TDATA(axis_udp_to_icmp_tdata), // output wire [63 : 0] inputPathPortUnreachable_TDATA
.inputPathPortUnreachable_TKEEP(axis_udp_to_icmp_tkeep), // output wire [7 : 0] inputPathPortUnreachable_TKEEP
.inputPathPortUnreachable_TLAST(axis_udp_to_icmp_tlast), // output wire [0 : 0] inputPathPortUnreachable_TLAST
//.ap_start(1'b1), // input wire ap_start
//.ap_ready(), // output wire ap_ready
//.ap_done(), // output wire ap_done
//.ap_idle(), // output wire ap_idle
.aclk(aclk), // input wire ap_clk
.aresetn(aresetn) // input wire ap_rst_n
);
ip_handler_ip ip_handler_inst (
.dataIn_TVALID(AXI_S_Stream_TVALID), // input wire dataIn_TVALID
.dataIn_TREADY(AXI_S_Stream_TREADY), // output wire dataIn_TREADY
.dataIn_TDATA(AXI_S_Stream_TDATA), // input wire [63 : 0] dataIn_TDATA
.dataIn_TKEEP(AXI_S_Stream_TKEEP), // input wire [7 : 0] dataIn_TKEEP
.dataIn_TLAST(AXI_S_Stream_TLAST), // input wire [0 : 0] dataIn_TLAST
.ARPdataOut_TVALID(axi_iph_to_arp_slice_tvalid), // output wire ARPdataOut_TVALID
.ARPdataOut_TREADY(axi_iph_to_arp_slice_tready), // input wire ARPdataOut_TREADY
.ARPdataOut_TDATA(axi_iph_to_arp_slice_tdata), // output wire [63 : 0] ARPdataOut_TDATA
.ARPdataOut_TKEEP(axi_iph_to_arp_slice_tkeep), // output wire [7 : 0] ARPdataOut_TKEEP
.ARPdataOut_TLAST(axi_iph_to_arp_slice_tlast), // output wire [0 : 0] ARPdataOut_TLAST
.ICMPdataOut_TVALID(axi_iph_to_icmp_slice_tvalid), // output wire ICMPdataOut_TVALID
.ICMPdataOut_TREADY(axi_iph_to_icmp_slice_tready), // input wire ICMPdataOut_TREADY
.ICMPdataOut_TDATA(axi_iph_to_icmp_slice_tdata), // output wire [63 : 0] ICMPdataOut_TDATA
.ICMPdataOut_TKEEP(axi_iph_to_icmp_slice_tkeep), // output wire [7 : 0] ICMPdataOut_TKEEP
.ICMPdataOut_TLAST(axi_iph_to_icmp_slice_tlast), // output wire [0 : 0] ICMPdataOut_TLAST
.ICMPexpDataOut_TVALID(axis_ttl_to_icmp_tvalid), // output wire ICMPexpDataOut_TVALID
.ICMPexpDataOut_TREADY(axis_ttl_to_icmp_tready), // input wire ICMPexpDataOut_TREADY
.ICMPexpDataOut_TDATA(axis_ttl_to_icmp_tdata), // output wire [63 : 0] ICMPexpDataOut_TDATA
.ICMPexpDataOut_TKEEP(axis_ttl_to_icmp_tkeep), // output wire [7 : 0] ICMPexpDataOut_TKEEP
.ICMPexpDataOut_TLAST(axis_ttl_to_icmp_tlast), // output wire [0 : 0] ICMPexpDataOut_TLAST
.UDPdataOut_TVALID(axi_iph_to_udp_tvalid), // output wire UDPdataOut_TVALID
.UDPdataOut_TREADY(axi_iph_to_udp_tready), // input wire UDPdataOut_TREADY
.UDPdataOut_TDATA(axi_iph_to_udp_tdata), // output wire [63 : 0] UDPdataOut_TDATA
.UDPdataOut_TKEEP(axi_iph_to_udp_tkeep), // output wire [7 : 0] UDPdataOut_TKEEP
.UDPdataOut_TLAST(axi_iph_to_udp_tlast), // output wire [0 : 0] UDPdataOut_TLAST
.TCPdataOut_TVALID(axi_iph_to_toe_tvalid), // output wire TCPdataOut_TVALID
.TCPdataOut_TREADY(axi_iph_to_toe_tready), // input wire TCPdataOut_TREADY
.TCPdataOut_TDATA(axi_iph_to_toe_tdata), // output wire [63 : 0] TCPdataOut_TDATA
.TCPdataOut_TKEEP(axi_iph_to_toe_tkeep), // output wire [7 : 0] TCPdataOut_TKEEP
.TCPdataOut_TLAST(axi_iph_to_toe_tlast), // output wire [0 : 0] TCPdataOut_TLAST
.regIpAddress_V(32'h01010101), // input wire [31 : 0] regIpAddress_V
.myMacAddress_V(myMacAddress), // input wire [47 : 0] myMacAddress_V
.ap_clk(aclk), // input wire ap_clk
.ap_rst_n(aresetn) // input wire ap_rst_n
);
// ARP lookup
wire axis_arp_lookup_request_TVALID;
wire axis_arp_lookup_request_TREADY;
wire[31:0] axis_arp_lookup_request_TDATA;
wire axis_arp_lookup_reply_TVALID;
wire axis_arp_lookup_reply_TREADY;
wire[55:0] axis_arp_lookup_reply_TDATA;
mac_ip_encode_ip mac_ip_encode_inst (
.dataIn_TVALID(axi_intercon_to_mie_tvalid), // input wire dataIn_TVALID
.dataIn_TREADY(axi_intercon_to_mie_tready), // output wire dataIn_TREADY
.dataIn_TDATA(axi_intercon_to_mie_tdata), // input wire [63 : 0] dataIn_TDATA
.dataIn_TKEEP(axi_intercon_to_mie_tkeep), // input wire [7 : 0] dataIn_TKEEP
.dataIn_TLAST(axi_intercon_to_mie_tlast), // input wire [0 : 0] dataIn_TLAST
.arpTableIn_V_TVALID(axis_arp_lookup_reply_TVALID), // input wire arpTableIn_V_TVALID
.arpTableIn_V_TREADY(axis_arp_lookup_reply_TREADY), // output wire arpTableIn_V_TREADY
.arpTableIn_V_TDATA(axis_arp_lookup_reply_TDATA), // input wire [55 : 0] arpTableIn_V_TDATA
.dataOut_TVALID(axi_mie_to_intercon_tvalid), // output wire dataOut_TVALID
.dataOut_TREADY(axi_mie_to_intercon_tready), // input wire dataOut_TREADY
.dataOut_TDATA(axi_mie_to_intercon_tdata), // output wire [63 : 0] dataOut_TDATA
.dataOut_TKEEP(axi_mie_to_intercon_tkeep), // output wire [7 : 0] dataOut_TKEEP
.dataOut_TLAST(axi_mie_to_intercon_tlast), // output wire [0 : 0] dataOut_TLAST
.arpTableOut_V_V_TVALID(axis_arp_lookup_request_TVALID), // output wire arpTableOut_V_V_TVALID
.arpTableOut_V_V_TREADY(axis_arp_lookup_request_TREADY), // input wire arpTableOut_V_V_TREADY
.arpTableOut_V_V_TDATA(axis_arp_lookup_request_TDATA), // output wire [31 : 0] arpTableOut_V_V_TDATA
.regSubNetMask_V(32'h00FFFFFF), // input wire [31 : 0] regSubNetMask_V
.regDefaultGateway_V(32'h01010101), // input wire [31 : 0] regDefaultGateway_V
.myMacAddress_V(myMacAddress), // input wire [47 : 0] myMacAddress_V
.ap_clk(aclk), // input wire ap_clk
.ap_rst_n(aresetn) // input wire ap_rst_n
);
// merges icmp and tcp
axis_interconnect_3to1 ip_merger (
.ACLK(aclk), // input wire ACLK
.ARESETN(aresetn), // input wire ARESETN
.S00_AXIS_ACLK(aclk), // input wire S00_AXIS_ACLK
.S01_AXIS_ACLK(aclk), // input wire S01_AXIS_ACLK
.S02_AXIS_ACLK(aclk), // input wire S02_AXIS_ACLK
.S00_AXIS_ARESETN(aresetn), // input wire S00_AXIS_ARESETN
.S01_AXIS_ARESETN(aresetn), // input wire S01_AXIS_ARESETN
.S02_AXIS_ARESETN(aresetn), // input wire S02_AXIS_ARESETN
.S00_AXIS_TVALID(axi_icmp_to_icmp_slice_tvalid), // input wire S00_AXIS_TVALID
.S01_AXIS_TVALID(axi_udp_to_merge_tvalid), // input wire S01_AXIS_TVALID
.S02_AXIS_TVALID(axi_toe_to_toe_slice_tvalid), // input wire S02_AXIS_TVALID
.S00_AXIS_TREADY(axi_icmp_to_icmp_slice_tready), // output wire S00_AXIS_TREADY
.S01_AXIS_TREADY(axi_udp_to_merge_tready), // output wire S01_AXIS_TREADY
.S02_AXIS_TREADY(axi_toe_to_toe_slice_tready), // output wire S02_AXIS_TREADY
.S00_AXIS_TDATA(axi_icmp_to_icmp_slice_tdata), // input wire [63 : 0] S00_AXIS_TDATA
.S01_AXIS_TDATA(axi_udp_to_merge_tdata), // input wire [63 : 0] S01_AXIS_TDATA
.S02_AXIS_TDATA(axi_toe_to_toe_slice_tdata), // input wire [63 : 0] S02_AXIS_TDATA
.S00_AXIS_TKEEP(axi_icmp_to_icmp_slice_tkeep), // input wire [7 : 0] S00_AXIS_TKEEP
.S01_AXIS_TKEEP(axi_udp_to_merge_tkeep), // input wire [7 : 0] S01_AXIS_TKEEP
.S02_AXIS_TKEEP(axi_toe_to_toe_slice_tkeep), // input wire [7 : 0] S02_AXIS_TKEEP
.S00_AXIS_TLAST(axi_icmp_to_icmp_slice_tlast), // input wire S00_AXIS_TLAST
.S01_AXIS_TLAST(axi_udp_to_merge_tlast), // input wire S01_AXIS_TLAST
.S02_AXIS_TLAST(axi_toe_to_toe_slice_tlast), // input wire S02_AXIS_TLAST
.M00_AXIS_ACLK(aclk), // input wire M00_AXIS_ACLK
.M00_AXIS_ARESETN(aresetn), // input wire M00_AXIS_ARESETN
.M00_AXIS_TVALID(axi_intercon_to_mie_tvalid), // output wire M00_AXIS_TVALID
.M00_AXIS_TREADY(axi_intercon_to_mie_tready), // input wire M00_AXIS_TREADY
.M00_AXIS_TDATA(axi_intercon_to_mie_tdata), // output wire [63 : 0] M00_AXIS_TDATA
.M00_AXIS_TKEEP(axi_intercon_to_mie_tkeep), // output wire [7 : 0] M00_AXIS_TKEEP
.M00_AXIS_TLAST(axi_intercon_to_mie_tlast), // output wire M00_AXIS_TLAST
.S00_ARB_REQ_SUPPRESS(1'b0), // input wire S00_ARB_REQ_SUPPRESS
.S01_ARB_REQ_SUPPRESS(1'b0), // input wire S01_ARB_REQ_SUPPRESS
.S02_ARB_REQ_SUPPRESS(1'b0) // input wire S02_ARB_REQ_SUPPRESS
);
// merges ip and arp
axis_interconnect_2to1 mac_merger (
.ACLK(aclk), // input ACLK
.ARESETN(aresetn), // input ARESETN
.S00_AXIS_ACLK(aclk), // input S00_AXIS_ACLK
.S01_AXIS_ACLK(aclk), // input S01_AXIS_ACLK
.S00_AXIS_ARESETN(aresetn), // input S00_AXIS_ARESETN
.S01_AXIS_ARESETN(aresetn), // input S01_AXIS_ARESETN
.S00_AXIS_TVALID(axi_arp_to_arp_slice_tvalid), // input S00_AXIS_TVALID
.S01_AXIS_TVALID(axi_mie_to_intercon_tvalid), // input S01_AXIS_TVALID
.S00_AXIS_TREADY(axi_arp_to_arp_slice_tready), // output S00_AXIS_TREADY
.S01_AXIS_TREADY(axi_mie_to_intercon_tready), // output S01_AXIS_TREADY
.S00_AXIS_TDATA(axi_arp_to_arp_slice_tdata), // input [63 : 0] S00_AXIS_TDATA
.S01_AXIS_TDATA(axi_mie_to_intercon_tdata), // input [63 : 0] S01_AXIS_TDATA
.S00_AXIS_TKEEP(axi_arp_to_arp_slice_tkeep), // input [7 : 0] S00_AXIS_TKEEP
.S01_AXIS_TKEEP(axi_mie_to_intercon_tkeep), // input [7 : 0] S01_AXIS_TKEEP
.S00_AXIS_TLAST(axi_arp_to_arp_slice_tlast), // input S00_AXIS_TLAST
.S01_AXIS_TLAST(axi_mie_to_intercon_tlast), // input S01_AXIS_TLAST
.M00_AXIS_ACLK(aclk), // input M00_AXIS_ACLK
.M00_AXIS_ARESETN(aresetn), // input M00_AXIS_ARESETN
.M00_AXIS_TVALID(AXI_M_Stream_TVALID), // output M00_AXIS_TVALID
.M00_AXIS_TREADY(AXI_M_Stream_TREADY), // input M00_AXIS_TREADY
.M00_AXIS_TDATA(AXI_M_Stream_TDATA), // output [63 : 0] M00_AXIS_TDATA
.M00_AXIS_TKEEP(AXI_M_Stream_TKEEP), // output [7 : 0] M00_AXIS_TKEEP
.M00_AXIS_TLAST(AXI_M_Stream_TLAST), // output M00_AXIS_TLAST
.S00_ARB_REQ_SUPPRESS(1'b0), // input S00_ARB_REQ_SUPPRESS
.S01_ARB_REQ_SUPPRESS(1'b0) // input S01_ARB_REQ_SUPPRESS
);
arpServerWrapper arpServerInst (
.axi_arp_to_arp_slice_tvalid(axi_arp_to_arp_slice_tvalid),
.axi_arp_to_arp_slice_tready(axi_arp_to_arp_slice_tready),
.axi_arp_to_arp_slice_tdata(axi_arp_to_arp_slice_tdata),
.axi_arp_to_arp_slice_tkeep(axi_arp_to_arp_slice_tkeep),
.axi_arp_to_arp_slice_tlast(axi_arp_to_arp_slice_tlast),
.axis_arp_lookup_reply_TVALID(axis_arp_lookup_reply_TVALID),
.axis_arp_lookup_reply_TREADY(axis_arp_lookup_reply_TREADY),
.axis_arp_lookup_reply_TDATA(axis_arp_lookup_reply_TDATA),
.axi_arp_slice_to_arp_tvalid(axi_arp_slice_to_arp_tvalid),
.axi_arp_slice_to_arp_tready(axi_arp_slice_to_arp_tready),
.axi_arp_slice_to_arp_tdata(axi_arp_slice_to_arp_tdata),
.axi_arp_slice_to_arp_tkeep(axi_arp_slice_to_arp_tkeep),
.axi_arp_slice_to_arp_tlast(axi_arp_slice_to_arp_tlast),
.axis_arp_lookup_request_TVALID(axis_arp_lookup_request_TVALID),
.axis_arp_lookup_request_TREADY(axis_arp_lookup_request_TREADY),
.axis_arp_lookup_request_TDATA(axis_arp_lookup_request_TDATA),
.myMacAddress(myMacAddress),
.myIpAddress(32'h01010101),
.aclk(aclk), // input aclk
.aresetn(aresetn)); // input aresetn
assign axi_debug1_tkeep = axi_toe_to_toe_slice_tkeep;
assign axi_debug1_tdata = axi_toe_to_toe_slice_tdata;
assign axi_debug1_tvalid = axi_toe_to_toe_slice_tvalid;
assign axi_debug1_tready = axi_toe_to_toe_slice_tready;
assign axi_debug1_tlast = axi_toe_to_toe_slice_tlast;
assign axi_debug2_tkeep = axi_iph_to_toe_tkeep;
assign axi_debug2_tdata = axi_iph_to_toe_tdata;
assign axi_debug2_tvalid = axi_iph_to_toe_tvalid;
assign axi_debug2_tready = axi_iph_to_toe_tready;
assign axi_debug2_tlast = axi_iph_to_toe_tlast;
icmp_server_ip icmp_server_inst (
.dataIn_TVALID(axi_icmp_slice_to_icmp_tvalid), // input wire dataIn_TVALID
.dataIn_TREADY(axi_icmp_slice_to_icmp_tready), // output wire dataIn_TREADY
.dataIn_TDATA(axi_icmp_slice_to_icmp_tdata), // input wire [63 : 0] dataIn_TDATA
.dataIn_TKEEP(axi_icmp_slice_to_icmp_tkeep), // input wire [7 : 0] dataIn_TKEEP
.dataIn_TLAST(axi_icmp_slice_to_icmp_tlast), // input wire [0 : 0] dataIn_TLAST
.udpIn_TVALID(axis_udp_to_icmp_tvalid), // input wire udpIn_TVALID
.udpIn_TREADY(axis_udp_to_icmp_tready), // output wire udpIn_TREADY
.udpIn_TDATA(axis_udp_to_icmp_tdata), // input wire [63 : 0] udpIn_TDATA
.udpIn_TKEEP(axis_udp_to_icmp_tkeep), // input wire [7 : 0] udpIn_TKEEP
.udpIn_TLAST(axis_udp_to_icmp_tlast), // input wire [0 : 0] udpIn_TLAST
.ttlIn_TVALID(axis_ttl_to_icmp_tvalid), // input wire ttlIn_TVALID
.ttlIn_TREADY(axis_ttl_to_icmp_tready), // output wire ttlIn_TREADY
.ttlIn_TDATA(axis_ttl_to_icmp_tdata), // input wire [63 : 0] ttlIn_TDATA
.ttlIn_TKEEP(axis_ttl_to_icmp_tkeep), // input wire [7 : 0] ttlIn_TKEEP
.ttlIn_TLAST(axis_ttl_to_icmp_tlast), // input wire [0 : 0] ttlIn_TLAST
.dataOut_TVALID(axi_icmp_to_icmp_slice_tvalid), // output wire dataOut_TVALID
.dataOut_TREADY(axi_icmp_to_icmp_slice_tready), // input wire dataOut_TREADY
.dataOut_TDATA(axi_icmp_to_icmp_slice_tdata), // output wire [63 : 0] dataOut_TDATA
.dataOut_TKEEP(axi_icmp_to_icmp_slice_tkeep), // output wire [7 : 0] dataOut_TKEEP
.dataOut_TLAST(axi_icmp_to_icmp_slice_tlast), // output wire [0 : 0] dataOut_TLAST
.ap_clk(aclk), // input wire ap_clk
.ap_rst_n(aresetn) // input wire ap_rst_n
);
/*
* Slices
*/
// ARP Input Slice
axis_register_slice_64 axis_register_arp_in_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_iph_to_arp_slice_tvalid),
.s_axis_tready(axi_iph_to_arp_slice_tready),
.s_axis_tdata(axi_iph_to_arp_slice_tdata),
.s_axis_tkeep(axi_iph_to_arp_slice_tkeep),
.s_axis_tlast(axi_iph_to_arp_slice_tlast),
.m_axis_tvalid(axi_arp_slice_to_arp_tvalid),
.m_axis_tready(axi_arp_slice_to_arp_tready),
.m_axis_tdata(axi_arp_slice_to_arp_tdata),
.m_axis_tkeep(axi_arp_slice_to_arp_tkeep),
.m_axis_tlast(axi_arp_slice_to_arp_tlast)
);
// ICMP Input Slice
axis_register_slice_64 axis_register_icmp_in_slice(
.aclk(aclk),
.aresetn(aresetn),
.s_axis_tvalid(axi_iph_to_icmp_slice_tvalid),
.s_axis_tready(axi_iph_to_icmp_slice_tready),
.s_axis_tdata(axi_iph_to_icmp_slice_tdata),
.s_axis_tkeep(axi_iph_to_icmp_slice_tkeep),
.s_axis_tlast(axi_iph_to_icmp_slice_tlast),
.m_axis_tvalid(axi_icmp_slice_to_icmp_tvalid),
.m_axis_tready(axi_icmp_slice_to_icmp_tready),
.m_axis_tdata(axi_icmp_slice_to_icmp_tdata),
.m_axis_tkeep(axi_icmp_slice_to_icmp_tkeep),
.m_axis_tlast(axi_icmp_slice_to_icmp_tlast)
);
udpAppMux_0 myAppMux (
.portOpenReplyIn_TVALID(udp2mux_portOpenReplyIn_V_V_TVALID), // input wire portOpenReplyIn_TVALID
.portOpenReplyIn_TREADY(udp2mux_portOpenReplyIn_V_V_TREADY), // output wire portOpenReplyIn_TREADY
.portOpenReplyIn_TDATA(udp2mux_portOpenReplyIn_V_V_TDATA), // input wire [7 : 0] portOpenReplyIn_TDATA
.requestPortOpenOut_TVALID(mux2udp_requestPortOpenOut_V_TVALID), // output wire requestPortOpenOut_TVALID
.requestPortOpenOut_TREADY(mux2udp_requestPortOpenOut_V_TREADY), // input wire requestPortOpenOut_TREADY
.requestPortOpenOut_TDATA(mux2udp_requestPortOpenOut_V_TDATA), // output wire [15 : 0] requestPortOpenOut_TDATA
.portOpenReplyOutApp_TVALID(lbPortOpenReplyIn_TVALID), // output wire portOpenReplyOutApp_TVALID
.portOpenReplyOutApp_TREADY(lbPortOpenReplyIn_TREADY), // input wire portOpenReplyOutApp_TREADY
.portOpenReplyOutApp_TDATA(lbPortOpenReplyIn_TDATA), // output wire [7 : 0] portOpenReplyOutApp_TDATA
.requestPortOpenInApp_TVALID(lbRequestPortOpenOut_TVALID), // input wire requestPortOpenInApp_TVALID
.requestPortOpenInApp_TREADY(lbRequestPortOpenOut_TREADY), // output wire requestPortOpenInApp_TREADY
.requestPortOpenInApp_TDATA(lbRequestPortOpenOut_TDATA), // input wire [15 : 0] requestPortOpenInApp_TDATA
.portOpenReplyOutDhcp_TVALID(mux2dhcp_portOpenReplyIn_V_V_TVALID), // output wire portOpenReplyOutDhcp_TVALID
.portOpenReplyOutDhcp_TREADY(mux2dhcp_portOpenReplyIn_V_V_TREADY), // input wire portOpenReplyOutDhcp_TREADY
.portOpenReplyOutDhcp_TDATA(mux2dhcp_portOpenReplyIn_V_V_TDATA), // output wire [7 : 0] portOpenReplyOutDhcp_TDATA
.requestPortOpenInDhcp_TVALID(dhcp2mux_requestPortOpenOut_V_TVALID), // input wire requestPortOpenInDhcp_TVALID
.requestPortOpenInDhcp_TREADY(dhcp2mux_requestPortOpenOut_V_TREADY), // output wire requestPortOpenInDhcp_TREADY
.requestPortOpenInDhcp_TDATA(dhcp2mux_requestPortOpenOut_V_TDATA), // input wire [15 : 0] requestPortOpenInDhcp_TDATA
.rxDataIn_TVALID(udp2muxRxDataIn_TVALID), // input wire rxDataIn_TVALID
.rxDataIn_TREADY(udp2muxRxDataIn_TREADY), // output wire rxDataIn_TREADY
.rxDataIn_TDATA(udp2muxRxDataIn_TDATA), // input wire [63 : 0] rxDataIn_TDATA
.rxDataIn_TKEEP(udp2muxRxDataIn_TKEEP), // input wire [7 : 0] rxDataIn_TKEEP
.rxDataIn_TLAST(udp2muxRxDataIn_TLAST), // input wire [0 : 0] rxDataIn_TLAST
.rxDataOutApp_TVALID(lbRxDataIn_TVALID), // output wire rxDataOutApp_TVALID
.rxDataOutApp_TREADY(lbRxDataIn_TREADY), // input wire rxDataOutApp_TREADY
.rxDataOutApp_TDATA(lbRxDataIn_TDATA), // output wire [63 : 0] rxDataOutApp_TDATA
.rxDataOutApp_TKEEP(lbRxDataIn_TKEEP), // output wire [7 : 0] rxDataOutApp_TKEEP
.rxDataOutApp_TLAST(lbRxDataIn_TLAST), // output wire [0 : 0] rxDataOutApp_TLAST
.rxDataOutDhcp_TVALID(mux2dhcpRxDataIn_TVALID), // output wire rxDataOutDhcp_TVALID
.rxDataOutDhcp_TREADY(mux2dhcpRxDataIn_TREADY), // input wire rxDataOutDhcp_TREADY
.rxDataOutDhcp_TDATA(mux2dhcpRxDataIn_TDATA), // output wire [63 : 0] rxDataOutDhcp_TDATA
.rxDataOutDhcp_TKEEP(mux2dhcpRxDataIn_TKEEP), // output wire [7 : 0] rxDataOutDhcp_TKEEP
.rxDataOutDhcp_TLAST(mux2dhcpRxDataIn_TLAST), // output wire [0 : 0] rxDataOutDhcp_TLAST
.rxMetadataIn_TVALID(udp2muxRxMetadataIn_V_TVALID), // input wire rxMetadataIn_TVALID
.rxMetadataIn_TREADY(udp2muxRxMetadataIn_V_TREADY), // output wire rxMetadataIn_TREADY
.rxMetadataIn_TDATA(udp2muxRxMetadataIn_V_TDATA), // input wire [95 : 0] rxMetadataIn_TDATA
.rxMetadataOutApp_TVALID(lbRxMetadataIn_TVALID), // output wire rxMetadataOutApp_TVALID
.rxMetadataOutApp_TREADY(lbRxMetadataIn_TREADY), // input wire rxMetadataOutApp_TREADY
.rxMetadataOutApp_TDATA(lbRxMetadataIn_TDATA), // output wire [95 : 0] rxMetadataOutApp_TDATA
.rxMetadataOutDhcp_TVALID(mux2dhcpRxMetadataIn_V_TVALID), // output wire rxMetadataOutDhcp_TVALID
.rxMetadataOutDhcp_TREADY(mux2dhcpRxMetadataIn_V_TREADY), // input wire rxMetadataOutDhcp_TREADY
.rxMetadataOutDhcp_TDATA(mux2dhcpRxMetadataIn_V_TDATA), // output wire [95 : 0] rxMetadataOutDhcp_TDATA
.txDataInApp_TVALID(lbTxDataOut_TVALID), // input wire txDataInApp_TVALID
.txDataInApp_TREADY(lbTxDataOut_TREADY), // output wire txDataInApp_TREADY
.txDataInApp_TDATA(lbTxDataOut_TDATA), // input wire [63 : 0] txDataInApp_TDATA
.txDataInApp_TKEEP(lbTxDataOut_TKEEP), // input wire [7 : 0] txDataInApp_TKEEP
.txDataInApp_TLAST(lbTxDataOut_TLAST), // input wire [0 : 0] txDataInApp_TLAST
.txDataInDhcp_TVALID(dhcp2mux_TVALID), // input wire txDataInDhcp_TVALID
.txDataInDhcp_TREADY(dhcp2mux_TREADY), // output wire txDataInDhcp_TREADY
.txDataInDhcp_TDATA(dhcp2mux_TDATA), // input wire [63 : 0] txDataInDhcp_TDATA
.txDataInDhcp_TKEEP(dhcp2mux_TKEEP), // input wire [7 : 0] txDataInDhcp_TKEEP
.txDataInDhcp_TLAST(dhcp2mux_TLAST), // input wire [0 : 0] txDataInDhcp_TLAST
.txDataOut_TVALID(mux2udp_TVALID), // output wire txDataOut_TVALID
.txDataOut_TREADY(mux2udp_TREADY), // input wire txDataOut_TREADY
.txDataOut_TDATA(mux2udp_TDATA), // output wire [63 : 0] txDataOut_TDATA
.txDataOut_TKEEP(mux2udp_TKEEP), // output wire [7 : 0] txDataOut_TKEEP
.txDataOut_TLAST(mux2udp_TLAST), // output wire [0 : 0] txDataOut_TLAST
.txLengthInApp_TVALID(lbTxLengthOut_TVALID), // input wire txLengthInApp_TVALID
.txLengthInApp_TREADY(lbTxLengthOut_TREADY), // output wire txLengthInApp_TREADY
.txLengthInApp_TDATA(lbTxLengthOut_TDATA), // input wire [15 : 0] txLengthInApp_TDATA
.txLengthInDhcp_TVALID(dhcp2muxTxLengthOut_V_V_TVALID), // input wire txLengthInDhcp_TVALID
.txLengthInDhcp_TREADY(dhcp2muxTxLengthOut_V_V_TREADY), // output wire txLengthInDhcp_TREADY
.txLengthInDhcp_TDATA(dhcp2muxTxLengthOut_V_V_TDATA), // input wire [15 : 0] txLengthInDhcp_TDATA
.txLengthOut_TVALID(mux2udpTxLengthOut_V_V_TVALID), // output wire txLengthOut_TVALID
.txLengthOut_TREADY(mux2udpTxLengthOut_V_V_TREADY), // input wire txLengthOut_TREADY
.txLengthOut_TDATA(mux2udpTxLengthOut_V_V_TDATA), // output wire [15 : 0] txLengthOut_TDATA
.txMetadataInApp_TVALID(lbTxMetadataOut_TVALID), // input wire txMetadataInApp_TVALID
.txMetadataInApp_TREADY(lbTxMetadataOut_TREADY), // output wire txMetadataInApp_TREADY
.txMetadataInApp_TDATA(lbTxMetadataOut_TDATA), // input wire [95 : 0] txMetadataInApp_TDATA
.txMetadataInDhcp_TVALID(dhcp2muxTxMetadataOut_V_TVALID), // input wire txMetadataInDhcp_TVALID
.txMetadataInDhcp_TREADY(dhcp2muxTxMetadataOut_V_TREADY), // output wire txMetadataInDhcp_TREADY
.txMetadataInDhcp_TDATA(dhcp2muxTxMetadataOut_V_TDATA), // input wire [95 : 0] txMetadataInDhcp_TDATA
.txMetadataOut_TVALID(mux2udpTxMetadataOut_V_TVALID), // output wire txMetadataOut_TVALID
.txMetadataOut_TREADY(mux2udpTxMetadataOut_V_TREADY), // input wire txMetadataOut_TREADY
.txMetadataOut_TDATA(mux2udpTxMetadataOut_V_TDATA), // output wire [95 : 0] txMetadataOut_TDATA
.aclk(aclk), // input wire aclk
.aresetn(aresetn) // input wire aresetn
);
dhcp_client_0 myDhcpClient (
.dhcpEnable_V(dhcpEnable), // input wire [0 : 0] dhcpEnable_V
.inputIpAddress_V(inputIpAddress), // input wire [31 : 0] inputIpAddress_V
.dhcpIpAddressOut_V(dhcpAddressOut), // output wire [31 : 0] dhcpIpAddressOut_V
.myMacAddress_V(myMacAddress), // input wire [47 : 0] myMacAddress_V
.m_axis_open_port_TVALID(dhcp2mux_requestPortOpenOut_V_TVALID), // output wire m_axis_open_port_TVALID
.m_axis_open_port_TREADY(dhcp2mux_requestPortOpenOut_V_TREADY), // input wire m_axis_open_port_TREADY
.m_axis_open_port_TDATA(dhcp2mux_requestPortOpenOut_V_TDATA), // output wire [15 : 0] m_axis_open_port_TDATA
.m_axis_tx_data_TVALID(dhcp2mux_TVALID), // output wire m_axis_tx_data_TVALID
.m_axis_tx_data_TREADY(dhcp2mux_TREADY), // input wire m_axis_tx_data_TREADY
.m_axis_tx_data_TDATA(dhcp2mux_TDATA), // output wire [63 : 0] m_axis_tx_data_TDATA
.m_axis_tx_data_TKEEP(dhcp2mux_TKEEP), // output wire [7 : 0] m_axis_tx_data_TKEEP
.m_axis_tx_data_TLAST(dhcp2mux_TLAST), // output wire [0 : 0] m_axis_tx_data_TLAST
.m_axis_tx_length_TVALID(dhcp2muxTxLengthOut_V_V_TVALID), // output wire m_axis_tx_length_TVALID
.m_axis_tx_length_TREADY(dhcp2muxTxLengthOut_V_V_TREADY), // input wire m_axis_tx_length_TREADY
.m_axis_tx_length_TDATA(dhcp2muxTxLengthOut_V_V_TDATA), // output wire [15 : 0] m_axis_tx_length_TDATA
.m_axis_tx_metadata_TVALID(dhcp2muxTxMetadataOut_V_TVALID), // output wire m_axis_tx_metadata_TVALID
.m_axis_tx_metadata_TREADY(dhcp2muxTxMetadataOut_V_TREADY), // input wire m_axis_tx_metadata_TREADY
.m_axis_tx_metadata_TDATA(dhcp2muxTxMetadataOut_V_TDATA), // output wire [95 : 0] m_axis_tx_metadata_TDATA
.s_axis_open_port_status_TVALID(mux2dhcp_portOpenReplyIn_V_V_TVALID), // input wire s_axis_open_port_status_TVALID
.s_axis_open_port_status_TREADY(mux2dhcp_portOpenReplyIn_V_V_TREADY), // output wire s_axis_open_port_status_TREADY
.s_axis_open_port_status_TDATA(mux2dhcp_portOpenReplyIn_V_V_TDATA), // input wire [7 : 0] s_axis_open_port_status_TDATA
.s_axis_rx_data_TVALID(mux2dhcpRxDataIn_TVALID), // input wire s_axis_rx_data_TVALID
.s_axis_rx_data_TREADY(mux2dhcpRxDataIn_TREADY), // output wire s_axis_rx_data_TREADY
.s_axis_rx_data_TDATA(mux2dhcpRxDataIn_TDATA), // input wire [63 : 0] s_axis_rx_data_TDATA
.s_axis_rx_data_TKEEP(mux2dhcpRxDataIn_TKEEP), // input wire [7 : 0] s_axis_rx_data_TKEEP
.s_axis_rx_data_TLAST(mux2dhcpRxDataIn_TLAST), // input wire [0 : 0] s_axis_rx_data_TLAST
.s_axis_rx_metadata_TVALID(mux2dhcpRxMetadataIn_V_TVALID), // input wire s_axis_rx_metadata_TVALID
.s_axis_rx_metadata_TREADY(mux2dhcpRxMetadataIn_V_TREADY), // output wire s_axis_rx_metadata_TREADY
.s_axis_rx_metadata_TDATA(mux2dhcpRxMetadataIn_V_TDATA), // input wire [95 : 0] s_axis_rx_metadata_TDATA
.aclk(aclk), // input wire aclk
.aresetn(aresetn) // input wire aresetn
);
assign ipAddressOut = dhcpAddressOut;
assign upd_req_TVALID_out = upd_req_TVALID;
assign upd_req_TREADY_out = upd_req_TREADY;
assign upd_req_TDATA_out = upd_req_TDATA[1];
assign upd_rsp_TVALID_out = upd_rsp_TVALID;
assign upd_rsp_TREADY_out = upd_rsp_TREADY;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOBUFSRC_BLACKBOX_V
`define SKY130_FD_SC_LP__ISOBUFSRC_BLACKBOX_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__isobufsrc (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOBUFSRC_BLACKBOX_V
|
// Author: Adam Nunez, [email protected]
// Copyright (C) 2015 Adam Nunez
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module KeyPadInterpreter(
input Clock,
input ResetButton,
input KeyRead,
input [3:0] RowDataIn,
output KeyReady,
output [3:0] DataOut,
output [3:0] ColDataOut,
output [3:0] PressCount
);
//The keypad interpreter accepts typical inputs...
// Clock, Reset
//As well as KeyPad input/output connections...
// RowDataIn, ColDataOut
//Important Outputs...
// KeyReady, PressCount, DataOut
// KeyReady goes high when a key is ready
// to be read and does not go down
// until KeyRead goes high.
// PressCout is the single hexadigit
// value describing the number of
// times a key has been pressed
// DataOut is the single hexadigit
// value describing the button
// most recently pressed.
//Important Inputs...
// KeyRead must be asserted high for the
// scanner to continue. The KeyRead
// signal may only stay high for 8ms
// at most, it is recommended that the
// signal not remain high for longer
// than 4ms.
wire [3:0] KeyCode;
wire LFSRRst;
wire LFSRFlg;
LFSR25000 LFSR (Clock, LFSRRst, LFSRFlg);
KeyPadScanner Scanner (ResetButton, Clock, RowDataIn, ColDataOut, LFSRRst, LFSRFlg, KeyCode, KeyReady, KeyRead);
PulseCounter Count (ResetButton, Clock, KeyReady, PressCount);
KeyPadDecoder Decoder (KeyCode , DataOut);
endmodule |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_qspi_physical_2(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [1:0] io_ctrl_fmt_proto,
input io_ctrl_fmt_endian,
input io_ctrl_fmt_iodir,
output io_op_ready,
input io_op_valid,
input io_op_bits_fn,
input io_op_bits_stb,
input [7:0] io_op_bits_cnt,
input [7:0] io_op_bits_data,
output io_rx_valid,
output [7:0] io_rx_bits
);
reg [11:0] ctrl_sck_div;
reg [31:0] GEN_2;
reg ctrl_sck_pol;
reg [31:0] GEN_31;
reg ctrl_sck_pha;
reg [31:0] GEN_52;
reg [1:0] ctrl_fmt_proto;
reg [31:0] GEN_67;
reg ctrl_fmt_endian;
reg [31:0] GEN_68;
reg ctrl_fmt_iodir;
reg [31:0] GEN_69;
wire proto_0;
wire proto_1;
wire proto_2;
wire accept;
wire sample;
wire setup;
wire last;
reg setup_d;
reg [31:0] GEN_70;
reg T_119;
reg [31:0] GEN_71;
reg T_120;
reg [31:0] GEN_72;
reg sample_d;
reg [31:0] GEN_73;
reg T_122;
reg [31:0] GEN_74;
reg T_123;
reg [31:0] GEN_75;
reg last_d;
reg [31:0] GEN_76;
reg [7:0] scnt;
reg [31:0] GEN_77;
reg [11:0] tcnt;
reg [31:0] GEN_78;
wire stop;
wire beat;
wire [11:0] T_127;
wire [12:0] T_129;
wire [11:0] decr;
wire sched;
wire [11:0] T_130;
reg sck;
reg [31:0] GEN_79;
reg cref;
reg [31:0] GEN_80;
wire cinv;
wire [1:0] T_133;
wire [1:0] T_134;
wire [3:0] rxd;
wire samples_0;
wire [1:0] samples_1;
reg [7:0] buffer;
reg [31:0] GEN_81;
wire T_135;
wire T_136;
wire T_137;
wire T_138;
wire T_139;
wire T_140;
wire T_141;
wire T_142;
wire T_143;
wire [1:0] T_144;
wire [1:0] T_145;
wire [3:0] T_146;
wire [1:0] T_147;
wire [1:0] T_148;
wire [3:0] T_149;
wire [7:0] T_150;
wire [7:0] buffer_in;
wire T_151;
wire shift;
wire [6:0] T_152;
wire [6:0] T_153;
wire [6:0] T_154;
wire T_155;
wire T_157;
wire [7:0] T_158;
wire [5:0] T_159;
wire [5:0] T_160;
wire [5:0] T_161;
wire [1:0] T_162;
wire [1:0] T_163;
wire [7:0] T_164;
wire [3:0] T_165;
wire [3:0] T_166;
wire [3:0] T_167;
wire [3:0] T_169;
wire [7:0] T_170;
wire [7:0] T_172;
wire [7:0] T_174;
wire [7:0] T_176;
wire [7:0] T_178;
wire [7:0] T_179;
wire [7:0] T_180;
reg [3:0] txd;
reg [31:0] GEN_82;
wire [3:0] T_182;
wire [3:0] txd_in;
wire [1:0] T_184;
wire txd_sel_0;
wire txd_sel_1;
wire txd_sel_2;
wire txd_shf_0;
wire [1:0] txd_shf_1;
wire T_186;
wire [1:0] T_188;
wire [3:0] T_190;
wire [1:0] GEN_65;
wire [1:0] T_192;
wire [3:0] GEN_66;
wire [3:0] T_193;
wire [3:0] T_194;
wire [3:0] GEN_0;
wire T_195;
wire T_196;
wire txen_1;
wire txen_0;
wire T_202_0;
wire T_206;
wire T_207;
wire T_208;
wire T_209;
reg done;
reg [31:0] GEN_83;
wire T_212;
wire T_213;
wire T_215;
wire T_216;
wire T_217;
wire T_218;
wire T_219;
wire T_220;
wire T_221;
wire [1:0] T_222;
wire [1:0] T_223;
wire [3:0] T_224;
wire [1:0] T_225;
wire [1:0] T_226;
wire [3:0] T_227;
wire [7:0] T_228;
wire [7:0] T_229;
reg xfr;
reg [31:0] GEN_84;
wire GEN_1;
wire T_234;
wire T_236;
wire T_237;
wire GEN_3;
wire GEN_4;
wire GEN_5;
wire [11:0] GEN_6;
wire GEN_7;
wire GEN_8;
wire GEN_9;
wire GEN_10;
wire [11:0] GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire GEN_15;
wire [11:0] GEN_16;
wire T_243;
wire T_244;
wire T_245;
wire T_248;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire T_251;
wire [1:0] GEN_24;
wire GEN_25;
wire GEN_26;
wire T_254;
wire T_257;
wire [7:0] GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_32;
wire [11:0] GEN_33;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire [11:0] GEN_37;
wire GEN_38;
wire GEN_39;
wire [11:0] GEN_40;
wire [1:0] GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire [7:0] GEN_45;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire [11:0] GEN_49;
wire GEN_50;
wire GEN_51;
wire [11:0] GEN_53;
wire [1:0] GEN_54;
wire GEN_55;
wire GEN_56;
wire GEN_57;
wire [7:0] GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire [11:0] GEN_62;
wire GEN_63;
wire GEN_64;
assign io_port_sck = sck;
assign io_port_dq_0_o = T_206;
assign io_port_dq_0_oe = txen_0;
assign io_port_dq_1_o = T_207;
assign io_port_dq_1_oe = txen_1;
assign io_port_dq_2_o = T_208;
assign io_port_dq_2_oe = T_196;
assign io_port_dq_3_o = T_209;
assign io_port_dq_3_oe = io_port_dq_2_oe;
assign io_port_cs_0 = T_202_0;
assign io_op_ready = T_251;
assign io_rx_valid = done;
assign io_rx_bits = T_229;
assign proto_0 = 2'h0 == ctrl_fmt_proto;
assign proto_1 = 2'h1 == ctrl_fmt_proto;
assign proto_2 = 2'h2 == ctrl_fmt_proto;
assign accept = GEN_21;
assign sample = GEN_14;
assign setup = GEN_60;
assign last = GEN_20;
assign stop = scnt == 8'h0;
assign beat = tcnt == 12'h0;
assign T_127 = beat ? {{4'd0}, scnt} : tcnt;
assign T_129 = T_127 - 12'h1;
assign decr = T_129[11:0];
assign sched = GEN_1;
assign T_130 = sched ? ctrl_sck_div : decr;
assign cinv = ctrl_sck_pha ^ ctrl_sck_pol;
assign T_133 = {io_port_dq_1_i,io_port_dq_0_i};
assign T_134 = {io_port_dq_3_i,io_port_dq_2_i};
assign rxd = {T_134,T_133};
assign samples_0 = rxd[1];
assign samples_1 = rxd[1:0];
assign T_135 = io_ctrl_fmt_endian == 1'h0;
assign T_136 = io_op_bits_data[0];
assign T_137 = io_op_bits_data[1];
assign T_138 = io_op_bits_data[2];
assign T_139 = io_op_bits_data[3];
assign T_140 = io_op_bits_data[4];
assign T_141 = io_op_bits_data[5];
assign T_142 = io_op_bits_data[6];
assign T_143 = io_op_bits_data[7];
assign T_144 = {T_142,T_143};
assign T_145 = {T_140,T_141};
assign T_146 = {T_145,T_144};
assign T_147 = {T_138,T_139};
assign T_148 = {T_136,T_137};
assign T_149 = {T_148,T_147};
assign T_150 = {T_149,T_146};
assign buffer_in = T_135 ? io_op_bits_data : T_150;
assign T_151 = sample_d & stop;
assign shift = setup_d | T_151;
assign T_152 = buffer[6:0];
assign T_153 = buffer[7:1];
assign T_154 = shift ? T_152 : T_153;
assign T_155 = buffer[0];
assign T_157 = sample_d ? samples_0 : T_155;
assign T_158 = {T_154,T_157};
assign T_159 = buffer[5:0];
assign T_160 = buffer[7:2];
assign T_161 = shift ? T_159 : T_160;
assign T_162 = buffer[1:0];
assign T_163 = sample_d ? samples_1 : T_162;
assign T_164 = {T_161,T_163};
assign T_165 = buffer[3:0];
assign T_166 = buffer[7:4];
assign T_167 = shift ? T_165 : T_166;
assign T_169 = sample_d ? rxd : T_165;
assign T_170 = {T_167,T_169};
assign T_172 = proto_0 ? T_158 : 8'h0;
assign T_174 = proto_1 ? T_164 : 8'h0;
assign T_176 = proto_2 ? T_170 : 8'h0;
assign T_178 = T_172 | T_174;
assign T_179 = T_178 | T_176;
assign T_180 = T_179;
assign T_182 = buffer_in[7:4];
assign txd_in = accept ? T_182 : T_166;
assign T_184 = accept ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign txd_sel_0 = 2'h0 == T_184;
assign txd_sel_1 = 2'h1 == T_184;
assign txd_sel_2 = 2'h2 == T_184;
assign txd_shf_0 = txd_in[3];
assign txd_shf_1 = txd_in[3:2];
assign T_186 = txd_sel_0 ? txd_shf_0 : 1'h0;
assign T_188 = txd_sel_1 ? txd_shf_1 : 2'h0;
assign T_190 = txd_sel_2 ? txd_in : 4'h0;
assign GEN_65 = {{1'd0}, T_186};
assign T_192 = GEN_65 | T_188;
assign GEN_66 = {{2'd0}, T_192};
assign T_193 = GEN_66 | T_190;
assign T_194 = T_193;
assign GEN_0 = setup ? T_194 : txd;
assign T_195 = proto_1 & ctrl_fmt_iodir;
assign T_196 = proto_2 & ctrl_fmt_iodir;
assign txen_1 = T_195 | T_196;
assign txen_0 = proto_0 | txen_1;
assign T_202_0 = 1'h1;
assign T_206 = txd[0];
assign T_207 = txd[1];
assign T_208 = txd[2];
assign T_209 = txd[3];
assign T_212 = done | last_d;
assign T_213 = ctrl_fmt_endian == 1'h0;
assign T_215 = buffer[1];
assign T_216 = buffer[2];
assign T_217 = buffer[3];
assign T_218 = buffer[4];
assign T_219 = buffer[5];
assign T_220 = buffer[6];
assign T_221 = buffer[7];
assign T_222 = {T_220,T_221};
assign T_223 = {T_218,T_219};
assign T_224 = {T_223,T_222};
assign T_225 = {T_216,T_217};
assign T_226 = {T_155,T_215};
assign T_227 = {T_226,T_225};
assign T_228 = {T_227,T_224};
assign T_229 = T_213 ? buffer : T_228;
assign GEN_1 = stop ? 1'h1 : beat;
assign T_234 = stop == 1'h0;
assign T_236 = cref == 1'h0;
assign T_237 = cref ^ cinv;
assign GEN_3 = xfr ? T_237 : sck;
assign GEN_4 = xfr ? cref : 1'h0;
assign GEN_5 = xfr ? T_236 : 1'h0;
assign GEN_6 = T_236 ? decr : {{4'd0}, scnt};
assign GEN_7 = beat ? T_236 : cref;
assign GEN_8 = beat ? GEN_3 : sck;
assign GEN_9 = beat ? GEN_4 : 1'h0;
assign GEN_10 = beat ? GEN_5 : 1'h0;
assign GEN_11 = beat ? GEN_6 : {{4'd0}, scnt};
assign GEN_12 = T_234 ? GEN_7 : cref;
assign GEN_13 = T_234 ? GEN_8 : sck;
assign GEN_14 = T_234 ? GEN_9 : 1'h0;
assign GEN_15 = T_234 ? GEN_10 : 1'h0;
assign GEN_16 = T_234 ? GEN_11 : {{4'd0}, scnt};
assign T_243 = scnt == 8'h1;
assign T_244 = beat & cref;
assign T_245 = T_244 & xfr;
assign T_248 = beat & T_236;
assign GEN_17 = T_248 ? 1'h1 : stop;
assign GEN_18 = T_248 ? 1'h0 : GEN_15;
assign GEN_19 = T_248 ? ctrl_sck_pol : GEN_13;
assign GEN_20 = T_243 ? T_245 : 1'h0;
assign GEN_21 = T_243 ? GEN_17 : stop;
assign GEN_22 = T_243 ? GEN_18 : GEN_15;
assign GEN_23 = T_243 ? GEN_19 : GEN_13;
assign T_251 = accept & done;
assign GEN_24 = io_op_bits_stb ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign GEN_25 = io_op_bits_stb ? io_ctrl_fmt_endian : ctrl_fmt_endian;
assign GEN_26 = io_op_bits_stb ? io_ctrl_fmt_iodir : ctrl_fmt_iodir;
assign T_254 = 1'h0 == io_op_bits_fn;
assign T_257 = io_op_bits_cnt == 8'h0;
assign GEN_27 = T_254 ? buffer_in : T_180;
assign GEN_28 = T_254 ? cinv : GEN_23;
assign GEN_29 = T_254 ? 1'h1 : GEN_22;
assign GEN_30 = T_254 ? T_257 : T_212;
assign GEN_32 = io_op_bits_stb ? io_ctrl_sck_pol : GEN_28;
assign GEN_33 = io_op_bits_stb ? io_ctrl_sck_div : ctrl_sck_div;
assign GEN_34 = io_op_bits_stb ? io_ctrl_sck_pol : ctrl_sck_pol;
assign GEN_35 = io_op_bits_stb ? io_ctrl_sck_pha : ctrl_sck_pha;
assign GEN_36 = io_op_bits_fn ? GEN_32 : GEN_28;
assign GEN_37 = io_op_bits_fn ? GEN_33 : ctrl_sck_div;
assign GEN_38 = io_op_bits_fn ? GEN_34 : ctrl_sck_pol;
assign GEN_39 = io_op_bits_fn ? GEN_35 : ctrl_sck_pha;
assign GEN_40 = io_op_valid ? {{4'd0}, io_op_bits_cnt} : GEN_16;
assign GEN_41 = io_op_valid ? GEN_24 : ctrl_fmt_proto;
assign GEN_42 = io_op_valid ? GEN_25 : ctrl_fmt_endian;
assign GEN_43 = io_op_valid ? GEN_26 : ctrl_fmt_iodir;
assign GEN_44 = io_op_valid ? T_254 : xfr;
assign GEN_45 = io_op_valid ? GEN_27 : T_180;
assign GEN_46 = io_op_valid ? GEN_36 : GEN_23;
assign GEN_47 = io_op_valid ? GEN_29 : GEN_22;
assign GEN_48 = io_op_valid ? GEN_30 : T_212;
assign GEN_49 = io_op_valid ? GEN_37 : ctrl_sck_div;
assign GEN_50 = io_op_valid ? GEN_38 : ctrl_sck_pol;
assign GEN_51 = io_op_valid ? GEN_39 : ctrl_sck_pha;
assign GEN_53 = T_251 ? GEN_40 : GEN_16;
assign GEN_54 = T_251 ? GEN_41 : ctrl_fmt_proto;
assign GEN_55 = T_251 ? GEN_42 : ctrl_fmt_endian;
assign GEN_56 = T_251 ? GEN_43 : ctrl_fmt_iodir;
assign GEN_57 = T_251 ? GEN_44 : xfr;
assign GEN_58 = T_251 ? GEN_45 : T_180;
assign GEN_59 = T_251 ? GEN_46 : GEN_23;
assign GEN_60 = T_251 ? GEN_47 : GEN_22;
assign GEN_61 = T_251 ? GEN_48 : T_212;
assign GEN_62 = T_251 ? GEN_49 : ctrl_sck_div;
assign GEN_63 = T_251 ? GEN_50 : ctrl_sck_pol;
assign GEN_64 = T_251 ? GEN_51 : ctrl_sck_pha;
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_sck_div <= 12'b0;
ctrl_sck_pol <= 1'b0;
ctrl_sck_pha <= 1'b0;
ctrl_fmt_proto <= 2'b0;
ctrl_fmt_endian <= 1'b0;
ctrl_fmt_iodir <= 1'b0;
setup_d <= 1'b0;
tcnt <= 12'b0;
sck <= 1'b0;
buffer <= 8'b0;
xfr <= 1'b0;
end
else begin
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_div <= io_ctrl_sck_div;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pol <= io_ctrl_sck_pol;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pha <= io_ctrl_sck_pha;
end
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_proto <= io_ctrl_fmt_proto;
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_endian <= io_ctrl_fmt_endian;
end
end
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_iodir <= io_ctrl_fmt_iodir;
end
end
end
setup_d <= setup;
if (sched) begin
tcnt <= ctrl_sck_div;
end else begin
tcnt <= decr;
end
if (T_251) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
sck <= io_ctrl_sck_pol;
end else begin
if (T_254) begin
sck <= cinv;
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end
end
end else begin
if (T_254) begin
sck <= cinv;
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end else begin
if (T_234) begin
if (beat) begin
if (xfr) begin
sck <= T_237;
end
end
end
end
end
end
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
end else begin
if (T_243) begin
if (T_248) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
if (T_251) begin
if (io_op_valid) begin
if (T_254) begin
if (T_135) begin
buffer <= io_op_bits_data;
end else begin
buffer <= T_150;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
if (T_251) begin
if (io_op_valid) begin
xfr <= T_254;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cref <= 1'h1;
end else begin
if (T_234) begin
if (beat) begin
cref <= T_236;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
txd <= 4'h0;
end else begin
if (setup) begin
txd <= T_194;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
done <= 1'h1;
end else begin
if (T_251) begin
if (io_op_valid) begin
if (T_254) begin
done <= T_257;
end else begin
done <= T_212;
end
end else begin
done <= T_212;
end
end else begin
done <= T_212;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_119 <= 1'h0;
end else begin
T_119 <= sample;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_120 <= 1'h0;
end else begin
T_120 <= T_119;
end
always @(posedge clock or posedge reset)
if (reset) begin
sample_d <= 1'h0;
end else begin
sample_d <= T_120;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_122 <= 1'h0;
end else begin
T_122 <= last;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_123 <= 1'h0;
end else begin
T_123 <= T_122;
end
always @(posedge clock or posedge reset)
if (reset) begin
last_d <= 1'h0;
end else begin
last_d <= T_123;
end
always @(posedge clock or posedge reset)
if (reset) begin
scnt <= 8'h0;
end else begin
scnt <= GEN_53[7:0];
end
endmodule
|
// fpgaTop_sp605.v - ssiegel 2010-03-30
module fpgaTop(
input wire sys0_clkp, // sys0 Clock +
input wire sys0_clkn, // sys0 Clock -
input wire pci0_clkp, // PCIe Clock +
input wire pci0_clkn, // PCIe Clock -
input wire pci0_reset_n, // PCIe Reset
output wire [7:0] pci_exp_txp, // PCIe lanes...
output wire [7:0] pci_exp_txn,
input wire [7:0] pci_exp_rxp,
input wire [7:0] pci_exp_rxn,
output wire [2:0] led, // LEDs ml555
input wire ppsExtIn, // PPS in
output wire ppsOut // PPS out
);
// Instance and connect mkFTop...
mkFTop_sp605 ftop(
.sys0_clkp (sys0_clkp),
.sys0_clkn (sys0_clkn),
.pci0_clkp (pci0_clkp),
.pci0_clkn (pci0_clkn),
.pci0_rstn (pci0_reset_n),
.pcie_rxp_i (pci_exp_rxp),
.pcie_rxn_i (pci_exp_rxn),
.pcie_txp (pci_exp_txp),
.pcie_txn (pci_exp_txn),
.led (led),
.gps_ppsSyncIn_x (ppsExtIn),
.gps_ppsSyncOut (ppsOut)
);
endmodule
|
/*
* sobel_cache.v
*
* Created on: 09/10/2012
* Author: Lord_Rafa
*/
`timescale 1 ps / 1 ps
module Sobel_cache (
input clk,
input rst,
input start,
input [ADD_WIDTH-1:0] base_add,
input [13:0] rdaddress,
output wire [12:0] valid_lines,
input free_line,
output wire [ 7:0] q,
output wire [ADD_WIDTH-1:0] ram_r_address,
input ram_r_waitrequest,
input ram_r_readdatavalid,
output wire [BYTE_ENABLE_WIDTH-1:0] ram_r_byteenable,
output wire ram_r_read,
input [DATA_WIDTH-1:0] ram_r_readdata,
output wire [BURST_WIDTH_R-1:0] ram_r_burstcount
);
parameter DATA_WIDTH=32;
parameter ADD_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4;
parameter BURST_WIDTH_R = 6;
parameter MAX_BURST_COUNT_R = 32;
reg [ADD_WIDTH-1:0] read_address;
reg [ADD_WIDTH-1:0] write_address;
reg [12:0] used_cache_pixels;
reg [31:0] in_n;
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n <= 0;
end else begin
if (start == 1) begin
in_n <= 384000;
end else begin
if (read_burst_end == 1) begin
in_n <= in_n - MAX_BURST_COUNT_R;
end
end
end
end
always @(posedge clk) begin
if (start == 1) begin
read_address <= base_add;
end else begin
if (read_burst_end == 1) begin
read_address <= read_address + MAX_BURST_COUNT_R * BYTE_ENABLE_WIDTH;
end
end
end
// reg [ 3:0] valid;
always @(posedge clk) begin
if (start == 1) begin
used_cache_pixels <= 0;
end else begin
if (read_complete == 1) begin
if (free_line == 0) begin
used_cache_pixels <= used_cache_pixels + 1;
end else begin
used_cache_pixels <= used_cache_pixels - 799;
end
end else begin
if (free_line == 1) begin
used_cache_pixels <= used_cache_pixels - 800;
end
end
end
end
assign valid_lines = used_cache_pixels;
reg [31:0] reads_pending;
always @ (posedge clk) begin
if (start == 1) begin
reads_pending <= 0;
end else begin
if(read_burst_end == 1) begin
if(read_complete == 0) begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R;
end else begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R - 1;
end
end else begin
if(read_complete == 0) begin
reads_pending <= reads_pending;
end else begin
reads_pending <= reads_pending - 1;
end
end
end
end
reg [31:0] next_r;
always @ (posedge clk) begin
if (start == 1) begin
next_r <= 0;
end else begin
if(read_burst_end == 1) begin
next_r <= 0;
end else begin
if (ram_r_read == 1) begin
next_r <= 1;
end
end
end
end
always @(posedge clk) begin
if (start == 1) begin
write_address <= 0;
end else begin
if (read_complete == 1) begin
if (write_address == 7999) begin
write_address <= 0;
end else begin
write_address <= write_address + 1;
end
end
end
end
altsyncram altsyncram_component (
.clock0 (clk),
.data_a (ram_r_readdata[7:0]),
.address_a (write_address),
.wren_a (read_complete),
.address_b (rdaddress),
.q_b (q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.numwords_b = 8192,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 13,
altsyncram_component.widthad_b = 13,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
assign read_complete = (ram_r_readdatavalid == 1);
assign read_burst_end = (ram_r_waitrequest == 0) & (next_r == 1);
assign too_many_reads_pending = (reads_pending + used_cache_pixels) > (8000 - MAX_BURST_COUNT_R);
assign ram_r_address = read_address;
assign ram_r_read = (too_many_reads_pending == 0) & (in_n != 0);
assign ram_r_byteenable = {BYTE_ENABLE_WIDTH{1'b1}};
assign ram_r_burstcount = MAX_BURST_COUNT_R;
endmodule
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// input clk is 24MHz
`include "min_max_tracker.v"
module lf_edge_detect(input clk, input [7:0] adc_d, input [7:0] lf_ed_threshold,
output [7:0] max, output [7:0] min,
output [7:0] high_threshold, output [7:0] highz_threshold,
output [7:0] lowz_threshold, output [7:0] low_threshold,
output edge_state, output edge_toggle);
min_max_tracker tracker(clk, adc_d, lf_ed_threshold, min, max);
// auto-tune
assign high_threshold = (max + min) / 2 + (max - min) / 4;
assign highz_threshold = (max + min) / 2 + (max - min) / 8;
assign lowz_threshold = (max + min) / 2 - (max - min) / 8;
assign low_threshold = (max + min) / 2 - (max - min) / 4;
// heuristic to see if it makes sense to try to detect an edge
wire enabled =
(high_threshold > highz_threshold)
& (highz_threshold > lowz_threshold)
& (lowz_threshold > low_threshold)
& ((high_threshold - highz_threshold) > 8)
& ((highz_threshold - lowz_threshold) > 16)
& ((lowz_threshold - low_threshold) > 8);
// Toggle the output with hysteresis
// Set to high if the ADC value is above the threshold
// Set to low if the ADC value is below the threshold
reg is_high = 0;
reg is_low = 0;
reg is_zero = 0;
reg trigger_enabled = 1;
reg output_edge = 0;
reg output_state;
always @(posedge clk)
begin
is_high <= (adc_d >= high_threshold);
is_low <= (adc_d <= low_threshold);
is_zero <= ((adc_d > lowz_threshold) & (adc_d < highz_threshold));
end
// all edges detection
always @(posedge clk)
if (enabled) begin
// To enable detecting two consecutive peaks at the same level
// (low or high) we check whether or not we went back near 0 in-between.
// This extra check is necessary to prevent from noise artifacts
// around the threshold values.
if (trigger_enabled & (is_high | is_low)) begin
output_edge <= ~output_edge;
trigger_enabled <= 0;
end else
trigger_enabled <= trigger_enabled | is_zero;
end
// edge states
always @(posedge clk)
if (enabled) begin
if (is_high)
output_state <= 1'd1;
else if (is_low)
output_state <= 1'd0;
end
assign edge_state = output_state;
assign edge_toggle = output_edge;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_OV2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__SDFRTP_OV2_FUNCTIONAL_PP_V
/**
* sdfrtp_ov2: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfrtp_ov2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_OV2_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3B_TB_V
`define SKY130_FD_SC_HDLL__AND3B_TB_V
/**
* and3b: 3-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and3b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A_N = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A_N = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A_N = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A_N = 1'bx;
end
sky130_fd_sc_hdll__and3b dut (.A_N(A_N), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3B_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__OR3_BEHAVIORAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NOR4B_PP_SYMBOL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_PP_SYMBOL_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : wrap_ref_chroma.v
// Author : Yufeng Bai
// Email : [email protected]
//
// $Id$
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module wrap_ref_chroma (
clk ,
rstn ,
wrif_en_i ,
wrif_addr_i ,
wrif_data_i ,
rdif_en_i ,
rdif_addr_i ,
rdif_pdata_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk ; // clk signal
input [1-1:0] rstn ; // asynchronous reset
input [1-1:0] wrif_en_i ; // write enabel signal
input [6-1:0] wrif_addr_i ; // mem addr (0 - 95)
input [48*`PIXEL_WIDTH-1:0] wrif_data_i ; // write pixel data (8 pixels)
input [1-1:0] rdif_en_i ; // read referrence pixels enable signale
input [6-1:0] rdif_addr_i ; // search window x position (0 - 32 )
output [48*`PIXEL_WIDTH-1:0] rdif_pdata_o ; // referrence pixles data
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
wire [6-1:0] ref_addr;
assign ref_addr = (wrif_en_i) ? wrif_addr_i : rdif_addr_i;
// ********************************************
//
// MEM INSTANCE DECLARATION
//
// ********************************************
rf_1p #(.Addr_Width(6),.Word_Width(`PIXEL_WIDTH*48))
wrap (
.clk (clk),
.cen_i(1'b0),
.wen_i(~wrif_en_i),
.addr_i(ref_addr),
.data_i(wrif_data_i),
.data_o(rdif_pdata_o)
);
endmodule
|
(* abc9_lut=1, lib_whitebox *)
module LUT4(input A, B, C, D, output Z);
parameter INIT = "0x0000";
`include "parse_init.vh"
localparam initp = parse_init(INIT);
wire [7:0] s3 = D ? initp[15:8] : initp[7:0];
wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
assign Z = A ? s1[1] : s1[0];
// Per-input delay differences are considered 'interconnect'
// so not known yet
specify
(A => Z) = 233;
(B => Z) = 233;
(C => Z) = 233;
(D => Z) = 233;
endspecify
endmodule
// This is a placeholder for ABC9 to extract the area/delay
// cost of 5-input LUTs and is not intended to be instantiated
(* abc9_lut=2 *)
module \$__ABC9_LUT5 (input SEL, D, C, B, A, output Z);
specify
(SEL => Z) = 171;
(D => Z) = 303;
(C => Z) = 311;
(B => Z) = 309;
(A => Z) = 306;
endspecify
endmodule
// Two LUT4s and MUX2
module WIDEFN9(input A0, B0, C0, D0, A1, B1, C1, D1, SEL, output Z);
parameter INIT0 = "0x0000";
parameter INIT1 = "0x0000";
wire z0, z1;
LUT4 #(.INIT(INIT0)) lut4_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(z0));
LUT4 #(.INIT(INIT1)) lut4_1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(z1));
assign Z = SEL ? z1 : z0;
endmodule
(* abc9_box, lib_whitebox *)
module INV(input A, output Z);
assign Z = !A;
specify
(A => Z) = 10;
endspecify
endmodule
// Bidirectional IO buffer
module BB(input T, I, output O,
(* iopad_external_pin *) inout B);
assign B = T ? 1'bz : O;
assign I = B;
endmodule
// Input buffer
module IB(
(* iopad_external_pin *) input I,
output O);
assign O = I;
endmodule
// Output buffer
module OB(input I,
(* iopad_external_pin *) output O);
assign O = I;
endmodule
// Output buffer with tristate
module OBZ(input I, T,
(* iopad_external_pin *) output O);
assign O = T ? 1'bz : I;
endmodule
// Constants
module VLO(output Z);
assign Z = 1'b0;
endmodule
module VHI(output Z);
assign Z = 1'b1;
endmodule
// Vendor flipflops
// (all have active high clock, enable and set/reset - use INV to invert)
// Async preset
(* abc9_box, lib_whitebox *)
module FD1P3BX(input D, CK, SP, PD, output reg Q);
parameter GSR = "DISABLED";
initial Q = 1'b1;
always @(posedge CK or posedge PD)
if (PD)
Q <= 1'b1;
else if (SP)
Q <= D;
specify
$setup(D, posedge CK, 0);
$setup(SP, posedge CK, 212);
$setup(PD, posedge CK, 224);
`ifndef YOSYS
if (PD) (posedge CLK => (Q : 1)) = 0;
`else
if (PD) (PD => Q) = 0; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!PD && SP) (posedge CK => (Q : D)) = 336;
endspecify
endmodule
// Async clear
(* abc9_box, lib_whitebox *)
module FD1P3DX(input D, CK, SP, CD, output reg Q);
parameter GSR = "DISABLED";
initial Q = 1'b0;
always @(posedge CK or posedge CD)
if (CD)
Q <= 1'b0;
else if (SP)
Q <= D;
specify
$setup(D, posedge CK, 0);
$setup(SP, posedge CK, 212);
$setup(CD, posedge CK, 224);
`ifndef YOSYS
if (CD) (posedge CLK => (Q : 0)) = 0;
`else
if (CD) (CD => Q) = 0; // Technically, this should be an edge sensitive path
// but for facilitating a bypass box, let's pretend it's
// a simple path
`endif
if (!CD && SP) (posedge CK => (Q : D)) = 336;
endspecify
endmodule
// Sync clear
(* abc9_flop, lib_whitebox *)
module FD1P3IX(input D, CK, SP, CD, output reg Q);
parameter GSR = "DISABLED";
initial Q = 1'b0;
always @(posedge CK)
if (CD)
Q <= 1'b0;
else if (SP)
Q <= D;
specify
$setup(D, posedge CK, 0);
$setup(SP, posedge CK, 212);
$setup(CD, posedge CK, 224);
if (!CD && SP) (posedge CK => (Q : D)) = 336;
endspecify
endmodule
// Sync preset
(* abc9_flop, lib_whitebox *)
module FD1P3JX(input D, CK, SP, PD, output reg Q);
parameter GSR = "DISABLED";
initial Q = 1'b1;
always @(posedge CK)
if (PD)
Q <= 1'b1;
else if (SP)
Q <= D;
specify
$setup(D, posedge CK, 0);
$setup(SP, posedge CK, 212);
$setup(PD, posedge CK, 224);
if (!PD && SP) (posedge CK => (Q : D)) = 336;
endspecify
endmodule
// LUT4 with LUT3 tap for CCU2 use only
(* lib_whitebox *)
module LUT4_3(input A, B, C, D, output Z, Z3);
parameter INIT = "0x0000";
`include "parse_init.vh"
localparam initp = parse_init(INIT);
wire [7:0] s3 = D ? initp[15:8] : initp[7:0];
wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
assign Z = A ? s1[1] : s1[0];
wire [3:0] s2_3 = C ? initp[ 7:4] : initp[3:0];
wire [1:0] s1_3 = B ? s2_3[ 3:2] : s2_3[1:0];
assign Z3 = A ? s1_3[1] : s1_3[0];
endmodule
// Carry primitive (incoporating two LUTs)
(* abc9_box, lib_whitebox *)
module CCU2(
(* abc9_carry *) input CIN,
input A1, B1, C1, D1, A0, B0, C0, D0,
output S1, S0,
(* abc9_carry *) output COUT);
parameter INJECT = "YES";
parameter INIT0 = "0x0000";
parameter INIT1 = "0x1111";
localparam inject_p = (INJECT == "YES") ? 1'b1 : 1'b0;
wire LUT3_0, LUT4_0, LUT3_1, LUT4_1, carry_0;
LUT4_3 #(.INIT(INIT0)) lut0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0), .Z3(LUT3_0));
LUT4_3 #(.INIT(INIT1)) lut1 (.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1), .Z3(LUT3_1));
assign S0 = LUT4_0 ^ (CIN & ~inject_p);
assign carry_0 = LUT4_0 ? CIN : (LUT3_0 & ~inject_p);
assign S1 = LUT4_1 ^ (carry_0 & ~inject_p);
assign COUT = LUT4_1 ? carry_0 : (LUT3_1 & ~inject_p);
specify
(A0 => S0) = 233;
(B0 => S0) = 233;
(C0 => S0) = 233;
(D0 => S0) = 233;
(CIN => S0) = 228;
(A0 => S1) = 481;
(B0 => S1) = 481;
(C0 => S1) = 481;
(D0 => S1) = 481;
(A1 => S1) = 233;
(B1 => S1) = 233;
(C1 => S1) = 233;
(D1 => S1) = 233;
(CIN => S1) = 307;
(A0 => COUT) = 347;
(B0 => COUT) = 347;
(C0 => COUT) = 347;
(D0 => COUT) = 347;
(A1 => COUT) = 347;
(B1 => COUT) = 347;
(C1 => COUT) = 347;
(D1 => COUT) = 347;
(CIN => COUT) = 59;
endspecify
endmodule
// Packed flipflop
module OXIDE_FF(input CLK, LSR, CE, DI, M, output reg Q);
parameter GSR = "ENABLED";
parameter [127:0] CEMUX = "1";
parameter CLKMUX = "CLK";
parameter LSRMUX = "LSR";
parameter REGDDR = "DISABLED";
parameter SRMODE = "LSR_OVER_CE";
parameter REGSET = "RESET";
parameter [127:0] LSRMODE = "LSR";
wire muxce;
generate
case (CEMUX)
"1": assign muxce = 1'b1;
"0": assign muxce = 1'b0;
"INV": assign muxce = ~CE;
default: assign muxce = CE;
endcase
endgenerate
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
wire srval;
generate
if (LSRMODE == "PRLD")
assign srval = M;
else
assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
endgenerate
initial Q = srval;
generate
if (REGDDR == "ENABLED") begin
if (SRMODE == "ASYNC") begin
always @(posedge muxclk, negedge muxclk, posedge muxlsr)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end else begin
always @(posedge muxclk, negedge muxclk)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end
end else begin
if (SRMODE == "ASYNC") begin
always @(posedge muxclk, posedge muxlsr)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end else begin
always @(posedge muxclk)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end
end
endgenerate
endmodule
// Packed combinational logic (for post-pnr sim)
module OXIDE_COMB(
input A, B, C, D, // LUT inputs
input SEL, // mux select input
input F1, // output from LUT 1 for mux
input FCI, // carry input
input WAD0, WAD1, WAD2, WAD3, // LUTRAM write address inputs
input WD, // LUTRAM write data input
input WCK, WRE, // LUTRAM write clock and enable
output F, // LUT/carry output
output OFX // mux output
);
parameter MODE = "LOGIC"; // LOGIC, CCU2, DPRAM
parameter [15:0] INIT = 16'h0000;
parameter INJECT = "YES";
localparam inject_p = (INJECT == "YES") ? 1'b1 : 1'b0;
reg [15:0] lut = INIT;
wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
wire Z = A ? s1[1] : s1[0];
wire [3:0] s2_3 = C ? INIT[ 7:4] : INIT[3:0];
wire [1:0] s1_3 = B ? s2_3[ 3:2] : s2_3[1:0];
wire Z3 = A ? s1_3[1] : s1_3[0];
generate
if (MODE == "DPRAM") begin
always @(posedge WCK)
if (WRE)
lut[{WAD3, WAD2, WAD1, WAD0}] <= WD;
end
if (MODE == "CCU2") begin
assign F = Z ^ (FCI & ~inject_p);
assign FCO = Z ? FCI : (Z3 & ~inject_p);
end else begin
assign F = Z;
end
endgenerate
assign OFX = SEL ? F1 : F;
endmodule
// LUTRAM
module DPR16X4(
input [3:0] RAD, DI, WAD,
input WRE, WCK,
output [3:0] DO
);
parameter INITVAL = "0x0000000000000000";
`include "parse_init.vh"
localparam [63:0] parsed_init = parse_init_64(INITVAL);
reg [3:0] mem[0:15];
integer i;
initial begin
for (i = 0; i < 15; i++)
mem[i] = parsed_init[i * 4 +: 4];
end
always @(posedge WCK)
if (WRE)
mem[WAD] <= DI;
assign DO = mem[RAD];
endmodule
// Used for all the DSP models to reduce duplication
module OXIDE_DSP_REG #(
parameter W = 18,
parameter USED = "REGISTER",
parameter RESETMODE = "SYNC"
) (
input CLK, CE, RST,
input [W-1:0] D,
output reg [W-1:0] Q
);
generate
if (USED == "BYPASS")
always @* Q = D;
else if (USED == "REGISTER") begin
initial Q = 0;
if (RESETMODE == "ASYNC")
always @(posedge CLK, posedge RST) begin
if (RST)
Q <= 0;
else if (CE)
Q <= D;
end
else if (RESETMODE == "SYNC")
always @(posedge CLK) begin
if (RST)
Q <= 0;
else if (CE)
Q <= D;
end
end
endgenerate
endmodule
module OXIDE_DSP_SIM #(
// User facing parameters
parameter REGINPUTA = "BYPASS",
parameter REGINPUTB = "BYPASS",
parameter REGINPUTC = "BYPASS",
parameter REGADDSUB = "BYPASS",
parameter REGLOADC = "BYPASS",
parameter REGLOADC2 = "BYPASS",
parameter REGCIN = "BYPASS",
parameter REGPIPELINE = "BYPASS",
parameter REGOUTPUT = "BYPASS",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC",
// Internally used parameters
parameter A_WIDTH = 36,
parameter B_WIDTH = 36,
parameter C_WIDTH = 36,
parameter Z_WIDTH = 72,
parameter PREADD_USED = 0,
parameter ADDSUB_USED = 0
) (
input [A_WIDTH-1:0] A,
input [B_WIDTH-1:0] B,
input [C_WIDTH-1:0] C,
input SIGNEDA,
input SIGNEDB,
input SIGNEDC,
input CIN,
input LOADC,
input ADDSUB,
input CLK,
input CEA, CEB, CEC, CEPIPE, CECTRL, CECIN, CEOUT,
input RSTA, RSTB, RSTC, RSTPIPE, RSTCTRL, RSTCIN, RSTOUT,
output wire [Z_WIDTH-1:0] Z
);
localparam M_WIDTH = (A_WIDTH+B_WIDTH);
/******** REGISTERS ********/
wire [M_WIDTH-1:0] pipe_d, pipe_q;
wire [Z_WIDTH-1:0] z_d;
wire [A_WIDTH-1:0] a_r;
wire [B_WIDTH-1:0] b_r;
wire [C_WIDTH-1:0] c_r, c_r2;
wire asgd_r, bsgd_r, csgd_r, csgd_r2;
wire addsub_r, addsub_r2, cin_r, cin_r2, sgd_r, sgd_r2;
wire loadc_r, loadc_r2;
OXIDE_DSP_REG #(A_WIDTH+1, REGINPUTA, RESETMODE) a_reg(CLK, CEA, RSTA, {SIGNEDA, A}, {asgd_r, a_r});
OXIDE_DSP_REG #(B_WIDTH+1, REGINPUTB, RESETMODE) b_reg(CLK, CEB, RSTB, {SIGNEDB, B}, {bsgd_r, b_r});
OXIDE_DSP_REG #(C_WIDTH+1, REGINPUTC, RESETMODE) c_reg(CLK, CEC, RSTC, {SIGNEDC, C}, {csgd_r, c_r});
OXIDE_DSP_REG #(M_WIDTH, REGPIPELINE, RESETMODE) pipe_reg(CLK, CEPIPE, RSTPIPE, pipe_d, pipe_q);
OXIDE_DSP_REG #(2, REGADDSUB, RESETMODE) addsub_reg(CLK, CECTRL, RSTCTRL, {SIGNEDA, ADDSUB}, {sgd_r, addsub_r});
OXIDE_DSP_REG #(1, REGLOADC, RESETMODE) loadc_reg(CLK, CECTRL, RSTCTRL, LOADC, loadc_r);
OXIDE_DSP_REG #(2, REGPIPELINE, RESETMODE) addsub2_reg(CLK, CECTRL, RSTCTRL, {sgd_r, addsub_r}, {sgd_r2, addsub_r2});
OXIDE_DSP_REG #(1, REGLOADC2, RESETMODE) loadc2_reg(CLK, CECTRL, RSTCTRL, loadc_r, loadc_r2);
OXIDE_DSP_REG #(1, REGCIN, RESETMODE) cin_reg(CLK, CECIN, RSTCIN, CIN, cin_r);
OXIDE_DSP_REG #(1, REGPIPELINE, RESETMODE) cin2_reg(CLK, CECIN, RSTCIN, cin_r, cin_r2);
OXIDE_DSP_REG #(C_WIDTH+1, REGPIPELINE, RESETMODE) c2_reg(CLK, CEC, RSTC, {csgd_r, c_r}, {csgd_r2, c_r2});
OXIDE_DSP_REG #(Z_WIDTH, REGOUTPUT, RESETMODE) z_reg(CLK, CEOUT, RSTOUT, z_d, Z);
/******** PREADDER ********/
wire [B_WIDTH-1:0] mult_b;
wire mult_b_sgd;
generate
if (PREADD_USED) begin
assign mult_b = (b_r + c_r);
assign mult_b_sgd = (bsgd_r | csgd_r);
end else begin
assign mult_b = b_r;
assign mult_b_sgd = bsgd_r;
end
endgenerate
/******** MULTIPLIER ********/
// sign extend operands if needed
wire [M_WIDTH-1:0] mult_a_ext = {{(M_WIDTH-A_WIDTH){asgd_r ? a_r[A_WIDTH-1] : 1'b0}}, a_r};
wire [M_WIDTH-1:0] mult_b_ext = {{(M_WIDTH-B_WIDTH){mult_b_sgd ? mult_b[B_WIDTH-1] : 1'b0}}, mult_b};
wire [M_WIDTH-1:0] mult_m = mult_a_ext * mult_b_ext;
/******** ACCUMULATOR ********/
wire [Z_WIDTH-1:0] m_ext;
generate
if (ADDSUB_USED) begin
assign pipe_d = mult_m;
assign m_ext = {{(Z_WIDTH-M_WIDTH){sgd_r2 ? pipe_q[M_WIDTH-1] : 1'b0}}, pipe_q};
assign z_d = (loadc_r2 ? c_r2 : Z) + cin_r2 + (addsub_r2 ? -m_ext : m_ext);
end else begin
assign z_d = mult_m;
end
endgenerate
endmodule
module MULT9X9 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [8:0] A,
input [8:0] B,
input CLK,
input CEA,
input RSTA,
input CEB,
input RSTB,
input SIGNEDA,
input SIGNEDB,
input RSTOUT,
input CEOUT,
output [17:0] Z
);
OXIDE_DSP_SIM #(
.REGINPUTA(REGINPUTA),
.REGINPUTB(REGINPUTB),
.REGOUTPUT(REGOUTPUT),
.GSR(GSR),
.RESETMODE(RESETMODE),
.A_WIDTH(9),
.B_WIDTH(9),
.Z_WIDTH(18),
.PREADD_USED(0),
.ADDSUB_USED(0)
) dsp_i (
.A(A), .B(B),
.CLK(CLK),
.CEA(CEA), .RSTA(RSTA),
.CEB(CEB), .RSTB(RSTB),
.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
.Z(Z)
);
endmodule
module MULT18X18 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [17:0] A,
input [17:0] B,
input CLK,
input CEA,
input RSTA,
input CEB,
input RSTB,
input SIGNEDA,
input SIGNEDB,
input RSTOUT,
input CEOUT,
output [35:0] Z
);
OXIDE_DSP_SIM #(
.REGINPUTA(REGINPUTA),
.REGINPUTB(REGINPUTB),
.REGOUTPUT(REGOUTPUT),
.GSR(GSR),
.RESETMODE(RESETMODE),
.A_WIDTH(18),
.B_WIDTH(18),
.Z_WIDTH(36),
.PREADD_USED(0),
.ADDSUB_USED(0)
) dsp_i (
.A(A), .B(B),
.CLK(CLK),
.CEA(CEA), .RSTA(RSTA),
.CEB(CEB), .RSTB(RSTB),
.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
.Z(Z)
);
endmodule
module MULT18X36 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [17:0] A,
input [35:0] B,
input CLK,
input CEA,
input RSTA,
input CEB,
input RSTB,
input SIGNEDA,
input SIGNEDB,
input RSTOUT,
input CEOUT,
output [53:0] Z
);
OXIDE_DSP_SIM #(
.REGINPUTA(REGINPUTA),
.REGINPUTB(REGINPUTB),
.REGOUTPUT(REGOUTPUT),
.GSR(GSR),
.RESETMODE(RESETMODE),
.A_WIDTH(18),
.B_WIDTH(36),
.Z_WIDTH(54),
.PREADD_USED(0),
.ADDSUB_USED(0)
) dsp_i (
.A(A), .B(B),
.CLK(CLK),
.CEA(CEA), .RSTA(RSTA),
.CEB(CEB), .RSTB(RSTB),
.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
.Z(Z)
);
endmodule
module MULT36X36 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [35:0] A,
input [35:0] B,
input CLK,
input CEA,
input RSTA,
input CEB,
input RSTB,
input SIGNEDA,
input SIGNEDB,
input RSTOUT,
input CEOUT,
output [71:0] Z
);
OXIDE_DSP_SIM #(
.REGINPUTA(REGINPUTA),
.REGINPUTB(REGINPUTB),
.REGOUTPUT(REGOUTPUT),
.GSR(GSR),
.RESETMODE(RESETMODE),
.A_WIDTH(36),
.B_WIDTH(36),
.Z_WIDTH(72),
.PREADD_USED(0),
.ADDSUB_USED(0)
) dsp_i (
.A(A), .B(B),
.CLK(CLK),
.CEA(CEA), .RSTA(RSTA),
.CEB(CEB), .RSTB(RSTB),
.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB),
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
.Z(Z)
);
endmodule
module MULTPREADD9X9 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGINPUTC = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [8:0] A,
input [8:0] B,
input [8:0] C,
input CLK,
input CEA,
input RSTA,
input CEB,
input RSTB,
input CEC,
input RSTC,
input SIGNEDA,
input SIGNEDB,
input SIGNEDC,
input RSTOUT,
input CEOUT,
output [17:0] Z
);
OXIDE_DSP_SIM #(
.REGINPUTA(REGINPUTA),
.REGINPUTB(REGINPUTB),
.REGINPUTC(REGINPUTC),
.REGOUTPUT(REGOUTPUT),
.GSR(GSR),
.RESETMODE(RESETMODE),
.A_WIDTH(9),
.B_WIDTH(9),
.C_WIDTH(9),
.Z_WIDTH(18),
.PREADD_USED(1),
.ADDSUB_USED(0)
) dsp_i (
.A(A), .B(B), .C(C),
.CLK(CLK),
.CEA(CEA), .RSTA(RSTA),
.CEB(CEB), .RSTB(RSTB),
.CEC(CEC), .RSTC(RSTC),
.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB), .SIGNEDC(SIGNEDC),
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
.Z(Z)
);
endmodule
module MULTPREADD18X18 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGINPUTC = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [17:0] A,
input [17:0] B,
input [17:0] C,
input CLK,
input CEA,
input RSTA,
input CEB,
input RSTB,
input CEC,
input RSTC,
input SIGNEDA,
input SIGNEDB,
input SIGNEDC,
input RSTOUT,
input CEOUT,
output [35:0] Z
);
OXIDE_DSP_SIM #(
.REGINPUTA(REGINPUTA),
.REGINPUTB(REGINPUTB),
.REGINPUTC(REGINPUTC),
.REGOUTPUT(REGOUTPUT),
.GSR(GSR),
.RESETMODE(RESETMODE),
.A_WIDTH(18),
.B_WIDTH(18),
.C_WIDTH(18),
.Z_WIDTH(36),
.PREADD_USED(1),
.ADDSUB_USED(0)
) dsp_i (
.A(A), .B(B), .C(C),
.CLK(CLK),
.CEA(CEA), .RSTA(RSTA),
.CEB(CEB), .RSTB(RSTB),
.CEC(CEC), .RSTC(RSTC),
.SIGNEDA(SIGNEDA), .SIGNEDB(SIGNEDB), .SIGNEDC(SIGNEDC),
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
.Z(Z)
);
endmodule
module MULTADDSUB18X18 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGINPUTC = "REGISTER",
parameter REGADDSUB = "REGISTER",
parameter REGLOADC = "REGISTER",
parameter REGLOADC2 = "REGISTER",
parameter REGCIN = "REGISTER",
parameter REGPIPELINE = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [17:0] A,
input [17:0] B,
input [53:0] C,
input CLK,
input CEA,
input RSTA,
input CEB,
input RSTB,
input CEC,
input RSTC,
input SIGNED,
input RSTPIPE,
input CEPIPE,
input RSTCTRL,
input CECTRL,
input RSTCIN,
input CECIN,
input LOADC,
input ADDSUB,
output [53:0] Z,
input RSTOUT,
input CEOUT,
input CIN
);
OXIDE_DSP_SIM #(
.REGINPUTA(REGINPUTA),
.REGINPUTB(REGINPUTB),
.REGINPUTC(REGINPUTC),
.REGADDSUB(REGADDSUB),
.REGLOADC(REGLOADC),
.REGLOADC2(REGLOADC2),
.REGCIN(REGCIN),
.REGPIPELINE(REGPIPELINE),
.REGOUTPUT(REGOUTPUT),
.GSR(GSR),
.RESETMODE(RESETMODE),
.A_WIDTH(18),
.B_WIDTH(18),
.C_WIDTH(54),
.Z_WIDTH(54),
.PREADD_USED(0),
.ADDSUB_USED(1)
) dsp_i (
.A(A), .B(B), .C(C),
.CLK(CLK),
.CEA(CEA), .RSTA(RSTA),
.CEB(CEB), .RSTB(RSTB),
.CEC(CEC), .RSTC(RSTC),
.CEPIPE(CEPIPE), .RSTPIPE(RSTPIPE),
.CECTRL(CECTRL), .RSTCTRL(RSTCTRL),
.CECIN(CECIN), .RSTCIN(RSTCIN),
.CIN(CIN), .LOADC(LOADC), .ADDSUB(ADDSUB),
.SIGNEDA(SIGNED), .SIGNEDB(SIGNED), .SIGNEDC(SIGNED),
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
.Z(Z)
);
endmodule
module MULTADDSUB36X36 #(
parameter REGINPUTA = "REGISTER",
parameter REGINPUTB = "REGISTER",
parameter REGINPUTC = "REGISTER",
parameter REGADDSUB = "REGISTER",
parameter REGLOADC = "REGISTER",
parameter REGLOADC2 = "REGISTER",
parameter REGCIN = "REGISTER",
parameter REGPIPELINE = "REGISTER",
parameter REGOUTPUT = "REGISTER",
parameter GSR = "ENABLED",
parameter RESETMODE = "SYNC"
) (
input [35:0] A,
input [35:0] B,
input [107:0] C,
input CLK,
input CEA,
input RSTA,
input CEB,
input RSTB,
input CEC,
input RSTC,
input SIGNED,
input RSTPIPE,
input CEPIPE,
input RSTCTRL,
input CECTRL,
input RSTCIN,
input CECIN,
input LOADC,
input ADDSUB,
output [107:0] Z,
input RSTOUT,
input CEOUT,
input CIN
);
OXIDE_DSP_SIM #(
.REGINPUTA(REGINPUTA),
.REGINPUTB(REGINPUTB),
.REGINPUTC(REGINPUTC),
.REGADDSUB(REGADDSUB),
.REGLOADC(REGLOADC),
.REGLOADC2(REGLOADC2),
.REGCIN(REGCIN),
.REGPIPELINE(REGPIPELINE),
.REGOUTPUT(REGOUTPUT),
.GSR(GSR),
.RESETMODE(RESETMODE),
.A_WIDTH(36),
.B_WIDTH(36),
.C_WIDTH(108),
.Z_WIDTH(108),
.PREADD_USED(0),
.ADDSUB_USED(1)
) dsp_i (
.A(A), .B(B), .C(C),
.CLK(CLK),
.CEA(CEA), .RSTA(RSTA),
.CEB(CEB), .RSTB(RSTB),
.CEC(CEC), .RSTC(RSTC),
.CEPIPE(CEPIPE), .RSTPIPE(RSTPIPE),
.CECTRL(CECTRL), .RSTCTRL(RSTCTRL),
.CECIN(CECIN), .RSTCIN(RSTCIN),
.CIN(CIN), .LOADC(LOADC), .ADDSUB(ADDSUB),
.SIGNEDA(SIGNED), .SIGNEDB(SIGNED), .SIGNEDC(SIGNED),
.RSTOUT(RSTOUT), .CEOUT(CEOUT),
.Z(Z)
);
endmodule
|
`timescale 1ns/1ns
module arb_test();
reg clk, reset_n, wreq, fifo_full;
reg [7:0] memadrs, memdata;
wire [7:0] synth_ctrl, synth_data;
reg [7:0] test_state;
reg [7:0] wait_cnt;
synth_arb arb1(
.clk(clk),
.reset_n(reset_n),
.memadrs(memadrs),
.memdata(memdata),
.wreq(wreq),
.synth_ctrl(synth_ctrl),
.synth_data(synth_data),
.fifo_full(fifo_full));
parameter CLOCK = 10;
initial clk <= 0;
always #(CLOCK / 2) clk <= ~clk;
initial test_state <= 0;
initial reset_n <= 1;
initial wreq <= 0;
initial fifo_full <= 0;
initial memadrs <= 0;
initial memdata <= 0;
initial wait_cnt <= 0;
always @(posedge clk)
begin
case(test_state)
8'D0 : test_state <= test_state + 1;
8'D1 : begin
test_state <= test_state + 1;
reset_n <= 0;
end
8'D2 : begin
test_state <= test_state + 1;
reset_n <= 1;
end
8'D3 : begin //Normal Operation
if(wait_cnt != 8'b11111111)
begin
wait_cnt <= wait_cnt + 1;
end
else
begin
wait_cnt <= 0;
test_state <= test_state + 1;
end
end
8'D4 : begin //FIFO Full Operation Test
if(wait_cnt != 8'b00001111)
begin
wait_cnt <= wait_cnt + 1;
fifo_full <= 1;
end
else
begin
wait_cnt <= 0;
fifo_full <= 0;
test_state <= test_state + 1;
end
end
8'D5 : begin //Frequency Register Write Operation 1
if(wait_cnt != 8'b00001111)
begin
memadrs <= 8'h01;
memdata <= 8'h08;
wreq <= 1;
wait_cnt <= wait_cnt + 1;
test_state <= test_state;
end
else
begin
memadrs <= 8'h00;
memdata <= 8'h00;
wreq <= 0;
test_state <= test_state + 1;
wait_cnt <= 0;
end
end
8'D6 : begin
wreq <= 0;
test_state <= test_state + 1;
end
8'D7 : begin //Frequency Register Write Operation 2
if(wait_cnt != 8'b00001111)
begin
memadrs <= 8'h11;
memdata <= 8'h0A;
wreq <= 1;
wait_cnt <= wait_cnt + 1;
test_state <= test_state;
end
else
begin
memadrs <= 8'h00;
memdata <= 8'h00;
wreq <= 0;
test_state <= test_state + 1;
wait_cnt <= 0;
end
end
8'D8 : begin
wreq <= 0;
test_state <= test_state + 1;
end
8'D9 : test_state <= test_state;
default : test_state <= 0;
endcase
end
endmodule |
// a barrel shifter to satisfy the single clock cycle constraint
// and yet support the multibit shift operation
// @requires: A 32-bit data input, a 32-bit control input;
// @returns: A 32-bit left shifted output to support shift by 7
module shiftll (busSLL, busA, sel, zSLL, oSLL, cSLL, nSLL);
output [31:0] busSLL;
input [31:0] busA, sel;
output zSLL, nSLL;
output reg oSLL, cSLL;
assign busSLL = busA << sel[2:0];
assign zSLL = ~|busSLL[31:0];
assign nSLL = busSLL[31];
always @(*) begin
if (sel[2:0] == 3'b0) begin
cSLL = 1'b0;
oSLL = 1'b0;
end else if (sel[2:0] == 3'b1) begin
cSLL = busSLL[31];
oSLL = busSLL[31];
end else if (sel[2:0] == 3'b10) begin
cSLL = busSLL[30];
oSLL = |busSLL[31:30];
end else if (sel[2:0] == 3'b11) begin
cSLL = busSLL[29];
oSLL = |busSLL[31:29];
end else if (sel[2:0] == 3'b100) begin
cSLL = busSLL[28];
oSLL = |busSLL[31:28];
end else if (sel[2:0] == 3'b101) begin
cSLL = busSLL[27];
oSLL = |busSLL[31:27];
end else if (sel[2:0] == 3'b110) begin
cSLL = busSLL[26];
oSLL = |busSLL[31:26];
end else begin
cSLL = busSLL[25];
oSLL = |busSLL[31:25];
end
end
endmodule |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: player1.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module player1 (
address,
clock,
q);
input [10:0] address;
input clock;
output [2:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [2:0] sub_wire0;
wire [2:0] q = sub_wire0[2:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({3{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "player1.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1190,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 3,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "player1.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1190"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "3"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "player1.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1190"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 3 0 @q_a 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL player1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL player1_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32A_1_V
`define SKY130_FD_SC_MS__O32A_1_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o32a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o32a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o32a_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o32a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32A_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRBP_2_V
`define SKY130_FD_SC_MS__SDFRBP_2_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfrbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRBP_2_V
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
(** printing [+] %\ensuremath+% #+# *)
(** printing {+} %\ensuremath+% #+# *)
Require Export CoRN.algebra.CSetoidInc.
(* Begin_SpecReals *)
(**
* Semigroups
** Definition of the notion of semigroup
*)
Definition is_CSemiGroup A (op : CSetoid_bin_op A) := associative op.
Record CSemiGroup : Type :=
{csg_crr :> CSetoid;
csg_op : CSetoid_bin_op csg_crr;
csg_proof : is_CSemiGroup csg_crr csg_op}.
(**
%\begin{nameconvention}%
In the %{\em %names%}% of lemmas, we will denote [[+]] with [plus].
%\end{nameconvention}%
*)
Arguments csg_op {c}.
Infix "[+]" := csg_op (at level 50, left associativity).
(* End_SpecReals *)
(**
** Semigroup axioms
The axiomatic properties of a semi group.
%\begin{convention}% Let [G] be a semi-group.
%\end{convention}%
*)
Section CSemiGroup_axioms.
Variable G : CSemiGroup.
Lemma CSemiGroup_is_CSemiGroup : is_CSemiGroup G csg_op.
Proof.
elim G; auto.
Qed.
Lemma plus_assoc : associative (csg_op (c:=G)).
Proof.
exact CSemiGroup_is_CSemiGroup.
Qed.
End CSemiGroup_axioms.
(* Begin_SpecReals *)
(**
** Semigroup basics
%\begin{convention}%
Let [G] be a semi-group.
%\end{convention}%
*)
Section CSemiGroup_basics.
Variable G : CSemiGroup.
(* End_SpecReals *)
Lemma plus_assoc_unfolded : forall (G : CSemiGroup) (x y z : G), x[+] (y[+]z) [=] x[+]y[+]z.
Proof.
exact plus_assoc.
Qed.
End CSemiGroup_basics.
Section p71R1.
(**
** Morphism
%\begin{convention}%
Let [S1 S2:CSemiGroup].
%\end{convention}%
*)
Variable S1:CSemiGroup.
Variable S2:CSemiGroup.
Definition morphism_of_CSemiGroups (f:(CSetoid_fun S1 S2)):CProp:=
forall (a b:S1), (f (a[+]b))[=] (f a)[+](f b).
End p71R1.
(**
** About the unit
*)
Definition is_rht_unit S (op : CSetoid_bin_op S) Zero : Prop := forall x, op x Zero [=] x.
(* End_SpecReals *)
Definition is_lft_unit S (op : CSetoid_bin_op S) Zero : Prop := forall x, op Zero x [=] x.
Arguments is_lft_unit [S].
(* Begin_SpecReals *)
Arguments is_rht_unit [S].
(** An alternative definition:
*)
Definition is_unit (S:CSemiGroup): S -> Prop :=
fun e => forall (a:S), e[+]a [=] a /\ a[+]e [=]a.
Lemma cs_unique_unit : forall (S:CSemiGroup) (e f:S),
(is_unit S e) /\ (is_unit S f) -> e[=]f.
Proof.
intros S e f.
unfold is_unit.
intros H.
elim H.
clear H.
intros H0 H1.
elim (H0 f).
clear H0.
intros H2 H3.
elim (H1 e).
clear H1.
intros H4 H5.
astepr (e[+]f).
astepl (e[+]f).
apply eq_reflexive.
Qed.
(* End_SpecReals *)
Hint Resolve plus_assoc_unfolded: algebra.
(**
** Functional operations
We can also define a similar addition operator, which will be denoted by [{+}], on partial functions.
%\begin{convention}% Whenever possible, we will denote the functional construction corresponding to an algebraic operation by the same symbol enclosed in curly braces.
%\end{convention}%
At this stage, we will always consider automorphisms; we %{\em %could%}% treat this in a more general setting, but we feel that it wouldn't really be a useful effort.
%\begin{convention}% Let [G:CSemiGroup] and [F,F':(PartFunct G)] and denote by [P] and [Q], respectively, the predicates characterizing their domains.
%\end{convention}%
*)
Section Part_Function_Plus.
Variable G : CSemiGroup.
Variables F F' : PartFunct G.
(* begin hide *)
Let P := Dom F.
Let Q := Dom F'.
(* end hide *)
Lemma part_function_plus_strext : forall x y (Hx : Conj P Q x) (Hy : Conj P Q y),
F x (Prj1 Hx) [+]F' x (Prj2 Hx) [#] F y (Prj1 Hy) [+]F' y (Prj2 Hy) -> x [#] y.
Proof.
intros x y Hx Hy H.
case (cs_bin_op_strext _ _ _ _ _ _ H); intros H1; exact (pfstrx _ _ _ _ _ _ H1).
Qed.
Definition Fplus := Build_PartFunct G _ (conj_wd (dom_wd _ F) (dom_wd _ F'))
(fun x Hx => F x (Prj1 Hx) [+]F' x (Prj2 Hx)) part_function_plus_strext.
(**
%\begin{convention}% Let [R:G->CProp].
%\end{convention}%
*)
Variable R : G -> CProp.
Lemma included_FPlus : included R P -> included R Q -> included R (Dom Fplus).
Proof.
intros; simpl in |- *; apply included_conj; assumption.
Qed.
Lemma included_FPlus' : included R (Dom Fplus) -> included R P.
Proof.
intro H; simpl in H; eapply included_conj_lft; apply H.
Qed.
Lemma included_FPlus'' : included R (Dom Fplus) -> included R Q.
Proof.
intro H; simpl in H; eapply included_conj_rht; apply H.
Qed.
End Part_Function_Plus.
Arguments Fplus [G].
Infix "{+}" := Fplus (at level 50, left associativity).
Hint Resolve included_FPlus : included.
Hint Immediate included_FPlus' included_FPlus'' : included.
(**
** Subsemigroups
%\begin{convention}%
Let [csg] a semi-group and [P] a non-empty
predicate on the semi-group which is preserved by [[+]].
%\end{convention}%
*)
Section SubCSemiGroups.
Variable csg : CSemiGroup.
Variable P : csg -> CProp.
Variable op_pres_P : bin_op_pres_pred _ P csg_op.
Let subcrr : CSetoid := Build_SubCSetoid _ P.
Definition Build_SubCSemiGroup : CSemiGroup := Build_CSemiGroup
subcrr (Build_SubCSetoid_bin_op _ _ _ op_pres_P)
(restr_f_assoc _ _ _ op_pres_P (plus_assoc csg)).
End SubCSemiGroups.
Section D9S.
(**
** Direct Product
%\begin{convention}%
Let [M1 M2:CSemiGroup]
%\end{convention}%
*)
Variable M1 M2: CSemiGroup.
Definition dprod (x:ProdCSetoid M1 M2)(y:ProdCSetoid M1 M2):
(ProdCSetoid M1 M2):=
let (x1, x2):= x in
let (y1, y2):= y in
(pairT (x1[+]y1) (x2 [+] y2)).
Lemma dprod_strext:(bin_fun_strext (ProdCSetoid M1 M2)(ProdCSetoid M1 M2)
(ProdCSetoid M1 M2)dprod).
Proof.
unfold bin_fun_strext.
intros x1 x2 y1 y2.
unfold dprod.
case x1.
intros a1 a2.
case x2.
intros b1 b2.
case y1.
intros c1 c2.
case y2.
intros d1 d2.
simpl.
intro H.
elim H.
clear H.
intro H.
cut (a1[#]b1 or c1[#]d1).
intuition.
set (H0:= (@csg_op M1)).
unfold CSetoid_bin_op in H0.
set (H1:= (@csbf_strext M1 M1 M1 H0)).
unfold bin_fun_strext in H1.
apply H1.
exact H.
clear H.
intro H.
cut (a2[#]b2 or c2[#]d2).
intuition.
set (H0:= (@csg_op M2)).
unfold CSetoid_bin_op in H0.
set (H1:= (@csbf_strext M2 M2 M2 H0)).
unfold bin_fun_strext in H1.
apply H1.
exact H.
Qed.
Definition dprod_as_csb_fun:
CSetoid_bin_fun (ProdCSetoid M1 M2) (ProdCSetoid M1 M2)(ProdCSetoid M1 M2):=
(Build_CSetoid_bin_fun (ProdCSetoid M1 M2)(ProdCSetoid M1 M2)
(ProdCSetoid M1 M2) dprod dprod_strext).
Lemma direct_product_is_CSemiGroup:
(is_CSemiGroup (ProdCSetoid M1 M2) dprod_as_csb_fun).
Proof.
unfold is_CSemiGroup.
unfold associative.
intros x y z.
case x.
intros x1 x2.
case y.
intros y1 y2.
case z.
intros z1 z2.
simpl.
split.
apply CSemiGroup_is_CSemiGroup.
apply CSemiGroup_is_CSemiGroup.
Qed.
Definition direct_product_as_CSemiGroup:=
(Build_CSemiGroup (ProdCSetoid M1 M2) dprod_as_csb_fun
direct_product_is_CSemiGroup).
End D9S.
(**
** The SemiGroup of Setoid functions
*)
Lemma FS_is_CSemiGroup:
forall (X:CSetoid),(is_CSemiGroup (FS_as_CSetoid X X) (comp_as_bin_op X )).
Proof.
unfold is_CSemiGroup.
exact assoc_comp.
Qed.
Definition FS_as_CSemiGroup (A : CSetoid) :=
Build_CSemiGroup (FS_as_CSetoid A A) (comp_as_bin_op A) (assoc_comp A).
Section p66E2b4.
(**
** The Free SemiGroup
%\begin{convention}% Let [A:CSetoid].
%\end{convention}%
*)
Variable A:CSetoid.
Lemma Astar_is_CSemiGroup:
(is_CSemiGroup (free_csetoid_as_csetoid A) (app_as_csb_fun A)).
Proof.
unfold is_CSemiGroup.
unfold associative.
intros x.
unfold app_as_csb_fun.
simpl.
induction x.
simpl.
intros x y.
apply eq_fm_reflexive.
simpl.
intuition.
Qed.
Definition Astar_as_CSemiGroup:=
(Build_CSemiGroup (free_csetoid_as_csetoid A) (app_as_csb_fun A)
Astar_is_CSemiGroup).
End p66E2b4.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SEDFXBP_BEHAVIORAL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXBP_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SDFSTP_BEHAVIORAL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_SYMBOL_V
`define SKY130_FD_SC_HS__DLXBN_SYMBOL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22OI_TB_V
`define SKY130_FD_SC_HD__A22OI_TB_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a22oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hd__a22oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22OI_TB_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_register_slice #(
parameter DATA_WIDTH = 32,
parameter FORWARD_REGISTERED = 0,
parameter BACKWARD_REGISTERED = 0)(
input clk,
input resetn,
input s_axi_valid,
output s_axi_ready,
input [DATA_WIDTH-1:0] s_axi_data,
output m_axi_valid,
input m_axi_ready,
output [DATA_WIDTH-1:0] m_axi_data
);
/*
s_axi_data -> bwd_data -> fwd_data(1) -> m_axi_data
s_axi_valid -> bwd_valid -> fwd_valid(1) -> m_axi_valid
s_axi_ready <- bwd_ready(2) <- fwd_ready <- m_axi_ready
(1) FORWARD_REGISTERED inserts a set of FF before m_axi_data and m_axi_valid
(2) BACKWARD_REGISTERED insters a FF before s_axi_ready
*/
wire [DATA_WIDTH-1:0] bwd_data_s;
wire bwd_valid_s;
wire bwd_ready_s;
wire [DATA_WIDTH-1:0] fwd_data_s;
wire fwd_valid_s;
wire fwd_ready_s;
generate if (FORWARD_REGISTERED == 1) begin
reg fwd_valid = 1'b0;
reg [DATA_WIDTH-1:0] fwd_data = 'h00;
assign fwd_ready_s = ~fwd_valid | m_axi_ready;
assign fwd_valid_s = fwd_valid;
assign fwd_data_s = fwd_data;
always @(posedge clk) begin
if (~fwd_valid | m_axi_ready)
fwd_data <= bwd_data_s;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
fwd_valid <= 1'b0;
end else begin
if (bwd_valid_s)
fwd_valid <= 1'b1;
else if (m_axi_ready)
fwd_valid <= 1'b0;
end
end
end else begin
assign fwd_data_s = bwd_data_s;
assign fwd_valid_s = bwd_valid_s;
assign fwd_ready_s = m_axi_ready;
end
endgenerate
generate if (BACKWARD_REGISTERED == 1) begin
reg bwd_ready = 1'b1;
reg [DATA_WIDTH-1:0] bwd_data = 'h00;
assign bwd_valid_s = ~bwd_ready | s_axi_valid;
assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
assign bwd_ready_s = bwd_ready;
always @(posedge clk) begin
if (bwd_ready)
bwd_data <= s_axi_data;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
bwd_ready <= 1'b1;
end else begin
if (fwd_ready_s)
bwd_ready <= 1'b1;
else if (s_axi_valid)
bwd_ready <= 1'b0;
end
end
end else begin
assign bwd_valid_s = s_axi_valid;
assign bwd_data_s = s_axi_data;
assign bwd_ready_s = fwd_ready_s;
end endgenerate
assign m_axi_data = fwd_data_s;
assign m_axi_valid = fwd_valid_s;
assign s_axi_ready = bwd_ready_s;
endmodule
|
// ================================================================================
// Legal Notice: Copyright (C) 1991-2008 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
// ================================================================================
//
`timescale 1ns / 1ps
module lpf_tb;
// inputs
reg clk;
reg reset_n;
wire clken;
reg[31:0] in_data;
wire[31:0] out_data;
wire[1:0] in_error;
wire[1:0] out_error;
reg in_valid;
wire out_ready;
wire in_ready;
wire out_valid;
reg start;
reg end_test;
integer data_in_int,data_file_in,data_file_out;
integer data_out_int;
parameter MAXVAL_c = 2147483648;
parameter OFFSET_c = 4294967295;
initial
begin
data_file_in = $fopen("lpf_tb_input.txt","r");
data_file_out = $fopen("lpf_tb_output.txt");
///////////////////////////////////////////////////////////////////////////////////////////////
// Reset Generation
#0 clk = 1'b0;
#0 reset_n = 1'b0;
#92 reset_n = 1'b1;
end
///////////////////////////////////////////////////////////////////////////////////////////////
// Clock Generation
///////////////////////////////////////////////////////////////////////////////////////////////
always
begin
if (end_test == 1'b1)
begin
clk = 1'b0;
$fclose(data_file_in);
$fclose(data_file_out);
$finish; //stop
end
else
begin
#5 clk = 1'b1;
#5 clk = 1'b0;
end
end
// clock enable
// always enabled
assign clken = 1'b1;
// for example purposes, the ready wire is always asserted.
assign out_ready = 1'b1;
// no input error
assign in_error = 2'b0;
// start valid for first cycle to indicate that the file reading should start.
always @ (posedge clk)
begin
if (reset_n == 1'b0)
start <= 1'b1;
else
begin
if (in_valid == 1'b1 & in_ready == 1'b1)
start <= 1'b0;
end
end
//////////////////////////////////////////////////////////////////////////////////////////////
// Read input data from files
//////////////////////////////////////////////////////////////////////////////////////////////
integer c_x;
always @ (posedge clk)
begin
if (reset_n == 1'b0)
begin
in_data <= 32'b0;
in_valid <= 1'b0;
end_test <= 1'b0;
end
else
begin
if (!$feof(data_file_in))
begin
if ((in_valid == 1'b1 & in_ready == 1'b1) ||
(start == 1'b1 & !(in_valid == 1'b1 & in_ready == 1'b0)))
begin
c_x = $fscanf(data_file_in,"%d",data_in_int);
in_data <= data_in_int;
in_valid <= 1'b1;
end
end
else
begin
if (end_test == 1'b0)
begin
if (in_valid == 1'b1 & in_ready == 1'b1)
begin
end_test <= 1'b1;
in_valid <= 1'b0;
in_data <= 32'b0;
end
else
begin
in_valid <= 1'b1;
in_data <= data_in_int;
end
end
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////
// Write data output to Files
////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge clk)
begin
if (reset_n == 1'b1 & out_valid == 1'b1 & out_ready == 1'b1)
begin
data_out_int = out_data;
$fdisplay(data_file_out, "%d", (data_out_int < MAXVAL_c) ? data_out_int : data_out_int - OFFSET_c - 1);
end
end
////////////////////////////////////////////////////////////////////////////////////////////
// CIC Module Instantiation
////////////////////////////////////////////////////////////////////////////////////////////
lpf lpf_inst (
.clk(clk),
.clken(clken),
.reset_n(reset_n),
.in_ready(in_ready),
.in_valid(in_valid),
.in_data(in_data),
.out_data(out_data),
.in_error(in_error),
.out_error(out_error),
.out_ready(out_ready),
.out_valid(out_valid)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_1_V
`define SKY130_FD_SC_LP__OR4_1_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_1 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4_1 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_1_V
|
module control (
input [5:0] op,
output [1:0] alu_op,
output regDst, aluSrc, memToReg, regWrite,
output memRead, memWrite, branch
);
wire int0, op0_bar, op1_bar, op2_bar, op3_bar, op4_bar, op5_bar;
not (op0_bar, op[0]);
not (op1_bar, op[1]);
not (op2_bar, op[2]);
not (op3_bar, op[3]);
not (op4_bar, op[4]);
not (op5_bar, op[5]);
and (alu_op[0], op5_bar, op4_bar, op3_bar, op[2] , op1_bar, op0_bar);
and (alu_op[1], op5_bar, op4_bar, op3_bar, op2_bar, op1_bar, op0_bar);
and (regDst , op5_bar, op4_bar, op3_bar, op2_bar, op1_bar, op0_bar);
and (memToReg , op[5] , op4_bar, op3_bar, op2_bar, op[1] , op[0] );
and (memRead , op[5] , op4_bar, op3_bar, op2_bar, op[1] , op[0] );
and (memWrite , op[5] , op4_bar, op[3] , op2_bar, op[1] , op[0] );
and (branch , op5_bar, op4_bar, op3_bar, op[2] , op1_bar, op0_bar);
and (int0 , op[5] , op4_bar, op3_bar, op2_bar, op[1] , op[0] );
and (aluSrc , op[5] , op4_bar, op2_bar, op[1] , op[0] );
or (regWrite , int0 , alu_op[1]);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2_BEHAVIORAL_V
`define SKY130_FD_SC_MS__OR2_BEHAVIORAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2_BEHAVIORAL_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:56:16 2016
/////////////////////////////////////////////////////////////
module RCA_N20 ( in1, in2, res );
input [19:0] in1;
input [19:0] in2;
output [20:0] res;
wire n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72,
n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86,
n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128;
OAI21X2TS U2 ( .A0(n104), .A1(n100), .B0(n101), .Y(n108) );
OAI21XLTS U3 ( .A0(n77), .A1(n73), .B0(n78), .Y(n8) );
OAI21X2TS U4 ( .A0(n38), .A1(n7), .B0(n6), .Y(n22) );
OAI21XLTS U5 ( .A0(n37), .A1(n33), .B0(n34), .Y(n32) );
OAI21XLTS U6 ( .A0(n126), .A1(n122), .B0(n123), .Y(n56) );
OAI21X1TS U7 ( .A0(n21), .A1(n20), .B0(n19), .Y(res[20]) );
XOR2X1TS U8 ( .A(n86), .B(n26), .Y(res[12]) );
XOR2X1TS U9 ( .A(n99), .B(n98), .Y(res[13]) );
XOR2X1TS U10 ( .A(n81), .B(n80), .Y(res[11]) );
XOR2X1TS U11 ( .A(n113), .B(n112), .Y(res[17]) );
XOR2X1TS U12 ( .A(n126), .B(n125), .Y(res[6]) );
XOR2XLTS U13 ( .A(n70), .B(n58), .Y(res[8]) );
XOR2XLTS U14 ( .A(n48), .B(n47), .Y(res[5]) );
XOR2XLTS U15 ( .A(n104), .B(n103), .Y(res[15]) );
OAI21X1TS U16 ( .A0(n70), .A1(n60), .B0(n59), .Y(n65) );
XOR2XLTS U17 ( .A(n37), .B(n36), .Y(res[2]) );
NOR2X1TS U18 ( .A(n24), .B(n12), .Y(n14) );
XOR2XLTS U19 ( .A(n121), .B(n127), .Y(res[1]) );
OAI21X1TS U20 ( .A0(n52), .A1(n123), .B0(n53), .Y(n4) );
OR2X2TS U21 ( .A(in1[18]), .B(in2[18]), .Y(n115) );
OR2X2TS U22 ( .A(in1[14]), .B(in2[14]), .Y(n88) );
OR2X2TS U23 ( .A(in1[16]), .B(in2[16]), .Y(n106) );
NAND2X2TS U24 ( .A(in1[8]), .B(in2[8]), .Y(n59) );
AOI21X4TS U25 ( .A0(n22), .A1(n14), .B0(n13), .Y(n104) );
OAI21X4TS U26 ( .A0(n113), .A1(n109), .B0(n110), .Y(n117) );
AOI21X4TS U27 ( .A0(n108), .A1(n106), .B0(n15), .Y(n113) );
OAI21X1TS U28 ( .A0(n23), .A1(n12), .B0(n11), .Y(n13) );
NOR2X1TS U29 ( .A(in1[4]), .B(in2[4]), .Y(n39) );
NOR2X2TS U30 ( .A(in1[11]), .B(in2[11]), .Y(n77) );
INVX2TS U31 ( .A(n71), .Y(n75) );
INVX2TS U32 ( .A(n66), .Y(n69) );
INVX2TS U33 ( .A(n67), .Y(n68) );
INVX2TS U34 ( .A(n25), .Y(n93) );
INVX2TS U35 ( .A(n91), .Y(n92) );
INVX2TS U36 ( .A(n83), .Y(n84) );
INVX2TS U37 ( .A(n105), .Y(n15) );
AOI21X1TS U38 ( .A0(n117), .A1(n115), .B0(n16), .Y(n21) );
INVX2TS U39 ( .A(n114), .Y(n16) );
INVX2TS U40 ( .A(n41), .Y(n42) );
INVX2TS U41 ( .A(n33), .Y(n35) );
NAND2X1TS U42 ( .A(n30), .B(n29), .Y(n31) );
INVX2TS U43 ( .A(n28), .Y(n30) );
NAND2X1TS U44 ( .A(n43), .B(n41), .Y(n40) );
INVX2TS U45 ( .A(n122), .Y(n124) );
INVX2TS U46 ( .A(n60), .Y(n57) );
NAND2X1TS U47 ( .A(n63), .B(n62), .Y(n64) );
INVX2TS U48 ( .A(n77), .Y(n79) );
INVX2TS U49 ( .A(n95), .Y(n97) );
INVX2TS U50 ( .A(n82), .Y(n85) );
INVX2TS U51 ( .A(n100), .Y(n102) );
INVX2TS U52 ( .A(n109), .Y(n111) );
XOR2X1TS U53 ( .A(n21), .B(n18), .Y(res[19]) );
INVX2TS U54 ( .A(n44), .Y(n46) );
OAI21X1TS U55 ( .A0(n44), .A1(n41), .B0(n45), .Y(n49) );
NOR2X2TS U56 ( .A(in1[5]), .B(in2[5]), .Y(n44) );
INVX2TS U57 ( .A(n20), .Y(n17) );
NOR2X1TS U58 ( .A(in1[19]), .B(in2[19]), .Y(n20) );
OAI21X1TS U59 ( .A0(n95), .A1(n91), .B0(n96), .Y(n83) );
NOR2X2TS U60 ( .A(in1[13]), .B(in2[13]), .Y(n95) );
INVX2TS U61 ( .A(n87), .Y(n10) );
OAI21X1TS U62 ( .A0(n61), .A1(n59), .B0(n62), .Y(n67) );
INVX2TS U63 ( .A(n118), .Y(n120) );
INVX2TS U64 ( .A(n73), .Y(n74) );
INVX2TS U65 ( .A(n27), .Y(n37) );
NAND2X1TS U66 ( .A(n54), .B(n53), .Y(n55) );
NOR2X1TS U67 ( .A(in1[1]), .B(in2[1]), .Y(n118) );
NAND2X1TS U68 ( .A(in1[0]), .B(in2[0]), .Y(n127) );
NAND2X1TS U69 ( .A(in1[1]), .B(in2[1]), .Y(n119) );
OAI21X1TS U70 ( .A0(n118), .A1(n127), .B0(n119), .Y(n27) );
NOR2X2TS U71 ( .A(in1[2]), .B(in2[2]), .Y(n33) );
NOR2X2TS U72 ( .A(in1[3]), .B(in2[3]), .Y(n28) );
NOR2X1TS U73 ( .A(n33), .B(n28), .Y(n3) );
NAND2X1TS U74 ( .A(in1[2]), .B(in2[2]), .Y(n34) );
NAND2X1TS U75 ( .A(in1[3]), .B(in2[3]), .Y(n29) );
OAI21X1TS U76 ( .A0(n28), .A1(n34), .B0(n29), .Y(n2) );
AOI21X2TS U77 ( .A0(n27), .A1(n3), .B0(n2), .Y(n38) );
NOR2X1TS U78 ( .A(n39), .B(n44), .Y(n50) );
NOR2X2TS U79 ( .A(in1[6]), .B(in2[6]), .Y(n122) );
NOR2X2TS U80 ( .A(in1[7]), .B(in2[7]), .Y(n52) );
NOR2X1TS U81 ( .A(n122), .B(n52), .Y(n5) );
NAND2X1TS U82 ( .A(n50), .B(n5), .Y(n7) );
NAND2X1TS U83 ( .A(in1[4]), .B(in2[4]), .Y(n41) );
NAND2X1TS U84 ( .A(in1[5]), .B(in2[5]), .Y(n45) );
NAND2X1TS U85 ( .A(in1[6]), .B(in2[6]), .Y(n123) );
NAND2X1TS U86 ( .A(in1[7]), .B(in2[7]), .Y(n53) );
AOI21X1TS U87 ( .A0(n49), .A1(n5), .B0(n4), .Y(n6) );
NOR2X2TS U88 ( .A(in1[8]), .B(in2[8]), .Y(n60) );
NOR2X2TS U89 ( .A(in1[9]), .B(in2[9]), .Y(n61) );
NOR2X1TS U90 ( .A(n60), .B(n61), .Y(n66) );
NOR2X1TS U91 ( .A(in1[10]), .B(in2[10]), .Y(n71) );
NOR2X1TS U92 ( .A(n71), .B(n77), .Y(n9) );
NAND2X1TS U93 ( .A(n66), .B(n9), .Y(n24) );
NOR2X1TS U94 ( .A(in1[12]), .B(in2[12]), .Y(n25) );
NOR2X1TS U95 ( .A(n25), .B(n95), .Y(n82) );
NAND2X1TS U96 ( .A(n82), .B(n88), .Y(n12) );
NAND2X1TS U97 ( .A(in1[9]), .B(in2[9]), .Y(n62) );
NAND2X1TS U98 ( .A(in1[10]), .B(in2[10]), .Y(n73) );
NAND2X1TS U99 ( .A(in1[11]), .B(in2[11]), .Y(n78) );
AOI21X1TS U100 ( .A0(n67), .A1(n9), .B0(n8), .Y(n23) );
NAND2X1TS U101 ( .A(in1[12]), .B(in2[12]), .Y(n91) );
NAND2X1TS U102 ( .A(in1[13]), .B(in2[13]), .Y(n96) );
NAND2X1TS U103 ( .A(in1[14]), .B(in2[14]), .Y(n87) );
AOI21X1TS U104 ( .A0(n83), .A1(n88), .B0(n10), .Y(n11) );
NOR2X1TS U105 ( .A(in1[15]), .B(in2[15]), .Y(n100) );
NAND2X1TS U106 ( .A(in1[15]), .B(in2[15]), .Y(n101) );
NAND2X1TS U107 ( .A(in1[16]), .B(in2[16]), .Y(n105) );
NOR2X1TS U108 ( .A(in1[17]), .B(in2[17]), .Y(n109) );
NAND2X1TS U109 ( .A(in1[17]), .B(in2[17]), .Y(n110) );
NAND2X1TS U110 ( .A(in1[18]), .B(in2[18]), .Y(n114) );
NAND2X1TS U111 ( .A(in1[19]), .B(in2[19]), .Y(n19) );
NAND2X1TS U112 ( .A(n17), .B(n19), .Y(n18) );
INVX2TS U113 ( .A(n22), .Y(n70) );
OAI21X1TS U114 ( .A0(n70), .A1(n24), .B0(n23), .Y(n94) );
INVX2TS U115 ( .A(n94), .Y(n86) );
NAND2X1TS U116 ( .A(n93), .B(n91), .Y(n26) );
XNOR2X1TS U117 ( .A(n32), .B(n31), .Y(res[3]) );
NAND2X1TS U118 ( .A(n35), .B(n34), .Y(n36) );
INVX2TS U119 ( .A(n38), .Y(n51) );
INVX2TS U120 ( .A(n39), .Y(n43) );
XNOR2X1TS U121 ( .A(n51), .B(n40), .Y(res[4]) );
AOI21X1TS U122 ( .A0(n51), .A1(n43), .B0(n42), .Y(n48) );
NAND2X1TS U123 ( .A(n46), .B(n45), .Y(n47) );
AOI21X1TS U124 ( .A0(n51), .A1(n50), .B0(n49), .Y(n126) );
INVX2TS U125 ( .A(n52), .Y(n54) );
XNOR2X1TS U126 ( .A(n56), .B(n55), .Y(res[7]) );
NAND2X1TS U127 ( .A(n57), .B(n59), .Y(n58) );
INVX2TS U128 ( .A(n61), .Y(n63) );
XNOR2X1TS U129 ( .A(n65), .B(n64), .Y(res[9]) );
OAI21X1TS U130 ( .A0(n70), .A1(n69), .B0(n68), .Y(n76) );
NAND2X1TS U131 ( .A(n75), .B(n73), .Y(n72) );
XNOR2X1TS U132 ( .A(n76), .B(n72), .Y(res[10]) );
AOI21X1TS U133 ( .A0(n76), .A1(n75), .B0(n74), .Y(n81) );
NAND2X1TS U134 ( .A(n79), .B(n78), .Y(n80) );
OAI21X1TS U135 ( .A0(n86), .A1(n85), .B0(n84), .Y(n90) );
NAND2X1TS U136 ( .A(n88), .B(n87), .Y(n89) );
XNOR2X1TS U137 ( .A(n90), .B(n89), .Y(res[14]) );
AOI21X1TS U138 ( .A0(n94), .A1(n93), .B0(n92), .Y(n99) );
NAND2X1TS U139 ( .A(n97), .B(n96), .Y(n98) );
NAND2X1TS U140 ( .A(n102), .B(n101), .Y(n103) );
NAND2X1TS U141 ( .A(n106), .B(n105), .Y(n107) );
XNOR2X1TS U142 ( .A(n108), .B(n107), .Y(res[16]) );
NAND2X1TS U143 ( .A(n111), .B(n110), .Y(n112) );
NAND2X1TS U144 ( .A(n115), .B(n114), .Y(n116) );
XNOR2X1TS U145 ( .A(n117), .B(n116), .Y(res[18]) );
NAND2X1TS U146 ( .A(n120), .B(n119), .Y(n121) );
NAND2X1TS U147 ( .A(n124), .B(n123), .Y(n125) );
OR2X1TS U148 ( .A(in1[0]), .B(in2[0]), .Y(n128) );
CLKAND2X2TS U149 ( .A(n128), .B(n127), .Y(res[0]) );
initial $sdf_annotate("RCA_N20_syn.sdf");
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:40:17 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_auto_pc_1_stub.v
// Design : zynq_design_1_auto_pc_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awid[11:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[11:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[11:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[11:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
/********************************************************************
* TEST BENCH FOR PROTECTION CELLS *
********************************************************************
* Laboratory : Robotics and Embedded System Technology
* Engineer : Hanjara Cahya Adhyatma
* Create Date : 12/05/2017
* Project Name : FINAL PROJECT
* Target Devices: TEST BENCH SIM PROTECTION AND FPGA
* Tool versions : VERILOG 2001 RUN ON ICARUS 10
* Description : 日本へかえりますために。。。
* Dependencies : いない
* Revision : 今から
* Additional Comments: いない
********************************************************************
* INCLUDE MODULES *
*******************************************************************/
`include "../module/top.v"
/********************************************************************
* IO DEFINITIONS *
*******************************************************************/
module protection_sim;
reg [3:0] a, b;
wire [7:0] c;
/********************************************************************
* DUMPER MONITOR *
*******************************************************************/
initial
begin
$dumpfile("vcd");
$dumpvars(0, tops);
$monitor($time, " A=%d b=%d a*b=%d",a,b,c);
end
/********************************************************************
* CLOCKING *
*******************************************************************
initial
begin
CLK = 1'b1;
forever #5 CLK = ~CLK;
end
********************************************************************
* RESET *
*******************************************************************
initial
begin
RST = 1'b1;
#5 RST = 1'b0;
end
********************************************************************
* DATAS INJECTION *
*******************************************************************/
initial
begin
a = 3'b000;
#2 a = 3'b001;
#2 a = 3'b010;
#2 a = 3'b011;
#2 a = 3'b100;
end
initial
begin
b = 3'b000;
#2 b = 3'b010;
#2 b = 3'b010;
#2 b = 3'b010;
#2 b = 3'b111;
$finish;
end
/********************************************************************
* MODULE IN TEST *
*******************************************************************/
top tops(a, b, c);
endmodule
|
`include "logfunc.h"
module pfengine_wp (
input clk
,input reset
,input logic pfgtopfe_op_valid
,output logic pfgtopfe_op_retry
,input PF_delta_type pfgtopfe_op_delta
,input PF_weigth_type pfgtopfe_op_w1
,input PF_weigth_type pfgtopfe_op_w2
,input SC_pcsign_type pfgtopfe_op_pcsign
,input SC_laddr_type pfgtopfe_op_laddr
,input SC_sptbr_type pfgtopfe_op_sptbr
,output logic pftodc_req0_valid
,input logic pftodc_req0_retry
,output SC_laddr_type pftodc_req0_laddr
,output SC_sptbr_type pftodc_req0_sptbr
,logic pftodc_req0_l2
,output logic pftodc_req1_valid
,input logic pftodc_req1_retry
,output SC_laddr_type pftodc_req1_laddr
,output SC_sptbr_type pftodc_req1_sptbr
,logic pftodc_req1_l2
`ifdef SC_4PIPE
,output logic pftodc_req2_valid
,input logic pftodc_req2_retry
,output SC_laddr_type pftodc_req2_laddr
,output SC_sptbr_type pftodc_req2_sptbr
,logic pftodc_req2_l2
,output logic pftodc_req3_valid
,input logic pftodc_req3_retry
,output SC_laddr_type pftodc_req3_laddr
,output SC_sptbr_type pftodc_req3_sptbr
,logic pftodc_req3_l2
`endif
//aggregated DC stats output from pfengine
,output logic [`PF_STATBITS-1:0] pf_dcstats_nhitmissd
,output logic [`PF_STATBITS-1:0] pf_dcstats_nhitmissp
,output logic [`PF_STATBITS-1:0] pf_dcstats_nhithit
,output logic [`PF_STATBITS-1:0] pf_dcstats_nmiss
,output logic [`PF_STATBITS-1:0] pf_dcstats_ndrop
,output logic [`PF_STATBITS-1:0] pf_dcstats_nreqs
,output logic [`PF_STATBITS-1:0] pf_dcstats_nsnoops
,output logic [`PF_STATBITS-1:0] pf_dcstats_ndisp
//aggregated L2 stats output from pfengine
,output logic [`PF_STATBITS-1:0] pf_l2stats_nhitmissd
,output logic [`PF_STATBITS-1:0] pf_l2stats_nhitmissp
,output logic [`PF_STATBITS-1:0] pf_l2stats_nhithit
,output logic [`PF_STATBITS-1:0] pf_l2stats_nmiss
,output logic [`PF_STATBITS-1:0] pf_l2stats_ndrop
,output logic [`PF_STATBITS-1:0] pf_l2stats_nreqs
,output logic [`PF_STATBITS-1:0] pf_l2stats_nsnoops
,output logic [`PF_STATBITS-1:0] pf_l2stats_ndisp
//pf0_dcstats from DC to pfengine
,input logic [`PF_STATBITS-1:0] pf0_dcstats_nhitmissd
,input logic [`PF_STATBITS-1:0] pf0_dcstats_nhitmissp
,input logic [`PF_STATBITS-1:0] pf0_dcstats_nhithit
,input logic [`PF_STATBITS-1:0] pf0_dcstats_nmiss
,input logic [`PF_STATBITS-1:0] pf0_dcstats_ndrop
,input logic [`PF_STATBITS-1:0] pf0_dcstats_nreqs
,input logic [`PF_STATBITS-1:0] pf0_dcstats_nsnoops
,input logic [`PF_STATBITS-1:0] pf0_dcstats_ndisp
//pf0_l2stats from L2 to pfengine
,input logic [`PF_STATBITS-1:0] pf0_l2stats_nhitmissd
,input logic [`PF_STATBITS-1:0] pf0_l2stats_nhitmissp
,input logic [`PF_STATBITS-1:0] pf0_l2stats_nhithit
,input logic [`PF_STATBITS-1:0] pf0_l2stats_nmiss
,input logic [`PF_STATBITS-1:0] pf0_l2stats_ndrop
,input logic [`PF_STATBITS-1:0] pf0_l2stats_nreqs
,input logic [`PF_STATBITS-1:0] pf0_l2stats_nsnoops
,input logic [`PF_STATBITS-1:0] pf0_l2stats_ndisp
//pf1_dcstats from DC to pfengine
,input logic [`PF_STATBITS-1:0] pf1_dcstats_nhitmissd
,input logic [`PF_STATBITS-1:0] pf1_dcstats_nhitmissp
,input logic [`PF_STATBITS-1:0] pf1_dcstats_nhithit
,input logic [`PF_STATBITS-1:0] pf1_dcstats_nmiss
,input logic [`PF_STATBITS-1:0] pf1_dcstats_ndrop
,input logic [`PF_STATBITS-1:0] pf1_dcstats_nreqs
,input logic [`PF_STATBITS-1:0] pf1_dcstats_nsnoops
,input logic [`PF_STATBITS-1:0] pf1_dcstats_ndisp
//pf1_l2stats from L2 to pfengine
,input logic [`PF_STATBITS-1:0] pf1_l2stats_nhitmissd
,input logic [`PF_STATBITS-1:0] pf1_l2stats_nhitmissp
,input logic [`PF_STATBITS-1:0] pf1_l2stats_nhithit
,input logic [`PF_STATBITS-1:0] pf1_l2stats_nmiss
,input logic [`PF_STATBITS-1:0] pf1_l2stats_ndrop
,input logic [`PF_STATBITS-1:0] pf1_l2stats_nreqs
,input logic [`PF_STATBITS-1:0] pf1_l2stats_nsnoops
,input logic [`PF_STATBITS-1:0] pf1_l2stats_ndisp
`ifdef SC_4PIPE
//pf2_dcstats from DC to pfengine
,input logic [`PF_STATBITS-1:0] pf2_dcstats_nhitmissd
,input logic [`PF_STATBITS-1:0] pf2_dcstats_nhitmissp
,input logic [`PF_STATBITS-1:0] pf2_dcstats_nhithit
,input logic [`PF_STATBITS-1:0] pf2_dcstats_nmiss
,input logic [`PF_STATBITS-1:0] pf2_dcstats_ndrop
,input logic [`PF_STATBITS-1:0] pf2_dcstats_nreqs
,input logic [`PF_STATBITS-1:0] pf2_dcstats_nsnoops
,input logic [`PF_STATBITS-1:0] pf2_dcstats_ndisp
//pf2_l2stats from L2 to pfengine
,input logic [`PF_STATBITS-1:0] pf2_l2stats_nhitmissd
,input logic [`PF_STATBITS-1:0] pf2_l2stats_nhitmissp
,input logic [`PF_STATBITS-1:0] pf2_l2stats_nhithit
,input logic [`PF_STATBITS-1:0] pf2_l2stats_nmiss
,input logic [`PF_STATBITS-1:0] pf2_l2stats_ndrop
,input logic [`PF_STATBITS-1:0] pf2_l2stats_nreqs
,input logic [`PF_STATBITS-1:0] pf2_l2stats_nsnoops
,input logic [`PF_STATBITS-1:0] pf2_l2stats_ndisp
//pf3_dcstats from DC to pfengine
,input logic [`PF_STATBITS-1:0] pf3_dcstats_nhitmissd
,input logic [`PF_STATBITS-1:0] pf3_dcstats_nhitmissp
,input logic [`PF_STATBITS-1:0] pf3_dcstats_nhithit
,input logic [`PF_STATBITS-1:0] pf3_dcstats_nmiss
,input logic [`PF_STATBITS-1:0] pf3_dcstats_ndrop
,input logic [`PF_STATBITS-1:0] pf3_dcstats_nreqs
,input logic [`PF_STATBITS-1:0] pf3_dcstats_nsnoops
,input logic [`PF_STATBITS-1:0] pf3_dcstats_ndisp
//pf3_l2stats from L2 to pfengine
,input logic [`PF_STATBITS-1:0] pf3_l2stats_nhitmissd
,input logic [`PF_STATBITS-1:0] pf3_l2stats_nhitmissp
,input logic [`PF_STATBITS-1:0] pf3_l2stats_nhithit
,input logic [`PF_STATBITS-1:0] pf3_l2stats_nmiss
,input logic [`PF_STATBITS-1:0] pf3_l2stats_ndrop
,input logic [`PF_STATBITS-1:0] pf3_l2stats_nreqs
,input logic [`PF_STATBITS-1:0] pf3_l2stats_nsnoops
,input logic [`PF_STATBITS-1:0] pf3_l2stats_ndisp
`endif
);
//* verilator lint_off WIDTH */
pfengine
pfe (
.clk (clk)
,.reset (reset)
,.pfgtopfe_op_valid (pfgtopfe_op_valid)
,.pfgtopfe_op_retry (pfgtopfe_op_retry)
,.pfgtopfe_op ({pfgtopfe_op_delta
,pfgtopfe_op_w1
,pfgtopfe_op_w2
,pfgtopfe_op_pcsign
,pfgtopfe_op_laddr
,pfgtopfe_op_sptbr})
,.pftodc_req0_valid (pftodc_req0_valid)
,.pftodc_req0_retry (pftodc_req0_retry)
,.pftodc_req0 ({pftodc_req0_laddr
,pftodc_req0_sptbr
,pftodc_req0_l2})
,.pftodc_req1_valid (pftodc_req1_valid)
,.pftodc_req1_retry (pftodc_req1_retry)
,.pftodc_req1 ({pftodc_req1_laddr
,pftodc_req1_sptbr
,pftodc_req1_l2})
`ifdef SC_4PIPE
,.pftodc_req2_valid (pftodc_req2_valid)
,.pftodc_req2_retry (pftodc_req2_retry)
,.pftodc_req2 ({pftodc_req2_laddr
,pftodc_req2_sptbr
,pftodc_req2_l2})
,.pftodc_req3_valid (pftodc_req3_valid)
,.pftodc_req3_retry (pftodc_req3_retry)
,.pftodc_req3 ({pftodc_req3_laddr
,pftodc_req3_sptbr
,pftodc_req3_l2})
`endif
,.pf_dcstats ({pf_dcstats_nhitmissd
,pf_dcstats_nhitmissp
,pf_dcstats_nhithit
,pf_dcstats_nmiss
,pf_dcstats_ndrop
,pf_dcstats_nreqs
,pf_dcstats_nsnoops
,pf_dcstats_ndisp})
,.pf_l2stats ({pf_l2stats_nhitmissd
,pf_l2stats_nhitmissp
,pf_l2stats_nhithit
,pf_l2stats_nmiss
,pf_l2stats_ndrop
,pf_l2stats_nreqs
,pf_l2stats_nsnoops
,pf_l2stats_ndisp})
,.pf0_dcstats ({pf0_dcstats_nhitmissd
,pf0_dcstats_nhitmissp
,pf0_dcstats_nhithit
,pf0_dcstats_nmiss
,pf0_dcstats_ndrop
,pf0_dcstats_nreqs
,pf0_dcstats_nsnoops
,pf0_dcstats_ndisp})
,.pf0_l2stats ({pf0_l2stats_nhitmissd
,pf0_l2stats_nhitmissp
,pf0_l2stats_nhithit
,pf0_l2stats_nmiss
,pf0_l2stats_ndrop
,pf0_l2stats_nreqs
,pf0_l2stats_nsnoops
,pf0_l2stats_ndisp})
,.pf1_dcstats ({pf1_dcstats_nhitmissd
,pf1_dcstats_nhitmissp
,pf1_dcstats_nhithit
,pf1_dcstats_nmiss
,pf1_dcstats_ndrop
,pf1_dcstats_nreqs
,pf1_dcstats_nsnoops
,pf1_dcstats_ndisp})
,.pf1_l2stats ({pf1_l2stats_nhitmissd
,pf1_l2stats_nhitmissp
,pf1_l2stats_nhithit
,pf1_l2stats_nmiss
,pf1_l2stats_ndrop
,pf1_l2stats_nreqs
,pf1_l2stats_nsnoops
,pf1_l2stats_ndisp})
`ifdef SC_4PIPE
,.pf2_dcstats ({pf2_dcstats_nhitmissd
,pf2_dcstats_nhitmissp
,pf2_dcstats_nhithit
,pf2_dcstats_nmiss
,pf2_dcstats_ndrop
,pf2_dcstats_nreqs
,pf2_dcstats_nsnoops
,pf2_dcstats_ndisp})
,.pf2_l2stats ({pf2_l2stats_nhitmissd
,pf2_l2stats_nhitmissp
,pf2_l2stats_nhithit
,pf2_l2stats_nmiss
,pf2_l2stats_ndrop
,pf2_l2stats_nreqs
,pf2_l2stats_nsnoops
,pf2_l2stats_ndisp})
,.pf3_dcstats ({pf3_dcstats_nhitmissd
,pf3_dcstats_nhitmissp
,pf3_dcstats_nhithit
,pf3_dcstats_nmiss
,pf3_dcstats_ndrop
,pf3_dcstats_nreqs
,pf3_dcstats_nsnoops
,pf3_dcstats_ndisp})
,.pf3_l2stats ({pf3_l2stats_nhitmissd
,pf3_l2stats_nhitmissp
,pf3_l2stats_nhithit
,pf3_l2stats_nmiss
,pf3_l2stats_ndrop
,pf3_l2stats_nreqs
,pf3_l2stats_nsnoops
,pf3_l2stats_ndisp})
`endif
);
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: Dave McCoy ([email protected])
* Description: Phy layer SD host controller for 1 bit SD mode
* When the i_data_en signal goes high the core will read in the
* i_write_flag.
* Writing:
* If high then it will read in the i_data_h2s data until
* it reads i_data_count bytes from the host, each i_data_stb will tell
* the above phy to present a new byte to on the i_data_h2s register.
*
* Reading:
* read the number of bytes on i_data_count. when a new byte is finished
* the new byte will be on o_data_s2h.
*
* To activate a transaction set i_en along with i_write_flag to 1 for write
* or 0 for read, the core will strobe in/out data on it's own, it's
* up to the above layer to make sure there is enough data or space
* available, the maximum space should be 2048 bytes. when a transaction is
* finished the o_finished flag will go high, the controlling core must
* de-assert i_en in order to reset the core to get ready for new
* transactions. This signal will go high for one clock cycle if the host
* de-asserts i_en before a transaction is finished.
*
* clk : sdio_clk
* rst : reset core
* i_en : Enable a data transaction
* i_write_flag : 1 = Write, 0 = Read
* i_data_h2s : Data from host to SD card
* o_data_h2s : Data from SD card to host
* i_data_count : Number of bytes to read/write
* o_data_stb : request or strobe in a byte
* o_crc_err : CRC error occured during read
* o_sd_data_dir : Direction of the data
* i_sd_data : raw data in
* o_sd_data : raw data out
*
* Changes:
* 2015.08.24: Initial commit
*/
//RIGHT NOW WE ARE ALWAYS ENABLED!
`define CRC_COUNT 8
module sd_sd4_phy (
input clk,
input rst,
// input ddr_en, //ALWAYS ENABLED FOR NOW!
input i_en,
input i_write_flag,
output reg o_crc_err, //Detected a CRC error during read
//Debug
output reg [15:0] o_crc0_rmt,
output reg [15:0] o_crc1_rmt,
output reg [15:0] o_crc2_rmt,
output reg [15:0] o_crc3_rmt,
output reg [15:0] o_crc0_gen,
output reg [15:0] o_crc1_gen,
output reg [15:0] o_crc2_gen,
output reg [15:0] o_crc3_gen,
output reg o_data_stb,
input [11:0] i_data_count,
input [7:0] i_data_h2s,
output reg [7:0] o_data_s2h,
output o_sd_data_dir,
input [7:0] i_sd_data,
output [7:0] o_sd_data
);
//local parameters
localparam IDLE = 4'h0;
localparam WRITE = 4'h2;
localparam WRITE_CRC = 4'h3;
localparam WRITE_FINISHED= 4'h4;
localparam READ_START = 4'h5;
localparam READ = 4'h6;
localparam READ_CRC = 4'h7;
localparam FINISHED = 4'h8;
//registes/wires
reg [3:0] state = IDLE;
reg [7:0] sd_data;
wire sd_data_bit;
wire [15:0] gen_crc[0:3];
reg [15:0] crc[0:3];
reg [15:0] prev_crc[0:3];
wire [15:0] crc0;
wire [15:0] crc1;
wire [15:0] crc2;
wire [15:0] crc3;
wire [15:0] prev_crc0;
wire [15:0] prev_crc1;
wire [15:0] prev_crc2;
wire [15:0] prev_crc3;
wire [15:0] gen_crc0;
wire [15:0] gen_crc1;
wire [15:0] gen_crc2;
wire [15:0] gen_crc3;
reg crc_rst;
reg crc_en;
wire sd_clk;
reg posedge_clk;
wire [3:0] crc_bit0;
wire [3:0] crc_bit1;
wire [3:0] crc_bit2;
wire [3:0] crc_bit3;
//wire [7:0] in_remap;
reg [11:0] data_count;
wire writing_active;
reg local_rst;
wire [7:0] crc_data;
initial begin
local_rst <= 1;
end
integer i = 0;
//submodules
//Generate 4 Copies of the CRC, data will be read in and out in parallel
genvar gv;
generate
for (gv = 0; gv < 4; gv = gv + 1) begin: gv_crc
crc16_2bit crc_module(
.clk (clk ),
.rst (crc_rst ),
.en (crc_en ),
.bit1 (crc_data[7 - gv] ),
.bit0 (crc_data[7 - gv - 4] ),
.crc (gen_crc[gv] )
);
end
endgenerate
assign crc_data = i_write_flag ? i_data_h2s : i_sd_data;
//asynchronous logic
assign prev_crc0 = prev_crc[0];
assign prev_crc1 = prev_crc[1];
assign prev_crc2 = prev_crc[2];
assign prev_crc3 = prev_crc[3];
assign crc0 = crc[0];
assign crc1 = crc[1];
assign crc2 = crc[2];
assign crc3 = crc[3];
assign gen_crc0 = gen_crc[0];
assign gen_crc1 = gen_crc[1];
assign gen_crc2 = gen_crc[2];
assign gen_crc3 = gen_crc[3];
assign o_sd_data = sd_data;
assign writing_active = ((state == WRITE) || (state == WRITE_CRC));
assign o_sd_data_dir = writing_active;
//synchronous logic
always @ (posedge clk) begin
//De-assert Strobes
o_data_stb <= 0;
if (rst | local_rst) begin
sd_data <= 0;
state <= IDLE;
crc_rst <= 1;
crc_en <= 0;
data_count <= 0;
o_crc_err <= 0;
o_data_s2h <= 0;
local_rst <= 0;
o_crc0_rmt <= 0;
o_crc1_rmt <= 0;
o_crc2_rmt <= 0;
o_crc3_rmt <= 0;
o_crc0_gen <= 0;
o_crc1_gen <= 0;
o_crc2_gen <= 0;
o_crc3_gen <= 0;
for (i = 0; i < 4; i = i + 1) begin
crc[i] <= 16'h0000;
end
end
else begin
case (state)
IDLE: begin
crc_en <= 0;
crc_rst <= 1;
data_count <= 0;
o_crc_err <= 0;
sd_data <= 8'hFF;
if (i_en) begin
crc_rst <= 0;
if(i_write_flag) begin
state <= WRITE;
sd_data <= 8'h00; //Is this only on the positive edge we need this start bit to be set?
o_data_stb <= 1;
crc_en <= 1;
end
else begin
state <= READ_START;
end
end
end
WRITE: begin
if (data_count < i_data_count - 1) begin
crc_en <= 1;
sd_data <= i_data_h2s;
data_count <= data_count + 1;
o_data_stb <= 1;
end
else begin
sd_data <= i_data_h2s;
data_count <= 0;
state <= WRITE_CRC;
crc_en <= 0;
end
end
WRITE_CRC: begin
if (data_count == 0) begin
o_crc0_gen <= gen_crc[0];
o_crc1_gen <= gen_crc[1];
o_crc2_gen <= gen_crc[2];
o_crc3_gen <= gen_crc[3];
sd_data <= {gen_crc0[15], gen_crc1[15], gen_crc2[15], gen_crc3[15],
gen_crc0[14], gen_crc1[14], gen_crc2[14], gen_crc3[14]};
for (i = 0; i < 4; i = i + 1) begin
crc[i] <= {gen_crc[i][13:0], 2'b0};
end
data_count <= data_count + 1;
//$display("CRC: %X %X %X %X", gen_crc0, gen_crc1, gen_crc2, gen_crc3);
//$display("Bus Value: %X", {gen_crc0[15], gen_crc1[15], gen_crc2[15], gen_crc3[15],
// gen_crc0[14], gen_crc1[14], gen_crc2[14], gen_crc3[14]});
end
else if (data_count <= 8) begin
//$display("SD Data: %X", sd_data);
sd_data <= {crc0[15], crc1[15], crc2[15], crc3[15],
crc0[14], crc1[14], crc2[14], crc3[14]};
for (i = 0; i < 4; i = i + 1) begin
crc[i] <= {crc[i][13:0], 2'b0};
end
data_count <= data_count + 1;
end
else begin
sd_data <= 8'hFF;
state <= WRITE_FINISHED;
end
end
WRITE_FINISHED: begin
//Pass through, assign statement will set the value to 1
state <= FINISHED;
end
READ_START: begin
//Wait for data bit to go low
if (!i_sd_data[0]) begin
state <= READ;
end
end
READ: begin
//Shift the bits in
o_data_s2h <= i_sd_data;
o_data_stb <= 1;
crc_en <= 1;
if (data_count < i_data_count - 1) begin
data_count <= data_count + 1;
end
else begin
//Finished reading all bytes
state <= READ_CRC;
data_count <= 0;
end
end
READ_CRC: begin
crc_en <= 0;
if (data_count < (`CRC_COUNT)) begin
data_count <= data_count + 1;
crc[0] <= {crc[0][13:0], i_sd_data[7], i_sd_data[3]};
crc[1] <= {crc[1][13:0], i_sd_data[6], i_sd_data[2]};
crc[2] <= {crc[2][13:0], i_sd_data[5], i_sd_data[1]};
crc[3] <= {crc[3][13:0], i_sd_data[4], i_sd_data[0]};
end
else begin
state <= FINISHED;
end
end
FINISHED: begin
o_crc0_rmt <= crc[0];
o_crc1_rmt <= crc[1];
o_crc2_rmt <= crc[2];
o_crc3_rmt <= crc[3];
o_crc_err <= !( (crc[0] == gen_crc[0]) &&
(crc[1] == gen_crc[1]) &&
(crc[2] == gen_crc[2]) &&
(crc[3] == gen_crc[3]));
if (!i_en) begin
state <= IDLE;
end
end
default: begin
local_rst <= 1;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s15 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S15_FUNCTIONAL_PP_V |
/* SRAM implementation
*
* Implements an SRAM with each entry holding eight bits and eight entries
* total.
*
* Created By David Tran
* Version 0.1.0.0
* Last Modified:05-01-2014
*/
module SRAM(read, // Specifies if we want to read from the FIFO
write, // Specifies if we want to write form the FIFO
address, // Specifies the address for read/write
dataIn, // The input packet
dataOut, // The output packet
clk // Clock input
);
parameter bits = 8;
parameter depth = 3;
parameter ad_length = 1<<depth;
input read;
input write;
input [depth-1:0] address; //2^depth = address
input [bits-1:0] dataIn;
output [bits-1:0] dataOut;
reg [bits-1:0] dataOut;
input clk;
reg [bits-1:0] memArray [ad_length-1:0];
always @(posedge clk) begin
if(write)
memArray[address] <= dataIn;
if(read)
dataOut <= memArray[address];
if (read & write) begin
$display("ERROR: simultaneous read and write to memory");
dataOut <= {bits{1'bx}};
$stop;
end
end
endmodule
|
`timescale 1ns / 1ps
module PS2_Controller #(parameter INITIALIZE_MOUSE = 0) (
// Inputs
CLOCK_50,
reset,
the_command,
send_command,
// Bidirectionals
PS2_CLK, // PS2 Clock
PS2_DAT, // PS2 Data
// Outputs
command_was_sent,
error_communication_timed_out,
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input reset;
input [7:0] the_command;
input send_command;
// Bidirectionals
inout PS2_CLK;
inout PS2_DAT;
// Outputs
output command_was_sent;
output error_communication_timed_out;
output [7:0] received_data;
output received_data_en;
wire [7:0] the_command_w;
wire send_command_w, command_was_sent_w, error_communication_timed_out_w;
generate
if(INITIALIZE_MOUSE) begin
assign the_command_w = init_done ? the_command : 8'hf4;
assign send_command_w = init_done ? send_command : (!command_was_sent_w && !error_communication_timed_out_w);
assign command_was_sent = init_done ? command_was_sent_w : 0;
assign error_communication_timed_out = init_done ? error_communication_timed_out_w : 1;
reg init_done;
always @(posedge CLOCK_50)
if(reset) init_done <= 0;
else if(command_was_sent_w) init_done <= 1;
end else begin
assign the_command_w = the_command;
assign send_command_w = send_command;
assign command_was_sent = command_was_sent_w;
assign error_communication_timed_out = error_communication_timed_out_w;
end
endgenerate
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire ps2_clk_posedge;
wire ps2_clk_negedge;
wire start_receiving_data;
wire wait_for_incoming_data;
// Internal Registers
reg [7:0] idle_counter;
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
// State Machine Registers
reg [2:0] ns_ps2_transceiver;
reg [2:0] s_ps2_transceiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
s_ps2_transceiver <= PS2_STATE_0_IDLE;
else
s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*)
begin
// Defaults
ns_ps2_transceiver = PS2_STATE_0_IDLE;
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if ((idle_counter == 8'hFF) &&
(send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else
ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
if ((received_data_en == 1'b1)/* && (ps2_clk_posedge == 1'b1)*/)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if ((command_was_sent == 1'b1) ||
(error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if (received_data_en == 1'b1)
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else
begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= PS2_CLK;
ps2_data_reg <= PS2_DAT;
end
end
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
idle_counter <= 6'h00;
else if ((s_ps2_transceiver == PS2_STATE_0_IDLE) &&
(idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign ps2_clk_posedge =
((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge =
((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data =
(s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_PS2_Data_In PS2_Data_In (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
// Bidirectionals
// Outputs
.received_data (received_data),
.received_data_en (received_data_en)
);
Altera_UP_PS2_Command_Out PS2_Command_Out (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.the_command (the_command_w),
.send_command (send_command_w),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
// Bidirectionals
.PS2_CLK (PS2_CLK),
.PS2_DAT (PS2_DAT),
// Outputs
.command_was_sent (command_was_sent_w),
.error_communication_timed_out (error_communication_timed_out_w)
);
endmodule
|
module sim();
reg CLK, RST;
initial CLK = 1'b0;
always #5 CLK = ~CLK; /* 100 MHz */
wire tb_enable;
wire[7:0] tb_wcount;
reg[7:0] tb_word;
reg[7:0] tb_key_length;
reg[7:0] tb_interval;
wire tb_valid;
wire[31:0] tb_hashkey;
wire tb_onloop;
reg[31:0] ROM7[0:6];
reg[31:0] ROM12[0:11];
reg[31:0] ROM15[0:14];
reg[31:0] ROM100[0:99];
reg[31:0] ROM200[0:199];
reg[31:0] ROM250[0:249];
initial begin
$readmemh("test/data/7.hex", ROM7);
$readmemh("test/data/12.hex", ROM12);
$readmemh("test/data/15.hex", ROM15);
$readmemh("test/data/100.hex", ROM100);
$readmemh("test/data/200.hex", ROM200);
$readmemh("test/data/250.hex", ROM250);
end
hash hash
// #(
// parameter maxwords = 250
// )
(
.CLK(CLK)
, .RST(RST)
, .enable(tb_enable)
, .onloop(tb_onloop)
, .wcount(tb_wcount)
, .word(tb_word)
, .key_length(tb_key_length)
, .interval(tb_interval)
, .valid(tb_valid)
, .hashkey(tb_hashkey)
);
task waitaclock;
begin
@(posedge CLK);
#1;
end
endtask
/* TASK: KEY_LENGTH=8'd15 */
task sim_n15;
begin
simstart = 1'b1;
tb_key_length = 8'd15;
tb_interval = 8'b0;
end
endtask
always begin
$dumpfile("hash.vcd");
$dumpvars(0, sim.hash);
RST = 1'b1;
waitaclock;
waitaclock;
waitaclock;
RST = 1'b0;
waitaclock;
sim_n15;
#1000;
$finish;
end
reg simstart = 1'b0;
reg[7:0] count = 8'b0;
always @(posedge CLK) begin
if (simstart) begin
count <= count + 8'b1;
case (tb_key_length)
8'd7: tb_word <= ROM7[count];
8'd12: tb_word <= ROM12[count];
8'd15: tb_word <= ROM15[count];
8'd100: tb_word <= ROM100[count];
8'd200: tb_word <= ROM200[count];
8'd250: tb_word <= ROM250[count];
endcase
end else
count <= 8'b0;
end
assign tb_enable = (tb_word) ? 1'b1 : 1'b0;
assign tb_wcount = (tb_word) ? tb_wcount - 8'b1 : tb_key_length;
assign tb_onloop = (tb_wcount > 8'd12) ? 1'b1 : 1'b0;
endmodule
|
/*
* Wrapper for Xilinx MIG'd DDR2 controller, allowing 3 masters
* to contol the single interface.
*/
module xilinx_ddr2
(
// Inputs
input [31:0] wbm0_adr_i,
input [1:0] wbm0_bte_i,
input [2:0] wbm0_cti_i,
input wbm0_cyc_i,
input [31:0] wbm0_dat_i,
input [3:0] wbm0_sel_i,
input wbm0_stb_i,
input wbm0_we_i,
// Outputs
output wbm0_ack_o,
output wbm0_err_o,
output wbm0_rty_o,
output [31:0] wbm0_dat_o,
// Inputs
input [31:0] wbm1_adr_i,
input [1:0] wbm1_bte_i,
input [2:0] wbm1_cti_i,
input wbm1_cyc_i,
input [31:0] wbm1_dat_i,
input [3:0] wbm1_sel_i,
input wbm1_stb_i,
input wbm1_we_i,
// Outputs
output wbm1_ack_o,
output wbm1_err_o,
output wbm1_rty_o,
output [31:0] wbm1_dat_o,
// Inputs
input [31:0] wbm2_adr_i,
input [1:0] wbm2_bte_i,
input [2:0] wbm2_cti_i,
input wbm2_cyc_i,
input [31:0] wbm2_dat_i,
input [3:0] wbm2_sel_i,
input wbm2_stb_i,
input wbm2_we_i,
// Outputs
output wbm2_ack_o,
output wbm2_err_o,
output wbm2_rty_o,
output [31:0] wbm2_dat_o,
input wb_clk,
input wb_rst,
output [12:0] ddr2_a,
output [1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [1:0] ddr2_cs_n,
output [1:0] ddr2_odt,
output [1:0] ddr2_cke,
output [7:0] ddr2_dm,
inout [63:0] ddr2_dq,
inout [7:0] ddr2_dqs,
inout [7:0] ddr2_dqs_n,
output [1:0] ddr2_ck,
output [1:0] ddr2_ck_n,
input ddr2_if_clk,
input clk200,
input ddr2_if_rst
, input sp_refresh_disable
);
// Internal wires to actual RAM
wire [31:0] wbs_ram_adr_i;
wire [1:0] wbs_ram_bte_i;
wire [2:0] wbs_ram_cti_i;
wire wbs_ram_cyc_i;
wire [31:0] wbs_ram_dat_i;
wire [3:0] wbs_ram_sel_i;
wire wbs_ram_stb_i;
wire wbs_ram_we_i;
wire wbs_ram_ack_o;
wire [31:0] wbs_ram_dat_o;
reg [2:0] input_select, last_selected;
wire arb_for_wbm0, arb_for_wbm1, arb_for_wbm2;
// Wires allowing selection of new input
assign arb_for_wbm0 = (last_selected[1] | last_selected[2] |
!wbm1_cyc_i | !wbm2_cyc_i) & !(|input_select);
assign arb_for_wbm1 = (last_selected[0] | last_selected[2] |
!wbm0_cyc_i | !wbm2_cyc_i) & !(|input_select);
assign arb_for_wbm2 = (last_selected[0] | last_selected[1] |
!wbm0_cyc_i | !wbm1_cyc_i) & !(|input_select);
// Master select logic
always @(posedge wb_clk)
if (wb_rst)
input_select <= 0;
else if ((input_select[0] & !wbm0_cyc_i) | (input_select[1] & !wbm1_cyc_i)
| (input_select[2] & !wbm2_cyc_i))
input_select <= 0;
else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
input_select <= 3'b001;
else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
input_select <= 3'b010;
else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
input_select <= 3'b100;
always @(posedge wb_clk)
if (wb_rst)
last_selected <= 0;
else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
last_selected <= 3'b001;
else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
last_selected <= 3'b010;
else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
last_selected <= 3'b100;
// Mux input signals to RAM (default to wbm0)
assign wbs_ram_adr_i = (input_select[2]) ? wbm2_adr_i :
(input_select[1]) ? wbm1_adr_i :
(input_select[0]) ? wbm0_adr_i : 0;
assign wbs_ram_bte_i = (input_select[2]) ? wbm2_bte_i :
(input_select[1]) ? wbm1_bte_i :
(input_select[0]) ? wbm0_bte_i : 0;
assign wbs_ram_cti_i = (input_select[2]) ? wbm2_cti_i :
(input_select[1]) ? wbm1_cti_i :
(input_select[0]) ? wbm0_cti_i : 0;
assign wbs_ram_cyc_i = (input_select[2]) ? wbm2_cyc_i :
(input_select[1]) ? wbm1_cyc_i :
(input_select[0]) ? wbm0_cyc_i : 0;
assign wbs_ram_dat_i = (input_select[2]) ? wbm2_dat_i :
(input_select[1]) ? wbm1_dat_i :
(input_select[0]) ? wbm0_dat_i : 0;
assign wbs_ram_sel_i = (input_select[2]) ? wbm2_sel_i :
(input_select[1]) ? wbm1_sel_i :
(input_select[0]) ? wbm0_sel_i : 0;
assign wbs_ram_stb_i = (input_select[2]) ? wbm2_stb_i :
(input_select[1]) ? wbm1_stb_i :
(input_select[0]) ? wbm0_stb_i : 0;
assign wbs_ram_we_i = (input_select[2]) ? wbm2_we_i :
(input_select[1]) ? wbm1_we_i :
(input_select[0]) ? wbm0_we_i : 0;
// Output from RAM, gate the ACK, ERR, RTY signals appropriately
assign wbm0_dat_o = wbs_ram_dat_o;
assign wbm0_ack_o = wbs_ram_ack_o & input_select[0];
assign wbm0_err_o = 0;
assign wbm0_rty_o = 0;
assign wbm1_dat_o = wbs_ram_dat_o;
assign wbm1_ack_o = wbs_ram_ack_o & input_select[1];
assign wbm1_err_o = 0;
assign wbm1_rty_o = 0;
assign wbm2_dat_o = wbs_ram_dat_o;
assign wbm2_ack_o = wbs_ram_ack_o & input_select[2];
assign wbm2_err_o = 0;
assign wbm2_rty_o = 0;
xilinx_ddr2_if xilinx_ddr2_if0
(
.wb_dat_o (wbs_ram_dat_o),
.wb_ack_o (wbs_ram_ack_o),
.wb_adr_i (wbs_ram_adr_i[31:0]),
.wb_stb_i (wbs_ram_stb_i),
.wb_cti_i (wbs_ram_cti_i),
.wb_bte_i (wbs_ram_bte_i),
.wb_cyc_i (wbs_ram_cyc_i),
.wb_we_i (wbs_ram_we_i),
.wb_sel_i (wbs_ram_sel_i[3:0]),
.wb_dat_i (wbs_ram_dat_i[31:0]),
.ddr2_a (ddr2_a[12:0]),
.ddr2_ba (ddr2_ba[1:0]),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_odt (ddr2_odt),
.ddr2_cke (ddr2_cke),
.ddr2_dm (ddr2_dm[7:0]),
.ddr2_ck (ddr2_ck[1:0]),
.ddr2_ck_n (ddr2_ck_n[1:0]),
.ddr2_dq (ddr2_dq[63:0]),
.ddr2_dqs (ddr2_dqs[7:0]),
.ddr2_dqs_n (ddr2_dqs_n[7:0]),
.ddr2_if_clk (ddr2_if_clk),
.idly_clk_200 (clk200),
.ddr2_if_rst (ddr2_if_rst),
.wb_clk (wb_clk),
.wb_rst (wb_rst), .sp_refresh_disable(sp_refresh_disable));
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
(*|
Tutorial on the HOAS for Coq terms
**********************************
:author: Enrico Tassi
.. include:: ../etc/tutorial_style.rst
..
Elpi is an extension language that comes as a library
to be embedded into host applications such as Coq.
Elpi is a variant of λProlog enriched with constraints.
λProlog is a programming language designed to make it easy
to manipulate abstract syntax trees containing binders.
Elpi extends λProlog with programming constructs that are
designed to make it easy to manipulate abstract syntax trees
containing metavariables (also called unification variables, or
evars in the Coq jargon).
This software, "coq-elpi", is a Coq plugin embedding Elpi and
exposing to the extension language Coq spefic data types (e.g. terms)
and API (e.g. to declare a new inductive type).
In order to get proper syntax highlighting using VSCode please install the
"gares.coq-elpi-lang" extension. In CoqIDE please chose "coq-elpi" in
Edit -> Preferences -> Colors.
This tutorial focuses on the integration of Elpi within Coq, in particular
it describes how Coq terms are exposed to Elpi programs and how Coq APIs can
be called.
This tutorial assumes the reader is familiar with Elpi and HOAS; if it is not
the case, please take a look at the
`Elpi tutorial <https://lpcic.github.io/coq-elpi/tutorial_elpi_lang.html>`_
first.
.. contents::
================
HOAS for Gallina
================
|*)
From elpi Require Import elpi. (* .none *)
Elpi Command tutorial_HOAS. (* .none *)
(*|
The full syntax of Coq terms can be found in
`coq-builtin.elpi <https://github.com/LPCIC/coq-elpi/blob/master/coq-builtin.elpi>`_
together with a detailed documentation of the encoding of contexts and the
APIs one can use to interact with Coq. This tutorial, and the two more
that focus on commands and tactics, are a gentle introduction to all that.
We defer to later quotations and antiquotations: syntactic features that
let one write terms in Coq's native syntax. Here we focus on the abstract
syntax tree of Coq terms.
-----------------------
Constructor :e:`global`
-----------------------
Let's start with the :type:`gref` data type (for global rerence).
.. code:: elpi
type const constant -> gref.
type indt inductive -> gref.
type indc constructor -> gref.
:type:`constant`, :type:`inductive` and :type:`constructor` are Coq specific
data types that are opaque to Elpi. Still the :type:`gref` data type lets you
see what these names point to (a constant, and inductive type or a
constructor).
The :builtin:`coq.locate` API resolves a string to a :type:`gref`.
|*)
Elpi Query lp:{{
coq.locate "nat" GRnat,
coq.locate "S" GRs,
coq.locate "plus" GRplus
}}.
(*|
The :e:`coq.env.*` family of APIs lets one access the
environment of well typed Coq terms that have a global name.
|*)
Definition x := 2.
Elpi Query lp:{{
coq.locate "x" GR,
% all global references have a type
coq.env.typeof GR Ty,
% destruct GR to obtain its constant part C
GR = const C,
% constants may have a body, do have a type
coq.env.const C (some Bo) TyC
}}.
(*|
An expression like :e:`indt «nat»` is not a Coq term (or better a type) yet.
The :constructor:`global` term constructor turns a :type:`gref` into an
actual :type:`term`.
.. code:: elpi
type global gref -> term.
----------------------------------
Constructors :e:`app` and :e:`fun`
----------------------------------
The :constructor:`app` term constructor takes a list of terms and builds
the (n-ary) application. The first term is the head, while the others
are the arguments.
For example :e:`app [global (indc «S»), global (indc «O»)]` is
the representation of `1`.
.. code:: elpi
type app list term -> term.
Let's move to binders!
|*)
Definition f := fun x : nat => x.
Elpi Query lp:{{
coq.locate "f" (const C),
coq.env.const C (some Bo) _
}}.
(*|
The :constructor:`fun` constructor carries a pretty printing hint ```x```,
the type of the bound variable `nat` and a function describing the body:
.. code:: elpi
type fun name -> term -> (term -> term) -> term.
.. note:: :type:`name` is just for pretty printing: in spite of carrying
a value in the Coq world, it has no content in Elpi (like the unit type)
Elpi terms of type :type:`name` are just identifiers
written between ````` (backticks).
.. coq::
Elpi Query lp:{{
fun `foo` T B = fun `bar` T B % names don't matter
}}.
API such as :builtin:`coq.name-suffix` lets one craft a family of
names starting from one, eg ``coq.name-suffix `H` 1 N`` sets :e:`N`
to ```H1```.
------------------------------------
Constructors :e:`fix` and :e:`match`
------------------------------------
The other binders :constructor:`prod` (Coq's `forall`, AKA `Π`) and :constructor:`let` are similar,
so let's rather focus on :constructor:`fix` here.
|*)
Elpi Query lp:{{
coq.locate "plus" (const C),
coq.env.const C (some Bo) _
}}.
(*|
The :constructor:`fix` constructor carries a pretty printing hint,
the number of the recursive argument (starting at :e:`0`), the type
of the recursive function and finally the body where the recursive
call is represented via a bound variable
.. code:: elpi
type fix name -> int -> term -> (term -> term) -> term.
A :constructor:`match` constructor carries the term being inspected,
the return clause
and a list of branches. Each branch is a Coq function expecting in input
the arguments of the corresponding constructor. The order follows the
order of the constructors in the inductive type declaration.
.. code:: elpi
type match term -> term -> list term -> term.
The return clause is represented as a Coq function expecting in input
the indexes of the inductive type, the inspected term and generating the
type of the branches.
|*)
Definition m (h : 0 = 1 ) P : P 0 -> P 1 :=
match h as e in eq _ x return P 0 -> P x
with eq_refl => fun (p : P 0) => p end.
Elpi Query lp:{{
coq.locate "m" (const C),
coq.env.const C (some (fun _ _ h\ fun _ _ p\ match _ (RT h p) _)) _,
coq.say "The return type of m is:" RT
}}.
(*|
---------------------
Constructor :e:`sort`
---------------------
The last term constructor worth discussing is :constructor:`sort`.
.. code:: elpi
type sort universe -> term.
type prop universe.
type typ univ -> universe.
The opaque type :type:`univ` is a universe level variable. Elpi holds a store of
constraints among these variables and provides APIs named :e:`coq.univ.*` to
impose constraints.
|*)
Elpi Query lp:{{
coq.univ.sup U U1,
coq.say U "<" U1,
% This constraint can't be allowed in the store!
not(coq.univ.leq U1 U)
}}.
(*|
.. note:: the user is not expected to declare universe constraints by hand
The type checking primitives update the store of constraints
automatically and put Coq universe variables in place of Elpi's unification
variables (:e:`U` and :e:`V` below).
Let's play a bit more with universe constraints using the
:builtin:`coq.typecheck` API:
|*)
Elpi Query lp:{{
ID = (fun `x` (sort (typ U)) x\ x),
A = (sort (typ U)), % the same U as before
B = (sort (typ V)),
coq.say "(id b) is:" (app [ID, B]),
% error, since U : U is not valid
coq.typecheck (app [ID, A]) T (error ErrMsg),
coq.say "(id a) is illtyped:" ErrMsg,
% ok, since V : U is possible
coq.typecheck (app [ID, B]) T ok,
% remark: U and V are now Coq's univ with constraints
coq.say "after typing (id b) is:" (app [ID, B]) ":" T,
coq.univ.print
}}.
(*|
The :stdtype:`diagnostic` data type is used by :builtin:`coq.typecheck` to
tell if the term is well typed. The constructor :e:`ok` signals success, while
:e:`error` carries an error message. In case of success universe constraints
are added to the store.
=============================
Quotations and Antiquotations
=============================
Writing Gallina terms as we did so far is surely possible but very verbose
and unhandy. Elpi provides a system of quotations and antiquotations to
let one take advantage of the Coq parser to write terms.
The antiquotation, from Coq to Elpi, is written `lp:{{ ... }}` and we have
been using it since the beginning of the tutorial. The quotation from
Elpi to Coq is written :e:`{{:coq ... }}` or also just :e:`{{ ... }}` since
the `:coq` is the default quotation (Coq has no default quotation, hence you always need
to write `lp:` there).
|*)
Elpi Query lp:{{
% the ":coq" flag is optional
coq.say {{:coq 1 + 2 }} "=" {{ 1 + 2 }}
}}.
(*|
Of course quotations can nest.
|*)
Elpi Query lp:{{
coq.locate "S" S,
coq.say {{ 1 + lp:{{ app[global S, {{ 0 }} ] }} }}
% elpi.... coq.. elpi........... coq elpi coq
}}.
(*|
One rule governs bound variables:
.. important::
if a variable is bound in a language, Coq or Elpi,
then the variable is only visible in that language (not in the other one).
The following example is horrible but proves this point. In real code
you are encouraged to pick appropriate names for your variables, avoiding
gratuitous (visual) clashes.
|*)
Elpi Query lp:{{
coq.say (fun `x` {{nat}} x\ {{ fun x : nat => x + lp:{{ x }} }})
% e c c e
}}.
(*|
A commodity quotation without parentheses let's one quote identifiers
omitting the curly braces.
That is `lp:{{ ident }}` can be written just `lp:ident`.
|*)
Elpi Query lp:{{
coq.say (fun `x` {{nat}} x\ {{ fun x : nat => x + lp:x }})
% e c c e
}}.
(*|
It is quite frequent to put Coq variables in the scope of an Elpi
unification variable, and this can be done by simply writing
`lp:(X a b)` which is a shorhand for `lp:{{ X {{ a }} {{ b }} }}`.
.. warning:: writing `lp:X a b` (without parentheses) would result in a
Coq application, not an Elpi one
Let's play a bit with these shorthands:
|*)
Elpi Query lp:{{
X = (x\y\ {{ lp:y + lp:x }}), % x and y live in Elpi
coq.say {{ fun a b : nat => lp:(X a b) }} % a and b live in Coq
}}.
(*|
Another commodity quotation lets one access the coqlib
feature introduced in Coq 8.10.
Coqlib gives you an indirection between your code and the actual name
of constants.
|*)
Register Coq.Init.Datatypes.nat as my.N.
Register Coq.Init.Logic.eq as my.eq.
Elpi Query lp:{{
coq.say {{ fun a b : lib:my.N => lib:@my.eq lib:my.N a b }}
}}.
(*|
.. note:: The (optional) `@` in `lib:@some.name` disables implicit arguments.
The `{{:gref .. }}` quotation lets one build the gref data type, instead of the
term one. It supports `lib:` as well.
|*)
Elpi Query lp:{{
coq.say {{:gref nat }},
coq.say {{:gref lib:my.N }}.
}}.
(*|
The last thing to keep in mind when using quotations is that implicit
arguments are inserted (according to the `Arguments` setting in Coq)
but not synthesized automatically.
It is the job of the type checker or elaborator to synthesize them.
We shall see more on this in the section on `holes`_.
|*)
Elpi Query lp:{{
T = (fun `ax` {{nat}} a\ {{ fun b : nat => lp:a = b }}),
coq.say "before:" T,
coq.typecheck T _ ok,
coq.say "after:" T
}}.
(*|
===========
The context
===========
The context of Elpi (the hypothetical program made of rules loaded
via :e:`=>`) is taken into account by the Coq APIs. In particular every time
a bound variable is crossed, the programmer *must* load in the context a
rule attaching to that variable a type. There are a few facilities to
do that, but let's first see what happens if one forgets it.
|*)
Fail Elpi Query lp:{{
T = {{ fun x : nat => x + 1 }},
coq.typecheck T _ ok,
T = fun _ _ Bo,
pi x\
coq.typecheck (Bo x) _ _
}}. (* .fails *)
(*|
This fatal error says that :e:`x` in :e:`(Bo x)` is unknown to Coq.
It is
a variable postulated in Elpi, but it's type, `nat`, was lost. There
is nothing wrong per se in using :e:`pi x\ ` as we did if we don't call Coq
APIs under it. But if we do, we have to record the type of :e:`x` somewhere.
In some sense Elpi's way of traversing a binder is similar to a Zipper.
The context of Elpi must record the part of the Zipper context that is
relevant for binders.
The two predicates :builtin:`decl` and :builtin:`def` are used
for that purpose:
.. code:: elpi
pred decl i:term, o:name, o:term. % Var Name Ty
pred def i:term, o:name, o:term, o:term. % Var Name Ty Bo
where :e:`def` is used to cross a :e:`let`.
|*)
Elpi Query lp:{{
T = {{ fun x : nat => x + 1 }},
coq.typecheck T _ ok,
T = fun N Ty Bo,
pi x\
decl x N Ty =>
coq.typecheck (Bo x) _ ok
}}.
(*|
In order to ease this task, Coq-Elpi provides a few commodity macros such as
`@pi-decl`:
.. code:: elpi
macro @pi-decl N T F :- pi x\ decl x N T => F x.
.. note:: the precedence of lambda abstraction :e:`x\ ` lets you write the
following code without parentheses for :e:`F`.
|*)
Elpi Query lp:{{
T = {{ fun x : nat => x + 1 }},
coq.typecheck T _ ok,
T = fun N Ty Bo,
@pi-decl N Ty x\
coq.typecheck (Bo x) _ ok
}}.
(*|
.. tip:: :e:`@pi-decl N Ty x\ ` takes arguments in the same order of :constructor:`fun` and
:constructor:`prod`, while
:e:`@pi-def N Ty Bo x\ ` takes arguments in the same order of :constructor:`let`.
.. _holes:
==========================
Holes (implicit arguments)
==========================
An "Evar" (Coq slang for existentially quantified meta variable) is
represented as a Elpi unification variable and a typing constraint.
|*)
Elpi Query lp:{{
T = {{ _ }},
coq.say "raw T =" T,
coq.sigma.print,
coq.say "--------------------------------",
coq.typecheck T {{ nat }} ok,
coq.sigma.print
}}.
(*|
Before the call to :builtin:`coq.typecheck`, :builtin:`coq.sigma.print`
prints nothing interesting, while after the call it also prints the following
syntactic constraint:
.. mquote:: .s(Elpi).msg(suspended on X0)
:language: elpi
which indicates that the hole :e:`X0` is linked to a Coq evar
and is expected to have type `nat`.
Now the bijective mapping from Coq evars to Elpi's unification variables
is not empty anymore:
.. mquote:: .s(Elpi).msg{Coq-Elpi mapping:*[?]X11 <-> X0*}
:language: text
Note that Coq's evar identifiers are of the form `?X<n>`, while the Elpi ones
have no leading `?`. The Coq Evar map says that `?X11` has type `nat`:
.. mquote:: .s(Elpi).msg{EVARS:*[?]X11==[[] |- nat[]]*}
:language: text
The intuition is that Coq's Evar map (AKA sigma or evd), which assigns
typing judgement to evars, is represented with Elpi constraints which carry
the same piece of info.
Naked Elpi unification variables, when passed to Coq's API, are
automatically linked to a Coq evar. We postpone the explanation of the
difference "raw" and "elab" unification variables to the chapter about
tactics, here the second copy of :e:`X0` in the evar constraint plays
no role.
Now, what about the typing context?
|*)
Elpi Query lp:{{
T = {{ fun x : nat => x + _ }},
coq.say "raw T =" T,
T = fun N Ty Bo,
@pi-decl N Ty x\
coq.typecheck (Bo x) {{ nat }} ok,
coq.sigma.print.
}}.
(*|
In the value of raw :e:`T` we can see that the hole in `x + _`, which occurs under the
binder :e:`c0\ `, is represented by an Elpi unification variable :e:`X0 c0`, that
means that :e:`X0` sees :e:`c0` (:e:`c0` is in the scope of :e:`X0`).
The constraint is this time a bit more complex. Let's dissect it:
.. mquote:: .s(Elpi).msg(suspended on X0)
:language: elpi
Here `{...}` is the set of names (not necessarily minimized) used in the
constraint, while `?-` separates the assumptions (the context) from the
conclusion (the suspended goal).
The mapping between Coq and Elpi is:
.. mquote:: .s(Elpi).msg{Coq-Elpi mapping:*[?]X13 <-> X0*}
:language: text
where `?X13` can be found in Coq's sigma:
.. mquote:: .s(Elpi).msg{EVARS:*[?]X13==[[]x |- nat[]]*}
:language: text
As expected both Elpi's constraint and Coq's evar map record a context
with a variable :e:`x` (of type `nat`) which is in the scope of the hole.
Unless one is writing a tactic, Elpi's constraints are just used to
represent the evar map. When a term is assigned to a variable
the corresponding constraint is dropped. When one is writing a tactic,
things are wired up so that assigning a term to an Elpi variable
representing an evar resumes a type checking goal to ensure the term has
the expected type.
We will explain this in detail in the tutorial about tactics.
----------------------------
Outside the pattern fragment
----------------------------
This encoding of evars is such that the programmer does not need to care
much about them: no need to carry around an assignment/typing map like the
Evar map, no need to declared new variables there, etc. The programmer
can freely call Coq API passing an Elpi term containing holes.
There is one limitation, though. The rest of this tutorial describes it
and introduces a few APIs and options to deal with it.
The limitation is that the automatic declaration and mapping
does not work in all situations. In particular it only works for Elpi
unification variables which are in the pattern fragment, which mean
that they are applied only to distinct names (bound variables).
This is the case for all the `{{ _ }}` one writes inside quotations, for
example, but it is not hard to craft a term outside this fragment.
In particular we can use Elpi's substitution (function application) to
put an arbitrary term in place of a bound variable.
|*)
Fail Elpi Query lp:{{
T = {{ fun x : nat => x + _ }},
% remark the hole sees x
T = fun N Ty Bo,
% 1 is the offending term we put in place of x
Bo1 = Bo {{ 1 }},
% Bo1 is outside the pattern fragment
coq.say "Bo1 (not in pattern fragment) =" Bo1,
% boom
coq.typecheck Bo1 {{ nat }} ok.
}}. (* .fails *)
(*|
This snippet fails hard, with the following message:
.. mquote:: .s(Elpi).msg(Flexible term outside)
:language: elpi
Indeed :e:`Bo1` contains a term outside the pattern fragment,
the second argument of `plus`, which is obtained by replacing
:e:`c0` with `{{ 1 }}` in :e:`X0 c0`.
While programming Coq extensions in Elpi, it may happen that we want to
use a Coq term as a syntax tree (with holes) and we need to apply
substitutions to it but we don't really care about the scope of holes.
We would like these holes to stay `{{ _ }}` (a fresh hole which sees the
entire context of bound variables). In some sense, we would like `{{ _ }}`
to be a special dummy constant, to be turned into an actual hole on the
fly when needed.
This use case is perfectly legitimate and is supported by all APIs taking
terms in input thanks to the :macro:`@holes!` option.
|*)
Elpi Query lp:{{
T = {{ fun x : nat => x + _ }},
T = fun N Ty Bo,
Bo1 = Bo {{ 1 }},
coq.say "Bo1 before =" Bo1,
% by loading this rule in the context, we set
% the option for the APIs called under it
@holes! => coq.typecheck Bo1 {{ nat }} ok,
coq.say "Bo1 after =" Bo1.
}}.
(*|
Note that after the call to :builtin:`coq.typecheck`, :e:`X0` is assigned the
term :e:`_\ X1`, that means that the offending argument has been pruned
(discarded).
.. note:: All APIs taking a term support the :macro:`@holes!` option.
In addition to the :macro:`@holes!` option, there is a class of APIs which can
deal with terms outside the pattern fragment. These APIs take in input a term
*skeleton*. A skeleton is not modified in place, as :builtin:`coq.typecheck`
does with its first argument, but is rather elaborated to a term related to it.
In some sense APIs taking a skeleton are more powerful, because they can
modify the structure of the term, eg. insert a coercions, but are less
precise, in the sense that the relation between the input and the output
terms is not straightforward (it's not unification).
|*)
Coercion nat2bool n := match n with O => false | _ => true end.
Open Scope bool_scope.
Elpi Query lp:{{
T = {{ fun x : nat => x && _ }},
T = fun N Ty Bo,
Bo1 = Bo {{ 1 }},
coq.elaborate-skeleton Bo1 {{ bool }} Bo2 ok
}}.
(*|
Here :e:`Bo2` is obtained by taking :e:`Bo1`, considering all
unification variables as holes and all `{{ Type }}` levels as fresh
(the are none in this example), and running Coq's elaborator on it.
The result is a term with a similar structure (skeleton), but a coercion
is inserted to make :e:`x` fit as a boolean value, and a fresh hole :e:`X1` is
put in place of the term :e:`X0 (app [global (indc «S»), global (indc «O»)])`
which is left untouched.
Skeletons and their APIs are described in more details in the tutorial
on commands.
That is all for this tutorial. You can continue by reading the tutorial
about
`commands <https://lpcic.github.io/coq-elpi/tutorial_coq_elpi_command.html>`_
or the one about
`tactics <https://lpcic.github.io/coq-elpi/tutorial_coq_elpi_tactic.html>`_.
|*)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NAND4B_FUNCTIONAL_PP_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand4b (
VPWR,
VGND,
Y ,
A_N ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B ;
input C ;
input D ;
// Local signals
wire D not0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4B_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__OR2_BEHAVIORAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2_BEHAVIORAL_V |
`timescale 1ns / 100ps
/* The GPIA bit input mux is used when a processing element reads from I/O
* space. Some bits may be configured to sample actual signals outside the
* GPIA ("inputs"). Some pins will be configured to drive signals outside the
* GPIA ("outputs"). If a particular I/O bit is configured as an output, we
* want to read back the last value we wrote to it. Otherwise, we want to
* read the current state of the external signal attached to it.
*/
module test();
reg out_o;
reg inp_o;
reg ddr_o;
reg stb_o;
wire q_i;
/* We have a clock, but the mux doesn't use it. I use it for test
* synchronization only.
*/
reg clk_o;
/* Scenario tag for knowing which test is running when viewing waveforms. */
reg [7:0] scenario_o;
/* Device Under Test */
GPIA_BIT_IN dut (
.out_i(out_o),
.inp_i(inp_o),
.ddr_i(ddr_o),
.stb_i(stb_o),
.q_o(q_i)
);
always begin
#20 clk_o <= ~clk_o;
end
task waitclk;
begin @(negedge clk_o); @(posedge clk_o);
end
endtask
/* The scenario tests commence here. */
initial begin
scenario_o <= 8'h00;
out_o <= 0;
inp_o <= 0;
ddr_o <= 0;
stb_o <= 0;
clk_o <= 0;
$dumpfile("test.vcd");
$dumpvars;
/* With stb_o low, we expect a zero result, regardless of the state
* of the inputs. This allows an implementation to logically-OR
* buses together.
*/
@(posedge clk_o);
scenario_o <= 8'h10;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h14;
out_o <= 1;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h18;
inp_o <= 1;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h1C;
out_o <= 0;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
/* With stb_o high, we expect actual results, according to the
* current value of ddr_o.
*
* We first exercise the circuit with DDR set to 0 (input).
*/
@(posedge clk_o);
scenario_o <= 8'h20;
stb_o <= 1;
inp_o <= 0;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h24;
out_o <= 1;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h28;
inp_o <= 1;
waitclk;
#2 if(q_i != 1) begin
$display("FAIL %x: Q not 1", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h2C;
out_o <= 0;
waitclk;
#2 if(q_i != 1) begin
$display("FAIL %x: Q not 1", scenario_o); $finish;
end
/* Next, we set the DDR to 1 (output), so Q should track
* out_o instead of inp_o.
*/
@(posedge clk_o);
scenario_o <= 8'h30;
stb_o <= 1;
ddr_o <= 1;
inp_o <= 0;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h34;
out_o <= 1;
waitclk;
#2 if(q_i != 1) begin
$display("FAIL %x: Q not 1", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h38;
inp_o <= 1;
waitclk;
#2 if(q_i != 1) begin
$display("FAIL %x: Q not 1", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h3C;
out_o <= 0;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
$display("PASS"); $finish;
end
endmodule
|
module axi_elink(/*AUTOARG*/
// Outputs
rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, e_chipid, e_resetb, e_cclk_p, e_cclk_n,
mailbox_not_empty, mailbox_full, m_axi_awid, m_axi_awaddr,
m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock,
m_axi_awcache, m_axi_awprot, m_axi_awqos, m_axi_awvalid, m_axi_wid,
m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_bready,
m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst,
m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos,
m_axi_arvalid, m_axi_rready, s_axi_arready, s_axi_awready,
s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_rid, s_axi_rdata,
s_axi_rlast, s_axi_rresp, s_axi_rvalid, s_axi_wready,
// Inputs
reset, sys_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n,
rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, m_axi_aresetn, m_axi_awready,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_arready,
m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid,
s_axi_aresetn, s_axi_arid, s_axi_araddr, s_axi_arburst,
s_axi_arcache, s_axi_arlock, s_axi_arlen, s_axi_arprot,
s_axi_arqos, s_axi_arsize, s_axi_arvalid, s_axi_awid, s_axi_awaddr,
s_axi_awburst, s_axi_awcache, s_axi_awlock, s_axi_awlen,
s_axi_awprot, s_axi_awqos, s_axi_awsize, s_axi_awvalid,
s_axi_bready, s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast,
s_axi_wstrb, s_axi_wvalid
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104; //packet width
parameter ID = 12'h810;
parameter S_IDW = 12; //ID width for S_AXI
parameter M_IDW = 6; //ID width for M_AXI
parameter IOSTD_ELINK = "LVDS_25";
parameter ETYPE = 1;
/****************************/
/*CLK AND RESET */
/****************************/
input reset; // active high async reset
input sys_clk; // system clock for AXI
/********************************/
/*ELINK I/O PINS */
/********************************/
//Receiver
input rxi_lclk_p, rxi_lclk_n; //link rx clock input
input rxi_frame_p, rxi_frame_n; //link rx frame signal
input [7:0] rxi_data_p, rxi_data_n; //link rx data
output rxo_wr_wait_p,rxo_wr_wait_n; //link rx write pushback output
output rxo_rd_wait_p,rxo_rd_wait_n; //link rx read pushback output
//Transmitter
output txo_lclk_p, txo_lclk_n; //link tx clock output
output txo_frame_p, txo_frame_n; //link tx frame signal
output [7:0] txo_data_p, txo_data_n; //link tx data
input txi_wr_wait_p,txi_wr_wait_n; //link tx write pushback input
input txi_rd_wait_p,txi_rd_wait_n; //link tx read pushback input
/********************************/
/*EPIPHANY INTERFACE (I/O PINS) */
/********************************/
output [11:0] e_chipid; //chip id strap pins for Epiphany
output e_resetb; //chip reset for Epiphany (active low)
output e_cclk_p,e_cclk_n; //high speed clock (up to 1GHz) to Epiphany
/*****************************/
/*MAILBOX (interrupts) */
/*****************************/
output mailbox_not_empty;
output mailbox_full;
//########################
//AXI MASTER INTERFACE
//########################
input m_axi_aresetn; // global reset singal.
//Write address channel
output [M_IDW-1:0] m_axi_awid; // write address ID
output [31 : 0] m_axi_awaddr; // master interface write address
output [7 : 0] m_axi_awlen; // burst length.
output [2 : 0] m_axi_awsize; // burst size.
output [1 : 0] m_axi_awburst; // burst type.
output [1 : 0] m_axi_awlock; // lock type
output [3 : 0] m_axi_awcache; // memory type.
output [2 : 0] m_axi_awprot; // protection type.
output [3 : 0] m_axi_awqos; // quality of service
output m_axi_awvalid; // write address valid
input m_axi_awready; // write address ready
//Write data channel
output [M_IDW-1:0] m_axi_wid;
output [63 : 0] m_axi_wdata; // master interface write data.
output [7 : 0] m_axi_wstrb; // byte write strobes
output m_axi_wlast; // last transfer in a write burst.
output m_axi_wvalid; // indicates data is ready to go
input m_axi_wready; // slave is ready for data
//Write response channel
input [M_IDW-1:0] m_axi_bid;
input [1 : 0] m_axi_bresp; // status of the write transaction.
input m_axi_bvalid; // valid write response
output m_axi_bready; // master can accept write response.
//Read address channel
output [M_IDW-1:0] m_axi_arid; // read address ID
output [31 : 0] m_axi_araddr; // initial address of a read burst
output [7 : 0] m_axi_arlen; // burst length
output [2 : 0] m_axi_arsize; // burst size
output [1 : 0] m_axi_arburst; // burst type
output [1 : 0] m_axi_arlock; // lock type
output [3 : 0] m_axi_arcache; // memory type
output [2 : 0] m_axi_arprot; // protection type
output [3 : 0] m_axi_arqos; // --
output m_axi_arvalid; // read address and control is valid
input m_axi_arready; // slave is ready to accept an address
//Read data channel
input [M_IDW-1:0] m_axi_rid;
input [63 : 0] m_axi_rdata; // master read data
input [1 : 0] m_axi_rresp; // status of the read transfer
input m_axi_rlast; // signals last transfer in a read burst
input m_axi_rvalid; // signaling the required read data
output m_axi_rready; // master can accept the readback data
/*****************************/
/*AXI slave interface */
/*****************************/
//Clock and reset
input s_axi_aresetn;
//Read address channel
input [S_IDW-1:0] s_axi_arid; //write address ID
input [31:0] s_axi_araddr;
input [1:0] s_axi_arburst;
input [3:0] s_axi_arcache;
input [1:0] s_axi_arlock;
input [7:0] s_axi_arlen;
input [2:0] s_axi_arprot;
input [3:0] s_axi_arqos;
output s_axi_arready;
input [2:0] s_axi_arsize;
input s_axi_arvalid;
//Write address channel
input [S_IDW-1:0] s_axi_awid; //write address ID
input [31:0] s_axi_awaddr;
input [1:0] s_axi_awburst;
input [3:0] s_axi_awcache;
input [1:0] s_axi_awlock;
input [7:0] s_axi_awlen;
input [2:0] s_axi_awprot;
input [3:0] s_axi_awqos;
input [2:0] s_axi_awsize;
input s_axi_awvalid;
output s_axi_awready;
//Buffered write response channel
output [S_IDW-1:0] s_axi_bid; //write address ID
output [1:0] s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
//Read channel
output [S_IDW-1:0] s_axi_rid; //write address ID
output [31:0] s_axi_rdata;
output s_axi_rlast;
output [1:0] s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
//Write channel
input [S_IDW-1:0] s_axi_wid; //write address ID
input [31:0] s_axi_wdata;
input s_axi_wlast;
input [3:0] s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
/*#############################################*/
/* END OF BLOCK INTERFACE */
/*#############################################*/
/*AUTOINPUT*/
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire elink_en; // From elink of elink.v
wire elink_reset; // From eclocks of eclocks.v
wire rx_lclk; // From eclocks of eclocks.v
wire rx_lclk_div4; // From eclocks of eclocks.v
wire rx_lclk_pll; // From elink of elink.v
wire rxrd_access; // From elink of elink.v
wire [PW-1:0] rxrd_packet; // From elink of elink.v
wire rxrd_wait; // From emaxi of emaxi.v
wire rxrr_access; // From elink of elink.v
wire [PW-1:0] rxrr_packet; // From elink of elink.v
wire rxrr_wait; // From esaxi of esaxi.v
wire rxwr_access; // From elink of elink.v
wire [PW-1:0] rxwr_packet; // From elink of elink.v
wire rxwr_wait; // From emaxi of emaxi.v
wire timeout; // From elink of elink.v
wire tx_lclk; // From eclocks of eclocks.v
wire tx_lclk90; // From eclocks of eclocks.v
wire tx_lclk_div4; // From eclocks of eclocks.v
wire txrd_access; // From esaxi of esaxi.v
wire [PW-1:0] txrd_packet; // From esaxi of esaxi.v
wire txrd_wait; // From elink of elink.v
wire txrr_access; // From emaxi of emaxi.v
wire [PW-1:0] txrr_packet; // From emaxi of emaxi.v
wire txrr_wait; // From elink of elink.v
wire txwr_access; // From esaxi of esaxi.v
wire [PW-1:0] txwr_packet; // From esaxi of esaxi.v
wire txwr_wait; // From elink of elink.v
// End of automatics
//########################################################
//ELINK
//########################################################
defparam elink.IOSTD_ELINK = IOSTD_ELINK;
defparam elink.ETYPE = ETYPE;
elink elink(.reset (elink_reset),
/*AUTOINST*/
// Outputs
.rx_lclk_pll (rx_lclk_pll),
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.e_chipid (e_chipid[11:0]),
.elink_en (elink_en),
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access),
.rxrd_packet (rxrd_packet[PW-1:0]),
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
.txwr_wait (txwr_wait),
.txrd_wait (txrd_wait),
.txrr_wait (txrr_wait),
.mailbox_not_empty (mailbox_not_empty),
.mailbox_full (mailbox_full),
.timeout (timeout),
// Inputs
.sys_clk (sys_clk),
.tx_lclk (tx_lclk),
.tx_lclk90 (tx_lclk90),
.tx_lclk_div4 (tx_lclk_div4),
.rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4),
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p),
.rxi_frame_n (rxi_frame_n),
.rxi_data_p (rxi_data_p[7:0]),
.rxi_data_n (rxi_data_n[7:0]),
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.rxwr_wait (rxwr_wait),
.rxrd_wait (rxrd_wait),
.rxrr_wait (rxrr_wait),
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]));
//########################################################
//CLOCK AND RESET
//########################################################
eclocks eclocks (.rx_clkin (rx_lclk_pll),
/*AUTOINST*/
// Outputs
.tx_lclk (tx_lclk),
.tx_lclk90 (tx_lclk90),
.tx_lclk_div4 (tx_lclk_div4),
.rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4),
.e_cclk_p (e_cclk_p),
.e_cclk_n (e_cclk_n),
.elink_reset (elink_reset),
.e_resetb (e_resetb),
// Inputs
.reset (reset),
.elink_en (elink_en),
.sys_clk (sys_clk));
//########################################################
//AXI SLAVE
//########################################################
defparam esaxi.IDW=S_IDW;
esaxi esaxi (.s_axi_aclk (sys_clk),
/*AUTOINST*/
// Outputs
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.rxrr_wait (rxrr_wait),
.s_axi_arready (s_axi_arready),
.s_axi_awready (s_axi_awready),
.s_axi_bid (s_axi_bid[S_IDW-1:0]),
.s_axi_bresp (s_axi_bresp[1:0]),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_rid (s_axi_rid[S_IDW-1:0]),
.s_axi_rdata (s_axi_rdata[31:0]),
.s_axi_rlast (s_axi_rlast),
.s_axi_rresp (s_axi_rresp[1:0]),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_wready (s_axi_wready),
// Inputs
.txwr_wait (txwr_wait),
.txrd_wait (txrd_wait),
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_arid (s_axi_arid[S_IDW-1:0]),
.s_axi_araddr (s_axi_araddr[31:0]),
.s_axi_arburst (s_axi_arburst[1:0]),
.s_axi_arcache (s_axi_arcache[3:0]),
.s_axi_arlock (s_axi_arlock[1:0]),
.s_axi_arlen (s_axi_arlen[7:0]),
.s_axi_arprot (s_axi_arprot[2:0]),
.s_axi_arqos (s_axi_arqos[3:0]),
.s_axi_arsize (s_axi_arsize[2:0]),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_awid (s_axi_awid[S_IDW-1:0]),
.s_axi_awaddr (s_axi_awaddr[31:0]),
.s_axi_awburst (s_axi_awburst[1:0]),
.s_axi_awcache (s_axi_awcache[3:0]),
.s_axi_awlock (s_axi_awlock[1:0]),
.s_axi_awlen (s_axi_awlen[7:0]),
.s_axi_awprot (s_axi_awprot[2:0]),
.s_axi_awqos (s_axi_awqos[3:0]),
.s_axi_awsize (s_axi_awsize[2:0]),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_bready (s_axi_bready),
.s_axi_rready (s_axi_rready),
.s_axi_wid (s_axi_wid[S_IDW-1:0]),
.s_axi_wdata (s_axi_wdata[31:0]),
.s_axi_wlast (s_axi_wlast),
.s_axi_wstrb (s_axi_wstrb[3:0]),
.s_axi_wvalid (s_axi_wvalid));
//########################################################
//AXI MASTER INTERFACE
//########################################################
defparam emaxi.IDW=M_IDW;
emaxi emaxi (.m_axi_aclk (sys_clk),
/*AUTOINST*/
// Outputs
.rxwr_wait (rxwr_wait),
.rxrd_wait (rxrd_wait),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]),
.m_axi_awid (m_axi_awid[M_IDW-1:0]),
.m_axi_awaddr (m_axi_awaddr[31:0]),
.m_axi_awlen (m_axi_awlen[7:0]),
.m_axi_awsize (m_axi_awsize[2:0]),
.m_axi_awburst (m_axi_awburst[1:0]),
.m_axi_awlock (m_axi_awlock[1:0]),
.m_axi_awcache (m_axi_awcache[3:0]),
.m_axi_awprot (m_axi_awprot[2:0]),
.m_axi_awqos (m_axi_awqos[3:0]),
.m_axi_awvalid (m_axi_awvalid),
.m_axi_wid (m_axi_wid[M_IDW-1:0]),
.m_axi_wdata (m_axi_wdata[63:0]),
.m_axi_wstrb (m_axi_wstrb[7:0]),
.m_axi_wlast (m_axi_wlast),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_bready (m_axi_bready),
.m_axi_arid (m_axi_arid[M_IDW-1:0]),
.m_axi_araddr (m_axi_araddr[31:0]),
.m_axi_arlen (m_axi_arlen[7:0]),
.m_axi_arsize (m_axi_arsize[2:0]),
.m_axi_arburst (m_axi_arburst[1:0]),
.m_axi_arlock (m_axi_arlock[1:0]),
.m_axi_arcache (m_axi_arcache[3:0]),
.m_axi_arprot (m_axi_arprot[2:0]),
.m_axi_arqos (m_axi_arqos[3:0]),
.m_axi_arvalid (m_axi_arvalid),
.m_axi_rready (m_axi_rready),
// Inputs
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access),
.rxrd_packet (rxrd_packet[PW-1:0]),
.txrr_wait (txrr_wait),
.m_axi_aresetn (m_axi_aresetn),
.m_axi_awready (m_axi_awready),
.m_axi_wready (m_axi_wready),
.m_axi_bid (m_axi_bid[M_IDW-1:0]),
.m_axi_bresp (m_axi_bresp[1:0]),
.m_axi_bvalid (m_axi_bvalid),
.m_axi_arready (m_axi_arready),
.m_axi_rid (m_axi_rid[M_IDW-1:0]),
.m_axi_rdata (m_axi_rdata[63:0]),
.m_axi_rresp (m_axi_rresp[1:0]),
.m_axi_rlast (m_axi_rlast),
.m_axi_rvalid (m_axi_rvalid));
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../erx/hdl" "../../etx/hdl" "../../memory/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// *********************************************************************
// Author : $Author: Marco $ @ bitec-dsp.com
// Department :
// Date : $Date: 2016-05-16 17:02:22 +0300 (Mon, 16 May 2016) $
// Revision : $Revision: 2260 $
// URL : $URL: svn://nas-bitec-fi/dp/trunk/demo/bitec_reconfig_alt_a10.v $
// *********************************************************************
// Description
//
// This module implements Altera RX/TX transceivers reconfiguration
// for Altera Arria 10 GX ES2, rev.D1 and ES3:
// - single 135MHz clock input for 1620,2700,5400 and 8100 Mbps
// - Duplex mode used if both RX and TX are present
// - TXPLL is a regular FPLL (not an ATXPLL)
// - FPLL "embedded debug features" must be enabled
// - XCVR "embedded debug features" must be enabled
//
// Supported link rates:
// 0 1.62G RBR
// 1 2.7G HBR
// 2 5.4G HBR2
// 3 6.75G
// 4 8.1G HBR3
//
// *********************************************************************
// synthesis translate_off
`timescale 1ns / 1ns
// synthesis translate_on
`default_nettype none
module bitec_reconfig_alt_a10
#(
parameter [3:0] TX_LANES = 4,
parameter [3:0] RX_LANES = 4,
parameter [2:0] TX_RATES_NUM = 3, // Number of TX link rates (0: no TX support, 1: up to RBR, 2: up to HBR, etc.)
parameter [2:0] RX_RATES_NUM = 3, // Number of RX link rates (0: no TX support, 1: up to RBR, 2: up to HBR, etc.)
parameter A10_ES2 = 0 // 1 = 10AX115S2F45I2SGE2 device (ES2 silicon) 0 = any other device silicon
)
(
input wire clk, // The same clock driving the reconfig controllers
input wire reset, // The same reset driving the reconfig controllers
input wire [7:0] rx_link_rate, // Link rate in multiples of 270 Mbps
input wire rx_link_rate_strobe, // Assert for at least 1 clk cycle when a new rx_link_rate must be used
output wire rx_xcvr_busy, // Asserted during RX reconfig and calibration time
output reg rx_xcvr_reset,
input wire [7:0] tx_link_rate, // Link rate in multiples of 270 Mbps
input wire [(TX_LANES*2)-1:0] tx_vod, // Voltage swing level, 0 to 3
input wire [(TX_LANES*2)-1:0] tx_emp, // Pre-emphasis level, 0 to 3
input wire tx_link_rate_strobe, // Assert for at least 1 clk cycle when a new tx_link_rate must be used
input wire tx_vodemp_strobe, // Assert for at least 1 clk cycle when new VOD/EMP values must be used
output wire tx_xcvr_busy, // Asserted during TX reconfig and calibration time
output reg tx_xcvr_reset, // Asserted when the TX XCVR must be reset
// XCVR reconfig controller interface
input wire rx_analogreset_ack,
output wire [1:0] rx_mgmt_chnum,
output wire [9:0] rx_mgmt_address,
output wire [31:0] rx_mgmt_writedata,
input wire [31:0] rx_mgmt_readdata,
output wire rx_mgmt_write,
output wire rx_mgmt_read,
input wire rx_mgmt_waitrequest,
input wire tx_analogreset_ack,
output wire [1:0] tx_mgmt_chnum,
output wire [9:0] tx_mgmt_address,
output wire [31:0] tx_mgmt_writedata,
input wire [31:0] tx_mgmt_readdata,
output wire tx_mgmt_write,
output wire tx_mgmt_read,
input wire tx_mgmt_waitrequest,
// TX PLL reconfig controller interface
output wire [9:0] txpll_mgmt_address,
output wire [31:0] txpll_mgmt_writedata,
input wire [31:0] txpll_mgmt_readdata,
output wire txpll_mgmt_write,
output wire txpll_mgmt_read,
input wire txpll_mgmt_waitrequest,
input wire rx_xcvr_cal_busy,
input wire tx_xcvr_cal_busy,
input wire tx_pll_cal_busy
);
// main FSM states
localparam FSM_CNF_TXPLL1 = 5'd0,
FSM_CNF_TXPLL2 = 5'd1,
FSM_CAL_TXPLL1 = 5'd2,
FSM_CAL_TXPLL2 = 5'd3,
FSM_CAL_TXPLL3 = 5'd4,
FSM_CAL_TXPLL4 = 5'd5,
FSM_MEM_TXPLL1 = 5'd6,
FSM_MEM_TXPLL2 = 5'd7,
FSM_CNF_RXGXB1 = 5'd8,
FSM_CNF_RXGXB2 = 5'd9,
FSM_CNF_RXGXB3 = 5'd10,
FSM_CNF_RXGXB_NEXTLANE = 5'd11,
FSM_CAL_RXGXB1 = 5'd12,
FSM_CAL_RXGXB2 = 5'd13,
FSM_CAL_RXGXB3 = 5'd14,
FSM_CAL_RXGXB4 = 5'd15,
FSM_CAL_RXGXB5 = 5'd16,
FSM_MEM_RXGXB = 5'd17,
FSM_CAL_RXGXB_NEXTLANE = 5'd18,
FSM_IDLE = 5'd19,
FSM_START_RX_LINKRATE = 5'd20,
FSM_START_TX_LINKRATE = 5'd21,
FSM_START_TX_ANALOG = 5'd22,
FSM_FEAT_RECONFIG = 5'd23,
FSM_WAIT_FOR_BUSY_LOW = 5'd24,
FSM_NEXT_RX_LRATE_FEATURE = 5'd25,
FSM_NEXT_TX_LRATE_FEATURE = 5'd26,
FSM_NEXT_TX_ANALOG_FEATURE = 5'd27,
FSM_END_RECONFIG = 5'd28,
FSM_NEXT_LANE = 5'd29,
FSM_END = 5'd30;
// Feature index
localparam FEAT_RX_REFCLK1 = 4'd0,
FEAT_RX_REFCLK2 = 4'd1,
FEAT_RX_REFCLK3 = 4'd2,
FEAT_RX_REFCLK4 = 4'd3,
FEAT_TX_VOD = 4'd4,
FEAT_TX_EMP1 = 4'd5,
FEAT_TX_EMP2 = 4'd6,
FEAT_TX_EMP3 = 4'd7,
FEAT_TX_EMP4 = 4'd8,
FEAT_TX_REFCLK1 = 4'd9,
FEAT_TX_REFCLK2 = 4'd10,
FEAT_TX_REFCLK3 = 4'd11;
// XCVR Reconfiguration controller register addresses
localparam ADDR_CALIB = 10'h100,
ADDR_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP = 10'h105,
ADDR_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP = 10'h106,
ADDR_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T = 10'h107,
ADDR_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T = 10'h108,
ADDR_VOD_OUTPUT_SWING_CTRL = 10'h109,
ADDR_L_PFD_COUNTER = 10'h13a,
ADDR_L_PD_COUNTER = 10'h13a,
ADDR_M_COUNTER = 10'h13b,
ADDR_CP_CALIB = 10'h166;
// XCVR Reconfiguration controller register masks
localparam MASK_CALIB = 32'h0000_0006,
MASK_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP = 32'h0000_005f,
MASK_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP = 32'h0000_002f,
MASK_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T = 32'h0000_003f,
MASK_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T = 32'h0000_0017,
MASK_VOD_OUTPUT_SWING_CTRL = 32'h0000_001f,
MASK_L_PFD_COUNTER = 32'h0000_0007,
MASK_L_PD_COUNTER = 32'h0000_0038,
MASK_M_COUNTER = 32'h0000_00ff,
MASK_CP_CALIB = 32'h0000_0080;
// TXPLL Reconfiguration controller register addresses
localparam ADDR_TXPLL_CALIB = 10'h100,
ADDR_TXPLL_M_CNT = 10'h12b,
ADDR_TXPLL_L_CNT = 10'h12c;
// TXPLL Reconfiguration controller register masks
localparam MASK_TXPLL_CALIB = 32'h0000_0002,
MASK_TXPLL_M_CNT = 32'h0000_00ff,
MASK_TXPLL_L_CNT = 32'h0000_0006;
// RXGXB linkrate-dependent register values
wire [2:0] COUNTER_L_PFD [3:0];
wire [2:0] COUNTER_L_PD [3:0];
wire [7:0] COUNTER_M [3:0];
assign COUNTER_L_PFD[0] = A10_ES2 ? 3'h3 : 3'h3; // 1.62G
assign COUNTER_L_PFD[1] = A10_ES2 ? 3'h3 : 3'h3; // 2.7G
assign COUNTER_L_PFD[2] = A10_ES2 ? 3'h4 : 3'h3; // 5.4G
assign COUNTER_L_PFD[3] = A10_ES2 ? 3'h3 : 3'h3; // 8.1G
assign COUNTER_L_PD[0] = A10_ES2 ? 3'h5 : 3'h5; // 1.62G
assign COUNTER_L_PD[1] = A10_ES2 ? 3'h4 : 3'h4; // 2.7G
assign COUNTER_L_PD[2] = A10_ES2 ? 3'h4 : 3'h3; // 5.4G
assign COUNTER_L_PD[3] = A10_ES2 ? 3'h3 : 3'h3; // 8.1G
assign COUNTER_M[0] = A10_ES2 ? 8'h18 : 8'hC; // 1.62G
assign COUNTER_M[1] = A10_ES2 ? 8'h14 : 8'h14; // 2.7G
assign COUNTER_M[2] = A10_ES2 ? 8'h14 : 8'h14; // 5.4G
assign COUNTER_M[3] = A10_ES2 ? 8'h1E : 8'hF; // 8.1G
// TXPLL linkrate-dependent register values
wire [1:0] L_COUNTER_FPLL [3:0];
wire [7:0] M_COUNTER_FPLL [3:0];
assign L_COUNTER_FPLL[0] = A10_ES2 ? 2'h3 : 2'h2; // 1.62G
assign L_COUNTER_FPLL[1] = A10_ES2 ? 2'h2 : 2'h2; // 2.7G
assign L_COUNTER_FPLL[2] = A10_ES2 ? 2'h1 : 2'h1; // 5.4G
assign L_COUNTER_FPLL[3] = A10_ES2 ? 2'h0 : 2'h0; // 8.1G
assign M_COUNTER_FPLL[0] = A10_ES2 ? 8'h315 : 8'hC; // 1.62G
assign M_COUNTER_FPLL[1] = A10_ES2 ? 8'h14 : 8'h14; // 2.7G
assign M_COUNTER_FPLL[2] = A10_ES2 ? 8'h14 : 8'h14; // 5.4G
assign M_COUNTER_FPLL[3] = A10_ES2 ? 8'hF : 8'hF; // 8.1G
reg [4:0] fsm_state; // Main FSM state
reg [3:0] feature_idx; // Feature index
// Synchronize asynchronous rx_analogreset_ack
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON; -name SDC_STATEMENT \"set_false_path -to [get_keepers {*bitec_reconfig_alt_a10:*|rx_reset_ack_r}]\" "} *) reg rx_reset_ack_r /* synopsys translate_off */ = 1'b1 /* synopsys translate_on */;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg rx_reset_ack_rr /* synopsys translate_off */ = 1'b1 /* synopsys translate_on */;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg rx_reset_ack_rrr /* synopsys translate_off */ = 1'b1 /* synopsys translate_on */;
always @(posedge clk or posedge reset)
if (reset)
{rx_reset_ack_r, rx_reset_ack_rr, rx_reset_ack_rrr} <= 3'b000;
else
{rx_reset_ack_r, rx_reset_ack_rr, rx_reset_ack_rrr} <= {rx_analogreset_ack, rx_reset_ack_r, rx_reset_ack_rr};
// Synchronize asynchronous tx_analogreset_ack
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON; -name SDC_STATEMENT \"set_false_path -to [get_keepers {*bitec_reconfig_alt_a10:*|tx_reset_ack_r}]\" "} *) reg tx_reset_ack_r /* synopsys translate_off */ = 1'b1 /* synopsys translate_on */;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg tx_reset_ack_rr /* synopsys translate_off */ = 1'b1 /* synopsys translate_on */;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg tx_reset_ack_rrr /* synopsys translate_off */ = 1'b1 /* synopsys translate_on */;
always @(posedge clk or posedge reset)
if (reset)
{tx_reset_ack_r, tx_reset_ack_rr, tx_reset_ack_rrr} <= 3'b000;
else
{tx_reset_ack_r, tx_reset_ack_rr, tx_reset_ack_rrr} <= {tx_analogreset_ack, tx_reset_ack_r, tx_reset_ack_rr};
// VOD & EMP mapped to the TX XCVR
wire [TX_LANES*5-1:0] vod_mapped;
wire [TX_LANES*6-1:0] emp_mapped;
// Generate mapping tables for each lane
generate
begin
genvar tx_lane;
for (tx_lane=0; tx_lane < TX_LANES; tx_lane = tx_lane + 1)
begin:lane
dp_analog_mappings dp_analog_mappings_i
(
.vod (tx_vod[(tx_lane*2) +:2]),
.pree (tx_emp[(tx_lane*2) +:2]),
.out_vod (vod_mapped[(tx_lane*5) +:5]),
.out_pree_post_tap1 (emp_mapped[(tx_lane*6) +:6])
);
end // for
end // generate
endgenerate
//-------------------
// Changes detection
//-------------------
reg [2:0] rx_link_rate_strobe_d,tx_link_rate_strobe_d,tx_vodemp_strobe_d;
reg rx_new_linkrate; // Asserted when RX linkrate changes are detected
reg tx_new_linkrate; // Asserted when TX linkrate changes are detected
reg tx_new_analog; // Asserted when TX VOD/EMP changes are detected
always @ (posedge clk or posedge reset)
begin
if(reset)
begin
rx_link_rate_strobe_d <= 3'h0;
tx_link_rate_strobe_d <= 3'h0;
tx_vodemp_strobe_d <= 3'h0;
rx_xcvr_reset <= 1'b0;
tx_xcvr_reset <= 1'b0;
rx_new_linkrate <= 1'b0;
tx_new_linkrate <= 1'b0;
tx_new_analog <= 1'b0;
end
else
begin
rx_link_rate_strobe_d <= {rx_link_rate_strobe_d[1:0],rx_link_rate_strobe};
tx_link_rate_strobe_d <= {tx_link_rate_strobe_d[1:0],tx_link_rate_strobe};
tx_vodemp_strobe_d <= {tx_vodemp_strobe_d[1:0],tx_vodemp_strobe};
rx_xcvr_reset <= (fsm_state == FSM_END) ? 1'b0 : (rx_new_linkrate ? 1'b1 : rx_xcvr_reset);
tx_xcvr_reset <= (fsm_state == FSM_END) ? 1'b0 : (tx_new_linkrate ? 1'b1 : (tx_new_analog ? 1'b1 : tx_xcvr_reset));
rx_new_linkrate <= rx_new_linkrate ? ~(fsm_state == FSM_START_RX_LINKRATE) : (~rx_link_rate_strobe_d[2] & rx_link_rate_strobe_d[1]);
tx_new_linkrate <= tx_new_linkrate ? ~(fsm_state == FSM_START_TX_LINKRATE) : (~tx_link_rate_strobe_d[2] & tx_link_rate_strobe_d[1]);
tx_new_analog <= tx_new_analog ? ~(fsm_state == FSM_START_TX_ANALOG) : (~tx_vodemp_strobe_d[2] & tx_vodemp_strobe_d[1]);
end
end
//----------
// Main FSM
//----------
reg [TX_LANES*5-1:0] vod_mem;
reg [TX_LANES*6-1:0] emp_mem;
reg [1:0] tx_link_rate_mem;
reg [1:0] rx_link_rate_mem;
reg [1:0] lane_idx; // Configured lane index (0-3)
reg [2:0] write_cnt; // Write operations counter
reg rcnf_reconfig; // Asserted to start a XCVR single item reconfig with the values defined below
reg [9:0] rcnf_address; // Reconfiguration address
reg [31:0] rcnf_data; // Reconfiguration data value
reg [31:0] rcnf_mask; // Reconfiguration data mask
reg rcnf_req_cbus; // Asserted to request access to Altera internal config bus
reg rcnf_rel_cbus; // Asserted to release Altera internal config bus
reg rcnf_wcalib; // Asserted to wait for calibration completion
reg rcnf_scalib; // Asserted to save linkrate related calibration results
reg rcnf_lcalib; // Asserted to load back linkrate related calibration results
wire rcnf_busy;
reg rx_lrate_busy; // Asserted when RX linkrate changes are being performed
reg tx_lrate_busy; // Asserted when TX linkrate changes are being performed
reg tx_analog_busy; // Asserted when TX analog changes are being performed
wire rx_cal_busy;
wire tx_cal_busy;
assign rx_cal_busy = rx_xcvr_cal_busy;
assign tx_cal_busy = tx_pll_cal_busy | tx_xcvr_cal_busy;
assign rx_xcvr_busy = rx_lrate_busy | rx_cal_busy;
assign tx_xcvr_busy = tx_lrate_busy | tx_cal_busy | tx_analog_busy;
//assign tx_xcvr_reset = tx_lrate_busy & (fsm_state == FSM_END);
always @ (posedge clk or posedge reset)
begin
if(reset)
begin
fsm_state <= FSM_CNF_TXPLL1;
vod_mem <= 0;
emp_mem <= 0;
tx_link_rate_mem <= 2'h0;
rx_link_rate_mem <= 2'h0;
rcnf_req_cbus <= 1'b0;
rcnf_rel_cbus <= 1'b0;
rcnf_wcalib <= 1'b0;
rcnf_scalib <= 1'b0;
rcnf_lcalib <= 1'b0;
rcnf_reconfig <= 1'b0;
rcnf_address <= 10'h0;
rcnf_data <= 32'h0;
rcnf_mask <= 32'h0;
feature_idx <= FEAT_RX_REFCLK1;
write_cnt <= 3'h0;
lane_idx <= 2'h0;
rx_lrate_busy <= 1'b0;
tx_lrate_busy <= 1'b0;
tx_analog_busy <= 1'b0;
end
else
begin
rcnf_req_cbus <= 1'b0;
rcnf_rel_cbus <= 1'b0;
rcnf_wcalib <= 1'b0;
rcnf_scalib <= 1'b0;
rcnf_lcalib <= 1'b0;
rcnf_reconfig <= 1'b0;
case(fsm_state)
FSM_CNF_TXPLL1: // Set the TXPLL to tx_link_rate_mem link rate
if(tx_link_rate_mem < TX_RATES_NUM[1:0])
begin
if(~rx_cal_busy & ~tx_cal_busy)
begin
tx_lrate_busy <= 1'b1;
rcnf_address <= ADDR_TXPLL_M_CNT;
rcnf_mask <= MASK_TXPLL_M_CNT;
rcnf_data <= {24'd0,M_COUNTER_FPLL[tx_link_rate_mem]};
rcnf_reconfig <= 1'b1;
fsm_state <= FSM_CNF_TXPLL2;
end
end
else
begin
tx_lrate_busy <= 1'b0;
fsm_state <= FSM_CNF_RXGXB1;
end
FSM_CNF_TXPLL2: // Set the TXPLL to tx_link_rate_mem link rate
if(!rcnf_busy)
begin
rcnf_address <= ADDR_TXPLL_L_CNT;
rcnf_mask <= MASK_TXPLL_L_CNT;
rcnf_data <= {29'd0,L_COUNTER_FPLL[tx_link_rate_mem],1'b0};
rcnf_reconfig <= 1'b1;
fsm_state <= FSM_CAL_TXPLL1;
end
FSM_CAL_TXPLL1: // Get access to TXPLL config bus
if(!rcnf_busy)
begin
rcnf_req_cbus <= 1'b1;
fsm_state <= FSM_CAL_TXPLL2;
end
FSM_CAL_TXPLL2: // Calibrate TXPLL
if(!rcnf_busy)
begin
rcnf_address <= ADDR_TXPLL_CALIB;
rcnf_mask <= MASK_TXPLL_CALIB;
rcnf_data <= 32'h2;
rcnf_reconfig <= 1'b1;
fsm_state <= FSM_CAL_TXPLL3;
end
FSM_CAL_TXPLL3: // Release TXPLL config bus
if(!rcnf_busy)
begin
rcnf_rel_cbus <= 1'b1;
fsm_state <= FSM_CAL_TXPLL4;
end
FSM_CAL_TXPLL4: // Wait for TXPLL calibration end
if(!rcnf_busy)
begin
rcnf_wcalib <= 1'b1;
fsm_state <= FSM_MEM_TXPLL1;
end
FSM_MEM_TXPLL1: // Store TXPLL link rate related calibration results
if(!rcnf_busy)
begin
rcnf_scalib <= 1'b1;
fsm_state <= FSM_MEM_TXPLL2;
end
FSM_MEM_TXPLL2: // Goto next link rate
if(!rcnf_busy)
begin
tx_link_rate_mem <= tx_link_rate_mem + 1'd1;
fsm_state <= FSM_CNF_TXPLL1;
end
FSM_CNF_RXGXB1: // Set the RXGXB to rx_link_rate_mem link rate
if(rx_link_rate_mem < RX_RATES_NUM[1:0])
begin
if(~rx_cal_busy & ~tx_cal_busy)
begin
rx_lrate_busy <= 1'b1;
rcnf_address <= ADDR_L_PFD_COUNTER;
rcnf_mask <= MASK_L_PFD_COUNTER;
rcnf_data <= {29'd0,COUNTER_L_PFD[rx_link_rate_mem]};
rcnf_reconfig <= 1'b1;
fsm_state <= FSM_CNF_RXGXB2;
end
end
else
begin
rx_lrate_busy <= 1'b0;
fsm_state <= FSM_IDLE;
end
FSM_CNF_RXGXB2: // Set the RXGXB to rx_link_rate_mem link rate
if(!rcnf_busy)
begin
rcnf_address <= ADDR_L_PD_COUNTER;
rcnf_mask <= MASK_L_PD_COUNTER;
rcnf_data <= {26'd0,COUNTER_L_PD[rx_link_rate_mem],3'd0};
rcnf_reconfig <= 1'b1;
fsm_state <= FSM_CNF_RXGXB3;
end
FSM_CNF_RXGXB3: // Set the RXGXB to rx_link_rate_mem link rate
if(!rcnf_busy)
begin
rcnf_address <= ADDR_M_COUNTER;
rcnf_mask <= MASK_M_COUNTER;
rcnf_data <= {24'd0,COUNTER_M[rx_link_rate_mem]};
rcnf_reconfig <= 1'b1;
fsm_state <= FSM_CNF_RXGXB_NEXTLANE;
end
FSM_CNF_RXGXB_NEXTLANE:
if(!rcnf_busy)
begin
if(lane_idx + 1'd1 < RX_LANES)
begin
// Configure next RX lane
lane_idx <= lane_idx + 2'd1;
fsm_state <= FSM_CNF_RXGXB1;
end
else
begin
lane_idx <= 2'd0;
fsm_state <= FSM_CAL_RXGXB1;
end
end
FSM_CAL_RXGXB1: // Get access to RXGXB config bus
if(!rcnf_busy)
begin
rcnf_req_cbus <= 1'b1;
fsm_state <= FSM_CAL_RXGXB2;
end
FSM_CAL_RXGXB2: // Calibrate RXGXB
if(!rcnf_busy)
begin
rcnf_address <= ADDR_CALIB;
rcnf_mask <= MASK_CALIB;
rcnf_data <= 32'h6; // Recalibrate CDR and offset cancellation
rcnf_reconfig <= 1'b1;
fsm_state <= FSM_CAL_RXGXB3;
end
FSM_CAL_RXGXB3: // To indicate the cal code that this is a new chgpmp current request and to calibrate based off of that initial value
if(!rcnf_busy)
begin
rcnf_address <= ADDR_CP_CALIB;
rcnf_mask <= MASK_CP_CALIB;
rcnf_data <= {24'd0,1'd0,7'd0};
rcnf_reconfig <= 1'b1;
fsm_state <= FSM_CAL_RXGXB4;
end
FSM_CAL_RXGXB4: // Release RXGXB config bus
if(!rcnf_busy)
begin
rcnf_rel_cbus <= 1'b1;
fsm_state <= FSM_CAL_RXGXB5;
end
FSM_CAL_RXGXB5: // Wait for RXGXB calibration end
if(!rcnf_busy)
begin
rcnf_wcalib <= 1'b1;
fsm_state <= FSM_MEM_RXGXB;
end
FSM_MEM_RXGXB: // Store RXGXB link rate related calibration results
if(!rcnf_busy)
begin
rcnf_scalib <= 1'b1;
fsm_state <= FSM_CAL_RXGXB_NEXTLANE;
end
FSM_CAL_RXGXB_NEXTLANE:
if(!rcnf_busy)
begin
if(lane_idx + 1'd1 < RX_LANES)
begin
// Calibrate next RX lane
lane_idx <= lane_idx + 2'd1;
fsm_state <= FSM_CAL_RXGXB1;
end
else
begin
// Goto next link rate
lane_idx <= 2'd0;
rx_link_rate_mem <= rx_link_rate_mem + 1'd1;
fsm_state <= FSM_CNF_RXGXB1;
end
end
FSM_IDLE:
begin
write_cnt <= 3'h0;
lane_idx <= 2'h0;
if(~rx_xcvr_busy & ~tx_xcvr_busy)
begin
// Start a reconfig if either RX or TX requests it
// (RX has precedence, do not serve RX and TX at the same time)
if(rx_new_linkrate & rx_reset_ack_rrr)
begin
rx_lrate_busy <= 1'b1;
fsm_state <= FSM_START_RX_LINKRATE;
if(rx_link_rate == 8'h06)
rx_link_rate_mem <= 2'b00; // RBR
else if(rx_link_rate == 8'h0a)
rx_link_rate_mem <= 2'b01; // HBR
else if(rx_link_rate == 8'h14)
rx_link_rate_mem <= 2'b10; // HBR2
else
begin
// Unsupported link rate
rx_lrate_busy <= 1'b0;
fsm_state <= FSM_IDLE;
end
end
else if(tx_new_linkrate & tx_reset_ack_rrr)
begin
tx_lrate_busy <= 1'b1;
fsm_state <= FSM_START_TX_LINKRATE;
if(tx_link_rate == 8'h06)
tx_link_rate_mem <= 2'b00; // RBR
else if(tx_link_rate == 8'h0a)
tx_link_rate_mem <= 2'b01; // HBR
else if(tx_link_rate == 8'h14)
tx_link_rate_mem <= 2'b10; // HBR2
else
begin
// Unsupported link rate
tx_lrate_busy <= 1'b0;
fsm_state <= FSM_IDLE;
end
end
else if(tx_new_analog & tx_reset_ack_rrr)
begin
vod_mem <= vod_mapped;
emp_mem <= emp_mapped;
tx_analog_busy <= 1'b1;
rcnf_req_cbus <= 1'b1; // For TX analog reconfiguration, request the control bus
fsm_state <= FSM_START_TX_ANALOG;
end
end
end
FSM_START_RX_LINKRATE: // Start RX linkrate reconfig
begin
feature_idx <= FEAT_RX_REFCLK1; // Start programming from this feature
if(!rcnf_busy)
fsm_state <= FSM_FEAT_RECONFIG;
end
FSM_START_TX_LINKRATE: // Start TX linkrate reconfig
begin
feature_idx <= FEAT_TX_REFCLK1; // Start programming from this feature
if(!rcnf_busy)
fsm_state <= FSM_FEAT_RECONFIG;
end
FSM_START_TX_ANALOG: // Start TX analog reconfig
begin
feature_idx <= FEAT_TX_VOD; // Start programming from this feature
if(!rcnf_busy)
fsm_state <= FSM_FEAT_RECONFIG;
end
FSM_FEAT_RECONFIG: // Reconfigure a single feature
begin
// Setup the registers feeding the low-level FSM based on feature_idx
rcnf_reconfig <= 1'b1;
write_cnt <= write_cnt + 1'd1;
fsm_state <= FSM_WAIT_FOR_BUSY_LOW;
case(feature_idx)
FEAT_RX_REFCLK1: // RX GXB
begin
rcnf_address <= ADDR_L_PFD_COUNTER;
rcnf_mask <= MASK_L_PFD_COUNTER;
rcnf_data <= {29'd0,COUNTER_L_PFD[rx_link_rate_mem]};
end
FEAT_RX_REFCLK2: // RX GXB
begin
rcnf_address <= ADDR_L_PD_COUNTER;
rcnf_mask <= MASK_L_PD_COUNTER;
rcnf_data <= {26'd0,COUNTER_L_PD[rx_link_rate_mem],3'd0};
end
FEAT_RX_REFCLK3: // RX GXB
begin
rcnf_address <= ADDR_M_COUNTER;
rcnf_mask <= MASK_M_COUNTER;
rcnf_data <= {24'd0,COUNTER_M[rx_link_rate_mem]};
end
FEAT_RX_REFCLK4: // RX GXB
begin
rcnf_reconfig <= 1'b0;
rcnf_lcalib <= 1'b1; // Re-load calibration results
end
FEAT_TX_VOD: // TX analog PMA
begin
rcnf_address <= ADDR_VOD_OUTPUT_SWING_CTRL;
rcnf_mask <= MASK_VOD_OUTPUT_SWING_CTRL;
rcnf_data <= {27'd0,vod_mem[5*lane_idx +:5]};
end
FEAT_TX_EMP1: // TX analog PMA
begin
rcnf_address <= ADDR_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP;
rcnf_mask <= MASK_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP;
rcnf_data <= {25'd0,emp_mem[6*lane_idx+5],1'b0,emp_mem[6*lane_idx +:5]};
end
FEAT_TX_EMP2: // TX analog PMA
begin
rcnf_address <= ADDR_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP;
rcnf_mask <= MASK_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP;
rcnf_data <= {26'd0,1'b1,1'b0,4'd0};
end
FEAT_TX_EMP3: // TX analog PMA
begin
rcnf_address <= ADDR_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T;
rcnf_mask <= MASK_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T;
rcnf_data <= {26'd0,1'b1,5'd0};
end
FEAT_TX_EMP4: // TX analog PMA
begin
rcnf_address <= ADDR_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T;
rcnf_mask <= MASK_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T;
rcnf_data <= {27'd0,1'b1,1'b0,3'd0};
end
FEAT_TX_REFCLK1: // TXPLL
begin
rcnf_address <= ADDR_TXPLL_M_CNT;
rcnf_mask <= MASK_TXPLL_M_CNT;
rcnf_data <= {24'd0,M_COUNTER_FPLL[tx_link_rate_mem]};
end
FEAT_TX_REFCLK2: // TXPLL
begin
rcnf_address <= ADDR_TXPLL_L_CNT;
rcnf_mask <= MASK_TXPLL_L_CNT;
rcnf_data <= {29'd0,L_COUNTER_FPLL[tx_link_rate_mem],1'b0};
end
FEAT_TX_REFCLK3: // TXPLL
begin
rcnf_reconfig <= 1'b0;
rcnf_lcalib <= 1'b1; // Re-load calibration results
end
endcase
end
FSM_WAIT_FOR_BUSY_LOW:
if(!rcnf_busy)
begin
if(rx_lrate_busy)
fsm_state <= FSM_NEXT_RX_LRATE_FEATURE;
else if(tx_lrate_busy)
fsm_state <= FSM_NEXT_TX_LRATE_FEATURE;
else
fsm_state <= FSM_NEXT_TX_ANALOG_FEATURE;
end
FSM_NEXT_RX_LRATE_FEATURE:
begin
if(write_cnt == 3'd4)
fsm_state <= FSM_END_RECONFIG;
else
begin
// Next feature
feature_idx <= feature_idx + 4'd1;
fsm_state <= FSM_FEAT_RECONFIG;
end
end
FSM_NEXT_TX_LRATE_FEATURE:
begin
if(write_cnt == 3'd3)
fsm_state <= FSM_END_RECONFIG;
else
begin
// Next feature
feature_idx <= feature_idx + 4'd1;
fsm_state <= FSM_FEAT_RECONFIG;
end
end
FSM_NEXT_TX_ANALOG_FEATURE:
begin
if(write_cnt == 3'd5)
fsm_state <= FSM_END_RECONFIG;
else
begin
// Next feature
feature_idx <= feature_idx + 4'd1;
fsm_state <= FSM_FEAT_RECONFIG;
end
end
FSM_END_RECONFIG:
if(!rcnf_busy)
fsm_state <= FSM_NEXT_LANE;
FSM_NEXT_LANE: // Reconfigure the features for all the lanes
begin
if((rx_lrate_busy & (lane_idx + 1 < RX_LANES)) |
(tx_analog_busy & (lane_idx + 1 < TX_LANES)))
begin
// Go to next lane
lane_idx <= lane_idx + 2'd1;
write_cnt <= 3'd0;
if(rx_lrate_busy)
fsm_state <= FSM_START_RX_LINKRATE;
else
begin
rcnf_req_cbus <= 1'b1;
fsm_state <= FSM_START_TX_ANALOG;
end
end
else
fsm_state <= FSM_END;
end
FSM_END:
begin
rx_lrate_busy <= 1'b0;
tx_lrate_busy <= 1'b0;
tx_analog_busy <= 1'b0;
fsm_state <= FSM_IDLE;
end
default:
fsm_state <= FSM_END;
endcase
end // if(reset)
end // always
// Instantiate the Avalon MM Master connected to the XCVR Reconfiguration Controller
wire rx_rcnf_busy, tx_rcnf_busy;
//RX
bitec_reconfig_avalon_mm_master
#(
.XCVR (1)
)
bitec_reconfig_avalon_mm_master_rx
(
.clk (clk),
.reset (reset),
.rcnf_req_cbus (rcnf_req_cbus),
.rcnf_rel_cbus (rcnf_rel_cbus),
.rcnf_wcalib (rcnf_wcalib),
.rcnf_scalib (rcnf_scalib),
.rcnf_lcalib (rcnf_lcalib),
.rcnf_reconfig (rcnf_reconfig),
.rcnf_en (rx_lrate_busy),
.rcnf_logical_ch (lane_idx),
.rcnf_address (rcnf_address),
.rcnf_data (rcnf_data),
.rcnf_mask (rcnf_mask),
.rcnf_linkrate (rx_link_rate_mem),
.rcnf_busy (rx_rcnf_busy),
.mgmt_chnum (rx_mgmt_chnum),
.mgmt_address (rx_mgmt_address),
.mgmt_writedata (rx_mgmt_writedata),
.mgmt_readdata (rx_mgmt_readdata),
.mgmt_write (rx_mgmt_write),
.mgmt_read (rx_mgmt_read),
.mgmt_waitrequest (rx_mgmt_waitrequest),
.cal_busy (rx_xcvr_cal_busy)
);
// TX
bitec_reconfig_avalon_mm_master
#(
.XCVR (1)
)
bitec_reconfig_avalon_mm_master_tx
(
.clk (clk),
.reset (reset),
.rcnf_req_cbus (rcnf_req_cbus),
.rcnf_rel_cbus (rcnf_rel_cbus),
.rcnf_wcalib (rcnf_wcalib),
.rcnf_scalib (rcnf_scalib),
.rcnf_lcalib (rcnf_lcalib),
.rcnf_reconfig (rcnf_reconfig),
.rcnf_en (tx_analog_busy),
.rcnf_logical_ch (lane_idx),
.rcnf_address (rcnf_address),
.rcnf_data (rcnf_data),
.rcnf_mask (rcnf_mask),
.rcnf_linkrate (tx_link_rate_mem),
.rcnf_busy (tx_rcnf_busy),
.mgmt_chnum (tx_mgmt_chnum),
.mgmt_address (tx_mgmt_address),
.mgmt_writedata (tx_mgmt_writedata),
.mgmt_readdata (tx_mgmt_readdata),
.mgmt_write (tx_mgmt_write),
.mgmt_read (tx_mgmt_read),
.mgmt_waitrequest (tx_mgmt_waitrequest),
.cal_busy (tx_xcvr_cal_busy)
);
// Instantiate the Avalon MM Master connected to the TX PLL Reconfiguration Controller
wire txpll_rcnf_busy;
bitec_reconfig_avalon_mm_master
#(
.XCVR (0)
)
bitec_reconfig_avalon_mm_master_txpll
(
.clk (clk),
.reset (reset),
.rcnf_req_cbus (rcnf_req_cbus),
.rcnf_rel_cbus (rcnf_rel_cbus),
.rcnf_wcalib (rcnf_wcalib),
.rcnf_scalib (rcnf_scalib),
.rcnf_lcalib (rcnf_lcalib),
.rcnf_reconfig (rcnf_reconfig),
.rcnf_en (tx_lrate_busy),
.rcnf_logical_ch (2'b00),
.rcnf_address (rcnf_address),
.rcnf_data (rcnf_data),
.rcnf_mask (rcnf_mask),
.rcnf_linkrate (tx_link_rate_mem),
.rcnf_busy (txpll_rcnf_busy),
.mgmt_chnum (),
.mgmt_address (txpll_mgmt_address),
.mgmt_writedata (txpll_mgmt_writedata),
.mgmt_readdata (txpll_mgmt_readdata),
.mgmt_write (txpll_mgmt_write),
.mgmt_read (txpll_mgmt_read),
.mgmt_waitrequest (txpll_mgmt_waitrequest),
.cal_busy (tx_pll_cal_busy)
);
assign rcnf_busy = tx_lrate_busy ? txpll_rcnf_busy : (rx_rcnf_busy | tx_rcnf_busy);
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//----------------------------------------------
// Avalon MM Master for driving the Reconfiguration
// (XCVR or TXPLL) management interface
//----------------------------------------------
module bitec_reconfig_avalon_mm_master
#(
parameter XCVR = 1 // Usage: 0 = TXPLL, 1 = XCVR
)
(
input wire clk,
input wire reset,
// Command strobes
input wire rcnf_req_cbus, // Assert for 1 clk cycle to get access to internal config bus
input wire rcnf_rel_cbus, // Assert for 1 clk cycle to release internal config bus
input wire rcnf_wcalib, // Assert for 1 clk cycle to wait for calibration end
input wire rcnf_scalib, // Assert for 1 clk cycle to save linkrate related calibration results
input wire rcnf_lcalib, // Assert for 1 clk cycle to load back linkrate related calibration results
input wire rcnf_reconfig, // Assert for 1 clk cycle to reconfig a single register
input wire rcnf_en, // Must be asserted for command strobes to be accepted
// Command parameters
input wire [1:0] rcnf_logical_ch, // Logical channel number
input wire [9:0] rcnf_address, // Register address
input wire [31:0] rcnf_data, // Value of data to write
input wire [31:0] rcnf_mask, // Mask for data to write (bits at 1 get written)
input wire [1:0] rcnf_linkrate, // Link rate: 0 = RBR .... 3 = HBR3
output wire rcnf_busy, // Asserted while operation is taking place
// Reconfig management interface
output reg [1:0] mgmt_chnum,
output reg [9:0] mgmt_address,
output reg [31:0] mgmt_writedata,
input wire [31:0] mgmt_readdata,
output reg mgmt_write,
output reg mgmt_read,
input wire mgmt_waitrequest,
input wire cal_busy
);
// XCVR Reconfiguration controller register addresses
localparam ADDR_XCVR_BUS_ARB = 10'h000,
ADDR_XCVR_CDR_VCO_SPEED_FIX_7_6 = 10'h132,
ADDR_XCVR_CHGPMP_PD_UP = 10'h133,
ADDR_XCVR_CDR_VCO_SPEED_FIX_4 = 10'h134,
ADDR_XCVR_LF_PD_PFD = 10'h135, //VCO_SPEED_FIX_5
ADDR_XCVR_CDR_VCO_SPEED_FIX = 10'h136, //VCO_SPEED_FIX_3_0
ADDR_XCVR_CDR_VCO_SPEED = 10'h137,
ADDR_XCVR_CHGPMP_PD_DN = 10'h139,
ADDR_XCVR_CAL_BUSY = 10'h281;
// TXPLL Reconfiguration controller register masks
localparam MASK_XCVR_LF_PD_PFD = 32'h0000_004f,
MASK_XCVR_CDR_VCO_SPEED_FIX_7_6 = 32'h0000_00F7,
MASK_XCVR_CDR_VCO_SPEED_FIX_4 = 32'h0000_00F7,
MASK_XCVR_CDR_VCO_SPEED_FIX = 32'h0000_000f,
MASK_XCVR_CDR_VCO_SPEED = 32'h0000_007c,
MASK_XCVR_CHGPMP_PD_UP = 32'h0000_00E0,
MASK_XCVR_CHGPMP_PD_DN = 32'h0000_00BF;
// TXPLL Reconfiguration controller register addresses
localparam ADDR_TXPLL_BUS_ARB = 10'h000,
ADDR_TXPLL_VCO_BAND1 = 10'h10A,
ADDR_TXPLL_VCO_BAND2 = 10'h10B,
ADDR_TXPLL_CAL_BUSY = 10'h280;
// TXPLL Reconfiguration controller register masks
localparam MASK_TXPLL_VCO_BAND1 = 32'h0000_001f,
MASK_TXPLL_VCO_BAND2 = 32'h0000_00f8;
// State variables
localparam FSM_IDLE = 6'd0,
FSM_REQBUS_RD = 6'd1,
FSM_REQBUS_WR = 6'd2,
FSM_RELBUS_RD = 6'd3,
FSM_RELBUS_WR = 6'd4,
FSM_WCAL_RD = 6'd5,
FSM_WCAL_TST = 6'd6,
FSM_SCAL_RD1 = 6'd7,
FSM_SCAL_RD2 = 6'd8,
FSM_SCAL_RD3 = 6'd9,
FSM_SCAL_RD4 = 6'd10,
FSM_SCAL_RD5 = 6'd11,
FSM_SCAL_RD6 = 6'd12,
FSM_SCAL_RD7 = 6'd13,
FSM_SCAL_RD8 = 6'd14,
FSM_SCAL_RD9 = 6'd15,
FSM_LCAL_RD1 = 6'd16,
FSM_LCAL_WR1 = 6'd17,
FSM_LCAL_RD2 = 6'd18,
FSM_LCAL_WR2 = 6'd19,
FSM_LCAL_RD3 = 6'd20,
FSM_LCAL_WR3 = 6'd21,
FSM_LCAL_RD4 = 6'd22,
FSM_LCAL_WR4 = 6'd23,
FSM_LCAL_RD5 = 6'd24,
FSM_LCAL_WR5 = 6'd25,
FSM_LCAL_RD6 = 6'd26,
FSM_LCAL_WR6 = 6'd27,
FSM_LCAL_RD7 = 6'd28,
FSM_LCAL_WR7 = 6'd29,
FSM_LCAL_RD8 = 6'd30,
FSM_LCAL_WR8 = 6'd31,
FSM_LCAL_RD9 = 6'd32,
FSM_LCAL_WR9 = 6'd33,
FSM_READ = 6'd34,
FSM_WRITE = 6'd35,
FSM_END = 6'd36;
localparam CALIB_RATES = 4; // 4 link rates
localparam CALIB_LANES = XCVR ? 4 : 1; // max 4 lanes
localparam CALIB_VALUES = XCVR ? 7 : 2; // number of calib result registers to store
localparam CALIB_RES_SIZE = CALIB_RATES * CALIB_LANES * CALIB_VALUES;
reg [5:0] state;
reg [7:0] calib_res [CALIB_RES_SIZE-1:0];
always @ (posedge clk or posedge reset)
if(reset)
begin
state <= FSM_IDLE;
mgmt_chnum <= 2'd0;
mgmt_address <= 10'd0;
mgmt_write <= 1'b0;
mgmt_read <= 1'b0;
mgmt_writedata <= 32'd0;
end
else
begin
mgmt_write <= 1'b0;
mgmt_read <= 1'b0;
case (state)
FSM_IDLE:
if(rcnf_en)
begin
if(rcnf_req_cbus)
state <= FSM_REQBUS_RD;
if(rcnf_reconfig)
state <= FSM_READ;
if(rcnf_rel_cbus)
state <= FSM_RELBUS_RD;
if(rcnf_wcalib)
state <= FSM_WCAL_RD;
if(rcnf_scalib)
state <= XCVR ? FSM_SCAL_RD3 : FSM_SCAL_RD1;
if(rcnf_lcalib)
state <= XCVR ? FSM_LCAL_RD3 : FSM_LCAL_RD1;
end
FSM_REQBUS_RD: // Grab AVMM control (read)
begin
if(mgmt_read & !mgmt_waitrequest)
state <= FSM_REQBUS_WR;
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= XCVR ? ADDR_XCVR_BUS_ARB : ADDR_TXPLL_BUS_ARB;
mgmt_read <= 1'b1;
end
end
FSM_REQBUS_WR: // Grab AVMM control (modify-write)
begin
if(mgmt_write & !mgmt_waitrequest)
state <= FSM_IDLE;
else
begin
mgmt_writedata <= (mgmt_readdata & ~32'h0000_0001) | 32'h0000_0000;
mgmt_write <= 1'b1;
end
end
FSM_RELBUS_RD: // Release AVMM control (read)
begin
if(mgmt_read & !mgmt_waitrequest)
state <= FSM_RELBUS_WR;
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= XCVR ? ADDR_XCVR_BUS_ARB : ADDR_TXPLL_BUS_ARB;
mgmt_read <= 1'b1;
end
end
FSM_RELBUS_WR: // Release AVMM control (modify-write)
begin
if(mgmt_write & !mgmt_waitrequest)
state <= FSM_IDLE;
else
begin
mgmt_writedata <= (mgmt_readdata & ~32'h0000_0001) | 32'h0000_0001;
mgmt_write <= 1'b1;
end
end
FSM_WCAL_RD: // Read calibration status
if(~cal_busy)
state <= FSM_IDLE; // rx_cal_busy or pll_cal_busy is 0
else
state <= FSM_WCAL_RD; // Still calibrating
FSM_SCAL_RD1: // Read TXPLL calibration results
begin
if(mgmt_read & !mgmt_waitrequest)
begin
calib_res[rcnf_linkrate*CALIB_VALUES+0] <= (mgmt_readdata[7:0] & MASK_TXPLL_VCO_BAND1[7:0]);
state <= FSM_SCAL_RD2;
end
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_TXPLL_VCO_BAND1;
mgmt_read <= 1'b1;
end
end
FSM_SCAL_RD2:
begin
if(mgmt_read & !mgmt_waitrequest)
begin
calib_res[rcnf_linkrate*CALIB_VALUES+1] <= (mgmt_readdata[7:0] & MASK_TXPLL_VCO_BAND2[7:0]);
state <= FSM_IDLE;
end
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_TXPLL_VCO_BAND2;
mgmt_read <= 1'b1;
end
end
FSM_SCAL_RD3: // Read XCVR calibration results
begin
if(mgmt_read & !mgmt_waitrequest)
begin
calib_res[rcnf_linkrate*CALIB_VALUES+rcnf_logical_ch*CALIB_RATES*CALIB_VALUES+0] <= (mgmt_readdata[7:0] & MASK_XCVR_CDR_VCO_SPEED[7:0]);
state <= FSM_SCAL_RD4;
end
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_CDR_VCO_SPEED;
mgmt_read <= 1'b1;
end
end
FSM_SCAL_RD4:
begin
if(mgmt_read & !mgmt_waitrequest)
begin
calib_res[rcnf_linkrate*CALIB_VALUES+rcnf_logical_ch*CALIB_RATES*CALIB_VALUES+1] <= (mgmt_readdata[7:0] & MASK_XCVR_CDR_VCO_SPEED_FIX[7:0]);
state <= FSM_SCAL_RD5;
end
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_CDR_VCO_SPEED_FIX;
mgmt_read <= 1'b1;
end
end
FSM_SCAL_RD5:
begin
if(mgmt_read & !mgmt_waitrequest)
begin
calib_res[rcnf_linkrate*CALIB_VALUES+rcnf_logical_ch*CALIB_RATES*CALIB_VALUES+2] <= (mgmt_readdata[7:0] & MASK_XCVR_CHGPMP_PD_UP[7:0]);
state <= FSM_SCAL_RD6;
end
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_CHGPMP_PD_UP;
mgmt_read <= 1'b1;
end
end
FSM_SCAL_RD6:
begin
if(mgmt_read & !mgmt_waitrequest)
begin
calib_res[rcnf_linkrate*CALIB_VALUES+rcnf_logical_ch*CALIB_RATES*CALIB_VALUES+3] <= (mgmt_readdata[7:0] & MASK_XCVR_CHGPMP_PD_DN[7:0]);
state <= FSM_SCAL_RD7;
end
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_CHGPMP_PD_DN;
mgmt_read <= 1'b1;
end
end
FSM_SCAL_RD7:
begin
if(mgmt_read & !mgmt_waitrequest)
begin
calib_res[rcnf_linkrate*CALIB_VALUES+rcnf_logical_ch*CALIB_RATES*CALIB_VALUES+4] <= (mgmt_readdata[7:0] & MASK_XCVR_LF_PD_PFD[7:0]);
state <= FSM_SCAL_RD8;
end
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_LF_PD_PFD;
mgmt_read <= 1'b1;
end
end
FSM_SCAL_RD8:
begin
if(mgmt_read & !mgmt_waitrequest)
begin
calib_res[rcnf_linkrate*CALIB_VALUES+rcnf_logical_ch*CALIB_RATES*CALIB_VALUES+5] <= (mgmt_readdata[7:0] & MASK_XCVR_CDR_VCO_SPEED_FIX_7_6[7:0]);
state <= FSM_SCAL_RD9;
end
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_CDR_VCO_SPEED_FIX_7_6;
mgmt_read <= 1'b1;
end
end
FSM_SCAL_RD9:
begin
if(mgmt_read & !mgmt_waitrequest)
begin
calib_res[rcnf_linkrate*CALIB_VALUES+rcnf_logical_ch*CALIB_RATES*CALIB_VALUES+6] <= (mgmt_readdata[7:0] & MASK_XCVR_CDR_VCO_SPEED_FIX_4[7:0]);
state <= FSM_IDLE;
end
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_CDR_VCO_SPEED_FIX_4;
mgmt_read <= 1'b1;
end
end
FSM_LCAL_RD1: // Load back TXPLL calibration results
begin
if(mgmt_read & !mgmt_waitrequest)
state <= FSM_LCAL_WR1;
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_TXPLL_VCO_BAND1;
mgmt_read <= 1'b1;
end
end
FSM_LCAL_WR1:
begin
if(mgmt_write & !mgmt_waitrequest)
state <= FSM_LCAL_RD2;
else
begin
mgmt_writedata <= (mgmt_readdata & ~MASK_TXPLL_VCO_BAND1) | calib_res[rcnf_linkrate*CALIB_VALUES+0];
mgmt_write <= 1'b1;
end
end
FSM_LCAL_RD2:
begin
if(mgmt_read & !mgmt_waitrequest)
state <= FSM_LCAL_WR2;
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_TXPLL_VCO_BAND2;
mgmt_read <= 1'b1;
end
end
FSM_LCAL_WR2:
begin
if(mgmt_write & !mgmt_waitrequest)
state <= FSM_IDLE;
else
begin
mgmt_writedata <= (mgmt_readdata & ~MASK_TXPLL_VCO_BAND2) | calib_res[rcnf_linkrate*CALIB_VALUES+1];
mgmt_write <= 1'b1;
end
end
FSM_LCAL_RD3: // Load back GXB calibration results
begin
if(mgmt_read & !mgmt_waitrequest)
state <= FSM_LCAL_WR3;
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_CDR_VCO_SPEED;
mgmt_read <= 1'b1;
end
end
FSM_LCAL_WR3:
begin
if(mgmt_write & !mgmt_waitrequest)
state <= FSM_LCAL_RD4;
else
begin
mgmt_writedata <= (mgmt_readdata & ~MASK_XCVR_CDR_VCO_SPEED) | calib_res[rcnf_linkrate*CALIB_VALUES+0];
mgmt_write <= 1'b1;
end
end
FSM_LCAL_RD4:
begin
if(mgmt_read & !mgmt_waitrequest)
state <= FSM_LCAL_WR4;
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_CDR_VCO_SPEED_FIX;
mgmt_read <= 1'b1;
end
end
FSM_LCAL_WR4:
begin
if(mgmt_write & !mgmt_waitrequest)
state <= FSM_LCAL_RD5;
else
begin
mgmt_writedata <= (mgmt_readdata & ~MASK_XCVR_CDR_VCO_SPEED_FIX) | calib_res[rcnf_linkrate*CALIB_VALUES+1];
mgmt_write <= 1'b1;
end
end
FSM_LCAL_RD5:
begin
if(mgmt_read & !mgmt_waitrequest)
state <= FSM_LCAL_WR5;
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_CHGPMP_PD_UP;
mgmt_read <= 1'b1;
end
end
FSM_LCAL_WR5:
begin
if(mgmt_write & !mgmt_waitrequest)
state <= FSM_LCAL_RD6;
else
begin
mgmt_writedata <= (mgmt_readdata & ~MASK_XCVR_CHGPMP_PD_UP) | calib_res[rcnf_linkrate*CALIB_VALUES+2];
mgmt_write <= 1'b1;
end
end
FSM_LCAL_RD6:
begin
if(mgmt_read & !mgmt_waitrequest)
state <= FSM_LCAL_WR6;
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_CHGPMP_PD_DN;
mgmt_read <= 1'b1;
end
end
FSM_LCAL_WR6:
begin
if(mgmt_write & !mgmt_waitrequest)
state <= FSM_LCAL_RD7;
else
begin
mgmt_writedata <= (mgmt_readdata & ~MASK_XCVR_CHGPMP_PD_DN) | calib_res[rcnf_linkrate*CALIB_VALUES+3];
mgmt_write <= 1'b1;
end
end
FSM_LCAL_RD7:
begin
if(mgmt_read & !mgmt_waitrequest)
state <= FSM_LCAL_WR7;
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_LF_PD_PFD;
mgmt_read <= 1'b1;
end
end
FSM_LCAL_WR7:
begin
if(mgmt_write & !mgmt_waitrequest)
state <= FSM_LCAL_RD8;
else
begin
mgmt_writedata <= (mgmt_readdata & ~MASK_XCVR_LF_PD_PFD) | calib_res[rcnf_linkrate*CALIB_VALUES+4];
mgmt_write <= 1'b1;
end
end
FSM_LCAL_RD8:
begin
if(mgmt_read & !mgmt_waitrequest)
state <= FSM_LCAL_WR8;
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_CDR_VCO_SPEED_FIX_7_6;
mgmt_read <= 1'b1;
end
end
FSM_LCAL_WR8:
begin
if(mgmt_write & !mgmt_waitrequest)
state <= FSM_LCAL_RD9;
else
begin
mgmt_writedata <= (mgmt_readdata & ~MASK_XCVR_CDR_VCO_SPEED_FIX_7_6) | calib_res[rcnf_linkrate*CALIB_VALUES+5];
mgmt_write <= 1'b1;
end
end
FSM_LCAL_RD9:
begin
if(mgmt_read & !mgmt_waitrequest)
state <= FSM_LCAL_WR9;
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= ADDR_XCVR_CDR_VCO_SPEED_FIX_4;
mgmt_read <= 1'b1;
end
end
FSM_LCAL_WR9:
begin
if(mgmt_write & !mgmt_waitrequest)
state <= FSM_IDLE;
else
begin
mgmt_writedata <= (mgmt_readdata & ~MASK_XCVR_CDR_VCO_SPEED_FIX_4) | calib_res[rcnf_linkrate*CALIB_VALUES+6];
mgmt_write <= 1'b1;
end
end
FSM_READ: // Single register read
begin
if(mgmt_read & !mgmt_waitrequest)
state <= FSM_WRITE;
else
begin
mgmt_chnum <= rcnf_logical_ch;
mgmt_address <= rcnf_address;
mgmt_read <= 1'b1;
end
end
FSM_WRITE: // Single register modify-write
begin
if(mgmt_write & !mgmt_waitrequest)
state <= FSM_IDLE;
else
begin
mgmt_writedata <= (mgmt_readdata & ~rcnf_mask) | rcnf_data;
mgmt_write <= 1'b1;
end
end
endcase
end
assign rcnf_busy = (state != FSM_IDLE) | rcnf_req_cbus | rcnf_rel_cbus | rcnf_reconfig | rcnf_wcalib | rcnf_scalib | rcnf_lcalib;
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//----------------------------------------------
// Map DisplayPort Voltage swing / Pre-emphasis
// to transceiver VOD / EMP settings
// for Arria 10 GX
//
// 1st pre-tap always supposed set to 0
// 2nd pre-tap always supposed set to 0
// 2nd post-tap always supposed set to 0
//----------------------------------------------
module dp_analog_mappings
(
input wire [1:0] vod,
input wire [1:0] pree,
output reg [4:0] out_vod,
output reg [5:0] out_pree_post_tap1 // bit5 is polarity, 1=neg 2=pos
);
always @(*)
case (vod)
2'b00 : // 400mv
begin
case(pree)
2'b00 : // (0db)
begin
out_vod = 5'd13;
out_pree_post_tap1 = {1'b1,5'd0};
end
2'b01 : // (3.5db)
begin
out_vod = 5'd19;
out_pree_post_tap1 = {1'b1,5'd6};
end
2'b10 : // (6db)
begin
out_vod = 5'd25;
out_pree_post_tap1 = {1'b1,5'd12};
end
2'b11 : // (9db)
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1,5'd19};
end
endcase
end
2'b01 : // 600mv
begin
case(pree)
2'b00 : // (0db)
begin
out_vod = 5'd19;
out_pree_post_tap1 = {1'b1,5'd0};
end
2'b01 : // (3.5db)
begin
out_vod = 5'd28;
out_pree_post_tap1 = {1'b1,5'd9};
end
2'b10 : // (6db)
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1,5'd14};
end
2'b11 : // unused
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1,5'd14};
end
endcase
end
2'b10 : // 800mv
begin
case(pree)
2'b00 : // (0db)
begin
out_vod = 5'd25;
out_pree_post_tap1 = {1'b1,5'd0};
end
2'b01 : // (3.5db)
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1,5'd6};
end
2'b10 : // unused
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1,5'd6};
end
2'b11 : // unused
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1,5'd6};
end
endcase
end
2'b11 : // 1200mv
begin
case(pree)
2'b00 : // (0db)
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1,5'd0};
end
2'b01 : //
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1,5'd0};
end
2'b10 : // unused
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1,5'd0};
end
2'b11 : // unused
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1,5'd0};
end
endcase
end
endcase
endmodule
`default_nettype wire
|
// -----------------------------------------------------------------------
//
// Copyright 2004 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
/*
* Simulate a specific subset of the Altera Shift register
* (lpm_clshift).
*
* Not very ambitious, just the bare minimum.
*/
`timescale 1ns/10ps
module logshiftright(distance,
data,
result);
parameter lpm_type = "LPM_CLSHIFT";
parameter lpm_width = 32;
parameter lpm_widthdist = 5;
input wire [lpm_widthdist-1:0] distance;
input wire [lpm_width-1 :0] data;
output wire [lpm_width-1 :0] result;
assign result = data >> distance;
endmodule
|
(** * Extraction: Extracting ML from Coq *)
(** * Basic Extraction *)
(** In its simplest form, program extraction from Coq is completely straightforward. *)
(** First we say what language we want to extract into. Options are OCaml (the
most mature), Haskell (which mostly works), and Scheme (a bit out
of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Have a look at this
file now. *)
(* ############################################################## *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ############################################################## *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and somehow
prints out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
more declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
<<
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
>>
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ############################################################## *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. (Of
course, the parser is not certified in any interesting sense,
since we didn't prove anything about it.) *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DFRBP_PP_SYMBOL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRBP_PP_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_gclk_inv_224x.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// --------------------------------------------------
// File: bw_clk_gclk_inv_224x.behV
// --------------------------------------------------
//
module bw_clk_gclk_inv_224x (
clkout,
clkin );
output clkout;
input clkin;
assign clkout = ~( clkin );
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* RGMII PHY interface
*/
module rgmii_phy_if #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
// Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
parameter USE_CLK90 = "TRUE"
)
(
input wire clk,
input wire clk90,
input wire rst,
/*
* GMII interface to MAC
*/
output wire mac_gmii_rx_clk,
output wire mac_gmii_rx_rst,
output wire [7:0] mac_gmii_rxd,
output wire mac_gmii_rx_dv,
output wire mac_gmii_rx_er,
output wire mac_gmii_tx_clk,
output wire mac_gmii_tx_rst,
output wire mac_gmii_tx_clk_en,
input wire [7:0] mac_gmii_txd,
input wire mac_gmii_tx_en,
input wire mac_gmii_tx_er,
/*
* RGMII interface to PHY
*/
input wire phy_rgmii_rx_clk,
input wire [3:0] phy_rgmii_rxd,
input wire phy_rgmii_rx_ctl,
output wire phy_rgmii_tx_clk,
output wire [3:0] phy_rgmii_txd,
output wire phy_rgmii_tx_ctl,
/*
* Control
*/
input wire [1:0] speed
);
// receive
wire rgmii_rx_ctl_1;
wire rgmii_rx_ctl_2;
ssio_ddr_in #
(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(5)
)
rx_ssio_ddr_inst (
.input_clk(phy_rgmii_rx_clk),
.input_d({phy_rgmii_rxd, phy_rgmii_rx_ctl}),
.output_clk(mac_gmii_rx_clk),
.output_q1({mac_gmii_rxd[3:0], rgmii_rx_ctl_1}),
.output_q2({mac_gmii_rxd[7:4], rgmii_rx_ctl_2})
);
assign mac_gmii_rx_dv = rgmii_rx_ctl_1;
assign mac_gmii_rx_er = rgmii_rx_ctl_1 ^ rgmii_rx_ctl_2;
// transmit
reg rgmii_tx_clk_1 = 1'b1;
reg rgmii_tx_clk_2 = 1'b0;
reg rgmii_tx_clk_rise = 1'b1;
reg rgmii_tx_clk_fall = 1'b1;
reg [5:0] count_reg = 6'd0, count_next;
always @(posedge clk) begin
if (rst) begin
rgmii_tx_clk_1 <= 1'b1;
rgmii_tx_clk_2 <= 1'b0;
rgmii_tx_clk_rise <= 1'b1;
rgmii_tx_clk_fall <= 1'b1;
count_reg <= 0;
end else begin
rgmii_tx_clk_1 <= rgmii_tx_clk_2;
if (speed == 2'b00) begin
// 10M
count_reg <= count_reg + 1;
rgmii_tx_clk_rise <= 1'b0;
rgmii_tx_clk_fall <= 1'b0;
if (count_reg == 24) begin
rgmii_tx_clk_1 <= 1'b1;
rgmii_tx_clk_2 <= 1'b1;
rgmii_tx_clk_rise <= 1'b1;
end else if (count_reg >= 49) begin
rgmii_tx_clk_1 <= 1'b0;
rgmii_tx_clk_2 <= 1'b0;
rgmii_tx_clk_fall <= 1'b1;
count_reg <= 0;
end
end else if (speed == 2'b01) begin
// 100M
count_reg <= count_reg + 1;
rgmii_tx_clk_rise <= 1'b0;
rgmii_tx_clk_fall <= 1'b0;
if (count_reg == 2) begin
rgmii_tx_clk_1 <= 1'b1;
rgmii_tx_clk_2 <= 1'b1;
rgmii_tx_clk_rise <= 1'b1;
end else if (count_reg >= 4) begin
rgmii_tx_clk_2 <= 1'b0;
rgmii_tx_clk_fall <= 1'b1;
count_reg <= 0;
end
end else begin
// 1000M
rgmii_tx_clk_1 <= 1'b1;
rgmii_tx_clk_2 <= 1'b0;
rgmii_tx_clk_rise <= 1'b1;
rgmii_tx_clk_fall <= 1'b1;
end
end
end
reg [3:0] rgmii_txd_1 = 0;
reg [3:0] rgmii_txd_2 = 0;
reg rgmii_tx_ctl_1 = 1'b0;
reg rgmii_tx_ctl_2 = 1'b0;
reg gmii_clk_en = 1'b1;
always @* begin
if (speed == 2'b00) begin
// 10M
rgmii_txd_1 = mac_gmii_txd[3:0];
rgmii_txd_2 = mac_gmii_txd[3:0];
if (rgmii_tx_clk_2) begin
rgmii_tx_ctl_1 = mac_gmii_tx_en;
rgmii_tx_ctl_2 = mac_gmii_tx_en;
end else begin
rgmii_tx_ctl_1 = mac_gmii_tx_en ^ mac_gmii_tx_er;
rgmii_tx_ctl_2 = mac_gmii_tx_en ^ mac_gmii_tx_er;
end
gmii_clk_en = rgmii_tx_clk_fall;
end else if (speed == 2'b01) begin
// 100M
rgmii_txd_1 = mac_gmii_txd[3:0];
rgmii_txd_2 = mac_gmii_txd[3:0];
if (rgmii_tx_clk_2) begin
rgmii_tx_ctl_1 = mac_gmii_tx_en;
rgmii_tx_ctl_2 = mac_gmii_tx_en;
end else begin
rgmii_tx_ctl_1 = mac_gmii_tx_en ^ mac_gmii_tx_er;
rgmii_tx_ctl_2 = mac_gmii_tx_en ^ mac_gmii_tx_er;
end
gmii_clk_en = rgmii_tx_clk_fall;
end else begin
// 1000M
rgmii_txd_1 = mac_gmii_txd[3:0];
rgmii_txd_2 = mac_gmii_txd[7:4];
rgmii_tx_ctl_1 = mac_gmii_tx_en;
rgmii_tx_ctl_2 = mac_gmii_tx_en ^ mac_gmii_tx_er;
gmii_clk_en = 1;
end
end
wire phy_rgmii_tx_clk_new;
wire [3:0] phy_rgmii_txd_new;
wire phy_rgmii_tx_ctl_new;
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(1)
)
clk_oddr_inst (
.clk(USE_CLK90 == "TRUE" ? clk90 : clk),
.d1(rgmii_tx_clk_1),
.d2(rgmii_tx_clk_2),
.q(phy_rgmii_tx_clk)
);
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(5)
)
data_oddr_inst (
.clk(clk),
.d1({rgmii_txd_1, rgmii_tx_ctl_1}),
.d2({rgmii_txd_2, rgmii_tx_ctl_2}),
.q({phy_rgmii_txd, phy_rgmii_tx_ctl})
);
assign mac_gmii_tx_clk = clk;
assign mac_gmii_tx_clk_en = gmii_clk_en;
// reset sync
reg [3:0] tx_rst_reg = 4'hf;
assign mac_gmii_tx_rst = tx_rst_reg[0];
always @(posedge mac_gmii_tx_clk or posedge rst) begin
if (rst) begin
tx_rst_reg <= 4'hf;
end else begin
tx_rst_reg <= {1'b0, tx_rst_reg[3:1]};
end
end
reg [3:0] rx_rst_reg = 4'hf;
assign mac_gmii_rx_rst = rx_rst_reg[0];
always @(posedge mac_gmii_rx_clk or posedge rst) begin
if (rst) begin
rx_rst_reg <= 4'hf;
end else begin
rx_rst_reg <= {1'b0, rx_rst_reg[3:1]};
end
end
endmodule
|
//deps: sdram_controller3.v, IS42S16160.v
`timescale 1ns/1ps
module sdram_controller3_tb;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [12:0] DRAM_ADDR; // From controller of sdram_controller3.v
wire [1:0] DRAM_BA; // From controller of sdram_controller3.v
wire DRAM_CAS_N; // From controller of sdram_controller3.v
wire DRAM_CKE; // From controller of sdram_controller3.v
wire DRAM_CLK; // From controller of sdram_controller3.v
wire DRAM_CS_N; // From controller of sdram_controller3.v
wire [15:0] DRAM_DQ; // To/From controller of sdram_controller3.v
wire [1:0] DRAM_DQM; // From controller of sdram_controller3.v
wire DRAM_RAS_N; // From controller of sdram_controller3.v
wire DRAM_WE_N; // From controller of sdram_controller3.v
wire [31:0] data_out; // From controller of sdram_controller3.v
wire data_valid; // From controller of sdram_controller3.v
wire write_complete; // From controller of sdram_controller3.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg CLOCK_100; // To controller of sdram_controller3.v
reg CLOCK_100_del_3ns; // To controller of sdram_controller3.v
reg CLOCK_50; // To controller of sdram_controller3.v
reg [23:0] address; // To controller of sdram_controller3.v
reg [31:0] data_in; // To controller of sdram_controller3.v
reg req_read; // To controller of sdram_controller3.v
reg req_write; // To controller of sdram_controller3.v
reg rst; // To controller of sdram_controller3.v
// End of automatics
sdram_controller3 controller(/*AUTOINST*/
// Outputs
.data_out (data_out[31:0]),
.data_valid (data_valid),
.write_complete (write_complete),
.DRAM_ADDR (DRAM_ADDR[12:0]),
.DRAM_BA (DRAM_BA[1:0]),
.DRAM_CAS_N (DRAM_CAS_N),
.DRAM_CKE (DRAM_CKE),
.DRAM_CLK (DRAM_CLK),
.DRAM_CS_N (DRAM_CS_N),
.DRAM_DQM (DRAM_DQM[1:0]),
.DRAM_RAS_N (DRAM_RAS_N),
.DRAM_WE_N (DRAM_WE_N),
// Inouts
.DRAM_DQ (DRAM_DQ[15:0]),
// Inputs
.CLOCK_50 (CLOCK_50),
.CLOCK_100 (CLOCK_100),
.CLOCK_100_del_3ns(CLOCK_100_del_3ns),
.rst (rst),
.address (address[23:0]),
.req_read (req_read),
.req_write (req_write),
.data_in (data_in[31:0]));
IS42S16160 RAM (
// Inouts
.Dq (DRAM_DQ[15:0]),
// Inputs
.Addr (DRAM_ADDR[12:0]),
.Ba (DRAM_BA[1:0]),
.Clk (DRAM_CLK),
.Cke (DRAM_CKE),
.Cs_n (DRAM_CS_N),
.Ras_n (DRAM_RAS_N),
.Cas_n (DRAM_CAS_N),
.We_n (DRAM_WE_N),
.Dqm (DRAM_DQM[1:0]));
initial begin
rst = 1;
CLOCK_50 = 0;
CLOCK_100 = 0;
CLOCK_100_del_3ns = 0;
address = 0;
req_read = 0;
req_write = 0;
data_in = 0;
$dumpfile("dump.vcd");
$dumpvars;
#3000 $finish;
end
always #10 CLOCK_50 <= ~CLOCK_50;
always #5 begin
CLOCK_100 <= ~CLOCK_100;
end
always @(CLOCK_100) begin
#3
CLOCK_100_del_3ns <= CLOCK_100;
end
initial begin
#20 rst = 0;
#1000 address = 16;
data_in = 32'h12345678;
req_write = 1;
#20 req_write = 0;
@(posedge write_complete) #60
address = 16;
req_read = 1;
#20
req_read = 0;
end // initial begin
endmodule
|
// file: in_dcm.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____96.002______0.000______50.0______408.330_____60.000
// CLK_OUT2___120.002______0.000______50.0______366.664_____60.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary__________48.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "in_dcm,clk_wiz_v3_2,{component_name=in_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.833,clkin2_period=20.833,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module in_dcm
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk2x;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (2),
.CLKFX_MULTIPLY (5),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (20.833),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("2X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (clk2x),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (RESET),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
assign clkfb = CLK_OUT1;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clk2x));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkfx));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_LP_V
`define SKY130_FD_SC_LP__NAND2B_LP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2b_lp (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2b_lp (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_LP_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Nov 2 08:19:23 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch3_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
overflow_flag, underflow_flag, zero_flag, busy, data_output );
input [63:0] data_in;
input [1:0] shift_region_flag;
output [63:0] data_output;
input clk, rst, beg_fsm_cordic, ack_cordic, operation;
output ready_cordic, overflow_flag, underflow_flag, zero_flag, busy;
wire ready_add_subt, d_ff1_operation_out, d_ff3_sign_out,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2,
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2,
inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2,
inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2,
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1,
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP,
inst_FPU_PIPELINED_FPADDSUB_intAS,
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6,
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_,
n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693,
n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703,
n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713,
n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723,
n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733,
n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743,
n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753,
n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763,
n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773,
n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783,
n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793,
n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803,
n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813,
n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823,
n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833,
n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843,
n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853,
n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863,
n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873,
n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883,
n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893,
n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903,
n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913,
n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923,
n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933,
n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943,
n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953,
n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963,
n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973,
n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983,
n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993,
n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003,
n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013,
n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023,
n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033,
n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043,
n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053,
n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063,
n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073,
n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083,
n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093,
n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103,
n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113,
n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123,
n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133,
n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143,
n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153,
n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163,
n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173,
n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183,
n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193,
n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203,
n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213,
n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223,
n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233,
n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243,
n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253,
n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263,
n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273,
n2274, n2276, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305,
n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315,
n2316, n2317, n2318, n2319, n2320, n2322, n2323, n2324, n2325, n2326,
n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336,
n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346,
n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356,
n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366,
n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2376,
n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385, n2386,
n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395, n2396,
n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405, n2406,
n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415, n2416,
n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425, n2426,
n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435, n2436,
n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445, n2446,
n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455, n2456,
n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465, n2466,
n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475, n2476,
n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485, n2486,
n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495, n2496,
n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505, n2506,
n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515, n2516,
n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525, n2526,
n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535, n2536,
n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545, n2546,
n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555, n2556,
n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565, n2566,
n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575, n2576,
n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585, n2586,
n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595, n2596,
n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605, n2606,
n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616,
n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626,
n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636,
n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646,
n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656,
n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666,
n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676,
n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685, n2686,
n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2696,
n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706,
n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715, n2716,
n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725, n2726,
n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735, n2736,
n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745, n2746,
n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755, n2756,
n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765, n2766,
n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775, n2776,
n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785, n2786,
n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795, n2796,
n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805, n2806,
n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815, n2816,
n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825, n2826,
n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835, n2836,
n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845, n2846,
n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855, n2856,
n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865, n2866,
n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875, n2876,
n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885, n2886,
n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895, n2896,
n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905, n2906,
n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915, n2916,
n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925, n2926,
n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935, n2936,
n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945, n2946,
n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955, n2956,
n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965, n2966,
n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975, n2976,
n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986,
n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996,
n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006,
n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016,
n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026,
n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036,
n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046,
n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056,
n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066,
n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076,
n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086,
n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096,
n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106,
n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116,
n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126,
n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136,
n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146,
n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156,
n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3165, n3167, n3168,
n3169, n3170, n3171, n3172, n3173, intadd_44_CI, intadd_44_SUM_2_,
intadd_44_SUM_1_, intadd_44_SUM_0_, intadd_44_n3, intadd_44_n2,
intadd_44_n1, intadd_45_CI, intadd_45_SUM_2_, intadd_45_SUM_1_,
intadd_45_SUM_0_, intadd_45_n3, intadd_45_n2, intadd_45_n1,
intadd_46_CI, intadd_46_SUM_2_, intadd_46_SUM_1_, intadd_46_SUM_0_,
intadd_46_n3, intadd_46_n2, intadd_46_n1, n3176, n3180, n3181, n3182,
n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192,
n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202,
n3203, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213,
n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223,
n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233,
n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3245, n3246, n3247,
n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257,
n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267,
n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277,
n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287,
n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297,
n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307,
n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317,
n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327,
n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335, n3336, n3337,
n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345, n3346, n3347,
n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355, n3356, n3357,
n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365, n3366, n3367,
n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375, n3376, n3377,
n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385, n3386, n3387,
n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395, n3396, n3397,
n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405, n3406, n3407,
n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415, n3416, n3417,
n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425, n3426, n3427,
n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435, n3436, n3437,
n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445, n3446, n3447,
n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455, n3456, n3457,
n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465, n3466, n3467,
n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475, n3476, n3477,
n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485, n3486, n3487,
n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495, n3496, n3497,
n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505, n3506, n3507,
n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515, n3516, n3517,
n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525, n3526, n3527,
n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535, n3536, n3537,
n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545, n3546, n3547,
n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555, n3556, n3557,
n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565, n3566, n3567,
n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575, n3576, n3577,
n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585, n3586, n3587,
n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595, n3596, n3597,
n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605, n3606, n3607,
n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615, n3616, n3617,
n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625, n3626, n3627,
n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635, n3636, n3637,
n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645, n3646, n3647,
n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655, n3656, n3657,
n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665, n3666, n3667,
n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675, n3676, n3677,
n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685, n3686, n3687,
n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695, n3696, n3697,
n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705, n3706, n3707,
n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715, n3716, n3717,
n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725, n3726, n3727,
n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735, n3736, n3737,
n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745, n3746, n3747,
n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755, n3756, n3757,
n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765, n3766, n3767,
n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775, n3776, n3777,
n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785, n3786, n3787,
n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795, n3796, n3797,
n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805, n3806, n3807,
n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815, n3816, n3817,
n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825, n3826, n3827,
n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835, n3836, n3837,
n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845, n3846, n3847,
n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855, n3856, n3857,
n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865, n3866, n3867,
n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875, n3876, n3877,
n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885, n3886, n3887,
n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895, n3896, n3897,
n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905, n3906, n3907,
n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915, n3916, n3917,
n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925, n3926, n3927,
n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935, n3936, n3937,
n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945, n3946, n3947,
n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955, n3956, n3957,
n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965, n3966, n3967,
n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975, n3976, n3977,
n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985, n3986, n3987,
n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995, n3996, n3997,
n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005, n4006, n4007,
n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015, n4016, n4017,
n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025, n4026, n4027,
n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035, n4036, n4037,
n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045, n4046, n4047,
n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055, n4056, n4057,
n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065, n4066, n4067,
n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075, n4076, n4077,
n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085, n4086, n4087,
n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095, n4096, n4097,
n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105, n4106, n4107,
n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115, n4116, n4117,
n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4127,
n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137,
n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147,
n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157,
n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167,
n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177,
n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187,
n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197,
n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207,
n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217,
n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227,
n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237,
n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247,
n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257,
n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265, n4266, n4267,
n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277,
n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4287,
n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297,
n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307,
n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317,
n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327,
n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337,
n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345, n4346, n4347,
n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355, n4356, n4357,
n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365, n4366, n4367,
n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375, n4376, n4377,
n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385, n4386, n4387,
n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395, n4396, n4397,
n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405, n4406, n4407,
n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415, n4416, n4417,
n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425, n4426, n4427,
n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435, n4436, n4437,
n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445, n4446, n4447,
n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455, n4456, n4457,
n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465, n4466, n4467,
n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475, n4476, n4477,
n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485, n4486, n4487,
n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495, n4496, n4497,
n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505, n4506, n4507,
n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515, n4516, n4517,
n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525, n4526, n4527,
n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535, n4536, n4537,
n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545, n4546, n4547,
n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555, n4556, n4557,
n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565, n4566, n4567,
n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575, n4576, n4577,
n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585, n4586, n4587,
n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595, n4596, n4597,
n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605, n4606, n4607,
n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615, n4616, n4617,
n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625, n4626, n4627,
n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635, n4636, n4637,
n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645, n4646, n4647,
n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655, n4656, n4657,
n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665, n4666, n4667,
n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675, n4676, n4677,
n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685, n4686, n4687,
n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695, n4696, n4697,
n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705, n4706, n4707,
n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715, n4716, n4717,
n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725, n4726, n4727,
n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735, n4736, n4737,
n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745, n4746, n4747,
n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755, n4756, n4757,
n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765, n4766, n4767,
n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775, n4776, n4777,
n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785, n4786, n4787,
n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795, n4796, n4797,
n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805, n4806, n4807,
n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815, n4816, n4817,
n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825, n4826, n4827,
n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835, n4836, n4837,
n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845, n4846, n4847,
n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855, n4856, n4857,
n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865, n4866, n4867,
n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875, n4876, n4877,
n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885, n4886, n4887,
n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895, n4896, n4897,
n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905, n4906, n4907,
n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915, n4916, n4917,
n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925, n4926, n4927,
n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935, n4936, n4937,
n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945, n4946, n4947,
n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955, n4956, n4957,
n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965, n4966, n4967,
n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975, n4976, n4977,
n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985, n4986, n4987,
n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995, n4996, n4997,
n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005, n5006, n5007,
n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015, n5016, n5017,
n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025, n5026, n5027,
n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035, n5036, n5037,
n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045, n5046, n5047,
n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055, n5056, n5057,
n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065, n5066, n5067,
n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075, n5076, n5077,
n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085, n5086, n5087,
n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095, n5096, n5097,
n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105, n5106, n5107,
n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115, n5116, n5117,
n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125, n5126, n5127,
n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135, n5136, n5137,
n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145, n5146, n5147,
n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155, n5156, n5157,
n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165, n5166, n5167,
n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175, n5176, n5177,
n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185, n5186, n5187,
n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195, n5196, n5197,
n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205, n5206, n5207,
n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215, n5216, n5217,
n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225, n5226, n5227,
n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235, n5236, n5237,
n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245, n5246, n5247,
n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255, n5256, n5257,
n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265, n5266, n5267,
n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275, n5276, n5277,
n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285, n5286, n5287,
n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295, n5296, n5297,
n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305, n5306, n5307,
n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315, n5316, n5317,
n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325, n5326, n5327,
n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335, n5336, n5337,
n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345, n5346, n5347,
n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355, n5356, n5357,
n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365, n5366, n5367,
n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375, n5376, n5377,
n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385, n5386, n5387,
n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395, n5396, n5397,
n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405, n5406, n5407,
n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415, n5416, n5417,
n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425, n5426, n5427,
n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435, n5436, n5437,
n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445, n5446, n5447,
n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455, n5456, n5457,
n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465, n5466, n5467,
n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475, n5476, n5477,
n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485, n5486, n5487,
n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495, n5496, n5497,
n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505, n5506, n5507,
n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515, n5516, n5517,
n5518, n5519, n5520, n5521, n5522, n5523, n5524, n5525, n5526, n5527,
n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535, n5536, n5537,
n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545, n5546, n5547,
n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555, n5556, n5557,
n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565, n5566, n5567,
n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575, n5576, n5577,
n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585, n5586, n5587,
n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595, n5596, n5597,
n5598, n5599, n5600, n5601, n5602, n5603, n5604, n5605, n5606, n5607,
n5608, n5609, n5610, n5611, n5612, n5613, n5614, n5615, n5616, n5617,
n5618, n5619, n5620, n5621, n5622, n5623, n5624, n5625, n5626, n5627,
n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635, n5636, n5637,
n5638, n5639, n5640, n5641, n5642, n5643, n5644, n5645, n5646, n5647,
n5648, n5649, n5650, n5651, n5652, n5653, n5654, n5655, n5656, n5657,
n5658, n5659, n5660, n5661, n5662, n5663, n5664, n5665, n5666, n5667,
n5668, n5669, n5670, n5671, n5672, n5673, n5674, n5675, n5676, n5677,
n5678, n5679, n5680, n5681, n5682, n5683, n5684, n5685, n5686, n5687,
n5688, n5689, n5690, n5691, n5692, n5693, n5694, n5695, n5696, n5697,
n5698, n5699, n5700, n5701, n5702, n5703, n5704, n5705, n5706, n5707,
n5708, n5709, n5710, n5711, n5712, n5713, n5714, n5715, n5716, n5717,
n5718, n5719, n5720, n5721, n5722, n5723, n5724, n5725, n5726, n5727,
n5728, n5729, n5730, n5731, n5732, n5733, n5734, n5735, n5736, n5737,
n5738, n5739, n5740, n5741, n5742, n5743, n5744, n5745, n5746, n5747,
n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755, n5756, n5757,
n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765, n5766, n5767,
n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775, n5776, n5777,
n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785, n5786, n5787,
n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795, n5796, n5797,
n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805, n5806, n5807,
n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815, n5816, n5817,
n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825, n5826, n5827,
n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835, n5836, n5837,
n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845, n5846, n5847,
n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855, n5856, n5857,
n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865, n5866, n5867,
n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875, n5876, n5877,
n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885, n5886, n5887,
n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895, n5896, n5897,
n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905, n5906, n5907,
n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915, n5916, n5917,
n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925, n5926, n5927,
n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935, n5936, n5937,
n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945, n5946, n5947,
n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955, n5956, n5957,
n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965, n5966, n5967,
n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975, n5976, n5977,
n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985, n5986, n5987,
n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995, n5996, n5997,
n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005, n6006, n6007,
n6008, n6009, n6010, n6011, n6012, n6013, n6014, n6015, n6016, n6017,
n6018, n6019, n6020, n6021, n6022, n6023, n6024, n6025, n6026, n6027,
n6028, n6029, n6030, n6031, n6032, n6033, n6034, n6035, n6036, n6037,
n6038, n6039, n6040, n6041, n6042, n6043, n6044, n6045, n6046, n6047,
n6048, n6049, n6050, n6051, n6052, n6053, n6054, n6055, n6056, n6057,
n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065, n6066, n6067,
n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075, n6076, n6077,
n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085, n6086, n6087,
n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095, n6096, n6097,
n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105, n6106, n6107,
n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115, n6116, n6117,
n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125, n6126, n6127,
n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135, n6136, n6137,
n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145, n6146, n6147,
n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155, n6156, n6157,
n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165, n6166, n6167,
n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175, n6176, n6177,
n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185, n6186, n6187,
n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195, n6196, n6197,
n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205, n6206, n6207,
n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215, n6216, n6217,
n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225, n6226, n6227,
n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235, n6236, n6237,
n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245, n6246, n6247,
n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255, n6256, n6257,
n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265, n6266, n6267,
n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275, n6276, n6277,
n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285, n6286, n6287,
n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295, n6296, n6297,
n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305, n6306, n6307,
n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315, n6316, n6317,
n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325, n6326, n6327,
n6328, n6329, n6330, n6331, n6332, n6333, n6334, n6335, n6336, n6337,
n6338, n6339, n6340, n6341, n6342, n6343, n6344, n6345, n6346, n6347,
n6348, n6349, n6350, n6351, n6352, n6353, n6354, n6355, n6356, n6357,
n6358, n6359, n6360, n6361, n6362, n6363, n6364, n6365, n6366, n6367,
n6368, n6369, n6370, n6371, n6372, n6373, n6374, n6375, n6376, n6377,
n6378, n6379, n6380, n6381, n6382, n6383, n6384, n6385, n6386, n6387,
n6388, n6389, n6390, n6391, n6392, n6393, n6394, n6395, n6396, n6397,
n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405, n6406, n6407,
n6408, n6409, n6410, n6411, n6412, n6413, n6414, n6415, n6416, n6417,
n6418, n6419, n6420, n6421, n6422, n6423, n6424, n6425, n6426, n6427,
n6428, n6429, n6430, n6431, n6432, n6433, n6434, n6435, n6436, n6437,
n6438, n6439, n6440, n6441, n6442, n6443, n6444, n6445, n6446, n6447,
n6448, n6449, n6450, n6451, n6452, n6453, n6454, n6455, n6456, n6457,
n6458, n6459, n6460, n6461, n6462, n6463, n6464, n6465, n6466, n6467,
n6468, n6469, n6470, n6471, n6472, n6473, n6474, n6475, n6476, n6477,
n6478, n6479, n6480, n6481, n6482, n6483, n6484, n6485, n6486, n6487,
n6488, n6489, n6490, n6491, n6492, n6493, n6494, n6495, n6496, n6497,
n6498, n6499, n6500, n6501, n6502, n6503, n6504, n6505, n6506, n6507,
n6508, n6509, n6510, n6511, n6512, n6513, n6514, n6515, n6516, n6517,
n6518, n6519, n6520, n6521, n6522, n6523, n6524, n6525, n6526, n6527,
n6528, n6529, n6530, n6531, n6532, n6533, n6534, n6535, n6536, n6537,
n6538, n6539, n6540, n6541, n6542, n6543, n6544, n6545, n6546, n6547,
n6548, n6549, n6550, n6551, n6552, n6553, n6554, n6555, n6556, n6557,
n6558, n6559, n6560, n6561, n6562, n6563, n6564, n6565, n6566, n6567,
n6568, n6569, n6570, n6571, n6572, n6573, n6574, n6575, n6576, n6577,
n6578, n6579, n6580, n6581, n6582, n6583, n6584, n6585, n6586, n6587,
n6588, n6589, n6590, n6591, n6592, n6593, n6594, n6595, n6596, n6597,
n6598, n6599, n6600, n6601, n6602, n6603, n6604, n6605, n6606, n6607,
n6608, n6609, n6610, n6611, n6612, n6613, n6614, n6615, n6616, n6617,
n6618, n6619, n6620, n6621, n6622, n6623, n6624, n6625, n6626, n6627,
n6628, n6629, n6630, n6631, n6632, n6633, n6634, n6635, n6636, n6637,
n6638, n6639, n6640, n6641, n6642, n6643, n6644, n6645, n6646, n6647,
n6648, n6649, n6650, n6651, n6652, n6653, n6654, n6655, n6656, n6657,
n6658, n6659, n6660, n6661, n6662, n6663, n6664, n6665, n6666, n6667,
n6668, n6669, n6670, n6671, n6672, n6673, n6674, n6675, n6676, n6677,
n6678, n6679, n6680, n6681, n6682, n6683, n6684, n6685, n6686, n6687,
n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695, n6696, n6697,
n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705, n6706, n6707,
n6708, n6709, n6710, n6711, n6712, n6713, n6714, n6715, n6716, n6717,
n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725, n6726, n6727,
n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735, n6736, n6737,
n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6745, n6746, n6747,
n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755, n6756, n6757,
n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765, n6766, n6767,
n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775, n6776, n6777,
n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785, n6786, n6787,
n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795, n6796, n6797,
n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805, n6806, n6807,
n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815, n6816, n6817,
n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825, n6826, n6827,
n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835, n6836, n6837,
n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845, n6846, n6847,
n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855, n6856, n6857,
n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865, n6866, n6867,
n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875, n6876, n6877,
n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885, n6886, n6887,
n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895, n6896, n6897,
n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905, n6906, n6907,
n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915, n6916, n6917,
n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925, n6926, n6927,
n6928, n6929, n6930, n6931, n6932, n6934, n6935, n6936, n6937, n6938,
n6939, n6940, n6941, n6942, n6943, n6944, n6945, n6946, n6947, n6948,
n6949, n6950, n6951, n6952, n6953, n6954, n6955, n6956, n6957, n6958,
n6959, n6960, n6961, n6962, n6963, n6964, n6965, n6966, n6967, n6968,
n6969, n6970, n6971, n6972, n6973, n6974, n6975, n6976, n6977, n6978,
n6979, n6980, n6981, n6982, n6983, n6984, n6985, n6986, n6987, n6988,
n6989, n6990, n6991, n6992, n6993, n6994, n6995, n6996, n6997, n6998,
n6999, n7000, n7001, n7002, n7003, n7004, n7005, n7006, n7007, n7008,
n7009, n7010, n7011, n7012, n7013;
wire [3:1] cont_iter_out;
wire [1:0] cont_var_out;
wire [1:0] d_ff1_shift_region_flag_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff_Xn;
wire [63:0] d_ff_Yn;
wire [63:0] d_ff_Zn;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [63:0] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [56:0] d_ff3_LUT_out;
wire [63:0] result_add_subt;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
wire [54:0] inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR;
wire [62:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SFG;
wire [5:0] inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW;
wire [10:0] inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW;
wire [10:0] inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW;
wire [5:2] inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR;
wire [62:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW;
wire [50:0] inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR;
wire [54:0] inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR;
wire [5:0] inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR;
wire [51:0] inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW;
wire [62:0] inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW;
wire [57:0] inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW;
wire [62:0] inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW;
wire [63:0] inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW;
wire [63:0] inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW;
wire [3:0] inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7;
wire [2:0] inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(n3107), .CK(clk), .RN(n6996), .Q(d_ff1_Z[62])
);
DFFRXLTS reg_Z0_Q_reg_61_ ( .D(n3106), .CK(clk), .RN(n6996), .Q(d_ff1_Z[61])
);
DFFRXLTS reg_Z0_Q_reg_60_ ( .D(n3105), .CK(clk), .RN(n6996), .Q(d_ff1_Z[60])
);
DFFRXLTS reg_Z0_Q_reg_59_ ( .D(n3104), .CK(clk), .RN(n6995), .Q(d_ff1_Z[59])
);
DFFRXLTS reg_Z0_Q_reg_58_ ( .D(n3103), .CK(clk), .RN(n6995), .Q(d_ff1_Z[58])
);
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(n3102), .CK(clk), .RN(n6995), .Q(d_ff1_Z[57])
);
DFFRXLTS reg_Z0_Q_reg_56_ ( .D(n3101), .CK(clk), .RN(n6995), .Q(d_ff1_Z[56])
);
DFFRXLTS reg_Z0_Q_reg_55_ ( .D(n3100), .CK(clk), .RN(n6995), .Q(d_ff1_Z[55])
);
DFFRXLTS reg_Z0_Q_reg_54_ ( .D(n3099), .CK(clk), .RN(n6995), .Q(d_ff1_Z[54])
);
DFFRXLTS reg_Z0_Q_reg_53_ ( .D(n3098), .CK(clk), .RN(n6995), .Q(d_ff1_Z[53])
);
DFFRXLTS reg_Z0_Q_reg_52_ ( .D(n3097), .CK(clk), .RN(n6995), .Q(d_ff1_Z[52])
);
DFFRXLTS reg_Z0_Q_reg_51_ ( .D(n3096), .CK(clk), .RN(n6995), .Q(d_ff1_Z[51])
);
DFFRXLTS reg_Z0_Q_reg_50_ ( .D(n3095), .CK(clk), .RN(n6995), .Q(d_ff1_Z[50])
);
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(n3094), .CK(clk), .RN(n7005), .Q(d_ff1_Z[49])
);
DFFRXLTS reg_Z0_Q_reg_48_ ( .D(n3093), .CK(clk), .RN(n7005), .Q(d_ff1_Z[48])
);
DFFRXLTS reg_Z0_Q_reg_47_ ( .D(n3092), .CK(clk), .RN(n6998), .Q(d_ff1_Z[47])
);
DFFRXLTS reg_Z0_Q_reg_46_ ( .D(n3091), .CK(clk), .RN(n6998), .Q(d_ff1_Z[46])
);
DFFRXLTS reg_Z0_Q_reg_45_ ( .D(n3090), .CK(clk), .RN(n7005), .Q(d_ff1_Z[45])
);
DFFRXLTS reg_Z0_Q_reg_44_ ( .D(n3089), .CK(clk), .RN(n7004), .Q(d_ff1_Z[44])
);
DFFRXLTS reg_Z0_Q_reg_43_ ( .D(n3088), .CK(clk), .RN(n7005), .Q(d_ff1_Z[43])
);
DFFRXLTS reg_Z0_Q_reg_42_ ( .D(n3087), .CK(clk), .RN(n6999), .Q(d_ff1_Z[42])
);
DFFRXLTS reg_Z0_Q_reg_41_ ( .D(n3086), .CK(clk), .RN(n7004), .Q(d_ff1_Z[41])
);
DFFRXLTS reg_Z0_Q_reg_40_ ( .D(n3085), .CK(clk), .RN(n7002), .Q(d_ff1_Z[40])
);
DFFRXLTS reg_Z0_Q_reg_39_ ( .D(n3084), .CK(clk), .RN(n6994), .Q(d_ff1_Z[39])
);
DFFRXLTS reg_Z0_Q_reg_38_ ( .D(n3083), .CK(clk), .RN(n6994), .Q(d_ff1_Z[38])
);
DFFRXLTS reg_Z0_Q_reg_37_ ( .D(n3082), .CK(clk), .RN(n6994), .Q(d_ff1_Z[37])
);
DFFRXLTS reg_Z0_Q_reg_36_ ( .D(n3081), .CK(clk), .RN(n6994), .Q(d_ff1_Z[36])
);
DFFRXLTS reg_Z0_Q_reg_35_ ( .D(n3080), .CK(clk), .RN(n6994), .Q(d_ff1_Z[35])
);
DFFRXLTS reg_Z0_Q_reg_34_ ( .D(n3079), .CK(clk), .RN(n6994), .Q(d_ff1_Z[34])
);
DFFRXLTS reg_Z0_Q_reg_33_ ( .D(n3078), .CK(clk), .RN(n6994), .Q(d_ff1_Z[33])
);
DFFRXLTS reg_Z0_Q_reg_32_ ( .D(n3077), .CK(clk), .RN(n6994), .Q(d_ff1_Z[32])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n3076), .CK(clk), .RN(n6994), .Q(d_ff1_Z[31])
);
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n3075), .CK(clk), .RN(n6994), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n3074), .CK(clk), .RN(n6993), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n3073), .CK(clk), .RN(n6993), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n3072), .CK(clk), .RN(n6993), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n3071), .CK(clk), .RN(n6993), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n3070), .CK(clk), .RN(n6993), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n3069), .CK(clk), .RN(n6993), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n3068), .CK(clk), .RN(n6993), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n3067), .CK(clk), .RN(n6993), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n3066), .CK(clk), .RN(n6993), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n3065), .CK(clk), .RN(n6993), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n3064), .CK(clk), .RN(n6992), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n3063), .CK(clk), .RN(n6992), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n3062), .CK(clk), .RN(n6992), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n3061), .CK(clk), .RN(n6992), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n3060), .CK(clk), .RN(n6992), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n3059), .CK(clk), .RN(n6992), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n3058), .CK(clk), .RN(n6992), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n3057), .CK(clk), .RN(n6992), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n3056), .CK(clk), .RN(n6992), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n3055), .CK(clk), .RN(n6992), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n3054), .CK(clk), .RN(n6991), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n3053), .CK(clk), .RN(n6991), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n3052), .CK(clk), .RN(n6991), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n3051), .CK(clk), .RN(n6991), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n3050), .CK(clk), .RN(n6991), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n3049), .CK(clk), .RN(n6991), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n3048), .CK(clk), .RN(n6991), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n3047), .CK(clk), .RN(n6991), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n3046), .CK(clk), .RN(n6991), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n3045), .CK(clk), .RN(n6991), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_63_ ( .D(n3044), .CK(clk), .RN(n6990), .Q(d_ff1_Z[63])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n3168),
.CK(clk), .RN(n6924), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]), .QN(n6717) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n3167),
.CK(clk), .RN(n6928), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n3186) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n3165),
.CK(clk), .RN(n6926), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .QN(n3289) );
DFFRXLTS reg_LUT_Q_reg_56_ ( .D(n3158), .CK(clk), .RN(n6990), .Q(
d_ff3_LUT_out[56]) );
DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n3154), .CK(clk), .RN(n6990), .Q(
d_ff3_LUT_out[52]) );
DFFRXLTS reg_LUT_Q_reg_42_ ( .D(n3149), .CK(clk), .RN(n6990), .Q(
d_ff3_LUT_out[42]) );
DFFRXLTS reg_LUT_Q_reg_37_ ( .D(n3146), .CK(clk), .RN(n6990), .Q(
d_ff3_LUT_out[37]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n3132), .CK(clk), .RN(n6989), .Q(
d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_32_ ( .D(n3142), .CK(clk), .RN(n6989), .Q(
d_ff3_LUT_out[32]) );
DFFRXLTS reg_LUT_Q_reg_41_ ( .D(n3148), .CK(clk), .RN(n6989), .Q(
d_ff3_LUT_out[41]), .QN(n6833) );
DFFRXLTS reg_LUT_Q_reg_53_ ( .D(n3155), .CK(clk), .RN(n6989), .Q(
d_ff3_LUT_out[53]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n3130), .CK(clk), .RN(n6988), .Q(
d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_50_ ( .D(n3153), .CK(clk), .RN(n6988), .Q(
d_ff3_LUT_out[50]), .QN(n6832) );
DFFRXLTS reg_LUT_Q_reg_44_ ( .D(n3150), .CK(clk), .RN(n6988), .Q(
d_ff3_LUT_out[44]), .QN(n6839) );
DFFRXLTS reg_LUT_Q_reg_28_ ( .D(n3139), .CK(clk), .RN(n6988), .Q(
d_ff3_LUT_out[28]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n3128), .CK(clk), .RN(n6988), .Q(
d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n3131), .CK(clk), .RN(n6988), .Q(
d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_35_ ( .D(n3145), .CK(clk), .RN(n6988), .Q(
d_ff3_LUT_out[35]), .QN(n6834) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n3129), .CK(clk), .RN(n6988), .Q(
d_ff3_LUT_out[18]), .QN(n6837) );
DFFRXLTS reg_LUT_Q_reg_45_ ( .D(n3151), .CK(clk), .RN(n7006), .Q(
d_ff3_LUT_out[45]), .QN(n6829) );
DFFRXLTS reg_LUT_Q_reg_55_ ( .D(n3157), .CK(clk), .RN(n7000), .Q(
d_ff3_LUT_out[55]), .QN(n6831) );
DFFRXLTS reg_LUT_Q_reg_39_ ( .D(n3147), .CK(clk), .RN(n7009), .Q(
d_ff3_LUT_out[39]) );
DFFRXLTS reg_LUT_Q_reg_31_ ( .D(n3141), .CK(clk), .RN(n7011), .Q(
d_ff3_LUT_out[31]), .QN(n6835) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(n3135), .CK(clk), .RN(n7009), .Q(
d_ff3_LUT_out[24]), .QN(n6836) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n3133), .CK(clk), .RN(n7008), .Q(
d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n3123), .CK(clk), .RN(n7012), .Q(
d_ff3_LUT_out[12]), .QN(n6838) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n3137), .CK(clk), .RN(n7008), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n3116), .CK(clk), .RN(n6987), .Q(
d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_34_ ( .D(n3144), .CK(clk), .RN(n6987), .Q(
d_ff3_LUT_out[34]), .QN(n6840) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n3127), .CK(clk), .RN(n6987), .Q(
d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n3111), .CK(clk), .RN(n6986), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(n2766), .CK(clk), .RN(n6986), .Q(
d_ff3_sh_x_out[52]) );
DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(n2765), .CK(clk), .RN(n6986), .Q(
d_ff3_sh_x_out[53]) );
DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(n2764), .CK(clk), .RN(n6986), .Q(
d_ff3_sh_x_out[54]) );
DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(n2763), .CK(clk), .RN(n6986), .Q(
d_ff3_sh_x_out[55]) );
DFFRXLTS reg_shift_x_Q_reg_56_ ( .D(n2762), .CK(clk), .RN(n6986), .Q(
d_ff3_sh_x_out[56]) );
DFFRXLTS reg_shift_x_Q_reg_57_ ( .D(n2761), .CK(clk), .RN(n6986), .Q(
d_ff3_sh_x_out[57]) );
DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(n2760), .CK(clk), .RN(n6986), .Q(
d_ff3_sh_x_out[58]) );
DFFRXLTS reg_shift_x_Q_reg_59_ ( .D(n2759), .CK(clk), .RN(n6986), .Q(
d_ff3_sh_x_out[59]) );
DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(n2758), .CK(clk), .RN(n6985), .Q(
d_ff3_sh_x_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_61_ ( .D(n2757), .CK(clk), .RN(n6985), .Q(
d_ff3_sh_x_out[61]) );
DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(n2756), .CK(clk), .RN(n6985), .Q(
d_ff3_sh_x_out[62]) );
DFFRXLTS reg_shift_y_Q_reg_52_ ( .D(n2583), .CK(clk), .RN(n6985), .Q(
d_ff3_sh_y_out[52]) );
DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(n2581), .CK(clk), .RN(n6985), .Q(
d_ff3_sh_y_out[53]) );
DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(n2579), .CK(clk), .RN(n6985), .Q(
d_ff3_sh_y_out[54]) );
DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(n2577), .CK(clk), .RN(n6985), .Q(
d_ff3_sh_y_out[55]) );
DFFRXLTS reg_shift_y_Q_reg_56_ ( .D(n2575), .CK(clk), .RN(n6985), .Q(
d_ff3_sh_y_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_57_ ( .D(n2573), .CK(clk), .RN(n6985), .Q(
d_ff3_sh_y_out[57]) );
DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(n2571), .CK(clk), .RN(n6985), .Q(
d_ff3_sh_y_out[58]) );
DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(n2569), .CK(clk), .RN(n6984), .Q(
d_ff3_sh_y_out[59]) );
DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(n2567), .CK(clk), .RN(n6984), .Q(
d_ff3_sh_y_out[60]) );
DFFRXLTS reg_shift_y_Q_reg_61_ ( .D(n2565), .CK(clk), .RN(n6984), .Q(
d_ff3_sh_y_out[61]) );
DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(n2563), .CK(clk), .RN(n6984), .Q(
d_ff3_sh_y_out[62]) );
DFFRXLTS reg_LUT_Q_reg_29_ ( .D(n3140), .CK(clk), .RN(n6984), .Q(
d_ff3_LUT_out[29]), .QN(n6830) );
DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(n2505), .CK(clk), .RN(n6984), .Q(
d_ff_Zn[52]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_52_ ( .D(n2370), .CK(clk), .RN(n6984),
.Q(d_ff2_Z[52]) );
DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(n2502), .CK(clk), .RN(n6983), .Q(
d_ff_Zn[53]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_53_ ( .D(n2368), .CK(clk), .RN(n6983),
.Q(d_ff2_Z[53]) );
DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(n2499), .CK(clk), .RN(n6983), .Q(
d_ff_Zn[54]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_54_ ( .D(n2366), .CK(clk), .RN(n6982),
.Q(d_ff2_Z[54]) );
DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(n2496), .CK(clk), .RN(n6982), .Q(
d_ff_Zn[55]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_55_ ( .D(n2364), .CK(clk), .RN(n6982),
.Q(d_ff2_Z[55]) );
DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(n2493), .CK(clk), .RN(n3870), .Q(
d_ff_Zn[56]) );
DFFRXLTS d_ff4_Yn_Q_reg_56_ ( .D(n2492), .CK(clk), .RN(n7001), .QN(n3200) );
DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(n2490), .CK(clk), .RN(n6981), .Q(
d_ff_Zn[57]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_57_ ( .D(n2360), .CK(clk), .RN(n6981),
.Q(d_ff2_Z[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(n2487), .CK(clk), .RN(n6981), .Q(
d_ff_Zn[58]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_58_ ( .D(n2358), .CK(clk), .RN(n6981),
.Q(d_ff2_Z[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(n2484), .CK(clk), .RN(n6980), .Q(
d_ff_Zn[59]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_59_ ( .D(n2356), .CK(clk), .RN(n6980),
.Q(d_ff2_Z[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(n2481), .CK(clk), .RN(n6979), .Q(
d_ff_Zn[60]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_60_ ( .D(n2354), .CK(clk), .RN(n6979),
.Q(d_ff2_Z[60]) );
DFFRXLTS d_ff4_Yn_Q_reg_60_ ( .D(n2480), .CK(clk), .RN(n6979), .QN(n3199) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_60_ ( .D(n2586), .CK(clk), .RN(n6979),
.Q(d_ff2_Y[60]), .QN(n6752) );
DFFRXLTS d_ff4_Xn_Q_reg_60_ ( .D(n2479), .CK(clk), .RN(n6979), .QN(n3188) );
DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(n2478), .CK(clk), .RN(n6979), .Q(
d_ff_Zn[61]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_61_ ( .D(n2352), .CK(clk), .RN(n6979),
.Q(d_ff2_Z[61]) );
DFFRXLTS d_ff4_Yn_Q_reg_61_ ( .D(n2477), .CK(clk), .RN(n6978), .QN(n3202) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_61_ ( .D(n2585), .CK(clk), .RN(n6978),
.Q(d_ff2_Y[61]), .QN(n3254) );
DFFRXLTS d_ff4_Xn_Q_reg_61_ ( .D(n2476), .CK(clk), .RN(n6978), .QN(n3190) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_61_ ( .D(n2768), .CK(clk), .RN(n6978),
.QN(n3197) );
DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(n2475), .CK(clk), .RN(n6978), .Q(
d_ff_Zn[62]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_62_ ( .D(n2350), .CK(clk), .RN(n6978),
.Q(d_ff2_Z[62]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_62_ ( .D(n2584), .CK(clk), .RN(n6978),
.QN(n3198) );
DFFRXLTS d_ff4_Xn_Q_reg_62_ ( .D(n2345), .CK(clk), .RN(n6978), .QN(n3203) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n2507),
.CK(clk), .RN(n6907), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(n2884), .CK(clk), .RN(n6977), .Q(
d_ff_Zn[51]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_51_ ( .D(n2372), .CK(clk), .RN(n6977),
.Q(d_ff2_Z[51]) );
DFFRXLTS d_ff4_Yn_Q_reg_51_ ( .D(n2883), .CK(clk), .RN(n6977), .QN(n3201) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_51_ ( .D(n2597), .CK(clk), .RN(n6977),
.Q(d_ff2_Y[51]), .QN(n3248) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(n2596), .CK(clk), .RN(n6977), .Q(
d_ff3_sh_y_out[51]) );
DFFRXLTS d_ff4_Xn_Q_reg_51_ ( .D(n2882), .CK(clk), .RN(n6977), .QN(n3189) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_51_ ( .D(n2779), .CK(clk), .RN(n6977),
.Q(d_ff2_X[51]), .QN(n3250) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(n2778), .CK(clk), .RN(n6977), .Q(
d_ff3_sh_x_out[51]) );
DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(n2887), .CK(clk), .RN(n7003), .Q(
d_ff_Zn[50]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_50_ ( .D(n2374), .CK(clk), .RN(n7004),
.Q(d_ff2_Z[50]) );
DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(n2599), .CK(clk), .RN(n7004), .Q(
d_ff3_sh_y_out[50]) );
DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(n2780), .CK(clk), .RN(n7002), .Q(
d_ff3_sh_x_out[50]) );
DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(n2896), .CK(clk), .RN(n7003), .Q(
d_ff_Zn[47]) );
DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(n2608), .CK(clk), .RN(n6976), .Q(
d_ff3_sh_y_out[47]) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(n2786), .CK(clk), .RN(n6976), .Q(
d_ff3_sh_x_out[47]) );
DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(n2890), .CK(clk), .RN(n6976), .Q(
d_ff_Zn[49]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_49_ ( .D(n2376), .CK(clk), .RN(n6976),
.Q(d_ff2_Z[49]) );
DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(n2602), .CK(clk), .RN(n6975), .Q(
d_ff3_sh_y_out[49]) );
DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(n2782), .CK(clk), .RN(n6975), .Q(
d_ff3_sh_x_out[49]) );
DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(n2893), .CK(clk), .RN(n6975), .Q(
d_ff_Zn[48]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_48_ ( .D(n2378), .CK(clk), .RN(n6975),
.Q(d_ff2_Z[48]) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(n2605), .CK(clk), .RN(n6975), .Q(
d_ff3_sh_y_out[48]) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(n2784), .CK(clk), .RN(n7004), .Q(
d_ff3_sh_x_out[48]) );
DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(n2938), .CK(clk), .RN(n6999), .Q(
d_ff_Zn[33]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_33_ ( .D(n2408), .CK(clk), .RN(n7002),
.Q(d_ff2_Z[33]) );
DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(n2650), .CK(clk), .RN(n7002), .Q(
d_ff3_sh_y_out[33]) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(n2814), .CK(clk), .RN(n7002), .Q(
d_ff3_sh_x_out[33]) );
DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(n2905), .CK(clk), .RN(n6974), .Q(
d_ff_Zn[44]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_44_ ( .D(n2386), .CK(clk), .RN(n6974),
.Q(d_ff2_Z[44]) );
DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(n2617), .CK(clk), .RN(n6974), .Q(
d_ff3_sh_y_out[44]) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(n2792), .CK(clk), .RN(n6974), .Q(
d_ff3_sh_x_out[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n3028), .CK(clk), .RN(n6974), .Q(d_ff_Zn[3])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n2468), .CK(clk), .RN(n6974), .Q(
d_ff2_Z[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n2740), .CK(clk), .RN(n6973), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n2874), .CK(clk), .RN(n6973), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(n2935), .CK(clk), .RN(n6973), .Q(
d_ff_Zn[34]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_34_ ( .D(n2406), .CK(clk), .RN(n6973),
.Q(d_ff2_Z[34]) );
DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(n2647), .CK(clk), .RN(n6972), .Q(
d_ff3_sh_y_out[34]) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(n2812), .CK(clk), .RN(n6972), .Q(
d_ff3_sh_x_out[34]) );
DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(n2902), .CK(clk), .RN(n6972), .Q(
d_ff_Zn[45]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_45_ ( .D(n2384), .CK(clk), .RN(n6972),
.Q(d_ff2_Z[45]) );
DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(n2614), .CK(clk), .RN(n6972), .Q(
d_ff3_sh_y_out[45]) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(n2790), .CK(clk), .RN(n6971), .Q(
d_ff3_sh_x_out[45]) );
DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(n2899), .CK(clk), .RN(n6971), .Q(
d_ff_Zn[46]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_46_ ( .D(n2382), .CK(clk), .RN(n6971),
.Q(d_ff2_Z[46]) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(n2611), .CK(clk), .RN(n6971), .Q(
d_ff3_sh_y_out[46]) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(n2788), .CK(clk), .RN(n6971), .Q(
d_ff3_sh_x_out[46]) );
DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(n2932), .CK(clk), .RN(n6970), .Q(
d_ff_Zn[35]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_35_ ( .D(n2404), .CK(clk), .RN(n6970),
.Q(d_ff2_Z[35]) );
DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(n2644), .CK(clk), .RN(n6970), .Q(
d_ff3_sh_y_out[35]) );
DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(n2810), .CK(clk), .RN(n6970), .Q(
d_ff3_sh_x_out[35]) );
DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(n2911), .CK(clk), .RN(n6970), .Q(
d_ff_Zn[42]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_42_ ( .D(n2390), .CK(clk), .RN(n6970),
.Q(d_ff2_Z[42]) );
DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(n2623), .CK(clk), .RN(n6969), .Q(
d_ff3_sh_y_out[42]) );
DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(n2796), .CK(clk), .RN(n6969), .Q(
d_ff3_sh_x_out[42]) );
DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(n2908), .CK(clk), .RN(n6969), .Q(
d_ff_Zn[43]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_43_ ( .D(n2388), .CK(clk), .RN(n6969),
.Q(d_ff2_Z[43]) );
DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(n2620), .CK(clk), .RN(n6968), .Q(
d_ff3_sh_y_out[43]) );
DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(n2794), .CK(clk), .RN(n6968), .Q(
d_ff3_sh_x_out[43]) );
DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(n2929), .CK(clk), .RN(n6968), .Q(
d_ff_Zn[36]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_36_ ( .D(n2402), .CK(clk), .RN(n6968),
.Q(d_ff2_Z[36]) );
DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(n2641), .CK(clk), .RN(n6968), .Q(
d_ff3_sh_y_out[36]) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(n2808), .CK(clk), .RN(n6967), .Q(
d_ff3_sh_x_out[36]) );
DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(n2920), .CK(clk), .RN(n6967), .Q(
d_ff_Zn[39]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_39_ ( .D(n2396), .CK(clk), .RN(n6967),
.Q(d_ff2_Z[39]) );
DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(n2632), .CK(clk), .RN(n6967), .Q(
d_ff3_sh_y_out[39]) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(n2802), .CK(clk), .RN(n6967), .Q(
d_ff3_sh_x_out[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(n2914), .CK(clk), .RN(n6966), .Q(
d_ff_Zn[41]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_41_ ( .D(n2392), .CK(clk), .RN(n6966),
.Q(d_ff2_Z[41]) );
DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(n2626), .CK(clk), .RN(n6966), .Q(
d_ff3_sh_y_out[41]) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(n2798), .CK(clk), .RN(n6966), .Q(
d_ff3_sh_x_out[41]) );
DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(n2923), .CK(clk), .RN(n6966), .Q(
d_ff_Zn[38]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_38_ ( .D(n2398), .CK(clk), .RN(n6966),
.Q(d_ff2_Z[38]) );
DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(n2635), .CK(clk), .RN(n6965), .Q(
d_ff3_sh_y_out[38]) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(n2804), .CK(clk), .RN(n6965), .Q(
d_ff3_sh_x_out[38]) );
DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(n2917), .CK(clk), .RN(n6965), .Q(
d_ff_Zn[40]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_40_ ( .D(n2394), .CK(clk), .RN(n6965),
.Q(d_ff2_Z[40]) );
DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(n2629), .CK(clk), .RN(n6964), .Q(
d_ff3_sh_y_out[40]) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(n2800), .CK(clk), .RN(n6964), .Q(
d_ff3_sh_x_out[40]) );
DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(n2926), .CK(clk), .RN(n6964), .Q(
d_ff_Zn[37]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_37_ ( .D(n2400), .CK(clk), .RN(n6964),
.Q(d_ff2_Z[37]) );
DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(n2638), .CK(clk), .RN(n6964), .Q(
d_ff3_sh_y_out[37]) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(n2806), .CK(clk), .RN(n6963), .Q(
d_ff3_sh_x_out[37]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n2953), .CK(clk), .RN(n6963), .Q(
d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n2418), .CK(clk), .RN(n6963),
.Q(d_ff2_Z[28]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n2665), .CK(clk), .RN(n6963), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n2824), .CK(clk), .RN(n6963), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n2944), .CK(clk), .RN(n6962), .Q(
d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n2412), .CK(clk), .RN(n6962),
.Q(d_ff2_Z[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n2656), .CK(clk), .RN(n6962), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n2818), .CK(clk), .RN(n6962), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n3001), .CK(clk), .RN(n6962), .Q(
d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n2450), .CK(clk), .RN(n6962),
.Q(d_ff2_Z[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n2713), .CK(clk), .RN(n6961), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n2856), .CK(clk), .RN(n6961), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n2992), .CK(clk), .RN(n6961), .Q(
d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n2444), .CK(clk), .RN(n6961),
.Q(d_ff2_Z[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n2704), .CK(clk), .RN(n6960), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n2850), .CK(clk), .RN(n6960), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n2947), .CK(clk), .RN(n6960), .Q(
d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n2414), .CK(clk), .RN(n6960),
.Q(d_ff2_Z[30]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n2659), .CK(clk), .RN(n6960), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n2820), .CK(clk), .RN(n6959), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n2986), .CK(clk), .RN(n6959), .Q(
d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n2440), .CK(clk), .RN(n6959),
.Q(d_ff2_Z[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n2698), .CK(clk), .RN(n6959), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n2846), .CK(clk), .RN(n6959), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(n2941), .CK(clk), .RN(n6958), .Q(
d_ff_Zn[32]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_32_ ( .D(n2410), .CK(clk), .RN(n6958),
.Q(d_ff2_Z[32]) );
DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(n2653), .CK(clk), .RN(n6958), .Q(
d_ff3_sh_y_out[32]) );
DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(n2816), .CK(clk), .RN(n6958), .Q(
d_ff3_sh_x_out[32]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n2995), .CK(clk), .RN(n6958), .Q(
d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n2446), .CK(clk), .RN(n6958),
.Q(d_ff2_Z[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n2707), .CK(clk), .RN(n6957), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n2852), .CK(clk), .RN(n6957), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n2950), .CK(clk), .RN(n6957), .Q(
d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n2416), .CK(clk), .RN(n6957),
.Q(d_ff2_Z[29]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n2662), .CK(clk), .RN(n6956), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n2822), .CK(clk), .RN(n6956), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n2998), .CK(clk), .RN(n6956), .Q(
d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n2448), .CK(clk), .RN(n6956),
.Q(d_ff2_Z[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n2710), .CK(clk), .RN(n6956), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n2854), .CK(clk), .RN(n6955), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(n2752), .CK(clk), .RN(n6955), .Q(
d_ff_Zn[63]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n2347),
.CK(clk), .RN(n6855), .Q(inst_FPU_PIPELINED_FPADDSUB_intAS) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(n2343), .CK(clk), .RN(n6955), .Q(
d_ff3_sh_y_out[63]) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(n2754), .CK(clk), .RN(n6954), .Q(
d_ff3_sh_x_out[63]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n2980), .CK(clk), .RN(n6954), .Q(
d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n2436), .CK(clk), .RN(n6954),
.Q(d_ff2_Z[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n2692), .CK(clk), .RN(n6954), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n2842), .CK(clk), .RN(n6954), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n2983), .CK(clk), .RN(n6953), .Q(
d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n2438), .CK(clk), .RN(n6953),
.Q(d_ff2_Z[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n2695), .CK(clk), .RN(n6953), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n2844), .CK(clk), .RN(n6953), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n2989), .CK(clk), .RN(n6953), .Q(
d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n2442), .CK(clk), .RN(n6952),
.Q(d_ff2_Z[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n2701), .CK(clk), .RN(n6952), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n2848), .CK(clk), .RN(n6952), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n3007), .CK(clk), .RN(n6952), .Q(
d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n2454), .CK(clk), .RN(n6952),
.Q(d_ff2_Z[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n2719), .CK(clk), .RN(n7012), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n2860), .CK(clk), .RN(n7006), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n3016), .CK(clk), .RN(n7012), .Q(d_ff_Zn[7])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n2460), .CK(clk), .RN(n7009), .Q(
d_ff2_Z[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n2728), .CK(clk), .RN(n6951), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n2866), .CK(clk), .RN(n6951), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n3019), .CK(clk), .RN(n6951), .Q(d_ff_Zn[6])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n2462), .CK(clk), .RN(n6951), .Q(
d_ff2_Z[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n2731), .CK(clk), .RN(n6950), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n2868), .CK(clk), .RN(n6950), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n3022), .CK(clk), .RN(n6950), .Q(d_ff_Zn[5])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n2464), .CK(clk), .RN(n6950), .Q(
d_ff2_Z[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n2734), .CK(clk), .RN(n6950), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n2870), .CK(clk), .RN(n6949), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n2977), .CK(clk), .RN(n6949), .Q(
d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n2434), .CK(clk), .RN(n6949),
.Q(d_ff2_Z[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n2689), .CK(clk), .RN(n6949), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n2840), .CK(clk), .RN(n6948), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n3013), .CK(clk), .RN(n6948), .Q(d_ff_Zn[8])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n2458), .CK(clk), .RN(n6948), .Q(
d_ff2_Z[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n2725), .CK(clk), .RN(n6948), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n2864), .CK(clk), .RN(n6948), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n2974), .CK(clk), .RN(n6947), .Q(
d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n2432), .CK(clk), .RN(n6947),
.Q(d_ff2_Z[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n2686), .CK(clk), .RN(n6947), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n2838), .CK(clk), .RN(n6947), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n3010), .CK(clk), .RN(n6947), .Q(d_ff_Zn[9])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n2456), .CK(clk), .RN(n6946), .Q(
d_ff2_Z[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n2722), .CK(clk), .RN(n6946), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n2862), .CK(clk), .RN(n6946), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n3004), .CK(clk), .RN(n6946), .Q(
d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n2452), .CK(clk), .RN(n6946),
.Q(d_ff2_Z[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n2716), .CK(clk), .RN(n6945), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n2858), .CK(clk), .RN(n6945), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n2971), .CK(clk), .RN(n6945), .Q(
d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n2430), .CK(clk), .RN(n6945),
.Q(d_ff2_Z[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n2683), .CK(clk), .RN(n6944), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n2836), .CK(clk), .RN(n6944), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n2959), .CK(clk), .RN(n6944), .Q(
d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n2422), .CK(clk), .RN(n6944),
.Q(d_ff2_Z[26]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n2671), .CK(clk), .RN(n6944), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n2828), .CK(clk), .RN(n6943), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n2956), .CK(clk), .RN(n6943), .Q(
d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n2420), .CK(clk), .RN(n6943),
.Q(d_ff2_Z[27]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n2668), .CK(clk), .RN(n6943), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n2826), .CK(clk), .RN(n6942), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n2968), .CK(clk), .RN(n6942), .Q(
d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n2428), .CK(clk), .RN(n6942),
.Q(d_ff2_Z[23]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n2680), .CK(clk), .RN(n6942), .Q(
d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n2834), .CK(clk), .RN(n6942), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n2965), .CK(clk), .RN(n6941), .Q(
d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n2426), .CK(clk), .RN(n6941),
.Q(d_ff2_Z[24]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n2677), .CK(clk), .RN(n6941), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n2832), .CK(clk), .RN(n6941), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n2962), .CK(clk), .RN(n6941), .Q(
d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n2424), .CK(clk), .RN(n6940),
.Q(d_ff2_Z[25]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n2674), .CK(clk), .RN(n6940), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n2830), .CK(clk), .RN(n6940), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n3025), .CK(clk), .RN(n6939), .Q(d_ff_Zn[4])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n2466), .CK(clk), .RN(n6939), .Q(
d_ff2_Z[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n2737), .CK(clk), .RN(n6939), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n2872), .CK(clk), .RN(n6938), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n3031), .CK(clk), .RN(n6938), .Q(d_ff_Zn[2])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n2470), .CK(clk), .RN(n6938), .Q(
d_ff2_Z[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n2743), .CK(clk), .RN(n6938), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n2876), .CK(clk), .RN(n6938), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n3034), .CK(clk), .RN(n6937), .Q(d_ff_Zn[1])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n2472), .CK(clk), .RN(n6937), .Q(
d_ff2_Z[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n2746), .CK(clk), .RN(n6937), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n2878), .CK(clk), .RN(n6937), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n3037), .CK(clk), .RN(n6936), .Q(d_ff_Zn[0])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n2474), .CK(clk), .RN(n6936), .Q(
d_ff2_Z[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n2749), .CK(clk), .RN(n6936), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n2880), .CK(clk), .RN(n6936), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n2506),
.CK(clk), .RN(n6905), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
n2274), .CK(clk), .RN(n6913), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
n2272), .CK(clk), .RN(n6913), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(
n2269), .CK(clk), .RN(n6887), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_52_ ( .D(n2257),
.CK(clk), .RN(n6860), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[52]),
.QN(n6704) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_58_ ( .D(n2251),
.CK(clk), .RN(n6861), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[58])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_59_ ( .D(n2250),
.CK(clk), .RN(n6861), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[59])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_60_ ( .D(n2249),
.CK(clk), .RN(n6861), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[60])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_61_ ( .D(n2248),
.CK(clk), .RN(n6861), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[61])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_62_ ( .D(n2247),
.CK(clk), .RN(n6861), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[62])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_52_ ( .D(n2246),
.CK(clk), .RN(n6861), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[52]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_52_ ( .D(n2245),
.CK(clk), .RN(n6861), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[52]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_52_ ( .D(n2244),
.CK(clk), .RN(n6861), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[52]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n2243),
.CK(clk), .RN(n6889), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n2242), .CK(clk), .RN(n6889), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_53_ ( .D(n2241),
.CK(clk), .RN(n6861), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[53]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_53_ ( .D(n2240),
.CK(clk), .RN(n6861), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[53]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_53_ ( .D(n2239),
.CK(clk), .RN(n6862), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[53]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n2238),
.CK(clk), .RN(n6889), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n2237), .CK(clk), .RN(n6889), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_54_ ( .D(n2236),
.CK(clk), .RN(n6862), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[54]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_54_ ( .D(n2235),
.CK(clk), .RN(n6862), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[54]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_54_ ( .D(n2234),
.CK(clk), .RN(n6862), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[54]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n2233),
.CK(clk), .RN(n6890), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_55_ ( .D(n2231),
.CK(clk), .RN(n6862), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[55]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_55_ ( .D(n2230),
.CK(clk), .RN(n6862), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[55]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_55_ ( .D(n2229),
.CK(clk), .RN(n6862), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[55]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n2228),
.CK(clk), .RN(n6890), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_56_ ( .D(n2226),
.CK(clk), .RN(n6862), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[56]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_56_ ( .D(n2225),
.CK(clk), .RN(n6862), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[56]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_56_ ( .D(n2224),
.CK(clk), .RN(n6862), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[56]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n2223),
.CK(clk), .RN(n6890), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_57_ ( .D(n2221),
.CK(clk), .RN(n6863), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[57]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_57_ ( .D(n2220),
.CK(clk), .RN(n6902), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[57]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_57_ ( .D(n2219),
.CK(clk), .RN(n6925), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[57]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n2218),
.CK(clk), .RN(n6890), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_58_ ( .D(n2216),
.CK(clk), .RN(n6863), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[58]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_58_ ( .D(n2215),
.CK(clk), .RN(n6902), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[58]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_58_ ( .D(n2214),
.CK(clk), .RN(n6925), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[58]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n2213),
.CK(clk), .RN(n6890), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_59_ ( .D(n2211),
.CK(clk), .RN(n6863), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[59]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_59_ ( .D(n2210),
.CK(clk), .RN(n6902), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[59]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_59_ ( .D(n2209),
.CK(clk), .RN(n6925), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[59]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n2208),
.CK(clk), .RN(n6891), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_60_ ( .D(n2206),
.CK(clk), .RN(n6863), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[60]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_60_ ( .D(n2205),
.CK(clk), .RN(n6864), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[60]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_60_ ( .D(n2204),
.CK(clk), .RN(n6864), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[60]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n2203),
.CK(clk), .RN(n6891), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[8]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_61_ ( .D(n2201),
.CK(clk), .RN(n6864), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[61]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_61_ ( .D(n2200),
.CK(clk), .RN(n6864), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[61]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_61_ ( .D(n2199),
.CK(clk), .RN(n6864), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[61]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n2198),
.CK(clk), .RN(n6891), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_62_ ( .D(n2196),
.CK(clk), .RN(n6864), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[62]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_62_ ( .D(n2195),
.CK(clk), .RN(n6864), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[62]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_62_ ( .D(n2194),
.CK(clk), .RN(n6864), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[62]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n2193),
.CK(clk), .RN(n6891), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_53_ ( .D(n2190),
.CK(clk), .RN(n6864), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[53]),
.QN(n6709) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_54_ ( .D(n2189),
.CK(clk), .RN(n6865), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[54]),
.QN(n6719) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_55_ ( .D(n2188),
.CK(clk), .RN(n6865), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[55]),
.QN(n6718) );
DFFRX4TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n2183), .CK(clk), .RN(n6912), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_51_ ( .D(n2180),
.CK(clk), .RN(n6865), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[51])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(
n2179), .CK(clk), .RN(n6905), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[51]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_47_ ( .D(n2174),
.CK(clk), .RN(n6865), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[47])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(
n2173), .CK(clk), .RN(n6901), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[47]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_49_ ( .D(n2171),
.CK(clk), .RN(n6865), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[49])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(
n2170), .CK(clk), .RN(n6929), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[49]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_48_ ( .D(n2168),
.CK(clk), .RN(n6865), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[48])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(
n2167), .CK(clk), .RN(n6895), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[48]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_33_ ( .D(n2165),
.CK(clk), .RN(n6866), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[33])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(
n2164), .CK(clk), .RN(n6897), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[33]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_44_ ( .D(n2162),
.CK(clk), .RN(n6866), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[44])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(
n2161), .CK(clk), .RN(n6901), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[44]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n2158), .CK(clk), .RN(n6906), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_34_ ( .D(n2156),
.CK(clk), .RN(n6866), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[34])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(
n2155), .CK(clk), .RN(n6902), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[34]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_45_ ( .D(n2153),
.CK(clk), .RN(n6866), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[45])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(
n2152), .CK(clk), .RN(n6901), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[45]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_35_ ( .D(n2147),
.CK(clk), .RN(n6866), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[35])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(
n2146), .CK(clk), .RN(n6925), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[35]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_42_ ( .D(n2144),
.CK(clk), .RN(n6866), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[42])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(
n2143), .CK(clk), .RN(n6901), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[42]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_43_ ( .D(n2141),
.CK(clk), .RN(n6866), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[43])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(
n2140), .CK(clk), .RN(n6901), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[43]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_36_ ( .D(n2138),
.CK(clk), .RN(n6866), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[36])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(
n2137), .CK(clk), .RN(n6863), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[36]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(
n2134), .CK(clk), .RN(n6902), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[39]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(
n2131), .CK(clk), .RN(n6863), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[41]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_38_ ( .D(n2129),
.CK(clk), .RN(n6867), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[38])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(
n2128), .CK(clk), .RN(n6925), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[38]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_40_ ( .D(n2126),
.CK(clk), .RN(n6867), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[40])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(
n2125), .CK(clk), .RN(n6902), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[40]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(
n2122), .CK(clk), .RN(n6925), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[37]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(
n2119), .CK(clk), .RN(n6898), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_31_ ( .D(n2117),
.CK(clk), .RN(n6867), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[31])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(
n2116), .CK(clk), .RN(n6897), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[31]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n2114),
.CK(clk), .RN(n6867), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(
n2113), .CK(clk), .RN(n6906), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n2111),
.CK(clk), .RN(n6867), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
n2110), .CK(clk), .RN(n6903), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_30_ ( .D(n2108),
.CK(clk), .RN(n6867), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[30])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(
n2107), .CK(clk), .RN(n6897), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
n2104), .CK(clk), .RN(n6900), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_32_ ( .D(n2102),
.CK(clk), .RN(n6868), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[32])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(
n2101), .CK(clk), .RN(n6897), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[32]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n2099),
.CK(clk), .RN(n6868), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
n2098), .CK(clk), .RN(n6906), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(
n2095), .CK(clk), .RN(n6897), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n2093),
.CK(clk), .RN(n6868), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n2092),
.CK(clk), .RN(n6868), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n2091),
.CK(clk), .RN(n6868), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n2090),
.CK(clk), .RN(n6868), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n2089),
.CK(clk), .RN(n6868), .Q(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(
n2088), .CK(clk), .RN(n6883), .Q(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n2086),
.CK(clk), .RN(n6868), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n2085),
.CK(clk), .RN(n6869), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n2084),
.CK(clk), .RN(n6869), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(
n2026), .CK(clk), .RN(n6889), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(
n2022), .CK(clk), .RN(n6889), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
n2019), .CK(clk), .RN(n6900), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n2018),
.CK(clk), .RN(n6869), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n2017),
.CK(clk), .RN(n6869), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n2013),
.CK(clk), .RN(n6869), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
n2012), .CK(clk), .RN(n6900), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n2011),
.CK(clk), .RN(n6869), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n2010),
.CK(clk), .RN(n6869), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n2006),
.CK(clk), .RN(n6869), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
n2005), .CK(clk), .RN(n6903), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n2004),
.CK(clk), .RN(n6869), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n2003),
.CK(clk), .RN(n6870), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1999),
.CK(clk), .RN(n6870), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
n1998), .CK(clk), .RN(n6907), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]), .QN(n6822) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1997),
.CK(clk), .RN(n6870), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1996),
.CK(clk), .RN(n6870), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1994),
.CK(clk), .RN(n6916), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]),
.QN(n3258) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1992),
.CK(clk), .RN(n6870), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1991), .CK(clk), .RN(n6907), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1990),
.CK(clk), .RN(n6870), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1989),
.CK(clk), .RN(n6870), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1988),
.CK(clk), .RN(n6915), .Q(n3180) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1987),
.CK(clk), .RN(n6915), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .QN(
n3246) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1985),
.CK(clk), .RN(n6870), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1984), .CK(clk), .RN(n6907), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1983),
.CK(clk), .RN(n6870), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1982),
.CK(clk), .RN(n6870), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1980),
.CK(clk), .RN(n6915), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .QN(
n3264) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1978),
.CK(clk), .RN(n6871), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1977), .CK(clk), .RN(n6906), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1975),
.CK(clk), .RN(n6871), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
n1974), .CK(clk), .RN(n6899), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1973),
.CK(clk), .RN(n6871), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1972),
.CK(clk), .RN(n6871), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1968),
.CK(clk), .RN(n6871), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1967), .CK(clk), .RN(n6907), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]),
.QN(n6823) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1965),
.CK(clk), .RN(n6871), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
n1964), .CK(clk), .RN(n6899), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1963),
.CK(clk), .RN(n6871), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1962),
.CK(clk), .RN(n6871), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1958),
.CK(clk), .RN(n6871), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1957), .CK(clk), .RN(n6907), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1956),
.CK(clk), .RN(n6871), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1955),
.CK(clk), .RN(n6872), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1951),
.CK(clk), .RN(n6872), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
n1950), .CK(clk), .RN(n6906), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1948),
.CK(clk), .RN(n6872), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
n1947), .CK(clk), .RN(n6898), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1946),
.CK(clk), .RN(n6872), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1945),
.CK(clk), .RN(n6872), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(n1941),
.CK(clk), .RN(n6872), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(
n1940), .CK(clk), .RN(n6897), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1938),
.CK(clk), .RN(n6872), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(
n1937), .CK(clk), .RN(n6897), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(n1935),
.CK(clk), .RN(n6872), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(
n1934), .CK(clk), .RN(n6898), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1933),
.CK(clk), .RN(n6872), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1932),
.CK(clk), .RN(n6872), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(n1928),
.CK(clk), .RN(n6873), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(
n1927), .CK(clk), .RN(n6896), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1926),
.CK(clk), .RN(n6873), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1925),
.CK(clk), .RN(n6873), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1919),
.CK(clk), .RN(n6873), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1918),
.CK(clk), .RN(n6873), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1915),
.CK(clk), .RN(n6873), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1914),
.CK(clk), .RN(n6873), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1911),
.CK(clk), .RN(n6873), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1910),
.CK(clk), .RN(n6873), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1907),
.CK(clk), .RN(n6874), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1906),
.CK(clk), .RN(n6874), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1904),
.CK(clk), .RN(n6916), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]),
.QN(n3266) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1903),
.CK(clk), .RN(n6874), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1902),
.CK(clk), .RN(n6874), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1901),
.CK(clk), .RN(n6915), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1899),
.CK(clk), .RN(n6874), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1898),
.CK(clk), .RN(n6874), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1896),
.CK(clk), .RN(n6915), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .QN(
n3268) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1894),
.CK(clk), .RN(n6874), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1893), .CK(clk), .RN(n6906), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1892),
.CK(clk), .RN(n6874), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1891),
.CK(clk), .RN(n6874), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1887),
.CK(clk), .RN(n6874), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1886), .CK(clk), .RN(n6907), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1885),
.CK(clk), .RN(n6875), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1884),
.CK(clk), .RN(n6875), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1882),
.CK(clk), .RN(n6914), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .QN(
n3272) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1880),
.CK(clk), .RN(n6875), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1879), .CK(clk), .RN(n6907), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1878),
.CK(clk), .RN(n6875), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1877),
.CK(clk), .RN(n6875), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1876),
.CK(clk), .RN(n6914), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1873),
.CK(clk), .RN(n6875), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1872), .CK(clk), .RN(n6907), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1871),
.CK(clk), .RN(n6875), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1870),
.CK(clk), .RN(n6875), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1868),
.CK(clk), .RN(n6914), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .QN(
n3262) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1867),
.CK(clk), .RN(n6875), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1866),
.CK(clk), .RN(n6875), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1865),
.CK(clk), .RN(n6876), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2)
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1864),
.CK(clk), .RN(n6876), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1863),
.CK(clk), .RN(n6876), .Q(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(
n1862), .CK(clk), .RN(n6876), .Q(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
n1859), .CK(clk), .RN(n6906), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1858),
.CK(clk), .RN(n6876), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1857),
.CK(clk), .RN(n6876), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1855),
.CK(clk), .RN(n6916), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]),
.QN(n3270) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1854),
.CK(clk), .RN(n6876), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1853),
.CK(clk), .RN(n6876), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1850),
.CK(clk), .RN(n6877), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1849),
.CK(clk), .RN(n6877), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_32_ ( .D(n1846),
.CK(clk), .RN(n6877), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[32])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1845),
.CK(clk), .RN(n6877), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[32]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1842),
.CK(clk), .RN(n6877), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1841),
.CK(clk), .RN(n6877), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1838),
.CK(clk), .RN(n6877), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1837),
.CK(clk), .RN(n6877), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1834),
.CK(clk), .RN(n6877), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1833),
.CK(clk), .RN(n6877), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1830),
.CK(clk), .RN(n6878), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1829),
.CK(clk), .RN(n6878), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1827),
.CK(clk), .RN(n6916), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]),
.QN(n3260) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_31_ ( .D(n1826),
.CK(clk), .RN(n6878), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[31])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1825),
.CK(clk), .RN(n6878), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[31]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1822),
.CK(clk), .RN(n6878), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1821),
.CK(clk), .RN(n6878), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_37_ ( .D(n1818),
.CK(clk), .RN(n6878), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[37])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1817),
.CK(clk), .RN(n6878), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[37]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1816),
.CK(clk), .RN(n6921), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[37]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_40_ ( .D(n1814),
.CK(clk), .RN(n6878), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[40])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1813),
.CK(clk), .RN(n6878), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[40]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1812),
.CK(clk), .RN(n6922), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[40]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_38_ ( .D(n1810),
.CK(clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[38])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1809),
.CK(clk), .RN(n3223), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[38]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1808),
.CK(clk), .RN(n6921), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[38]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_41_ ( .D(n1806),
.CK(clk), .RN(n6931), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[41])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1805),
.CK(clk), .RN(n3872), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[41]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1804),
.CK(clk), .RN(n6922), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[41]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_39_ ( .D(n1802),
.CK(clk), .RN(n6926), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[39])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1801),
.CK(clk), .RN(n3872), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[39]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1800),
.CK(clk), .RN(n6922), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[39]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_36_ ( .D(n1798),
.CK(clk), .RN(n6926), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[36])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1797),
.CK(clk), .RN(n3872), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[36]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_43_ ( .D(n1794),
.CK(clk), .RN(n3872), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[43])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1793),
.CK(clk), .RN(n3872), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[43]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1792),
.CK(clk), .RN(n6922), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[43]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_42_ ( .D(n1790),
.CK(clk), .RN(n6879), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[42])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1789),
.CK(clk), .RN(n6879), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[42]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1788),
.CK(clk), .RN(n6922), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[42]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_35_ ( .D(n1786),
.CK(clk), .RN(n6879), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[35])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1785),
.CK(clk), .RN(n6879), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[35]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_46_ ( .D(n1782),
.CK(clk), .RN(n6879), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[46])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1781),
.CK(clk), .RN(n6879), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[46]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1780),
.CK(clk), .RN(n6923), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[46]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_45_ ( .D(n1778),
.CK(clk), .RN(n6879), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[45])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1777),
.CK(clk), .RN(n6879), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[45]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1776),
.CK(clk), .RN(n6923), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[45]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_34_ ( .D(n1774),
.CK(clk), .RN(n6879), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[34])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1773),
.CK(clk), .RN(n6879), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[34]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1770),
.CK(clk), .RN(n6880), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1769),
.CK(clk), .RN(n6880), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1768),
.CK(clk), .RN(n6914), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_44_ ( .D(n1766),
.CK(clk), .RN(n6880), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[44])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1765),
.CK(clk), .RN(n6880), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[44]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1764),
.CK(clk), .RN(n6923), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[44]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_33_ ( .D(n1762),
.CK(clk), .RN(n6880), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[33])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1761),
.CK(clk), .RN(n6880), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[33]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_48_ ( .D(n1758),
.CK(clk), .RN(n6880), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[48])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1757),
.CK(clk), .RN(n6880), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[48]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1756),
.CK(clk), .RN(n6923), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[48]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_49_ ( .D(n1754),
.CK(clk), .RN(n6880), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[49])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1753),
.CK(clk), .RN(n6880), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[49]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1752),
.CK(clk), .RN(n6924), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[49]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_47_ ( .D(n1750),
.CK(clk), .RN(n6881), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[47])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1749),
.CK(clk), .RN(n6881), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[47]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1748),
.CK(clk), .RN(n6923), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[47]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_50_ ( .D(n1746),
.CK(clk), .RN(n6881), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[50])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1745),
.CK(clk), .RN(n6881), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[50]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1744),
.CK(clk), .RN(n6924), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[50]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_51_ ( .D(n1742),
.CK(clk), .RN(n6881), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[51])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1741),
.CK(clk), .RN(n6881), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[51]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1740),
.CK(clk), .RN(n6930), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[51]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1738),
.CK(clk), .RN(n6905), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[0]), .QN(n6828) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(n3162), .CK(clk), .RN(n6997), .Q(
cont_iter_out[2]), .QN(n3297) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n2521),
.CK(clk), .RN(n6903), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .QN(n6738) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n2518),
.CK(clk), .RN(n6905), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .QN(n6734) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n2522),
.CK(clk), .RN(n6899), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .QN(n6732) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n2525),
.CK(clk), .RN(n6899), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .QN(n6731) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n2523),
.CK(clk), .RN(n6898), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .QN(n6730) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n2527),
.CK(clk), .RN(n6898), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .QN(n6728) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n2524),
.CK(clk), .RN(n6900), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .QN(n6725) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_51_ ( .D(n2557),
.CK(clk), .RN(n6903), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .QN(n6713) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n2531),
.CK(clk), .RN(n6896), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .QN(n6668) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n3169),
.CK(clk), .RN(n6924), .QN(n6845) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1861),
.CK(clk), .RN(n6876), .Q(zero_flag) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n2185),
.CK(clk), .RN(n6865), .Q(underflow_flag) );
DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(n2276), .CK(clk), .RN(n6936), .Q(
data_output[63]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n2184),
.CK(clk), .RN(n6881), .Q(overflow_flag) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(n2281), .CK(clk), .RN(n6979), .Q(
data_output[59]) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(n2280), .CK(clk), .RN(n6979), .Q(
data_output[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(n2279), .CK(clk), .RN(n6978), .Q(
data_output[61]) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(n2278), .CK(clk), .RN(n6977), .Q(
data_output[62]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n6997), .Q(
inst_CORDIC_FSM_v3_state_reg[6]) );
DFFSX2TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n6997), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n2066), .CK(clk), .RN(n6909), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]),
.QN(n6754) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n2029), .CK(clk), .RN(n6912), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[51]),
.QN(n6706) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n2031), .CK(clk), .RN(n6912), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[49]),
.QN(n6664) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n2028), .CK(clk), .RN(n6912), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[52]),
.QN(n6702) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n2001),
.CK(clk), .RN(n6917), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_32_ ( .D(n1843),
.CK(clk), .RN(n6920), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(
n2742), .CK(clk), .RN(n6859), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1923),
.CK(clk), .RN(n6918), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(
n2649), .CK(clk), .RN(n6850), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n2008),
.CK(clk), .RN(n6917), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1900),
.CK(clk), .RN(n6915), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(
n2715), .CK(clk), .RN(n6858), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]) );
DFFSX4TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n3284),
.CK(clk), .SN(n6926), .Q(n6932), .QN(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ (
.D(inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_),
.CK(clk), .RN(n6847), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(
n6766) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n3170),
.CK(clk), .RN(n6930), .Q(n6637), .QN(n6763) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n3160), .CK(clk), .RN(n6990), .Q(
cont_var_out[0]), .QN(n6642) );
DFFRX2TS VAR_CONT_temp_reg_1_ ( .D(n3159), .CK(clk), .RN(n6990), .Q(
cont_var_out[1]), .QN(n6695) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n2076),
.CK(clk), .RN(n6908), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n6672) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(
n2721), .CK(clk), .RN(n6858), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .QN(n6696) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(
n2455), .CK(clk), .RN(n6858), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .QN(n6663) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(
n2736), .CK(clk), .RN(n6859), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .QN(n6613) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(
n2595), .CK(clk), .RN(n6849), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[51]), .QN(n6745) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n2072),
.CK(clk), .RN(n6909), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n6684) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n2054), .CK(clk), .RN(n6910), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[26]),
.QN(n6703) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
n3040), .CK(clk), .RN(n6908), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .QN(n6652) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n2057), .CK(clk), .RN(n6913), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]),
.QN(n6761) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n2053), .CK(clk), .RN(n6892), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[27]),
.QN(n6708) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n2037), .CK(clk), .RN(n6912), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[43]),
.QN(n6824) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n2052), .CK(clk), .RN(n6910), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[28]),
.QN(n6841) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(
n2401), .CK(clk), .RN(n6852), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[36]), .QN(n6627) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(
n2415), .CK(clk), .RN(n6855), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .QN(n6602) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(
n2427), .CK(clk), .RN(n6859), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .QN(n6622) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(
n2431), .CK(clk), .RN(n6857), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .QN(n6618) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(
n2433), .CK(clk), .RN(n6857), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .QN(n6609) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(
n2437), .CK(clk), .RN(n6856), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .QN(n6621) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(
n2439), .CK(clk), .RN(n6854), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .QN(n6619) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(
n2441), .CK(clk), .RN(n6856), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .QN(n6657) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(
n2443), .CK(clk), .RN(n6854), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .QN(n6617) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(
n2423), .CK(clk), .RN(n6859), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .QN(n6604) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(
n2429), .CK(clk), .RN(n6858), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .QN(n6608) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(
n2449), .CK(clk), .RN(n6854), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .QN(n6611) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(
n2435), .CK(clk), .RN(n6856), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .QN(n6620) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(
n2421), .CK(clk), .RN(n6858), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .QN(n6606) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(
n2447), .CK(clk), .RN(n6855), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .QN(n6614) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(
n2451), .CK(clk), .RN(n6858), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .QN(n6615) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(
n2457), .CK(clk), .RN(n6857), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .QN(n6616) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(
n2467), .CK(clk), .RN(n6851), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .QN(n6612) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(
n2407), .CK(clk), .RN(n6850), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[33]), .QN(n6628) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(
n2375), .CK(clk), .RN(n6850), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[49]), .QN(n6631) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(
n2403), .CK(clk), .RN(n6852), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[35]), .QN(n6629) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(
n2419), .CK(clk), .RN(n6858), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .QN(n6605) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(
n2564), .CK(clk), .RN(n6849), .QN(n6623) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(
n2572), .CK(clk), .RN(n6849), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[57]), .QN(n6643) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(
n2373), .CK(clk), .RN(n6850), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[50]), .QN(n6633) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(
n2383), .CK(clk), .RN(n6851), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[45]), .QN(n6624) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(
n2387), .CK(clk), .RN(n6852), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[43]), .QN(n6626) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(
n2391), .CK(clk), .RN(n6853), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[41]), .QN(n6625) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(
n2411), .CK(clk), .RN(n6854), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .QN(n6607) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(
n2363), .CK(clk), .RN(n6847), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[55]), .QN(n6634) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(
n2367), .CK(clk), .RN(n6847), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[53]), .QN(n6630) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(
n2445), .CK(clk), .RN(n6855), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .QN(n6610) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(
n2601), .CK(clk), .RN(n6850), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[49]), .QN(n6744) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(
n2607), .CK(clk), .RN(n6850), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[47]), .QN(n6751) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(
n2610), .CK(clk), .RN(n6851), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[46]), .QN(n6740) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(
n2622), .CK(clk), .RN(n6852), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[42]), .QN(n6748) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(
n2628), .CK(clk), .RN(n6853), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[40]), .QN(n6750) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(
n2640), .CK(clk), .RN(n6852), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[36]), .QN(n6741) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(
n2646), .CK(clk), .RN(n6851), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[34]), .QN(n6747) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(
n2652), .CK(clk), .RN(n6854), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[32]), .QN(n6746) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(
n2664), .CK(clk), .RN(n6853), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .QN(n6743) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n2033), .CK(clk), .RN(n6912), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[47]),
.QN(n6843) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n2030), .CK(clk), .RN(n6912), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[50]),
.QN(n6710) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n2530),
.CK(clk), .RN(n6896), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .QN(n6726) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n6996), .Q(
inst_CORDIC_FSM_v3_state_reg[7]), .QN(n3291) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
n2182), .CK(clk), .RN(n6889), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n2051), .CK(clk), .RN(n6910), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]),
.QN(n6842) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n2034), .CK(clk), .RN(n6913), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[46]),
.QN(n6720) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
n2023), .CK(clk), .RN(n6888), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n2333), .CK(clk), .RN(n6951), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n2338), .CK(clk), .RN(n6937), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(n2302), .CK(clk), .RN(n7011), .Q(
data_output[38]) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(n2293), .CK(clk), .RN(n6934), .Q(
data_output[47]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1698), .CK(clk), .RN(n6896), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[40]),
.QN(n6768) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_60_ ( .D(n2769), .CK(clk), .RN(n6979),
.Q(d_ff2_X[60]), .QN(n6737) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(
n2469), .CK(clk), .RN(n6859), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .QN(n6645) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(
n2568), .CK(clk), .RN(n6849), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[59]), .QN(n6649) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(
n2395), .CK(clk), .RN(n6852), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[39]), .QN(n6646) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1721), .CK(clk), .RN(n6893), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]),
.QN(n6804) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1684), .CK(clk), .RN(n6891), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[54]),
.QN(n6817) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n2069), .CK(clk), .RN(n6909), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]),
.QN(n6820) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(
n2580), .CK(clk), .RN(n6848), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(
n2661), .CK(clk), .RN(n6855), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(
n2685), .CK(clk), .RN(n6857), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(
n2625), .CK(clk), .RN(n6852), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(
n2673), .CK(clk), .RN(n6859), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(
n2465), .CK(clk), .RN(n6859), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(
n2578), .CK(clk), .RN(n6848), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(
n2724), .CK(clk), .RN(n6857), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(
n2697), .CK(clk), .RN(n6854), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(
n2574), .CK(clk), .RN(n6849), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(
n2667), .CK(clk), .RN(n6858), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(
n2351), .CK(clk), .RN(n6848), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n2074),
.CK(clk), .RN(n6908), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(
n2730), .CK(clk), .RN(n6857), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .QN(n3285) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(
n2619), .CK(clk), .RN(n6852), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .QN(n6739) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(
n2561), .CK(clk), .RN(n6848), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n2079),
.CK(clk), .RN(n6905), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1930),
.CK(clk), .RN(n6918), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_33_ ( .D(n1759),
.CK(clk), .RN(n6920), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[33]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_35_ ( .D(n1783),
.CK(clk), .RN(n6921), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[35]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_42_ ( .D(n1787),
.CK(clk), .RN(n6922), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[42]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_39_ ( .D(n1799),
.CK(clk), .RN(n6921), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[39]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_41_ ( .D(n1803),
.CK(clk), .RN(n6922), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[41]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_37_ ( .D(n1815),
.CK(clk), .RN(n6921), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[37]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1819),
.CK(clk), .RN(n6919), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_31_ ( .D(n1823),
.CK(clk), .RN(n6920), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[31]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1835),
.CK(clk), .RN(n6920), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1839),
.CK(clk), .RN(n6917), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1851),
.CK(clk), .RN(n6919), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1908),
.CK(clk), .RN(n6919), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1912),
.CK(clk), .RN(n6919), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1916),
.CK(clk), .RN(n6919), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1943),
.CK(clk), .RN(n6918), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1960),
.CK(clk), .RN(n6918), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1970),
.CK(clk), .RN(n6918), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n2015),
.CK(clk), .RN(n6917), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_56_ ( .D(n2773), .CK(clk), .RN(n7001),
.Q(d_ff2_X[56]) );
DFFRX2TS reg_val_muxY_2stage_Q_reg_56_ ( .D(n2590), .CK(clk), .RN(n7010),
.Q(d_ff2_Y[56]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(
n2637), .CK(clk), .RN(n6853), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[37]), .QN(n3292) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_31_ ( .D(n2537),
.CK(clk), .RN(n6897), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_37_ ( .D(n2543),
.CK(clk), .RN(n6900), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_36_ ( .D(n2542),
.CK(clk), .RN(n6926), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_42_ ( .D(n2548),
.CK(clk), .RN(n6898), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_38_ ( .D(n2544),
.CK(clk), .RN(n6882), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_32_ ( .D(n2538),
.CK(clk), .RN(n6881), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_35_ ( .D(n2541),
.CK(clk), .RN(n6896), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n2528),
.CK(clk), .RN(n6898), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n2526),
.CK(clk), .RN(n6899), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_34_ ( .D(n1771),
.CK(clk), .RN(n6920), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[34]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_36_ ( .D(n1795),
.CK(clk), .RN(n6921), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[36]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_38_ ( .D(n1807),
.CK(clk), .RN(n6921), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[38]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_40_ ( .D(n1811),
.CK(clk), .RN(n6922), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[40]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(
n2733), .CK(clk), .RN(n6857), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .QN(n3286) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(
n2359), .CK(clk), .RN(n6848), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[57]), .QN(n3294) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(
n2727), .CK(clk), .RN(n6856), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .QN(n3283) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_45_ ( .D(n2551),
.CK(clk), .RN(n6900), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_48_ ( .D(n2554),
.CK(clk), .RN(n6901), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_49_ ( .D(n2555),
.CK(clk), .RN(n6900), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_50_ ( .D(n1743),
.CK(clk), .RN(n6924), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[50]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_48_ ( .D(n1755),
.CK(clk), .RN(n6923), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_46_ ( .D(n1779),
.CK(clk), .RN(n6923), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[46]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_47_ ( .D(n1747),
.CK(clk), .RN(n6923), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[47]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_49_ ( .D(n1751),
.CK(clk), .RN(n6923), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[49]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_45_ ( .D(n1775),
.CK(clk), .RN(n6923), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[45]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_44_ ( .D(n1763),
.CK(clk), .RN(n6922), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[44]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_51_ ( .D(n1739),
.CK(clk), .RN(n6931), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[51]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_43_ ( .D(n1791),
.CK(clk), .RN(n6922), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[43]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n2077),
.CK(clk), .RN(n6908), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]) );
DFFRX4TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n2070), .CK(clk), .RN(n6909), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]),
.QN(n6733) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n2202), .CK(clk), .RN(n6891), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[8]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n2212), .CK(clk), .RN(n6890), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n2222), .CK(clk), .RN(n6890), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(
n2385), .CK(clk), .RN(n6851), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[44]), .QN(n6694) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_59_ ( .D(n2770), .CK(clk), .RN(n6980),
.Q(d_ff2_X[59]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_57_ ( .D(n2589), .CK(clk), .RN(n6981),
.Q(d_ff2_Y[57]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_59_ ( .D(n2587), .CK(clk), .RN(n6980),
.Q(d_ff2_Y[59]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n3219), .CK(clk), .RN(n6847), .Q(ready_add_subt) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1881),
.CK(clk), .RN(n6888), .Q(result_add_subt[1]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1888),
.CK(clk), .RN(n6888), .Q(result_add_subt[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1895),
.CK(clk), .RN(n6888), .Q(result_add_subt[4]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1929), .CK(clk), .RN(n6886), .Q(result_add_subt[24]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1936), .CK(clk), .RN(n6886), .Q(result_add_subt[23]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1939), .CK(clk), .RN(n6886), .Q(result_add_subt[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1942), .CK(clk), .RN(n6886), .Q(result_add_subt[26]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1949), .CK(clk), .RN(n6886), .Q(result_add_subt[22]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1952), .CK(clk), .RN(n6887), .Q(result_add_subt[11]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1959),
.CK(clk), .RN(n6904), .Q(result_add_subt[9]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1966), .CK(clk), .RN(n6886), .Q(result_add_subt[21]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1976), .CK(clk), .RN(n6886), .Q(result_add_subt[20]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1993),
.CK(clk), .RN(n6888), .Q(result_add_subt[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n2000), .CK(clk), .RN(n6930), .Q(result_add_subt[10]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n2007), .CK(clk), .RN(n6895), .Q(result_add_subt[16]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n2014), .CK(clk), .RN(n6886), .Q(result_add_subt[18]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n2021), .CK(clk), .RN(n6886), .Q(result_add_subt[19]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n2094), .CK(clk), .RN(n6887), .Q(result_add_subt[13]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n2097), .CK(clk), .RN(n6885), .Q(result_add_subt[29]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n2100), .CK(clk), .RN(n6904), .Q(result_add_subt[14]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_32_ ( .D(n2103), .CK(clk), .RN(n6885), .Q(result_add_subt[32]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n2106), .CK(clk), .RN(n6930), .Q(result_add_subt[17]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n2109), .CK(clk), .RN(n6885), .Q(result_add_subt[30]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n2112), .CK(clk), .RN(n6895), .Q(result_add_subt[15]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n2118), .CK(clk), .RN(n6885), .Q(result_add_subt[31]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n2121), .CK(clk), .RN(n6885), .Q(result_add_subt[28]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_37_ ( .D(n2124), .CK(clk), .RN(n6885), .Q(result_add_subt[37]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_40_ ( .D(n2127), .CK(clk), .RN(n6884), .Q(result_add_subt[40]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_38_ ( .D(n2130), .CK(clk), .RN(n6884), .Q(result_add_subt[38]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n2133), .CK(clk), .RN(n6884), .Q(result_add_subt[41]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_39_ ( .D(n2136), .CK(clk), .RN(n6884), .Q(result_add_subt[39]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_36_ ( .D(n2139), .CK(clk), .RN(n6885), .Q(result_add_subt[36]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n2142), .CK(clk), .RN(n6884), .Q(result_add_subt[43]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n2145), .CK(clk), .RN(n6884), .Q(result_add_subt[42]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_35_ ( .D(n2148), .CK(clk), .RN(n6885), .Q(result_add_subt[35]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n2151), .CK(clk), .RN(n6884), .Q(result_add_subt[46]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n2154), .CK(clk), .RN(n6884), .Q(result_add_subt[45]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_34_ ( .D(n2157), .CK(clk), .RN(n6885), .Q(result_add_subt[34]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n2160),
.CK(clk), .RN(n6888), .Q(result_add_subt[3]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n2163), .CK(clk), .RN(n6884), .Q(result_add_subt[44]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_33_ ( .D(n2166), .CK(clk), .RN(n6885), .Q(result_add_subt[33]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n2169), .CK(clk), .RN(n6883), .Q(result_add_subt[48]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n2172), .CK(clk), .RN(n6883), .Q(result_add_subt[49]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n2175), .CK(clk), .RN(n6884), .Q(result_add_subt[47]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n2178), .CK(clk), .RN(n6883), .Q(result_add_subt[50]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1874),
.CK(clk), .RN(n6888), .Q(result_add_subt[0]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1969),
.CK(clk), .RN(n6887), .Q(result_add_subt[8]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1979),
.CK(clk), .RN(n6888), .Q(result_add_subt[5]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1986),
.CK(clk), .RN(n6888), .Q(result_add_subt[6]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n2115), .CK(clk), .RN(n6904), .Q(result_add_subt[12]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n2516),
.CK(clk), .RN(n6930), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n2559),
.CK(clk), .RN(n6905), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]), .QN(n6711) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_52_ ( .D(n2558),
.CK(clk), .RN(n6928), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]), .QN(n6712) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(
n2357), .CK(clk), .RN(n6848), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[58]), .QN(n3282) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_54_ ( .D(n2560),
.CK(clk), .RN(n6929), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]), .QN(n6714) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n2259), .CK(clk), .RN(n6883), .Q(result_add_subt[61]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n2261), .CK(clk), .RN(n6883), .Q(result_add_subt[59]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n2262), .CK(clk), .RN(n6883), .Q(result_add_subt[58]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n2266), .CK(clk), .RN(n6883), .Q(result_add_subt[54]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n2268), .CK(clk), .RN(n6883), .Q(result_add_subt[52]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1922), .CK(clk), .RN(n6886), .Q(result_add_subt[25]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n2514),
.CK(clk), .RN(n6905), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n2181), .CK(clk), .RN(n6888), .Q(result_add_subt[51]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n2260), .CK(clk), .RN(n6882), .Q(result_add_subt[60]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n2263), .CK(clk), .RN(n6882), .Q(result_add_subt[57]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n2264), .CK(clk), .RN(n6882), .Q(result_add_subt[56]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n2265), .CK(clk), .RN(n6882), .Q(result_add_subt[55]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n2267), .CK(clk), .RN(n6882), .Q(result_add_subt[53]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n2258), .CK(clk), .RN(n6882), .Q(result_add_subt[62]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n2197), .CK(clk), .RN(n6891), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[9]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n2207), .CK(clk), .RN(n6891), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n2217), .CK(clk), .RN(n6890), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n2227), .CK(clk), .RN(n6890), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n2232), .CK(clk), .RN(n6890), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
n2192), .CK(clk), .RN(n6891), .Q(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[10]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n2083),
.CK(clk), .RN(n6913), .Q(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n3171),
.CK(clk), .RN(n6847), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .QN(n6666) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_55_ ( .D(n2774), .CK(clk), .RN(n7001),
.Q(d_ff2_X[55]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_54_ ( .D(n2775), .CK(clk), .RN(n6982),
.Q(d_ff2_X[54]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_53_ ( .D(n2776), .CK(clk), .RN(n6983),
.Q(d_ff2_X[53]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_55_ ( .D(n2254),
.CK(clk), .RN(n6860), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[55])
);
DFFRX1TS reg_val_muxY_2stage_Q_reg_55_ ( .D(n2591), .CK(clk), .RN(n6982),
.Q(d_ff2_Y[55]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_53_ ( .D(n2593), .CK(clk), .RN(n6983),
.Q(d_ff2_Y[53]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n2513),
.CK(clk), .RN(n6903), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n2520),
.CK(clk), .RN(n6903), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .QN(n6735) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n2512),
.CK(clk), .RN(n6903), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_63_ ( .D(n2349), .CK(clk), .RN(n6955),
.Q(d_ff2_Z[63]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n2515),
.CK(clk), .RN(n6907), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .QN(n6736) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_52_ ( .D(n2191),
.CK(clk), .RN(n6864), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[52])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n2519),
.CK(clk), .RN(n6906), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .QN(n6755) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n2032), .CK(clk), .RN(n6912), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[48]),
.QN(n3252) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n2082),
.CK(clk), .RN(n6891), .Q(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM)
);
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n2829), .CK(clk), .RN(n6943),
.Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n2859), .CK(clk), .RN(n6945),
.Q(d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n2863), .CK(clk), .RN(n6946), .Q(
d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n2865), .CK(clk), .RN(n6948), .Q(
d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n2869), .CK(clk), .RN(n6950), .Q(
d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n2867), .CK(clk), .RN(n6951), .Q(
d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n2843), .CK(clk), .RN(n6954),
.Q(d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n2855), .CK(clk), .RN(n6955),
.Q(d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n2853), .CK(clk), .RN(n6957),
.Q(d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_32_ ( .D(n2817), .CK(clk), .RN(n6958),
.Q(d_ff2_X[32]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n2819), .CK(clk), .RN(n6962),
.Q(d_ff2_X[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n2825), .CK(clk), .RN(n6963),
.Q(d_ff2_X[28]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_41_ ( .D(n2799), .CK(clk), .RN(n6966),
.Q(d_ff2_X[41]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_39_ ( .D(n2803), .CK(clk), .RN(n6967),
.Q(d_ff2_X[39]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_43_ ( .D(n2795), .CK(clk), .RN(n6968),
.Q(d_ff2_X[43]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_42_ ( .D(n2797), .CK(clk), .RN(n6969),
.Q(d_ff2_X[42]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_46_ ( .D(n2789), .CK(clk), .RN(n6971),
.Q(d_ff2_X[46]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_45_ ( .D(n2791), .CK(clk), .RN(n6971),
.Q(d_ff2_X[45]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_34_ ( .D(n2813), .CK(clk), .RN(n6972),
.Q(d_ff2_X[34]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n2875), .CK(clk), .RN(n6973), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_48_ ( .D(n2785), .CK(clk), .RN(n7002),
.Q(d_ff2_X[48]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n2750), .CK(clk), .RN(n6936), .Q(
d_ff2_Y[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n2747), .CK(clk), .RN(n6937), .Q(
d_ff2_Y[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n2877), .CK(clk), .RN(n6938), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n2738), .CK(clk), .RN(n6939), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n2831), .CK(clk), .RN(n6940),
.Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n2678), .CK(clk), .RN(n6941),
.Q(d_ff2_Y[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n2835), .CK(clk), .RN(n6942),
.Q(d_ff2_X[23]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n2827), .CK(clk), .RN(n6943),
.Q(d_ff2_X[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n2837), .CK(clk), .RN(n6944),
.Q(d_ff2_X[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n2839), .CK(clk), .RN(n6947),
.Q(d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n2841), .CK(clk), .RN(n6949),
.Q(d_ff2_X[20]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n2871), .CK(clk), .RN(n6949), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n2720), .CK(clk), .RN(n7008),
.Q(d_ff2_Y[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n2849), .CK(clk), .RN(n6952),
.Q(d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n2845), .CK(clk), .RN(n6953),
.Q(d_ff2_X[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n2663), .CK(clk), .RN(n6957),
.Q(d_ff2_Y[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n2847), .CK(clk), .RN(n6959),
.Q(d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n2821), .CK(clk), .RN(n6959),
.Q(d_ff2_X[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n2851), .CK(clk), .RN(n6960),
.Q(d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n2857), .CK(clk), .RN(n6961),
.Q(d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_37_ ( .D(n2807), .CK(clk), .RN(n6963),
.Q(d_ff2_X[37]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_40_ ( .D(n2801), .CK(clk), .RN(n6964),
.Q(d_ff2_X[40]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_38_ ( .D(n2636), .CK(clk), .RN(n6965),
.Q(d_ff2_Y[38]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_36_ ( .D(n2642), .CK(clk), .RN(n6968),
.Q(d_ff2_Y[36]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_35_ ( .D(n2645), .CK(clk), .RN(n6970),
.Q(d_ff2_Y[35]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_44_ ( .D(n2618), .CK(clk), .RN(n6974),
.Q(d_ff2_Y[44]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_33_ ( .D(n2651), .CK(clk), .RN(n6999),
.Q(d_ff2_Y[33]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_49_ ( .D(n2603), .CK(clk), .RN(n6976),
.Q(d_ff2_Y[49]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_47_ ( .D(n2787), .CK(clk), .RN(n6976),
.Q(d_ff2_X[47]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_50_ ( .D(n2781), .CK(clk), .RN(n7007),
.Q(d_ff2_X[50]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n2881), .CK(clk), .RN(n6936), .Q(
d_ff2_X[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n2833), .CK(clk), .RN(n6941),
.Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n2823), .CK(clk), .RN(n6956),
.Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_36_ ( .D(n2809), .CK(clk), .RN(n6967),
.Q(d_ff2_X[36]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_35_ ( .D(n2811), .CK(clk), .RN(n6970),
.Q(d_ff2_X[35]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_49_ ( .D(n2783), .CK(clk), .RN(n6975),
.Q(d_ff2_X[49]) );
DFFRX1TS d_ff4_Xn_Q_reg_63_ ( .D(n2341), .CK(clk), .RN(n6955), .Q(
d_ff_Xn[63]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n2879), .CK(clk), .RN(n6937), .Q(
d_ff2_X[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n2669), .CK(clk), .RN(n6943),
.Q(d_ff2_Y[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n2684), .CK(clk), .RN(n6945),
.Q(d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n2723), .CK(clk), .RN(n6946), .Q(
d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n2735), .CK(clk), .RN(n6950), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n2729), .CK(clk), .RN(n6951), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n2861), .CK(clk), .RN(n7008),
.Q(d_ff2_X[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n2708), .CK(clk), .RN(n6957),
.Q(d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n2714), .CK(clk), .RN(n6961),
.Q(d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_37_ ( .D(n2639), .CK(clk), .RN(n6964),
.Q(d_ff2_Y[37]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_40_ ( .D(n2630), .CK(clk), .RN(n6965),
.Q(d_ff2_Y[40]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_38_ ( .D(n2805), .CK(clk), .RN(n6965),
.Q(d_ff2_X[38]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_42_ ( .D(n2624), .CK(clk), .RN(n6969),
.Q(d_ff2_Y[42]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_33_ ( .D(n2815), .CK(clk), .RN(n6999),
.Q(d_ff2_X[33]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_47_ ( .D(n2609), .CK(clk), .RN(n6976),
.Q(d_ff2_Y[47]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_50_ ( .D(n2600), .CK(clk), .RN(n7007),
.Q(d_ff2_Y[50]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1831),
.CK(clk), .RN(n6917), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n3710), .CK(clk), .RN(
n6996), .Q(inst_CORDIC_FSM_v3_state_reg[3]), .QN(n3191) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n3110), .CK(clk), .RN(n6996), .Q(
d_ff1_operation_out), .QN(n6636) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n3109), .CK(clk), .RN(n6996), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n6757) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(
n2342), .CK(clk), .RN(n6855), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[63]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(
n2025), .CK(clk), .RN(n6889), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRX1TS reg_LUT_Q_reg_48_ ( .D(n3152), .CK(clk), .RN(n6990), .Q(
d_ff3_LUT_out[48]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(
n2753), .CK(clk), .RN(n6855), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[63]), .QN(n6765) );
DFFRX1TS reg_LUT_Q_reg_11_ ( .D(n3122), .CK(clk), .RN(n6987), .Q(
d_ff3_LUT_out[11]) );
DFFRX1TS reg_LUT_Q_reg_8_ ( .D(n3119), .CK(clk), .RN(n6987), .Q(
d_ff3_LUT_out[8]) );
DFFRX1TS reg_LUT_Q_reg_15_ ( .D(n3126), .CK(clk), .RN(n6987), .Q(
d_ff3_LUT_out[15]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1844),
.CK(clk), .RN(n6920), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[32]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1924),
.CK(clk), .RN(n6919), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n2002),
.CK(clk), .RN(n6917), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n2009),
.CK(clk), .RN(n6917), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
n2273), .CK(clk), .RN(n6908), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRX1TS reg_LUT_Q_reg_6_ ( .D(n3117), .CK(clk), .RN(n6989), .Q(
d_ff3_LUT_out[6]) );
DFFRX1TS reg_LUT_Q_reg_10_ ( .D(n3121), .CK(clk), .RN(n6989), .Q(
d_ff3_LUT_out[10]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(
n2149), .CK(clk), .RN(n6901), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[46]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_28_ ( .D(n2120),
.CK(clk), .RN(n6867), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[28])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_39_ ( .D(n2135),
.CK(clk), .RN(n6867), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[39])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n2159),
.CK(clk), .RN(n6866), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_50_ ( .D(n2177),
.CK(clk), .RN(n6865), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[50])
);
DFFRX1TS reg_LUT_Q_reg_2_ ( .D(n3113), .CK(clk), .RN(n6987), .Q(
d_ff3_LUT_out[2]) );
DFFRX1TS reg_LUT_Q_reg_14_ ( .D(n3125), .CK(clk), .RN(n6988), .Q(
d_ff3_LUT_out[14]) );
DFFRX1TS reg_LUT_Q_reg_3_ ( .D(n3114), .CK(clk), .RN(n6989), .Q(
d_ff3_LUT_out[3]) );
DFFRX1TS reg_LUT_Q_reg_33_ ( .D(n3143), .CK(clk), .RN(n6987), .Q(
d_ff3_LUT_out[33]) );
DFFRX1TS reg_LUT_Q_reg_9_ ( .D(n3120), .CK(clk), .RN(n6987), .Q(
d_ff3_LUT_out[9]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n2508),
.CK(clk), .RN(n6895), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n2517),
.CK(clk), .RN(n6903), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .QN(n6759) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n2509),
.CK(clk), .RN(n6903), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
n2270), .CK(clk), .RN(n6908), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(
n2598), .CK(clk), .RN(n6849), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(
n2676), .CK(clk), .RN(n6859), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(
n2670), .CK(clk), .RN(n6858), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(
n2688), .CK(clk), .RN(n6857), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(
n2691), .CK(clk), .RN(n6856), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(
n2700), .CK(clk), .RN(n6856), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .QN(n3277) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(
n2718), .CK(clk), .RN(n6856), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .QN(n3281) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(
n2748), .CK(clk), .RN(n6860), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(
n2582), .CK(clk), .RN(n6848), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .QN(n3290) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(
n2739), .CK(clk), .RN(n6851), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(
n2576), .CK(clk), .RN(n6848), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_47_ ( .D(n2553),
.CK(clk), .RN(n6899), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_44_ ( .D(n2550),
.CK(clk), .RN(n6901), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(
n2355), .CK(clk), .RN(n6848), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[59]), .QN(n3287) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_56_ ( .D(n2253),
.CK(clk), .RN(n6860), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[56])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(
n2679), .CK(clk), .RN(n6859), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(
n2655), .CK(clk), .RN(n6853), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(
n2703), .CK(clk), .RN(n6854), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(
n2369), .CK(clk), .RN(n6847), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[52]), .QN(n6685) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(
n2634), .CK(clk), .RN(n6853), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[38]), .QN(n6764) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_26_ ( .D(n2532),
.CK(clk), .RN(n6896), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]), .QN(n6667) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_27_ ( .D(n2533),
.CK(clk), .RN(n6897), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]), .QN(n6727) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(
n2616), .CK(clk), .RN(n6850), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[44]), .QN(n6742) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(
n2353), .CK(clk), .RN(n6848), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[60]), .QN(n3278) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_57_ ( .D(n2772), .CK(clk), .RN(n6981),
.Q(d_ff2_X[57]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(
n2712), .CK(clk), .RN(n6854), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(
n2631), .CK(clk), .RN(n6852), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_54_ ( .D(n2255),
.CK(clk), .RN(n6860), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[54])
);
DFFRX1TS reg_val_muxY_2stage_Q_reg_54_ ( .D(n2592), .CK(clk), .RN(n6982),
.Q(d_ff2_Y[54]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_53_ ( .D(n2256),
.CK(clk), .RN(n6860), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[53])
);
DFFRX4TS ITER_CONT_temp_reg_1_ ( .D(n3163), .CK(clk), .RN(n6997), .Q(
cont_iter_out[1]), .QN(n6670) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_56_ ( .D(n2187),
.CK(clk), .RN(n6865), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[56])
);
DFFRX1TS d_ff4_Xn_Q_reg_58_ ( .D(n2485), .CK(clk), .RN(n6980), .Q(
d_ff_Xn[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(n2298), .CK(clk), .RN(n7011), .Q(
data_output[42]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n3035), .CK(clk), .RN(n6936), .Q(d_ff_Xn[0])
);
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(n2304), .CK(clk), .RN(n7006), .Q(
data_output[36]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n2957), .CK(clk), .RN(n6943), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n2963), .CK(clk), .RN(n6941), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n3008), .CK(clk), .RN(n6946), .Q(d_ff_Xn[9])
);
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n3002), .CK(clk), .RN(n6945), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n3017), .CK(clk), .RN(n6950), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n3011), .CK(clk), .RN(n6948), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n2978), .CK(clk), .RN(n6954), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n3014), .CK(clk), .RN(n6951), .Q(d_ff_Xn[7])
);
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n2948), .CK(clk), .RN(n6956), .Q(
d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n2996), .CK(clk), .RN(n6956), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_32_ ( .D(n2939), .CK(clk), .RN(n6958), .Q(
d_ff_Xn[32]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n2993), .CK(clk), .RN(n6957), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n2951), .CK(clk), .RN(n6963), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n2942), .CK(clk), .RN(n6962), .Q(
d_ff_Xn[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_39_ ( .D(n2918), .CK(clk), .RN(n6967), .Q(
d_ff_Xn[39]) );
DFFRX1TS d_ff4_Xn_Q_reg_41_ ( .D(n2912), .CK(clk), .RN(n6966), .Q(
d_ff_Xn[41]) );
DFFRX1TS d_ff4_Xn_Q_reg_43_ ( .D(n2906), .CK(clk), .RN(n6968), .Q(
d_ff_Xn[43]) );
DFFRX1TS d_ff4_Xn_Q_reg_36_ ( .D(n2927), .CK(clk), .RN(n6968), .Q(
d_ff_Xn[36]) );
DFFRX1TS d_ff4_Xn_Q_reg_35_ ( .D(n2930), .CK(clk), .RN(n6970), .Q(
d_ff_Xn[35]) );
DFFRX1TS d_ff4_Xn_Q_reg_42_ ( .D(n2909), .CK(clk), .RN(n6969), .Q(
d_ff_Xn[42]) );
DFFRX1TS d_ff4_Xn_Q_reg_45_ ( .D(n2900), .CK(clk), .RN(n6972), .Q(
d_ff_Xn[45]) );
DFFRX1TS d_ff4_Xn_Q_reg_46_ ( .D(n2897), .CK(clk), .RN(n6971), .Q(
d_ff_Xn[46]) );
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n3026), .CK(clk), .RN(n6973), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_34_ ( .D(n2933), .CK(clk), .RN(n6972), .Q(
d_ff_Xn[34]) );
DFFRX1TS d_ff4_Xn_Q_reg_49_ ( .D(n2888), .CK(clk), .RN(n6975), .Q(
d_ff_Xn[49]) );
DFFRX1TS d_ff4_Xn_Q_reg_48_ ( .D(n2891), .CK(clk), .RN(n6975), .Q(
d_ff_Xn[48]) );
DFFRX1TS d_ff4_Xn_Q_reg_59_ ( .D(n2482), .CK(clk), .RN(n6980), .Q(
d_ff_Xn[59]) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n3032), .CK(clk), .RN(n6937), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_54_ ( .D(n2497), .CK(clk), .RN(n6982), .Q(
d_ff_Xn[54]) );
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n3023), .CK(clk), .RN(n6939), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n3029), .CK(clk), .RN(n6938), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n2966), .CK(clk), .RN(n6942), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n2960), .CK(clk), .RN(n6940), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n2969), .CK(clk), .RN(n6944), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n2954), .CK(clk), .RN(n6943), .Q(
d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n2975), .CK(clk), .RN(n6949), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n2972), .CK(clk), .RN(n6947), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n3005), .CK(clk), .RN(n7009), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n3020), .CK(clk), .RN(n6949), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n2981), .CK(clk), .RN(n6953), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n2987), .CK(clk), .RN(n6952), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n2945), .CK(clk), .RN(n6960), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n2984), .CK(clk), .RN(n6959), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n2999), .CK(clk), .RN(n6961), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n2990), .CK(clk), .RN(n6960), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_40_ ( .D(n2915), .CK(clk), .RN(n6964), .Q(
d_ff_Xn[40]) );
DFFRX1TS d_ff4_Xn_Q_reg_37_ ( .D(n2924), .CK(clk), .RN(n6964), .Q(
d_ff_Xn[37]) );
DFFRX1TS d_ff4_Xn_Q_reg_44_ ( .D(n2903), .CK(clk), .RN(n6974), .Q(
d_ff_Xn[44]) );
DFFRX1TS d_ff4_Xn_Q_reg_38_ ( .D(n2921), .CK(clk), .RN(n6965), .Q(
d_ff_Xn[38]) );
DFFRX1TS d_ff4_Xn_Q_reg_47_ ( .D(n2894), .CK(clk), .RN(n6976), .Q(
d_ff_Xn[47]) );
DFFRX1TS d_ff4_Xn_Q_reg_33_ ( .D(n2936), .CK(clk), .RN(n7004), .Q(
d_ff_Xn[33]) );
DFFRX1TS d_ff4_Xn_Q_reg_52_ ( .D(n2503), .CK(clk), .RN(n6984), .Q(
d_ff_Xn[52]) );
DFFRX1TS d_ff4_Xn_Q_reg_50_ ( .D(n2885), .CK(clk), .RN(n7003), .Q(
d_ff_Xn[50]) );
DFFRX1TS d_ff4_Yn_Q_reg_19_ ( .D(n2979), .CK(clk), .RN(n6954), .Q(
d_ff_Yn[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(n2297), .CK(clk), .RN(n7007), .Q(
data_output[43]) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(n2300), .CK(clk), .RN(n7007), .Q(
data_output[40]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n2511),
.CK(clk), .RN(n6906), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n2510),
.CK(clk), .RN(n6905), .Q(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DMP_Q_reg_57_ ( .D(n2252),
.CK(clk), .RN(n6860), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[57])
);
DFFRX1TS d_ff4_Yn_Q_reg_0_ ( .D(n3036), .CK(clk), .RN(n6936), .Q(d_ff_Yn[0])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1689), .CK(clk), .RN(n6900), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[49]),
.QN(n6788) );
DFFRX1TS d_ff4_Yn_Q_reg_2_ ( .D(n3030), .CK(clk), .RN(n6938), .Q(d_ff_Yn[2])
);
DFFRX1TS d_ff4_Yn_Q_reg_1_ ( .D(n3033), .CK(clk), .RN(n6937), .Q(d_ff_Yn[1])
);
DFFRX1TS d_ff4_Yn_Q_reg_25_ ( .D(n2961), .CK(clk), .RN(n6940), .Q(
d_ff_Yn[25]) );
DFFRX1TS d_ff4_Yn_Q_reg_4_ ( .D(n3024), .CK(clk), .RN(n6939), .Q(d_ff_Yn[4])
);
DFFRX1TS d_ff4_Yn_Q_reg_23_ ( .D(n2967), .CK(clk), .RN(n6942), .Q(
d_ff_Yn[23]) );
DFFRX1TS d_ff4_Yn_Q_reg_24_ ( .D(n2964), .CK(clk), .RN(n6941), .Q(
d_ff_Yn[24]) );
DFFRX1TS d_ff4_Yn_Q_reg_26_ ( .D(n2958), .CK(clk), .RN(n6944), .Q(
d_ff_Yn[26]) );
DFFRX1TS d_ff4_Yn_Q_reg_27_ ( .D(n2955), .CK(clk), .RN(n6943), .Q(
d_ff_Yn[27]) );
DFFRX1TS d_ff4_Yn_Q_reg_11_ ( .D(n3003), .CK(clk), .RN(n6945), .Q(
d_ff_Yn[11]) );
DFFRX1TS d_ff4_Yn_Q_reg_22_ ( .D(n2970), .CK(clk), .RN(n6945), .Q(
d_ff_Yn[22]) );
DFFRX1TS d_ff4_Yn_Q_reg_21_ ( .D(n2973), .CK(clk), .RN(n6947), .Q(
d_ff_Yn[21]) );
DFFRX1TS d_ff4_Yn_Q_reg_9_ ( .D(n3009), .CK(clk), .RN(n6946), .Q(d_ff_Yn[9])
);
DFFRX1TS d_ff4_Yn_Q_reg_20_ ( .D(n2976), .CK(clk), .RN(n6949), .Q(
d_ff_Yn[20]) );
DFFRX1TS d_ff4_Yn_Q_reg_8_ ( .D(n3012), .CK(clk), .RN(n6948), .Q(d_ff_Yn[8])
);
DFFRX1TS d_ff4_Yn_Q_reg_6_ ( .D(n3018), .CK(clk), .RN(n6951), .Q(d_ff_Yn[6])
);
DFFRX1TS d_ff4_Yn_Q_reg_5_ ( .D(n3021), .CK(clk), .RN(n6950), .Q(d_ff_Yn[5])
);
DFFRX1TS d_ff4_Yn_Q_reg_16_ ( .D(n2988), .CK(clk), .RN(n6952), .Q(
d_ff_Yn[16]) );
DFFRX1TS d_ff4_Yn_Q_reg_10_ ( .D(n3006), .CK(clk), .RN(n7009), .Q(
d_ff_Yn[10]) );
DFFRX1TS d_ff4_Yn_Q_reg_13_ ( .D(n2997), .CK(clk), .RN(n6956), .Q(
d_ff_Yn[13]) );
DFFRX1TS d_ff4_Yn_Q_reg_18_ ( .D(n2982), .CK(clk), .RN(n6953), .Q(
d_ff_Yn[18]) );
DFFRX1TS d_ff4_Yn_Q_reg_14_ ( .D(n2994), .CK(clk), .RN(n6957), .Q(
d_ff_Yn[14]) );
DFFRX1TS d_ff4_Yn_Q_reg_29_ ( .D(n2949), .CK(clk), .RN(n6957), .Q(
d_ff_Yn[29]) );
DFFRX1TS d_ff4_Yn_Q_reg_17_ ( .D(n2985), .CK(clk), .RN(n6959), .Q(
d_ff_Yn[17]) );
DFFRX1TS d_ff4_Yn_Q_reg_32_ ( .D(n2940), .CK(clk), .RN(n6958), .Q(
d_ff_Yn[32]) );
DFFRX1TS d_ff4_Yn_Q_reg_15_ ( .D(n2991), .CK(clk), .RN(n6961), .Q(
d_ff_Yn[15]) );
DFFRX1TS d_ff4_Yn_Q_reg_30_ ( .D(n2946), .CK(clk), .RN(n6960), .Q(
d_ff_Yn[30]) );
DFFRX1TS d_ff4_Yn_Q_reg_31_ ( .D(n2943), .CK(clk), .RN(n6962), .Q(
d_ff_Yn[31]) );
DFFRX1TS d_ff4_Yn_Q_reg_12_ ( .D(n3000), .CK(clk), .RN(n6961), .Q(
d_ff_Yn[12]) );
DFFRX1TS d_ff4_Yn_Q_reg_37_ ( .D(n2925), .CK(clk), .RN(n6964), .Q(
d_ff_Yn[37]) );
DFFRX1TS d_ff4_Yn_Q_reg_28_ ( .D(n2952), .CK(clk), .RN(n6963), .Q(
d_ff_Yn[28]) );
DFFRX1TS d_ff4_Yn_Q_reg_38_ ( .D(n2922), .CK(clk), .RN(n6965), .Q(
d_ff_Yn[38]) );
DFFRX1TS d_ff4_Yn_Q_reg_40_ ( .D(n2916), .CK(clk), .RN(n6965), .Q(
d_ff_Yn[40]) );
DFFRX1TS d_ff4_Yn_Q_reg_39_ ( .D(n2919), .CK(clk), .RN(n6967), .Q(
d_ff_Yn[39]) );
DFFRX1TS d_ff4_Yn_Q_reg_41_ ( .D(n2913), .CK(clk), .RN(n6966), .Q(
d_ff_Yn[41]) );
DFFRX1TS d_ff4_Yn_Q_reg_43_ ( .D(n2907), .CK(clk), .RN(n6969), .Q(
d_ff_Yn[43]) );
DFFRX1TS d_ff4_Yn_Q_reg_36_ ( .D(n2928), .CK(clk), .RN(n6968), .Q(
d_ff_Yn[36]) );
DFFRX1TS d_ff4_Yn_Q_reg_35_ ( .D(n2931), .CK(clk), .RN(n6970), .Q(
d_ff_Yn[35]) );
DFFRX1TS d_ff4_Yn_Q_reg_42_ ( .D(n2910), .CK(clk), .RN(n6969), .Q(
d_ff_Yn[42]) );
DFFRX1TS d_ff4_Yn_Q_reg_45_ ( .D(n2901), .CK(clk), .RN(n6972), .Q(
d_ff_Yn[45]) );
DFFRX1TS d_ff4_Yn_Q_reg_46_ ( .D(n2898), .CK(clk), .RN(n6971), .Q(
d_ff_Yn[46]) );
DFFRX1TS d_ff4_Yn_Q_reg_3_ ( .D(n3027), .CK(clk), .RN(n6973), .Q(d_ff_Yn[3])
);
DFFRX1TS d_ff4_Yn_Q_reg_34_ ( .D(n2934), .CK(clk), .RN(n6973), .Q(
d_ff_Yn[34]) );
DFFRX1TS d_ff4_Yn_Q_reg_33_ ( .D(n2937), .CK(clk), .RN(n7004), .Q(
d_ff_Yn[33]) );
DFFRX1TS d_ff4_Yn_Q_reg_44_ ( .D(n2904), .CK(clk), .RN(n6974), .Q(
d_ff_Yn[44]) );
DFFRX1TS d_ff4_Yn_Q_reg_49_ ( .D(n2889), .CK(clk), .RN(n6976), .Q(
d_ff_Yn[49]) );
DFFRX1TS d_ff4_Yn_Q_reg_48_ ( .D(n2892), .CK(clk), .RN(n6975), .Q(
d_ff_Yn[48]) );
DFFRX1TS d_ff4_Yn_Q_reg_50_ ( .D(n2886), .CK(clk), .RN(n7003), .Q(
d_ff_Yn[50]) );
DFFRX1TS d_ff4_Yn_Q_reg_47_ ( .D(n2895), .CK(clk), .RN(n6976), .Q(
d_ff_Yn[47]) );
DFFRX1TS d_ff4_Yn_Q_reg_54_ ( .D(n2498), .CK(clk), .RN(n6982), .Q(
d_ff_Yn[54]) );
DFFRX1TS d_ff4_Yn_Q_reg_59_ ( .D(n2483), .CK(clk), .RN(n6980), .Q(
d_ff_Yn[59]) );
DFFRX1TS d_ff4_Yn_Q_reg_58_ ( .D(n2486), .CK(clk), .RN(n6981), .Q(
d_ff_Yn[58]) );
DFFRX1TS d_ff4_Yn_Q_reg_52_ ( .D(n2504), .CK(clk), .RN(n6984), .Q(
d_ff_Yn[52]) );
DFFRX1TS d_ff4_Xn_Q_reg_53_ ( .D(n2500), .CK(clk), .RN(n6983), .Q(
d_ff_Xn[53]) );
DFFRX1TS d_ff4_Xn_Q_reg_55_ ( .D(n2494), .CK(clk), .RN(n3870), .Q(
d_ff_Xn[55]) );
DFFRX1TS d_ff4_Xn_Q_reg_56_ ( .D(n2491), .CK(clk), .RN(n7000), .Q(
d_ff_Xn[56]) );
DFFRX1TS d_ff4_Xn_Q_reg_57_ ( .D(n2488), .CK(clk), .RN(n6981), .Q(
d_ff_Xn[57]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_63_ ( .D(n2344), .CK(clk), .RN(n6955),
.Q(d_ff2_Y[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_48_ ( .D(n2606), .CK(clk), .RN(n6975),
.Q(d_ff2_Y[48]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_44_ ( .D(n2793), .CK(clk), .RN(n6974),
.Q(d_ff2_X[44]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n2741), .CK(clk), .RN(n6973), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_34_ ( .D(n2648), .CK(clk), .RN(n6973),
.Q(d_ff2_Y[34]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_45_ ( .D(n2615), .CK(clk), .RN(n6972),
.Q(d_ff2_Y[45]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_46_ ( .D(n2612), .CK(clk), .RN(n6971),
.Q(d_ff2_Y[46]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_43_ ( .D(n2621), .CK(clk), .RN(n6969),
.Q(d_ff2_Y[43]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_39_ ( .D(n2633), .CK(clk), .RN(n6967),
.Q(d_ff2_Y[39]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_41_ ( .D(n2627), .CK(clk), .RN(n6966),
.Q(d_ff2_Y[41]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n2666), .CK(clk), .RN(n6963),
.Q(d_ff2_Y[28]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n2657), .CK(clk), .RN(n6962),
.Q(d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n2705), .CK(clk), .RN(n6961),
.Q(d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n2660), .CK(clk), .RN(n6960),
.Q(d_ff2_Y[30]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n2699), .CK(clk), .RN(n6959),
.Q(d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_32_ ( .D(n2654), .CK(clk), .RN(n6958),
.Q(d_ff2_Y[32]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n2711), .CK(clk), .RN(n6956),
.Q(d_ff2_Y[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_63_ ( .D(n2755), .CK(clk), .RN(n6955),
.Q(d_ff2_X[63]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n2693), .CK(clk), .RN(n6954),
.Q(d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n2696), .CK(clk), .RN(n6953),
.Q(d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n2702), .CK(clk), .RN(n6952),
.Q(d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n2732), .CK(clk), .RN(n6951), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n2690), .CK(clk), .RN(n6949),
.Q(d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n2726), .CK(clk), .RN(n6948), .Q(
d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n2687), .CK(clk), .RN(n6947),
.Q(d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n2717), .CK(clk), .RN(n6945),
.Q(d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n2672), .CK(clk), .RN(n6944),
.Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n2681), .CK(clk), .RN(n6942),
.Q(d_ff2_Y[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n2675), .CK(clk), .RN(n6940),
.Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n2873), .CK(clk), .RN(n6939), .Q(
d_ff2_X[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n2744), .CK(clk), .RN(n6938), .Q(
d_ff2_Y[2]) );
DFFRX1TS d_ff4_Yn_Q_reg_63_ ( .D(n2751), .CK(clk), .RN(n6955), .Q(
d_ff_Yn[63]) );
DFFRX1TS d_ff4_Yn_Q_reg_53_ ( .D(n2501), .CK(clk), .RN(n6983), .Q(
d_ff_Yn[53]) );
DFFRX1TS d_ff4_Yn_Q_reg_55_ ( .D(n2495), .CK(clk), .RN(n6982), .Q(
d_ff_Yn[55]) );
DFFRX1TS d_ff4_Yn_Q_reg_57_ ( .D(n2489), .CK(clk), .RN(n6981), .Q(
d_ff_Yn[57]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n2348), .CK(clk), .RN(n6955), .Q(
d_ff3_sign_out) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(
n2745), .CK(clk), .RN(n6860), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .QN(n3279) );
DFFRX1TS d_ff4_Yn_Q_reg_7_ ( .D(n3015), .CK(clk), .RN(n7008), .Q(d_ff_Yn[7])
);
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n2330), .CK(clk), .RN(n7008), .Q(
data_output[10]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_56_ ( .D(n2362), .CK(clk), .RN(n7000),
.Q(d_ff2_Z[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(n2284), .CK(clk), .RN(n7000), .Q(
data_output[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(n2301), .CK(clk), .RN(n7010), .Q(
data_output[39]) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(n2303), .CK(clk), .RN(n7010), .Q(
data_output[37]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(
n3043), .CK(clk), .RN(n6927), .Q(
inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .QN(n6716) );
DFFRX1TS reg_LUT_Q_reg_7_ ( .D(n3118), .CK(clk), .RN(n6988), .Q(
d_ff3_LUT_out[7]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(
n1920), .CK(clk), .RN(n6897), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[25]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_57_ ( .D(n2186),
.CK(clk), .RN(n6865), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[57])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n2016),
.CK(clk), .RN(n6918), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1971),
.CK(clk), .RN(n6918), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1961),
.CK(clk), .RN(n6918), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1944),
.CK(clk), .RN(n6918), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1931),
.CK(clk), .RN(n6918), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1913),
.CK(clk), .RN(n6919), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1909),
.CK(clk), .RN(n6919), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1852),
.CK(clk), .RN(n6920), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1848),
.CK(clk), .RN(n6917), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1840),
.CK(clk), .RN(n6917), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1836),
.CK(clk), .RN(n6920), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1832),
.CK(clk), .RN(n6917), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1820),
.CK(clk), .RN(n6919), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1796),
.CK(clk), .RN(n6921), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[36]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1784),
.CK(clk), .RN(n6921), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[35]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1772),
.CK(clk), .RN(n6921), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[34]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1760),
.CK(clk), .RN(n6920), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[33]) );
DFFRX1TS reg_LUT_Q_reg_54_ ( .D(n3156), .CK(clk), .RN(n6989), .Q(
d_ff3_LUT_out[54]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(
n2176), .CK(clk), .RN(n6904), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[50]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_46_ ( .D(n2150),
.CK(clk), .RN(n6866), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[46])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_41_ ( .D(n2132),
.CK(clk), .RN(n6867), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[41])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_37_ ( .D(n2123),
.CK(clk), .RN(n6867), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[37])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n2105),
.CK(clk), .RN(n6868), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_29_ ( .D(n2096),
.CK(clk), .RN(n6868), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[29])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(n1921),
.CK(clk), .RN(n6873), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1860),
.CK(clk), .RN(n6876), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13])
);
DFFRX1TS reg_LUT_Q_reg_23_ ( .D(n3134), .CK(clk), .RN(n6989), .Q(
d_ff3_LUT_out[23]) );
DFFRX1TS reg_LUT_Q_reg_25_ ( .D(n3136), .CK(clk), .RN(n7010), .Q(
d_ff3_LUT_out[25]) );
DFFRX1TS reg_LUT_Q_reg_27_ ( .D(n3138), .CK(clk), .RN(n6987), .Q(
d_ff3_LUT_out[27]) );
DFFRX1TS reg_LUT_Q_reg_13_ ( .D(n3124), .CK(clk), .RN(n7001), .Q(
d_ff3_LUT_out[13]) );
DFFRX1TS reg_LUT_Q_reg_1_ ( .D(n3112), .CK(clk), .RN(n6986), .Q(
d_ff3_LUT_out[1]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
n2271), .CK(clk), .RN(n6908), .Q(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRX1TS reg_LUT_Q_reg_4_ ( .D(n3115), .CK(clk), .RN(n6989), .Q(
d_ff3_LUT_out[4]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_47_ ( .D(n2380), .CK(clk), .RN(n3870),
.Q(d_ff2_Z[47]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_30_ ( .D(n2536),
.CK(clk), .RN(n6882), .QN(n3196) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_33_ ( .D(n2539),
.CK(clk), .RN(n6882), .QN(n3195) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_39_ ( .D(n2545),
.CK(clk), .RN(n6899), .QN(n3194) );
DFFRX2TS ITER_CONT_temp_reg_3_ ( .D(n3161), .CK(clk), .RN(n6997), .Q(
cont_iter_out[3]), .QN(n3183) );
DFFSX2TS ITER_CONT_temp_reg_0_ ( .D(n3288), .CK(clk), .SN(n6997), .Q(n6673),
.QN(n3187) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_34_ ( .D(n2540),
.CK(clk), .RN(n6881), .QN(n3184) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n2050), .CK(clk), .RN(n6910), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30])
);
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n2047), .CK(clk), .RN(n6911), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33]),
.QN(n6756) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n2045), .CK(clk), .RN(n6911), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[35]),
.QN(n6826) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n2043), .CK(clk), .RN(n6911), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[37]),
.QN(n6827) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n2041), .CK(clk), .RN(n6911), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[39]),
.QN(n6701) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n2040), .CK(clk), .RN(n6911), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[40])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n2038), .CK(clk), .RN(n6911), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[42]),
.QN(n6640) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n2036), .CK(clk), .RN(n6913), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[44]),
.QN(n6641) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n2035), .CK(clk), .RN(n6913), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[45])
);
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(
n2024), .CK(clk), .RN(n6889), .Q(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n2064), .CK(clk), .RN(n6910), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]),
.QN(n6707) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n2058), .CK(clk), .RN(n6913), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]),
.QN(n6691) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(n2288), .CK(clk), .RN(n6983), .Q(
data_output[52]) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(n2287), .CK(clk), .RN(n6983), .Q(
data_output[53]) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(n2286), .CK(clk), .RN(n6982), .Q(
data_output[54]) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(n2285), .CK(clk), .RN(n7001), .Q(
data_output[55]) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(n2283), .CK(clk), .RN(n6981), .Q(
data_output[57]) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(n2282), .CK(clk), .RN(n6980), .Q(
data_output[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n2322), .CK(clk), .RN(n6953), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n2324), .CK(clk), .RN(n6952), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n2334), .CK(clk), .RN(n6950), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n2320), .CK(clk), .RN(n6948), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n2319), .CK(clk), .RN(n6947), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n2331), .CK(clk), .RN(n6946), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n2318), .CK(clk), .RN(n6944), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n2317), .CK(clk), .RN(n6942), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n2316), .CK(clk), .RN(n6941), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n2315), .CK(clk), .RN(n6940), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n2313), .CK(clk), .RN(n6940), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n2314), .CK(clk), .RN(n6940), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n2329), .CK(clk), .RN(n6939), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n2332), .CK(clk), .RN(n6939), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n2335), .CK(clk), .RN(n6939), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n2336), .CK(clk), .RN(n6938), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n2339), .CK(clk), .RN(n6937), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n2340), .CK(clk), .RN(n6936), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n2327), .CK(clk), .RN(n6935), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n2311), .CK(clk), .RN(n6935), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n2326), .CK(clk), .RN(n6935), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(n2308), .CK(clk), .RN(n6935), .Q(
data_output[32]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n2323), .CK(clk), .RN(n6935), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n2310), .CK(clk), .RN(n6935), .Q(
data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n2325), .CK(clk), .RN(n6935), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n2328), .CK(clk), .RN(n6935), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n2309), .CK(clk), .RN(n6935), .Q(
data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n2312), .CK(clk), .RN(n6935), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(n2299), .CK(clk), .RN(n7000), .Q(
data_output[41]) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(n2305), .CK(clk), .RN(n7012), .Q(
data_output[35]) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(n2294), .CK(clk), .RN(n7009), .Q(
data_output[46]) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(n2295), .CK(clk), .RN(n6934), .Q(
data_output[45]) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(n2306), .CK(clk), .RN(n6934), .Q(
data_output[34]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n2337), .CK(clk), .RN(n6934), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(n2296), .CK(clk), .RN(n6934), .Q(
data_output[44]) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(n2307), .CK(clk), .RN(n6934), .Q(
data_output[33]) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(n2292), .CK(clk), .RN(n6934), .Q(
data_output[48]) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(n2291), .CK(clk), .RN(n6934), .Q(
data_output[49]) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(n2290), .CK(clk), .RN(n6934), .Q(
data_output[50]) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(n2289), .CK(clk), .RN(n6934), .Q(
data_output[51]) );
DFFSX1TS d_ff5_data_out_Q_reg_19_ ( .D(n7013), .CK(clk), .SN(n6954), .QN(
data_output[19]) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1711), .CK(clk), .RN(n6894), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[27]),
.QN(n6674) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_52_ ( .D(n2594), .CK(clk), .RN(n6984),
.Q(d_ff2_Y[52]), .QN(n6686) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(
n2562), .CK(clk), .RN(n6849), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[62]), .QN(n6693) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1702), .CK(clk), .RN(n6887), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[36]),
.QN(n6770) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1703), .CK(clk), .RN(n6904), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[35]),
.QN(n6796) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1705), .CK(clk), .RN(n6930), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[33]),
.QN(n6797) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1706), .CK(clk), .RN(n6895), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[32]),
.QN(n6772) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1707), .CK(clk), .RN(n6887), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[31]),
.QN(n6798) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1708), .CK(clk), .RN(n6904), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[30]),
.QN(n6773) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1709), .CK(clk), .RN(n6894), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[29]),
.QN(n6799) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1710), .CK(clk), .RN(n6894), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[28]),
.QN(n6774) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1726), .CK(clk), .RN(n6893), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]),
.QN(n6782) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1697), .CK(clk), .RN(n6896), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[41]),
.QN(n6793) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1699), .CK(clk), .RN(n6928), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[39]),
.QN(n6794) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1716), .CK(clk), .RN(n6894), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]),
.QN(n6777) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1718), .CK(clk), .RN(n6894), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]),
.QN(n6778) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1725), .CK(clk), .RN(n6893), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]),
.QN(n6806) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1712), .CK(clk), .RN(n6894), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[26]),
.QN(n6775) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1713), .CK(clk), .RN(n6894), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]),
.QN(n6800) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1714), .CK(clk), .RN(n6894), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]),
.QN(n6776) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1715), .CK(clk), .RN(n6894), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]),
.QN(n6801) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1717), .CK(clk), .RN(n6894), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]),
.QN(n6802) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1719), .CK(clk), .RN(n6893), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]),
.QN(n6803) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1727), .CK(clk), .RN(n6893), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]),
.QN(n6807) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1700), .CK(clk), .RN(n6931), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[38]),
.QN(n6769) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(
n2604), .CK(clk), .RN(n6850), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[48]), .QN(n6597) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1728), .CK(clk), .RN(n6893), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]),
.QN(n6783) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n2055), .CK(clk), .RN(n6910), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]),
.QN(n6825) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ (
.D(n3173), .CK(clk), .RN(n6847), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(
n6671) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n2080),
.CK(clk), .RN(n6905), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n6758) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n6996), .Q(
inst_CORDIC_FSM_v3_state_reg[2]), .QN(n6698) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n6996), .Q(
inst_CORDIC_FSM_v3_state_reg[1]), .QN(n6692) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ (
.D(n3172), .CK(clk), .RN(n6847), .Q(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(
n6760) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(
n3042), .CK(clk), .RN(n6914), .Q(
inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2), .QN(n6635) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n2078),
.CK(clk), .RN(n6908), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .QN(n6654) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_58_ ( .D(n2588), .CK(clk), .RN(n6980),
.Q(d_ff2_Y[58]), .QN(n6723) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_58_ ( .D(n2771), .CK(clk), .RN(n6980),
.Q(d_ff2_X[58]), .QN(n6722) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(
n2471), .CK(clk), .RN(n6860), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .QN(n6658) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(
n2473), .CK(clk), .RN(n6860), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .QN(n6656) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(
n2397), .CK(clk), .RN(n6853), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[38]), .QN(n6680) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(
n2463), .CK(clk), .RN(n6857), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .QN(n6651) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(
n2461), .CK(clk), .RN(n6857), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .QN(n6678) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(
n2459), .CK(clk), .RN(n6856), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .QN(n6679) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n3108), .CK(clk), .RN(n6996), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n6669) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(
n2453), .CK(clk), .RN(n6856), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .QN(n6677) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(
n2425), .CK(clk), .RN(n6859), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .QN(n6644) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1704), .CK(clk), .RN(n6931), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[34]),
.QN(n6771) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1729),
.CK(clk), .RN(n6892), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n6808) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1693), .CK(clk), .RN(n6898), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[45]),
.QN(n6790) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1696), .CK(clk), .RN(n6896), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[42]),
.QN(n6767) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1720), .CK(clk), .RN(n6893), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]),
.QN(n6779) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1723), .CK(clk), .RN(n6893), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]),
.QN(n6805) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1724), .CK(clk), .RN(n6893), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]),
.QN(n6781) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(
n2361), .CK(clk), .RN(n6847), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[56]), .QN(n6650) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(
n2566), .CK(clk), .RN(n6849), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[60]), .QN(n6648) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(
n2570), .CK(clk), .RN(n6849), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[58]), .QN(n6647) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1695), .CK(clk), .RN(n6896), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[43]),
.QN(n6792) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n2075),
.CK(clk), .RN(n6908), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n6688) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(
n2393), .CK(clk), .RN(n6853), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[40]), .QN(n6682) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(
n2399), .CK(clk), .RN(n6853), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[37]), .QN(n6659) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(
n2379), .CK(clk), .RN(n6850), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[47]), .QN(n6681) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(
n2413), .CK(clk), .RN(n6854), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .QN(n6601) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(
n2371), .CK(clk), .RN(n6849), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[51]), .QN(n6632) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(
n2409), .CK(clk), .RN(n6855), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[32]), .QN(n6661) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(
n2377), .CK(clk), .RN(n6850), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[48]), .QN(n6660) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(
n2389), .CK(clk), .RN(n6852), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[42]), .QN(n6599) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(
n2405), .CK(clk), .RN(n6851), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[34]), .QN(n6600) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(
n2381), .CK(clk), .RN(n6851), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[46]), .QN(n6598) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(
n2417), .CK(clk), .RN(n6853), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .QN(n6603) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(
n2365), .CK(clk), .RN(n6847), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[54]), .QN(n6596) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n2073),
.CK(clk), .RN(n6909), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .QN(n6724) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1722), .CK(clk), .RN(n6893), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]),
.QN(n6780) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1701), .CK(clk), .RN(n6931), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[37]),
.QN(n6795) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1736),
.CK(clk), .RN(n6892), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n6812) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1691), .CK(clk), .RN(n6899), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[47]),
.QN(n6789) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1731),
.CK(clk), .RN(n6892), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n6809) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1686), .CK(clk), .RN(n6903), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[52]),
.QN(n6813) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1692), .CK(clk), .RN(n6898), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[46]),
.QN(n6816) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1694), .CK(clk), .RN(n6898), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[44]),
.QN(n6791) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1730),
.CK(clk), .RN(n6892), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n6784) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1735),
.CK(clk), .RN(n6892), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n6811) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1687), .CK(clk), .RN(n6926), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[51]),
.QN(n6787) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1732),
.CK(clk), .RN(n6892), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n6785) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1690), .CK(clk), .RN(n6900), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[48]),
.QN(n6815) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1685), .CK(clk), .RN(n6905), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[53]),
.QN(n6753) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1737),
.CK(clk), .RN(n6906), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n6639) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n2071),
.CK(clk), .RN(n6909), .Q(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n6676) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n2062), .CK(clk), .RN(n6910), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]),
.QN(n6653) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
n3039), .CK(clk), .RN(n6892), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n6697) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n2061), .CK(clk), .RN(n6913), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]),
.QN(n6819) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1734),
.CK(clk), .RN(n6892), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n6786) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1688), .CK(clk), .RN(n6901), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[50]),
.QN(n6814) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
n3041), .CK(clk), .RN(n6908), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n6683) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n2068), .CK(clk), .RN(n6909), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]),
.QN(n6665) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n2060), .CK(clk), .RN(n6910), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]),
.QN(n6690) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n2087), .CK(clk), .RN(n6883), .Q(result_add_subt[63]), .QN(n6818) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n2059), .CK(clk), .RN(n6913), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]),
.QN(n6821) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(
n3038), .CK(clk), .RN(n6895), .Q(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[5]), .QN(n6662) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n2063), .CK(clk), .RN(n6909), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]),
.QN(n6699) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n2056), .CK(clk), .RN(n6910), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]),
.QN(n6675) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n2049), .CK(clk), .RN(n6910), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[31]),
.QN(n6638) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n2529),
.CK(clk), .RN(n6896), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .QN(n6729) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(
n2643), .CK(clk), .RN(n6851), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(
n2694), .CK(clk), .RN(n6856), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(
n2682), .CK(clk), .RN(n6858), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(
n2613), .CK(clk), .RN(n6851), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(
n2658), .CK(clk), .RN(n6854), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .QN(n6749) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(
n2709), .CK(clk), .RN(n6855), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(
n2706), .CK(clk), .RN(n6855), .Q(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_29_ ( .D(n2535),
.CK(clk), .RN(n6882), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_28_ ( .D(n2534),
.CK(clk), .RN(n6881), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_46_ ( .D(n2552),
.CK(clk), .RN(n6899), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_40_ ( .D(n2546),
.CK(clk), .RN(n6901), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_43_ ( .D(n2549),
.CK(clk), .RN(n6899), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_41_ ( .D(n2547),
.CK(clk), .RN(n6900), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SHT2_SHIFT_DATA_Q_reg_50_ ( .D(n2556),
.CK(clk), .RN(n6931), .Q(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]) );
DFFRX4TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n2046), .CK(clk), .RN(n6911), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[34]),
.QN(n6705) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n2048), .CK(clk), .RN(n6911), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[32]),
.QN(n6700) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(
n2081), .CK(clk), .RN(n6889), .Q(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .QN(n3185) );
DFFRX1TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n2039), .CK(clk), .RN(n6911), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[41]),
.QN(n6655) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n2020),
.CK(clk), .RN(n6869), .Q(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1917),
.CK(clk), .RN(n6919), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1824),
.CK(clk), .RN(n6920), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_52_ ( .D(n2777), .CK(clk), .RN(n6983),
.Q(d_ff2_X[52]), .QN(n6687) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n2042), .CK(clk), .RN(n6911), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[38]),
.QN(n6721) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n2027), .CK(clk), .RN(n6912), .Q(n3176), .QN(n6844) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n2044), .CK(clk), .RN(n6912), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[36]),
.QN(n6715) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n2067), .CK(clk), .RN(n6909), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]),
.QN(n6762) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1767),
.CK(clk), .RN(n6914), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1847),
.CK(clk), .RN(n6916), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n2065), .CK(clk), .RN(n6909), .Q(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]),
.QN(n6689) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1889),
.CK(clk), .RN(n6914), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1953),
.CK(clk), .RN(n6915), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1875),
.CK(clk), .RN(n6914), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]) );
DFFRX2TS inst_FPU_PIPELINED_FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1733),
.CK(clk), .RN(n6892), .Q(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n6810) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n6990), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n6990), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
CMPR32X2TS intadd_44_U4 ( .A(n6709), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[53]), .C(intadd_44_CI), .CO(
intadd_44_n3), .S(intadd_44_SUM_0_) );
CMPR32X2TS intadd_45_U4 ( .A(d_ff2_Y[53]), .B(n6670), .C(intadd_45_CI), .CO(
intadd_45_n3), .S(intadd_45_SUM_0_) );
CMPR32X2TS intadd_46_U4 ( .A(d_ff2_X[53]), .B(n6670), .C(intadd_46_CI), .CO(
intadd_46_n3), .S(intadd_46_SUM_0_) );
CMPR32X2TS intadd_45_U3 ( .A(d_ff2_Y[54]), .B(n3297), .C(intadd_45_n3), .CO(
intadd_45_n2), .S(intadd_45_SUM_1_) );
CMPR32X2TS intadd_44_U3 ( .A(n6719), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[54]), .C(intadd_44_n3), .CO(
intadd_44_n2), .S(intadd_44_SUM_1_) );
CMPR32X2TS intadd_44_U2 ( .A(n6718), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[55]), .C(intadd_44_n2), .CO(
intadd_44_n1), .S(intadd_44_SUM_2_) );
CMPR32X2TS intadd_46_U2 ( .A(d_ff2_X[55]), .B(n3212), .C(intadd_46_n2), .CO(
intadd_46_n1), .S(intadd_46_SUM_2_) );
CMPR32X2TS intadd_45_U2 ( .A(d_ff2_Y[55]), .B(n3212), .C(intadd_45_n2), .CO(
intadd_45_n1), .S(intadd_45_SUM_2_) );
DFFRX2TS d_ff4_Yn_Q_reg_62_ ( .D(n2346), .CK(clk), .RN(n6978), .Q(
d_ff_Yn[62]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_62_ ( .D(n2767), .CK(clk), .RN(n6977),
.Q(d_ff2_X[62]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1995),
.CK(clk), .RN(n6916), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1954),
.CK(clk), .RN(n6916), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1905),
.CK(clk), .RN(n6916), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1856),
.CK(clk), .RN(n6916), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1828),
.CK(clk), .RN(n6916), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1883),
.CK(clk), .RN(n6914), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1869),
.CK(clk), .RN(n6914), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1981),
.CK(clk), .RN(n6915), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1897),
.CK(clk), .RN(n6915), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5])
);
DFFRXLTS inst_FPU_PIPELINED_FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1890),
.CK(clk), .RN(n6915), .Q(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4])
);
AO21X1TS U3188 ( .A0(n5216), .A1(n5299), .B0(n3828), .Y(n2506) );
OAI222X1TS U3189 ( .A0(n5397), .A1(n5426), .B0(n5420), .B1(n5424), .C0(n6795), .C1(n5433), .Y(n1701) );
BUFX3TS U3190 ( .A(n5164), .Y(n5172) );
AOI222X1TS U3191 ( .A0(n6013), .A1(n5047), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]), .B1(n4183),
.C0(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .C1(n5305),
.Y(n4023) );
AOI222X1TS U3192 ( .A0(n6012), .A1(n5047), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[5]), .B1(n4183),
.C0(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[5]), .C1(n5323),
.Y(n4185) );
AOI222X1TS U3193 ( .A0(n6014), .A1(n4184), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]), .B1(n4183),
.C0(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .C1(n5323),
.Y(n4121) );
AOI211X1TS U3194 ( .A0(n5374), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]), .B0(n5373), .C0(n5372),
.Y(n5378) );
AOI222X1TS U3195 ( .A0(n4095), .A1(d_ff2_Z[60]), .B0(n4084), .B1(d_ff1_Z[60]), .C0(d_ff_Zn[60]), .C1(n4098), .Y(n4094) );
AOI222X1TS U3196 ( .A0(n4095), .A1(d_ff2_Z[35]), .B0(n4066), .B1(d_ff1_Z[35]), .C0(d_ff_Zn[35]), .C1(n4087), .Y(n4067) );
AOI222X1TS U3197 ( .A0(n4099), .A1(d_ff2_Z[49]), .B0(n4066), .B1(d_ff1_Z[49]), .C0(d_ff_Zn[49]), .C1(n4098), .Y(n4097) );
AOI222X1TS U3198 ( .A0(n4099), .A1(d_ff2_Z[50]), .B0(n4041), .B1(d_ff1_Z[50]), .C0(d_ff_Zn[50]), .C1(n4087), .Y(n4074) );
AOI222X1TS U3199 ( .A0(n4095), .A1(d_ff2_Z[61]), .B0(n4066), .B1(d_ff1_Z[61]), .C0(d_ff_Zn[61]), .C1(n4098), .Y(n4092) );
AOI222X1TS U3200 ( .A0(n4095), .A1(d_ff2_Z[57]), .B0(n4066), .B1(d_ff1_Z[57]), .C0(d_ff_Zn[57]), .C1(n4098), .Y(n4090) );
AOI222X1TS U3201 ( .A0(n4099), .A1(d_ff2_Z[53]), .B0(n4041), .B1(d_ff1_Z[53]), .C0(d_ff_Zn[53]), .C1(n4087), .Y(n4088) );
AOI222X1TS U3202 ( .A0(n4099), .A1(d_ff2_Z[52]), .B0(n4041), .B1(d_ff1_Z[52]), .C0(d_ff_Zn[52]), .C1(n4087), .Y(n4073) );
AOI222X1TS U3203 ( .A0(n4095), .A1(d_ff2_Z[58]), .B0(n4066), .B1(d_ff1_Z[58]), .C0(d_ff_Zn[58]), .C1(n4098), .Y(n4096) );
AOI222X1TS U3204 ( .A0(n4099), .A1(d_ff2_Z[48]), .B0(n4041), .B1(d_ff1_Z[48]), .C0(d_ff_Zn[48]), .C1(n4087), .Y(n4076) );
AOI222X1TS U3205 ( .A0(n6151), .A1(d_ff2_Z[0]), .B0(n4098), .B1(d_ff_Zn[0]),
.C0(n4041), .C1(d_ff1_Z[0]), .Y(n4042) );
AOI222X1TS U3206 ( .A0(n6293), .A1(d_ff2_Z[4]), .B0(n4037), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n6292), .Y(n4033) );
AOI222X1TS U3207 ( .A0(n4099), .A1(d_ff2_Z[51]), .B0(n4069), .B1(d_ff1_Z[51]), .C0(d_ff_Zn[51]), .C1(n4087), .Y(n4065) );
AOI222X1TS U3208 ( .A0(n6151), .A1(d_ff2_Z[55]), .B0(n4069), .B1(d_ff1_Z[55]), .C0(d_ff_Zn[55]), .C1(n4087), .Y(n4077) );
AOI222X1TS U3209 ( .A0(n4099), .A1(d_ff2_Z[54]), .B0(n4069), .B1(d_ff1_Z[54]), .C0(d_ff_Zn[54]), .C1(n4087), .Y(n4070) );
AOI222X1TS U3210 ( .A0(n4081), .A1(d_ff2_Z[46]), .B0(n4069), .B1(d_ff1_Z[46]), .C0(d_ff_Zn[46]), .C1(n4087), .Y(n4064) );
AOI222X1TS U3211 ( .A0(n4095), .A1(d_ff2_Z[62]), .B0(n4069), .B1(d_ff1_Z[62]), .C0(d_ff_Zn[62]), .C1(n4098), .Y(n4089) );
AOI222X1TS U3212 ( .A0(n4095), .A1(d_ff2_Z[59]), .B0(n4069), .B1(d_ff1_Z[59]), .C0(d_ff_Zn[59]), .C1(n4098), .Y(n4091) );
AOI222X1TS U3213 ( .A0(n6151), .A1(d_ff2_Z[1]), .B0(n4041), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n6292), .Y(n3995) );
AOI222X1TS U3214 ( .A0(n6151), .A1(d_ff2_Z[3]), .B0(n4041), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n6292), .Y(n3996) );
AOI222X1TS U3215 ( .A0(n6151), .A1(d_ff2_Z[2]), .B0(n4041), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n6292), .Y(n3994) );
INVX4TS U3216 ( .A(n5309), .Y(n3220) );
INVX2TS U3217 ( .A(n5119), .Y(n5303) );
BUFX4TS U3218 ( .A(n5350), .Y(n5278) );
BUFX3TS U3219 ( .A(n4906), .Y(n4877) );
BUFX3TS U3220 ( .A(n6456), .Y(n6256) );
BUFX3TS U3221 ( .A(n6197), .Y(n6376) );
BUFX3TS U3222 ( .A(n3876), .Y(n6456) );
BUFX3TS U3223 ( .A(n3903), .Y(n4043) );
INVX2TS U3224 ( .A(n5127), .Y(n5058) );
BUFX3TS U3225 ( .A(n6558), .Y(n6476) );
BUFX4TS U3226 ( .A(n4202), .Y(n4236) );
INVX2TS U3227 ( .A(n3216), .Y(n6473) );
INVX4TS U3228 ( .A(n3936), .Y(n3937) );
CLKBUFX2TS U3229 ( .A(n6143), .Y(n6144) );
INVX2TS U3230 ( .A(n3215), .Y(n3216) );
OR2X2TS U3231 ( .A(n6717), .B(n3219), .Y(n6558) );
OAI2BB2XLTS U3232 ( .B0(n3394), .B1(n3393), .A0N(n3392), .A1N(n3391), .Y(
n3455) );
INVX6TS U3233 ( .A(n6460), .Y(n6458) );
INVX2TS U3234 ( .A(n3218), .Y(n3219) );
CLKBUFX2TS U3235 ( .A(n3303), .Y(n3876) );
CMPR32X2TS U3236 ( .A(d_ff2_X[54]), .B(n3297), .C(intadd_46_n3), .CO(
intadd_46_n2), .S(intadd_46_SUM_1_) );
INVX2TS U3237 ( .A(n6846), .Y(n3218) );
OR3X2TS U3238 ( .A(inst_CORDIC_FSM_v3_state_reg[7]), .B(n3191), .C(n3875),
.Y(n3303) );
INVX2TS U3239 ( .A(n5446), .Y(n6580) );
BUFX3TS U3240 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(
n6846) );
OA21XLTS U3241 ( .A0(n3448), .A1(n3447), .B0(n3446), .Y(n3449) );
NAND2X1TS U3242 ( .A(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(
n6671), .Y(n6057) );
INVX2TS U3243 ( .A(n6673), .Y(n3217) );
OA21XLTS U3244 ( .A0(n4111), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]), .B0(n3769), .Y(
n3770) );
AND4X1TS U3245 ( .A(n3791), .B(n3790), .C(n3789), .D(n3788), .Y(n3792) );
NAND2X1TS U3246 ( .A(n4170), .B(n3775), .Y(n3779) );
NOR3BX2TS U3247 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(n3900), .Y(n6053) );
CLKXOR2X2TS U3248 ( .A(n4412), .B(n4411), .Y(n6040) );
NOR2X1TS U3249 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[8]), .B(
n3182), .Y(n4421) );
NAND3X1TS U3250 ( .A(n3413), .B(n3422), .C(n3307), .Y(n3453) );
NAND4X1TS U3251 ( .A(n3403), .B(n3401), .C(n3309), .D(n3308), .Y(n3443) );
NAND2X1TS U3252 ( .A(n3301), .B(n4404), .Y(n4406) );
NOR2X1TS U3253 ( .A(n5489), .B(n5483), .Y(n3592) );
OAI21X1TS U3254 ( .A0(n5488), .A1(n5483), .B0(n5484), .Y(n3591) );
NAND2X2TS U3255 ( .A(n3785), .B(n3733), .Y(n3795) );
AOI21X1TS U3256 ( .A0(n4138), .A1(n3543), .B0(n3542), .Y(n3684) );
NOR2BX1TS U3257 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[39]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .Y(n3439) );
NOR2X1TS U3258 ( .A(n4392), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]), .Y(n4408) );
NOR2X1TS U3259 ( .A(n5629), .B(n3521), .Y(n3523) );
NOR2X1TS U3260 ( .A(n3600), .B(n3578), .Y(n3580) );
NOR2XLTS U3261 ( .A(n3881), .B(n3491), .Y(n3493) );
OAI21X1TS U3262 ( .A0(n5895), .A1(n3477), .B0(n3476), .Y(n3879) );
NOR2X1TS U3263 ( .A(n5773), .B(n3833), .Y(n3568) );
NOR2X1TS U3264 ( .A(n5900), .B(n5881), .Y(n3556) );
NOR2X1TS U3265 ( .A(n5771), .B(n3497), .Y(n3499) );
NOR2X1TS U3266 ( .A(n5732), .B(n5704), .Y(n3574) );
NOR2X1TS U3267 ( .A(n5998), .B(n5992), .Y(n5710) );
NOR2X1TS U3268 ( .A(n5844), .B(n5855), .Y(n3560) );
OAI21X1TS U3269 ( .A0(n5462), .A1(n5788), .B0(n5463), .Y(n3837) );
INVX2TS U3270 ( .A(n4404), .Y(n4399) );
XOR2X1TS U3271 ( .A(n4383), .B(n3182), .Y(n4407) );
NOR2X1TS U3272 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[47]), .B(
n3237), .Y(n3712) );
INVX2TS U3273 ( .A(n3236), .Y(n3237) );
NOR2X1TS U3274 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[41]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33]), .Y(n3716) );
NOR2XLTS U3275 ( .A(n3349), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]),
.Y(n3350) );
OAI21XLTS U3276 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .A1(n6622), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .Y(n3356) );
NOR2X1TS U3277 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[50]), .Y(n3711) );
NOR2XLTS U3278 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[26]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30]), .Y(n3722) );
NOR2XLTS U3279 ( .A(n3368), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]),
.Y(n3369) );
NAND2X1TS U3280 ( .A(n3882), .B(n3489), .Y(n3491) );
NOR2X1TS U3281 ( .A(n5731), .B(n3511), .Y(n3513) );
OAI21XLTS U3282 ( .A0(n3529), .A1(n5559), .B0(n3528), .Y(n3530) );
OAI21X1TS U3283 ( .A0(n5992), .A1(n5997), .B0(n5993), .Y(n5709) );
NOR2XLTS U3284 ( .A(n5058), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .Y(n5059) );
NOR2XLTS U3285 ( .A(n4712), .B(n4461), .Y(n4713) );
NOR2XLTS U3286 ( .A(n4637), .B(n4636), .Y(n4645) );
NOR2XLTS U3287 ( .A(n4556), .B(n4555), .Y(n4558) );
NOR2XLTS U3288 ( .A(n4782), .B(n4461), .Y(n4783) );
OA21XLTS U3289 ( .A0(n3803), .A1(n3802), .B0(n3801), .Y(n3981) );
AOI21X2TS U3290 ( .A0(n3636), .A1(n3635), .B0(n3634), .Y(n5549) );
INVX2TS U3291 ( .A(n3981), .Y(n3982) );
NAND2X2TS U3292 ( .A(n6015), .B(n5184), .Y(n4945) );
NOR2XLTS U3293 ( .A(n3781), .B(n3746), .Y(n3747) );
NOR2XLTS U3294 ( .A(n5058), .B(n6733), .Y(n5054) );
NOR2XLTS U3295 ( .A(n4786), .B(n4785), .Y(n4789) );
INVX4TS U3296 ( .A(n5301), .Y(n5263) );
CLKINVX3TS U3297 ( .A(n4906), .Y(n4343) );
AND2X4TS U3298 ( .A(n4958), .B(n5013), .Y(n5309) );
NAND2X1TS U3299 ( .A(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B(
n6057), .Y(n5358) );
BUFX4TS U3300 ( .A(n3710), .Y(n6143) );
CLKXOR2X2TS U3301 ( .A(n4406), .B(n4405), .Y(n6038) );
BUFX3TS U3302 ( .A(n6143), .Y(n6239) );
NOR2X4TS U3303 ( .A(n6069), .B(n6293), .Y(n3936) );
NAND2X1TS U3304 ( .A(n5353), .B(n6052), .Y(n6119) );
OAI211XLTS U3305 ( .A0(n5330), .A1(n5350), .B0(n5329), .C0(n5328), .Y(n2556)
);
OAI211XLTS U3306 ( .A0(n5291), .A1(n5332), .B0(n5219), .C0(n5218), .Y(n2529)
);
OAI21XLTS U3307 ( .A0(n4539), .A1(n5397), .B0(n3955), .Y(n1737) );
OAI211XLTS U3308 ( .A0(n4199), .A1(n6647), .B0(n4193), .C0(n4197), .Y(n2570)
);
OAI211XLTS U3309 ( .A0(n4199), .A1(n6597), .B0(n4196), .C0(n4197), .Y(n2604)
);
OAI211XLTS U3310 ( .A0(n5254), .A1(n5164), .B0(n5046), .C0(n5045), .Y(n2540)
);
OAI21XLTS U3311 ( .A0(n6614), .A1(n4895), .B0(n4867), .Y(n1860) );
OAI21XLTS U3312 ( .A0(n6650), .A1(n4921), .B0(n4889), .Y(n2187) );
OAI211XLTS U3313 ( .A0(n5291), .A1(n5304), .B0(n5290), .C0(n5289), .Y(n2509)
);
OAI21XLTS U3314 ( .A0(n6620), .A1(n4910), .B0(n4886), .Y(n2020) );
NOR3X1TS U3315 ( .A(inst_CORDIC_FSM_v3_state_reg[0]), .B(n6698), .C(n3964),
.Y(n3710) );
OAI211XLTS U3316 ( .A0(n5224), .A1(n5350), .B0(n5223), .C0(n5222), .Y(n2513)
);
OAI21XLTS U3317 ( .A0(n5301), .A1(n5277), .B0(n4948), .Y(n2560) );
OAI211XLTS U3318 ( .A0(n5291), .A1(n5229), .B0(n5228), .C0(n5227), .Y(n2555)
);
OAI211XLTS U3319 ( .A0(n5340), .A1(n5339), .B0(n5338), .C0(n5337), .Y(n2528)
);
OAI211XLTS U3320 ( .A0(n4163), .A1(n6739), .B0(n4148), .C0(n4156), .Y(n2619)
);
OAI211XLTS U3321 ( .A0(n4153), .A1(n6743), .B0(n4152), .C0(n4161), .Y(n2664)
);
OAI211XLTS U3322 ( .A0(n4153), .A1(n6613), .B0(n4047), .C0(n4146), .Y(n2736)
);
OAI211XLTS U3323 ( .A0(n5279), .A1(n5301), .B0(n4980), .C0(n4979), .Y(n2524)
);
OAI21XLTS U3324 ( .A0(n6694), .A1(n4284), .B0(n4283), .Y(n1766) );
OAI21XLTS U3325 ( .A0(n6629), .A1(n4284), .B0(n4281), .Y(n1786) );
OAI21XLTS U3326 ( .A0(n6661), .A1(n4366), .B0(n4301), .Y(n1846) );
OAI21XLTS U3327 ( .A0(n6656), .A1(n4366), .B0(n4334), .Y(n1871) );
OAI21XLTS U3328 ( .A0(n6644), .A1(n4895), .B0(n4894), .Y(n1928) );
OAI21XLTS U3329 ( .A0(n6609), .A1(n4914), .B0(n4900), .Y(n1975) );
OAI21XLTS U3330 ( .A0(n6679), .A1(n4914), .B0(n4878), .Y(n1992) );
OAI21XLTS U3331 ( .A0(n6621), .A1(n4910), .B0(n4892), .Y(n2013) );
OAI21XLTS U3332 ( .A0(n6610), .A1(n4910), .B0(n4864), .Y(n2099) );
OAI21XLTS U3333 ( .A0(n6693), .A1(n4921), .B0(n4870), .Y(n2247) );
OAI211X1TS U3334 ( .A0(n5270), .A1(n5164), .B0(n5071), .C0(n5070), .Y(n2516)
);
OAI211X1TS U3335 ( .A0(n5143), .A1(n5164), .B0(n5142), .C0(n5141), .Y(n2550)
);
OAI211X1TS U3336 ( .A0(n5181), .A1(n5068), .B0(n5062), .C0(n5061), .Y(n2515)
);
OAI21X1TS U3337 ( .A0(n5381), .A1(n4927), .B0(n4930), .Y(n2178) );
OAI21X1TS U3338 ( .A0(n3993), .A1(n5057), .B0(n3992), .Y(n3040) );
OAI21X1TS U3339 ( .A0(n6602), .A1(n4366), .B0(n3461), .Y(n1854) );
BUFX4TS U3340 ( .A(n4872), .Y(n4536) );
INVX4TS U3341 ( .A(n4877), .Y(n4374) );
INVX4TS U3342 ( .A(n4877), .Y(n4361) );
INVX4TS U3343 ( .A(n4877), .Y(n4371) );
INVX4TS U3344 ( .A(n4877), .Y(n4364) );
INVX4TS U3345 ( .A(n4877), .Y(n4348) );
OAI21X1TS U3346 ( .A0(n5643), .A1(n5637), .B0(n5638), .Y(n3609) );
INVX4TS U3347 ( .A(n3458), .Y(n4953) );
OAI21X1TS U3348 ( .A0(n4199), .A1(n6693), .B0(n4040), .Y(n2562) );
OAI211X1TS U3349 ( .A0(n4199), .A1(n6623), .B0(n4194), .C0(n4197), .Y(n2564)
);
INVX4TS U3350 ( .A(n4906), .Y(n4282) );
AOI2BB2X1TS U3351 ( .B0(n4018), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .A0N(n3799), .A1N(
n3798), .Y(n3800) );
BUFX3TS U3352 ( .A(n6149), .Y(n6194) );
NAND2X4TS U3353 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .B(
n6556), .Y(n3458) );
INVX2TS U3354 ( .A(n6149), .Y(n4083) );
INVX4TS U3355 ( .A(n6149), .Y(n4098) );
INVX2TS U3356 ( .A(n6149), .Y(n4079) );
INVX1TS U3357 ( .A(n3781), .Y(n3791) );
INVX2TS U3358 ( .A(n6149), .Y(n4034) );
INVX2TS U3359 ( .A(n6149), .Y(n4036) );
INVX4TS U3360 ( .A(n6149), .Y(n4087) );
AND3X2TS U3361 ( .A(n6041), .B(n4413), .C(n6040), .Y(n4420) );
NOR2X6TS U3362 ( .A(n4011), .B(n3724), .Y(n3743) );
BUFX4TS U3363 ( .A(n3901), .Y(n6250) );
NAND2X2TS U3364 ( .A(n4201), .B(n4200), .Y(n6472) );
NOR2X4TS U3365 ( .A(n4011), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30]), .Y(n3785) );
OAI21X1TS U3366 ( .A0(n3453), .A1(n3452), .B0(n3451), .Y(n3454) );
NAND2X6TS U3367 ( .A(n3734), .B(n6638), .Y(n4011) );
OAI2BB1X2TS U3368 ( .A0N(n3363), .A1N(n3362), .B0(n3361), .Y(n3366) );
NOR2X2TS U3369 ( .A(n3450), .B(n3449), .Y(n3451) );
NAND3X1TS U3370 ( .A(cont_iter_out[1]), .B(n3217), .C(n6070), .Y(n3959) );
INVX3TS U3371 ( .A(n6239), .Y(n4095) );
OAI211X1TS U3372 ( .A0(n5365), .A1(n4686), .B0(n4685), .C0(n4684), .Y(n4687)
);
NOR2X6TS U3373 ( .A(n3736), .B(n3720), .Y(n3734) );
INVX3TS U3374 ( .A(n6239), .Y(n4085) );
INVX3TS U3375 ( .A(n6239), .Y(n4099) );
INVX3TS U3376 ( .A(n6239), .Y(n4081) );
NOR2X1TS U3377 ( .A(n4648), .B(n4647), .Y(n4649) );
NOR2X1TS U3378 ( .A(n4551), .B(n4550), .Y(n4559) );
NOR2X1TS U3379 ( .A(n4640), .B(n4639), .Y(n4644) );
NOR2X1TS U3380 ( .A(n4752), .B(n4751), .Y(n4760) );
NOR2X1TS U3381 ( .A(n4757), .B(n4756), .Y(n4759) );
NOR2X1TS U3382 ( .A(n4597), .B(n4596), .Y(n4605) );
NOR2X1TS U3383 ( .A(n4595), .B(n4594), .Y(n4606) );
INVX3TS U3384 ( .A(n3181), .Y(n5305) );
INVX3TS U3385 ( .A(n3181), .Y(n5323) );
INVX3TS U3386 ( .A(n3181), .Y(n5341) );
AOI21X2TS U3387 ( .A0(n3879), .A1(n3493), .B0(n3492), .Y(n3667) );
NOR2X1TS U3388 ( .A(n4686), .B(n4647), .Y(n4520) );
INVX4TS U3389 ( .A(n5354), .Y(n5375) );
CLKBUFX2TS U3390 ( .A(n5371), .Y(n3213) );
INVX2TS U3391 ( .A(n4430), .Y(n4417) );
INVX2TS U3392 ( .A(n4845), .Y(n5371) );
INVX4TS U3393 ( .A(n3303), .Y(n6102) );
NAND3X2TS U3394 ( .A(n3945), .B(n3944), .C(n4661), .Y(n4777) );
NOR2X1TS U3395 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54]), .B(
n3237), .Y(n3782) );
XOR2X1TS U3396 ( .A(n3182), .B(n4381), .Y(n4384) );
INVX3TS U3397 ( .A(n5053), .Y(n5137) );
INVX3TS U3398 ( .A(n5053), .Y(n5099) );
NOR2X1TS U3399 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[50]), .B(
n3256), .Y(n3761) );
INVX3TS U3400 ( .A(n4458), .Y(n4719) );
OAI21X1TS U3401 ( .A0(n5704), .A1(n5733), .B0(n5705), .Y(n3573) );
NAND3X1TS U3402 ( .A(n6627), .B(n3427), .C(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[36]), .Y(n3428) );
NOR3X1TS U3403 ( .A(n6764), .B(n3439), .C(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[38]), .Y(n3442) );
INVX3TS U3404 ( .A(n4458), .Y(n4598) );
INVX4TS U3405 ( .A(n4647), .Y(n4836) );
INVX3TS U3406 ( .A(n4785), .Y(n5985) );
CLKBUFX2TS U3407 ( .A(cont_iter_out[2]), .Y(n3463) );
NAND2BXLTS U3408 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .Y(n3321) );
NAND2BX1TS U3409 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .Y(n3312) );
OAI21X1TS U3410 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .A1(n6634), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .Y(n3421) );
OAI211X1TS U3411 ( .A0(n5201), .A1(n5291), .B0(n5200), .C0(n5199), .Y(n2548)
);
OAI21X1TS U3412 ( .A0(n3192), .A1(n5020), .B0(n4966), .Y(n2531) );
OAI211X1TS U3413 ( .A0(n5172), .A1(n5105), .B0(n5104), .C0(n5103), .Y(n2535)
);
OAI211X1TS U3414 ( .A0(n5172), .A1(n5091), .B0(n5090), .C0(n5089), .Y(n2537)
);
OAI211X1TS U3415 ( .A0(n5165), .A1(n5164), .B0(n5163), .C0(n5162), .Y(n2534)
);
OAI211X1TS U3416 ( .A0(n5109), .A1(n5164), .B0(n5108), .C0(n5107), .Y(n2536)
);
OAI211X1TS U3417 ( .A0(n5279), .A1(n5172), .B0(n5168), .C0(n5167), .Y(n2522)
);
OAI211X1TS U3418 ( .A0(n5172), .A1(n5115), .B0(n5114), .C0(n5113), .Y(n2539)
);
OAI211X1TS U3419 ( .A0(n5182), .A1(n5181), .B0(n5132), .C0(n5131), .Y(n2552)
);
OAI211X1TS U3420 ( .A0(n5094), .A1(n5164), .B0(n5093), .C0(n5092), .Y(n2538)
);
OAI211X1TS U3421 ( .A0(n5351), .A1(n5350), .B0(n5349), .C0(n5348), .Y(n2543)
);
OAI211X1TS U3422 ( .A0(n5278), .A1(n5246), .B0(n5245), .C0(n5244), .Y(n2512)
);
OAI211X1TS U3423 ( .A0(n5172), .A1(n5160), .B0(n5159), .C0(n5158), .Y(n2549)
);
OAI211X1TS U3424 ( .A0(n5172), .A1(n5332), .B0(n5171), .C0(n5170), .Y(n2527)
);
OAI211X1TS U3425 ( .A0(n5298), .A1(n5350), .B0(n5297), .C0(n5296), .Y(n2523)
);
OAI211X1TS U3426 ( .A0(n5234), .A1(n5350), .B0(n5233), .C0(n5232), .Y(n2547)
);
OAI211X1TS U3427 ( .A0(n5278), .A1(n5239), .B0(n5238), .C0(n5237), .Y(n2546)
);
OAI211X1TS U3428 ( .A0(n5278), .A1(n5277), .B0(n5276), .C0(n5275), .Y(n2557)
);
OAI211X1TS U3429 ( .A0(n5266), .A1(n5350), .B0(n5265), .C0(n5264), .Y(n2525)
);
OAI211X1TS U3430 ( .A0(n5351), .A1(n3221), .B0(n5214), .C0(n5213), .Y(n2545)
);
OAI211X1TS U3431 ( .A0(n5321), .A1(n5020), .B0(n5019), .C0(n5018), .Y(n2530)
);
OAI211X1TS U3432 ( .A0(n3221), .A1(n5304), .B0(n5248), .C0(n5247), .Y(n2508)
);
OAI211X1TS U3433 ( .A0(n3192), .A1(n5320), .B0(n5313), .C0(n5312), .Y(n2533)
);
OAI211X1TS U3434 ( .A0(n5254), .A1(n3221), .B0(n5253), .C0(n5252), .Y(n2541)
);
OAI211X1TS U3435 ( .A0(n5278), .A1(n5259), .B0(n5258), .C0(n5257), .Y(n2544)
);
OAI211X1TS U3436 ( .A0(n5172), .A1(n5277), .B0(n5067), .C0(n5066), .Y(n2558)
);
OAI211X1TS U3437 ( .A0(n5321), .A1(n5320), .B0(n5319), .C0(n5318), .Y(n2532)
);
OAI211X1TS U3438 ( .A0(n5278), .A1(n5332), .B0(n5079), .C0(n5078), .Y(n2526)
);
OAI211X1TS U3439 ( .A0(n5220), .A1(n5301), .B0(n5194), .C0(n5193), .Y(n2514)
);
OAI211X1TS U3440 ( .A0(n5288), .A1(n3220), .B0(n5052), .C0(n5051), .Y(n2511)
);
OAI21X1TS U3441 ( .A0(n3220), .A1(n5277), .B0(n5012), .Y(n2559) );
OAI211X1TS U3442 ( .A0(n5172), .A1(n5069), .B0(n5032), .C0(n5031), .Y(n2517)
);
OAI211X1TS U3443 ( .A0(n5254), .A1(n5301), .B0(n5180), .C0(n5179), .Y(n2542)
);
OAI211X1TS U3444 ( .A0(n5267), .A1(n3221), .B0(n5025), .C0(n5024), .Y(n2519)
);
OAI211X1TS U3445 ( .A0(n5172), .A1(n5146), .B0(n5145), .C0(n5144), .Y(n2551)
);
OAI211X1TS U3446 ( .A0(n5267), .A1(n5301), .B0(n5008), .C0(n5007), .Y(n2520)
);
OAI211X1TS U3447 ( .A0(n5172), .A1(n5229), .B0(n5153), .C0(n5152), .Y(n2553)
);
INVX12TS U3448 ( .A(n3221), .Y(n5336) );
INVX12TS U3449 ( .A(n5309), .Y(n3221) );
OAI211X1TS U3450 ( .A0(n5278), .A1(n5304), .B0(n5300), .C0(n3827), .Y(n3828)
);
BUFX8TS U3451 ( .A(n5291), .Y(n5301) );
OAI21X1TS U3452 ( .A0(n5409), .A1(n4863), .B0(n4571), .Y(n2007) );
OAI21X1TS U3453 ( .A0(n5431), .A1(n4941), .B0(n4940), .Y(n2172) );
OAI21X1TS U3454 ( .A0(n5424), .A1(n4858), .B0(n4791), .Y(n2148) );
OAI21X1TS U3455 ( .A0(n5407), .A1(n4824), .B0(n4816), .Y(n1949) );
OAI21X1TS U3456 ( .A0(n5410), .A1(n4858), .B0(n4827), .Y(n2109) );
OAI21X1TS U3457 ( .A0(n5408), .A1(n4858), .B0(n4831), .Y(n2157) );
OAI21X1TS U3458 ( .A0(n5402), .A1(n4858), .B0(n4821), .Y(n2136) );
OAI21X1TS U3459 ( .A0(n5386), .A1(n4941), .B0(n4800), .Y(n2142) );
OAI21X1TS U3460 ( .A0(n5406), .A1(n4824), .B0(n4811), .Y(n2121) );
OAI21X1TS U3461 ( .A0(n5393), .A1(n4863), .B0(n4561), .Y(n2000) );
OAI21X1TS U3462 ( .A0(n5414), .A1(n4824), .B0(n4701), .Y(n1939) );
OAI21X1TS U3463 ( .A0(n5439), .A1(n4853), .B0(n4692), .Y(n1888) );
OAI21X1TS U3464 ( .A0(n5442), .A1(n4941), .B0(n4924), .Y(n2175) );
OAI21X1TS U3465 ( .A0(n5444), .A1(n4853), .B0(n4772), .Y(n2160) );
OAI21X1TS U3466 ( .A0(n5437), .A1(n4853), .B0(n4852), .Y(n1895) );
OAI21X1TS U3467 ( .A0(n5429), .A1(n4863), .B0(n4715), .Y(n2100) );
OAI21X1TS U3468 ( .A0(n5426), .A1(n4863), .B0(n4862), .Y(n2112) );
OAI21X1TS U3469 ( .A0(n5417), .A1(n4824), .B0(n4660), .Y(n1966) );
OAI21X1TS U3470 ( .A0(n5413), .A1(n4863), .B0(n4618), .Y(n2106) );
OAI21X1TS U3471 ( .A0(n5419), .A1(n4858), .B0(n4737), .Y(n2118) );
OAI21X1TS U3472 ( .A0(n5404), .A1(n4824), .B0(n4794), .Y(n1942) );
OAI21X1TS U3473 ( .A0(n5405), .A1(n4824), .B0(n4746), .Y(n1929) );
OAI21X1TS U3474 ( .A0(n4539), .A1(n4853), .B0(n4538), .Y(n2181) );
OAI21X1TS U3475 ( .A0(n5391), .A1(n4863), .B0(n4586), .Y(n1959) );
OAI21X1TS U3476 ( .A0(n5416), .A1(n4824), .B0(n4548), .Y(n2097) );
OAI21X1TS U3477 ( .A0(n5403), .A1(n4863), .B0(n4762), .Y(n1952) );
OAI21X1TS U3478 ( .A0(n5398), .A1(n4858), .B0(n4814), .Y(n2124) );
OAI21X1TS U3479 ( .A0(n5421), .A1(n4824), .B0(n4823), .Y(n2021) );
OAI21X1TS U3480 ( .A0(n5390), .A1(n4941), .B0(n4797), .Y(n2133) );
OAI21X1TS U3481 ( .A0(n5438), .A1(n4941), .B0(n4936), .Y(n2169) );
OAI21X1TS U3482 ( .A0(n5411), .A1(n4824), .B0(n4678), .Y(n1976) );
OAI21X1TS U3483 ( .A0(n5400), .A1(n4858), .B0(n4835), .Y(n2130) );
OAI21X1TS U3484 ( .A0(n5387), .A1(n4853), .B0(n4607), .Y(n1993) );
OAI21X1TS U3485 ( .A0(n5383), .A1(n4941), .B0(n4680), .Y(n2163) );
OAI21X1TS U3486 ( .A0(n5395), .A1(n4858), .B0(n4633), .Y(n2103) );
OAI21X1TS U3487 ( .A0(n5396), .A1(n4863), .B0(n4630), .Y(n2014) );
OAI21X1TS U3488 ( .A0(n5388), .A1(n4941), .B0(n4833), .Y(n2145) );
OAI21X1TS U3489 ( .A0(n5412), .A1(n4858), .B0(n4621), .Y(n2166) );
OAI21X1TS U3490 ( .A0(n5436), .A1(n4941), .B0(n4933), .Y(n2151) );
OAI21X1TS U3491 ( .A0(n5415), .A1(n4824), .B0(n4818), .Y(n1936) );
OAI21X1TS U3492 ( .A0(n5399), .A1(n4863), .B0(n4646), .Y(n2094) );
OAI21X1TS U3493 ( .A0(n5392), .A1(n4941), .B0(n4775), .Y(n2127) );
OAI21X1TS U3494 ( .A0(n5428), .A1(n4858), .B0(n4857), .Y(n2139) );
OAI21X1TS U3495 ( .A0(n5432), .A1(n4853), .B0(n4658), .Y(n1881) );
OAI21X1TS U3496 ( .A0(n5389), .A1(n4853), .B0(n4518), .Y(n1969) );
OAI21X1TS U3497 ( .A0(n5401), .A1(n4863), .B0(n4485), .Y(n2115) );
OAI21X1TS U3498 ( .A0(n5382), .A1(n4853), .B0(n4535), .Y(n1874) );
OAI21X1TS U3499 ( .A0(n5380), .A1(n4853), .B0(n4467), .Y(n1979) );
OAI21X1TS U3500 ( .A0(n5384), .A1(n4853), .B0(n4499), .Y(n1986) );
OAI21X1TS U3501 ( .A0(n3993), .A1(n6559), .B0(n3991), .Y(n2025) );
NOR2X1TS U3502 ( .A(n4177), .B(n3772), .Y(n3773) );
INVX1TS U3503 ( .A(n6029), .Y(n6020) );
NAND3X2TS U3504 ( .A(n3817), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .C(n6654), .Y(n4181)
);
INVX4TS U3505 ( .A(n6030), .Y(n6050) );
OAI21X1TS U3506 ( .A0(n6619), .A1(n4910), .B0(n4897), .Y(n2105) );
OAI21X1TS U3507 ( .A0(n6682), .A1(n4345), .B0(n4317), .Y(n1814) );
OAI21X1TS U3508 ( .A0(n6607), .A1(n4910), .B0(n4868), .Y(n2117) );
OAI21X1TS U3509 ( .A0(n6746), .A1(n4352), .B0(n4329), .Y(n2102) );
OAI21X1TS U3510 ( .A0(n6596), .A1(n4350), .B0(n4320), .Y(n2255) );
OAI21X1TS U3511 ( .A0(n6656), .A1(n4895), .B0(n4299), .Y(n1873) );
OAI21X1TS U3512 ( .A0(n6659), .A1(n4910), .B0(n4883), .Y(n2123) );
OAI21X1TS U3513 ( .A0(n6633), .A1(n4921), .B0(n4904), .Y(n2177) );
OAI21X1TS U3514 ( .A0(n6747), .A1(n4352), .B0(n4328), .Y(n2156) );
OAI21X1TS U3515 ( .A0(n6740), .A1(n4352), .B0(n4319), .Y(n2150) );
OAI21X1TS U3516 ( .A0(n6625), .A1(n4921), .B0(n4911), .Y(n2132) );
OAI21X1TS U3517 ( .A0(n6612), .A1(n4921), .B0(n4871), .Y(n2159) );
OAI21X1TS U3518 ( .A0(n6647), .A1(n4895), .B0(n4875), .Y(n2251) );
OAI21X1TS U3519 ( .A0(n6604), .A1(n4895), .B0(n4890), .Y(n1921) );
OAI21X1TS U3520 ( .A0(n6622), .A1(n4895), .B0(n4873), .Y(n1935) );
OAI21X1TS U3521 ( .A0(n6602), .A1(n4910), .B0(n4909), .Y(n2096) );
OAI21X1TS U3522 ( .A0(n6643), .A1(n4350), .B0(n3459), .Y(n2186) );
OAI21X1TS U3523 ( .A0(n6605), .A1(n4895), .B0(n4888), .Y(n1938) );
OAI21X1TS U3524 ( .A0(n6678), .A1(n4914), .B0(n4884), .Y(n1985) );
OAI21X1TS U3525 ( .A0(n6625), .A1(n4345), .B0(n4342), .Y(n1806) );
OAI21X1TS U3526 ( .A0(n6624), .A1(n4921), .B0(n4891), .Y(n2153) );
OAI21X1TS U3527 ( .A0(n6606), .A1(n4914), .B0(n4899), .Y(n1941) );
OAI21X1TS U3528 ( .A0(n6745), .A1(n4350), .B0(n4316), .Y(n2180) );
OAI21X1TS U3529 ( .A0(n6651), .A1(n4914), .B0(n4879), .Y(n1978) );
OAI21X1TS U3530 ( .A0(n6750), .A1(n4352), .B0(n4330), .Y(n2126) );
OAI21X1TS U3531 ( .A0(n6628), .A1(n4921), .B0(n4920), .Y(n2165) );
OAI21X1TS U3532 ( .A0(n6645), .A1(n4895), .B0(n4300), .Y(n1887) );
OAI21X1TS U3533 ( .A0(n6607), .A1(n4345), .B0(n4337), .Y(n1826) );
OAI21X1TS U3534 ( .A0(n6646), .A1(n4921), .B0(n4865), .Y(n2135) );
OAI21X1TS U3535 ( .A0(n6742), .A1(n4350), .B0(n4349), .Y(n2162) );
OAI21X1TS U3536 ( .A0(n6764), .A1(n4352), .B0(n4347), .Y(n2129) );
OAI21X1TS U3537 ( .A0(n6626), .A1(n4345), .B0(n4315), .Y(n1794) );
OAI21X1TS U3538 ( .A0(n6634), .A1(n4350), .B0(n4322), .Y(n2254) );
OAI21X1TS U3539 ( .A0(n6611), .A1(n4910), .B0(n4866), .Y(n2114) );
OAI21X1TS U3540 ( .A0(n6659), .A1(n4345), .B0(n4344), .Y(n1818) );
OAI21X1TS U3541 ( .A0(n6613), .A1(n4895), .B0(n4882), .Y(n1892) );
OAI21X1TS U3542 ( .A0(n6751), .A1(n4350), .B0(n4321), .Y(n2174) );
OAI21X1TS U3543 ( .A0(n6611), .A1(n4345), .B0(n4340), .Y(n1830) );
OAI21X1TS U3544 ( .A0(n6623), .A1(n4921), .B0(n4880), .Y(n2248) );
OAI21X1TS U3545 ( .A0(n6741), .A1(n4352), .B0(n4332), .Y(n2138) );
OAI21X1TS U3546 ( .A0(n6680), .A1(n4345), .B0(n4325), .Y(n1810) );
OAI21X1TS U3547 ( .A0(n6603), .A1(n4345), .B0(n4327), .Y(n1822) );
OAI21X1TS U3548 ( .A0(n6608), .A1(n4914), .B0(n4885), .Y(n1948) );
OAI21X1TS U3549 ( .A0(n6617), .A1(n4910), .B0(n4869), .Y(n2111) );
OAI21X1TS U3550 ( .A0(n6739), .A1(n4352), .B0(n4346), .Y(n2141) );
OAI21X1TS U3551 ( .A0(n6627), .A1(n4345), .B0(n4323), .Y(n1798) );
OAI21X1TS U3552 ( .A0(n6629), .A1(n4921), .B0(n4917), .Y(n2147) );
OAI21X1TS U3553 ( .A0(n6749), .A1(n4352), .B0(n4351), .Y(n2108) );
OAI21X1TS U3554 ( .A0(n6618), .A1(n4914), .B0(n4913), .Y(n1965) );
OAI21X1TS U3555 ( .A0(n6650), .A1(n4350), .B0(n4338), .Y(n2253) );
OAI21X1TS U3556 ( .A0(n6646), .A1(n4345), .B0(n4339), .Y(n1802) );
OAI21X1TS U3557 ( .A0(n6630), .A1(n4350), .B0(n4333), .Y(n2256) );
OAI21X1TS U3558 ( .A0(n6743), .A1(n4352), .B0(n4331), .Y(n2120) );
OAI21X1TS U3559 ( .A0(n6615), .A1(n4914), .B0(n4898), .Y(n1951) );
OAI21X1TS U3560 ( .A0(n6748), .A1(n4352), .B0(n4318), .Y(n2144) );
OAI21X1TS U3561 ( .A0(n6616), .A1(n4914), .B0(n4903), .Y(n1968) );
OAI21X1TS U3562 ( .A0(n6677), .A1(n4914), .B0(n4887), .Y(n1999) );
OAI21X1TS U3563 ( .A0(n6597), .A1(n4350), .B0(n4324), .Y(n2168) );
OAI21X1TS U3564 ( .A0(n6744), .A1(n4350), .B0(n4326), .Y(n2171) );
OAI21X1TS U3565 ( .A0(n6658), .A1(n4895), .B0(n4296), .Y(n1880) );
OAI21X1TS U3566 ( .A0(n6657), .A1(n4910), .B0(n4901), .Y(n2006) );
OAI21X1TS U3567 ( .A0(n6657), .A1(n4376), .B0(n3460), .Y(n2004) );
OAI21X1TS U3568 ( .A0(n6677), .A1(n4376), .B0(n4358), .Y(n1997) );
OAI21X1TS U3569 ( .A0(n6679), .A1(n4376), .B0(n4335), .Y(n1990) );
OAI21X1TS U3570 ( .A0(n6678), .A1(n4376), .B0(n4354), .Y(n1983) );
OAI21X1TS U3571 ( .A0(n6620), .A1(n4376), .B0(n4357), .Y(n2018) );
OAI21X1TS U3572 ( .A0(n6609), .A1(n4376), .B0(n4369), .Y(n1973) );
OAI21X1TS U3573 ( .A0(n6618), .A1(n4376), .B0(n4375), .Y(n1963) );
OAI21X1TS U3574 ( .A0(n6696), .A1(n4376), .B0(n4302), .Y(n1958) );
OAI21X1TS U3575 ( .A0(n6663), .A1(n4376), .B0(n4304), .Y(n1956) );
OAI21X1TS U3576 ( .A0(n6621), .A1(n4376), .B0(n4362), .Y(n2011) );
NOR2BX2TS U3577 ( .AN(n4448), .B(n6043), .Y(n4449) );
XNOR2X2TS U3578 ( .A(n4419), .B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n4450) );
OAI21X1TS U3579 ( .A0(n3816), .A1(n3771), .B0(n3770), .Y(n3772) );
NOR2X6TS U3580 ( .A(n3816), .B(n3755), .Y(n3780) );
INVX3TS U3581 ( .A(n4872), .Y(n4373) );
INVX3TS U3582 ( .A(n4872), .Y(n4284) );
INVX3TS U3583 ( .A(n4872), .Y(n4366) );
AO22XLTS U3584 ( .A0(n3230), .A1(n6191), .B0(d_ff2_X[62]), .B1(n6463), .Y(
n2767) );
BUFX4TS U3585 ( .A(n4953), .Y(n4872) );
AOI222X1TS U3586 ( .A0(n4954), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[52]), .B1(n6572), .C0(n4953),
.C1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[52]), .Y(n4949) );
AO22XLTS U3587 ( .A0(d_ff_Yn[57]), .A1(n6291), .B0(d_ff2_Y[57]), .B1(n6294),
.Y(n2589) );
AO22XLTS U3588 ( .A0(n3226), .A1(n6291), .B0(d_ff2_Y[56]), .B1(n6294), .Y(
n2590) );
AOI222X1TS U3589 ( .A0(n4099), .A1(d_ff2_Z[63]), .B0(n4069), .B1(d_ff1_Z[63]), .C0(d_ff_Zn[63]), .C1(n4098), .Y(n4100) );
CLKAND2X2TS U3590 ( .A(n4008), .B(n3800), .Y(n3801) );
AOI222X1TS U3591 ( .A0(n4099), .A1(d_ff2_Z[47]), .B0(n4041), .B1(d_ff1_Z[47]), .C0(d_ff_Zn[47]), .C1(n4087), .Y(n4075) );
OAI211X1TS U3592 ( .A0(n4199), .A1(n6745), .B0(n4198), .C0(n4197), .Y(n2595)
);
OAI211X1TS U3593 ( .A0(n4199), .A1(n6643), .B0(n4195), .C0(n4197), .Y(n2572)
);
OAI211X1TS U3594 ( .A0(n4163), .A1(n6740), .B0(n4044), .C0(n4149), .Y(n2610)
);
CLKBUFX3TS U3595 ( .A(n3872), .Y(n3223) );
OAI211X1TS U3596 ( .A0(n4199), .A1(n6649), .B0(n4191), .C0(n4197), .Y(n2568)
);
OAI211X1TS U3597 ( .A0(n4199), .A1(n6648), .B0(n4192), .C0(n4197), .Y(n2566)
);
NOR2X4TS U3598 ( .A(n4236), .B(n6468), .Y(n4204) );
OAI21X1TS U3599 ( .A0(n6078), .A1(n6079), .B0(n4167), .Y(n3118) );
AOI222X1TS U3600 ( .A0(n6458), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[63]), .B0(n6452), .B1(
d_ff3_sh_y_out[63]), .C0(n6201), .C1(d_ff3_sh_x_out[63]), .Y(n4039) );
BUFX4TS U3601 ( .A(n6148), .Y(n6149) );
NAND2BX1TS U3602 ( .AN(n6098), .B(n6089), .Y(n3128) );
BUFX4TS U3603 ( .A(n3937), .Y(n6148) );
OAI222X1TS U3604 ( .A0(n5441), .A1(n5407), .B0(n5423), .B1(n5406), .C0(n6776), .C1(n5422), .Y(n1714) );
OAI31XLTS U3605 ( .A0(n4186), .A1(n4102), .A2(n6217), .B0(n4101), .Y(n3117)
);
INVX3TS U3606 ( .A(n5385), .Y(n5420) );
INVX3TS U3607 ( .A(n5385), .Y(n5434) );
INVX3TS U3608 ( .A(n5385), .Y(n5443) );
OAI21X1TS U3609 ( .A0(n4105), .A1(n6065), .B0(n4104), .Y(n3134) );
OAI211X1TS U3610 ( .A0(n4123), .A1(n6836), .B0(n6071), .C0(n6065), .Y(n3135)
);
INVX3TS U3611 ( .A(n5385), .Y(n5427) );
OAI211X1TS U3612 ( .A0(n4123), .A1(n6838), .B0(n6071), .C0(n3960), .Y(n3123)
);
OAI211X1TS U3613 ( .A0(n6101), .A1(n6084), .B0(n4190), .C0(n6099), .Y(n3122)
);
NAND3X1TS U3614 ( .A(n6101), .B(n6100), .C(n6099), .Y(n3120) );
INVX3TS U3615 ( .A(n4153), .Y(n6453) );
NAND3X1TS U3616 ( .A(n4570), .B(n4569), .C(n4753), .Y(n4828) );
NAND3X1TS U3617 ( .A(n6115), .B(n6114), .C(n6113), .Y(n3113) );
AO22XLTS U3618 ( .A0(n6460), .A1(n6459), .B0(n6458), .B1(
inst_FPU_PIPELINED_FPADDSUB_intAS), .Y(n2347) );
INVX3TS U3619 ( .A(n6150), .Y(n6151) );
INVX2TS U3620 ( .A(n6217), .Y(n6323) );
NAND3X1TS U3621 ( .A(n4464), .B(n4463), .C(n4462), .Y(n4465) );
NAND3X1TS U3622 ( .A(n4525), .B(n4524), .C(n4523), .Y(n4534) );
INVX2TS U3623 ( .A(n6217), .Y(n4123) );
INVX3TS U3624 ( .A(n4153), .Y(n6393) );
INVX3TS U3625 ( .A(n4153), .Y(n6425) );
INVX3TS U3626 ( .A(n4153), .Y(n6410) );
OAI21X1TS U3627 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54]),
.A1(n3808), .B0(n3807), .Y(n3809) );
NAND3X1TS U3628 ( .A(n3187), .B(n6067), .C(n3183), .Y(n6099) );
INVX3TS U3629 ( .A(n6144), .Y(n4051) );
INVX3TS U3630 ( .A(n6475), .Y(n6578) );
NOR2X1TS U3631 ( .A(n5314), .B(n4943), .Y(n4944) );
OAI21X2TS U3632 ( .A0(n3597), .A1(n3582), .B0(n3581), .Y(n3673) );
INVX3TS U3633 ( .A(n6475), .Y(n6478) );
NAND2BX2TS U3634 ( .AN(n3347), .B(n3346), .Y(n3362) );
OAI21X2TS U3635 ( .A0(n3667), .A1(n3525), .B0(n3524), .Y(n3610) );
NAND3X1TS U3636 ( .A(n3806), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[45]), .C(n6720), .Y(n3807) );
NAND3X1TS U3637 ( .A(n5097), .B(n5096), .C(n5095), .Y(n5165) );
INVX2TS U3638 ( .A(n6476), .Y(n5449) );
NAND3X1TS U3639 ( .A(n5991), .B(n5990), .C(n5989), .Y(n6019) );
NAND3X1TS U3640 ( .A(n5082), .B(n5081), .C(n5080), .Y(n5091) );
INVX2TS U3641 ( .A(n6476), .Y(n5454) );
NAND3X1TS U3642 ( .A(n5035), .B(n5034), .C(n5033), .Y(n5111) );
NAND3X1TS U3643 ( .A(n5006), .B(n5005), .C(n5004), .Y(n5285) );
NAND3X1TS U3644 ( .A(n4732), .B(n4731), .C(n4730), .Y(n4822) );
NOR2X4TS U3645 ( .A(n5375), .B(rst), .Y(n3871) );
NAND3X1TS U3646 ( .A(n4491), .B(n4490), .C(n4489), .Y(n4498) );
NAND3X1TS U3647 ( .A(n4496), .B(n4495), .C(n4494), .Y(n4497) );
INVX2TS U3648 ( .A(n6476), .Y(n5450) );
INVX3TS U3649 ( .A(n6476), .Y(n5452) );
NAND3X1TS U3650 ( .A(n4457), .B(n4456), .C(n4455), .Y(n4466) );
NAND3X1TS U3651 ( .A(n4532), .B(n4531), .C(n4530), .Y(n4533) );
NAND3X1TS U3652 ( .A(n5157), .B(n5156), .C(n5155), .Y(n5239) );
NAND3X1TS U3653 ( .A(n5212), .B(n5211), .C(n5210), .Y(n5259) );
INVX3TS U3654 ( .A(n6476), .Y(n5459) );
NAND3X1TS U3655 ( .A(n4510), .B(n4509), .C(n4508), .Y(n4517) );
NAND3X1TS U3656 ( .A(n4515), .B(n4514), .C(n4513), .Y(n4516) );
NAND2X4TS U3657 ( .A(n3975), .B(n3715), .Y(n3736) );
NAND3X1TS U3658 ( .A(n4629), .B(n4628), .C(n4627), .Y(n4631) );
AOI21X2TS U3659 ( .A0(n3299), .A1(n4399), .B0(n4386), .Y(n4387) );
NAND3X1TS U3660 ( .A(n5088), .B(n5087), .C(n5086), .Y(n5105) );
OAI21X1TS U3661 ( .A0(n3406), .A1(n3405), .B0(n3404), .Y(n3408) );
NOR2X4TS U3662 ( .A(n3714), .B(n3713), .Y(n3975) );
NAND2BXLTS U3663 ( .AN(n4686), .B(n5367), .Y(n4629) );
NAND2X1TS U3664 ( .A(n3703), .B(n3523), .Y(n3525) );
AOI21X1TS U3665 ( .A0(n3702), .A1(n3523), .B0(n3522), .Y(n3524) );
NAND2X1TS U3666 ( .A(n3599), .B(n3580), .Y(n3582) );
OAI21X2TS U3667 ( .A0(n5886), .A1(n3558), .B0(n3557), .Y(n3654) );
NAND2BXLTS U3668 ( .AN(n4786), .B(n5367), .Y(n4732) );
NOR4X1TS U3669 ( .A(n3453), .B(n3429), .C(n3443), .D(n3311), .Y(n3457) );
OAI21X2TS U3670 ( .A0(n4786), .A1(n4647), .B0(n4763), .Y(n3193) );
INVX3TS U3671 ( .A(n4750), .Y(n5374) );
INVX3TS U3672 ( .A(n6592), .Y(n5453) );
NAND3BX1TS U3673 ( .AN(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[1]), .C(n3965), .Y(n5353) );
AND3X1TS U3674 ( .A(n4663), .B(n4662), .C(n4661), .Y(n5364) );
AOI222X1TS U3675 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .A1(n6613), .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .B1(n3286), .C0(n3324), .C1(
n3323), .Y(n3326) );
NAND4XLTS U3676 ( .A(n6498), .B(n6497), .C(n6496), .D(n6495), .Y(n6554) );
INVX3TS U3677 ( .A(n6592), .Y(n6474) );
NOR2X1TS U3678 ( .A(n3729), .B(n3728), .Y(n3730) );
AND3X1TS U3679 ( .A(n4522), .B(n4521), .C(n4661), .Y(n4681) );
INVX1TS U3680 ( .A(n6053), .Y(n6055) );
INVX3TS U3681 ( .A(n6592), .Y(n5451) );
INVX4TS U3682 ( .A(n3942), .Y(n3181) );
INVX3TS U3683 ( .A(n6330), .Y(n6034) );
OAI211X1TS U3684 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]), .A1(
n6623), .B0(n3390), .C0(n3389), .Y(n3391) );
INVX3TS U3685 ( .A(n6462), .Y(n6017) );
AOI211X2TS U3686 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[44]), .A1(
n6742), .B0(n3396), .C0(n3405), .Y(n3403) );
INVX3TS U3687 ( .A(n6329), .Y(n6047) );
INVX2TS U3688 ( .A(n5910), .Y(n5912) );
INVX3TS U3689 ( .A(n6462), .Y(n6022) );
INVX2TS U3690 ( .A(n5855), .Y(n5857) );
INVX3TS U3691 ( .A(n6462), .Y(n6018) );
INVX2TS U3692 ( .A(n5848), .Y(n5849) );
INVX3TS U3693 ( .A(n6462), .Y(n6021) );
INVX3TS U3694 ( .A(n6330), .Y(n6032) );
INVX3TS U3695 ( .A(n6330), .Y(n6035) );
INVX3TS U3696 ( .A(n6330), .Y(n6033) );
INVX3TS U3697 ( .A(n6329), .Y(n6049) );
OAI21X1TS U3698 ( .A0(n4017), .A1(n3741), .B0(n3740), .Y(n3742) );
NOR2X1TS U3699 ( .A(n3257), .B(n3237), .Y(n3764) );
OR3X2TS U3700 ( .A(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[6]), .C(n3709), .Y(n3964) );
INVX3TS U3701 ( .A(n6044), .Y(n6048) );
INVX3TS U3702 ( .A(n6044), .Y(n6045) );
OR2X2TS U3703 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[9]), .B(n3185), .Y(n3296) );
CLKBUFX3TS U3704 ( .A(n4806), .Y(n3214) );
INVX3TS U3705 ( .A(n5053), .Y(n5208) );
INVX3TS U3706 ( .A(n6044), .Y(n6046) );
NOR2X1TS U3707 ( .A(n3412), .B(n3411), .Y(n3425) );
NAND4XLTS U3708 ( .A(n6514), .B(n6513), .C(n6512), .D(n6511), .Y(n6552) );
NAND4XLTS U3709 ( .A(n6506), .B(n6505), .C(n6504), .D(n6503), .Y(n6553) );
INVX3TS U3710 ( .A(n6591), .Y(n5984) );
NOR2X1TS U3711 ( .A(n3382), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[56]),
.Y(n3383) );
NOR2X1TS U3712 ( .A(n3804), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[41]), .Y(n3768) );
INVX3TS U3713 ( .A(n5056), .Y(n5185) );
NAND3X1TS U3714 ( .A(n3278), .B(n3388), .C(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[60]), .Y(n3389) );
NOR2X1TS U3715 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .B(
n3274), .Y(n3727) );
OAI211X2TS U3716 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .A1(
n6611), .B0(n3345), .C0(n3314), .Y(n3339) );
INVX2TS U3717 ( .A(n3786), .Y(n4108) );
INVX2TS U3718 ( .A(n6466), .Y(n6327) );
OAI211X2TS U3719 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .A1(
n6609), .B0(n3360), .C0(n3312), .Y(n3354) );
CLKAND2X2TS U3720 ( .A(n4168), .B(n3751), .Y(n3732) );
INVX3TS U3721 ( .A(n6328), .Y(n6326) );
INVX3TS U3722 ( .A(n5056), .Y(n6559) );
INVX3TS U3723 ( .A(n4458), .Y(n4725) );
OAI211X2TS U3724 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .A1(
n6603), .B0(n3379), .C0(n3364), .Y(n3373) );
NOR2X4TS U3725 ( .A(n5990), .B(n6697), .Y(n4461) );
AOI211X2TS U3726 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[52]), .A1(
n3290), .B0(n3305), .C0(n3411), .Y(n3413) );
NAND2X1TS U3727 ( .A(n6640), .B(n4109), .Y(n3717) );
INVX3TS U3728 ( .A(n6591), .Y(n6477) );
NOR2X1TS U3729 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54]), .B(
n3176), .Y(n3767) );
INVX2TS U3730 ( .A(n6591), .Y(n6569) );
INVX3TS U3731 ( .A(n6328), .Y(n6036) );
NOR2X2TS U3732 ( .A(n3256), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[48]), .Y(n3784) );
NOR2X2TS U3733 ( .A(n3176), .B(n3257), .Y(n3783) );
INVX2TS U3734 ( .A(n6591), .Y(n6575) );
INVX1TS U3735 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(
n5446) );
BUFX3TS U3736 ( .A(n6666), .Y(n4272) );
AND3X2TS U3737 ( .A(cont_var_out[1]), .B(ready_add_subt), .C(n6642), .Y(
n6044) );
NAND2BX1TS U3738 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[47]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[47]), .Y(n3395) );
NAND2BX1TS U3739 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[62]), .Y(n3390) );
NOR2X2TS U3740 ( .A(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n3462) );
NAND2BX1TS U3741 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[62]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]), .Y(n3392) );
NOR2X1TS U3742 ( .A(n6630), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]),
.Y(n3305) );
INVX6TS U3743 ( .A(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n3182)
);
NAND2BX1TS U3744 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[51]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[51]), .Y(n3416) );
NAND2BX1TS U3745 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[40]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[40]), .Y(n3308) );
NAND2BX1TS U3746 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[59]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[59]), .Y(n3384) );
NAND2BX1TS U3747 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[41]), .Y(n3309) );
NAND2BX1TS U3748 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[32]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[32]), .Y(n3310) );
OAI21X1TS U3749 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .A1(n6607), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .Y(n3375) );
NOR2X1TS U3750 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n3740) );
NAND2BX1TS U3751 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .Y(n3351) );
NOR2X1TS U3752 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .Y(n3726) );
NAND2BX1TS U3753 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .Y(n3370) );
NOR2X1TS U3754 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]), .Y(n3721) );
NAND2BX1TS U3755 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .Y(n3364) );
OR2X2TS U3756 ( .A(n6662), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n4488) );
BUFX3TS U3757 ( .A(n4204), .Y(n4229) );
AOI21X4TS U3758 ( .A0(n3646), .A1(n3645), .B0(n3644), .Y(n3647) );
OR2X6TS U3759 ( .A(n5320), .B(n5013), .Y(n5291) );
OAI21X2TS U3760 ( .A0(n3650), .A1(n3649), .B0(n3648), .Y(n6007) );
OAI2BB1X2TS U3761 ( .A0N(n4420), .A1N(n4450), .B0(n3219), .Y(n6030) );
NAND2X1TS U3762 ( .A(n4389), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]), .Y(n4396) );
NAND2X2TS U3763 ( .A(n4009), .B(n3716), .Y(n3718) );
NAND2X4TS U3764 ( .A(n6016), .B(n3820), .Y(n5013) );
NAND2X4TS U3765 ( .A(n3819), .B(n5056), .Y(n6016) );
OAI211X1TS U3766 ( .A0(n5278), .A1(n5221), .B0(n4994), .C0(n4993), .Y(n2510)
);
OAI21X1TS U3767 ( .A0(n5379), .A1(n4941), .B0(n4926), .Y(n2154) );
NAND4BX2TS U3768 ( .AN(n6042), .B(n4440), .C(n4439), .D(n4438), .Y(n4444) );
NOR2X1TS U3769 ( .A(n4429), .B(n6041), .Y(n4440) );
OAI211X1TS U3770 ( .A0(n3220), .A1(n5229), .B0(n5190), .C0(n5189), .Y(n2554)
);
NOR3XLTS U3771 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[34]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33]), .C(n6700), .Y(n3738) );
AOI21X4TS U3772 ( .A0(n5543), .A1(n3620), .B0(n3619), .Y(n5518) );
OAI21X2TS U3773 ( .A0(n3618), .A1(n3617), .B0(n3616), .Y(n5543) );
NOR2X2TS U3774 ( .A(n6053), .B(n6056), .Y(n3967) );
XNOR2X2TS U3775 ( .A(n4416), .B(n4395), .Y(n6041) );
OAI21X4TS U3776 ( .A0(n4412), .A1(n4408), .B0(n4409), .Y(n4416) );
NAND2X2TS U3777 ( .A(n4384), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]), .Y(n4404) );
NAND2X6TS U3778 ( .A(n4174), .B(n6676), .Y(n3749) );
NOR2X8TS U3779 ( .A(n3980), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n4174) );
AOI2BB2X1TS U3780 ( .B0(n5303), .B1(n5302), .A0N(n5301), .A1N(n5300), .Y(
n5308) );
OAI211X1TS U3781 ( .A0(n5310), .A1(n3220), .B0(n5308), .C0(n5307), .Y(n2507)
);
AOI21X2TS U3782 ( .A0(n3610), .A1(n3547), .B0(n3546), .Y(n5487) );
AOI21X4TS U3783 ( .A0(n5528), .A1(n3628), .B0(n3627), .Y(n5537) );
OAI21X2TS U3784 ( .A0(n5499), .A1(n3626), .B0(n3625), .Y(n5528) );
OAI21X1TS U3785 ( .A0(n3684), .A1(n3545), .B0(n3544), .Y(n3546) );
OAI21X4TS U3786 ( .A0(n5549), .A1(n5544), .B0(n5545), .Y(n5520) );
OAI21X4TS U3787 ( .A0(n5511), .A1(n5506), .B0(n5507), .Y(n5501) );
OAI21X4TS U3788 ( .A0(n5479), .A1(n5473), .B0(n5474), .Y(n3636) );
CLKAND2X2TS U3789 ( .A(n6789), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[45]),
.Y(n3619) );
INVX2TS U3790 ( .A(n4401), .Y(n4386) );
CLKAND2X2TS U3791 ( .A(n6788), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[47]),
.Y(n3623) );
NOR2X1TS U3792 ( .A(n6615), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]),
.Y(n3332) );
NAND2BXLTS U3793 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .Y(n3335) );
NAND3XLTS U3794 ( .A(n6616), .B(n3334), .C(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .Y(n3336) );
NOR2X4TS U3795 ( .A(n3749), .B(n3731), .Y(n4170) );
INVX2TS U3796 ( .A(n4396), .Y(n4390) );
NOR2XLTS U3797 ( .A(n4750), .B(n6759), .Y(n4576) );
INVX2TS U3798 ( .A(n3654), .Y(n5877) );
INVX2TS U3799 ( .A(n3597), .Y(n5793) );
AOI21X2TS U3800 ( .A0(n5539), .A1(n5535), .B0(n3639), .Y(n3650) );
CLKAND2X2TS U3801 ( .A(n6790), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[43]),
.Y(n3550) );
CLKAND2X2TS U3802 ( .A(n6787), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[49]),
.Y(n3627) );
BUFX3TS U3803 ( .A(n6473), .Y(n5492) );
OR2X4TS U3804 ( .A(n6556), .B(n4950), .Y(n4906) );
NAND2BXLTS U3805 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .Y(n3334) );
NAND2BXLTS U3806 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .Y(n3314) );
NOR2XLTS U3807 ( .A(n3332), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]),
.Y(n3333) );
OAI21XLTS U3808 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[43]),
.A1(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[44]), .B0(n3760), .Y(
n3762) );
NOR2X1TS U3809 ( .A(n5759), .B(n3698), .Y(n3570) );
NAND2X1TS U3810 ( .A(n3697), .B(n3570), .Y(n3572) );
NOR2X1TS U3811 ( .A(n5839), .B(n3481), .Y(n3483) );
NOR2X1TS U3812 ( .A(n5562), .B(n5676), .Y(n3584) );
NOR2X1TS U3813 ( .A(n5558), .B(n3529), .Y(n3531) );
OAI21XLTS U3814 ( .A0(n3606), .A1(n5638), .B0(n3607), .Y(n3575) );
NOR2X1TS U3815 ( .A(n5757), .B(n3503), .Y(n3505) );
NAND2X1TS U3816 ( .A(n3856), .B(n3505), .Y(n3507) );
NOR2X1TS U3817 ( .A(n5797), .B(n3487), .Y(n3489) );
NOR2X1TS U3818 ( .A(n6604), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]),
.Y(n3368) );
AOI21X2TS U3819 ( .A0(n3654), .A1(n3566), .B0(n3565), .Y(n3597) );
NOR2X1TS U3820 ( .A(n3656), .B(n3564), .Y(n3566) );
OAI21X1TS U3821 ( .A0(n3655), .A1(n3564), .B0(n3563), .Y(n3565) );
NOR2X1TS U3822 ( .A(n3863), .B(n3858), .Y(n3697) );
OAI21XLTS U3823 ( .A0(n3833), .A1(n5774), .B0(n3834), .Y(n3567) );
NAND2X1TS U3824 ( .A(n3838), .B(n3568), .Y(n3692) );
OAI21XLTS U3825 ( .A0(n3497), .A1(n5770), .B0(n3496), .Y(n3498) );
NAND2X1TS U3826 ( .A(n5461), .B(n3499), .Y(n3829) );
NOR2X1TS U3827 ( .A(n5602), .B(n3535), .Y(n3537) );
NAND2X1TS U3828 ( .A(n5586), .B(n3537), .Y(n3539) );
OAI21XLTS U3829 ( .A0(n3517), .A1(n5635), .B0(n3516), .Y(n3518) );
AOI2BB2XLTS U3830 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .B1(
n6630), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[52]), .A1N(n3410),
.Y(n3412) );
OAI21XLTS U3831 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .A1(n6630), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .Y(n3410) );
OAI21XLTS U3832 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[37]), .A1(n3292), .B0(n3428), .Y(n3437) );
AND2X2TS U3833 ( .A(n3445), .B(n3444), .Y(n3446) );
INVX2TS U3834 ( .A(n3443), .Y(n3444) );
NAND2BX1TS U3835 ( .AN(n3442), .B(n3441), .Y(n3447) );
INVX2TS U3836 ( .A(n3440), .Y(n3441) );
NOR2X1TS U3837 ( .A(n3294), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[57]),
.Y(n3382) );
NOR2BX1TS U3838 ( .AN(n3313), .B(n3354), .Y(n3363) );
INVX2TS U3839 ( .A(n4441), .Y(n4418) );
NOR2XLTS U3840 ( .A(n4755), .B(n6731), .Y(n4639) );
NOR2XLTS U3841 ( .A(n4750), .B(n6734), .Y(n4550) );
NOR2XLTS U3842 ( .A(n4755), .B(n6732), .Y(n4555) );
NOR2XLTS U3843 ( .A(n4755), .B(n6755), .Y(n4594) );
NOR2XLTS U3844 ( .A(n4750), .B(n6736), .Y(n4596) );
NOR2XLTS U3845 ( .A(n4755), .B(n6730), .Y(n4756) );
NAND2X1TS U3846 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .Y(n5872) );
AND3X1TS U3847 ( .A(n3804), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[37]), .C(n6721), .Y(n3810) );
AOI21X1TS U3848 ( .A0(n5723), .A1(n3603), .B0(n3602), .Y(n5695) );
NAND2X1TS U3849 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n5788) );
NAND2X1TS U3850 ( .A(n5897), .B(n3475), .Y(n3477) );
NOR2X1TS U3851 ( .A(n5899), .B(n3473), .Y(n3475) );
NOR2X1TS U3852 ( .A(n3845), .B(n3501), .Y(n3856) );
AOI2BB2XLTS U3853 ( .B0(n3811), .B1(n3777), .A0N(n3988), .A1N(n3776), .Y(
n3778) );
OAI21XLTS U3854 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[40]),
.A1(n6701), .B0(n6655), .Y(n3777) );
NAND2X1TS U3855 ( .A(n4171), .B(n3727), .Y(n3728) );
INVX2TS U3856 ( .A(n5999), .Y(n5723) );
CLKAND2X2TS U3857 ( .A(n4669), .B(n4608), .Y(n4650) );
NAND4XLTS U3858 ( .A(n4581), .B(n4580), .C(n4579), .D(n4578), .Y(n5988) );
OAI21X1TS U3859 ( .A0(n5530), .A1(n5524), .B0(n5525), .Y(n5539) );
AOI2BB2XLTS U3860 ( .B0(n5367), .B1(n5366), .A0N(n5365), .A1N(n5364), .Y(
n5368) );
CLKAND2X2TS U3861 ( .A(n4669), .B(n4668), .Y(n5361) );
NAND3XLTS U3862 ( .A(n4171), .B(n6653), .C(n6754), .Y(n4172) );
NAND3XLTS U3863 ( .A(n6758), .B(n4168), .C(n6654), .Y(n4169) );
OAI21XLTS U3864 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[40]),
.A1(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[42]), .B0(n3985), .Y(
n3986) );
AOI2BB2XLTS U3865 ( .B0(n4013), .B1(n4012), .A0N(n4011), .A1N(n4010), .Y(
n4014) );
OAI21X1TS U3866 ( .A0(n5672), .A1(n4130), .B0(n4129), .Y(n5612) );
NAND2X1TS U3867 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[34]), .Y(n5620) );
NAND3X2TS U3868 ( .A(n3899), .B(n3191), .C(n3291), .Y(n3900) );
INVX2TS U3869 ( .A(n3195), .Y(n3241) );
OR2X1TS U3870 ( .A(n5183), .B(n6715), .Y(n5035) );
INVX2TS U3871 ( .A(n3196), .Y(n3240) );
OR2X1TS U3872 ( .A(n5058), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n4983) );
OR2X1TS U3873 ( .A(n5209), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n4981) );
OR2X1TS U3874 ( .A(n5133), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[43]), .Y(n5134) );
OR2X1TS U3875 ( .A(n5207), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[45]), .Y(n5136) );
OR2X1TS U3876 ( .A(n5183), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[43]), .Y(n5157) );
OR2X1TS U3877 ( .A(n5209), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[41]), .Y(n5155) );
OR2X1TS U3878 ( .A(n5098), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30]), .Y(n5097) );
OR2X1TS U3879 ( .A(n5098), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[31]), .Y(n5088) );
AND3X1TS U3880 ( .A(n4989), .B(n4988), .C(n4987), .Y(n5288) );
AND3X1TS U3881 ( .A(n4986), .B(n4985), .C(n4984), .Y(n5287) );
AND3X1TS U3882 ( .A(n4992), .B(n4991), .C(n4990), .Y(n5286) );
OR2X1TS U3883 ( .A(n5058), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n4992) );
BUFX3TS U3884 ( .A(n6271), .Y(n6110) );
AND3X1TS U3885 ( .A(n5003), .B(n5002), .C(n5001), .Y(n5166) );
AND3X1TS U3886 ( .A(n4997), .B(n4996), .C(n4995), .Y(n5267) );
XNOR2X2TS U3887 ( .A(n4398), .B(n4397), .Y(n6039) );
NAND2X1TS U3888 ( .A(n3298), .B(n4396), .Y(n4398) );
NAND2X1TS U3889 ( .A(n4410), .B(n4409), .Y(n4411) );
INVX2TS U3890 ( .A(n4408), .Y(n4410) );
NAND2X1TS U3891 ( .A(n3300), .B(n4414), .Y(n4395) );
AND3X1TS U3892 ( .A(n5050), .B(n5049), .C(n5048), .Y(n5220) );
CLKXOR2X2TS U3893 ( .A(n4403), .B(n4402), .Y(n6025) );
NAND2X1TS U3894 ( .A(n3299), .B(n4401), .Y(n4402) );
AOI21X1TS U3895 ( .A0(n4400), .A1(n3301), .B0(n4399), .Y(n4403) );
AND3X1TS U3896 ( .A(n5150), .B(n5149), .C(n5148), .Y(n5226) );
OR2X1TS U3897 ( .A(n5209), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[47]), .Y(n5120) );
OR2X1TS U3898 ( .A(n5207), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[47]), .Y(n5125) );
AND3X1TS U3899 ( .A(n5130), .B(n5129), .C(n5128), .Y(n5143) );
AND3X1TS U3900 ( .A(n5118), .B(n5117), .C(n5116), .Y(n5182) );
OR2X1TS U3901 ( .A(n5209), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[39]), .Y(n5210) );
AND3X1TS U3902 ( .A(n5178), .B(n5177), .C(n5176), .Y(n5251) );
OR2X1TS U3903 ( .A(n5183), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[37]), .Y(n5038) );
AND3X1TS U3904 ( .A(n5175), .B(n5174), .C(n5173), .Y(n5342) );
OR2X1TS U3905 ( .A(n5183), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[39]), .Y(n5175) );
OR2X1TS U3906 ( .A(n6011), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[37]), .Y(n5173) );
AND3X1TS U3907 ( .A(n5206), .B(n5205), .C(n5204), .Y(n5351) );
OR2X1TS U3908 ( .A(n5098), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33]), .Y(n5082) );
OR2X1TS U3909 ( .A(n5098), .B(n6700), .Y(n5085) );
INVX2TS U3910 ( .A(n5860), .Y(n5861) );
OR2X1TS U3911 ( .A(n5098), .B(n6825), .Y(n4964) );
NOR2XLTS U3912 ( .A(n6816), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[44]), .Y(
n3617) );
INVX2TS U3913 ( .A(n5839), .Y(n5842) );
OAI21XLTS U3914 ( .A0(n5906), .A1(n5900), .B0(n5901), .Y(n5890) );
AO22XLTS U3915 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .A1(
n5371), .B0(n3206), .B1(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]),
.Y(n3952) );
INVX2TS U3916 ( .A(n5926), .Y(n5916) );
OAI21XLTS U3917 ( .A0(n5618), .A1(n3685), .B0(n3684), .Y(n3688) );
INVX2TS U3918 ( .A(n5653), .Y(n3679) );
OAI21XLTS U3919 ( .A0(n3864), .A1(n3863), .B0(n3862), .Y(n3866) );
NOR2XLTS U3920 ( .A(n6814), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]), .Y(
n3626) );
INVX2TS U3921 ( .A(n5811), .Y(n5814) );
INVX2TS U3922 ( .A(ready_cordic), .Y(n4201) );
BUFX3TS U3923 ( .A(n4297), .Y(n4313) );
OR2X1TS U3924 ( .A(n5098), .B(n6703), .Y(n4961) );
INVX2TS U3925 ( .A(n5797), .Y(n5800) );
OR2X1TS U3926 ( .A(n5133), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n4973) );
OR2X1TS U3927 ( .A(n5207), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n4975) );
OR2X1TS U3928 ( .A(n5098), .B(n6675), .Y(n5017) );
OR2X1TS U3929 ( .A(n5207), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n5074) );
AND3X1TS U3930 ( .A(n4972), .B(n4971), .C(n4970), .Y(n5298) );
AND3X1TS U3931 ( .A(n4978), .B(n4977), .C(n4976), .Y(n5292) );
OR2X1TS U3932 ( .A(n5133), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n4976) );
OR2X1TS U3933 ( .A(n5207), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n4978) );
AND3X1TS U3934 ( .A(n4969), .B(n4968), .C(n4967), .Y(n5279) );
OR2X1TS U3935 ( .A(n5183), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n5000) );
OR2X1TS U3936 ( .A(n5209), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n4998) );
BUFX3TS U3937 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n5056) );
OAI21XLTS U3938 ( .A0(n5625), .A1(n5489), .B0(n5488), .Y(n5491) );
NOR2XLTS U3939 ( .A(n3685), .B(n3545), .Y(n3547) );
INVX2TS U3940 ( .A(n5648), .Y(n5651) );
INVX2TS U3941 ( .A(n5662), .Y(n5665) );
INVX2TS U3942 ( .A(n5681), .Y(n5682) );
INVX2TS U3943 ( .A(n3610), .Y(n5618) );
BUFX3TS U3944 ( .A(n4906), .Y(n4910) );
BUFX3TS U3945 ( .A(n6595), .Y(n6590) );
BUFX3TS U3946 ( .A(n4906), .Y(n4895) );
INVX2TS U3947 ( .A(n4906), .Y(n4954) );
NAND2X1TS U3948 ( .A(n6313), .B(n6723), .Y(n6316) );
NAND2X1TS U3949 ( .A(n6161), .B(n6737), .Y(n6164) );
BUFX3TS U3950 ( .A(n6256), .Y(n6175) );
NAND2X1TS U3951 ( .A(n6157), .B(n6722), .Y(n6162) );
OAI21XLTS U3952 ( .A0(n6643), .A1(n4906), .B0(n4905), .Y(n2252) );
AO22XLTS U3953 ( .A0(n6118), .A1(d_ff1_shift_region_flag_out[0]), .B0(n6126),
.B1(shift_region_flag[0]), .Y(n3109) );
AO22XLTS U3954 ( .A0(n6118), .A1(d_ff1_operation_out), .B0(n6131), .B1(
operation), .Y(n3110) );
AO22XLTS U3955 ( .A0(d_ff_Yn[59]), .A1(n3936), .B0(d_ff2_Y[59]), .B1(n6294),
.Y(n2587) );
AO22XLTS U3956 ( .A0(n6118), .A1(d_ff1_shift_region_flag_out[1]), .B0(n6122),
.B1(shift_region_flag[1]), .Y(n3108) );
AOI22X1TS U3957 ( .A0(n3651), .A1(n6008), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54]), .B1(n5492), .Y(
n3652) );
XOR2X1TS U3958 ( .A(n3647), .B(n6817), .Y(n3653) );
XNOR2X1TS U3959 ( .A(n6007), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[54]), .Y(n3651) );
AOI2BB2XLTS U3960 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .B1(
n3279), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .A1N(n3319),
.Y(n3320) );
NOR2X1TS U3961 ( .A(n5637), .B(n3606), .Y(n3576) );
OAI21XLTS U3962 ( .A0(n5881), .A1(n5901), .B0(n5882), .Y(n3555) );
NOR2X1TS U3963 ( .A(n3661), .B(n3663), .Y(n3562) );
NAND2X1TS U3964 ( .A(n3985), .B(n6640), .Y(n3759) );
NOR2X1TS U3965 ( .A(n4131), .B(n4133), .Y(n3586) );
NAND2X1TS U3966 ( .A(n4127), .B(n3586), .Y(n3588) );
NAND2X1TS U3967 ( .A(n3605), .B(n3576), .Y(n3578) );
OAI21XLTS U3968 ( .A0(n3487), .A1(n5798), .B0(n3486), .Y(n3488) );
OAI221X1TS U3969 ( .A0(n6685), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .B0(n6608), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .C0(n6533), .Y(n6536) );
NOR2XLTS U3970 ( .A(n3414), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[48]),
.Y(n3415) );
OAI21XLTS U3971 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .A1(n6628), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[32]), .Y(n3430) );
NOR2BX1TS U3972 ( .AN(n3330), .B(n3329), .Y(n3347) );
NOR2BX1TS U3973 ( .AN(n3316), .B(n3315), .Y(n3330) );
OAI211XLTS U3974 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .A1(n6616), .B0(n3334), .C0(n3337), .Y(n3315) );
OAI2BB2XLTS U3975 ( .B0(n3340), .B1(n3339), .A0N(n3338), .A1N(n3337), .Y(
n3343) );
OAI21XLTS U3976 ( .A0(n5855), .A1(n5860), .B0(n5856), .Y(n3559) );
NAND2X1TS U3977 ( .A(n5847), .B(n3560), .Y(n3656) );
XOR2X1TS U3978 ( .A(n4380), .B(n3185), .Y(n4389) );
NOR2BX1TS U3979 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4380) );
XOR2X1TS U3980 ( .A(n4391), .B(n3182), .Y(n4392) );
XOR2X1TS U3981 ( .A(n4393), .B(n3185), .Y(n4394) );
XOR2X1TS U3982 ( .A(n3182), .B(n4382), .Y(n4385) );
NOR2BX1TS U3983 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4382) );
NOR2BX1TS U3984 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4381) );
NAND2X1TS U3985 ( .A(n5710), .B(n3574), .Y(n3600) );
OAI21X1TS U3986 ( .A0(n5830), .A1(n5872), .B0(n5831), .Y(n5848) );
NOR2X1TS U3987 ( .A(n5871), .B(n5830), .Y(n5847) );
OAI21XLTS U3988 ( .A0(n3473), .A1(n5898), .B0(n3472), .Y(n3474) );
OAI21XLTS U3989 ( .A0(n3698), .A1(n5760), .B0(n3699), .Y(n3569) );
NOR2X1TS U3990 ( .A(n3692), .B(n3572), .Y(n3599) );
INVX2TS U3991 ( .A(n3975), .Y(n3799) );
INVX2TS U3992 ( .A(n3974), .Y(n3797) );
OAI21XLTS U3993 ( .A0(n3481), .A1(n5840), .B0(n3480), .Y(n3482) );
NAND2X1TS U3994 ( .A(n5826), .B(n3483), .Y(n3881) );
INVX2TS U3995 ( .A(n4168), .Y(n3752) );
NAND4XLTS U3996 ( .A(n3787), .B(n3786), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33]), .D(n6705), .Y(n3788) );
NAND3XLTS U3997 ( .A(n4117), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .C(n6691), .Y(n3790) );
NOR2XLTS U3998 ( .A(n4108), .B(n3738), .Y(n3745) );
INVX2TS U3999 ( .A(n3734), .Y(n3735) );
NOR2X1TS U4000 ( .A(n3678), .B(n3680), .Y(n3590) );
NOR2X1TS U4001 ( .A(n5648), .B(n3541), .Y(n3543) );
NOR2X1TS U4002 ( .A(n4126), .B(n3588), .Y(n3674) );
NOR2X1TS U4003 ( .A(n5594), .B(n5590), .Y(n4127) );
OAI21XLTS U4004 ( .A0(n5676), .A1(n5681), .B0(n5677), .Y(n3583) );
NAND2X1TS U4005 ( .A(n5565), .B(n3584), .Y(n4126) );
NOR2X1TS U4006 ( .A(n5619), .B(n5573), .Y(n5565) );
NAND2X1TS U4007 ( .A(n5554), .B(n3531), .Y(n5585) );
NAND2X1TS U4008 ( .A(n5634), .B(n3519), .Y(n3521) );
OAI21X1TS U4009 ( .A0(n3830), .A1(n3507), .B0(n3506), .Y(n3702) );
OAI21XLTS U4010 ( .A0(n3503), .A1(n5756), .B0(n3502), .Y(n3504) );
NOR2X1TS U4011 ( .A(n3829), .B(n3507), .Y(n3703) );
AOI21X1TS U4012 ( .A0(n5727), .A1(n3513), .B0(n3512), .Y(n5630) );
OAI21XLTS U4013 ( .A0(n3511), .A1(n5730), .B0(n3510), .Y(n3512) );
NAND2X1TS U4014 ( .A(n5728), .B(n3513), .Y(n5629) );
NAND2X1TS U4015 ( .A(n3292), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[37]),
.Y(n3427) );
OAI21X1TS U4016 ( .A0(n5877), .A1(n3656), .B0(n3655), .Y(n3892) );
NOR2X1TS U4017 ( .A(n5811), .B(n3485), .Y(n3882) );
NAND2X1TS U4018 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
n3185), .Y(n4430) );
OAI21X2TS U4019 ( .A0(n4437), .A1(n4433), .B0(n4434), .Y(n4432) );
NAND2X1TS U4020 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[9]), .B(
n3182), .Y(n4441) );
NOR2X1TS U4021 ( .A(n3890), .B(n3886), .Y(n3657) );
NAND4BXLTS U4022 ( .AN(n6040), .B(n4428), .C(n4427), .D(n4426), .Y(n4429) );
NOR2XLTS U4023 ( .A(n6024), .B(n6038), .Y(n4428) );
INVX2TS U4024 ( .A(n5844), .Y(n5862) );
INVX2TS U4025 ( .A(n5915), .Y(n5927) );
NOR2XLTS U4026 ( .A(n5958), .B(n3467), .Y(n3469) );
OAI21XLTS U4027 ( .A0(n3467), .A1(n5957), .B0(n3466), .Y(n3468) );
AOI21X1TS U4028 ( .A0(n5793), .A1(n3599), .B0(n3598), .Y(n5999) );
AOI21X1TS U4029 ( .A0(n5793), .A1(n3695), .B0(n3694), .Y(n3864) );
INVX2TS U4030 ( .A(n4011), .Y(n3976) );
AOI21X1TS U4031 ( .A0(n5787), .A1(n3703), .B0(n3702), .Y(n5718) );
INVX2TS U4032 ( .A(n5941), .Y(n5966) );
INVX2TS U4033 ( .A(n3890), .Y(n5817) );
MX2X1TS U4034 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[27]), .S0(n6010), .Y(
n5014) );
AOI21X1TS U4035 ( .A0(n5787), .A1(n3832), .B0(n3831), .Y(n3846) );
AOI21X1TS U4036 ( .A0(n3675), .A1(n3590), .B0(n3589), .Y(n5488) );
OAI21XLTS U4037 ( .A0(n3680), .A1(n5653), .B0(n3681), .Y(n3589) );
NAND2X1TS U4038 ( .A(n3674), .B(n3590), .Y(n5489) );
INVX2TS U4039 ( .A(n3678), .Y(n5654) );
OAI21X1TS U4040 ( .A0(n5584), .A1(n3539), .B0(n3538), .Y(n4138) );
OAI21XLTS U4041 ( .A0(n3535), .A1(n5603), .B0(n3534), .Y(n3536) );
NOR2X1TS U4042 ( .A(n5585), .B(n3539), .Y(n4137) );
INVX2TS U4043 ( .A(n4131), .Y(n5608) );
OAI21X1TS U4044 ( .A0(n5625), .A1(n4126), .B0(n4125), .Y(n5596) );
NOR2X1TS U4045 ( .A(n5662), .B(n3533), .Y(n5586) );
INVX2TS U4046 ( .A(n5594), .Y(n5668) );
INVX2TS U4047 ( .A(n5562), .Y(n5683) );
OAI21X1TS U4048 ( .A0(n3527), .A1(n5616), .B0(n3526), .Y(n5555) );
NOR2X1TS U4049 ( .A(n5745), .B(n5690), .Y(n3605) );
NAND4XLTS U4050 ( .A(n6550), .B(n6549), .C(n6548), .D(n6547), .Y(n6551) );
INVX2TS U4051 ( .A(n3426), .Y(n3450) );
OA21XLTS U4052 ( .A0(n3387), .A1(n3386), .B0(n3385), .Y(n3393) );
NAND2X1TS U4053 ( .A(n3381), .B(n3380), .Y(n3456) );
OAI2BB2XLTS U4054 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .B1(
n3367), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .A1N(n6602),
.Y(n3378) );
NAND2X1TS U4055 ( .A(n3462), .B(n3899), .Y(n3875) );
INVX2TS U4056 ( .A(n3886), .Y(n3888) );
NAND2X2TS U4057 ( .A(n5375), .B(n3217), .Y(n6061) );
NOR3X1TS U4058 ( .A(cont_var_out[0]), .B(n6695), .C(n6458), .Y(n3902) );
XOR2X1TS U4059 ( .A(n4447), .B(n4446), .Y(n6043) );
NAND2X1TS U4060 ( .A(n3280), .B(n4445), .Y(n4446) );
XOR2X1TS U4061 ( .A(n4425), .B(n4424), .Y(n6042) );
NAND2X1TS U4062 ( .A(n4423), .B(n4422), .Y(n4424) );
INVX2TS U4063 ( .A(n4421), .Y(n4423) );
XOR2X1TS U4064 ( .A(n4437), .B(n4436), .Y(n6026) );
NAND2X1TS U4065 ( .A(n4435), .B(n4434), .Y(n4436) );
XNOR2X1TS U4066 ( .A(n4432), .B(n4431), .Y(n6027) );
NAND2X1TS U4067 ( .A(n3295), .B(n4430), .Y(n4431) );
XNOR2X1TS U4068 ( .A(n4443), .B(n4442), .Y(n6028) );
NAND2X1TS U4069 ( .A(n3296), .B(n4441), .Y(n4442) );
NAND2X6TS U4070 ( .A(n6050), .B(n6037), .Y(n6029) );
OR2X1TS U4071 ( .A(n6010), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n5028) );
OAI211XLTS U4072 ( .A0(n5365), .A1(n4786), .B0(n4767), .C0(n4766), .Y(n4768)
);
CLKAND2X2TS U4073 ( .A(n4764), .B(n4763), .Y(n5444) );
INVX2TS U4074 ( .A(n3302), .Y(n4939) );
INVX4TS U4075 ( .A(n3302), .Y(n4856) );
CLKAND2X2TS U4076 ( .A(n4615), .B(n4753), .Y(n4616) );
BUFX3TS U4077 ( .A(n4927), .Y(n4858) );
CLKAND2X2TS U4078 ( .A(n4675), .B(n4753), .Y(n4676) );
AOI2BB2XLTS U4079 ( .B0(n5371), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .A0N(n4755), .A1N(
n6738), .Y(n4585) );
BUFX3TS U4080 ( .A(n4927), .Y(n4863) );
INVX4TS U4081 ( .A(n3302), .Y(n4861) );
INVX4TS U4082 ( .A(n3302), .Y(n4830) );
AOI2BB2XLTS U4083 ( .B0(n3206), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .A0N(n4845), .A1N(
n6735), .Y(n4847) );
INVX4TS U4084 ( .A(n3302), .Y(n4851) );
AOI2BB2XLTS U4085 ( .B0(n3206), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .A0N(n4845), .A1N(
n6759), .Y(n4655) );
BUFX3TS U4086 ( .A(n4927), .Y(n4853) );
OAI21XLTS U4087 ( .A0(n5885), .A1(n5870), .B0(n5869), .Y(n5875) );
INVX2TS U4088 ( .A(n5830), .Y(n5832) );
OAI21XLTS U4089 ( .A0(n5877), .A1(n5871), .B0(n5872), .Y(n5835) );
AOI2BB1X1TS U4090 ( .A0N(n3816), .A1N(n3815), .B0(n3814), .Y(n3818) );
INVX2TS U4091 ( .A(n5704), .Y(n5706) );
OAI21XLTS U4092 ( .A0(n5738), .A1(n5732), .B0(n5733), .Y(n5712) );
NAND2X1TS U4093 ( .A(n4020), .B(n3773), .Y(n6015) );
INVX2TS U4094 ( .A(n5690), .Y(n5692) );
OAI21XLTS U4095 ( .A0(n5758), .A1(n5757), .B0(n5756), .Y(n5763) );
INVX2TS U4096 ( .A(n3661), .Y(n5803) );
INVX2TS U4097 ( .A(n3833), .Y(n3835) );
OAI21XLTS U4098 ( .A0(n5779), .A1(n5773), .B0(n5774), .Y(n3840) );
INVX2TS U4099 ( .A(n5773), .Y(n5775) );
OAI21XLTS U4100 ( .A0(n5772), .A1(n5771), .B0(n5770), .Y(n5777) );
CLKAND2X2TS U4101 ( .A(n4682), .B(n4837), .Y(n5439) );
INVX2TS U4102 ( .A(n5462), .Y(n5464) );
CLKAND2X2TS U4103 ( .A(n4838), .B(n4837), .Y(n5437) );
CLKAND2X2TS U4104 ( .A(n4487), .B(n4837), .Y(n5384) );
CLKAND2X2TS U4105 ( .A(n4379), .B(n4763), .Y(n5380) );
CLKAND2X2TS U4106 ( .A(n4787), .B(n4836), .Y(n4788) );
BUFX3TS U4107 ( .A(n6182), .Y(n6413) );
BUFX3TS U4108 ( .A(n6182), .Y(n6434) );
BUFX3TS U4109 ( .A(n6218), .Y(n6431) );
CLKAND2X2TS U4110 ( .A(n4805), .B(n5367), .Y(n4483) );
NAND4BXLTS U4111 ( .AN(n4479), .B(n4478), .C(n4477), .D(n4476), .Y(n4484) );
CLKAND2X2TS U4112 ( .A(n4591), .B(n4763), .Y(n5387) );
BUFX3TS U4113 ( .A(n6218), .Y(n6451) );
BUFX3TS U4114 ( .A(n6218), .Y(n6428) );
INVX2TS U4115 ( .A(n3967), .Y(n5356) );
NAND2BX1TS U4116 ( .AN(n3304), .B(n3965), .Y(n5354) );
INVX2TS U4117 ( .A(n5732), .Y(n5734) );
OAI21XLTS U4118 ( .A0(n5996), .A1(n5731), .B0(n5730), .Y(n5736) );
INVX2TS U4119 ( .A(n3698), .Y(n3700) );
INVX2TS U4120 ( .A(n3680), .Y(n3682) );
INVX2TS U4121 ( .A(n5992), .Y(n5994) );
INVX2TS U4122 ( .A(n3858), .Y(n3860) );
INVX2TS U4123 ( .A(n5998), .Y(n5719) );
OAI21XLTS U4124 ( .A0(n5718), .A1(n5717), .B0(n5716), .Y(n5721) );
INVX2TS U4125 ( .A(n5900), .Y(n5902) );
OAI21XLTS U4126 ( .A0(n5914), .A1(n5899), .B0(n5898), .Y(n5904) );
CLKAND2X2TS U4127 ( .A(n4503), .B(n4837), .Y(n5389) );
BUFX3TS U4128 ( .A(n6460), .Y(n4153) );
CLKAND2X2TS U4129 ( .A(n4703), .B(n4702), .Y(n5429) );
CLKAND2X2TS U4130 ( .A(n4575), .B(n4763), .Y(n5391) );
CLKAND2X2TS U4131 ( .A(n4624), .B(n4623), .Y(n5396) );
CLKAND2X2TS U4132 ( .A(n4741), .B(n4740), .Y(n5405) );
CLKAND2X2TS U4133 ( .A(n4699), .B(n4698), .Y(n5415) );
CLKAND2X2TS U4134 ( .A(n4809), .B(n4808), .Y(n5407) );
CLKAND2X2TS U4135 ( .A(n4546), .B(n4545), .Y(n5417) );
CLKAND2X2TS U4136 ( .A(n4667), .B(n4666), .Y(n5411) );
CLKAND2X2TS U4137 ( .A(n4735), .B(n4734), .Y(n5421) );
CLKAND2X2TS U4138 ( .A(n4612), .B(n4611), .Y(n5413) );
CLKAND2X2TS U4139 ( .A(n4683), .B(n4836), .Y(n4566) );
BUFX3TS U4140 ( .A(n6376), .Y(n6371) );
OAI21XLTS U4141 ( .A0(n5959), .A1(n5958), .B0(n5957), .Y(n5964) );
OAI21X1TS U4142 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(
n5358), .Y(n6051) );
CLKBUFX2TS U4143 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[49]), .Y(
n3256) );
BUFX3TS U4144 ( .A(n6144), .Y(n6150) );
INVX2TS U4145 ( .A(n3863), .Y(n3847) );
OR2X1TS U4146 ( .A(n5183), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54]), .Y(n4947) );
AO22XLTS U4147 ( .A0(n5371), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .B0(n3206), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .Y(n5372) );
NAND4BXLTS U4148 ( .AN(n4182), .B(n4181), .C(n4180), .D(n4179), .Y(n6012) );
NAND3BXLTS U4149 ( .AN(n4177), .B(n4176), .C(n4175), .Y(n4182) );
NAND3BX1TS U4150 ( .AN(n4120), .B(n4119), .C(n4118), .Y(n6014) );
OAI211XLTS U4151 ( .A0(n4114), .A1(n4113), .B0(n4112), .C0(n4111), .Y(n4115)
);
OAI21XLTS U4152 ( .A0(n4110), .A1(n6705), .B0(n4014), .Y(n4015) );
INVX2TS U4153 ( .A(n5473), .Y(n5475) );
INVX2TS U4154 ( .A(n5483), .Y(n5485) );
INVX2TS U4155 ( .A(n4133), .Y(n4135) );
INVX2TS U4156 ( .A(n5676), .Y(n5678) );
INVX2TS U4157 ( .A(n5573), .Y(n5575) );
OAI21XLTS U4158 ( .A0(n5625), .A1(n5619), .B0(n5620), .Y(n5579) );
INVX2TS U4159 ( .A(n5619), .Y(n5621) );
OAI21XLTS U4160 ( .A0(n5618), .A1(n5617), .B0(n5616), .Y(n5623) );
AOI21X1TS U4161 ( .A0(n5751), .A1(n3605), .B0(n3604), .Y(n5643) );
INVX2TS U4162 ( .A(n5637), .Y(n5639) );
OAI21XLTS U4163 ( .A0(n5694), .A1(n5636), .B0(n5635), .Y(n5641) );
OAI21XLTS U4164 ( .A0(n5744), .A1(n5743), .B0(n5742), .Y(n5749) );
CLKAND2X2TS U4165 ( .A(n6753), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[51]),
.Y(n3644) );
AND2X4TS U4166 ( .A(n5356), .B(n6051), .Y(n6460) );
INVX4TS U4167 ( .A(n6239), .Y(n6293) );
NAND2X2TS U4168 ( .A(n3212), .B(n3297), .Y(n6105) );
NOR2X2TS U4169 ( .A(n6105), .B(n3973), .Y(n6069) );
AO21XLTS U4170 ( .A0(n6673), .A1(n3183), .B0(n6113), .Y(n3971) );
CLKAND2X2TS U4171 ( .A(n6071), .B(n4103), .Y(n6068) );
OAI21XLTS U4172 ( .A0(n6010), .A1(n3185), .B0(n5058), .Y(n2081) );
MX2X1TS U4173 ( .A(intadd_44_SUM_0_), .B(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]), .S0(n6593), .Y(
n2271) );
MX2X1TS U4174 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[50]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[50]), .S0(n5984), .Y(n2176)
);
MX2X1TS U4175 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[33]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[33]), .S0(n6474), .Y(n1760)
);
MX2X1TS U4176 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[34]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[34]), .S0(n6474), .Y(n1772)
);
MX2X1TS U4177 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[35]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[35]), .S0(n6474), .Y(n1784)
);
MX2X1TS U4178 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[36]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[36]), .S0(n5455), .Y(n1796)
);
MX2X1TS U4179 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]), .S0(n6474), .Y(n1820)
);
MX2X1TS U4180 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[31]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[31]), .S0(n6474), .Y(n1824)
);
MX2X1TS U4181 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]), .S0(n5453), .Y(n1828)
);
MX2X1TS U4182 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]), .S0(n5453), .Y(n1832)
);
MX2X1TS U4183 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]), .S0(n6474), .Y(n1836)
);
MX2X1TS U4184 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]), .S0(n5453), .Y(n1840)
);
MX2X1TS U4185 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]), .S0(n5453), .Y(n1848)
);
MX2X1TS U4186 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]), .S0(n5451), .Y(n1852)
);
MX2X1TS U4187 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]), .S0(n5453), .Y(n1856)
);
MX2X1TS U4188 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0]), .S0(n5455), .Y(n1869)
);
MX2X1TS U4189 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2]), .S0(n5455), .Y(n1883)
);
MX2X1TS U4190 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4]), .S0(n5455), .Y(n1890)
);
MX2X1TS U4191 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5]), .S0(n5455), .Y(n1897)
);
MX2X1TS U4192 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]), .S0(n5453), .Y(n1905)
);
MX2X1TS U4193 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]), .S0(n5451), .Y(n1909)
);
MX2X1TS U4194 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]), .S0(n6474), .Y(n1913)
);
MX2X1TS U4195 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]), .S0(n5451), .Y(n1917)
);
MX2X1TS U4196 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]), .S0(n5451), .Y(n1931)
);
MX2X1TS U4197 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]), .S0(n5451), .Y(n1944)
);
MX2X1TS U4198 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9]), .S0(n5453), .Y(n1954)
);
MX2X1TS U4199 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]), .S0(n5451), .Y(n1961)
);
MX2X1TS U4200 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]), .S0(n5451), .Y(n1971)
);
MX2X1TS U4201 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6]), .S0(n5455), .Y(n1981)
);
MX2X1TS U4202 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]), .S0(n5453), .Y(n1995)
);
MX2X1TS U4203 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]), .S0(n5451), .Y(n2016)
);
MX2X1TS U4204 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]), .S0(n6477), .Y(n1920)
);
OAI21XLTS U4205 ( .A0(n3181), .A1(n6716), .B0(n5058), .Y(n3043) );
AOI222X1TS U4206 ( .A0(n4294), .A1(data_output[56]), .B0(n4204), .B1(n3226),
.C0(n4297), .C1(d_ff_Xn[56]), .Y(n4289) );
MX2X1TS U4207 ( .A(result_add_subt[7]), .B(d_ff_Yn[7]), .S0(n6032), .Y(n3015) );
MX2X1TS U4208 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3]), .S0(n5454), .Y(n1767)
);
AO22XLTS U4209 ( .A0(n6457), .A1(d_ff2_Z[63]), .B0(n6456), .B1(
d_ff3_sign_out), .Y(n2348) );
AO22XLTS U4210 ( .A0(n6328), .A1(result_add_subt[57]), .B0(n6461), .B1(
d_ff_Yn[57]), .Y(n2489) );
AO22XLTS U4211 ( .A0(n6328), .A1(result_add_subt[55]), .B0(n6326), .B1(
d_ff_Yn[55]), .Y(n2495) );
AO22XLTS U4212 ( .A0(n6328), .A1(result_add_subt[53]), .B0(n6326), .B1(
d_ff_Yn[53]), .Y(n2501) );
AO22XLTS U4213 ( .A0(n6328), .A1(result_add_subt[63]), .B0(n6326), .B1(
d_ff_Yn[63]), .Y(n2751) );
AO22XLTS U4214 ( .A0(d_ff_Yn[2]), .A1(n6191), .B0(d_ff2_Y[2]), .B1(n6294),
.Y(n2744) );
AO22XLTS U4215 ( .A0(d_ff_Xn[4]), .A1(n6147), .B0(d_ff2_X[4]), .B1(n6200),
.Y(n2873) );
AO22XLTS U4216 ( .A0(d_ff_Yn[25]), .A1(n6253), .B0(d_ff2_Y[25]), .B1(n6259),
.Y(n2675) );
AO22XLTS U4217 ( .A0(d_ff_Yn[23]), .A1(n6253), .B0(d_ff2_Y[23]), .B1(n6235),
.Y(n2681) );
AO22XLTS U4218 ( .A0(d_ff_Yn[26]), .A1(n6253), .B0(d_ff2_Y[26]), .B1(n6259),
.Y(n2672) );
AO22XLTS U4219 ( .A0(d_ff_Yn[11]), .A1(n6221), .B0(d_ff2_Y[11]), .B1(n6200),
.Y(n2717) );
AO22XLTS U4220 ( .A0(d_ff_Yn[21]), .A1(n6253), .B0(d_ff2_Y[21]), .B1(n6231),
.Y(n2687) );
AO22XLTS U4221 ( .A0(d_ff_Yn[8]), .A1(n6191), .B0(d_ff2_Y[8]), .B1(n6463),
.Y(n2726) );
AO22XLTS U4222 ( .A0(d_ff_Yn[20]), .A1(n6274), .B0(d_ff2_Y[20]), .B1(n6231),
.Y(n2690) );
AO22XLTS U4223 ( .A0(d_ff_Yn[6]), .A1(n6191), .B0(d_ff2_Y[6]), .B1(n6463),
.Y(n2732) );
AO22XLTS U4224 ( .A0(d_ff_Yn[16]), .A1(n6221), .B0(d_ff2_Y[16]), .B1(n6231),
.Y(n2702) );
AO22XLTS U4225 ( .A0(d_ff_Yn[18]), .A1(n6221), .B0(d_ff2_Y[18]), .B1(n6231),
.Y(n2696) );
AO22XLTS U4226 ( .A0(d_ff_Yn[19]), .A1(n6253), .B0(d_ff2_Y[19]), .B1(n6231),
.Y(n2693) );
AO22XLTS U4227 ( .A0(n3936), .A1(d_ff_Xn[63]), .B0(d_ff2_X[63]), .B1(n6235),
.Y(n2755) );
AO22XLTS U4228 ( .A0(d_ff_Yn[13]), .A1(n6221), .B0(d_ff2_Y[13]), .B1(n6231),
.Y(n2711) );
AO22XLTS U4229 ( .A0(d_ff_Yn[32]), .A1(n6274), .B0(d_ff2_Y[32]), .B1(n6259),
.Y(n2654) );
AO22XLTS U4230 ( .A0(d_ff_Yn[17]), .A1(n6221), .B0(d_ff2_Y[17]), .B1(n6231),
.Y(n2699) );
AO22XLTS U4231 ( .A0(d_ff_Yn[30]), .A1(n6274), .B0(d_ff2_Y[30]), .B1(n6259),
.Y(n2660) );
AO22XLTS U4232 ( .A0(d_ff_Yn[15]), .A1(n6221), .B0(d_ff2_Y[15]), .B1(n6231),
.Y(n2705) );
AO22XLTS U4233 ( .A0(d_ff_Yn[31]), .A1(n6274), .B0(d_ff2_Y[31]), .B1(n6259),
.Y(n2657) );
AO22XLTS U4234 ( .A0(d_ff_Yn[28]), .A1(n6253), .B0(d_ff2_Y[28]), .B1(n6259),
.Y(n2666) );
AO22XLTS U4235 ( .A0(d_ff_Yn[41]), .A1(n6286), .B0(d_ff2_Y[41]), .B1(n6281),
.Y(n2627) );
AO22XLTS U4236 ( .A0(d_ff_Yn[39]), .A1(n6286), .B0(d_ff2_Y[39]), .B1(n6281),
.Y(n2633) );
AO22XLTS U4237 ( .A0(d_ff_Yn[43]), .A1(n6286), .B0(d_ff2_Y[43]), .B1(n6289),
.Y(n2621) );
AO22XLTS U4238 ( .A0(d_ff_Yn[46]), .A1(n6286), .B0(d_ff2_Y[46]), .B1(n6289),
.Y(n2612) );
AO22XLTS U4239 ( .A0(d_ff_Yn[45]), .A1(n6286), .B0(d_ff2_Y[45]), .B1(n6289),
.Y(n2615) );
AO22XLTS U4240 ( .A0(d_ff_Yn[34]), .A1(n6274), .B0(d_ff2_Y[34]), .B1(n6281),
.Y(n2648) );
AO22XLTS U4241 ( .A0(d_ff_Yn[3]), .A1(n6191), .B0(d_ff2_Y[3]), .B1(n6463),
.Y(n2741) );
AO22XLTS U4242 ( .A0(d_ff_Xn[44]), .A1(n6147), .B0(d_ff2_X[44]), .B1(n6463),
.Y(n2793) );
AO22XLTS U4243 ( .A0(d_ff_Yn[48]), .A1(n6291), .B0(d_ff2_Y[48]), .B1(n6289),
.Y(n2606) );
AO22XLTS U4244 ( .A0(n3936), .A1(d_ff_Yn[63]), .B0(d_ff2_Y[63]), .B1(n6463),
.Y(n2344) );
AO22XLTS U4245 ( .A0(n6330), .A1(result_add_subt[62]), .B0(n6461), .B1(
d_ff_Yn[62]), .Y(n2346) );
AO22XLTS U4246 ( .A0(n6462), .A1(result_add_subt[57]), .B0(n6327), .B1(
d_ff_Xn[57]), .Y(n2488) );
AO22XLTS U4247 ( .A0(n6466), .A1(result_add_subt[56]), .B0(n6023), .B1(
d_ff_Xn[56]), .Y(n2491) );
AO22XLTS U4248 ( .A0(n6466), .A1(result_add_subt[55]), .B0(n6023), .B1(
d_ff_Xn[55]), .Y(n2494) );
AO22XLTS U4249 ( .A0(n6466), .A1(result_add_subt[53]), .B0(n6023), .B1(
d_ff_Xn[53]), .Y(n2500) );
MX2X1TS U4250 ( .A(result_add_subt[52]), .B(d_ff_Yn[52]), .S0(n6326), .Y(
n2504) );
MX2X1TS U4251 ( .A(result_add_subt[58]), .B(d_ff_Yn[58]), .S0(n6326), .Y(
n2486) );
MX2X1TS U4252 ( .A(result_add_subt[59]), .B(d_ff_Yn[59]), .S0(n6326), .Y(
n2483) );
MX2X1TS U4253 ( .A(result_add_subt[54]), .B(d_ff_Yn[54]), .S0(n6326), .Y(
n2498) );
MX2X1TS U4254 ( .A(result_add_subt[47]), .B(d_ff_Yn[47]), .S0(n6036), .Y(
n2895) );
MX2X1TS U4255 ( .A(result_add_subt[50]), .B(d_ff_Yn[50]), .S0(n6326), .Y(
n2886) );
MX2X1TS U4256 ( .A(result_add_subt[48]), .B(d_ff_Yn[48]), .S0(n6036), .Y(
n2892) );
MX2X1TS U4257 ( .A(result_add_subt[49]), .B(d_ff_Yn[49]), .S0(n6036), .Y(
n2889) );
MX2X1TS U4258 ( .A(result_add_subt[44]), .B(d_ff_Yn[44]), .S0(n6036), .Y(
n2904) );
MX2X1TS U4259 ( .A(result_add_subt[33]), .B(d_ff_Yn[33]), .S0(n6035), .Y(
n2937) );
MX2X1TS U4260 ( .A(result_add_subt[34]), .B(d_ff_Yn[34]), .S0(n6035), .Y(
n2934) );
MX2X1TS U4261 ( .A(result_add_subt[3]), .B(d_ff_Yn[3]), .S0(n6032), .Y(n3027) );
MX2X1TS U4262 ( .A(result_add_subt[46]), .B(d_ff_Yn[46]), .S0(n6036), .Y(
n2898) );
MX2X1TS U4263 ( .A(result_add_subt[45]), .B(d_ff_Yn[45]), .S0(n6036), .Y(
n2901) );
MX2X1TS U4264 ( .A(result_add_subt[42]), .B(d_ff_Yn[42]), .S0(n6036), .Y(
n2910) );
MX2X1TS U4265 ( .A(result_add_subt[35]), .B(d_ff_Yn[35]), .S0(n6035), .Y(
n2931) );
MX2X1TS U4266 ( .A(result_add_subt[36]), .B(d_ff_Yn[36]), .S0(n6035), .Y(
n2928) );
MX2X1TS U4267 ( .A(result_add_subt[43]), .B(d_ff_Yn[43]), .S0(n6036), .Y(
n2907) );
MX2X1TS U4268 ( .A(result_add_subt[41]), .B(d_ff_Yn[41]), .S0(n6036), .Y(
n2913) );
MX2X1TS U4269 ( .A(result_add_subt[39]), .B(d_ff_Yn[39]), .S0(n6035), .Y(
n2919) );
MX2X1TS U4270 ( .A(result_add_subt[40]), .B(d_ff_Yn[40]), .S0(n6036), .Y(
n2916) );
MX2X1TS U4271 ( .A(result_add_subt[38]), .B(d_ff_Yn[38]), .S0(n6035), .Y(
n2922) );
MX2X1TS U4272 ( .A(result_add_subt[28]), .B(d_ff_Yn[28]), .S0(n6034), .Y(
n2952) );
MX2X1TS U4273 ( .A(result_add_subt[37]), .B(d_ff_Yn[37]), .S0(n6035), .Y(
n2925) );
MX2X1TS U4274 ( .A(result_add_subt[12]), .B(d_ff_Yn[12]), .S0(n6033), .Y(
n3000) );
MX2X1TS U4275 ( .A(result_add_subt[31]), .B(d_ff_Yn[31]), .S0(n6035), .Y(
n2943) );
MX2X1TS U4276 ( .A(result_add_subt[30]), .B(d_ff_Yn[30]), .S0(n6035), .Y(
n2946) );
MX2X1TS U4277 ( .A(result_add_subt[15]), .B(d_ff_Yn[15]), .S0(n6033), .Y(
n2991) );
MX2X1TS U4278 ( .A(result_add_subt[32]), .B(d_ff_Yn[32]), .S0(n6035), .Y(
n2940) );
MX2X1TS U4279 ( .A(result_add_subt[17]), .B(d_ff_Yn[17]), .S0(n6033), .Y(
n2985) );
MX2X1TS U4280 ( .A(result_add_subt[29]), .B(d_ff_Yn[29]), .S0(n6034), .Y(
n2949) );
MX2X1TS U4281 ( .A(result_add_subt[14]), .B(d_ff_Yn[14]), .S0(n6033), .Y(
n2994) );
MX2X1TS U4282 ( .A(result_add_subt[18]), .B(d_ff_Yn[18]), .S0(n6033), .Y(
n2982) );
MX2X1TS U4283 ( .A(result_add_subt[13]), .B(d_ff_Yn[13]), .S0(n6033), .Y(
n2997) );
MX2X1TS U4284 ( .A(result_add_subt[10]), .B(d_ff_Yn[10]), .S0(n6033), .Y(
n3006) );
MX2X1TS U4285 ( .A(result_add_subt[16]), .B(d_ff_Yn[16]), .S0(n6033), .Y(
n2988) );
MX2X1TS U4286 ( .A(result_add_subt[5]), .B(d_ff_Yn[5]), .S0(n6032), .Y(n3021) );
MX2X1TS U4287 ( .A(result_add_subt[6]), .B(d_ff_Yn[6]), .S0(n6032), .Y(n3018) );
MX2X1TS U4288 ( .A(result_add_subt[8]), .B(d_ff_Yn[8]), .S0(n6032), .Y(n3012) );
MX2X1TS U4289 ( .A(result_add_subt[20]), .B(d_ff_Yn[20]), .S0(n6034), .Y(
n2976) );
MX2X1TS U4290 ( .A(result_add_subt[9]), .B(d_ff_Yn[9]), .S0(n6032), .Y(n3009) );
MX2X1TS U4291 ( .A(result_add_subt[21]), .B(d_ff_Yn[21]), .S0(n6034), .Y(
n2973) );
MX2X1TS U4292 ( .A(result_add_subt[22]), .B(d_ff_Yn[22]), .S0(n6034), .Y(
n2970) );
MX2X1TS U4293 ( .A(result_add_subt[11]), .B(d_ff_Yn[11]), .S0(n6033), .Y(
n3003) );
MX2X1TS U4294 ( .A(result_add_subt[27]), .B(d_ff_Yn[27]), .S0(n6034), .Y(
n2955) );
MX2X1TS U4295 ( .A(result_add_subt[26]), .B(d_ff_Yn[26]), .S0(n6034), .Y(
n2958) );
MX2X1TS U4296 ( .A(result_add_subt[24]), .B(d_ff_Yn[24]), .S0(n6034), .Y(
n2964) );
MX2X1TS U4297 ( .A(result_add_subt[23]), .B(d_ff_Yn[23]), .S0(n6034), .Y(
n2967) );
MX2X1TS U4298 ( .A(result_add_subt[4]), .B(d_ff_Yn[4]), .S0(n6032), .Y(n3024) );
MX2X1TS U4299 ( .A(result_add_subt[25]), .B(d_ff_Yn[25]), .S0(n6034), .Y(
n2961) );
MX2X1TS U4300 ( .A(result_add_subt[1]), .B(d_ff_Yn[1]), .S0(n6032), .Y(n3033) );
MX2X1TS U4301 ( .A(result_add_subt[2]), .B(d_ff_Yn[2]), .S0(n6032), .Y(n3030) );
MX2X1TS U4302 ( .A(result_add_subt[0]), .B(d_ff_Yn[0]), .S0(n6032), .Y(n3036) );
MX2X1TS U4303 ( .A(result_add_subt[19]), .B(d_ff_Yn[19]), .S0(n6033), .Y(
n2979) );
MX2X1TS U4304 ( .A(result_add_subt[50]), .B(d_ff_Xn[50]), .S0(n6327), .Y(
n2885) );
MX2X1TS U4305 ( .A(result_add_subt[52]), .B(d_ff_Xn[52]), .S0(n6465), .Y(
n2503) );
MX2X1TS U4306 ( .A(result_add_subt[33]), .B(d_ff_Xn[33]), .S0(n6022), .Y(
n2936) );
MX2X1TS U4307 ( .A(result_add_subt[47]), .B(d_ff_Xn[47]), .S0(n6465), .Y(
n2894) );
MX2X1TS U4308 ( .A(result_add_subt[38]), .B(d_ff_Xn[38]), .S0(n6022), .Y(
n2921) );
MX2X1TS U4309 ( .A(result_add_subt[44]), .B(d_ff_Xn[44]), .S0(n6327), .Y(
n2903) );
MX2X1TS U4310 ( .A(result_add_subt[37]), .B(d_ff_Xn[37]), .S0(n6022), .Y(
n2924) );
MX2X1TS U4311 ( .A(result_add_subt[40]), .B(d_ff_Xn[40]), .S0(n6023), .Y(
n2915) );
MX2X1TS U4312 ( .A(result_add_subt[15]), .B(d_ff_Xn[15]), .S0(n6018), .Y(
n2990) );
MX2X1TS U4313 ( .A(result_add_subt[12]), .B(d_ff_Xn[12]), .S0(n6018), .Y(
n2999) );
MX2X1TS U4314 ( .A(result_add_subt[17]), .B(d_ff_Xn[17]), .S0(n6018), .Y(
n2984) );
MX2X1TS U4315 ( .A(result_add_subt[30]), .B(d_ff_Xn[30]), .S0(n6022), .Y(
n2945) );
MX2X1TS U4316 ( .A(result_add_subt[16]), .B(d_ff_Xn[16]), .S0(n6018), .Y(
n2987) );
MX2X1TS U4317 ( .A(result_add_subt[18]), .B(d_ff_Xn[18]), .S0(n6018), .Y(
n2981) );
MX2X1TS U4318 ( .A(result_add_subt[5]), .B(d_ff_Xn[5]), .S0(n6017), .Y(n3020) );
MX2X1TS U4319 ( .A(result_add_subt[10]), .B(d_ff_Xn[10]), .S0(n6018), .Y(
n3005) );
MX2X1TS U4320 ( .A(result_add_subt[21]), .B(d_ff_Xn[21]), .S0(n6021), .Y(
n2972) );
MX2X1TS U4321 ( .A(result_add_subt[20]), .B(d_ff_Xn[20]), .S0(n6021), .Y(
n2975) );
MX2X1TS U4322 ( .A(result_add_subt[27]), .B(d_ff_Xn[27]), .S0(n6021), .Y(
n2954) );
MX2X1TS U4323 ( .A(result_add_subt[22]), .B(d_ff_Xn[22]), .S0(n6021), .Y(
n2969) );
MX2X1TS U4324 ( .A(result_add_subt[25]), .B(d_ff_Xn[25]), .S0(n6021), .Y(
n2960) );
MX2X1TS U4325 ( .A(result_add_subt[23]), .B(d_ff_Xn[23]), .S0(n6021), .Y(
n2966) );
MX2X1TS U4326 ( .A(result_add_subt[2]), .B(d_ff_Xn[2]), .S0(n6017), .Y(n3029) );
MX2X1TS U4327 ( .A(result_add_subt[4]), .B(d_ff_Xn[4]), .S0(n6017), .Y(n3023) );
MX2X1TS U4328 ( .A(result_add_subt[54]), .B(d_ff_Xn[54]), .S0(n6327), .Y(
n2497) );
MX2X1TS U4329 ( .A(result_add_subt[1]), .B(d_ff_Xn[1]), .S0(n6017), .Y(n3032) );
MX2X1TS U4330 ( .A(result_add_subt[59]), .B(d_ff_Xn[59]), .S0(n6327), .Y(
n2482) );
MX2X1TS U4331 ( .A(result_add_subt[48]), .B(d_ff_Xn[48]), .S0(n6327), .Y(
n2891) );
MX2X1TS U4332 ( .A(result_add_subt[49]), .B(d_ff_Xn[49]), .S0(n6465), .Y(
n2888) );
MX2X1TS U4333 ( .A(result_add_subt[34]), .B(d_ff_Xn[34]), .S0(n6022), .Y(
n2933) );
MX2X1TS U4334 ( .A(result_add_subt[3]), .B(d_ff_Xn[3]), .S0(n6017), .Y(n3026) );
MX2X1TS U4335 ( .A(result_add_subt[46]), .B(d_ff_Xn[46]), .S0(n6465), .Y(
n2897) );
MX2X1TS U4336 ( .A(result_add_subt[45]), .B(d_ff_Xn[45]), .S0(n6327), .Y(
n2900) );
MX2X1TS U4337 ( .A(result_add_subt[42]), .B(d_ff_Xn[42]), .S0(n6023), .Y(
n2909) );
MX2X1TS U4338 ( .A(result_add_subt[35]), .B(d_ff_Xn[35]), .S0(n6022), .Y(
n2930) );
MX2X1TS U4339 ( .A(result_add_subt[36]), .B(d_ff_Xn[36]), .S0(n6022), .Y(
n2927) );
MX2X1TS U4340 ( .A(result_add_subt[43]), .B(d_ff_Xn[43]), .S0(n6327), .Y(
n2906) );
MX2X1TS U4341 ( .A(result_add_subt[41]), .B(d_ff_Xn[41]), .S0(n6023), .Y(
n2912) );
MX2X1TS U4342 ( .A(result_add_subt[39]), .B(d_ff_Xn[39]), .S0(n6022), .Y(
n2918) );
MX2X1TS U4343 ( .A(result_add_subt[31]), .B(d_ff_Xn[31]), .S0(n6022), .Y(
n2942) );
MX2X1TS U4344 ( .A(result_add_subt[28]), .B(d_ff_Xn[28]), .S0(n6021), .Y(
n2951) );
MX2X1TS U4345 ( .A(result_add_subt[14]), .B(d_ff_Xn[14]), .S0(n6018), .Y(
n2993) );
MX2X1TS U4346 ( .A(result_add_subt[32]), .B(d_ff_Xn[32]), .S0(n6022), .Y(
n2939) );
MX2X1TS U4347 ( .A(result_add_subt[13]), .B(d_ff_Xn[13]), .S0(n6018), .Y(
n2996) );
MX2X1TS U4348 ( .A(result_add_subt[29]), .B(d_ff_Xn[29]), .S0(n6021), .Y(
n2948) );
MX2X1TS U4349 ( .A(result_add_subt[7]), .B(d_ff_Xn[7]), .S0(n6017), .Y(n3014) );
MX2X1TS U4350 ( .A(result_add_subt[19]), .B(d_ff_Xn[19]), .S0(n6018), .Y(
n2978) );
MX2X1TS U4351 ( .A(result_add_subt[8]), .B(d_ff_Xn[8]), .S0(n6017), .Y(n3011) );
MX2X1TS U4352 ( .A(result_add_subt[6]), .B(d_ff_Xn[6]), .S0(n6017), .Y(n3017) );
MX2X1TS U4353 ( .A(result_add_subt[11]), .B(d_ff_Xn[11]), .S0(n6018), .Y(
n3002) );
MX2X1TS U4354 ( .A(result_add_subt[9]), .B(d_ff_Xn[9]), .S0(n6017), .Y(n3008) );
MX2X1TS U4355 ( .A(result_add_subt[24]), .B(d_ff_Xn[24]), .S0(n6021), .Y(
n2963) );
MX2X1TS U4356 ( .A(result_add_subt[26]), .B(d_ff_Xn[26]), .S0(n6021), .Y(
n2957) );
MX2X1TS U4357 ( .A(result_add_subt[0]), .B(d_ff_Xn[0]), .S0(n6017), .Y(n3035) );
MX2X1TS U4358 ( .A(result_add_subt[58]), .B(d_ff_Xn[58]), .S0(n6465), .Y(
n2485) );
AO22XLTS U4359 ( .A0(d_ff_Yn[54]), .A1(n6291), .B0(d_ff2_Y[54]), .B1(n6294),
.Y(n2592) );
MX2X1TS U4360 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[46]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[46]), .S0(n6575), .Y(n2149)
);
MX2X1TS U4361 ( .A(intadd_44_SUM_2_), .B(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]), .S0(n6593), .Y(
n2273) );
MX2X1TS U4362 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]), .S0(n5451), .Y(n2009)
);
MX2X1TS U4363 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]), .S0(n5453), .Y(n2002)
);
MX2X1TS U4364 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]), .S0(n5451), .Y(n1924)
);
MX2X1TS U4365 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[32]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[32]), .S0(n6474), .Y(n1844)
);
NAND4XLTS U4366 ( .A(n6097), .B(n6096), .C(n6095), .D(n6094), .Y(n3126) );
NAND3XLTS U4367 ( .A(cont_iter_out[2]), .B(n6093), .C(n3212), .Y(n6096) );
AOI2BB2XLTS U4368 ( .B0(d_ff3_LUT_out[15]), .B1(n6092), .A0N(n6105), .A1N(
n6091), .Y(n6097) );
NAND2BXLTS U4369 ( .AN(d_ff3_LUT_out[48]), .B(n6217), .Y(n3152) );
MX2X1TS U4370 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[15]), .S0(n5459), .Y(n1831)
);
AO22XLTS U4371 ( .A0(d_ff_Yn[50]), .A1(n6291), .B0(d_ff2_Y[50]), .B1(n6289),
.Y(n2600) );
AO22XLTS U4372 ( .A0(d_ff_Yn[47]), .A1(n6286), .B0(d_ff2_Y[47]), .B1(n6289),
.Y(n2609) );
AO22XLTS U4373 ( .A0(d_ff_Xn[33]), .A1(n6191), .B0(d_ff2_X[33]), .B1(n6200),
.Y(n2815) );
AO22XLTS U4374 ( .A0(d_ff_Yn[42]), .A1(n6286), .B0(d_ff2_Y[42]), .B1(n6281),
.Y(n2624) );
AO22XLTS U4375 ( .A0(d_ff_Xn[38]), .A1(n6147), .B0(d_ff2_X[38]), .B1(n6180),
.Y(n2805) );
AO22XLTS U4376 ( .A0(d_ff_Yn[40]), .A1(n6286), .B0(d_ff2_Y[40]), .B1(n6281),
.Y(n2630) );
AO22XLTS U4377 ( .A0(d_ff_Yn[37]), .A1(n6274), .B0(d_ff2_Y[37]), .B1(n6281),
.Y(n2639) );
AO22XLTS U4378 ( .A0(d_ff_Yn[12]), .A1(n6221), .B0(d_ff2_Y[12]), .B1(n6235),
.Y(n2714) );
AO22XLTS U4379 ( .A0(d_ff_Yn[14]), .A1(n6221), .B0(d_ff2_Y[14]), .B1(n6231),
.Y(n2708) );
AO22XLTS U4380 ( .A0(d_ff_Xn[10]), .A1(n6292), .B0(d_ff2_X[10]), .B1(n6180),
.Y(n2861) );
AO22XLTS U4381 ( .A0(d_ff_Yn[7]), .A1(n6191), .B0(d_ff2_Y[7]), .B1(n6289),
.Y(n2729) );
AO22XLTS U4382 ( .A0(d_ff_Yn[5]), .A1(n6253), .B0(d_ff2_Y[5]), .B1(n6200),
.Y(n2735) );
AO22XLTS U4383 ( .A0(d_ff_Yn[9]), .A1(n6221), .B0(d_ff2_Y[9]), .B1(n6235),
.Y(n2723) );
AO22XLTS U4384 ( .A0(d_ff_Yn[22]), .A1(n6253), .B0(d_ff2_Y[22]), .B1(n6231),
.Y(n2684) );
AO22XLTS U4385 ( .A0(d_ff_Yn[27]), .A1(n6253), .B0(d_ff2_Y[27]), .B1(n6259),
.Y(n2669) );
AO22XLTS U4386 ( .A0(d_ff_Xn[1]), .A1(n6291), .B0(d_ff2_X[1]), .B1(n6294),
.Y(n2879) );
AO22XLTS U4387 ( .A0(n6466), .A1(result_add_subt[63]), .B0(n6465), .B1(
d_ff_Xn[63]), .Y(n2341) );
AO22XLTS U4388 ( .A0(d_ff_Xn[50]), .A1(n6147), .B0(d_ff2_X[50]), .B1(n6235),
.Y(n2781) );
AO22XLTS U4389 ( .A0(d_ff_Xn[47]), .A1(n6147), .B0(d_ff2_X[47]), .B1(n6235),
.Y(n2787) );
AO22XLTS U4390 ( .A0(d_ff_Yn[49]), .A1(n6291), .B0(d_ff2_Y[49]), .B1(n6289),
.Y(n2603) );
AO22XLTS U4391 ( .A0(d_ff_Yn[33]), .A1(n6274), .B0(d_ff2_Y[33]), .B1(n6281),
.Y(n2651) );
AO22XLTS U4392 ( .A0(d_ff_Yn[44]), .A1(n6286), .B0(d_ff2_Y[44]), .B1(n6289),
.Y(n2618) );
AO22XLTS U4393 ( .A0(d_ff_Yn[35]), .A1(n6286), .B0(d_ff2_Y[35]), .B1(n6281),
.Y(n2645) );
AO22XLTS U4394 ( .A0(d_ff_Yn[36]), .A1(n6274), .B0(d_ff2_Y[36]), .B1(n6281),
.Y(n2642) );
AO22XLTS U4395 ( .A0(d_ff_Yn[38]), .A1(n6274), .B0(d_ff2_Y[38]), .B1(n6281),
.Y(n2636) );
AO22XLTS U4396 ( .A0(d_ff_Xn[40]), .A1(n6147), .B0(d_ff2_X[40]), .B1(n6235),
.Y(n2801) );
AO22XLTS U4397 ( .A0(d_ff_Xn[37]), .A1(n6147), .B0(d_ff2_X[37]), .B1(n6200),
.Y(n2807) );
AO22XLTS U4398 ( .A0(d_ff_Xn[12]), .A1(n6138), .B0(d_ff2_X[12]), .B1(n6200),
.Y(n2857) );
AO22XLTS U4399 ( .A0(d_ff_Xn[15]), .A1(n6138), .B0(d_ff2_X[15]), .B1(n6200),
.Y(n2851) );
AO22XLTS U4400 ( .A0(d_ff_Xn[30]), .A1(n6147), .B0(d_ff2_X[30]), .B1(n6180),
.Y(n2821) );
AO22XLTS U4401 ( .A0(d_ff_Xn[17]), .A1(n6138), .B0(d_ff2_X[17]), .B1(n6463),
.Y(n2847) );
AO22XLTS U4402 ( .A0(d_ff_Yn[29]), .A1(n6274), .B0(d_ff2_Y[29]), .B1(n6259),
.Y(n2663) );
AO22XLTS U4403 ( .A0(d_ff_Xn[18]), .A1(n6138), .B0(d_ff2_X[18]), .B1(n6200),
.Y(n2845) );
AO22XLTS U4404 ( .A0(d_ff_Xn[16]), .A1(n6138), .B0(d_ff2_X[16]), .B1(n6463),
.Y(n2849) );
AO22XLTS U4405 ( .A0(d_ff_Yn[10]), .A1(n6221), .B0(d_ff2_Y[10]), .B1(n6235),
.Y(n2720) );
AO22XLTS U4406 ( .A0(d_ff_Xn[5]), .A1(n6292), .B0(d_ff2_X[5]), .B1(n6180),
.Y(n2871) );
AO22XLTS U4407 ( .A0(d_ff_Xn[20]), .A1(n6138), .B0(d_ff2_X[20]), .B1(n6180),
.Y(n2841) );
AO22XLTS U4408 ( .A0(d_ff_Xn[21]), .A1(n6138), .B0(d_ff2_X[21]), .B1(n6180),
.Y(n2839) );
AO22XLTS U4409 ( .A0(d_ff_Xn[22]), .A1(n6138), .B0(d_ff2_X[22]), .B1(n6180),
.Y(n2837) );
AO22XLTS U4410 ( .A0(d_ff_Xn[27]), .A1(n6147), .B0(d_ff2_X[27]), .B1(n6200),
.Y(n2827) );
AO22XLTS U4411 ( .A0(d_ff_Xn[23]), .A1(n6138), .B0(d_ff2_X[23]), .B1(n6180),
.Y(n2835) );
AO22XLTS U4412 ( .A0(d_ff_Yn[24]), .A1(n6253), .B0(d_ff2_Y[24]), .B1(n6259),
.Y(n2678) );
AO22XLTS U4413 ( .A0(d_ff_Xn[25]), .A1(n6138), .B0(d_ff2_X[25]), .B1(n6180),
.Y(n2831) );
AO22XLTS U4414 ( .A0(d_ff_Yn[4]), .A1(n6191), .B0(d_ff2_Y[4]), .B1(n6180),
.Y(n2738) );
AO22XLTS U4415 ( .A0(d_ff_Xn[2]), .A1(n3936), .B0(d_ff2_X[2]), .B1(n6200),
.Y(n2877) );
AO22XLTS U4416 ( .A0(d_ff_Yn[1]), .A1(n6191), .B0(d_ff2_Y[1]), .B1(n6235),
.Y(n2747) );
AO22XLTS U4417 ( .A0(d_ff_Yn[0]), .A1(n6191), .B0(d_ff2_Y[0]), .B1(n6463),
.Y(n2750) );
AO22XLTS U4418 ( .A0(n6009), .A1(n6008), .B0(
inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM), .B1(n6579), .Y(n2082) );
OR2X1TS U4419 ( .A(n6007), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[54]), .Y(n6009) );
XOR2XLTS U4420 ( .A(n5518), .B(n5517), .Y(n5523) );
OAI222X1TS U4421 ( .A0(n5427), .A1(n5444), .B0(n5425), .B1(n5442), .C0(n6810), .C1(n5452), .Y(n1733) );
AO22XLTS U4422 ( .A0(d_ff_Yn[53]), .A1(n6291), .B0(d_ff2_Y[53]), .B1(n6294),
.Y(n2593) );
AO22XLTS U4423 ( .A0(d_ff_Yn[55]), .A1(n6291), .B0(d_ff2_Y[55]), .B1(n6294),
.Y(n2591) );
XOR2XLTS U4424 ( .A(n5564), .B(n5563), .Y(n5572) );
MX2X1TS U4425 ( .A(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .B(
inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2), .S0(n5454), .Y(n2083) );
MX2X1TS U4426 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[10]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[10]), .S0(n6010), .Y(n2192)
);
MX2X1TS U4427 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n6011), .Y(n2232)
);
MX2X1TS U4428 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]), .S0(n6011), .Y(n2227)
);
MX2X1TS U4429 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]), .S0(n6011), .Y(n2217)
);
MX2X1TS U4430 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n6010), .Y(n2207)
);
MX2X1TS U4431 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[9]), .S0(n6010), .Y(n2197)
);
AO22XLTS U4432 ( .A0(n6050), .A1(n6043), .B0(result_add_subt[62]), .B1(n4691), .Y(n2258) );
AO22XLTS U4433 ( .A0(n6020), .A1(n6019), .B0(result_add_subt[25]), .B1(n4691), .Y(n1922) );
MX2X1TS U4434 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]), .S0(n6011), .Y(n2222)
);
MX2X1TS U4435 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]), .S0(n6011), .Y(n2212)
);
MX2X1TS U4436 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[8]), .S0(n6010), .Y(n2202)
);
XOR2XLTS U4437 ( .A(n5959), .B(n5952), .Y(n5956) );
MX2X1TS U4438 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[43]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[43]), .S0(n3210), .Y(n1791)
);
MX2X1TS U4439 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[51]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[51]), .S0(n3210), .Y(n1739)
);
MX2X1TS U4440 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[44]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[44]), .S0(n5452), .Y(n1763)
);
MX2X1TS U4441 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[45]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[45]), .S0(n5454), .Y(n1775)
);
MX2X1TS U4442 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[49]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[49]), .S0(n3210), .Y(n1751)
);
MX2X1TS U4443 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[47]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[47]), .S0(n5449), .Y(n1747)
);
MX2X1TS U4444 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[46]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[46]), .S0(n5450), .Y(n1779)
);
MX2X1TS U4445 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[48]), .S0(n5452), .Y(n1755)
);
MX2X1TS U4446 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[50]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[50]), .S0(n5449), .Y(n1743)
);
MX2X1TS U4447 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[4]), .S0(n5454), .Y(n1889)
);
MX2X1TS U4448 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[40]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[40]), .S0(n5454), .Y(n1811)
);
MX2X1TS U4449 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[38]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[38]), .S0(n5449), .Y(n1807)
);
MX2X1TS U4450 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[36]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[36]), .S0(n3210), .Y(n1795)
);
MX2X1TS U4451 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[34]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[34]), .S0(n5450), .Y(n1771)
);
AOI22X1TS U4452 ( .A0(n5343), .A1(n5331), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .B1(n5305), .Y(n5338)
);
AOI22X1TS U4453 ( .A0(n5263), .A1(n5106), .B0(n5256), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .Y(n5092) );
AOI22X1TS U4454 ( .A0(n5317), .A1(n5198), .B0(n5216), .B1(n5230), .Y(n5200)
);
MX2X1TS U4455 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[19]), .S0(n3210), .Y(n2015)
);
MX2X1TS U4456 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[20]), .S0(n5459), .Y(n1970)
);
MX2X1TS U4457 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[21]), .S0(n3211), .Y(n1960)
);
MX2X1TS U4458 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[9]), .S0(n5449), .Y(n1953)
);
MX2X1TS U4459 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[22]), .S0(n5449), .Y(n1943)
);
MX2X1TS U4460 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[25]), .S0(n5449), .Y(n1916)
);
MX2X1TS U4461 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[27]), .S0(n5452), .Y(n1912)
);
MX2X1TS U4462 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[26]), .S0(n5452), .Y(n1908)
);
MX2X1TS U4463 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[29]), .S0(n5454), .Y(n1851)
);
MX2X1TS U4464 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[14]), .S0(n5450), .Y(n1847)
);
MX2X1TS U4465 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[17]), .S0(n5449), .Y(n1839)
);
MX2X1TS U4466 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[30]), .S0(n5450), .Y(n1835)
);
MX2X1TS U4467 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[31]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[31]), .S0(n5459), .Y(n1823)
);
MX2X1TS U4468 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[28]), .S0(n5459), .Y(n1819)
);
MX2X1TS U4469 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[37]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[37]), .S0(n5450), .Y(n1815)
);
MX2X1TS U4470 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[41]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[41]), .S0(n3211), .Y(n1803)
);
MX2X1TS U4471 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[39]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[39]), .S0(n5454), .Y(n1799)
);
MX2X1TS U4472 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[42]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[42]), .S0(n5452), .Y(n1787)
);
MX2X1TS U4473 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[35]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[35]), .S0(n5450), .Y(n1783)
);
MX2X1TS U4474 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[33]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[33]), .S0(n3210), .Y(n1759)
);
XOR2XLTS U4475 ( .A(n5859), .B(n5858), .Y(n5868) );
MX2X1TS U4476 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[23]), .S0(n5452), .Y(n1930)
);
XOR2XLTS U4477 ( .A(n5929), .B(n5928), .Y(n5935) );
OAI222X1TS U4478 ( .A0(n5434), .A1(n5378), .B0(n6817), .B1(n5433), .C0(n5425), .C1(n5377), .Y(n1684) );
AOI2BB2XLTS U4479 ( .B0(n6151), .B1(n6737), .A0N(n3231), .A1N(n6194), .Y(
n2769) );
OAI222X1TS U4480 ( .A0(n3245), .A1(n5401), .B0(n5443), .B1(n5400), .C0(n6768), .C1(n3211), .Y(n1698) );
AOI222X1TS U4481 ( .A0(n4236), .A1(data_output[7]), .B0(n4235), .B1(
d_ff_Yn[7]), .C0(n4234), .C1(d_ff_Xn[7]), .Y(n4221) );
OAI2BB1X1TS U4482 ( .A0N(n5703), .A1N(n3596), .B0(n3595), .Y(n2034) );
XOR2XLTS U4483 ( .A(n3618), .B(n3552), .Y(n3596) );
MX2X1TS U4484 ( .A(n6015), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[1]), .S0(n6559), .Y(
n2182) );
AOI22X1TS U4485 ( .A0(n5263), .A1(n5331), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .B1(n3942), .Y(n5019)
);
XOR2XLTS U4486 ( .A(n5694), .B(n5693), .Y(n5701) );
XOR2XLTS U4487 ( .A(n5499), .B(n5498), .Y(n5504) );
XOR2XLTS U4488 ( .A(n3666), .B(n3668), .Y(n3672) );
XOR2XLTS U4489 ( .A(n5846), .B(n5845), .Y(n5854) );
XOR2XLTS U4490 ( .A(n5772), .B(n5465), .Y(n5472) );
XOR2XLTS U4491 ( .A(n5791), .B(n5790), .Y(n5796) );
XOR2XLTS U4492 ( .A(n5885), .B(n5884), .Y(n5894) );
OAI222X1TS U4493 ( .A0(n5425), .A1(n5437), .B0(n5420), .B1(n5436), .C0(n6815), .C1(n6578), .Y(n1690) );
OAI222X1TS U4494 ( .A0(n5440), .A1(n5389), .B0(n5420), .B1(n5388), .C0(n6791), .C1(n5422), .Y(n1694) );
OAI222X1TS U4495 ( .A0(n3245), .A1(n5384), .B0(n5420), .B1(n5383), .C0(n6816), .C1(n5433), .Y(n1692) );
OAI222X1TS U4496 ( .A0(n5397), .A1(n5382), .B0(n5420), .B1(n5381), .C0(n6813), .C1(n5452), .Y(n1686) );
OAI222X1TS U4497 ( .A0(n5434), .A1(n5429), .B0(n5423), .B1(n5428), .C0(n6780), .C1(n6578), .Y(n1722) );
XOR2XLTS U4498 ( .A(n5914), .B(n5913), .Y(n5921) );
OAI222X1TS U4499 ( .A0(n5435), .A1(n5391), .B0(n5420), .B1(n5390), .C0(n6792), .C1(n6478), .Y(n1695) );
OAI222X1TS U4500 ( .A0(n5427), .A1(n5401), .B0(n5440), .B1(n5400), .C0(n6781), .C1(n5422), .Y(n1724) );
OAI222X1TS U4501 ( .A0(n5434), .A1(n5399), .B0(n5435), .B1(n5398), .C0(n6805), .C1(n6478), .Y(n1723) );
OAI222X1TS U4502 ( .A0(n5425), .A1(n5393), .B0(n5420), .B1(n5392), .C0(n6767), .C1(n6578), .Y(n1696) );
OAI222X1TS U4503 ( .A0(n5425), .A1(n5387), .B0(n5420), .B1(n5386), .C0(n6790), .C1(n5433), .Y(n1693) );
AOI2BB2XLTS U4504 ( .B0(n6151), .B1(n6722), .A0N(d_ff_Xn[58]), .A1N(n6149),
.Y(n2771) );
AO22XLTS U4505 ( .A0(d_ff2_Y[58]), .A1(n6293), .B0(d_ff_Yn[58]), .B1(n6292),
.Y(n2588) );
XOR2XLTS U4506 ( .A(n5973), .B(n5972), .Y(n5975) );
CLKAND2X2TS U4507 ( .A(n5971), .B(n5970), .Y(n5973) );
NAND2BXLTS U4508 ( .AN(n6058), .B(n6057), .Y(n3173) );
XOR2XLTS U4509 ( .A(n3683), .B(n3686), .Y(n3691) );
XOR2XLTS U4510 ( .A(n5996), .B(n5995), .Y(n6005) );
XOR2XLTS U4511 ( .A(n5758), .B(n3861), .Y(n3869) );
OAI222X1TS U4512 ( .A0(n5397), .A1(n5429), .B0(n5420), .B1(n5428), .C0(n6769), .C1(n5433), .Y(n1700) );
OAI222X1TS U4513 ( .A0(n5443), .A1(n5421), .B0(n5425), .B1(n5419), .C0(n6802), .C1(n3210), .Y(n1717) );
OAI222X1TS U4514 ( .A0(n5427), .A1(n5417), .B0(n5440), .B1(n5416), .C0(n6801), .C1(n5433), .Y(n1715) );
OAI222X1TS U4515 ( .A0(n5434), .A1(n5415), .B0(n5435), .B1(n5414), .C0(n6800), .C1(n5433), .Y(n1713) );
OAI222X1TS U4516 ( .A0(n5443), .A1(n5405), .B0(n3245), .B1(n5404), .C0(n6775), .C1(n6578), .Y(n1712) );
OAI222X1TS U4517 ( .A0(n5443), .A1(n5396), .B0(n5397), .B1(n5395), .C0(n6778), .C1(n5418), .Y(n1718) );
OAI222X1TS U4518 ( .A0(n5427), .A1(n5411), .B0(n5435), .B1(n5410), .C0(n6777), .C1(n5448), .Y(n1716) );
OAI222X1TS U4519 ( .A0(n3245), .A1(n5403), .B0(n5420), .B1(n5402), .C0(n6793), .C1(n5418), .Y(n1697) );
AO22XLTS U4520 ( .A0(d_ff2_X[52]), .A1(n6235), .B0(d_ff_Xn[52]), .B1(n6292),
.Y(n2777) );
AO22XLTS U4521 ( .A0(d_ff2_Y[52]), .A1(n6293), .B0(d_ff_Yn[52]), .B1(n6292),
.Y(n2594) );
MX2X1TS U4522 ( .A(n6019), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[27]), .S0(n6577), .Y(
n1711) );
OAI31X1TS U4523 ( .A0(n6063), .A1(cont_var_out[1]), .A2(n6642), .B0(n5376),
.Y(n3159) );
MX2X1TS U4524 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1]), .S0(n3211), .Y(n1875)
);
MX2X1TS U4525 ( .A(n5492), .B(n6932), .S0(n6059), .Y(n3284) );
MX2X1TS U4526 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8]), .S0(n5459), .Y(n1900)
);
MX2X1TS U4527 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[18]), .S0(n5459), .Y(n2008)
);
MX2X1TS U4528 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[24]), .S0(n5459), .Y(n1923)
);
MX2X1TS U4529 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[32]), .S0(n5454), .Y(n1843)
);
MX2X1TS U4530 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[16]), .S0(n5450), .Y(n2001)
);
OAI2BB1X1TS U4531 ( .A0N(n5553), .A1N(n3643), .B0(n3642), .Y(n2027) );
XOR2XLTS U4532 ( .A(n5537), .B(n5536), .Y(n5542) );
XOR2XLTS U4533 ( .A(n5819), .B(n5818), .Y(n5825) );
AOI2BB1XLTS U4534 ( .A0N(n6846), .A1N(overflow_flag), .B0(n6050), .Y(n2184)
);
AO22XLTS U4535 ( .A0(n4202), .A1(data_output[63]), .B0(n6472), .B1(n6471),
.Y(n2276) );
AO22XLTS U4536 ( .A0(n3219), .A1(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2), .B0(n4691), .B1(
zero_flag), .Y(n1861) );
XOR2XLTS U4537 ( .A(n5805), .B(n5804), .Y(n5810) );
OAI211XLTS U4538 ( .A0(n5278), .A1(n5285), .B0(n5274), .C0(n5273), .Y(n2518)
);
OAI211XLTS U4539 ( .A0(n5291), .A1(n5285), .B0(n5284), .C0(n5283), .Y(n2521)
);
AOI2BB2XLTS U4540 ( .B0(n6062), .B1(cont_iter_out[2]), .A0N(cont_iter_out[2]), .A1N(n6062), .Y(n3162) );
OAI222X1TS U4541 ( .A0(n5430), .A1(n5377), .B0(n6828), .B1(n5433), .C0(n5440), .C1(n5378), .Y(n1738) );
AO22XLTS U4542 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[51]), .B0(n6595), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[51]), .Y(n1740) );
AO22XLTS U4543 ( .A0(n6594), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[51]), .B0(n6593), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[51]), .Y(n1741) );
OAI21XLTS U4544 ( .A0(n6632), .A1(n3458), .B0(n4303), .Y(n1742) );
AO22XLTS U4545 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[50]), .B0(n6592), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[50]), .Y(n1744) );
AO22XLTS U4546 ( .A0(n6594), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[50]), .B0(n6591), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[50]), .Y(n1745) );
OAI21XLTS U4547 ( .A0(n6633), .A1(n3458), .B0(n4271), .Y(n1746) );
AO22XLTS U4548 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[47]), .B0(n6590), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[47]), .Y(n1748) );
AO22XLTS U4549 ( .A0(n6594), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[47]), .B0(n6763), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[47]), .Y(n1749) );
OAI21XLTS U4550 ( .A0(n6681), .A1(n3458), .B0(n4270), .Y(n1750) );
AO22XLTS U4551 ( .A0(n6589), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[49]), .B0(n6590), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[49]), .Y(n1752) );
AO22XLTS U4552 ( .A0(n6594), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[49]), .B0(n6763), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[49]), .Y(n1753) );
AO22XLTS U4553 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[48]), .B0(n6590), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[48]), .Y(n1756) );
AO22XLTS U4554 ( .A0(n6594), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[48]), .B0(n6588), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[48]), .Y(n1757) );
AO22XLTS U4555 ( .A0(n6594), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[33]), .B0(n6588), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[33]), .Y(n1761) );
AO22XLTS U4556 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[44]), .B0(n6587), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[44]), .Y(n1764) );
AO22XLTS U4557 ( .A0(n6594), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[44]), .B0(n6588), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[44]), .Y(n1765) );
MX2X1TS U4558 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3]), .S0(n5455), .Y(n1768)
);
AO22XLTS U4559 ( .A0(n6594), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3]), .B0(n6588), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1769) );
AO22XLTS U4560 ( .A0(n6594), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[34]), .B0(n6588), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[34]), .Y(n1773) );
AO22XLTS U4561 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[45]), .B0(n6587), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[45]), .Y(n1776) );
AO22XLTS U4562 ( .A0(n6594), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[45]), .B0(n6588), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[45]), .Y(n1777) );
AO22XLTS U4563 ( .A0(n6589), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[46]), .B0(n6587), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[46]), .Y(n1780) );
AO22XLTS U4564 ( .A0(n6585), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[46]), .B0(n6588), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[46]), .Y(n1781) );
AO22XLTS U4565 ( .A0(n6585), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[35]), .B0(n6588), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[35]), .Y(n1785) );
AO22XLTS U4566 ( .A0(n6589), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[42]), .B0(n6587), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[42]), .Y(n1788) );
AO22XLTS U4567 ( .A0(n6585), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[42]), .B0(n6588), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[42]), .Y(n1789) );
AO22XLTS U4568 ( .A0(n6589), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[43]), .B0(n6587), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[43]), .Y(n1792) );
AO22XLTS U4569 ( .A0(n6585), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[43]), .B0(n6588), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[43]), .Y(n1793) );
AO22XLTS U4570 ( .A0(n6585), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[36]), .B0(n6583), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[36]), .Y(n1797) );
AO22XLTS U4571 ( .A0(n6589), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[39]), .B0(n6587), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[39]), .Y(n1800) );
AO22XLTS U4572 ( .A0(n6585), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[39]), .B0(n6583), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[39]), .Y(n1801) );
AO22XLTS U4573 ( .A0(n6589), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[41]), .B0(n6587), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[41]), .Y(n1804) );
AO22XLTS U4574 ( .A0(n6585), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[41]), .B0(n6583), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[41]), .Y(n1805) );
AO22XLTS U4575 ( .A0(n6589), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[38]), .B0(n6587), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[38]), .Y(n1808) );
AO22XLTS U4576 ( .A0(n6585), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[38]), .B0(n6583), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[38]), .Y(n1809) );
AO22XLTS U4577 ( .A0(n6589), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[40]), .B0(n6587), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[40]), .Y(n1812) );
AO22XLTS U4578 ( .A0(n6585), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[40]), .B0(n6583), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[40]), .Y(n1813) );
AO22XLTS U4579 ( .A0(n6589), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[37]), .B0(n6587), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[37]), .Y(n1816) );
AO22XLTS U4580 ( .A0(n6585), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[37]), .B0(n6583), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[37]), .Y(n1817) );
AO22XLTS U4581 ( .A0(n6582), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28]), .B0(n6583), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1821) );
AO22XLTS U4582 ( .A0(n6582), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[31]), .B0(n6583), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[31]), .Y(n1825) );
MX2X1TS U4583 ( .A(n3261), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[12]),
.S0(n3211), .Y(n1827) );
AO22XLTS U4584 ( .A0(n6582), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12]), .B0(n6583), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1829) );
AO22XLTS U4585 ( .A0(n6582), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15]), .B0(n6583), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1833) );
AO22XLTS U4586 ( .A0(n6582), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30]), .B0(n6763), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1837) );
AO22XLTS U4587 ( .A0(n6582), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17]), .B0(n6763), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1841) );
AO22XLTS U4588 ( .A0(n6582), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[32]), .B0(n6763), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[32]), .Y(n1845) );
AO22XLTS U4589 ( .A0(n6582), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14]), .B0(n6763), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1849) );
AO22XLTS U4590 ( .A0(n6582), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29]), .B0(n6593), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1853) );
MX2X1TS U4591 ( .A(n3271), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[13]),
.S0(n3211), .Y(n1855) );
AO22XLTS U4592 ( .A0(n6582), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13]), .B0(n6593), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1857) );
MX2X1TS U4593 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13]), .S0(n5984), .Y(n1859)
);
AO22XLTS U4594 ( .A0(n3216), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG),
.B0(n6579), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM), .Y(n1863)
);
AO22XLTS U4595 ( .A0(n5422), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2),
.B0(n6577), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SFG), .Y(n1864)
);
AO22XLTS U4596 ( .A0(n6576), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1),
.B0(n6595), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT2), .Y(n1865)
);
AO22XLTS U4597 ( .A0(n6569), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP),
.B0(n6591), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1), .Y(n1866)
);
AO22XLTS U4598 ( .A0(n6574), .A1(n6573), .B0(
inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_EXP), .B1(n6572), .Y(n1867) );
MX2X1TS U4599 ( .A(n3263), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[0]),
.S0(n5459), .Y(n1868) );
AO22XLTS U4600 ( .A0(n5984), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]), .B0(n6584), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1870) );
AO22XLTS U4601 ( .A0(n6569), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]), .B0(n6565), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1872)
);
MX2X1TS U4602 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1]), .S0(n5455), .Y(n1876)
);
AO22XLTS U4603 ( .A0(n6575), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]), .B0(n6591), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1877) );
AO22XLTS U4604 ( .A0(n5984), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]), .B0(n6571), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n1879)
);
MX2X1TS U4605 ( .A(n3273), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[2]),
.S0(n3211), .Y(n1882) );
AO22XLTS U4606 ( .A0(n6575), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2]), .B0(n6571), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1884) );
AO22XLTS U4607 ( .A0(n6569), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2]), .B0(n6571), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1886)
);
AO22XLTS U4608 ( .A0(n6569), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]), .B0(n6571), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1891) );
AO22XLTS U4609 ( .A0(n6575), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4]), .B0(n6571), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1893)
);
MX2X1TS U4610 ( .A(n3269), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[5]),
.S0(n5449), .Y(n1896) );
AO22XLTS U4611 ( .A0(n5984), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]), .B0(n6571), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1898) );
MX2X1TS U4612 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8]), .S0(n5453), .Y(n1901)
);
AO22XLTS U4613 ( .A0(n3276), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]), .B0(n6571), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1902) );
MX2X1TS U4614 ( .A(n3267), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[11]),
.S0(n5459), .Y(n1904) );
AO22XLTS U4615 ( .A0(n3276), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11]), .B0(n6571), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1906) );
AO22XLTS U4616 ( .A0(n3276), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]), .B0(n6571), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1910) );
AO22XLTS U4617 ( .A0(n3276), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .B0(n6571), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1914) );
AO22XLTS U4618 ( .A0(n3276), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]), .B0(n6570), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1918) );
AO22XLTS U4619 ( .A0(n3276), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]), .B0(n6570), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1925) );
AO22XLTS U4620 ( .A0(n3276), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24]), .B0(n6570), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[24]), .Y(n1927) );
AO22XLTS U4621 ( .A0(n3276), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]), .B0(n6570), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1932) );
AO22XLTS U4622 ( .A0(n3276), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .B0(n6570), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[23]), .Y(n1934) );
AO22XLTS U4623 ( .A0(n3276), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27]), .B0(n6570), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[27]), .Y(n1937) );
AO22XLTS U4624 ( .A0(n6575), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26]), .B0(n6570), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[26]), .Y(n1940) );
AO22XLTS U4625 ( .A0(n5984), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22]), .B0(n6570), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1945) );
AO22XLTS U4626 ( .A0(n6569), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22]), .B0(n6570), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1947) );
AO22XLTS U4627 ( .A0(n6575), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11]), .B0(n6570), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1950) );
AO22XLTS U4628 ( .A0(n5984), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]), .B0(n6568), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1955) );
AO22XLTS U4629 ( .A0(n6569), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]), .B0(n6568), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n1957)
);
AO22XLTS U4630 ( .A0(n6575), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21]), .B0(n6568), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1962) );
AO22XLTS U4631 ( .A0(n5984), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21]), .B0(n6568), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1964) );
AO22XLTS U4632 ( .A0(n6569), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8]), .B0(n6568), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1967)
);
AO22XLTS U4633 ( .A0(n6575), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20]), .B0(n6568), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1972) );
AO22XLTS U4634 ( .A0(n6567), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20]), .B0(n6568), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1974) );
AO22XLTS U4635 ( .A0(n6567), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]), .B0(n6568), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1977)
);
MX2X1TS U4636 ( .A(n3265), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[6]),
.S0(n5452), .Y(n1980) );
AO22XLTS U4637 ( .A0(n6567), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]), .B0(n6568), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1982) );
AO22XLTS U4638 ( .A0(n6567), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6]), .B0(n6566), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1984)
);
MX2X1TS U4639 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(n3180), .S0(
n5450), .Y(n1987) );
MX2X1TS U4640 ( .A(n3180), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7]),
.S0(n5455), .Y(n1988) );
AO22XLTS U4641 ( .A0(n6567), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]), .B0(n6566), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1989) );
AO22XLTS U4642 ( .A0(n6567), .A1(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]), .B0(n6566), .B1(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1991)
);
MX2X1TS U4643 ( .A(n3259), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[10]),
.S0(n5459), .Y(n1994) );
AO22XLTS U4644 ( .A0(n6567), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10]), .B0(n6566), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1996) );
AO22XLTS U4645 ( .A0(n6567), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10]), .B0(n6566), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1998) );
AO22XLTS U4646 ( .A0(n6567), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16]), .B0(n6566), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n2003) );
AO22XLTS U4647 ( .A0(n6567), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16]), .B0(n6566), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n2005) );
AO22XLTS U4648 ( .A0(n6564), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18]), .B0(n6566), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n2010) );
AO22XLTS U4649 ( .A0(n6564), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18]), .B0(n6566), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n2012) );
AO22XLTS U4650 ( .A0(n6564), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19]), .B0(n6566), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n2017) );
MX2X1TS U4651 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19]), .S0(n6575), .Y(n2019)
);
MX2X1TS U4652 ( .A(n6012), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[5]), .S0(n6559), .Y(
n2022) );
MX2X1TS U4653 ( .A(n6014), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[2]), .S0(n6559), .Y(
n2024) );
MX2X1TS U4654 ( .A(n6013), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]), .S0(n6559), .Y(
n2026) );
XOR2XLTS U4655 ( .A(n5487), .B(n5486), .Y(n5495) );
XOR2XLTS U4656 ( .A(n5656), .B(n5655), .Y(n5661) );
OAI2BB1X1TS U4657 ( .A0N(n5766), .A1N(n4145), .B0(n4144), .Y(n2039) );
XOR2XLTS U4658 ( .A(n4136), .B(n4141), .Y(n4145) );
XOR2XLTS U4659 ( .A(n5610), .B(n5609), .Y(n5615) );
XOR2XLTS U4660 ( .A(n5670), .B(n5669), .Y(n5675) );
XOR2XLTS U4661 ( .A(n5680), .B(n5679), .Y(n5689) );
AO22XLTS U4662 ( .A0(n6589), .A1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1),
.B0(n6595), .B1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT2), .Y(n2084)
);
AO22XLTS U4663 ( .A0(n6564), .A1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP),
.B0(n6563), .B1(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SHT1), .Y(n2085)
);
AO22XLTS U4664 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM), .B0(n6559), .B1(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n2088) );
AO22XLTS U4665 ( .A0(n3216), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG),
.B0(n6579), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_NRM), .Y(n2089)
);
AO22XLTS U4666 ( .A0(n6478), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2),
.B0(n6558), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SFG), .Y(n2090)
);
AO22XLTS U4667 ( .A0(n6576), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1),
.B0(n6590), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT2), .Y(n2091)
);
AO22XLTS U4668 ( .A0(n6564), .A1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP),
.B0(n6563), .B1(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1), .Y(n2092)
);
MX2X1TS U4669 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[29]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[29]), .S0(n6477), .Y(n2095)
);
AO22XLTS U4670 ( .A0(n6564), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14]), .B0(n6563), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n2098) );
AO22XLTS U4671 ( .A0(n6564), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[32]), .B0(n6568), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[32]), .Y(n2101) );
MX2X1TS U4672 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17]), .S0(n6477), .Y(n2104)
);
AO22XLTS U4673 ( .A0(n6564), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[30]), .B0(n6563), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[30]), .Y(n2107) );
AO22XLTS U4674 ( .A0(n6564), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15]), .B0(n6563), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n2110) );
AO22XLTS U4675 ( .A0(n6564), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12]), .B0(n6563), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n2113) );
AO22XLTS U4676 ( .A0(n6482), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[31]), .B0(n6563), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[31]), .Y(n2116) );
MX2X1TS U4677 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[28]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[28]), .S0(n6477), .Y(n2119)
);
MX2X1TS U4678 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[37]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[37]), .S0(n6569), .Y(n2122)
);
AO22XLTS U4679 ( .A0(n6482), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[40]), .B0(n6563), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[40]), .Y(n2125) );
AO22XLTS U4680 ( .A0(n6482), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[38]), .B0(n6563), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[38]), .Y(n2128) );
MX2X1TS U4681 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[41]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[41]), .S0(n5984), .Y(n2131)
);
MX2X1TS U4682 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[39]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[39]), .S0(n6569), .Y(n2134)
);
AO22XLTS U4683 ( .A0(n6482), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[36]), .B0(n6481), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[36]), .Y(n2137) );
AO22XLTS U4684 ( .A0(n6482), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[43]), .B0(n6563), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[43]), .Y(n2140) );
AO22XLTS U4685 ( .A0(n6482), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[42]), .B0(n6481), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[42]), .Y(n2143) );
AO22XLTS U4686 ( .A0(n6482), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[35]), .B0(n6481), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[35]), .Y(n2146) );
AO22XLTS U4687 ( .A0(n6482), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[45]), .B0(n6481), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[45]), .Y(n2152) );
AO22XLTS U4688 ( .A0(n6482), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[34]), .B0(n6481), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[34]), .Y(n2155) );
MX2X1TS U4689 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3]), .S0(n5984), .Y(n2158) );
AO22XLTS U4690 ( .A0(n6482), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[44]), .B0(n6481), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[44]), .Y(n2161) );
AO22XLTS U4691 ( .A0(n3275), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[33]), .B0(n6481), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[33]), .Y(n2164) );
AO22XLTS U4692 ( .A0(n3275), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[48]), .B0(n6481), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[48]), .Y(n2167) );
AO22XLTS U4693 ( .A0(n3275), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[49]), .B0(n6481), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[49]), .Y(n2170) );
AO22XLTS U4694 ( .A0(n3275), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[47]), .B0(n6480), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[47]), .Y(n2173) );
AO22XLTS U4695 ( .A0(n3275), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[51]), .B0(n6481), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[51]), .Y(n2179) );
AO22XLTS U4696 ( .A0(n6580), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[62]),
.B0(n6579), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[10]), .Y(
n2193) );
AO22XLTS U4697 ( .A0(n5418), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[62]), .B0(n6558), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[62]), .Y(n2194) );
AO22XLTS U4698 ( .A0(n6576), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[62]), .B0(n6592), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[62]), .Y(n2195) );
AO22XLTS U4699 ( .A0(n3275), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[62]), .B0(n6480), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[62]), .Y(n2196) );
AO22XLTS U4700 ( .A0(n6580), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[61]),
.B0(n5446), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[9]), .Y(
n2198) );
AO22XLTS U4701 ( .A0(n5422), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[61]), .B0(n6577), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[61]), .Y(n2199) );
AO22XLTS U4702 ( .A0(n6576), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[61]), .B0(n6592), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[61]), .Y(n2200) );
AO22XLTS U4703 ( .A0(n3275), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[61]), .B0(n6480), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[61]), .Y(n2201) );
AO22XLTS U4704 ( .A0(n6580), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[60]),
.B0(n5446), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[8]), .Y(
n2203) );
AO22XLTS U4705 ( .A0(n6578), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[60]), .B0(n6577), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[60]), .Y(n2204) );
AO22XLTS U4706 ( .A0(busy), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[60]), .B0(n6592), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[60]), .Y(n2205) );
AO22XLTS U4707 ( .A0(n3275), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[60]), .B0(n6480), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[60]), .Y(n2206) );
AO22XLTS U4708 ( .A0(n6580), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[59]),
.B0(n3215), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[7]), .Y(
n2208) );
AO22XLTS U4709 ( .A0(n6478), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[59]), .B0(n6577), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[59]), .Y(n2209) );
AO22XLTS U4710 ( .A0(n6576), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[59]), .B0(n6592), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[59]), .Y(n2210) );
AO22XLTS U4711 ( .A0(n3275), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[59]), .B0(n6480), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[59]), .Y(n2211) );
AO22XLTS U4712 ( .A0(n6580), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[58]),
.B0(n3215), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[6]), .Y(
n2213) );
AO22XLTS U4713 ( .A0(n5418), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[58]), .B0(n6577), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[58]), .Y(n2214) );
AO22XLTS U4714 ( .A0(n6576), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[58]), .B0(n6590), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[58]), .Y(n2215) );
AO22XLTS U4715 ( .A0(n3275), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[58]), .B0(n6480), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[58]), .Y(n2216) );
AO22XLTS U4716 ( .A0(n6580), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[57]),
.B0(n6473), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[5]), .Y(
n2218) );
AO22XLTS U4717 ( .A0(n5422), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[57]), .B0(n6577), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[57]), .Y(n2219) );
AO22XLTS U4718 ( .A0(n6576), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[57]), .B0(n6592), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[57]), .Y(n2220) );
AO22XLTS U4719 ( .A0(n6477), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[57]), .B0(n6480), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[57]), .Y(n2221) );
AO22XLTS U4720 ( .A0(n3216), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[56]),
.B0(n6473), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[4]), .Y(
n2223) );
AO22XLTS U4721 ( .A0(n5422), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[56]), .B0(n6577), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[56]), .Y(n2224) );
AO22XLTS U4722 ( .A0(n6576), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[56]), .B0(n6592), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[56]), .Y(n2225) );
AO22XLTS U4723 ( .A0(n6477), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[56]), .B0(n6480), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[56]), .Y(n2226) );
AO22XLTS U4724 ( .A0(n6580), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[55]),
.B0(n6473), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[3]), .Y(
n2228) );
AO22XLTS U4725 ( .A0(n3211), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[55]), .B0(n6476), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[55]), .Y(n2229) );
AO22XLTS U4726 ( .A0(n6576), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[55]), .B0(n6590), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[55]), .Y(n2230) );
AO22XLTS U4727 ( .A0(n6477), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[55]), .B0(n6480), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[55]), .Y(n2231) );
AO22XLTS U4728 ( .A0(n3216), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[54]),
.B0(n6473), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[2]), .Y(
n2233) );
AO22XLTS U4729 ( .A0(n5422), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[54]), .B0(n6558), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[54]), .Y(n2234) );
AO22XLTS U4730 ( .A0(n6576), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[54]), .B0(n6845), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[54]), .Y(n2235) );
AO22XLTS U4731 ( .A0(n6477), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[54]), .B0(n6565), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[54]), .Y(n2236) );
MX2X1TS U4732 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]), .S0(n6011), .Y(n2237)
);
AO22XLTS U4733 ( .A0(n6580), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[53]),
.B0(n3186), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[1]), .Y(
n2238) );
AO22XLTS U4734 ( .A0(n6478), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[53]), .B0(n6558), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[53]), .Y(n2239) );
AO22XLTS U4735 ( .A0(n6474), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[53]), .B0(n6595), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[53]), .Y(n2240) );
AO22XLTS U4736 ( .A0(n6477), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[53]), .B0(n6591), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[53]), .Y(n2241) );
MX2X1TS U4737 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]), .S0(n6011), .Y(n2242)
);
AO22XLTS U4738 ( .A0(n3216), .A1(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[52]),
.B0(n3186), .B1(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM_EW[0]), .Y(
n2243) );
AO22XLTS U4739 ( .A0(n5418), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[52]), .B0(n6475), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[52]), .Y(n2244) );
AO22XLTS U4740 ( .A0(n6474), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[52]), .B0(n6595), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT2_EWSW[52]), .Y(n2245) );
AO22XLTS U4741 ( .A0(n6477), .A1(
inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[52]), .B0(n6586), .B1(
inst_FPU_PIPELINED_FPADDSUB_DMP_SHT1_EWSW[52]), .Y(n2246) );
OAI21XLTS U4742 ( .A0(n6648), .A1(n4906), .B0(n4874), .Y(n2249) );
OAI21XLTS U4743 ( .A0(n6649), .A1(n4877), .B0(n4876), .Y(n2250) );
MX2X1TS U4744 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[5]),
.B(n5983), .S0(n6575), .Y(n2269) );
MX2X1TS U4745 ( .A(intadd_44_SUM_1_), .B(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[2]), .S0(n6593), .Y(
n2272) );
MX2X1TS U4746 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[4]),
.B(n5458), .S0(n6569), .Y(n2274) );
AO22XLTS U4747 ( .A0(n6311), .A1(d_ff2_X[0]), .B0(n6134), .B1(
d_ff3_sh_x_out[0]), .Y(n2880) );
AO22XLTS U4748 ( .A0(n6464), .A1(d_ff2_Y[0]), .B0(n6185), .B1(
d_ff3_sh_y_out[0]), .Y(n2749) );
MX2X1TS U4749 ( .A(result_add_subt[0]), .B(d_ff_Zn[0]), .S0(n6047), .Y(n3037) );
AO22XLTS U4750 ( .A0(n6311), .A1(d_ff2_X[1]), .B0(n6134), .B1(
d_ff3_sh_x_out[1]), .Y(n2878) );
AO22XLTS U4751 ( .A0(n6464), .A1(d_ff2_Y[1]), .B0(n6185), .B1(
d_ff3_sh_y_out[1]), .Y(n2746) );
MX2X1TS U4752 ( .A(result_add_subt[1]), .B(d_ff_Zn[1]), .S0(n6170), .Y(n3034) );
AO22XLTS U4753 ( .A0(n6136), .A1(d_ff2_X[2]), .B0(n6134), .B1(
d_ff3_sh_x_out[2]), .Y(n2876) );
AO22XLTS U4754 ( .A0(n6206), .A1(d_ff2_Y[2]), .B0(n6256), .B1(
d_ff3_sh_y_out[2]), .Y(n2743) );
MX2X1TS U4755 ( .A(result_add_subt[2]), .B(d_ff_Zn[2]), .S0(n6170), .Y(n3031) );
AO22XLTS U4756 ( .A0(n6311), .A1(d_ff2_X[4]), .B0(n6134), .B1(
d_ff3_sh_x_out[4]), .Y(n2872) );
AO22XLTS U4757 ( .A0(n6464), .A1(d_ff2_Y[4]), .B0(n6185), .B1(
d_ff3_sh_y_out[4]), .Y(n2737) );
MX2X1TS U4758 ( .A(result_add_subt[4]), .B(d_ff_Zn[4]), .S0(n6170), .Y(n3025) );
AO22XLTS U4759 ( .A0(n6141), .A1(d_ff2_X[25]), .B0(n6140), .B1(
d_ff3_sh_x_out[25]), .Y(n2830) );
AO22XLTS U4760 ( .A0(n6249), .A1(d_ff2_Y[25]), .B0(n6246), .B1(
d_ff3_sh_y_out[25]), .Y(n2674) );
MX2X1TS U4761 ( .A(result_add_subt[25]), .B(d_ff_Zn[25]), .S0(n6046), .Y(
n2962) );
AO22XLTS U4762 ( .A0(n6139), .A1(d_ff2_X[24]), .B0(n6140), .B1(
d_ff3_sh_x_out[24]), .Y(n2832) );
AO22XLTS U4763 ( .A0(n6267), .A1(d_ff2_Y[24]), .B0(n6246), .B1(
d_ff3_sh_y_out[24]), .Y(n2677) );
MX2X1TS U4764 ( .A(result_add_subt[24]), .B(d_ff_Zn[24]), .S0(n6048), .Y(
n2965) );
AO22XLTS U4765 ( .A0(n6141), .A1(d_ff2_X[23]), .B0(n6140), .B1(
d_ff3_sh_x_out[23]), .Y(n2834) );
AO22XLTS U4766 ( .A0(n6267), .A1(d_ff2_Y[23]), .B0(n6246), .B1(
d_ff3_sh_y_out[23]), .Y(n2680) );
MX2X1TS U4767 ( .A(result_add_subt[23]), .B(d_ff_Zn[23]), .S0(n6331), .Y(
n2968) );
AO22XLTS U4768 ( .A0(n6141), .A1(d_ff2_X[27]), .B0(n6140), .B1(
d_ff3_sh_x_out[27]), .Y(n2826) );
AO22XLTS U4769 ( .A0(n6249), .A1(d_ff2_Y[27]), .B0(n6266), .B1(
d_ff3_sh_y_out[27]), .Y(n2668) );
MX2X1TS U4770 ( .A(result_add_subt[27]), .B(d_ff_Zn[27]), .S0(n6047), .Y(
n2956) );
AO22XLTS U4771 ( .A0(n6139), .A1(d_ff2_X[26]), .B0(n6140), .B1(
d_ff3_sh_x_out[26]), .Y(n2828) );
AO22XLTS U4772 ( .A0(n6267), .A1(d_ff2_Y[26]), .B0(n6246), .B1(
d_ff3_sh_y_out[26]), .Y(n2671) );
MX2X1TS U4773 ( .A(result_add_subt[26]), .B(d_ff_Zn[26]), .S0(n6045), .Y(
n2959) );
AO22XLTS U4774 ( .A0(n6139), .A1(d_ff2_X[22]), .B0(n6140), .B1(
d_ff3_sh_x_out[22]), .Y(n2836) );
AO22XLTS U4775 ( .A0(n6249), .A1(d_ff2_Y[22]), .B0(n6246), .B1(
d_ff3_sh_y_out[22]), .Y(n2683) );
MX2X1TS U4776 ( .A(result_add_subt[22]), .B(d_ff_Zn[22]), .S0(n6048), .Y(
n2971) );
AO22XLTS U4777 ( .A0(n6139), .A1(d_ff2_X[11]), .B0(n6137), .B1(
d_ff3_sh_x_out[11]), .Y(n2858) );
AO22XLTS U4778 ( .A0(n6206), .A1(d_ff2_Y[11]), .B0(n6214), .B1(
d_ff3_sh_y_out[11]), .Y(n2716) );
MX2X1TS U4779 ( .A(result_add_subt[11]), .B(d_ff_Zn[11]), .S0(n6046), .Y(
n3004) );
AO22XLTS U4780 ( .A0(n6136), .A1(d_ff2_X[9]), .B0(n6134), .B1(
d_ff3_sh_x_out[9]), .Y(n2862) );
AO22XLTS U4781 ( .A0(n6206), .A1(d_ff2_Y[9]), .B0(n6214), .B1(
d_ff3_sh_y_out[9]), .Y(n2722) );
MX2X1TS U4782 ( .A(result_add_subt[9]), .B(d_ff_Zn[9]), .S0(n6048), .Y(n3010) );
AO22XLTS U4783 ( .A0(n6139), .A1(d_ff2_X[21]), .B0(n6140), .B1(
d_ff3_sh_x_out[21]), .Y(n2838) );
AO22XLTS U4784 ( .A0(n6267), .A1(d_ff2_Y[21]), .B0(n6246), .B1(
d_ff3_sh_y_out[21]), .Y(n2686) );
MX2X1TS U4785 ( .A(result_add_subt[21]), .B(d_ff_Zn[21]), .S0(n6045), .Y(
n2974) );
AO22XLTS U4786 ( .A0(n6136), .A1(d_ff2_X[8]), .B0(n6134), .B1(
d_ff3_sh_x_out[8]), .Y(n2864) );
AO22XLTS U4787 ( .A0(n6206), .A1(d_ff2_Y[8]), .B0(n6214), .B1(
d_ff3_sh_y_out[8]), .Y(n2725) );
MX2X1TS U4788 ( .A(result_add_subt[8]), .B(d_ff_Zn[8]), .S0(n6045), .Y(n3013) );
AO22XLTS U4789 ( .A0(n6139), .A1(d_ff2_X[20]), .B0(n6140), .B1(
d_ff3_sh_x_out[20]), .Y(n2840) );
AO22XLTS U4790 ( .A0(n6267), .A1(d_ff2_Y[20]), .B0(n6246), .B1(
d_ff3_sh_y_out[20]), .Y(n2689) );
MX2X1TS U4791 ( .A(result_add_subt[20]), .B(d_ff_Zn[20]), .S0(n6046), .Y(
n2977) );
AO22XLTS U4792 ( .A0(n6311), .A1(d_ff2_X[5]), .B0(n6134), .B1(
d_ff3_sh_x_out[5]), .Y(n2870) );
AO22XLTS U4793 ( .A0(n6206), .A1(d_ff2_Y[5]), .B0(n6185), .B1(
d_ff3_sh_y_out[5]), .Y(n2734) );
MX2X1TS U4794 ( .A(result_add_subt[5]), .B(d_ff_Zn[5]), .S0(n6170), .Y(n3022) );
AO22XLTS U4795 ( .A0(n6311), .A1(d_ff2_X[6]), .B0(n6134), .B1(
d_ff3_sh_x_out[6]), .Y(n2868) );
AO22XLTS U4796 ( .A0(n6206), .A1(d_ff2_Y[6]), .B0(n6185), .B1(
d_ff3_sh_y_out[6]), .Y(n2731) );
MX2X1TS U4797 ( .A(result_add_subt[6]), .B(d_ff_Zn[6]), .S0(n6331), .Y(n3019) );
AO22XLTS U4798 ( .A0(n6136), .A1(d_ff2_X[7]), .B0(n6134), .B1(
d_ff3_sh_x_out[7]), .Y(n2866) );
AO22XLTS U4799 ( .A0(n6206), .A1(d_ff2_Y[7]), .B0(n6214), .B1(
d_ff3_sh_y_out[7]), .Y(n2728) );
MX2X1TS U4800 ( .A(result_add_subt[7]), .B(d_ff_Zn[7]), .S0(n6046), .Y(n3016) );
AO22XLTS U4801 ( .A0(n6136), .A1(d_ff2_X[10]), .B0(n6137), .B1(
d_ff3_sh_x_out[10]), .Y(n2860) );
AO22XLTS U4802 ( .A0(n6206), .A1(d_ff2_Y[10]), .B0(n6214), .B1(
d_ff3_sh_y_out[10]), .Y(n2719) );
MX2X1TS U4803 ( .A(result_add_subt[10]), .B(d_ff_Zn[10]), .S0(n6331), .Y(
n3007) );
AO22XLTS U4804 ( .A0(n6136), .A1(d_ff2_X[16]), .B0(n6137), .B1(
d_ff3_sh_x_out[16]), .Y(n2848) );
AO22XLTS U4805 ( .A0(n6249), .A1(d_ff2_Y[16]), .B0(n6214), .B1(
d_ff3_sh_y_out[16]), .Y(n2701) );
MX2X1TS U4806 ( .A(result_add_subt[16]), .B(d_ff_Zn[16]), .S0(n6048), .Y(
n2989) );
AO22XLTS U4807 ( .A0(n6139), .A1(d_ff2_X[18]), .B0(n6137), .B1(
d_ff3_sh_x_out[18]), .Y(n2844) );
AO22XLTS U4808 ( .A0(n6249), .A1(d_ff2_Y[18]), .B0(n6246), .B1(
d_ff3_sh_y_out[18]), .Y(n2695) );
MX2X1TS U4809 ( .A(result_add_subt[18]), .B(d_ff_Zn[18]), .S0(n6045), .Y(
n2983) );
AO22XLTS U4810 ( .A0(n6139), .A1(d_ff2_X[19]), .B0(n6137), .B1(
d_ff3_sh_x_out[19]), .Y(n2842) );
AO22XLTS U4811 ( .A0(n6249), .A1(d_ff2_Y[19]), .B0(n6246), .B1(
d_ff3_sh_y_out[19]), .Y(n2692) );
MX2X1TS U4812 ( .A(result_add_subt[19]), .B(d_ff_Zn[19]), .S0(n6048), .Y(
n2980) );
AO22XLTS U4813 ( .A0(n6464), .A1(d_ff2_X[63]), .B0(n6175), .B1(
d_ff3_sh_x_out[63]), .Y(n2754) );
AO22XLTS U4814 ( .A0(n6464), .A1(d_ff2_Y[63]), .B0(n6158), .B1(
d_ff3_sh_y_out[63]), .Y(n2343) );
AO22XLTS U4815 ( .A0(n6329), .A1(result_add_subt[63]), .B0(n6170), .B1(
d_ff_Zn[63]), .Y(n2752) );
AO22XLTS U4816 ( .A0(n6136), .A1(d_ff2_X[13]), .B0(n6137), .B1(
d_ff3_sh_x_out[13]), .Y(n2854) );
AO22XLTS U4817 ( .A0(n6206), .A1(d_ff2_Y[13]), .B0(n6214), .B1(
d_ff3_sh_y_out[13]), .Y(n2710) );
MX2X1TS U4818 ( .A(result_add_subt[13]), .B(d_ff_Zn[13]), .S0(n6048), .Y(
n2998) );
AO22XLTS U4819 ( .A0(n6145), .A1(d_ff2_X[29]), .B0(n6140), .B1(
d_ff3_sh_x_out[29]), .Y(n2822) );
AO22XLTS U4820 ( .A0(n6267), .A1(d_ff2_Y[29]), .B0(n6266), .B1(
d_ff3_sh_y_out[29]), .Y(n2662) );
MX2X1TS U4821 ( .A(result_add_subt[29]), .B(d_ff_Zn[29]), .S0(n6047), .Y(
n2950) );
AO22XLTS U4822 ( .A0(n6136), .A1(d_ff2_X[14]), .B0(n6137), .B1(
d_ff3_sh_x_out[14]), .Y(n2852) );
AO22XLTS U4823 ( .A0(n6249), .A1(d_ff2_Y[14]), .B0(n6214), .B1(
d_ff3_sh_y_out[14]), .Y(n2707) );
MX2X1TS U4824 ( .A(result_add_subt[14]), .B(d_ff_Zn[14]), .S0(n6046), .Y(
n2995) );
AO22XLTS U4825 ( .A0(n6141), .A1(d_ff2_X[32]), .B0(n6142), .B1(
d_ff3_sh_x_out[32]), .Y(n2816) );
AO22XLTS U4826 ( .A0(n6290), .A1(d_ff2_Y[32]), .B0(n6266), .B1(
d_ff3_sh_y_out[32]), .Y(n2653) );
MX2X1TS U4827 ( .A(result_add_subt[32]), .B(d_ff_Zn[32]), .S0(n6047), .Y(
n2941) );
AO22XLTS U4828 ( .A0(n6139), .A1(d_ff2_X[17]), .B0(n6137), .B1(
d_ff3_sh_x_out[17]), .Y(n2846) );
AO22XLTS U4829 ( .A0(n6249), .A1(d_ff2_Y[17]), .B0(n6246), .B1(
d_ff3_sh_y_out[17]), .Y(n2698) );
MX2X1TS U4830 ( .A(result_add_subt[17]), .B(d_ff_Zn[17]), .S0(n6046), .Y(
n2986) );
AO22XLTS U4831 ( .A0(n6141), .A1(d_ff2_X[30]), .B0(n6142), .B1(
d_ff3_sh_x_out[30]), .Y(n2820) );
AO22XLTS U4832 ( .A0(n6290), .A1(d_ff2_Y[30]), .B0(n6266), .B1(
d_ff3_sh_y_out[30]), .Y(n2659) );
MX2X1TS U4833 ( .A(result_add_subt[30]), .B(d_ff_Zn[30]), .S0(n6047), .Y(
n2947) );
AO22XLTS U4834 ( .A0(n6139), .A1(d_ff2_X[15]), .B0(n6137), .B1(
d_ff3_sh_x_out[15]), .Y(n2850) );
AO22XLTS U4835 ( .A0(n6249), .A1(d_ff2_Y[15]), .B0(n6214), .B1(
d_ff3_sh_y_out[15]), .Y(n2704) );
MX2X1TS U4836 ( .A(result_add_subt[15]), .B(d_ff_Zn[15]), .S0(n6045), .Y(
n2992) );
AO22XLTS U4837 ( .A0(n6136), .A1(d_ff2_X[12]), .B0(n6137), .B1(
d_ff3_sh_x_out[12]), .Y(n2856) );
AO22XLTS U4838 ( .A0(n6249), .A1(d_ff2_Y[12]), .B0(n6214), .B1(
d_ff3_sh_y_out[12]), .Y(n2713) );
MX2X1TS U4839 ( .A(result_add_subt[12]), .B(d_ff_Zn[12]), .S0(n6045), .Y(
n3001) );
AO22XLTS U4840 ( .A0(n6141), .A1(d_ff2_X[31]), .B0(n6142), .B1(
d_ff3_sh_x_out[31]), .Y(n2818) );
AO22XLTS U4841 ( .A0(n6267), .A1(d_ff2_Y[31]), .B0(n6266), .B1(
d_ff3_sh_y_out[31]), .Y(n2656) );
MX2X1TS U4842 ( .A(result_add_subt[31]), .B(d_ff_Zn[31]), .S0(n6047), .Y(
n2944) );
AO22XLTS U4843 ( .A0(n6141), .A1(d_ff2_X[28]), .B0(n6140), .B1(
d_ff3_sh_x_out[28]), .Y(n2824) );
AO22XLTS U4844 ( .A0(n6267), .A1(d_ff2_Y[28]), .B0(n6266), .B1(
d_ff3_sh_y_out[28]), .Y(n2665) );
MX2X1TS U4845 ( .A(result_add_subt[28]), .B(d_ff_Zn[28]), .S0(n6047), .Y(
n2953) );
AO22XLTS U4846 ( .A0(n6145), .A1(d_ff2_X[37]), .B0(n6142), .B1(
d_ff3_sh_x_out[37]), .Y(n2806) );
AO22XLTS U4847 ( .A0(n6464), .A1(d_ff2_Y[37]), .B0(n6282), .B1(
d_ff3_sh_y_out[37]), .Y(n2638) );
MX2X1TS U4848 ( .A(result_add_subt[37]), .B(d_ff_Zn[37]), .S0(n6048), .Y(
n2926) );
AO22XLTS U4849 ( .A0(n6145), .A1(d_ff2_X[40]), .B0(n6146), .B1(
d_ff3_sh_x_out[40]), .Y(n2800) );
AO22XLTS U4850 ( .A0(n6290), .A1(d_ff2_Y[40]), .B0(n6282), .B1(
d_ff3_sh_y_out[40]), .Y(n2629) );
MX2X1TS U4851 ( .A(result_add_subt[40]), .B(d_ff_Zn[40]), .S0(n6046), .Y(
n2917) );
AO22XLTS U4852 ( .A0(n6145), .A1(d_ff2_X[38]), .B0(n6142), .B1(
d_ff3_sh_x_out[38]), .Y(n2804) );
AO22XLTS U4853 ( .A0(n6290), .A1(d_ff2_Y[38]), .B0(n6282), .B1(
d_ff3_sh_y_out[38]), .Y(n2635) );
MX2X1TS U4854 ( .A(result_add_subt[38]), .B(d_ff_Zn[38]), .S0(n6331), .Y(
n2923) );
AO22XLTS U4855 ( .A0(n6160), .A1(d_ff2_X[41]), .B0(n6146), .B1(
d_ff3_sh_x_out[41]), .Y(n2798) );
AO22XLTS U4856 ( .A0(n6315), .A1(d_ff2_Y[41]), .B0(n6282), .B1(
d_ff3_sh_y_out[41]), .Y(n2626) );
MX2X1TS U4857 ( .A(result_add_subt[41]), .B(d_ff_Zn[41]), .S0(n6045), .Y(
n2914) );
AO22XLTS U4858 ( .A0(n6145), .A1(d_ff2_X[39]), .B0(n6142), .B1(
d_ff3_sh_x_out[39]), .Y(n2802) );
AO22XLTS U4859 ( .A0(n6290), .A1(d_ff2_Y[39]), .B0(n6282), .B1(
d_ff3_sh_y_out[39]), .Y(n2632) );
MX2X1TS U4860 ( .A(result_add_subt[39]), .B(d_ff_Zn[39]), .S0(n6048), .Y(
n2920) );
AO22XLTS U4861 ( .A0(n6141), .A1(d_ff2_X[36]), .B0(n6142), .B1(
d_ff3_sh_x_out[36]), .Y(n2808) );
AO22XLTS U4862 ( .A0(n6290), .A1(d_ff2_Y[36]), .B0(n6282), .B1(
d_ff3_sh_y_out[36]), .Y(n2641) );
MX2X1TS U4863 ( .A(result_add_subt[36]), .B(d_ff_Zn[36]), .S0(n6045), .Y(
n2929) );
AO22XLTS U4864 ( .A0(n6145), .A1(d_ff2_X[43]), .B0(n6146), .B1(
d_ff3_sh_x_out[43]), .Y(n2794) );
AO22XLTS U4865 ( .A0(n6290), .A1(d_ff2_Y[43]), .B0(n6282), .B1(
d_ff3_sh_y_out[43]), .Y(n2620) );
MX2X1TS U4866 ( .A(result_add_subt[43]), .B(d_ff_Zn[43]), .S0(n6046), .Y(
n2908) );
AO22XLTS U4867 ( .A0(n6145), .A1(d_ff2_X[42]), .B0(n6146), .B1(
d_ff3_sh_x_out[42]), .Y(n2796) );
AO22XLTS U4868 ( .A0(n6315), .A1(d_ff2_Y[42]), .B0(n6282), .B1(
d_ff3_sh_y_out[42]), .Y(n2623) );
MX2X1TS U4869 ( .A(result_add_subt[42]), .B(d_ff_Zn[42]), .S0(n6048), .Y(
n2911) );
AO22XLTS U4870 ( .A0(n6145), .A1(d_ff2_X[35]), .B0(n6142), .B1(
d_ff3_sh_x_out[35]), .Y(n2810) );
AO22XLTS U4871 ( .A0(n6267), .A1(d_ff2_Y[35]), .B0(n6266), .B1(
d_ff3_sh_y_out[35]), .Y(n2644) );
MX2X1TS U4872 ( .A(result_add_subt[35]), .B(d_ff_Zn[35]), .S0(n6047), .Y(
n2932) );
AO22XLTS U4873 ( .A0(n6145), .A1(d_ff2_X[46]), .B0(n6146), .B1(
d_ff3_sh_x_out[46]), .Y(n2788) );
AO22XLTS U4874 ( .A0(n6290), .A1(d_ff2_Y[46]), .B0(n6092), .B1(
d_ff3_sh_y_out[46]), .Y(n2611) );
MX2X1TS U4875 ( .A(result_add_subt[46]), .B(d_ff_Zn[46]), .S0(n6049), .Y(
n2899) );
AO22XLTS U4876 ( .A0(n6160), .A1(d_ff2_X[45]), .B0(n6146), .B1(
d_ff3_sh_x_out[45]), .Y(n2790) );
AO22XLTS U4877 ( .A0(n6315), .A1(d_ff2_Y[45]), .B0(n6282), .B1(
d_ff3_sh_y_out[45]), .Y(n2614) );
MX2X1TS U4878 ( .A(result_add_subt[45]), .B(d_ff_Zn[45]), .S0(n6331), .Y(
n2902) );
AO22XLTS U4879 ( .A0(n6141), .A1(d_ff2_X[34]), .B0(n6142), .B1(
d_ff3_sh_x_out[34]), .Y(n2812) );
AO22XLTS U4880 ( .A0(n6267), .A1(d_ff2_Y[34]), .B0(n6266), .B1(
d_ff3_sh_y_out[34]), .Y(n2647) );
MX2X1TS U4881 ( .A(result_add_subt[34]), .B(d_ff_Zn[34]), .S0(n6047), .Y(
n2935) );
AO22XLTS U4882 ( .A0(n6136), .A1(d_ff2_X[3]), .B0(n6134), .B1(
d_ff3_sh_x_out[3]), .Y(n2874) );
AO22XLTS U4883 ( .A0(n6206), .A1(d_ff2_Y[3]), .B0(n6185), .B1(
d_ff3_sh_y_out[3]), .Y(n2740) );
MX2X1TS U4884 ( .A(result_add_subt[3]), .B(d_ff_Zn[3]), .S0(n6170), .Y(n3028) );
AO22XLTS U4885 ( .A0(n6145), .A1(d_ff2_X[44]), .B0(n6146), .B1(
d_ff3_sh_x_out[44]), .Y(n2792) );
AO22XLTS U4886 ( .A0(n6315), .A1(d_ff2_Y[44]), .B0(n6282), .B1(
d_ff3_sh_y_out[44]), .Y(n2617) );
MX2X1TS U4887 ( .A(result_add_subt[44]), .B(d_ff_Zn[44]), .S0(n6045), .Y(
n2905) );
AO22XLTS U4888 ( .A0(n6141), .A1(d_ff2_X[33]), .B0(n6142), .B1(
d_ff3_sh_x_out[33]), .Y(n2814) );
AO22XLTS U4889 ( .A0(n6290), .A1(d_ff2_Y[33]), .B0(n6266), .B1(
d_ff3_sh_y_out[33]), .Y(n2650) );
MX2X1TS U4890 ( .A(result_add_subt[33]), .B(d_ff_Zn[33]), .S0(n6047), .Y(
n2938) );
AO22XLTS U4891 ( .A0(n6160), .A1(d_ff2_X[48]), .B0(n6146), .B1(
d_ff3_sh_x_out[48]), .Y(n2784) );
AO22XLTS U4892 ( .A0(n6315), .A1(d_ff2_Y[48]), .B0(n6092), .B1(
d_ff3_sh_y_out[48]), .Y(n2605) );
MX2X1TS U4893 ( .A(result_add_subt[48]), .B(d_ff_Zn[48]), .S0(n6049), .Y(
n2893) );
AO22XLTS U4894 ( .A0(n6160), .A1(d_ff2_X[49]), .B0(n6146), .B1(
d_ff3_sh_x_out[49]), .Y(n2782) );
AO22XLTS U4895 ( .A0(n6315), .A1(d_ff2_Y[49]), .B0(n6092), .B1(
d_ff3_sh_y_out[49]), .Y(n2602) );
MX2X1TS U4896 ( .A(result_add_subt[49]), .B(d_ff_Zn[49]), .S0(n6049), .Y(
n2890) );
AO22XLTS U4897 ( .A0(n6160), .A1(d_ff2_X[47]), .B0(n6146), .B1(
d_ff3_sh_x_out[47]), .Y(n2786) );
AO22XLTS U4898 ( .A0(n6315), .A1(d_ff2_Y[47]), .B0(n6456), .B1(
d_ff3_sh_y_out[47]), .Y(n2608) );
MX2X1TS U4899 ( .A(result_add_subt[47]), .B(d_ff_Zn[47]), .S0(n6049), .Y(
n2896) );
AO22XLTS U4900 ( .A0(n6160), .A1(d_ff2_X[50]), .B0(n6271), .B1(
d_ff3_sh_x_out[50]), .Y(n2780) );
AO22XLTS U4901 ( .A0(n6457), .A1(d_ff2_Y[50]), .B0(n6271), .B1(
d_ff3_sh_y_out[50]), .Y(n2599) );
MX2X1TS U4902 ( .A(result_add_subt[50]), .B(d_ff_Zn[50]), .S0(n6049), .Y(
n2887) );
AO22XLTS U4903 ( .A0(n6160), .A1(d_ff2_X[51]), .B0(n6158), .B1(
d_ff3_sh_x_out[51]), .Y(n2778) );
AO22XLTS U4904 ( .A0(n3229), .A1(n6147), .B0(d_ff2_X[51]), .B1(n6463), .Y(
n2779) );
AO22XLTS U4905 ( .A0(n6466), .A1(result_add_subt[51]), .B0(n6023), .B1(n3229), .Y(n2882) );
AO22XLTS U4906 ( .A0(n6290), .A1(d_ff2_Y[51]), .B0(n3876), .B1(
d_ff3_sh_y_out[51]), .Y(n2596) );
AO22XLTS U4907 ( .A0(n3228), .A1(n6291), .B0(d_ff2_Y[51]), .B1(n6289), .Y(
n2597) );
AO22XLTS U4908 ( .A0(n6328), .A1(result_add_subt[51]), .B0(n6326), .B1(n3228), .Y(n2883) );
AO22XLTS U4909 ( .A0(n6329), .A1(result_add_subt[51]), .B0(n6170), .B1(
d_ff_Zn[51]), .Y(n2884) );
AO22XLTS U4910 ( .A0(n6462), .A1(result_add_subt[62]), .B0(n6465), .B1(n3230), .Y(n2345) );
AO22XLTS U4911 ( .A0(d_ff_Yn[62]), .A1(n3936), .B0(n3232), .B1(n6294), .Y(
n2584) );
AO22XLTS U4912 ( .A0(n6044), .A1(result_add_subt[62]), .B0(n6331), .B1(
d_ff_Zn[62]), .Y(n2475) );
MX2X1TS U4913 ( .A(result_add_subt[61]), .B(n3233), .S0(n6465), .Y(n2476) );
AO22XLTS U4914 ( .A0(n3222), .A1(n3936), .B0(n3255), .B1(n6294), .Y(n2585)
);
MX2X1TS U4915 ( .A(result_add_subt[61]), .B(n3222), .S0(n6326), .Y(n2477) );
MX2X1TS U4916 ( .A(result_add_subt[61]), .B(d_ff_Zn[61]), .S0(n6049), .Y(
n2478) );
AO22XLTS U4917 ( .A0(n6462), .A1(result_add_subt[60]), .B0(n6327), .B1(n3231), .Y(n2479) );
AO22XLTS U4918 ( .A0(d_ff2_Y[60]), .A1(n6293), .B0(n3227), .B1(n6292), .Y(
n2586) );
AO22XLTS U4919 ( .A0(n6330), .A1(result_add_subt[60]), .B0(n6461), .B1(n3227), .Y(n2480) );
AO22XLTS U4920 ( .A0(n6329), .A1(result_add_subt[60]), .B0(n6046), .B1(
d_ff_Zn[60]), .Y(n2481) );
MX2X1TS U4921 ( .A(result_add_subt[59]), .B(d_ff_Zn[59]), .S0(n6049), .Y(
n2484) );
MX2X1TS U4922 ( .A(result_add_subt[58]), .B(d_ff_Zn[58]), .S0(n6049), .Y(
n2487) );
AO22XLTS U4923 ( .A0(n6329), .A1(result_add_subt[57]), .B0(n6045), .B1(
d_ff_Zn[57]), .Y(n2490) );
AO22XLTS U4924 ( .A0(n6328), .A1(result_add_subt[56]), .B0(n6461), .B1(n3226), .Y(n2492) );
AO22XLTS U4925 ( .A0(n6329), .A1(result_add_subt[56]), .B0(n6048), .B1(
d_ff_Zn[56]), .Y(n2493) );
AO22XLTS U4926 ( .A0(n6329), .A1(result_add_subt[55]), .B0(n6331), .B1(
d_ff_Zn[55]), .Y(n2496) );
MX2X1TS U4927 ( .A(result_add_subt[54]), .B(d_ff_Zn[54]), .S0(n6049), .Y(
n2499) );
AO22XLTS U4928 ( .A0(n6329), .A1(result_add_subt[53]), .B0(n6331), .B1(
d_ff_Zn[53]), .Y(n2502) );
MX2X1TS U4929 ( .A(result_add_subt[52]), .B(d_ff_Zn[52]), .S0(n6049), .Y(
n2505) );
AO22XLTS U4930 ( .A0(n6457), .A1(n6325), .B0(n6158), .B1(d_ff3_sh_y_out[62]),
.Y(n2563) );
AOI2BB2XLTS U4931 ( .B0(n6323), .B1(n6322), .A0N(d_ff3_sh_y_out[61]), .A1N(
n6321), .Y(n2565) );
AO22XLTS U4932 ( .A0(n6457), .A1(n6319), .B0(n6456), .B1(d_ff3_sh_y_out[60]),
.Y(n2567) );
OAI21XLTS U4933 ( .A0(n6318), .A1(n6752), .B0(n6320), .Y(n6319) );
AOI2BB2XLTS U4934 ( .B0(n6323), .B1(n6317), .A0N(d_ff3_sh_y_out[59]), .A1N(
n6321), .Y(n2569) );
AO22XLTS U4935 ( .A0(n6315), .A1(n6314), .B0(n6456), .B1(d_ff3_sh_y_out[58]),
.Y(n2571) );
OAI21XLTS U4936 ( .A0(n6313), .A1(n6723), .B0(n6316), .Y(n6314) );
AOI2BB2XLTS U4937 ( .B0(n6323), .B1(n6312), .A0N(d_ff3_sh_y_out[57]), .A1N(
n6311), .Y(n2573) );
AOI2BB2XLTS U4938 ( .B0(n6323), .B1(n6306), .A0N(d_ff3_sh_y_out[56]), .A1N(
n6321), .Y(n2575) );
AO22XLTS U4939 ( .A0(n6315), .A1(intadd_45_SUM_2_), .B0(n3303), .B1(
d_ff3_sh_y_out[55]), .Y(n2577) );
AO22XLTS U4940 ( .A0(n6457), .A1(intadd_45_SUM_1_), .B0(n3303), .B1(
d_ff3_sh_y_out[54]), .Y(n2579) );
AO22XLTS U4941 ( .A0(n6457), .A1(intadd_45_SUM_0_), .B0(n3303), .B1(
d_ff3_sh_y_out[53]), .Y(n2581) );
AO22XLTS U4942 ( .A0(n6315), .A1(n6295), .B0(n3303), .B1(d_ff3_sh_y_out[52]),
.Y(n2583) );
OAI21XLTS U4943 ( .A0(n3217), .A1(n6686), .B0(intadd_45_CI), .Y(n6295) );
AO22XLTS U4944 ( .A0(n6464), .A1(n6167), .B0(n6185), .B1(d_ff3_sh_x_out[62]),
.Y(n2756) );
AOI2BB2XLTS U4945 ( .B0(n6323), .B1(n6165), .A0N(d_ff3_sh_x_out[61]), .A1N(
n6311), .Y(n2757) );
AO22XLTS U4946 ( .A0(n6464), .A1(n3898), .B0(n6175), .B1(d_ff3_sh_x_out[60]),
.Y(n2758) );
OAI21XLTS U4947 ( .A0(n6161), .A1(n6737), .B0(n6164), .Y(n3898) );
AOI2BB2XLTS U4948 ( .B0(n6323), .B1(n6163), .A0N(d_ff3_sh_x_out[59]), .A1N(
n6311), .Y(n2759) );
AO22XLTS U4949 ( .A0(n6160), .A1(n6159), .B0(n6266), .B1(d_ff3_sh_x_out[58]),
.Y(n2760) );
OAI21XLTS U4950 ( .A0(n6157), .A1(n6722), .B0(n6162), .Y(n6159) );
AOI2BB2XLTS U4951 ( .B0(n6323), .B1(n6156), .A0N(d_ff3_sh_x_out[57]), .A1N(
n6311), .Y(n2761) );
AOI2BB2XLTS U4952 ( .B0(n6323), .B1(n6153), .A0N(d_ff3_sh_x_out[56]), .A1N(
n6311), .Y(n2762) );
AO22XLTS U4953 ( .A0(n6464), .A1(intadd_46_SUM_2_), .B0(n6158), .B1(
d_ff3_sh_x_out[55]), .Y(n2763) );
AO22XLTS U4954 ( .A0(n6160), .A1(intadd_46_SUM_1_), .B0(n6456), .B1(
d_ff3_sh_x_out[54]), .Y(n2764) );
AO22XLTS U4955 ( .A0(n6464), .A1(intadd_46_SUM_0_), .B0(n6456), .B1(
d_ff3_sh_x_out[53]), .Y(n2765) );
AO22XLTS U4956 ( .A0(n6160), .A1(n6152), .B0(n6092), .B1(d_ff3_sh_x_out[52]),
.Y(n2766) );
OAI21XLTS U4957 ( .A0(n3187), .A1(n6687), .B0(intadd_46_CI), .Y(n6152) );
OAI211XLTS U4958 ( .A0(n4123), .A1(n6840), .B0(n6090), .C0(n6091), .Y(n3144)
);
OAI211XLTS U4959 ( .A0(n4123), .A1(n6837), .B0(n3969), .C0(n6113), .Y(n3129)
);
OAI211XLTS U4960 ( .A0(n4123), .A1(n6834), .B0(n3969), .C0(n3971), .Y(n3145)
);
OAI211XLTS U4961 ( .A0(n4123), .A1(n6833), .B0(n6083), .C0(n6091), .Y(n3148)
);
AOI2BB2XLTS U4962 ( .B0(n6093), .B1(n6071), .A0N(n6457), .A1N(
d_ff3_LUT_out[32]), .Y(n3142) );
AOI2BB2XLTS U4963 ( .B0(n6109), .B1(n6082), .A0N(n6457), .A1N(
d_ff3_LUT_out[21]), .Y(n3132) );
AO21XLTS U4964 ( .A0(d_ff3_LUT_out[37]), .A1(n3303), .B0(n6070), .Y(n3146)
);
AO21XLTS U4965 ( .A0(d_ff3_LUT_out[52]), .A1(n3303), .B0(n6066), .Y(n3154)
);
AO21XLTS U4966 ( .A0(d_ff3_LUT_out[56]), .A1(n3303), .B0(n6072), .Y(n3158)
);
MX2X1TS U4967 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[2]), .S0(n6059), .Y(
n3167) );
AO22XLTS U4968 ( .A0(n6060), .A1(busy), .B0(n6059), .B1(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n3168) );
AO21XLTS U4969 ( .A0(n6053), .A1(n6054), .B0(n6321), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
AO22XLTS U4970 ( .A0(n6133), .A1(d_ff1_Z[63]), .B0(n6132), .B1(data_in[63]),
.Y(n3044) );
AO22XLTS U4971 ( .A0(n6133), .A1(d_ff1_Z[0]), .B0(n6132), .B1(data_in[0]),
.Y(n3045) );
AO22XLTS U4972 ( .A0(n6133), .A1(d_ff1_Z[1]), .B0(n6132), .B1(data_in[1]),
.Y(n3046) );
AO22XLTS U4973 ( .A0(n6133), .A1(d_ff1_Z[2]), .B0(n6132), .B1(data_in[2]),
.Y(n3047) );
AO22XLTS U4974 ( .A0(n6133), .A1(d_ff1_Z[3]), .B0(n6132), .B1(data_in[3]),
.Y(n3048) );
AO22XLTS U4975 ( .A0(n6133), .A1(d_ff1_Z[4]), .B0(n6132), .B1(data_in[4]),
.Y(n3049) );
AO22XLTS U4976 ( .A0(n6133), .A1(d_ff1_Z[5]), .B0(n6132), .B1(data_in[5]),
.Y(n3050) );
AO22XLTS U4977 ( .A0(n6130), .A1(d_ff1_Z[6]), .B0(n6132), .B1(data_in[6]),
.Y(n3051) );
AO22XLTS U4978 ( .A0(n6130), .A1(d_ff1_Z[7]), .B0(n6132), .B1(data_in[7]),
.Y(n3052) );
AO22XLTS U4979 ( .A0(n6130), .A1(d_ff1_Z[8]), .B0(n6129), .B1(data_in[8]),
.Y(n3053) );
AO22XLTS U4980 ( .A0(n6130), .A1(d_ff1_Z[9]), .B0(n6129), .B1(data_in[9]),
.Y(n3054) );
AO22XLTS U4981 ( .A0(n6130), .A1(d_ff1_Z[10]), .B0(n6129), .B1(data_in[10]),
.Y(n3055) );
AO22XLTS U4982 ( .A0(n6130), .A1(d_ff1_Z[11]), .B0(n6129), .B1(data_in[11]),
.Y(n3056) );
AO22XLTS U4983 ( .A0(n6130), .A1(d_ff1_Z[12]), .B0(n6129), .B1(data_in[12]),
.Y(n3057) );
AO22XLTS U4984 ( .A0(n6130), .A1(d_ff1_Z[13]), .B0(n6129), .B1(data_in[13]),
.Y(n3058) );
AO22XLTS U4985 ( .A0(n6130), .A1(d_ff1_Z[14]), .B0(n6129), .B1(data_in[14]),
.Y(n3059) );
AO22XLTS U4986 ( .A0(n6130), .A1(d_ff1_Z[15]), .B0(n6129), .B1(data_in[15]),
.Y(n3060) );
AO22XLTS U4987 ( .A0(n6128), .A1(d_ff1_Z[16]), .B0(n6129), .B1(data_in[16]),
.Y(n3061) );
AO22XLTS U4988 ( .A0(n6128), .A1(d_ff1_Z[17]), .B0(n6129), .B1(data_in[17]),
.Y(n3062) );
AO22XLTS U4989 ( .A0(n6128), .A1(d_ff1_Z[18]), .B0(n6127), .B1(data_in[18]),
.Y(n3063) );
AO22XLTS U4990 ( .A0(n6128), .A1(d_ff1_Z[19]), .B0(n6127), .B1(data_in[19]),
.Y(n3064) );
AO22XLTS U4991 ( .A0(n6128), .A1(d_ff1_Z[20]), .B0(n6127), .B1(data_in[20]),
.Y(n3065) );
AO22XLTS U4992 ( .A0(n6128), .A1(d_ff1_Z[21]), .B0(n6127), .B1(data_in[21]),
.Y(n3066) );
AO22XLTS U4993 ( .A0(n6128), .A1(d_ff1_Z[22]), .B0(n6127), .B1(data_in[22]),
.Y(n3067) );
AO22XLTS U4994 ( .A0(n6128), .A1(d_ff1_Z[23]), .B0(n6127), .B1(data_in[23]),
.Y(n3068) );
AO22XLTS U4995 ( .A0(n6128), .A1(d_ff1_Z[24]), .B0(n6127), .B1(data_in[24]),
.Y(n3069) );
AO22XLTS U4996 ( .A0(n6128), .A1(d_ff1_Z[25]), .B0(n6127), .B1(data_in[25]),
.Y(n3070) );
AO22XLTS U4997 ( .A0(n6125), .A1(d_ff1_Z[26]), .B0(n6127), .B1(data_in[26]),
.Y(n3071) );
AO22XLTS U4998 ( .A0(n6125), .A1(d_ff1_Z[27]), .B0(n6127), .B1(data_in[27]),
.Y(n3072) );
AO22XLTS U4999 ( .A0(n6125), .A1(d_ff1_Z[28]), .B0(n6123), .B1(data_in[28]),
.Y(n3073) );
AO22XLTS U5000 ( .A0(n6125), .A1(d_ff1_Z[29]), .B0(n6123), .B1(data_in[29]),
.Y(n3074) );
AO22XLTS U5001 ( .A0(n6125), .A1(d_ff1_Z[30]), .B0(n6123), .B1(data_in[30]),
.Y(n3075) );
AO22XLTS U5002 ( .A0(n6125), .A1(d_ff1_Z[31]), .B0(n6123), .B1(data_in[31]),
.Y(n3076) );
AO22XLTS U5003 ( .A0(n6125), .A1(d_ff1_Z[32]), .B0(n6123), .B1(data_in[32]),
.Y(n3077) );
AO22XLTS U5004 ( .A0(n6125), .A1(d_ff1_Z[33]), .B0(n6123), .B1(data_in[33]),
.Y(n3078) );
AO22XLTS U5005 ( .A0(n6125), .A1(d_ff1_Z[34]), .B0(n6123), .B1(data_in[34]),
.Y(n3079) );
AO22XLTS U5006 ( .A0(n6125), .A1(d_ff1_Z[35]), .B0(n6123), .B1(data_in[35]),
.Y(n3080) );
AO22XLTS U5007 ( .A0(n6121), .A1(d_ff1_Z[36]), .B0(n6123), .B1(data_in[36]),
.Y(n3081) );
AO22XLTS U5008 ( .A0(n6121), .A1(d_ff1_Z[37]), .B0(n6123), .B1(data_in[37]),
.Y(n3082) );
AO22XLTS U5009 ( .A0(n6121), .A1(d_ff1_Z[38]), .B0(n6126), .B1(data_in[38]),
.Y(n3083) );
AO22XLTS U5010 ( .A0(n6121), .A1(d_ff1_Z[39]), .B0(n6131), .B1(data_in[39]),
.Y(n3084) );
AO22XLTS U5011 ( .A0(n6121), .A1(d_ff1_Z[40]), .B0(n6126), .B1(data_in[40]),
.Y(n3085) );
AO22XLTS U5012 ( .A0(n6121), .A1(d_ff1_Z[41]), .B0(n6124), .B1(data_in[41]),
.Y(n3086) );
AO22XLTS U5013 ( .A0(n6121), .A1(d_ff1_Z[42]), .B0(n6124), .B1(data_in[42]),
.Y(n3087) );
AO22XLTS U5014 ( .A0(n6121), .A1(d_ff1_Z[43]), .B0(n6131), .B1(data_in[43]),
.Y(n3088) );
AO22XLTS U5015 ( .A0(n6121), .A1(d_ff1_Z[44]), .B0(n6124), .B1(data_in[44]),
.Y(n3089) );
AO22XLTS U5016 ( .A0(n6121), .A1(d_ff1_Z[45]), .B0(n6131), .B1(data_in[45]),
.Y(n3090) );
AO22XLTS U5017 ( .A0(n6120), .A1(d_ff1_Z[46]), .B0(n6124), .B1(data_in[46]),
.Y(n3091) );
AO22XLTS U5018 ( .A0(n6120), .A1(d_ff1_Z[47]), .B0(n6119), .B1(data_in[47]),
.Y(n3092) );
AO22XLTS U5019 ( .A0(n6120), .A1(d_ff1_Z[48]), .B0(n6124), .B1(data_in[48]),
.Y(n3093) );
AO22XLTS U5020 ( .A0(n6120), .A1(d_ff1_Z[49]), .B0(n6124), .B1(data_in[49]),
.Y(n3094) );
AO22XLTS U5021 ( .A0(n6120), .A1(d_ff1_Z[50]), .B0(n6131), .B1(data_in[50]),
.Y(n3095) );
AO22XLTS U5022 ( .A0(n6120), .A1(d_ff1_Z[51]), .B0(n6131), .B1(data_in[51]),
.Y(n3096) );
AO22XLTS U5023 ( .A0(n6120), .A1(d_ff1_Z[52]), .B0(n6132), .B1(data_in[52]),
.Y(n3097) );
AO22XLTS U5024 ( .A0(n6120), .A1(d_ff1_Z[53]), .B0(n6126), .B1(data_in[53]),
.Y(n3098) );
AO22XLTS U5025 ( .A0(n6120), .A1(d_ff1_Z[54]), .B0(n6126), .B1(data_in[54]),
.Y(n3099) );
AO22XLTS U5026 ( .A0(n6120), .A1(d_ff1_Z[55]), .B0(n6124), .B1(data_in[55]),
.Y(n3100) );
AO22XLTS U5027 ( .A0(n6118), .A1(d_ff1_Z[56]), .B0(n6124), .B1(data_in[56]),
.Y(n3101) );
AO22XLTS U5028 ( .A0(n6118), .A1(d_ff1_Z[57]), .B0(n6131), .B1(data_in[57]),
.Y(n3102) );
AO22XLTS U5029 ( .A0(n6118), .A1(d_ff1_Z[58]), .B0(n6122), .B1(data_in[58]),
.Y(n3103) );
AO22XLTS U5030 ( .A0(n6118), .A1(d_ff1_Z[59]), .B0(n6122), .B1(data_in[59]),
.Y(n3104) );
AO22XLTS U5031 ( .A0(n6118), .A1(d_ff1_Z[60]), .B0(n6122), .B1(data_in[60]),
.Y(n3105) );
AO22XLTS U5032 ( .A0(n6118), .A1(d_ff1_Z[61]), .B0(n6122), .B1(data_in[61]),
.Y(n3106) );
AO22XLTS U5033 ( .A0(n6118), .A1(d_ff1_Z[62]), .B0(n6122), .B1(data_in[62]),
.Y(n3107) );
MXI2X2TS U5034 ( .A(n5014), .B(n5315), .S0(n5013), .Y(n3192) );
INVX2TS U5035 ( .A(n6475), .Y(n5422) );
INVX2TS U5036 ( .A(n5990), .Y(n4806) );
OR2X2TS U5037 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[5]), .Y(n4647) );
INVX2TS U5038 ( .A(n4647), .Y(n5360) );
CLKBUFX2TS U5039 ( .A(n3871), .Y(n6928) );
INVX2TS U5040 ( .A(n3181), .Y(n5256) );
INVX2TS U5041 ( .A(n4755), .Y(n3205) );
INVX2TS U5042 ( .A(n4755), .Y(n3206) );
INVX2TS U5043 ( .A(n5360), .Y(n3207) );
INVX2TS U5044 ( .A(n3207), .Y(n3208) );
INVX2TS U5045 ( .A(n3207), .Y(n3209) );
INVX2TS U5046 ( .A(n6476), .Y(n5448) );
INVX2TS U5047 ( .A(n6475), .Y(n3210) );
INVX2TS U5048 ( .A(n6475), .Y(n3211) );
INVX2TS U5049 ( .A(cont_iter_out[3]), .Y(n3212) );
INVX2TS U5050 ( .A(n6580), .Y(n3215) );
INVX2TS U5051 ( .A(n3202), .Y(n3222) );
OAI21X1TS U5052 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]),
.A1(n3756), .B0(n3780), .Y(n3757) );
OAI211XLTS U5053 ( .A0(n6109), .A1(n4189), .B0(n3961), .C0(n6095), .Y(n3112)
);
OAI21XLTS U5054 ( .A0(n6109), .A1(n6110), .B0(n4124), .Y(n3124) );
OAI21XLTS U5055 ( .A0(n3297), .A1(n6114), .B0(n4165), .Y(n3156) );
AOI222X4TS U5056 ( .A0(n4051), .A1(d_ff2_Z[24]), .B0(n4080), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n4034), .Y(n4007) );
AOI222X4TS U5057 ( .A0(n4081), .A1(d_ff2_Z[27]), .B0(n4080), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n4079), .Y(n4057) );
AOI222X4TS U5058 ( .A0(n6293), .A1(d_ff2_Z[22]), .B0(n4071), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n4034), .Y(n4005) );
AOI222X4TS U5059 ( .A0(n4051), .A1(d_ff2_Z[9]), .B0(n4037), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n4036), .Y(n4028) );
AOI222X4TS U5060 ( .A0(n6151), .A1(d_ff2_Z[5]), .B0(n4037), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n4034), .Y(n4035) );
AOI222X4TS U5061 ( .A0(n6151), .A1(d_ff2_Z[7]), .B0(n4037), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n4036), .Y(n4032) );
AOI222X4TS U5062 ( .A0(n4051), .A1(d_ff2_Z[10]), .B0(n4037), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n4036), .Y(n4030) );
AOI222X4TS U5063 ( .A0(n4081), .A1(d_ff2_Z[29]), .B0(n4080), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n4079), .Y(n4058) );
AOI222X4TS U5064 ( .A0(n4051), .A1(d_ff2_Z[14]), .B0(n4071), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n4036), .Y(n4003) );
AOI222X4TS U5065 ( .A0(n4085), .A1(d_ff2_Z[12]), .B0(n4037), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n4036), .Y(n4029) );
AOI222X4TS U5066 ( .A0(n4095), .A1(d_ff2_Z[37]), .B0(n4069), .B1(d_ff1_Z[37]), .C0(d_ff_Zn[37]), .C1(n4083), .Y(n4059) );
AOI222X4TS U5067 ( .A0(n4085), .A1(d_ff2_Z[40]), .B0(n4084), .B1(d_ff1_Z[40]), .C0(d_ff_Zn[40]), .C1(n4083), .Y(n4060) );
AOI222X4TS U5068 ( .A0(n4085), .A1(d_ff2_Z[38]), .B0(n4066), .B1(d_ff1_Z[38]), .C0(d_ff_Zn[38]), .C1(n4083), .Y(n4062) );
AOI222X4TS U5069 ( .A0(n4099), .A1(d_ff2_Z[36]), .B0(n4066), .B1(d_ff1_Z[36]), .C0(d_ff_Zn[36]), .C1(n4083), .Y(n4053) );
AOI222X4TS U5070 ( .A0(n4085), .A1(d_ff2_Z[42]), .B0(n4084), .B1(d_ff1_Z[42]), .C0(d_ff_Zn[42]), .C1(n4083), .Y(n4055) );
AOI222X4TS U5071 ( .A0(n4081), .A1(d_ff2_Z[44]), .B0(n4069), .B1(d_ff1_Z[44]), .C0(d_ff_Zn[44]), .C1(n4083), .Y(n4056) );
AOI222X4TS U5072 ( .A0(n4095), .A1(d_ff2_Z[33]), .B0(n4080), .B1(d_ff1_Z[33]), .C0(d_ff_Zn[33]), .C1(n4079), .Y(n4049) );
NAND2X1TS U5073 ( .A(n3366), .B(n3293), .Y(n3381) );
OR2X1TS U5074 ( .A(n5133), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n5004) );
CLKBUFX3TS U5075 ( .A(n6928), .Y(n6927) );
INVX2TS U5076 ( .A(n6466), .Y(n6023) );
NAND3X2TS U5077 ( .A(n5122), .B(n5121), .C(n5120), .Y(n5229) );
INVX2TS U5078 ( .A(n4681), .Y(n3224) );
NAND3X2TS U5079 ( .A(n3826), .B(n3825), .C(n3824), .Y(n5304) );
OAI21XLTS U5080 ( .A0(n4539), .A1(n5441), .B0(n3956), .Y(n1685) );
OAI222X4TS U5081 ( .A0(n5441), .A1(n5403), .B0(n5440), .B1(n5402), .C0(n6806), .C1(n5422), .Y(n1725) );
OAI222X4TS U5082 ( .A0(n5441), .A1(n5439), .B0(n5397), .B1(n5438), .C0(n6786), .C1(n5450), .Y(n1734) );
OAI222X4TS U5083 ( .A0(n3245), .A1(n5409), .B0(n5441), .B1(n5408), .C0(n6770), .C1(n6478), .Y(n1702) );
OAI222X4TS U5084 ( .A0(n5435), .A1(n5417), .B0(n5441), .B1(n5416), .C0(n6798), .C1(n6478), .Y(n1707) );
OAI222X4TS U5085 ( .A0(n5445), .A1(n5439), .B0(n5441), .B1(n5438), .C0(n6814), .C1(n5433), .Y(n1688) );
CLKINVX3TS U5086 ( .A(n5057), .Y(n5047) );
INVX2TS U5087 ( .A(n5960), .Y(n5962) );
OAI21XLTS U5088 ( .A0(n5966), .A1(n5960), .B0(n5961), .Y(n5943) );
NOR2XLTS U5089 ( .A(n5960), .B(n5936), .Y(n3554) );
NOR2X2TS U5090 ( .A(n3273), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n5960) );
NAND3X2TS U5091 ( .A(n5188), .B(n5187), .C(n5186), .Y(n5327) );
OR2X1TS U5092 ( .A(n5183), .B(n3236), .Y(n5188) );
NAND3X2TS U5093 ( .A(n5074), .B(n5073), .C(n5072), .Y(n5332) );
NAND3X2TS U5094 ( .A(n5017), .B(n5016), .C(n5015), .Y(n5331) );
NAND3X2TS U5095 ( .A(n5065), .B(n5064), .C(n5063), .Y(n5324) );
OR2X1TS U5096 ( .A(n5183), .B(n6702), .Y(n5065) );
OAI21XLTS U5097 ( .A0(n6323), .A1(d_ff3_LUT_out[5]), .B0(n6116), .Y(n6104)
);
INVX2TS U5098 ( .A(n5364), .Y(n3225) );
CLKBUFX3TS U5099 ( .A(n7007), .Y(n7010) );
NAND3X2TS U5100 ( .A(n5140), .B(n5139), .C(n5138), .Y(n5230) );
NAND3X2TS U5101 ( .A(n5011), .B(n5010), .C(n5009), .Y(n5322) );
NAND3X2TS U5102 ( .A(n5085), .B(n5084), .C(n5083), .Y(n5106) );
BUFX3TS U5103 ( .A(n7001), .Y(n7000) );
CLKINVX3TS U5104 ( .A(n4458), .Y(n4706) );
BUFX3TS U5105 ( .A(n3870), .Y(n7001) );
NAND2X1TS U5106 ( .A(n4105), .B(n6082), .Y(n6084) );
AOI21X2TS U5107 ( .A0(cont_iter_out[1]), .A1(n3183), .B0(n6110), .Y(n6082)
);
BUFX3TS U5108 ( .A(n7009), .Y(n7008) );
AOI221X1TS U5109 ( .A0(n6658), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .B1(n6630), .C0(n6501), .Y(
n6504) );
AOI222X1TS U5110 ( .A0(n4294), .A1(data_output[57]), .B0(n4204), .B1(
d_ff_Yn[57]), .C0(n4297), .C1(d_ff_Xn[57]), .Y(n4290) );
INVX2TS U5111 ( .A(n3200), .Y(n3226) );
AOI222X1TS U5112 ( .A0(n4294), .A1(data_output[55]), .B0(n4204), .B1(
d_ff_Yn[55]), .C0(n4297), .C1(d_ff_Xn[55]), .Y(n4292) );
AOI222X1TS U5113 ( .A0(n4294), .A1(data_output[53]), .B0(n4204), .B1(
d_ff_Yn[53]), .C0(n4313), .C1(d_ff_Xn[53]), .Y(n4285) );
INVX2TS U5114 ( .A(n3199), .Y(n3227) );
INVX2TS U5115 ( .A(n3201), .Y(n3228) );
INVX2TS U5116 ( .A(n3189), .Y(n3229) );
INVX2TS U5117 ( .A(n3203), .Y(n3230) );
INVX2TS U5118 ( .A(n3188), .Y(n3231) );
AOI222X1TS U5119 ( .A0(n4294), .A1(data_output[52]), .B0(n4204), .B1(
d_ff_Yn[52]), .C0(n4313), .C1(d_ff_Xn[52]), .Y(n4288) );
AOI222X1TS U5120 ( .A0(n4286), .A1(data_output[58]), .B0(n4204), .B1(
d_ff_Yn[58]), .C0(n4297), .C1(d_ff_Xn[58]), .Y(n4287) );
AOI222X1TS U5121 ( .A0(n4294), .A1(data_output[54]), .B0(n4229), .B1(
d_ff_Yn[54]), .C0(n4297), .C1(d_ff_Xn[54]), .Y(n4295) );
AOI222X1TS U5122 ( .A0(n4286), .A1(data_output[59]), .B0(n4204), .B1(
d_ff_Yn[59]), .C0(n4297), .C1(d_ff_Xn[59]), .Y(n4298) );
AOI222X1TS U5123 ( .A0(n4294), .A1(data_output[50]), .B0(n4229), .B1(
d_ff_Yn[50]), .C0(n4313), .C1(d_ff_Xn[50]), .Y(n4291) );
AOI222X1TS U5124 ( .A0(n4255), .A1(data_output[47]), .B0(n4254), .B1(
d_ff_Yn[47]), .C0(n4253), .C1(d_ff_Xn[47]), .Y(n4205) );
AOI222X1TS U5125 ( .A0(n4294), .A1(data_output[48]), .B0(n4254), .B1(
d_ff_Yn[48]), .C0(n4253), .C1(d_ff_Xn[48]), .Y(n4227) );
AOI222X1TS U5126 ( .A0(n4294), .A1(data_output[49]), .B0(n4254), .B1(
d_ff_Yn[49]), .C0(n4253), .C1(d_ff_Xn[49]), .Y(n4225) );
AOI222X1TS U5127 ( .A0(n4255), .A1(data_output[44]), .B0(n4254), .B1(
d_ff_Yn[44]), .C0(n4253), .C1(d_ff_Xn[44]), .Y(n4232) );
AOI222X1TS U5128 ( .A0(n4268), .A1(data_output[33]), .B0(n4267), .B1(
d_ff_Yn[33]), .C0(n4266), .C1(d_ff_Xn[33]), .Y(n4230) );
AOI222X1TS U5129 ( .A0(n4268), .A1(data_output[34]), .B0(n4267), .B1(
d_ff_Yn[34]), .C0(n4266), .C1(d_ff_Xn[34]), .Y(n4239) );
AOI222X1TS U5130 ( .A0(n4236), .A1(data_output[3]), .B0(n4235), .B1(
d_ff_Yn[3]), .C0(n4234), .C1(d_ff_Xn[3]), .Y(n4237) );
AOI222X1TS U5131 ( .A0(n4255), .A1(data_output[46]), .B0(n4254), .B1(
d_ff_Yn[46]), .C0(n4253), .C1(d_ff_Xn[46]), .Y(n4242) );
AOI222X1TS U5132 ( .A0(n4255), .A1(data_output[45]), .B0(n4254), .B1(
d_ff_Yn[45]), .C0(n4253), .C1(d_ff_Xn[45]), .Y(n4241) );
AOI222X1TS U5133 ( .A0(n4268), .A1(data_output[35]), .B0(n4267), .B1(
d_ff_Yn[35]), .C0(n4266), .C1(d_ff_Xn[35]), .Y(n4244) );
AOI222X1TS U5134 ( .A0(n4255), .A1(data_output[42]), .B0(n4254), .B1(
d_ff_Yn[42]), .C0(n4253), .C1(d_ff_Xn[42]), .Y(n4245) );
AOI222X1TS U5135 ( .A0(n4268), .A1(data_output[36]), .B0(n4267), .B1(
d_ff_Yn[36]), .C0(n4266), .C1(d_ff_Xn[36]), .Y(n4248) );
AOI222X1TS U5136 ( .A0(n4255), .A1(data_output[43]), .B0(n4254), .B1(
d_ff_Yn[43]), .C0(n4253), .C1(d_ff_Xn[43]), .Y(n4246) );
AOI222X1TS U5137 ( .A0(n4255), .A1(data_output[41]), .B0(n4254), .B1(
d_ff_Yn[41]), .C0(n4253), .C1(d_ff_Xn[41]), .Y(n4250) );
AOI222X1TS U5138 ( .A0(n4255), .A1(data_output[39]), .B0(n4267), .B1(
d_ff_Yn[39]), .C0(n4266), .C1(d_ff_Xn[39]), .Y(n4249) );
AOI222X1TS U5139 ( .A0(n4255), .A1(data_output[40]), .B0(n4254), .B1(
d_ff_Yn[40]), .C0(n4253), .C1(d_ff_Xn[40]), .Y(n4256) );
AOI222X1TS U5140 ( .A0(n4255), .A1(data_output[38]), .B0(n4267), .B1(
d_ff_Yn[38]), .C0(n4266), .C1(d_ff_Xn[38]), .Y(n4252) );
AOI222X1TS U5141 ( .A0(n4268), .A1(data_output[28]), .B0(n4260), .B1(
d_ff_Yn[28]), .C0(n4259), .C1(d_ff_Xn[28]), .Y(n4261) );
AOI222X1TS U5142 ( .A0(n4268), .A1(data_output[37]), .B0(n4267), .B1(
d_ff_Yn[37]), .C0(n4266), .C1(d_ff_Xn[37]), .Y(n4258) );
AOI222X1TS U5143 ( .A0(n4264), .A1(data_output[12]), .B0(n4263), .B1(
d_ff_Yn[12]), .C0(n4262), .C1(d_ff_Xn[12]), .Y(n4216) );
AOI222X1TS U5144 ( .A0(n4268), .A1(data_output[31]), .B0(n4267), .B1(
d_ff_Yn[31]), .C0(n4266), .C1(d_ff_Xn[31]), .Y(n4269) );
AOI222X1TS U5145 ( .A0(n4268), .A1(data_output[30]), .B0(n4267), .B1(
d_ff_Yn[30]), .C0(n4266), .C1(d_ff_Xn[30]), .Y(n4257) );
AOI222X1TS U5146 ( .A0(n4264), .A1(data_output[15]), .B0(n4263), .B1(
d_ff_Yn[15]), .C0(n4262), .C1(d_ff_Xn[15]), .Y(n4265) );
AOI222X1TS U5147 ( .A0(n4268), .A1(data_output[32]), .B0(n4267), .B1(
d_ff_Yn[32]), .C0(n4266), .C1(d_ff_Xn[32]), .Y(n4247) );
AOI222X1TS U5148 ( .A0(n4264), .A1(data_output[17]), .B0(n4263), .B1(
d_ff_Yn[17]), .C0(n4262), .C1(d_ff_Xn[17]), .Y(n4251) );
AOI222X1TS U5149 ( .A0(n4268), .A1(data_output[29]), .B0(n4260), .B1(
d_ff_Yn[29]), .C0(n4259), .C1(d_ff_Xn[29]), .Y(n4240) );
AOI222X1TS U5150 ( .A0(n4264), .A1(data_output[14]), .B0(n4263), .B1(
d_ff_Yn[14]), .C0(n4262), .C1(d_ff_Xn[14]), .Y(n4243) );
AOI222X1TS U5151 ( .A0(n4226), .A1(data_output[18]), .B0(n4263), .B1(
d_ff_Yn[18]), .C0(n4262), .C1(d_ff_Xn[18]), .Y(n4224) );
AOI222X1TS U5152 ( .A0(n4264), .A1(data_output[13]), .B0(n4263), .B1(
d_ff_Yn[13]), .C0(n4262), .C1(d_ff_Xn[13]), .Y(n4238) );
AOI222X1TS U5153 ( .A0(n4264), .A1(data_output[10]), .B0(n4263), .B1(
d_ff_Yn[10]), .C0(n4262), .C1(d_ff_Xn[10]), .Y(n4215) );
AOI222X1TS U5154 ( .A0(n4264), .A1(data_output[16]), .B0(n4263), .B1(
d_ff_Yn[16]), .C0(n4262), .C1(d_ff_Xn[16]), .Y(n4220) );
AOI222X1TS U5155 ( .A0(n4236), .A1(data_output[5]), .B0(n4235), .B1(
d_ff_Yn[5]), .C0(n4234), .C1(d_ff_Xn[5]), .Y(n4222) );
AOI222X1TS U5156 ( .A0(n4236), .A1(data_output[6]), .B0(n4235), .B1(
d_ff_Yn[6]), .C0(n4234), .C1(d_ff_Xn[6]), .Y(n4214) );
AOI222X1TS U5157 ( .A0(n4264), .A1(data_output[8]), .B0(n4235), .B1(
d_ff_Yn[8]), .C0(n4234), .C1(d_ff_Xn[8]), .Y(n4208) );
AOI222X1TS U5158 ( .A0(n4226), .A1(data_output[20]), .B0(n4260), .B1(
d_ff_Yn[20]), .C0(n4259), .C1(d_ff_Xn[20]), .Y(n4219) );
AOI222X1TS U5159 ( .A0(n4264), .A1(data_output[9]), .B0(n4235), .B1(
d_ff_Yn[9]), .C0(n4234), .C1(d_ff_Xn[9]), .Y(n4218) );
AOI222X1TS U5160 ( .A0(n4226), .A1(data_output[21]), .B0(n4260), .B1(
d_ff_Yn[21]), .C0(n4259), .C1(d_ff_Xn[21]), .Y(n4212) );
AOI222X1TS U5161 ( .A0(n4226), .A1(data_output[22]), .B0(n4260), .B1(
d_ff_Yn[22]), .C0(n4259), .C1(d_ff_Xn[22]), .Y(n4217) );
AOI222X1TS U5162 ( .A0(n4264), .A1(data_output[11]), .B0(n4263), .B1(
d_ff_Yn[11]), .C0(n4262), .C1(d_ff_Xn[11]), .Y(n4206) );
AOI222X1TS U5163 ( .A0(n4226), .A1(data_output[27]), .B0(n4260), .B1(
d_ff_Yn[27]), .C0(n4259), .C1(d_ff_Xn[27]), .Y(n4211) );
AOI222X1TS U5164 ( .A0(n4226), .A1(data_output[26]), .B0(n4260), .B1(
d_ff_Yn[26]), .C0(n4259), .C1(d_ff_Xn[26]), .Y(n4210) );
AOI222X1TS U5165 ( .A0(n4226), .A1(data_output[24]), .B0(n4260), .B1(
d_ff_Yn[24]), .C0(n4259), .C1(d_ff_Xn[24]), .Y(n4209) );
AOI222X1TS U5166 ( .A0(n4226), .A1(data_output[23]), .B0(n4260), .B1(
d_ff_Yn[23]), .C0(n4259), .C1(d_ff_Xn[23]), .Y(n4207) );
AOI222X1TS U5167 ( .A0(n4236), .A1(data_output[4]), .B0(n4235), .B1(
d_ff_Yn[4]), .C0(n4234), .C1(d_ff_Xn[4]), .Y(n4223) );
AOI222X1TS U5168 ( .A0(n4226), .A1(data_output[25]), .B0(n4260), .B1(
d_ff_Yn[25]), .C0(n4259), .C1(d_ff_Xn[25]), .Y(n4213) );
AOI222X1TS U5169 ( .A0(n4236), .A1(data_output[1]), .B0(n4235), .B1(
d_ff_Yn[1]), .C0(n4234), .C1(d_ff_Xn[1]), .Y(n4231) );
AOI222X1TS U5170 ( .A0(n4236), .A1(data_output[2]), .B0(n4235), .B1(
d_ff_Yn[2]), .C0(n4234), .C1(d_ff_Xn[2]), .Y(n4228) );
AOI222X1TS U5171 ( .A0(n4236), .A1(data_output[0]), .B0(n4235), .B1(
d_ff_Yn[0]), .C0(n4234), .C1(d_ff_Xn[0]), .Y(n4233) );
INVX2TS U5172 ( .A(n3198), .Y(n3232) );
CLKBUFX3TS U5173 ( .A(n3870), .Y(n7007) );
INVX2TS U5174 ( .A(n3190), .Y(n3233) );
CLKBUFX3TS U5175 ( .A(n7001), .Y(n7006) );
CLKBUFX3TS U5176 ( .A(n7006), .Y(n7011) );
NOR2X2TS U5177 ( .A(n6670), .B(n6061), .Y(n6062) );
NOR2X2TS U5178 ( .A(n6670), .B(n6071), .Y(n6107) );
OAI221XLTS U5179 ( .A0(n6646), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .B0(n6610), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .C0(n6516), .Y(n6521) );
OAI221XLTS U5180 ( .A0(n6611), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B0(n6601), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .C0(n6540), .Y(n6545) );
INVX2TS U5181 ( .A(n3197), .Y(n3235) );
NOR3X2TS U5182 ( .A(d_ff2_X[57]), .B(d_ff2_X[56]), .C(intadd_46_n1), .Y(
n6157) );
OAI221X1TS U5183 ( .A0(n6619), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .B0(n6648), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[60]), .C0(n6517), .Y(n6520) );
AOI221X1TS U5184 ( .A0(n6694), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[44]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .B1(n6616), .C0(n6508),
.Y(n6513) );
OAI221X1TS U5185 ( .A0(n6680), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[38]), .B0(n6650), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .C0(n6515), .Y(n6522) );
INVX2TS U5186 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[51]), .Y(
n3236) );
AOI222X1TS U5187 ( .A0(n4954), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[52]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[52]), .B1(n6572), .C0(n4953),
.C1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .Y(n4955) );
OAI221X1TS U5188 ( .A0(n6605), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B0(n6617), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .C0(n6523), .Y(n6530) );
OAI221XLTS U5189 ( .A0(n6602), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .B0(n6607), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .C0(n6488), .Y(n6493) );
AOI221X1TS U5190 ( .A0(n6622), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .B1(n6613), .C0(n6499),
.Y(n6506) );
OAI221XLTS U5191 ( .A0(n6626), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .B0(n6649), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[59]), .C0(n6526), .Y(n6527) );
INVX2TS U5192 ( .A(n3194), .Y(n3238) );
INVX2TS U5193 ( .A(n3184), .Y(n3239) );
OAI221X1TS U5194 ( .A0(n6634), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .B0(n6614), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .C0(n6541), .Y(n6544) );
OAI211XLTS U5195 ( .A0(n6612), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .B0(n3321), .C0(n3320), .Y(n3324) );
OAI221XLTS U5196 ( .A0(n6612), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .B0(n6693), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]), .C0(n6483), .Y(
n6484) );
AOI221X1TS U5197 ( .A0(n6629), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .B1(n6656), .C0(n6502),
.Y(n6503) );
OAI221XLTS U5198 ( .A0(n6623), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]), .B0(n6677), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .C0(n6518), .Y(n6519) );
AOI32X1TS U5199 ( .A0(n6621), .A1(n3351), .A2(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .B1(n6620), .Y(n3352) );
OAI221XLTS U5200 ( .A0(n6620), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .B0(n6621), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .C0(n6532), .Y(n6537) );
OAI221X1TS U5201 ( .A0(n6609), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B0(n6647), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[58]), .C0(n6487), .Y(n6494) );
AOI32X1TS U5202 ( .A0(n6606), .A1(n3370), .A2(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B1(n6605), .Y(n3371) );
OAI221XLTS U5203 ( .A0(n6606), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .B0(n6604), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .C0(n6490), .Y(n6491) );
OAI221XLTS U5204 ( .A0(n6644), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .B0(n6624), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]), .C0(n6542), .Y(n6543) );
AOI221X1TS U5205 ( .A0(n6633), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .B1(n6625), .C0(n6485),
.Y(n6497) );
OAI211XLTS U5206 ( .A0(n5370), .A1(n6734), .B0(n5369), .C0(n5368), .Y(n5373)
);
OAI211XLTS U5207 ( .A0(n5370), .A1(n6755), .B0(n3951), .C0(n3950), .Y(n3953)
);
NOR2XLTS U5208 ( .A(n5370), .B(n6727), .Y(n4637) );
NOR2XLTS U5209 ( .A(n5370), .B(n6728), .Y(n4597) );
NOR2XLTS U5210 ( .A(n5370), .B(n6726), .Y(n4551) );
NOR2XLTS U5211 ( .A(n5370), .B(n6668), .Y(n4752) );
NOR2XLTS U5212 ( .A(n5370), .B(n6729), .Y(n4577) );
OAI221X1TS U5213 ( .A0(n6600), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[34]), .B0(n6681), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[47]), .C0(n6525), .Y(n6528) );
OAI221X1TS U5214 ( .A0(n6599), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[42]), .B0(n6682), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[40]), .C0(n6489), .Y(n6492) );
OAI21XLTS U5215 ( .A0(n3941), .A1(n6593), .B0(n3940), .Y(n2270) );
NOR2BX1TS U5216 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[4]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4391) );
NOR2BX1TS U5217 ( .AN(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[5]),
.B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4393) );
OAI21XLTS U5218 ( .A0(n3601), .A1(n3578), .B0(n3577), .Y(n3579) );
OAI21X1TS U5219 ( .A0(n3693), .A1(n3572), .B0(n3571), .Y(n3598) );
OAI211XLTS U5220 ( .A0(n6076), .A1(n4024), .B0(n3972), .C0(n3971), .Y(n3143)
);
OAI21XLTS U5221 ( .A0(d_ff3_LUT_out[19]), .A1(n6102), .B0(n6084), .Y(n6085)
);
OAI211XLTS U5222 ( .A0(n6064), .A1(n6091), .B0(n3963), .C0(n3962), .Y(n3114)
);
OAI21XLTS U5223 ( .A0(n6556), .A1(n6573), .B0(n6765), .Y(n6555) );
AOI211X1TS U5224 ( .A0(n3379), .A1(n3378), .B0(n3377), .C0(n3376), .Y(n3380)
);
NAND2X2TS U5225 ( .A(n4723), .B(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2),
.Y(n4590) );
AOI211X4TS U5226 ( .A0(n5374), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]), .B0(n3953), .C0(n3952),
.Y(n4539) );
AOI222X4TS U5227 ( .A0(n4095), .A1(d_ff2_Z[34]), .B0(n4066), .B1(d_ff1_Z[34]), .C0(d_ff_Zn[34]), .C1(n4079), .Y(n4061) );
AOI222X4TS U5228 ( .A0(n4081), .A1(d_ff2_Z[45]), .B0(n4069), .B1(d_ff1_Z[45]), .C0(d_ff_Zn[45]), .C1(n4083), .Y(n4048) );
AOI222X4TS U5229 ( .A0(n4085), .A1(d_ff2_Z[43]), .B0(n4084), .B1(d_ff1_Z[43]), .C0(d_ff_Zn[43]), .C1(n4083), .Y(n4078) );
AOI222X4TS U5230 ( .A0(n4085), .A1(d_ff2_Z[39]), .B0(n4084), .B1(d_ff1_Z[39]), .C0(d_ff_Zn[39]), .C1(n4083), .Y(n4050) );
AOI222X4TS U5231 ( .A0(n4085), .A1(d_ff2_Z[41]), .B0(n4084), .B1(d_ff1_Z[41]), .C0(d_ff_Zn[41]), .C1(n4083), .Y(n4086) );
AOI222X4TS U5232 ( .A0(n4081), .A1(d_ff2_Z[28]), .B0(n4080), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n4079), .Y(n4063) );
AOI222X4TS U5233 ( .A0(n4081), .A1(d_ff2_Z[31]), .B0(n4080), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n4079), .Y(n4054) );
AOI222X4TS U5234 ( .A0(n4081), .A1(d_ff2_Z[15]), .B0(n4071), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n4036), .Y(n4001) );
AOI222X4TS U5235 ( .A0(n4081), .A1(d_ff2_Z[30]), .B0(n4080), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n4079), .Y(n4068) );
AOI222X4TS U5236 ( .A0(n4085), .A1(d_ff2_Z[17]), .B0(n4071), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n4034), .Y(n4004) );
AOI222X4TS U5237 ( .A0(n4081), .A1(d_ff2_Z[32]), .B0(n4080), .B1(d_ff1_Z[32]), .C0(d_ff_Zn[32]), .C1(n4079), .Y(n4082) );
AOI222X4TS U5238 ( .A0(n4051), .A1(d_ff2_Z[13]), .B0(n4037), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n4036), .Y(n4026) );
AOI222X4TS U5239 ( .A0(n6293), .A1(d_ff2_Z[19]), .B0(n4071), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n4034), .Y(n4002) );
AOI222X4TS U5240 ( .A0(n6293), .A1(d_ff2_Z[18]), .B0(n4071), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n4034), .Y(n3997) );
AOI222X4TS U5241 ( .A0(n4085), .A1(d_ff2_Z[16]), .B0(n4071), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n4034), .Y(n3999) );
AOI222X4TS U5242 ( .A0(n4051), .A1(d_ff2_Z[6]), .B0(n4037), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n4036), .Y(n4027) );
AOI222X4TS U5243 ( .A0(n4085), .A1(d_ff2_Z[20]), .B0(n4071), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n4079), .Y(n4072) );
AOI222X4TS U5244 ( .A0(n4051), .A1(d_ff2_Z[8]), .B0(n4037), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n4036), .Y(n4038) );
AOI222X4TS U5245 ( .A0(n6293), .A1(d_ff2_Z[21]), .B0(n4071), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n4034), .Y(n4000) );
AOI222X4TS U5246 ( .A0(n4051), .A1(d_ff2_Z[11]), .B0(n4037), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n4036), .Y(n4031) );
AOI222X4TS U5247 ( .A0(n4051), .A1(d_ff2_Z[26]), .B0(n4080), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n4079), .Y(n4052) );
AOI222X4TS U5248 ( .A0(n6293), .A1(d_ff2_Z[23]), .B0(n4071), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n4034), .Y(n4006) );
AOI222X4TS U5249 ( .A0(n4051), .A1(d_ff2_Z[25]), .B0(n4080), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n4034), .Y(n3998) );
MXI2X2TS U5250 ( .A(n5217), .B(n5014), .S0(n5013), .Y(n5321) );
NOR2X2TS U5251 ( .A(n6064), .B(n6087), .Y(n6106) );
BUFX3TS U5252 ( .A(n6930), .Y(n6925) );
BUFX3TS U5253 ( .A(n3871), .Y(n6930) );
OAI33X1TS U5254 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n6757), .B0(n6669), .B1(n6636), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n6469) );
NAND3X2TS U5255 ( .A(n5102), .B(n5101), .C(n5100), .Y(n5316) );
NOR2X2TS U5256 ( .A(n5055), .B(n5054), .Y(n5224) );
OAI21X2TS U5257 ( .A0(n6841), .A1(n5058), .B0(n4956), .Y(n5315) );
NAND3X2TS U5258 ( .A(n5197), .B(n5196), .C(n5195), .Y(n5235) );
OR2X1TS U5259 ( .A(n5207), .B(n6640), .Y(n5197) );
NAND3X2TS U5260 ( .A(n5044), .B(n5043), .C(n5042), .Y(n5110) );
OR2X1TS U5261 ( .A(n5098), .B(n6705), .Y(n5044) );
OAI222X4TS U5262 ( .A0(n5441), .A1(n5426), .B0(n5435), .B1(n5424), .C0(n6804), .C1(n6578), .Y(n1721) );
OAI222X4TS U5263 ( .A0(n5441), .A1(n5409), .B0(n5423), .B1(n5408), .C0(n6779), .C1(n5418), .Y(n1720) );
INVX2TS U5264 ( .A(n5394), .Y(n3245) );
OAI222X4TS U5265 ( .A0(n5441), .A1(n5413), .B0(n5397), .B1(n5412), .C0(n6803), .C1(n6478), .Y(n1719) );
OAI211XLTS U5266 ( .A0(n4123), .A1(n6832), .B0(n6068), .C0(n4189), .Y(n3153)
);
OAI211XLTS U5267 ( .A0(n4123), .A1(n6835), .B0(n6073), .C0(n3959), .Y(n3141)
);
OAI211XLTS U5268 ( .A0(n4123), .A1(n6839), .B0(n6071), .C0(n4189), .Y(n3150)
);
INVX2TS U5269 ( .A(n3246), .Y(n3247) );
INVX2TS U5270 ( .A(n3248), .Y(n3249) );
INVX2TS U5271 ( .A(n3250), .Y(n3251) );
INVX2TS U5272 ( .A(n3252), .Y(n3253) );
NOR2XLTS U5273 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[47]), .B(
n3253), .Y(n3763) );
CLKBUFX3TS U5274 ( .A(n7009), .Y(n7012) );
BUFX3TS U5275 ( .A(n7006), .Y(n7009) );
OAI21X2TS U5276 ( .A0(n3217), .A1(n3463), .B0(n3183), .Y(n6109) );
NOR2X4TS U5277 ( .A(n6670), .B(n4103), .Y(n6093) );
NAND2X1TS U5278 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[10]), .B(
n3185), .Y(n4445) );
NAND2X1TS U5279 ( .A(n4385), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]), .Y(n4401) );
NAND2X1TS U5280 ( .A(n4394), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]), .Y(n4414) );
INVX2TS U5281 ( .A(n3254), .Y(n3255) );
NOR3X2TS U5282 ( .A(d_ff2_Y[57]), .B(d_ff2_Y[56]), .C(intadd_45_n1), .Y(
n6313) );
OAI21XLTS U5283 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .A1(n6617), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .Y(n3341) );
NOR2XLTS U5284 ( .A(n3396), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[44]),
.Y(n3397) );
NAND2X1TS U5285 ( .A(n4392), .B(
inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[4]), .Y(n4409) );
NOR2X1TS U5286 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
n3185), .Y(n4433) );
NAND2X1TS U5287 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
n3182), .Y(n4434) );
NAND2X1TS U5288 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[8]), .B(
n3185), .Y(n4422) );
CLKBUFX2TS U5289 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[52]), .Y(
n3257) );
OAI21XLTS U5290 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .A1(n6614), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .Y(n3331) );
OA22X1TS U5291 ( .A0(n6601), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]),
.B0(n6607), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .Y(n3379)
);
OR2X1TS U5292 ( .A(n6789), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[45]), .Y(
n3620) );
OR2X1TS U5293 ( .A(n6787), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[49]), .Y(
n3628) );
OR2X1TS U5294 ( .A(n6788), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[47]), .Y(
n3624) );
OR2X1TS U5295 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[46]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[48]), .Y(n5516) );
OR2X1TS U5296 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[50]), .Y(n5497) );
OR2X1TS U5297 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[50]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[52]), .Y(n5535) );
OAI221X1TS U5298 ( .A0(n6645), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .B0(n6679), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .C0(n6531), .Y(
n6538) );
OAI221XLTS U5299 ( .A0(n6603), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .B0(n6643), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[57]), .C0(n6524), .Y(n6529) );
OAI221X1TS U5300 ( .A0(n6631), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[49]), .B0(n6651), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .C0(n6539), .Y(n6546) );
INVX2TS U5301 ( .A(n3258), .Y(n3259) );
INVX2TS U5302 ( .A(n3260), .Y(n3261) );
INVX2TS U5303 ( .A(n3262), .Y(n3263) );
NOR2XLTS U5304 ( .A(n6812), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .Y(
n3465) );
NAND2X1TS U5305 ( .A(n3263), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n5970) );
INVX2TS U5306 ( .A(n3264), .Y(n3265) );
INVX2TS U5307 ( .A(n3266), .Y(n3267) );
INVX2TS U5308 ( .A(n3268), .Y(n3269) );
INVX2TS U5309 ( .A(n3270), .Y(n3271) );
NOR2X1TS U5310 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n3661) );
NOR3X1TS U5311 ( .A(n3754), .B(n3274), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .Y(n3756) );
NAND2X1TS U5312 ( .A(n4178), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .Y(n4180) );
NAND2X1TS U5313 ( .A(n6800), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]),
.Y(n5716) );
INVX2TS U5314 ( .A(n3272), .Y(n3273) );
NOR2X1TS U5315 ( .A(n6786), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .Y(
n3467) );
NAND2X1TS U5316 ( .A(n3273), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n5961) );
OA22X1TS U5317 ( .A0(n6599), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[42]),
.B0(n6626), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .Y(n3401)
);
OAI21XLTS U5318 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .A1(n6626), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[42]), .Y(n3399) );
OAI221XLTS U5319 ( .A0(n6615), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .B0(n6678), .B1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .C0(n6534), .Y(n6535) );
OAI21XLTS U5320 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n4170), .Y(n3987) );
NAND2X1TS U5321 ( .A(n6623), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]),
.Y(n3388) );
CLKBUFX2TS U5322 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(
n3274) );
NOR2X4TS U5323 ( .A(n4106), .B(n3274), .Y(n4178) );
NOR2X1TS U5324 ( .A(n6624), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]),
.Y(n3396) );
OA22X1TS U5325 ( .A0(n6608), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]),
.B0(n6622), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .Y(n3360)
);
BUFX3TS U5326 ( .A(n6637), .Y(n3275) );
BUFX3TS U5327 ( .A(n6637), .Y(n3276) );
OAI21XLTS U5328 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .A1(n6625), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[40]), .Y(n3398) );
OAI21XLTS U5329 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .A1(n6602), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .Y(n3367) );
OA22X1TS U5330 ( .A0(n6600), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[34]),
.B0(n6629), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .Y(n3433)
);
OR2X1TS U5331 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[10]), .B(
n3182), .Y(n3280) );
OAI21XLTS U5332 ( .A0(n5375), .A1(n3187), .B0(n6061), .Y(n3288) );
NOR4X1TS U5333 ( .A(n3374), .B(n3373), .C(n3365), .D(n3368), .Y(n3293) );
OR2X1TS U5334 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[7]), .B(n3182), .Y(n3295) );
BUFX3TS U5335 ( .A(n4084), .Y(n4066) );
AND2X4TS U5336 ( .A(n6069), .B(n6150), .Y(n4084) );
BUFX3TS U5337 ( .A(n4202), .Y(n4286) );
INVX2TS U5338 ( .A(n6472), .Y(n4202) );
OR2X1TS U5339 ( .A(n4389), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[3]), .Y(n3298) );
OR2X2TS U5340 ( .A(n4385), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[2]), .Y(n3299) );
OR2X1TS U5341 ( .A(n4394), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[5]), .Y(n3300) );
OR2X2TS U5342 ( .A(n4384), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[1]), .Y(n3301) );
OR2X4TS U5343 ( .A(n6029), .B(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2),
.Y(n3302) );
OR2X2TS U5344 ( .A(n6029), .B(n6635), .Y(n4927) );
BUFX3TS U5345 ( .A(n6376), .Y(n6218) );
CLKBUFX2TS U5346 ( .A(n3902), .Y(n6197) );
BUFX3TS U5347 ( .A(n6119), .Y(n6126) );
BUFX3TS U5348 ( .A(n3876), .Y(n6271) );
BUFX3TS U5349 ( .A(n4043), .Y(n6232) );
NOR2X2TS U5350 ( .A(n6458), .B(n6054), .Y(n3903) );
BUFX3TS U5351 ( .A(n6250), .Y(n6343) );
BUFX3TS U5352 ( .A(n6343), .Y(n6182) );
OAI21XLTS U5353 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1(n3279),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .Y(n3319) );
OAI21XLTS U5354 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .A1(n6612),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .Y(n3322) );
OAI21XLTS U5355 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .A1(n6629), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[34]), .Y(n3431) );
OAI21XLTS U5356 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[50]),
.A1(n6664), .B0(n6706), .Y(n3805) );
NOR2X1TS U5357 ( .A(n3718), .B(n3717), .Y(n3719) );
OAI21XLTS U5358 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .A1(n6618), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .Y(n3348) );
OAI21XLTS U5359 ( .A0(n3663), .A1(n5802), .B0(n3664), .Y(n3561) );
NAND2X1TS U5360 ( .A(n3657), .B(n3562), .Y(n3564) );
INVX2TS U5361 ( .A(n5759), .Y(n5761) );
INVX2TS U5362 ( .A(n5466), .Y(n5789) );
INVX2TS U5363 ( .A(n5816), .Y(n3891) );
INVX2TS U5364 ( .A(n5871), .Y(n5873) );
OR2X1TS U5365 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[44]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[46]), .Y(n3635) );
INVX2TS U5366 ( .A(n5590), .Y(n5592) );
INVX2TS U5367 ( .A(n5745), .Y(n5747) );
NOR2XLTS U5368 ( .A(n4750), .B(n6738), .Y(n4636) );
NOR2XLTS U5369 ( .A(n4750), .B(n6755), .Y(n4751) );
OAI21XLTS U5370 ( .A0(n5695), .A1(n5745), .B0(n5746), .Y(n5697) );
INVX2TS U5371 ( .A(n3667), .Y(n5787) );
OAI21XLTS U5372 ( .A0(n5999), .A1(n5998), .B0(n5997), .Y(n6001) );
INVX2TS U5373 ( .A(n5558), .Y(n5561) );
INVX2TS U5374 ( .A(n3796), .Y(n4018) );
INVX2TS U5375 ( .A(n5602), .Y(n5605) );
INVX2TS U5376 ( .A(n3673), .Y(n5625) );
INVX2TS U5377 ( .A(n4414), .Y(n4415) );
OR2X1TS U5378 ( .A(n5098), .B(n6842), .Y(n5102) );
OR2X1TS U5379 ( .A(n5209), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[35]), .Y(n5036) );
OR2X1TS U5380 ( .A(n5207), .B(n6641), .Y(n5140) );
OR2X1TS U5381 ( .A(n6011), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n4990) );
OR2X1TS U5382 ( .A(n5183), .B(n6844), .Y(n5011) );
BUFX3TS U5383 ( .A(n4043), .Y(n6387) );
OAI21XLTS U5384 ( .A0(n5765), .A1(n5759), .B0(n5760), .Y(n3701) );
OR2X1TS U5385 ( .A(n5058), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n5030) );
NOR2X4TS U5386 ( .A(n4236), .B(n6467), .Y(n4297) );
OAI21XLTS U5387 ( .A0(n3846), .A1(n3845), .B0(n3844), .Y(n3849) );
AND3X1TS U5388 ( .A(n5000), .B(n4999), .C(n4998), .Y(n5293) );
BUFX3TS U5389 ( .A(n5164), .Y(n5225) );
OR2X1TS U5390 ( .A(n5207), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[41]), .Y(n5212) );
OR2X1TS U5391 ( .A(n5098), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[35]), .Y(n5041) );
OR2X1TS U5392 ( .A(n5209), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n5021) );
OR2X1TS U5393 ( .A(n5133), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[45]), .Y(n5123) );
INVX2TS U5394 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[0]), .Y(
n5979) );
AND3X1TS U5395 ( .A(n5077), .B(n5076), .C(n5075), .Y(n5266) );
INVX2TS U5396 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n6581) );
BUFX3TS U5397 ( .A(n4906), .Y(n4914) );
BUFX3TS U5398 ( .A(n4927), .Y(n4824) );
BUFX3TS U5399 ( .A(n4927), .Y(n4941) );
BUFX3TS U5400 ( .A(n4906), .Y(n4921) );
NAND2X2TS U5401 ( .A(n6037), .B(n6846), .Y(n6479) );
OAI211XLTS U5402 ( .A0(n6323), .A1(d_ff3_LUT_out[17]), .B0(n6088), .C0(n6087), .Y(n6089) );
NOR3BX2TS U5403 ( .AN(inst_CORDIC_FSM_v3_state_reg[5]), .B(
inst_CORDIC_FSM_v3_state_reg[4]), .C(n3900), .Y(n6056) );
OAI21XLTS U5404 ( .A0(beg_fsm_cordic), .A1(n6052), .B0(n3968), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
OAI2BB1X1TS U5405 ( .A0N(n5766), .A1N(n3615), .B0(n3614), .Y(n2047) );
OAI2BB1X1TS U5406 ( .A0N(n5553), .A1N(n3653), .B0(n3652), .Y(n2183) );
OAI211XLTS U5407 ( .A0(n4123), .A1(n6831), .B0(n4122), .C0(n6080), .Y(n3157)
);
OAI32X4TS U5408 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(
n5358), .B1(n6760), .Y(n6059) );
NAND2X1TS U5409 ( .A(n6692), .B(inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3304)
);
NAND3X2TS U5410 ( .A(n3191), .B(n3462), .C(n3291), .Y(n3709) );
NOR3X2TS U5411 ( .A(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(n3709), .Y(n3965) );
OAI22X1TS U5412 ( .A0(n6634), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .B1(n6596), .Y(n3411) );
NOR2BX1TS U5413 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[56]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .Y(n3306) );
OAI211X1TS U5414 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[60]), .A1(
n3278), .B0(n3392), .C0(n3388), .Y(n3394) );
OAI21X1TS U5415 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[58]), .A1(n3282), .B0(n3384), .Y(n3386) );
NOR4X2TS U5416 ( .A(n3306), .B(n3382), .C(n3394), .D(n3386), .Y(n3422) );
NOR2X1TS U5417 ( .A(n6631), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[49]),
.Y(n3414) );
OAI21X1TS U5418 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .A1(n6633), .B0(n3416), .Y(n3420) );
AOI211X1TS U5419 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[48]), .A1(
n6597), .B0(n3414), .C0(n3420), .Y(n3307) );
AOI21X1TS U5420 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[38]), .A1(n6764), .B0(n3439), .Y(n3438) );
OAI211X1TS U5421 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[36]), .A1(
n6627), .B0(n3438), .C0(n3427), .Y(n3429) );
OAI21X1TS U5422 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[46]), .A1(n6598), .B0(n3395), .Y(n3405) );
OAI211X1TS U5423 ( .A0(n6628), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .B0(n3310), .C0(n3433),
.Y(n3311) );
NOR2X1TS U5424 ( .A(n6619), .B(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]),
.Y(n3349) );
OAI21X1TS U5425 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .A1(n6621), .B0(n3351), .Y(n3355) );
AOI211X1TS U5426 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .A1(
n3277), .B0(n3349), .C0(n3355), .Y(n3313) );
OA22X1TS U5427 ( .A0(n6610), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]),
.B0(n6617), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .Y(n3345)
);
INVX2TS U5428 ( .A(n3339), .Y(n3316) );
AOI21X1TS U5429 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .A1(n3281), .B0(n3332), .Y(n3337) );
OAI2BB1X1TS U5430 ( .A0N(n3286), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[4]), .Y(n3317) );
OAI22X1TS U5431 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .A1(n3317),
.B0(n3286), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .Y(n3328)
);
OAI2BB1X1TS U5432 ( .A0N(n3283), .A1N(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .Y(n3318) );
OAI22X1TS U5433 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .A1(n3318),
.B0(n3283), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .Y(n3327)
);
AOI2BB2X1TS U5434 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .B1(
n6612), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .A1N(n3322),
.Y(n3323) );
AOI22X1TS U5435 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .A1(n3283),
.B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .B1(n3285), .Y(n3325)
);
OAI32X1TS U5436 ( .A0(n3328), .A1(n3327), .A2(n3326), .B0(n3325), .B1(n3327),
.Y(n3329) );
OAI2BB2XLTS U5437 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .B1(
n3331), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .A1N(n6614),
.Y(n3344) );
AOI22X1TS U5438 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .A1(n6615), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .B1(n3333), .Y(n3340) );
AOI21X1TS U5439 ( .A0(n3336), .A1(n3335), .B0(n3339), .Y(n3338) );
OAI2BB2XLTS U5440 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .B1(
n3341), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .A1N(n6617),
.Y(n3342) );
AOI211X1TS U5441 ( .A0(n3345), .A1(n3344), .B0(n3343), .C0(n3342), .Y(n3346)
);
OAI2BB2XLTS U5442 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .B1(
n3348), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .A1N(n6618),
.Y(n3359) );
AOI22X1TS U5443 ( .A0(n3350), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .B1(n6619), .Y(n3353) );
OAI32X1TS U5444 ( .A0(n3355), .A1(n3354), .A2(n3353), .B0(n3352), .B1(n3354),
.Y(n3358) );
OAI2BB2XLTS U5445 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .B1(
n3356), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .A1N(n6622),
.Y(n3357) );
AOI211X1TS U5446 ( .A0(n3360), .A1(n3359), .B0(n3358), .C0(n3357), .Y(n3361)
);
OAI21X1TS U5447 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .A1(n6606), .B0(n3370), .Y(n3374) );
NOR2BX1TS U5448 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .Y(n3365) );
AOI22X1TS U5449 ( .A0(n3369), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .B1(n6604), .Y(n3372) );
OAI32X1TS U5450 ( .A0(n3374), .A1(n3373), .A2(n3372), .B0(n3371), .B1(n3373),
.Y(n3377) );
OAI2BB2XLTS U5451 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .B1(
n3375), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .A1N(n6607),
.Y(n3376) );
AOI22X1TS U5452 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[57]), .A1(n3294), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .B1(n3383), .Y(n3387) );
AOI32X1TS U5453 ( .A0(n3282), .A1(n3384), .A2(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[58]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[59]), .B1(n3287), .Y(n3385) );
NOR2BX1TS U5454 ( .AN(n3395), .B(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[46]),
.Y(n3409) );
AOI22X1TS U5455 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]), .A1(n6624), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[44]), .B1(n3397), .Y(n3406) );
OAI2BB2XLTS U5456 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[40]), .B1(
n3398), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .A1N(n6625),
.Y(n3402) );
OAI2BB2XLTS U5457 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[42]), .B1(
n3399), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .A1N(n6626),
.Y(n3400) );
AOI32X1TS U5458 ( .A0(n3403), .A1(n3402), .A2(n3401), .B0(n3400), .B1(n3403),
.Y(n3404) );
NOR2BX1TS U5459 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[47]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[47]), .Y(n3407) );
AOI211X1TS U5460 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[46]), .A1(
n3409), .B0(n3408), .C0(n3407), .Y(n3452) );
INVX2TS U5461 ( .A(n3413), .Y(n3419) );
AOI22X1TS U5462 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[49]), .A1(n6631), .B0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[48]), .B1(n3415), .Y(n3418) );
AOI32X1TS U5463 ( .A0(n6633), .A1(n3416), .A2(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[51]), .B1(n6632), .Y(n3417) );
OAI32X1TS U5464 ( .A0(n3420), .A1(n3419), .A2(n3418), .B0(n3417), .B1(n3419),
.Y(n3424) );
OAI2BB2XLTS U5465 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[54]), .B1(
n3421), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .A1N(n6634),
.Y(n3423) );
OAI31X1TS U5466 ( .A0(n3425), .A1(n3424), .A2(n3423), .B0(n3422), .Y(n3426)
);
INVX2TS U5467 ( .A(n3429), .Y(n3435) );
OAI2BB2XLTS U5468 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[32]), .B1(
n3430), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .A1N(n6628),
.Y(n3434) );
OAI2BB2XLTS U5469 ( .B0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[34]), .B1(
n3431), .A0N(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .A1N(n6629),
.Y(n3432) );
AOI32X1TS U5470 ( .A0(n3435), .A1(n3434), .A2(n3433), .B0(n3432), .B1(n3435),
.Y(n3436) );
OAI2BB1X1TS U5471 ( .A0N(n3438), .A1N(n3437), .B0(n3436), .Y(n3448) );
NOR2BX1TS U5472 ( .AN(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .B(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[39]), .Y(n3440) );
INVX2TS U5473 ( .A(n3453), .Y(n3445) );
AOI211X4TS U5474 ( .A0(n3457), .A1(n3456), .B0(n3455), .C0(n3454), .Y(n6556)
);
INVX4TS U5475 ( .A(n4536), .Y(n4350) );
BUFX3TS U5476 ( .A(n4272), .Y(n6572) );
BUFX3TS U5477 ( .A(n4272), .Y(n4950) );
BUFX3TS U5478 ( .A(n4272), .Y(n4918) );
AOI22X1TS U5479 ( .A0(n4348), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[57]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[57]), .B1(n4918), .Y(n3459) );
INVX4TS U5480 ( .A(n4872), .Y(n4376) );
BUFX3TS U5481 ( .A(n4272), .Y(n4907) );
AOI22X1TS U5482 ( .A0(n4361), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[16]), .B1(n4907), .Y(n3460) );
BUFX3TS U5483 ( .A(n4272), .Y(n4363) );
AOI22X1TS U5484 ( .A0(n4364), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[29]), .B1(n4363), .Y(n3461) );
NOR4X2TS U5485 ( .A(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[0]), .C(inst_CORDIC_FSM_v3_state_reg[1]),
.D(inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3899) );
NOR3X2TS U5486 ( .A(inst_CORDIC_FSM_v3_state_reg[3]), .B(n3291), .C(n3875),
.Y(ready_cordic) );
NAND2X2TS U5487 ( .A(cont_iter_out[3]), .B(cont_iter_out[2]), .Y(n5352) );
INVX2TS U5488 ( .A(n5352), .Y(n6064) );
NAND2X4TS U5489 ( .A(n6062), .B(n6064), .Y(n4200) );
OAI21XLTS U5490 ( .A0(ack_cordic), .A1(n4201), .B0(n4200), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
AND2X2TS U5491 ( .A(n3216), .B(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .Y(
n5703) );
NAND2X1TS U5492 ( .A(n6639), .B(n5979), .Y(n5972) );
NAND2X1TS U5493 ( .A(n6812), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[0]), .Y(
n3464) );
OAI21X1TS U5494 ( .A0(n5972), .A1(n3465), .B0(n3464), .Y(n5948) );
NOR2X1TS U5495 ( .A(n6811), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .Y(
n5958) );
NAND2X1TS U5496 ( .A(n6811), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .Y(
n5957) );
NAND2X1TS U5497 ( .A(n6786), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[2]), .Y(
n3466) );
AOI21X1TS U5498 ( .A0(n5948), .A1(n3469), .B0(n3468), .Y(n5895) );
NOR2X1TS U5499 ( .A(n6810), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .Y(
n5922) );
NOR2X1TS U5500 ( .A(n6785), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .Y(
n3471) );
NOR2X1TS U5501 ( .A(n5922), .B(n3471), .Y(n5897) );
NOR2X1TS U5502 ( .A(n6809), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .Y(
n5899) );
NOR2X1TS U5503 ( .A(n6784), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .Y(
n3473) );
NAND2X1TS U5504 ( .A(n6810), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .Y(
n5923) );
NAND2X1TS U5505 ( .A(n6785), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .Y(
n3470) );
OAI21X1TS U5506 ( .A0(n3471), .A1(n5923), .B0(n3470), .Y(n5896) );
NAND2X1TS U5507 ( .A(n6809), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[5]), .Y(
n5898) );
NAND2X1TS U5508 ( .A(n6784), .B(n3265), .Y(n3472) );
AOI21X1TS U5509 ( .A0(n5896), .A1(n3475), .B0(n3474), .Y(n3476) );
NOR2X1TS U5510 ( .A(n6808), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .Y(
n5870) );
NOR2X1TS U5511 ( .A(n6783), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .Y(
n3479) );
NOR2X1TS U5512 ( .A(n5870), .B(n3479), .Y(n5826) );
NOR2X1TS U5513 ( .A(n6807), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .Y(
n5839) );
NOR2X1TS U5514 ( .A(n6782), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]), .Y(
n3481) );
NOR2X1TS U5515 ( .A(n6806), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]), .Y(
n5811) );
NOR2X1TS U5516 ( .A(n6781), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .Y(
n3485) );
NOR2X1TS U5517 ( .A(n6805), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]), .Y(
n5797) );
NOR2X1TS U5518 ( .A(n6780), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .Y(
n3487) );
NAND2X1TS U5519 ( .A(n6808), .B(n3247), .Y(n5869) );
NAND2X1TS U5520 ( .A(n6783), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .Y(
n3478) );
OAI21X1TS U5521 ( .A0(n3479), .A1(n5869), .B0(n3478), .Y(n5827) );
NAND2X1TS U5522 ( .A(n6807), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .Y(
n5840) );
NAND2X1TS U5523 ( .A(n6782), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[10]),
.Y(n3480) );
AOI21X1TS U5524 ( .A0(n5827), .A1(n3483), .B0(n3482), .Y(n3880) );
NAND2X1TS U5525 ( .A(n6806), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[11]),
.Y(n5812) );
NAND2X1TS U5526 ( .A(n6781), .B(n3261), .Y(n3484) );
OAI21X1TS U5527 ( .A0(n3485), .A1(n5812), .B0(n3484), .Y(n3883) );
NAND2X1TS U5528 ( .A(n6805), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[13]),
.Y(n5798) );
NAND2X1TS U5529 ( .A(n6780), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]),
.Y(n3486) );
AOI21X1TS U5530 ( .A0(n3883), .A1(n3489), .B0(n3488), .Y(n3490) );
OAI21X1TS U5531 ( .A0(n3880), .A1(n3491), .B0(n3490), .Y(n3492) );
NOR2X1TS U5532 ( .A(n6804), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .Y(
n5783) );
NOR2X1TS U5533 ( .A(n6779), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .Y(
n3495) );
NOR2X1TS U5534 ( .A(n5783), .B(n3495), .Y(n5461) );
NOR2X1TS U5535 ( .A(n6803), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .Y(
n5771) );
NOR2X1TS U5536 ( .A(n6778), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .Y(
n3497) );
NOR2X1TS U5537 ( .A(n6802), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .Y(
n3845) );
NOR2X1TS U5538 ( .A(n6777), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .Y(
n3501) );
NOR2X1TS U5539 ( .A(n6801), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .Y(
n5757) );
NOR2X1TS U5540 ( .A(n6776), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .Y(
n3503) );
NOR2X1TS U5541 ( .A(n6800), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .Y(
n5717) );
NOR2X1TS U5542 ( .A(n6775), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .Y(
n3509) );
NOR2X1TS U5543 ( .A(n5717), .B(n3509), .Y(n5728) );
NOR2X1TS U5544 ( .A(n6674), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .Y(
n5731) );
NOR2X1TS U5545 ( .A(n6774), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .Y(
n3511) );
NOR2X1TS U5546 ( .A(n6799), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .Y(
n5743) );
NOR2X1TS U5547 ( .A(n6773), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .Y(
n3515) );
NOR2X1TS U5548 ( .A(n5743), .B(n3515), .Y(n5634) );
NOR2X1TS U5549 ( .A(n6798), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]), .Y(
n5636) );
NOR2X1TS U5550 ( .A(n6772), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]), .Y(
n3517) );
NOR2X1TS U5551 ( .A(n5636), .B(n3517), .Y(n3519) );
NAND2X1TS U5552 ( .A(n6804), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]),
.Y(n5784) );
NAND2X1TS U5553 ( .A(n6779), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]),
.Y(n3494) );
OAI21X1TS U5554 ( .A0(n3495), .A1(n5784), .B0(n3494), .Y(n5460) );
NAND2X1TS U5555 ( .A(n6803), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]),
.Y(n5770) );
NAND2X1TS U5556 ( .A(n6778), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]),
.Y(n3496) );
AOI21X1TS U5557 ( .A0(n5460), .A1(n3499), .B0(n3498), .Y(n3830) );
NAND2X1TS U5558 ( .A(n6802), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]),
.Y(n3844) );
NAND2X1TS U5559 ( .A(n6777), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]),
.Y(n3500) );
OAI21X1TS U5560 ( .A0(n3501), .A1(n3844), .B0(n3500), .Y(n3855) );
NAND2X1TS U5561 ( .A(n6801), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]),
.Y(n5756) );
NAND2X1TS U5562 ( .A(n6776), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]),
.Y(n3502) );
AOI21X1TS U5563 ( .A0(n3855), .A1(n3505), .B0(n3504), .Y(n3506) );
NAND2X1TS U5564 ( .A(n6775), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]),
.Y(n3508) );
OAI21X1TS U5565 ( .A0(n3509), .A1(n5716), .B0(n3508), .Y(n5727) );
NAND2X1TS U5566 ( .A(n6674), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]),
.Y(n5730) );
NAND2X1TS U5567 ( .A(n6774), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]),
.Y(n3510) );
NAND2X1TS U5568 ( .A(n6799), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]),
.Y(n5742) );
NAND2X1TS U5569 ( .A(n6773), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]),
.Y(n3514) );
OAI21X1TS U5570 ( .A0(n3515), .A1(n5742), .B0(n3514), .Y(n5633) );
NAND2X1TS U5571 ( .A(n6798), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]),
.Y(n5635) );
NAND2X1TS U5572 ( .A(n6772), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]),
.Y(n3516) );
AOI21X1TS U5573 ( .A0(n5633), .A1(n3519), .B0(n3518), .Y(n3520) );
OAI21X1TS U5574 ( .A0(n5630), .A1(n3521), .B0(n3520), .Y(n3522) );
NOR2X1TS U5575 ( .A(n6797), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[31]), .Y(
n5617) );
NOR2X1TS U5576 ( .A(n6771), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]), .Y(
n3527) );
NOR2X1TS U5577 ( .A(n5617), .B(n3527), .Y(n5554) );
NOR2X1TS U5578 ( .A(n6796), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[33]), .Y(
n5558) );
NOR2X1TS U5579 ( .A(n6770), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[34]), .Y(
n3529) );
NOR2X1TS U5580 ( .A(n6795), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[35]), .Y(
n5662) );
NOR2X1TS U5581 ( .A(n6769), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[36]), .Y(
n3533) );
NOR2X1TS U5582 ( .A(n6794), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[37]), .Y(
n5602) );
NOR2X1TS U5583 ( .A(n6768), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[38]), .Y(
n3535) );
NOR2X1TS U5584 ( .A(n6793), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[39]), .Y(
n5648) );
NOR2X1TS U5585 ( .A(n6767), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[40]), .Y(
n3541) );
NAND2X2TS U5586 ( .A(n4137), .B(n3543), .Y(n3685) );
NOR2X1TS U5587 ( .A(n6792), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[41]), .Y(
n3545) );
NAND2X1TS U5588 ( .A(n6797), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[31]),
.Y(n5616) );
NAND2X1TS U5589 ( .A(n6771), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]),
.Y(n3526) );
NAND2X1TS U5590 ( .A(n6796), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[33]),
.Y(n5559) );
NAND2X1TS U5591 ( .A(n6770), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[34]),
.Y(n3528) );
AOI21X1TS U5592 ( .A0(n5555), .A1(n3531), .B0(n3530), .Y(n5584) );
NAND2X1TS U5593 ( .A(n6795), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[35]),
.Y(n5663) );
NAND2X1TS U5594 ( .A(n6769), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[36]),
.Y(n3532) );
OAI21X1TS U5595 ( .A0(n3533), .A1(n5663), .B0(n3532), .Y(n5587) );
NAND2X1TS U5596 ( .A(n6794), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[37]),
.Y(n5603) );
NAND2X1TS U5597 ( .A(n6768), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[38]),
.Y(n3534) );
AOI21X1TS U5598 ( .A0(n5587), .A1(n3537), .B0(n3536), .Y(n3538) );
NAND2X1TS U5599 ( .A(n6793), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[39]),
.Y(n5649) );
NAND2X1TS U5600 ( .A(n6767), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[40]),
.Y(n3540) );
OAI21X1TS U5601 ( .A0(n3541), .A1(n5649), .B0(n3540), .Y(n3542) );
NAND2X1TS U5602 ( .A(n6792), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[41]),
.Y(n3544) );
NOR2X1TS U5603 ( .A(n6791), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[42]), .Y(
n3549) );
NAND2X1TS U5604 ( .A(n6791), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[42]),
.Y(n3548) );
OAI21X4TS U5605 ( .A0(n5487), .A1(n3549), .B0(n3548), .Y(n5477) );
OR2X1TS U5606 ( .A(n6790), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[43]), .Y(
n3551) );
AOI21X4TS U5607 ( .A0(n5477), .A1(n3551), .B0(n3550), .Y(n3618) );
NAND2X1TS U5608 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[44]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[46]), .Y(n3633) );
NAND2X1TS U5609 ( .A(n3635), .B(n3633), .Y(n3593) );
INVX2TS U5610 ( .A(n3593), .Y(n3552) );
NOR2X1TS U5611 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n5949) );
NAND2X1TS U5612 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n5950) );
OAI21X1TS U5613 ( .A0(n5949), .A1(n5970), .B0(n5950), .Y(n5941) );
NOR2X2TS U5614 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n5936) );
NAND2X1TS U5615 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[3]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n5937) );
OAI21X1TS U5616 ( .A0(n5936), .A1(n5961), .B0(n5937), .Y(n3553) );
AOI21X2TS U5617 ( .A0(n5941), .A1(n3554), .B0(n3553), .Y(n5886) );
NOR2X1TS U5618 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n5915) );
NOR2X2TS U5619 ( .A(n3269), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n5910) );
NOR2X1TS U5620 ( .A(n5915), .B(n5910), .Y(n5888) );
NOR2X2TS U5621 ( .A(n3265), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n5900) );
NOR2X2TS U5622 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n5881) );
NAND2X1TS U5623 ( .A(n5888), .B(n3556), .Y(n3558) );
NAND2X1TS U5624 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n5926) );
NAND2X1TS U5625 ( .A(n3269), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n5911) );
OAI21X1TS U5626 ( .A0(n5910), .A1(n5926), .B0(n5911), .Y(n5887) );
NAND2X1TS U5627 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[6]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n5901) );
NAND2X1TS U5628 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n5882) );
AOI21X1TS U5629 ( .A0(n5887), .A1(n3556), .B0(n3555), .Y(n3557) );
NOR2X2TS U5630 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[8]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[10]), .Y(n5871) );
NOR2X2TS U5631 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .Y(n5830) );
NOR2X1TS U5632 ( .A(n3259), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n5844) );
NOR2X2TS U5633 ( .A(n3267), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n5855) );
NOR2X1TS U5634 ( .A(n3261), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n3890) );
NOR2X2TS U5635 ( .A(n3271), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n3886) );
NOR2X2TS U5636 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n3663) );
NAND2X1TS U5637 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[9]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[11]), .Y(n5831) );
NAND2X1TS U5638 ( .A(n3259), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n5860) );
NAND2X1TS U5639 ( .A(n3267), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n5856) );
AOI21X1TS U5640 ( .A0(n5848), .A1(n3560), .B0(n3559), .Y(n3655) );
NAND2X1TS U5641 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[12]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n5816) );
NAND2X1TS U5642 ( .A(n3271), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n3887) );
OAI21X1TS U5643 ( .A0(n3886), .A1(n5816), .B0(n3887), .Y(n3658) );
NAND2X1TS U5644 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[14]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n5802) );
NAND2X1TS U5645 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[15]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n3664) );
AOI21X1TS U5646 ( .A0(n3658), .A1(n3562), .B0(n3561), .Y(n3563) );
NOR2X1TS U5647 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[16]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n5466) );
NOR2X2TS U5648 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n5462) );
NOR2X1TS U5649 ( .A(n5466), .B(n5462), .Y(n3838) );
NOR2X2TS U5650 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n5773) );
NOR2X2TS U5651 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n3833) );
NOR2X2TS U5652 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n3863) );
NOR2X2TS U5653 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n3858) );
NOR2X2TS U5654 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n5759) );
NOR2X2TS U5655 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n3698) );
NOR2X2TS U5656 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[26]), .Y(n5998) );
NOR2X2TS U5657 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[27]), .Y(n5992) );
NOR2X2TS U5658 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[28]), .Y(n5732) );
NOR2X2TS U5659 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[29]), .Y(n5704) );
NOR2X2TS U5660 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[30]), .Y(n5745) );
NOR2X2TS U5661 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[31]), .Y(n5690) );
NOR2X2TS U5662 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[32]), .Y(n5637) );
NOR2X2TS U5663 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[31]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[33]), .Y(n3606) );
NAND2X1TS U5664 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n5463) );
NAND2X1TS U5665 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[18]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n5774) );
NAND2X1TS U5666 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n3834) );
AOI21X1TS U5667 ( .A0(n3837), .A1(n3568), .B0(n3567), .Y(n3693) );
NAND2X1TS U5668 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[20]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n3862) );
NAND2X1TS U5669 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[21]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n3859) );
OAI21X1TS U5670 ( .A0(n3858), .A1(n3862), .B0(n3859), .Y(n3696) );
NAND2X1TS U5671 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n5760) );
NAND2X1TS U5672 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[23]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n3699) );
AOI21X1TS U5673 ( .A0(n3696), .A1(n3570), .B0(n3569), .Y(n3571) );
NAND2X1TS U5674 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[24]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[26]), .Y(n5997) );
NAND2X1TS U5675 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[25]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[27]), .Y(n5993) );
NAND2X1TS U5676 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[26]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[28]), .Y(n5733) );
NAND2X1TS U5677 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[29]), .Y(n5705) );
AOI21X1TS U5678 ( .A0(n5709), .A1(n3574), .B0(n3573), .Y(n3601) );
NAND2X1TS U5679 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[28]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[30]), .Y(n5746) );
NAND2X1TS U5680 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[29]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[31]), .Y(n5691) );
OAI21X1TS U5681 ( .A0(n5690), .A1(n5746), .B0(n5691), .Y(n3604) );
NAND2X1TS U5682 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[30]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[32]), .Y(n5638) );
NAND2X1TS U5683 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[31]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[33]), .Y(n3607) );
AOI21X1TS U5684 ( .A0(n3604), .A1(n3576), .B0(n3575), .Y(n3577) );
AOI21X1TS U5685 ( .A0(n3598), .A1(n3580), .B0(n3579), .Y(n3581) );
NOR2X2TS U5686 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[32]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[34]), .Y(n5619) );
NOR2X2TS U5687 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[33]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[35]), .Y(n5573) );
NOR2X1TS U5688 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[34]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[36]), .Y(n5562) );
NOR2X2TS U5689 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[35]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[37]), .Y(n5676) );
NOR2X1TS U5690 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[36]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[38]), .Y(n5594) );
NOR2X2TS U5691 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[37]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[39]), .Y(n5590) );
NOR2X1TS U5692 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[38]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[40]), .Y(n4131) );
NOR2X2TS U5693 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[39]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[41]), .Y(n4133) );
NOR2X1TS U5694 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[40]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[42]), .Y(n3678) );
NOR2X2TS U5695 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[41]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[43]), .Y(n3680) );
NOR2X2TS U5696 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[42]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[44]), .Y(n5483) );
NAND2X1TS U5697 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[33]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[35]), .Y(n5574) );
OAI21X1TS U5698 ( .A0(n5573), .A1(n5620), .B0(n5574), .Y(n5566) );
NAND2X1TS U5699 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[34]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[36]), .Y(n5681) );
NAND2X1TS U5700 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[35]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[37]), .Y(n5677) );
AOI21X1TS U5701 ( .A0(n5566), .A1(n3584), .B0(n3583), .Y(n4125) );
NAND2X1TS U5702 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[36]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[38]), .Y(n5667) );
NAND2X1TS U5703 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[37]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[39]), .Y(n5591) );
OAI21X1TS U5704 ( .A0(n5590), .A1(n5667), .B0(n5591), .Y(n4128) );
NAND2X1TS U5705 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[38]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[40]), .Y(n5607) );
NAND2X1TS U5706 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[39]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[41]), .Y(n4134) );
OAI21X1TS U5707 ( .A0(n4133), .A1(n5607), .B0(n4134), .Y(n3585) );
AOI21X1TS U5708 ( .A0(n4128), .A1(n3586), .B0(n3585), .Y(n3587) );
OAI21X2TS U5709 ( .A0(n4125), .A1(n3588), .B0(n3587), .Y(n3675) );
NAND2X1TS U5710 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[40]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[42]), .Y(n5653) );
NAND2X1TS U5711 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[41]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[43]), .Y(n3681) );
NAND2X1TS U5712 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[42]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[44]), .Y(n5484) );
AOI21X4TS U5713 ( .A0(n3673), .A1(n3592), .B0(n3591), .Y(n5479) );
NOR2X1TS U5714 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[43]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[45]), .Y(n5473) );
NAND2X1TS U5715 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[43]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[45]), .Y(n5474) );
XNOR2X1TS U5716 ( .A(n3636), .B(n3593), .Y(n3594) );
NOR2X4TS U5717 ( .A(n5492), .B(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_SFG), .Y(
n5766) );
BUFX3TS U5718 ( .A(n5766), .Y(n6008) );
AOI22X1TS U5719 ( .A0(n3594), .A1(n6008), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[46]), .B1(n5492), .Y(
n3595) );
INVX2TS U5720 ( .A(n3600), .Y(n3603) );
INVX2TS U5721 ( .A(n3601), .Y(n3602) );
INVX2TS U5722 ( .A(n5695), .Y(n5751) );
INVX2TS U5723 ( .A(n3606), .Y(n3608) );
NAND2X1TS U5724 ( .A(n3608), .B(n3607), .Y(n3611) );
XNOR2X1TS U5725 ( .A(n3609), .B(n3611), .Y(n3615) );
INVX2TS U5726 ( .A(n3611), .Y(n3612) );
XOR2X1TS U5727 ( .A(n5618), .B(n3612), .Y(n3613) );
BUFX3TS U5728 ( .A(n5703), .Y(n5978) );
BUFX3TS U5729 ( .A(n6473), .Y(n5698) );
AOI22X1TS U5730 ( .A0(n3613), .A1(n5978), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[33]), .B1(n5698), .Y(
n3614) );
BUFX3TS U5731 ( .A(n5703), .Y(n5553) );
NAND2X1TS U5732 ( .A(n6816), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[44]),
.Y(n3616) );
NOR2X1TS U5733 ( .A(n6815), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[46]), .Y(
n3622) );
NAND2X1TS U5734 ( .A(n6815), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[46]),
.Y(n3621) );
OAI21X4TS U5735 ( .A0(n5518), .A1(n3622), .B0(n3621), .Y(n5505) );
AOI21X4TS U5736 ( .A0(n5505), .A1(n3624), .B0(n3623), .Y(n5499) );
NAND2X1TS U5737 ( .A(n6814), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]),
.Y(n3625) );
NOR2X1TS U5738 ( .A(n6813), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[50]), .Y(
n3630) );
NAND2X1TS U5739 ( .A(n6813), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[50]),
.Y(n3629) );
OAI21X4TS U5740 ( .A0(n5537), .A1(n3630), .B0(n3629), .Y(n3646) );
NOR2X1TS U5741 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[51]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[53]), .Y(n3649) );
INVX2TS U5742 ( .A(n3649), .Y(n3631) );
NAND2X1TS U5743 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[51]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[53]), .Y(n3648) );
NAND2X1TS U5744 ( .A(n3631), .B(n3648), .Y(n3640) );
INVX2TS U5745 ( .A(n3640), .Y(n3632) );
XNOR2X1TS U5746 ( .A(n3646), .B(n3632), .Y(n3643) );
INVX2TS U5747 ( .A(n3633), .Y(n3634) );
NOR2X1TS U5748 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[45]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[47]), .Y(n5544) );
NAND2X1TS U5749 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[45]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[47]), .Y(n5545) );
NAND2X1TS U5750 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[46]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[48]), .Y(n5515) );
INVX2TS U5751 ( .A(n5515), .Y(n3637) );
AOI21X4TS U5752 ( .A0(n5520), .A1(n5516), .B0(n3637), .Y(n5511) );
NOR2X1TS U5753 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[47]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[49]), .Y(n5506) );
NAND2X1TS U5754 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[47]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[49]), .Y(n5507) );
NAND2X1TS U5755 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[48]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[50]), .Y(n5496) );
INVX2TS U5756 ( .A(n5496), .Y(n3638) );
AOI21X4TS U5757 ( .A0(n5501), .A1(n5497), .B0(n3638), .Y(n5530) );
NOR2X1TS U5758 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[49]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[51]), .Y(n5524) );
NAND2X1TS U5759 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[49]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[51]), .Y(n5525) );
NAND2X1TS U5760 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[50]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[52]), .Y(n5534) );
INVX2TS U5761 ( .A(n5534), .Y(n3639) );
XOR2X1TS U5762 ( .A(n3650), .B(n3640), .Y(n3641) );
BUFX3TS U5763 ( .A(n6473), .Y(n5580) );
AOI22X1TS U5764 ( .A0(n3641), .A1(n6008), .B0(n3176), .B1(n5580), .Y(n3642)
);
OR2X1TS U5765 ( .A(n6753), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_SFG[51]), .Y(
n3645) );
INVX2TS U5766 ( .A(n3892), .Y(n5821) );
INVX2TS U5767 ( .A(n3657), .Y(n3660) );
INVX2TS U5768 ( .A(n3658), .Y(n3659) );
OAI21X1TS U5769 ( .A0(n5821), .A1(n3660), .B0(n3659), .Y(n5807) );
INVX2TS U5770 ( .A(n5802), .Y(n3662) );
AOI21X1TS U5771 ( .A0(n5807), .A1(n5803), .B0(n3662), .Y(n3666) );
INVX2TS U5772 ( .A(n3663), .Y(n3665) );
NAND2X1TS U5773 ( .A(n3665), .B(n3664), .Y(n3668) );
INVX2TS U5774 ( .A(n3668), .Y(n3669) );
XNOR2X1TS U5775 ( .A(n5787), .B(n3669), .Y(n3670) );
BUFX3TS U5776 ( .A(n6473), .Y(n5932) );
AOI22X1TS U5777 ( .A0(n3670), .A1(n5978), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .B1(n5932), .Y(
n3671) );
OAI2BB1X1TS U5778 ( .A0N(n5766), .A1N(n3672), .B0(n3671), .Y(n2063) );
INVX2TS U5779 ( .A(n3674), .Y(n3677) );
INVX2TS U5780 ( .A(n3675), .Y(n3676) );
OAI21X1TS U5781 ( .A0(n5625), .A1(n3677), .B0(n3676), .Y(n5658) );
AOI21X1TS U5782 ( .A0(n5658), .A1(n5654), .B0(n3679), .Y(n3683) );
NAND2X1TS U5783 ( .A(n3682), .B(n3681), .Y(n3686) );
INVX2TS U5784 ( .A(n3686), .Y(n3687) );
XNOR2X1TS U5785 ( .A(n3688), .B(n3687), .Y(n3689) );
AOI22X1TS U5786 ( .A0(n3689), .A1(n5978), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[43]), .B1(n5580), .Y(
n3690) );
OAI2BB1X1TS U5787 ( .A0N(n5766), .A1N(n3691), .B0(n3690), .Y(n2037) );
INVX2TS U5788 ( .A(n3692), .Y(n3695) );
INVX2TS U5789 ( .A(n3693), .Y(n3694) );
INVX2TS U5790 ( .A(n3864), .Y(n3851) );
AOI21X1TS U5791 ( .A0(n3851), .A1(n3697), .B0(n3696), .Y(n5765) );
NAND2X1TS U5792 ( .A(n3700), .B(n3699), .Y(n3704) );
XNOR2X1TS U5793 ( .A(n3701), .B(n3704), .Y(n3708) );
INVX2TS U5794 ( .A(n5718), .Y(n5729) );
INVX2TS U5795 ( .A(n3704), .Y(n3705) );
XNOR2X1TS U5796 ( .A(n5729), .B(n3705), .Y(n3706) );
BUFX3TS U5797 ( .A(n6473), .Y(n5822) );
AOI22X1TS U5798 ( .A0(n3706), .A1(n5978), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .B1(n5822), .Y(
n3707) );
OAI2BB1X1TS U5799 ( .A0N(n5766), .A1N(n3708), .B0(n3707), .Y(n2055) );
BUFX3TS U5800 ( .A(n6239), .Y(n6260) );
NAND2X1TS U5801 ( .A(n5185), .B(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n4942) );
BUFX3TS U5802 ( .A(n6845), .Y(n6595) );
NAND2X2TS U5803 ( .A(n3783), .B(n3784), .Y(n3714) );
NAND2X2TS U5804 ( .A(n3712), .B(n3711), .Y(n3713) );
NOR2X2TS U5805 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[45]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[46]), .Y(n3760) );
NAND2X2TS U5806 ( .A(n3760), .B(n6641), .Y(n3974) );
NOR2X2TS U5807 ( .A(n3974), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[43]), .Y(n3715) );
NOR2X2TS U5808 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[37]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[38]), .Y(n4009) );
NOR2X1TS U5809 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[34]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[32]), .Y(n4109) );
NOR2X2TS U5810 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[40]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[39]), .Y(n3804) );
NOR2X2TS U5811 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[35]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[36]), .Y(n3786) );
NAND3X2TS U5812 ( .A(n3719), .B(n3804), .C(n3786), .Y(n3720) );
NOR2X1TS U5813 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[27]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[28]), .Y(n3723) );
NAND3X1TS U5814 ( .A(n3723), .B(n3722), .C(n3721), .Y(n3724) );
NAND2X6TS U5815 ( .A(n3743), .B(n6675), .Y(n3796) );
NOR2X8TS U5816 ( .A(n3796), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n4117) );
NOR2X2TS U5817 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n3739) );
NAND2X6TS U5818 ( .A(n4117), .B(n3739), .Y(n3988) );
NOR2X1TS U5819 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n3741) );
INVX2TS U5820 ( .A(n3741), .Y(n3725) );
NOR2X8TS U5821 ( .A(n3988), .B(n3725), .Y(n4173) );
NOR2X1TS U5822 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .Y(n3754) );
NAND2X1TS U5823 ( .A(n3754), .B(n3726), .Y(n3729) );
NOR2X2TS U5824 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n4171) );
NAND2X4TS U5825 ( .A(n4173), .B(n3730), .Y(n3980) );
NOR2X1TS U5826 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n3750) );
INVX2TS U5827 ( .A(n3750), .Y(n3731) );
NOR2X2TS U5828 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n4168) );
NOR2X1TS U5829 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n3751) );
NAND2X4TS U5830 ( .A(n4170), .B(n3732), .Y(n4021) );
NOR2X1TS U5831 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n4022) );
NAND2X1TS U5832 ( .A(n4022), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[0]), .Y(n3748) );
NOR2X1TS U5833 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[28]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]), .Y(n3733) );
OAI22X1TS U5834 ( .A0(n3795), .A1(n6708), .B0(n6638), .B1(n3735), .Y(n3781)
);
INVX2TS U5835 ( .A(n3736), .Y(n3985) );
NAND2X1TS U5836 ( .A(n3804), .B(n6655), .Y(n3737) );
NOR2X2TS U5837 ( .A(n3759), .B(n3737), .Y(n4013) );
NAND2X2TS U5838 ( .A(n4013), .B(n4009), .Y(n4110) );
INVX2TS U5839 ( .A(n3739), .Y(n4017) );
NAND2X1TS U5840 ( .A(n3743), .B(n3742), .Y(n3744) );
OAI21X1TS U5841 ( .A0(n4110), .A1(n3745), .B0(n3744), .Y(n3746) );
OA21X4TS U5842 ( .A0(n4021), .A1(n3748), .B0(n3747), .Y(n4020) );
INVX2TS U5843 ( .A(n3749), .Y(n3984) );
OAI21X1TS U5844 ( .A0(n3752), .A1(n3751), .B0(n3750), .Y(n3753) );
NAND2X2TS U5845 ( .A(n3984), .B(n3753), .Y(n3758) );
NAND2X4TS U5846 ( .A(n4173), .B(n6653), .Y(n3816) );
INVX2TS U5847 ( .A(n4171), .Y(n3755) );
NAND2X2TS U5848 ( .A(n3758), .B(n3757), .Y(n4177) );
NAND2X1TS U5849 ( .A(n6699), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n3771) );
NAND2X1TS U5850 ( .A(n3785), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[28]), .Y(n4111) );
INVX2TS U5851 ( .A(n3759), .Y(n3811) );
OAI2BB1X1TS U5852 ( .A0N(n3763), .A1N(n3762), .B0(n3761), .Y(n3765) );
NAND2X1TS U5853 ( .A(n3765), .B(n3764), .Y(n3766) );
AOI22X1TS U5854 ( .A0(n3811), .A1(n3768), .B0(n3767), .B1(n3766), .Y(n3769)
);
OR2X2TS U5855 ( .A(n6932), .B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM),
.Y(n5057) );
OAI21X4TS U5856 ( .A0(n4942), .A1(n6590), .B0(n4945), .Y(n4957) );
NAND2X1TS U5857 ( .A(n6672), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n3774) );
AOI21X1TS U5858 ( .A0(n3774), .A1(n6688), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n3775) );
NAND2X1TS U5859 ( .A(n6690), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n3776) );
NAND2X2TS U5860 ( .A(n3779), .B(n3778), .Y(n3989) );
NAND2X4TS U5861 ( .A(n3780), .B(n6689), .Y(n4106) );
NAND3X1TS U5862 ( .A(n4178), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .C(n6665), .Y(n3793) );
NAND2X1TS U5863 ( .A(n3783), .B(n3782), .Y(n4113) );
NAND2X1TS U5864 ( .A(n6710), .B(n3784), .Y(n4107) );
NOR2X1TS U5865 ( .A(n4113), .B(n4107), .Y(n3806) );
AOI22X1TS U5866 ( .A0(n3785), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]), .B0(n3806), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[47]), .Y(n3789) );
INVX2TS U5867 ( .A(n4110), .Y(n3787) );
NAND3X2TS U5868 ( .A(n4180), .B(n3793), .C(n3792), .Y(n3794) );
NOR2X4TS U5869 ( .A(n3989), .B(n3794), .Y(n4119) );
INVX2TS U5870 ( .A(n4174), .Y(n3803) );
AOI21X1TS U5871 ( .A0(n6684), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .Y(n3802) );
NOR2X2TS U5872 ( .A(n3795), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[27]), .Y(n3977) );
NAND3X1TS U5873 ( .A(n3977), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .C(n6703), .Y(n4008) );
NAND2X1TS U5874 ( .A(n3797), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[43]), .Y(n3798) );
AOI21X1TS U5875 ( .A0(n6707), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n3815) );
NAND2X1TS U5876 ( .A(n6715), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[35]), .Y(n3813) );
AOI21X1TS U5877 ( .A0(n3805), .A1(n6702), .B0(n3176), .Y(n3808) );
AOI21X1TS U5878 ( .A0(n3811), .A1(n3810), .B0(n3809), .Y(n3812) );
OAI21X1TS U5879 ( .A0(n4110), .A1(n3813), .B0(n3812), .Y(n3814) );
INVX2TS U5880 ( .A(n4021), .Y(n3817) );
NAND4X2TS U5881 ( .A(n4119), .B(n3981), .C(n3818), .D(n4181), .Y(n3819) );
NAND2X1TS U5882 ( .A(n5056), .B(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM),
.Y(n3823) );
INVX2TS U5883 ( .A(n3823), .Y(n5202) );
CLKBUFX2TS U5884 ( .A(n5202), .Y(n5147) );
AOI21X1TS U5885 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[0]),
.A1(n6559), .B0(n5147), .Y(n3820) );
INVX2TS U5886 ( .A(n5013), .Y(n3821) );
NAND2X6TS U5887 ( .A(n4957), .B(n3821), .Y(n5164) );
INVX2TS U5888 ( .A(n5225), .Y(n5216) );
INVX2TS U5889 ( .A(n5057), .Y(n4184) );
AOI22X1TS U5890 ( .A0(n5047), .A1(n3257), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[0]), .B1(n6559), .Y(n3822) );
OAI2BB1X1TS U5891 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]),
.A1N(n5147), .B0(n3822), .Y(n5299) );
NAND2X6TS U5892 ( .A(n4957), .B(n5013), .Y(n5350) );
INVX2TS U5893 ( .A(n3823), .Y(n5127) );
INVX2TS U5894 ( .A(n5127), .Y(n5207) );
OR2X1TS U5895 ( .A(n5207), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n3826) );
NAND2X1TS U5896 ( .A(n4184), .B(n6706), .Y(n3825) );
BUFX3TS U5897 ( .A(n5056), .Y(n6010) );
CLKBUFX2TS U5898 ( .A(n6010), .Y(n5133) );
OR2X1TS U5899 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n3824) );
AOI22X1TS U5900 ( .A0(n5047), .A1(n3176), .B0(n5202), .B1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n5300) );
INVX4TS U5901 ( .A(n6590), .Y(n5455) );
NOR2X2TS U5902 ( .A(n5455), .B(n5056), .Y(n3942) );
AOI22X1TS U5903 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[54]),
.A1(n5047), .B0(n5314), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[0]), .Y(n3827) );
INVX2TS U5904 ( .A(n3829), .Y(n3832) );
INVX2TS U5905 ( .A(n3830), .Y(n3831) );
INVX2TS U5906 ( .A(n3846), .Y(n3857) );
NAND2X1TS U5907 ( .A(n3835), .B(n3834), .Y(n3839) );
INVX2TS U5908 ( .A(n3839), .Y(n3836) );
XNOR2X1TS U5909 ( .A(n3857), .B(n3836), .Y(n3843) );
AOI21X1TS U5910 ( .A0(n5793), .A1(n3838), .B0(n3837), .Y(n5779) );
XNOR2X1TS U5911 ( .A(n3840), .B(n3839), .Y(n3841) );
BUFX3TS U5912 ( .A(n5766), .Y(n5644) );
AOI22X1TS U5913 ( .A0(n3841), .A1(n5644), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[21]), .B1(n5492), .Y(
n3842) );
OAI2BB1X1TS U5914 ( .A0N(n5703), .A1N(n3843), .B0(n3842), .Y(n2059) );
NAND2X1TS U5915 ( .A(n3847), .B(n3862), .Y(n3850) );
INVX2TS U5916 ( .A(n3850), .Y(n3848) );
XNOR2X1TS U5917 ( .A(n3849), .B(n3848), .Y(n3854) );
XNOR2X1TS U5918 ( .A(n3851), .B(n3850), .Y(n3852) );
AOI22X1TS U5919 ( .A0(n3852), .A1(n6008), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .B1(n5492), .Y(
n3853) );
OAI2BB1X1TS U5920 ( .A0N(n5703), .A1N(n3854), .B0(n3853), .Y(n2058) );
AOI21X1TS U5921 ( .A0(n3857), .A1(n3856), .B0(n3855), .Y(n5758) );
NAND2X1TS U5922 ( .A(n3860), .B(n3859), .Y(n3865) );
INVX2TS U5923 ( .A(n3865), .Y(n3861) );
XNOR2X1TS U5924 ( .A(n3866), .B(n3865), .Y(n3867) );
AOI22X1TS U5925 ( .A0(n3867), .A1(n6008), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[23]), .B1(n5492), .Y(
n3868) );
OAI2BB1X1TS U5926 ( .A0N(n5703), .A1N(n3869), .B0(n3868), .Y(n2057) );
INVX2TS U5927 ( .A(rst), .Y(n3870) );
INVX2TS U5928 ( .A(n6595), .Y(busy) );
BUFX3TS U5929 ( .A(n7011), .Y(n6943) );
BUFX3TS U5930 ( .A(n7012), .Y(n6949) );
BUFX3TS U5931 ( .A(n7012), .Y(n6945) );
CLKBUFX2TS U5932 ( .A(n6927), .Y(n3874) );
BUFX3TS U5933 ( .A(n3874), .Y(n6882) );
BUFX3TS U5934 ( .A(n6925), .Y(n6868) );
BUFX3TS U5935 ( .A(n3874), .Y(n6911) );
CLKBUFX2TS U5936 ( .A(n3871), .Y(n6929) );
CLKBUFX2TS U5937 ( .A(n6930), .Y(n6926) );
BUFX3TS U5938 ( .A(n6925), .Y(n6862) );
CLKBUFX2TS U5939 ( .A(n3874), .Y(n3873) );
BUFX3TS U5940 ( .A(n3873), .Y(n6890) );
BUFX3TS U5941 ( .A(n6902), .Y(n6864) );
BUFX3TS U5942 ( .A(n6863), .Y(n6866) );
BUFX3TS U5943 ( .A(n6925), .Y(n6884) );
BUFX3TS U5944 ( .A(n3874), .Y(n6885) );
BUFX3TS U5945 ( .A(n7008), .Y(n6985) );
BUFX3TS U5946 ( .A(n6927), .Y(n6848) );
CLKBUFX2TS U5947 ( .A(n7006), .Y(n7003) );
BUFX3TS U5948 ( .A(n7003), .Y(n6976) );
BUFX3TS U5949 ( .A(n7011), .Y(n6995) );
CLKBUFX2TS U5950 ( .A(n7012), .Y(n6998) );
BUFX3TS U5951 ( .A(n6998), .Y(n6994) );
BUFX3TS U5952 ( .A(n6998), .Y(n6993) );
CLKBUFX3TS U5953 ( .A(n6998), .Y(n7005) );
CLKBUFX3TS U5954 ( .A(n7005), .Y(n6999) );
BUFX3TS U5955 ( .A(n6999), .Y(n6992) );
BUFX3TS U5956 ( .A(n6999), .Y(n6991) );
BUFX3TS U5957 ( .A(n7005), .Y(n6989) );
BUFX3TS U5958 ( .A(n6999), .Y(n6988) );
BUFX3TS U5959 ( .A(n7000), .Y(n6987) );
BUFX3TS U5960 ( .A(n6998), .Y(n6986) );
BUFX3TS U5961 ( .A(n7010), .Y(n6965) );
BUFX3TS U5962 ( .A(n3870), .Y(n6964) );
BUFX3TS U5963 ( .A(n7006), .Y(n6963) );
BUFX3TS U5964 ( .A(n7006), .Y(n6962) );
BUFX3TS U5965 ( .A(n7006), .Y(n6961) );
BUFX3TS U5966 ( .A(n7007), .Y(n6960) );
BUFX3TS U5967 ( .A(n7007), .Y(n6959) );
BUFX3TS U5968 ( .A(n7007), .Y(n6958) );
BUFX3TS U5969 ( .A(n7008), .Y(n6957) );
BUFX3TS U5970 ( .A(n7008), .Y(n6956) );
BUFX3TS U5971 ( .A(n7008), .Y(n6955) );
BUFX3TS U5972 ( .A(n7003), .Y(n6975) );
BUFX3TS U5973 ( .A(n6999), .Y(n7004) );
BUFX3TS U5974 ( .A(n7004), .Y(n6974) );
BUFX3TS U5975 ( .A(n7004), .Y(n6973) );
BUFX3TS U5976 ( .A(n3870), .Y(n6972) );
BUFX3TS U5977 ( .A(n3870), .Y(n6971) );
BUFX3TS U5978 ( .A(n3870), .Y(n6970) );
BUFX3TS U5979 ( .A(n7000), .Y(n6966) );
BUFX3TS U5980 ( .A(n7000), .Y(n6984) );
BUFX3TS U5981 ( .A(n3871), .Y(n6904) );
BUFX3TS U5982 ( .A(n3874), .Y(n6883) );
BUFX3TS U5983 ( .A(n3874), .Y(n6888) );
BUFX3TS U5984 ( .A(n6902), .Y(n6865) );
BUFX3TS U5985 ( .A(n7000), .Y(n6983) );
BUFX3TS U5986 ( .A(n7000), .Y(n6982) );
BUFX3TS U5987 ( .A(n7001), .Y(n6981) );
CLKBUFX3TS U5988 ( .A(n7004), .Y(n7002) );
BUFX3TS U5989 ( .A(n7002), .Y(n6978) );
BUFX3TS U5990 ( .A(n7002), .Y(n6977) );
BUFX3TS U5991 ( .A(n7006), .Y(n6954) );
BUFX3TS U5992 ( .A(n7001), .Y(n6953) );
BUFX3TS U5993 ( .A(n7007), .Y(n6952) );
CLKBUFX2TS U5994 ( .A(n3871), .Y(n6931) );
BUFX3TS U5995 ( .A(n6929), .Y(n6874) );
BUFX3TS U5996 ( .A(n7009), .Y(n6951) );
BUFX3TS U5997 ( .A(n7009), .Y(n6950) );
BUFX3TS U5998 ( .A(n7002), .Y(n6979) );
CLKBUFX2TS U5999 ( .A(n3871), .Y(n3938) );
BUFX3TS U6000 ( .A(n3938), .Y(n6917) );
BUFX3TS U6001 ( .A(n6927), .Y(n6877) );
BUFX3TS U6002 ( .A(n3873), .Y(n6903) );
BUFX3TS U6003 ( .A(n6902), .Y(n6910) );
CLKBUFX2TS U6004 ( .A(n3873), .Y(n3872) );
BUFX3TS U6005 ( .A(n3223), .Y(n6892) );
BUFX3TS U6006 ( .A(n6999), .Y(n6990) );
BUFX3TS U6007 ( .A(n6927), .Y(n6875) );
BUFX3TS U6008 ( .A(n3223), .Y(n6893) );
BUFX3TS U6009 ( .A(n7001), .Y(n6980) );
BUFX3TS U6010 ( .A(n3873), .Y(n6900) );
BUFX3TS U6011 ( .A(n6863), .Y(n6856) );
BUFX3TS U6012 ( .A(n6925), .Y(n6857) );
BUFX3TS U6013 ( .A(n6902), .Y(n6859) );
BUFX3TS U6014 ( .A(n6863), .Y(n6855) );
BUFX3TS U6015 ( .A(n3223), .Y(n6915) );
BUFX3TS U6016 ( .A(n3223), .Y(n6916) );
BUFX3TS U6017 ( .A(n6927), .Y(n6847) );
BUFX3TS U6018 ( .A(n3873), .Y(n6906) );
BUFX3TS U6019 ( .A(n6927), .Y(n6851) );
BUFX3TS U6020 ( .A(n6927), .Y(n6849) );
BUFX3TS U6021 ( .A(n6927), .Y(n6854) );
BUFX3TS U6022 ( .A(n3223), .Y(n6914) );
BUFX3TS U6023 ( .A(n3871), .Y(n6895) );
BUFX3TS U6024 ( .A(n7005), .Y(n6996) );
BUFX3TS U6025 ( .A(n3938), .Y(n6920) );
BUFX3TS U6026 ( .A(n3873), .Y(n6907) );
BUFX3TS U6027 ( .A(n3223), .Y(n6909) );
CLKBUFX2TS U6028 ( .A(n7010), .Y(n6997) );
BUFX3TS U6029 ( .A(n3871), .Y(n6887) );
BUFX3TS U6030 ( .A(n6863), .Y(n6871) );
BUFX3TS U6031 ( .A(n6927), .Y(n6899) );
BUFX3TS U6032 ( .A(n3223), .Y(n6879) );
BUFX3TS U6033 ( .A(n3223), .Y(n6912) );
BUFX3TS U6034 ( .A(n3873), .Y(n6905) );
BUFX3TS U6035 ( .A(n7012), .Y(n6948) );
BUFX3TS U6036 ( .A(n7012), .Y(n6947) );
BUFX3TS U6037 ( .A(n7007), .Y(n6946) );
BUFX3TS U6038 ( .A(n7012), .Y(n6944) );
BUFX3TS U6039 ( .A(n7011), .Y(n6942) );
BUFX3TS U6040 ( .A(n7011), .Y(n6941) );
BUFX3TS U6041 ( .A(n7011), .Y(n6940) );
BUFX3TS U6042 ( .A(n7010), .Y(n6934) );
BUFX3TS U6043 ( .A(n7011), .Y(n6939) );
BUFX3TS U6044 ( .A(n3874), .Y(n6881) );
BUFX3TS U6045 ( .A(n7011), .Y(n6938) );
BUFX3TS U6046 ( .A(n7010), .Y(n6937) );
BUFX3TS U6047 ( .A(n3938), .Y(n6922) );
BUFX3TS U6048 ( .A(n7010), .Y(n6936) );
CLKBUFX2TS U6049 ( .A(n3939), .Y(n6924) );
BUFX3TS U6050 ( .A(n6924), .Y(n6923) );
BUFX3TS U6051 ( .A(n3938), .Y(n6921) );
BUFX3TS U6052 ( .A(n3938), .Y(n6918) );
BUFX3TS U6053 ( .A(n3938), .Y(n6919) );
BUFX3TS U6054 ( .A(n3871), .Y(n6873) );
BUFX3TS U6055 ( .A(n7010), .Y(n6935) );
OAI21XLTS U6056 ( .A0(n3181), .A1(n6635), .B0(n5057), .Y(n3042) );
INVX2TS U6057 ( .A(n6456), .Y(n6315) );
INVX2TS U6058 ( .A(n6456), .Y(n6457) );
NAND2X1TS U6059 ( .A(n6673), .B(n3183), .Y(n6111) );
NAND2X1TS U6060 ( .A(n3297), .B(n6111), .Y(n6103) );
AOI22X1TS U6061 ( .A0(d_ff3_LUT_out[10]), .A1(n6271), .B0(n6082), .B1(n6103),
.Y(n3877) );
NAND2X1TS U6062 ( .A(n3463), .B(n3183), .Y(n4105) );
NAND2X1TS U6063 ( .A(n6102), .B(n4105), .Y(n6088) );
INVX2TS U6064 ( .A(n6088), .Y(n6070) );
NAND2X1TS U6065 ( .A(n3877), .B(n3959), .Y(n3121) );
NAND2X2TS U6066 ( .A(cont_iter_out[1]), .B(n6102), .Y(n4189) );
AOI21X2TS U6067 ( .A0(cont_iter_out[1]), .A1(n3187), .B0(n6110), .Y(n4164)
);
BUFX3TS U6068 ( .A(n6271), .Y(n6092) );
AOI22X1TS U6069 ( .A0(cont_iter_out[2]), .A1(n4164), .B0(d_ff3_LUT_out[14]),
.B1(n6092), .Y(n3878) );
OAI21XLTS U6070 ( .A0(n3183), .A1(n4189), .B0(n3878), .Y(n3125) );
BUFX3TS U6071 ( .A(n5703), .Y(n5947) );
INVX2TS U6072 ( .A(n3879), .Y(n5885) );
OAI21X1TS U6073 ( .A0(n5885), .A1(n3881), .B0(n3880), .Y(n5815) );
INVX2TS U6074 ( .A(n5815), .Y(n5859) );
INVX2TS U6075 ( .A(n3882), .Y(n3885) );
INVX2TS U6076 ( .A(n3883), .Y(n3884) );
OAI21X1TS U6077 ( .A0(n5859), .A1(n3885), .B0(n3884), .Y(n5801) );
NAND2X1TS U6078 ( .A(n3888), .B(n3887), .Y(n3893) );
INVX2TS U6079 ( .A(n3893), .Y(n3889) );
XNOR2X1TS U6080 ( .A(n5801), .B(n3889), .Y(n3897) );
AOI21X1TS U6081 ( .A0(n3892), .A1(n5817), .B0(n3891), .Y(n3894) );
XOR2X1TS U6082 ( .A(n3894), .B(n3893), .Y(n3895) );
BUFX3TS U6083 ( .A(n5766), .Y(n5752) );
AOI22X1TS U6084 ( .A0(n3895), .A1(n5752), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .B1(n5932), .Y(
n3896) );
OAI2BB1X1TS U6085 ( .A0N(n5947), .A1N(n3897), .B0(n3896), .Y(n2065) );
INVX2TS U6086 ( .A(n6175), .Y(n6464) );
NOR2X2TS U6087 ( .A(d_ff2_X[59]), .B(n6162), .Y(n6161) );
NOR3X2TS U6088 ( .A(cont_var_out[1]), .B(n6458), .C(n6642), .Y(n3901) );
BUFX3TS U6089 ( .A(n6343), .Y(n6390) );
BUFX3TS U6090 ( .A(n6376), .Y(n6403) );
AOI22X1TS U6091 ( .A0(n6390), .A1(d_ff2_X[25]), .B0(n6403), .B1(d_ff2_Y[25]),
.Y(n3905) );
NAND2X1TS U6092 ( .A(cont_var_out[1]), .B(cont_var_out[0]), .Y(n6054) );
AOI22X1TS U6093 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[25]), .A1(n6393), .B0(n4043), .B1(d_ff2_Z[25]), .Y(n3904) );
NAND2X1TS U6094 ( .A(n3905), .B(n3904), .Y(n2423) );
AOI22X1TS U6095 ( .A0(n6390), .A1(d_ff2_X[23]), .B0(n6403), .B1(d_ff2_Y[23]),
.Y(n3907) );
BUFX3TS U6096 ( .A(n6232), .Y(n6377) );
AOI22X1TS U6097 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[23]), .A1(n6393), .B0(n6377), .B1(d_ff2_Z[23]), .Y(n3906) );
NAND2X1TS U6098 ( .A(n3907), .B(n3906), .Y(n2427) );
AOI22X1TS U6099 ( .A0(n6390), .A1(d_ff2_X[26]), .B0(n6403), .B1(d_ff2_Y[26]),
.Y(n3909) );
AOI22X1TS U6100 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[26]), .A1(n6393), .B0(n6387), .B1(d_ff2_Z[26]), .Y(n3908) );
NAND2X1TS U6101 ( .A(n3909), .B(n3908), .Y(n2421) );
BUFX3TS U6102 ( .A(n6250), .Y(n6446) );
BUFX3TS U6103 ( .A(n6376), .Y(n6349) );
AOI22X1TS U6104 ( .A0(d_ff2_X[62]), .A1(n6446), .B0(n6349), .B1(n3232), .Y(
n3911) );
CLKINVX3TS U6105 ( .A(n6460), .Y(n6334) );
BUFX3TS U6106 ( .A(n6232), .Y(n6344) );
AOI22X1TS U6107 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]), .A1(n6334), .B0(n6344), .B1(d_ff2_Z[62]), .Y(n3910) );
NAND2X1TS U6108 ( .A(n3911), .B(n3910), .Y(n2561) );
AOI22X1TS U6109 ( .A0(n6413), .A1(d_ff2_X[30]), .B0(n6349), .B1(d_ff2_Y[30]),
.Y(n3913) );
AOI22X1TS U6110 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .A1(n6393), .B0(n3903), .B1(d_ff2_Z[30]), .Y(n3912) );
NAND2X1TS U6111 ( .A(n3913), .B(n3912), .Y(n2413) );
AOI22X1TS U6112 ( .A0(n6413), .A1(d_ff2_X[31]), .B0(n6403), .B1(d_ff2_Y[31]),
.Y(n3915) );
AOI22X1TS U6113 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[31]), .A1(n6410), .B0(n6387), .B1(d_ff2_Z[31]), .Y(n3914) );
NAND2X1TS U6114 ( .A(n3915), .B(n3914), .Y(n2411) );
AOI22X1TS U6115 ( .A0(n6413), .A1(d_ff2_X[28]), .B0(n6371), .B1(d_ff2_Y[28]),
.Y(n3917) );
AOI22X1TS U6116 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .A1(n6393), .B0(n6387), .B1(d_ff2_Z[28]), .Y(n3916) );
NAND2X1TS U6117 ( .A(n3917), .B(n3916), .Y(n2417) );
AOI22X1TS U6118 ( .A0(n6434), .A1(d_ff2_X[45]), .B0(n6431), .B1(d_ff2_Y[45]),
.Y(n3919) );
BUFX3TS U6119 ( .A(n4043), .Y(n6443) );
AOI22X1TS U6120 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[45]), .A1(n6425), .B0(n6443), .B1(d_ff2_Z[45]), .Y(n3918) );
NAND2X1TS U6121 ( .A(n3919), .B(n3918), .Y(n2383) );
AOI22X1TS U6122 ( .A0(n6413), .A1(d_ff2_X[41]), .B0(n6218), .B1(d_ff2_Y[41]),
.Y(n3921) );
AOI22X1TS U6123 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[41]), .A1(n6410), .B0(n6377), .B1(d_ff2_Z[41]), .Y(n3920) );
NAND2X1TS U6124 ( .A(n3921), .B(n3920), .Y(n2391) );
AOI22X1TS U6125 ( .A0(n6413), .A1(d_ff2_X[39]), .B0(n6431), .B1(d_ff2_Y[39]),
.Y(n3923) );
AOI22X1TS U6126 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[39]), .A1(n6410), .B0(n6232), .B1(d_ff2_Z[39]), .Y(n3922) );
NAND2X1TS U6127 ( .A(n3923), .B(n3922), .Y(n2395) );
AOI22X1TS U6128 ( .A0(n6434), .A1(d_ff2_X[43]), .B0(n6218), .B1(d_ff2_Y[43]),
.Y(n3925) );
AOI22X1TS U6129 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[43]), .A1(n6425), .B0(n6377), .B1(d_ff2_Z[43]), .Y(n3924) );
NAND2X1TS U6130 ( .A(n3925), .B(n3924), .Y(n2387) );
AOI22X1TS U6131 ( .A0(n6434), .A1(d_ff2_X[48]), .B0(n6431), .B1(d_ff2_Y[48]),
.Y(n3927) );
AOI22X1TS U6132 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[48]), .A1(n6425), .B0(n6443), .B1(d_ff2_Z[48]), .Y(n3926) );
NAND2X1TS U6133 ( .A(n3927), .B(n3926), .Y(n2377) );
AOI22X1TS U6134 ( .A0(n6413), .A1(d_ff2_X[32]), .B0(n6431), .B1(d_ff2_Y[32]),
.Y(n3929) );
AOI22X1TS U6135 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[32]), .A1(n6410), .B0(n4043), .B1(d_ff2_Z[32]), .Y(n3928) );
NAND2X1TS U6136 ( .A(n3929), .B(n3928), .Y(n2409) );
AOI22X1TS U6137 ( .A0(n6413), .A1(d_ff2_X[34]), .B0(n6431), .B1(d_ff2_Y[34]),
.Y(n3931) );
AOI22X1TS U6138 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[34]), .A1(n6410), .B0(n4043), .B1(d_ff2_Z[34]), .Y(n3930) );
NAND2X1TS U6139 ( .A(n3931), .B(n3930), .Y(n2405) );
AOI22X1TS U6140 ( .A0(n6434), .A1(d_ff2_X[46]), .B0(n6431), .B1(d_ff2_Y[46]),
.Y(n3933) );
AOI22X1TS U6141 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[46]), .A1(n6425), .B0(n6443), .B1(d_ff2_Z[46]), .Y(n3932) );
NAND2X1TS U6142 ( .A(n3933), .B(n3932), .Y(n2381) );
AOI22X1TS U6143 ( .A0(n6434), .A1(d_ff2_X[54]), .B0(n6218), .B1(d_ff2_Y[54]),
.Y(n3935) );
AOI22X1TS U6144 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[54]), .A1(n6453), .B0(n6443), .B1(d_ff2_Z[54]), .Y(n3934) );
NAND2X1TS U6145 ( .A(n3935), .B(n3934), .Y(n2365) );
NOR2X2TS U6146 ( .A(cont_iter_out[1]), .B(n3217), .Y(n4102) );
INVX2TS U6147 ( .A(n4102), .Y(n3973) );
BUFX3TS U6148 ( .A(n6148), .Y(n6135) );
OA22X1TS U6149 ( .A0(n6143), .A1(d_ff2_X[31]), .B0(d_ff_Xn[31]), .B1(n6135),
.Y(n2819) );
OA22X1TS U6150 ( .A0(n6144), .A1(d_ff2_X[8]), .B0(d_ff_Xn[8]), .B1(n6265),
.Y(n2865) );
OA22X1TS U6151 ( .A0(n6188), .A1(d_ff2_X[13]), .B0(d_ff_Xn[13]), .B1(n6265),
.Y(n2855) );
OA22X1TS U6152 ( .A0(n6260), .A1(d_ff2_X[7]), .B0(d_ff_Xn[7]), .B1(n6265),
.Y(n2867) );
OA22X1TS U6153 ( .A0(n6144), .A1(d_ff2_X[42]), .B0(d_ff_Xn[42]), .B1(n6135),
.Y(n2797) );
OA22X1TS U6154 ( .A0(n6150), .A1(d_ff2_X[34]), .B0(d_ff_Xn[34]), .B1(n3937),
.Y(n2813) );
OA22X1TS U6155 ( .A0(n6260), .A1(d_ff2_X[26]), .B0(d_ff_Xn[26]), .B1(n6265),
.Y(n2829) );
OA22X1TS U6156 ( .A0(n6188), .A1(d_ff2_X[19]), .B0(d_ff_Xn[19]), .B1(n6265),
.Y(n2843) );
OA22X1TS U6157 ( .A0(n6260), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n3937),
.Y(n2823) );
OA22X1TS U6158 ( .A0(n6188), .A1(d_ff2_X[24]), .B0(d_ff_Xn[24]), .B1(n6265),
.Y(n2833) );
OA22X1TS U6159 ( .A0(n6150), .A1(d_ff2_X[32]), .B0(d_ff_Xn[32]), .B1(n6149),
.Y(n2817) );
OA22X1TS U6160 ( .A0(n6144), .A1(d_ff2_X[9]), .B0(d_ff_Xn[9]), .B1(n6135),
.Y(n2863) );
OA22X1TS U6161 ( .A0(n6260), .A1(d_ff2_X[14]), .B0(d_ff_Xn[14]), .B1(n6135),
.Y(n2853) );
OA22X1TS U6162 ( .A0(n6188), .A1(d_ff2_X[11]), .B0(d_ff_Xn[11]), .B1(n6135),
.Y(n2859) );
OA22X1TS U6163 ( .A0(n6260), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n6135),
.Y(n2825) );
BUFX3TS U6164 ( .A(n6904), .Y(n6869) );
BUFX3TS U6165 ( .A(n6887), .Y(n6870) );
BUFX3TS U6166 ( .A(n6928), .Y(n6861) );
BUFX3TS U6167 ( .A(n6930), .Y(n6863) );
BUFX3TS U6168 ( .A(n6895), .Y(n6889) );
BUFX3TS U6169 ( .A(n6929), .Y(n6867) );
BUFX3TS U6170 ( .A(n7005), .Y(n6969) );
BUFX3TS U6171 ( .A(n7005), .Y(n6968) );
BUFX3TS U6172 ( .A(n7005), .Y(n6967) );
CLKBUFX2TS U6173 ( .A(n3938), .Y(n3939) );
BUFX3TS U6174 ( .A(n3939), .Y(n6891) );
BUFX3TS U6175 ( .A(n6930), .Y(n6902) );
BUFX3TS U6176 ( .A(n6904), .Y(n6878) );
BUFX3TS U6177 ( .A(n3939), .Y(n6894) );
BUFX3TS U6178 ( .A(n6887), .Y(n6876) );
BUFX3TS U6179 ( .A(n3939), .Y(n6908) );
BUFX3TS U6180 ( .A(n6904), .Y(n6901) );
BUFX3TS U6181 ( .A(n6887), .Y(n6852) );
BUFX3TS U6182 ( .A(n6904), .Y(n6860) );
BUFX3TS U6183 ( .A(n6895), .Y(n6850) );
BUFX3TS U6184 ( .A(n6929), .Y(n6853) );
BUFX3TS U6185 ( .A(n6887), .Y(n6858) );
BUFX3TS U6186 ( .A(n6895), .Y(n6913) );
BUFX3TS U6187 ( .A(n3939), .Y(n6898) );
BUFX3TS U6188 ( .A(n6928), .Y(n6872) );
BUFX3TS U6189 ( .A(n6895), .Y(n6880) );
BUFX3TS U6190 ( .A(n3939), .Y(n6897) );
BUFX3TS U6191 ( .A(n6929), .Y(n6886) );
BUFX3TS U6192 ( .A(n3939), .Y(n6896) );
NAND2X1TS U6193 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[52]), .B(n6704), .Y(intadd_44_CI) );
OA21XLTS U6194 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[52]), .A1(
n6704), .B0(intadd_44_CI), .Y(n3941) );
BUFX3TS U6195 ( .A(n6763), .Y(n6591) );
CLKBUFX2TS U6196 ( .A(n6591), .Y(n6584) );
BUFX3TS U6197 ( .A(n6584), .Y(n6593) );
NAND2X1TS U6198 ( .A(n6593), .B(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n3940) );
OR2X2TS U6199 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4458) );
NAND2X2TS U6200 ( .A(n4725), .B(n4836), .Y(n4750) );
NOR2X2TS U6201 ( .A(n6652), .B(n6683), .Y(n4473) );
BUFX3TS U6202 ( .A(n4473), .Y(n4723) );
NAND2X1TS U6203 ( .A(n4723), .B(n4836), .Y(n3943) );
BUFX3TS U6204 ( .A(n3943), .Y(n5370) );
NOR2X2TS U6205 ( .A(n6697), .B(n6662), .Y(n4839) );
NOR2X4TS U6206 ( .A(n6683), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4724) );
NAND2X1TS U6207 ( .A(n4724), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]), .Y(n3945) );
NAND2X1TS U6208 ( .A(n4598), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .Y(n3944) );
NAND2X1TS U6209 ( .A(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4661) );
NAND2X1TS U6210 ( .A(n4839), .B(n4777), .Y(n3951) );
INVX2TS U6211 ( .A(n4488), .Y(n5367) );
NOR2X2TS U6212 ( .A(n6652), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n4552) );
BUFX3TS U6213 ( .A(n4552), .Y(n4717) );
AOI22X1TS U6214 ( .A0(n4717), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .B0(n4723), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .Y(n3947) );
BUFX3TS U6215 ( .A(n4724), .Y(n4705) );
AOI22X1TS U6216 ( .A0(n4705), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .B0(n4725), .B1(n3241), .Y(n3946) );
NAND2X1TS U6217 ( .A(n3947), .B(n3946), .Y(n4778) );
OR2X2TS U6218 ( .A(n6697), .B(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[5]), .Y(n4785) );
INVX2TS U6219 ( .A(n4785), .Y(n5363) );
BUFX3TS U6220 ( .A(n4473), .Y(n4718) );
AOI22X1TS U6221 ( .A0(n4725), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .B0(n4718), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]), .Y(n3949) );
BUFX3TS U6222 ( .A(n4724), .Y(n4716) );
AOI22X1TS U6223 ( .A0(n4717), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .B0(n4716), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .Y(n3948) );
NAND2X1TS U6224 ( .A(n3949), .B(n3948), .Y(n4779) );
AOI22X1TS U6225 ( .A0(n5367), .A1(n4778), .B0(n5985), .B1(n4779), .Y(n3950)
);
BUFX3TS U6226 ( .A(n4552), .Y(n4722) );
NAND2X1TS U6227 ( .A(n4722), .B(n4836), .Y(n4845) );
NAND2X2TS U6228 ( .A(n4716), .B(n4836), .Y(n4755) );
NAND2X2TS U6229 ( .A(n5448), .B(n6635), .Y(n5445) );
INVX2TS U6230 ( .A(n5445), .Y(n5394) );
INVX2TS U6231 ( .A(n5394), .Y(n5440) );
NAND2X1TS U6232 ( .A(n4458), .B(n6716), .Y(n4669) );
NAND2X1TS U6233 ( .A(n4719), .B(n6711), .Y(n3954) );
NAND2X1TS U6234 ( .A(n4669), .B(n3954), .Y(n4786) );
NAND2X1TS U6235 ( .A(n4647), .B(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2),
.Y(n4486) );
CLKBUFX2TS U6236 ( .A(n4486), .Y(n4763) );
NAND2X2TS U6237 ( .A(n5448), .B(inst_FPU_PIPELINED_FPADDSUB_left_right_SHT2),
.Y(n5430) );
INVX2TS U6238 ( .A(n5430), .Y(n5385) );
BUFX3TS U6239 ( .A(n6558), .Y(n6577) );
AOI22X1TS U6240 ( .A0(n3193), .A1(n5385), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[1]), .B1(n6577), .Y(n3955) );
AOI22X1TS U6241 ( .A0(n3193), .A1(n5394), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[53]), .B1(n6577), .Y(
n3956) );
NAND2X1TS U6242 ( .A(n3187), .B(n6686), .Y(intadd_45_CI) );
AOI32X1TS U6243 ( .A0(n4200), .A1(n6062), .A2(cont_iter_out[2]), .B0(
cont_iter_out[3]), .B1(n4200), .Y(n3957) );
INVX2TS U6244 ( .A(n3957), .Y(n3161) );
BUFX3TS U6245 ( .A(n6092), .Y(n6217) );
NAND2X2TS U6246 ( .A(n6102), .B(n6105), .Y(n6071) );
NAND2X2TS U6247 ( .A(n3187), .B(n6102), .Y(n4103) );
NOR2X2TS U6248 ( .A(n3463), .B(n3183), .Y(n6076) );
NOR2XLTS U6249 ( .A(cont_iter_out[3]), .B(n6673), .Y(n3958) );
AOI211X1TS U6250 ( .A0(n6076), .A1(n6673), .B0(cont_iter_out[1]), .C0(n3958),
.Y(n6117) );
NAND2X1TS U6251 ( .A(n6102), .B(n6117), .Y(n3969) );
NAND2X1TS U6252 ( .A(cont_iter_out[1]), .B(n6070), .Y(n6113) );
BUFX3TS U6253 ( .A(n3303), .Y(n6185) );
NOR2X2TS U6254 ( .A(cont_iter_out[1]), .B(n6185), .Y(n6112) );
NOR2X2TS U6255 ( .A(n3217), .B(n4189), .Y(n4187) );
NAND2X2TS U6256 ( .A(n5352), .B(n6105), .Y(n6079) );
AOI22X1TS U6257 ( .A0(n3463), .A1(n6112), .B0(n4187), .B1(n6079), .Y(n6073)
);
INVX2TS U6258 ( .A(n4103), .Y(n6066) );
NAND2X1TS U6259 ( .A(n6066), .B(n6670), .Y(n3960) );
INVX2TS U6260 ( .A(n6079), .Y(n4186) );
NOR3X1TS U6261 ( .A(cont_iter_out[1]), .B(n4186), .C(n4103), .Y(n3970) );
AOI21X1TS U6262 ( .A0(d_ff3_LUT_out[1]), .A1(n6185), .B0(n3970), .Y(n3961)
);
NAND4X1TS U6263 ( .A(n6112), .B(n6673), .C(n5352), .D(n6105), .Y(n6095) );
INVX2TS U6264 ( .A(n4187), .Y(n6091) );
NAND2X1TS U6265 ( .A(n6102), .B(n4102), .Y(n4024) );
INVX2TS U6266 ( .A(n4024), .Y(n4188) );
INVX2TS U6267 ( .A(n6076), .Y(n6086) );
AOI22X1TS U6268 ( .A0(n4188), .A1(n6086), .B0(d_ff3_LUT_out[3]), .B1(n6110),
.Y(n3963) );
NOR2X2TS U6269 ( .A(n3463), .B(n4103), .Y(n6074) );
INVX2TS U6270 ( .A(n6074), .Y(n3962) );
NAND3BX1TS U6271 ( .AN(n3964), .B(inst_CORDIC_FSM_v3_state_reg[0]), .C(n6698), .Y(n6052) );
BUFX3TS U6272 ( .A(n6119), .Y(n6122) );
NOR4X1TS U6273 ( .A(n5375), .B(n6102), .C(n6150), .D(n6122), .Y(n3966) );
AOI32X1TS U6274 ( .A0(n3967), .A1(n4201), .A2(n3966), .B0(ready_cordic),
.B1(ack_cordic), .Y(n3968) );
NAND2X1TS U6275 ( .A(n3187), .B(n6687), .Y(intadd_46_CI) );
AOI21X1TS U6276 ( .A0(d_ff3_LUT_out[33]), .A1(n6110), .B0(n3970), .Y(n3972)
);
NAND2X1TS U6277 ( .A(n4164), .B(n3973), .Y(n6065) );
AOI22X1TS U6278 ( .A0(n3976), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30]), .B0(n3975), .B1(
n3974), .Y(n3979) );
OAI31X1TS U6279 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]),
.A1(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[26]), .A2(n4017),
.B0(n3977), .Y(n3978) );
OAI211X1TS U6280 ( .A0(n3980), .A1(n6733), .B0(n3979), .C0(n3978), .Y(n3983)
);
AOI211X1TS U6281 ( .A0(n3984), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .B0(n3983), .C0(
n3982), .Y(n3990) );
OAI211X1TS U6282 ( .A0(n6690), .A1(n3988), .B0(n3987), .C0(n3986), .Y(n4120)
);
NOR3BX1TS U6283 ( .AN(n3990), .B(n3989), .C(n4120), .Y(n3993) );
NAND2X1TS U6284 ( .A(n6932), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n3991) );
NOR2X2TS U6285 ( .A(n5314), .B(n5056), .Y(n4183) );
AOI22X1TS U6286 ( .A0(n4183), .A1(
inst_FPU_PIPELINED_FPADDSUB_Shift_amount_SHT1_EWR[3]), .B0(
inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n5305), .Y(
n3992) );
AOI21X1TS U6287 ( .A0(n6102), .A1(cont_iter_out[3]), .B0(n6107), .Y(n6083)
);
AOI21X1TS U6288 ( .A0(n6112), .A1(n6111), .B0(n6107), .Y(n6090) );
BUFX3TS U6289 ( .A(n4084), .Y(n4041) );
INVX2TS U6290 ( .A(n3994), .Y(n2470) );
INVX2TS U6291 ( .A(n3995), .Y(n2472) );
INVX2TS U6292 ( .A(n3996), .Y(n2468) );
BUFX3TS U6293 ( .A(n4066), .Y(n4071) );
INVX2TS U6294 ( .A(n3997), .Y(n2438) );
BUFX3TS U6295 ( .A(n4066), .Y(n4080) );
INVX2TS U6296 ( .A(n3998), .Y(n2424) );
INVX2TS U6297 ( .A(n3999), .Y(n2442) );
INVX2TS U6298 ( .A(n4000), .Y(n2432) );
INVX2TS U6299 ( .A(n4001), .Y(n2444) );
INVX2TS U6300 ( .A(n4002), .Y(n2436) );
INVX2TS U6301 ( .A(n4003), .Y(n2446) );
INVX2TS U6302 ( .A(n4004), .Y(n2440) );
INVX2TS U6303 ( .A(n4005), .Y(n2430) );
INVX2TS U6304 ( .A(n4006), .Y(n2428) );
INVX2TS U6305 ( .A(n4007), .Y(n2426) );
INVX2TS U6306 ( .A(n4008), .Y(n4016) );
NAND2X1TS U6307 ( .A(n4009), .B(n6756), .Y(n4012) );
NOR4X1TS U6308 ( .A(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[28]), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[26]), .C(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30]), .D(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]), .Y(n4010) );
AOI211X1TS U6309 ( .A0(n4018), .A1(n4017), .B0(n4016), .C0(n4015), .Y(n4019)
);
OAI211X1TS U6310 ( .A0(n4022), .A1(n4021), .B0(n4020), .C0(n4019), .Y(n6013)
);
INVX2TS U6311 ( .A(n4023), .Y(n3039) );
NAND2X1TS U6312 ( .A(n4024), .B(n6084), .Y(n4166) );
AOI211X1TS U6313 ( .A0(d_ff3_LUT_out[8]), .A1(n6092), .B0(n6074), .C0(n4166),
.Y(n4025) );
INVX2TS U6314 ( .A(n4025), .Y(n3119) );
BUFX3TS U6315 ( .A(n4041), .Y(n4037) );
INVX2TS U6316 ( .A(n4026), .Y(n2448) );
INVX2TS U6317 ( .A(n4027), .Y(n2462) );
INVX2TS U6318 ( .A(n4028), .Y(n2456) );
INVX2TS U6319 ( .A(n4029), .Y(n2450) );
INVX2TS U6320 ( .A(n4030), .Y(n2454) );
INVX2TS U6321 ( .A(n4031), .Y(n2452) );
INVX2TS U6322 ( .A(n4032), .Y(n2460) );
INVX2TS U6323 ( .A(n4033), .Y(n2466) );
INVX2TS U6324 ( .A(n4035), .Y(n2464) );
INVX2TS U6325 ( .A(n4038), .Y(n2458) );
BUFX3TS U6326 ( .A(n6250), .Y(n6452) );
BUFX3TS U6327 ( .A(n6197), .Y(n6201) );
INVX2TS U6328 ( .A(n4039), .Y(n2342) );
BUFX3TS U6329 ( .A(n4153), .Y(n4199) );
BUFX3TS U6330 ( .A(n6376), .Y(n6407) );
BUFX3TS U6331 ( .A(n6250), .Y(n6398) );
AOI22X1TS U6332 ( .A0(d_ff3_sh_x_out[62]), .A1(n6407), .B0(n6398), .B1(
d_ff3_sh_y_out[62]), .Y(n4040) );
INVX2TS U6333 ( .A(n4042), .Y(n2474) );
BUFX3TS U6334 ( .A(n4153), .Y(n4163) );
BUFX3TS U6335 ( .A(n6250), .Y(n6236) );
BUFX3TS U6336 ( .A(n6236), .Y(n6364) );
BUFX3TS U6337 ( .A(n6376), .Y(n6301) );
AOI22X1TS U6338 ( .A0(n6364), .A1(d_ff3_sh_y_out[46]), .B0(n6301), .B1(
d_ff3_sh_x_out[46]), .Y(n4044) );
BUFX3TS U6339 ( .A(n4043), .Y(n6181) );
NAND2X1TS U6340 ( .A(n6181), .B(d_ff3_LUT_out[44]), .Y(n4149) );
AOI22X1TS U6341 ( .A0(n6364), .A1(d_ff3_sh_y_out[47]), .B0(n6301), .B1(
d_ff3_sh_x_out[47]), .Y(n4045) );
NAND2X1TS U6342 ( .A(n6181), .B(d_ff3_LUT_out[42]), .Y(n4159) );
OAI211X1TS U6343 ( .A0(n4163), .A1(n6751), .B0(n4045), .C0(n4159), .Y(n2607)
);
AOI22X1TS U6344 ( .A0(n6364), .A1(d_ff3_sh_y_out[49]), .B0(n6301), .B1(
d_ff3_sh_x_out[49]), .Y(n4046) );
OAI211X1TS U6345 ( .A0(n4199), .A1(n6744), .B0(n4046), .C0(n4149), .Y(n2601)
);
BUFX3TS U6346 ( .A(n6236), .Y(n6268) );
AOI22X1TS U6347 ( .A0(n6268), .A1(d_ff3_sh_y_out[4]), .B0(n6201), .B1(
d_ff3_sh_x_out[4]), .Y(n4047) );
NAND2X1TS U6348 ( .A(n6181), .B(d_ff3_LUT_out[4]), .Y(n4146) );
BUFX3TS U6349 ( .A(n4084), .Y(n4069) );
INVX2TS U6350 ( .A(n4048), .Y(n2384) );
INVX2TS U6351 ( .A(n4049), .Y(n2408) );
INVX2TS U6352 ( .A(n4050), .Y(n2396) );
INVX2TS U6353 ( .A(n4052), .Y(n2422) );
INVX2TS U6354 ( .A(n4053), .Y(n2402) );
INVX2TS U6355 ( .A(n4054), .Y(n2412) );
INVX2TS U6356 ( .A(n4055), .Y(n2390) );
INVX2TS U6357 ( .A(n4056), .Y(n2386) );
INVX2TS U6358 ( .A(n4057), .Y(n2420) );
INVX2TS U6359 ( .A(n4058), .Y(n2416) );
INVX2TS U6360 ( .A(n4059), .Y(n2400) );
INVX2TS U6361 ( .A(n4060), .Y(n2394) );
INVX2TS U6362 ( .A(n4061), .Y(n2406) );
INVX2TS U6363 ( .A(n4062), .Y(n2398) );
INVX2TS U6364 ( .A(n4063), .Y(n2418) );
INVX2TS U6365 ( .A(n4064), .Y(n2382) );
INVX2TS U6366 ( .A(n4065), .Y(n2372) );
INVX2TS U6367 ( .A(n4067), .Y(n2404) );
INVX2TS U6368 ( .A(n4068), .Y(n2414) );
INVX2TS U6369 ( .A(n4070), .Y(n2366) );
INVX2TS U6370 ( .A(n4072), .Y(n2434) );
INVX2TS U6371 ( .A(n4073), .Y(n2370) );
INVX2TS U6372 ( .A(n4074), .Y(n2374) );
INVX2TS U6373 ( .A(n4075), .Y(n2380) );
INVX2TS U6374 ( .A(n4076), .Y(n2378) );
INVX2TS U6375 ( .A(n4077), .Y(n2364) );
INVX2TS U6376 ( .A(n4078), .Y(n2388) );
INVX2TS U6377 ( .A(n4082), .Y(n2410) );
INVX2TS U6378 ( .A(n4086), .Y(n2392) );
INVX2TS U6379 ( .A(n4088), .Y(n2368) );
INVX2TS U6380 ( .A(n4089), .Y(n2350) );
INVX2TS U6381 ( .A(n4090), .Y(n2360) );
INVX2TS U6382 ( .A(n4091), .Y(n2356) );
INVX2TS U6383 ( .A(n4092), .Y(n2352) );
AOI222X1TS U6384 ( .A0(n6151), .A1(d_ff2_Z[56]), .B0(n4084), .B1(d_ff1_Z[56]), .C0(d_ff_Zn[56]), .C1(n4098), .Y(n4093) );
INVX2TS U6385 ( .A(n4093), .Y(n2362) );
INVX2TS U6386 ( .A(n4094), .Y(n2354) );
INVX2TS U6387 ( .A(n4096), .Y(n2358) );
INVX2TS U6388 ( .A(n4097), .Y(n2376) );
INVX2TS U6389 ( .A(n4100), .Y(n2349) );
INVX2TS U6390 ( .A(n6112), .Y(n6087) );
NOR2X1TS U6391 ( .A(n3297), .B(n6087), .Y(n6075) );
AOI22X1TS U6392 ( .A0(d_ff3_LUT_out[6]), .A1(n6092), .B0(n6075), .B1(n6673),
.Y(n4101) );
AOI22X1TS U6393 ( .A0(n6093), .A1(n6086), .B0(d_ff3_LUT_out[23]), .B1(n6110),
.Y(n4104) );
AOI21X1TS U6394 ( .A0(n6754), .A1(n6665), .B0(n4106), .Y(n4116) );
INVX2TS U6395 ( .A(n4107), .Y(n4114) );
OR3X1TS U6396 ( .A(n4110), .B(n4109), .C(n4108), .Y(n4112) );
AOI211X1TS U6397 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]),
.A1(n4117), .B0(n4116), .C0(n4115), .Y(n4118) );
INVX2TS U6398 ( .A(n4121), .Y(n3041) );
NAND2X1TS U6399 ( .A(n6093), .B(n6079), .Y(n4122) );
NAND2X1TS U6400 ( .A(n4164), .B(n3183), .Y(n6080) );
AOI21X1TS U6401 ( .A0(d_ff3_LUT_out[13]), .A1(n6110), .B0(n6106), .Y(n4124)
);
INVX2TS U6402 ( .A(n5596), .Y(n5672) );
INVX2TS U6403 ( .A(n4127), .Y(n4130) );
INVX2TS U6404 ( .A(n4128), .Y(n4129) );
INVX2TS U6405 ( .A(n5607), .Y(n4132) );
AOI21X1TS U6406 ( .A0(n5612), .A1(n5608), .B0(n4132), .Y(n4136) );
NAND2X1TS U6407 ( .A(n4135), .B(n4134), .Y(n4141) );
INVX2TS U6408 ( .A(n4137), .Y(n4140) );
INVX2TS U6409 ( .A(n4138), .Y(n4139) );
OAI21X1TS U6410 ( .A0(n5618), .A1(n4140), .B0(n4139), .Y(n5652) );
INVX2TS U6411 ( .A(n4141), .Y(n4142) );
XNOR2X1TS U6412 ( .A(n5652), .B(n4142), .Y(n4143) );
AOI22X1TS U6413 ( .A0(n4143), .A1(n5978), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[41]), .B1(n5698), .Y(
n4144) );
BUFX3TS U6414 ( .A(n6236), .Y(n6275) );
BUFX3TS U6415 ( .A(n6371), .Y(n6261) );
AOI22X1TS U6416 ( .A0(n6275), .A1(d_ff3_sh_y_out[30]), .B0(n6261), .B1(
d_ff3_sh_x_out[30]), .Y(n4147) );
OAI211X1TS U6417 ( .A0(n4153), .A1(n6749), .B0(n4147), .C0(n4146), .Y(n2658)
);
BUFX3TS U6418 ( .A(n6371), .Y(n6283) );
AOI22X1TS U6419 ( .A0(n6364), .A1(d_ff3_sh_y_out[43]), .B0(n6283), .B1(
d_ff3_sh_x_out[43]), .Y(n4148) );
NAND2X1TS U6420 ( .A(n6377), .B(d_ff3_LUT_out[34]), .Y(n4156) );
AOI22X1TS U6421 ( .A0(n6364), .A1(d_ff3_sh_y_out[44]), .B0(n6283), .B1(
d_ff3_sh_x_out[44]), .Y(n4150) );
OAI211X1TS U6422 ( .A0(n4163), .A1(n6742), .B0(n4150), .C0(n4149), .Y(n2616)
);
AOI22X1TS U6423 ( .A0(n6275), .A1(d_ff3_sh_y_out[38]), .B0(n6283), .B1(
d_ff3_sh_x_out[38]), .Y(n4151) );
NAND2X1TS U6424 ( .A(n6377), .B(d_ff3_LUT_out[32]), .Y(n4154) );
OAI211X1TS U6425 ( .A0(n4163), .A1(n6764), .B0(n4151), .C0(n4154), .Y(n2634)
);
AOI22X1TS U6426 ( .A0(n6268), .A1(d_ff3_sh_y_out[28]), .B0(n6261), .B1(
d_ff3_sh_x_out[28]), .Y(n4152) );
NAND2X1TS U6427 ( .A(n6181), .B(d_ff3_LUT_out[28]), .Y(n4161) );
AOI22X1TS U6428 ( .A0(n6268), .A1(d_ff3_sh_y_out[32]), .B0(n6261), .B1(
d_ff3_sh_x_out[32]), .Y(n4155) );
OAI211X1TS U6429 ( .A0(n4163), .A1(n6746), .B0(n4155), .C0(n4154), .Y(n2652)
);
AOI22X1TS U6430 ( .A0(n6268), .A1(d_ff3_sh_y_out[34]), .B0(n6261), .B1(
d_ff3_sh_x_out[34]), .Y(n4157) );
OAI211X1TS U6431 ( .A0(n4163), .A1(n6747), .B0(n4157), .C0(n4156), .Y(n2646)
);
AOI22X1TS U6432 ( .A0(n6275), .A1(d_ff3_sh_y_out[40]), .B0(n6283), .B1(
d_ff3_sh_x_out[40]), .Y(n4158) );
OAI211X1TS U6433 ( .A0(n4163), .A1(n6750), .B0(n4158), .C0(n4161), .Y(n2628)
);
AOI22X1TS U6434 ( .A0(n6275), .A1(d_ff3_sh_y_out[42]), .B0(n6283), .B1(
d_ff3_sh_x_out[42]), .Y(n4160) );
OAI211X1TS U6435 ( .A0(n4163), .A1(n6748), .B0(n4160), .C0(n4159), .Y(n2622)
);
AOI22X1TS U6436 ( .A0(n6275), .A1(d_ff3_sh_y_out[36]), .B0(n6261), .B1(
d_ff3_sh_x_out[36]), .Y(n4162) );
OAI211X1TS U6437 ( .A0(n4163), .A1(n6741), .B0(n4162), .C0(n4161), .Y(n2640)
);
INVX2TS U6438 ( .A(n6093), .Y(n6114) );
AOI22X1TS U6439 ( .A0(d_ff3_LUT_out[54]), .A1(n6271), .B0(n4164), .B1(n3297),
.Y(n4165) );
AOI21X1TS U6440 ( .A0(n6093), .A1(n3463), .B0(n4166), .Y(n6078) );
AOI22X1TS U6441 ( .A0(d_ff3_LUT_out[7]), .A1(n6271), .B0(n4187), .B1(n5352),
.Y(n4167) );
NAND2X1TS U6442 ( .A(n4170), .B(n4169), .Y(n4176) );
AOI22X1TS U6443 ( .A0(n4174), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B0(n4173), .B1(
n4172), .Y(n4175) );
NAND2X1TS U6444 ( .A(n4178), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n4179) );
INVX2TS U6445 ( .A(n4185), .Y(n3038) );
AOI22X1TS U6446 ( .A0(n3187), .A1(n6106), .B0(n4187), .B1(n4186), .Y(n6101)
);
AOI22X1TS U6447 ( .A0(d_ff3_LUT_out[11]), .A1(n6092), .B0(n4188), .B1(n5352),
.Y(n4190) );
INVX2TS U6448 ( .A(n4189), .Y(n6067) );
AOI22X1TS U6449 ( .A0(n6236), .A1(d_ff3_sh_y_out[59]), .B0(n6349), .B1(
d_ff3_sh_x_out[59]), .Y(n4191) );
NAND2X2TS U6450 ( .A(n6181), .B(d_ff3_LUT_out[48]), .Y(n4197) );
AOI22X1TS U6451 ( .A0(n6236), .A1(d_ff3_sh_y_out[60]), .B0(n6349), .B1(
d_ff3_sh_x_out[60]), .Y(n4192) );
AOI22X1TS U6452 ( .A0(n6236), .A1(d_ff3_sh_y_out[58]), .B0(n6301), .B1(
d_ff3_sh_x_out[58]), .Y(n4193) );
AOI22X1TS U6453 ( .A0(n6236), .A1(d_ff3_sh_y_out[61]), .B0(n6349), .B1(
d_ff3_sh_x_out[61]), .Y(n4194) );
AOI22X1TS U6454 ( .A0(n6236), .A1(d_ff3_sh_y_out[57]), .B0(n6301), .B1(
d_ff3_sh_x_out[57]), .Y(n4195) );
AOI22X1TS U6455 ( .A0(n6364), .A1(d_ff3_sh_y_out[48]), .B0(n6301), .B1(
d_ff3_sh_x_out[48]), .Y(n4196) );
AOI22X1TS U6456 ( .A0(n6364), .A1(d_ff3_sh_y_out[51]), .B0(n6301), .B1(
d_ff3_sh_x_out[51]), .Y(n4198) );
BUFX3TS U6457 ( .A(n4286), .Y(n4255) );
XNOR2X1TS U6458 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out), .Y(n4203) );
CLKXOR2X2TS U6459 ( .A(d_ff1_shift_region_flag_out[0]), .B(n4203), .Y(n6468)
);
BUFX3TS U6460 ( .A(n4229), .Y(n4254) );
INVX2TS U6461 ( .A(n6468), .Y(n6467) );
BUFX3TS U6462 ( .A(n4297), .Y(n4253) );
INVX2TS U6463 ( .A(n4205), .Y(n2293) );
BUFX3TS U6464 ( .A(n4286), .Y(n4264) );
BUFX3TS U6465 ( .A(n4229), .Y(n4263) );
BUFX3TS U6466 ( .A(n4313), .Y(n4262) );
INVX2TS U6467 ( .A(n4206), .Y(n2329) );
BUFX3TS U6468 ( .A(n4286), .Y(n4226) );
BUFX3TS U6469 ( .A(n4229), .Y(n4260) );
BUFX3TS U6470 ( .A(n4313), .Y(n4259) );
INVX2TS U6471 ( .A(n4207), .Y(n2317) );
BUFX3TS U6472 ( .A(n4229), .Y(n4235) );
BUFX3TS U6473 ( .A(n4313), .Y(n4234) );
INVX2TS U6474 ( .A(n4208), .Y(n2332) );
INVX2TS U6475 ( .A(n4209), .Y(n2316) );
INVX2TS U6476 ( .A(n4210), .Y(n2314) );
INVX2TS U6477 ( .A(n4211), .Y(n2313) );
INVX2TS U6478 ( .A(n4212), .Y(n2319) );
INVX2TS U6479 ( .A(n4213), .Y(n2315) );
INVX2TS U6480 ( .A(n4214), .Y(n2334) );
INVX2TS U6481 ( .A(n4215), .Y(n2330) );
INVX2TS U6482 ( .A(n4216), .Y(n2328) );
INVX2TS U6483 ( .A(n4217), .Y(n2318) );
INVX2TS U6484 ( .A(n4218), .Y(n2331) );
INVX2TS U6485 ( .A(n4219), .Y(n2320) );
INVX2TS U6486 ( .A(n4220), .Y(n2324) );
INVX2TS U6487 ( .A(n4221), .Y(n2333) );
INVX2TS U6488 ( .A(n4222), .Y(n2335) );
INVX2TS U6489 ( .A(n4223), .Y(n2336) );
INVX2TS U6490 ( .A(n4224), .Y(n2322) );
BUFX3TS U6491 ( .A(n4286), .Y(n4294) );
INVX2TS U6492 ( .A(n4225), .Y(n2291) );
AOI222X1TS U6493 ( .A0(n4226), .A1(data_output[19]), .B0(n4263), .B1(
d_ff_Yn[19]), .C0(n4262), .C1(d_ff_Xn[19]), .Y(n7013) );
INVX2TS U6494 ( .A(n4227), .Y(n2292) );
INVX2TS U6495 ( .A(n4228), .Y(n2338) );
BUFX3TS U6496 ( .A(n4286), .Y(n4268) );
BUFX3TS U6497 ( .A(n4229), .Y(n4267) );
BUFX3TS U6498 ( .A(n4297), .Y(n4266) );
INVX2TS U6499 ( .A(n4230), .Y(n2307) );
INVX2TS U6500 ( .A(n4231), .Y(n2339) );
INVX2TS U6501 ( .A(n4232), .Y(n2296) );
INVX2TS U6502 ( .A(n4233), .Y(n2340) );
INVX2TS U6503 ( .A(n4237), .Y(n2337) );
INVX2TS U6504 ( .A(n4238), .Y(n2327) );
INVX2TS U6505 ( .A(n4239), .Y(n2306) );
INVX2TS U6506 ( .A(n4240), .Y(n2311) );
INVX2TS U6507 ( .A(n4241), .Y(n2295) );
INVX2TS U6508 ( .A(n4242), .Y(n2294) );
INVX2TS U6509 ( .A(n4243), .Y(n2326) );
INVX2TS U6510 ( .A(n4244), .Y(n2305) );
INVX2TS U6511 ( .A(n4245), .Y(n2298) );
INVX2TS U6512 ( .A(n4246), .Y(n2297) );
INVX2TS U6513 ( .A(n4247), .Y(n2308) );
INVX2TS U6514 ( .A(n4248), .Y(n2304) );
INVX2TS U6515 ( .A(n4249), .Y(n2301) );
INVX2TS U6516 ( .A(n4250), .Y(n2299) );
INVX2TS U6517 ( .A(n4251), .Y(n2323) );
INVX2TS U6518 ( .A(n4252), .Y(n2302) );
INVX2TS U6519 ( .A(n4256), .Y(n2300) );
INVX2TS U6520 ( .A(n4257), .Y(n2310) );
INVX2TS U6521 ( .A(n4258), .Y(n2303) );
INVX2TS U6522 ( .A(n4261), .Y(n2312) );
INVX2TS U6523 ( .A(n4265), .Y(n2325) );
INVX2TS U6524 ( .A(n4269), .Y(n2309) );
BUFX3TS U6525 ( .A(n6666), .Y(n6560) );
AOI22X1TS U6526 ( .A0(n4282), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[47]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[47]), .B1(n6560), .Y(n4270) );
AOI22X1TS U6527 ( .A0(n4282), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[50]), .B1(n6560), .Y(n4271) );
BUFX3TS U6528 ( .A(n4272), .Y(n4341) );
AOI22X1TS U6529 ( .A0(n4282), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[46]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[46]), .B1(n4341), .Y(n4273) );
OAI21X1TS U6530 ( .A0(n6598), .A1(n4284), .B0(n4273), .Y(n1782) );
AOI22X1TS U6531 ( .A0(n4343), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[42]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[42]), .B1(n4341), .Y(n4274) );
OAI21X1TS U6532 ( .A0(n6599), .A1(n4284), .B0(n4274), .Y(n1790) );
AOI22X1TS U6533 ( .A0(n4282), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[34]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[34]), .B1(n6560), .Y(n4275) );
OAI21X1TS U6534 ( .A0(n6600), .A1(n4284), .B0(n4275), .Y(n1774) );
AOI22X1TS U6535 ( .A0(n4282), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[48]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[48]), .B1(n6560), .Y(n4276) );
OAI21X1TS U6536 ( .A0(n6660), .A1(n4284), .B0(n4276), .Y(n1758) );
AOI22X1TS U6537 ( .A0(n4282), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[49]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[49]), .B1(n6560), .Y(n4277) );
OAI21X1TS U6538 ( .A0(n6631), .A1(n4284), .B0(n4277), .Y(n1754) );
AOI22X1TS U6539 ( .A0(n4282), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[45]), .B1(n4341), .Y(n4278) );
OAI21X1TS U6540 ( .A0(n6624), .A1(n4284), .B0(n4278), .Y(n1778) );
AOI22X1TS U6541 ( .A0(n4282), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[3]), .B1(n6560), .Y(n4279) );
OAI21X1TS U6542 ( .A0(n6612), .A1(n4284), .B0(n4279), .Y(n1770) );
AOI22X1TS U6543 ( .A0(n4282), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[33]), .B1(n6560), .Y(n4280) );
OAI21X1TS U6544 ( .A0(n6628), .A1(n4284), .B0(n4280), .Y(n1762) );
AOI22X1TS U6545 ( .A0(n4343), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[35]), .B1(n4341), .Y(n4281) );
AOI22X1TS U6546 ( .A0(n4282), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[44]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[44]), .B1(n6560), .Y(n4283) );
INVX2TS U6547 ( .A(n4285), .Y(n2287) );
INVX2TS U6548 ( .A(n4287), .Y(n2282) );
INVX2TS U6549 ( .A(n4288), .Y(n2288) );
INVX2TS U6550 ( .A(n4289), .Y(n2284) );
INVX2TS U6551 ( .A(n4290), .Y(n2283) );
INVX2TS U6552 ( .A(n4291), .Y(n2290) );
INVX2TS U6553 ( .A(n4292), .Y(n2285) );
AOI222X1TS U6554 ( .A0(n4294), .A1(data_output[51]), .B0(n4204), .B1(n3228),
.C0(n4313), .C1(n3229), .Y(n4293) );
INVX2TS U6555 ( .A(n4293), .Y(n2289) );
INVX2TS U6556 ( .A(n4295), .Y(n2286) );
BUFX3TS U6557 ( .A(n6572), .Y(n4881) );
AOI22X1TS U6558 ( .A0(n4536), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[1]), .B1(n4881), .Y(n4296) );
INVX2TS U6559 ( .A(n4298), .Y(n2281) );
AOI22X1TS U6560 ( .A0(n4536), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[0]), .B1(n4881), .Y(n4299) );
AOI22X1TS U6561 ( .A0(n4536), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[2]), .B1(n4881), .Y(n4300) );
AOI22X1TS U6562 ( .A0(n4364), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[32]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[32]), .B1(n4363), .Y(n4301) );
BUFX3TS U6563 ( .A(n4272), .Y(n4912) );
AOI22X1TS U6564 ( .A0(n4374), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[9]), .B1(n4912), .Y(n4302) );
BUFX3TS U6565 ( .A(n4272), .Y(n4902) );
AOI22X1TS U6566 ( .A0(n4371), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[51]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[51]), .B1(n4902), .Y(n4303) );
AOI22X1TS U6567 ( .A0(n4374), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[9]), .B1(n4912), .Y(n4304) );
AOI22X1TS U6568 ( .A0(n4371), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[1]), .B1(n4881), .Y(n4305) );
OAI21X1TS U6569 ( .A0(n6658), .A1(n4366), .B0(n4305), .Y(n1878) );
AOI22X1TS U6570 ( .A0(n4364), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[14]), .B1(n4363), .Y(n4306) );
OAI21X1TS U6571 ( .A0(n6610), .A1(n4366), .B0(n4306), .Y(n1850) );
AOI22X1TS U6572 ( .A0(n4364), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[13]), .B1(n4881), .Y(n4307) );
OAI21X1TS U6573 ( .A0(n6614), .A1(n4366), .B0(n4307), .Y(n1858) );
AOI22X1TS U6574 ( .A0(n4364), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[15]), .B1(n4363), .Y(n4308) );
OAI21X1TS U6575 ( .A0(n6617), .A1(n4366), .B0(n4308), .Y(n1834) );
BUFX3TS U6576 ( .A(n6572), .Y(n4893) );
AOI22X1TS U6577 ( .A0(n4374), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[23]), .B1(n4893), .Y(n4309) );
OAI21X1TS U6578 ( .A0(n6622), .A1(n4373), .B0(n4309), .Y(n1933) );
AOI22X1TS U6579 ( .A0(n4364), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[30]), .B1(n4363), .Y(n4310) );
OAI21X1TS U6580 ( .A0(n6601), .A1(n4366), .B0(n4310), .Y(n1838) );
AOI222X1TS U6581 ( .A0(n4286), .A1(data_output[62]), .B0(n4204), .B1(
d_ff_Yn[62]), .C0(n4313), .C1(n3230), .Y(n4311) );
INVX2TS U6582 ( .A(n4311), .Y(n2278) );
AOI222X1TS U6583 ( .A0(n4286), .A1(data_output[61]), .B0(n4229), .B1(n3222),
.C0(n4313), .C1(n3233), .Y(n4312) );
INVX2TS U6584 ( .A(n4312), .Y(n2279) );
AOI222X1TS U6585 ( .A0(n4286), .A1(data_output[60]), .B0(n4229), .B1(n3227),
.C0(n4313), .C1(n3231), .Y(n4314) );
INVX2TS U6586 ( .A(n4314), .Y(n2280) );
INVX4TS U6587 ( .A(n4536), .Y(n4345) );
AOI22X1TS U6588 ( .A0(n4343), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[43]), .B1(n4341), .Y(n4315) );
AOI22X1TS U6589 ( .A0(n4348), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[51]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[51]), .B1(n4918), .Y(n4316) );
AOI22X1TS U6590 ( .A0(n4343), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[40]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[40]), .B1(n4341), .Y(n4317) );
INVX4TS U6591 ( .A(n4536), .Y(n4352) );
BUFX3TS U6592 ( .A(n4272), .Y(n4915) );
AOI22X1TS U6593 ( .A0(n4348), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[42]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[42]), .B1(n4915), .Y(n4318) );
AOI22X1TS U6594 ( .A0(n4348), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[46]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[46]), .B1(n4915), .Y(n4319) );
AOI22X1TS U6595 ( .A0(n4954), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[54]), .B1(n4950), .Y(n4320) );
AOI22X1TS U6596 ( .A0(n4348), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[47]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[47]), .B1(n4918), .Y(n4321) );
AOI22X1TS U6597 ( .A0(n4348), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[55]), .B1(n4950), .Y(n4322) );
AOI22X1TS U6598 ( .A0(n4343), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[36]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[36]), .B1(n4341), .Y(n4323) );
AOI22X1TS U6599 ( .A0(n4348), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[48]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[48]), .B1(n4918), .Y(n4324) );
AOI22X1TS U6600 ( .A0(n4343), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[38]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[38]), .B1(n4341), .Y(n4325) );
AOI22X1TS U6601 ( .A0(n4348), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[49]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[49]), .B1(n4918), .Y(n4326) );
AOI22X1TS U6602 ( .A0(n4343), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[28]), .B1(n4363), .Y(n4327) );
AOI22X1TS U6603 ( .A0(n4348), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[34]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[34]), .B1(n4915), .Y(n4328) );
BUFX3TS U6604 ( .A(n4272), .Y(n4896) );
AOI22X1TS U6605 ( .A0(n4361), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[32]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[32]), .B1(n4896), .Y(n4329) );
AOI22X1TS U6606 ( .A0(n4361), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[40]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[40]), .B1(n4896), .Y(n4330) );
AOI22X1TS U6607 ( .A0(n4361), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[28]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[28]), .B1(n4896), .Y(n4331) );
AOI22X1TS U6608 ( .A0(n4361), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[36]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[36]), .B1(n4915), .Y(n4332) );
AOI22X1TS U6609 ( .A0(n4954), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[53]), .B1(n4950), .Y(n4333) );
AOI22X1TS U6610 ( .A0(n4364), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[0]), .B1(n4881), .Y(n4334) );
AOI22X1TS U6611 ( .A0(n4374), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[7]), .B1(n4902), .Y(n4335) );
AOI22X1TS U6612 ( .A0(n4371), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[5]), .B1(n4893), .Y(n4336) );
OAI21X1TS U6613 ( .A0(n6651), .A1(n4373), .B0(n4336), .Y(n1899) );
AOI22X1TS U6614 ( .A0(n4364), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[31]), .B1(n4363), .Y(n4337) );
AOI22X1TS U6615 ( .A0(n4954), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[56]), .B1(n4918), .Y(n4338) );
AOI22X1TS U6616 ( .A0(n4343), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[39]), .B1(n4341), .Y(n4339) );
AOI22X1TS U6617 ( .A0(n4364), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[12]), .B1(n4363), .Y(n4340) );
AOI22X1TS U6618 ( .A0(n4343), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[41]), .B1(n4341), .Y(n4342) );
AOI22X1TS U6619 ( .A0(n4343), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[37]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[37]), .B1(n4363), .Y(n4344) );
AOI22X1TS U6620 ( .A0(n4361), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[43]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[43]), .B1(n4915), .Y(n4346) );
AOI22X1TS U6621 ( .A0(n4361), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[38]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[38]), .B1(n4907), .Y(n4347) );
AOI22X1TS U6622 ( .A0(n4348), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[44]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[44]), .B1(n4896), .Y(n4349) );
AOI22X1TS U6623 ( .A0(n4361), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[30]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[30]), .B1(n4896), .Y(n4351) );
AOI22X1TS U6624 ( .A0(n4371), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[2]), .B1(n4881), .Y(n4353) );
OAI21X1TS U6625 ( .A0(n6645), .A1(n4366), .B0(n4353), .Y(n1885) );
AOI22X1TS U6626 ( .A0(n4374), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[6]), .B1(n4902), .Y(n4354) );
AOI22X1TS U6627 ( .A0(n4374), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[22]), .B1(n4912), .Y(n4355) );
OAI21X1TS U6628 ( .A0(n6608), .A1(n4373), .B0(n4355), .Y(n1946) );
AOI22X1TS U6629 ( .A0(n4371), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[27]), .B1(n4893), .Y(n4356) );
OAI21X1TS U6630 ( .A0(n6605), .A1(n4373), .B0(n4356), .Y(n1915) );
AOI22X1TS U6631 ( .A0(n4361), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[19]), .B1(n4907), .Y(n4357) );
AOI22X1TS U6632 ( .A0(n4374), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[10]), .B1(n4902), .Y(n4358) );
AOI22X1TS U6633 ( .A0(n4371), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[25]), .B1(n4893), .Y(n4359) );
OAI21X1TS U6634 ( .A0(n6604), .A1(n4373), .B0(n4359), .Y(n1919) );
AOI22X1TS U6635 ( .A0(n4374), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[24]), .B1(n4893), .Y(n4360) );
OAI21X1TS U6636 ( .A0(n6644), .A1(n4373), .B0(n4360), .Y(n1926) );
AOI22X1TS U6637 ( .A0(n4361), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[18]), .B1(n4907), .Y(n4362) );
AOI22X1TS U6638 ( .A0(n4364), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[17]), .B1(n4363), .Y(n4365) );
OAI21X1TS U6639 ( .A0(n6619), .A1(n4366), .B0(n4365), .Y(n1842) );
AOI22X1TS U6640 ( .A0(n4371), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[11]), .B1(n4893), .Y(n4367) );
OAI21X1TS U6641 ( .A0(n6615), .A1(n4373), .B0(n4367), .Y(n1907) );
AOI22X1TS U6642 ( .A0(n4371), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[26]), .B1(n4893), .Y(n4368) );
OAI21X1TS U6643 ( .A0(n6606), .A1(n4373), .B0(n4368), .Y(n1911) );
AOI22X1TS U6644 ( .A0(n4374), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[20]), .B1(n4902), .Y(n4369) );
AOI22X1TS U6645 ( .A0(n4371), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[4]), .B1(n4881), .Y(n4370) );
OAI21X1TS U6646 ( .A0(n6613), .A1(n4373), .B0(n4370), .Y(n1894) );
AOI22X1TS U6647 ( .A0(n4371), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[8]), .B1(n4893), .Y(n4372) );
OAI21X1TS U6648 ( .A0(n6616), .A1(n4373), .B0(n4372), .Y(n1903) );
AOI22X1TS U6649 ( .A0(n4374), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[21]), .B1(n4912), .Y(n4375) );
NAND2X1TS U6650 ( .A(n4716), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .Y(n4378) );
NAND2X1TS U6651 ( .A(n4706), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .Y(n4377) );
NAND3X1TS U6652 ( .A(n4378), .B(n4377), .C(n4661), .Y(n4641) );
NAND2X1TS U6653 ( .A(n4641), .B(n3209), .Y(n4379) );
NAND2X2TS U6654 ( .A(n3301), .B(n3299), .Y(n4388) );
OR2X2TS U6655 ( .A(inst_FPU_PIPELINED_FPADDSUB_ADD_OVRFLW_NRM2), .B(
inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n4383) );
OAI21X4TS U6656 ( .A0(n4388), .A1(n4405), .B0(n4387), .Y(n4397) );
AOI21X4TS U6657 ( .A0(n3298), .A1(n4397), .B0(n4390), .Y(n4412) );
INVX2TS U6658 ( .A(n4405), .Y(n4400) );
AFHCONX2TS U6659 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n3182), .CI(n4407), .CON(n4405), .S(n6024) );
AND4X1TS U6660 ( .A(n6039), .B(n6025), .C(n6038), .D(n6024), .Y(n4413) );
AOI21X4TS U6661 ( .A0(n4416), .A1(n3300), .B0(n4415), .Y(n4437) );
AOI21X4TS U6662 ( .A0(n4432), .A1(n3295), .B0(n4417), .Y(n4425) );
OAI21X4TS U6663 ( .A0(n4425), .A1(n4421), .B0(n4422), .Y(n4443) );
AOI21X4TS U6664 ( .A0(n4443), .A1(n3296), .B0(n4418), .Y(n4447) );
NAND2X1TS U6665 ( .A(n4445), .B(n4447), .Y(n4419) );
INVX2TS U6666 ( .A(n6039), .Y(n4427) );
INVX2TS U6667 ( .A(n6025), .Y(n4426) );
INVX2TS U6668 ( .A(n6027), .Y(n4439) );
INVX2TS U6669 ( .A(n4433), .Y(n4435) );
INVX2TS U6670 ( .A(n6026), .Y(n4438) );
NOR2X2TS U6671 ( .A(n4444), .B(n6028), .Y(n4448) );
NAND2BX4TS U6672 ( .AN(n4450), .B(n4449), .Y(n6037) );
INVX2TS U6673 ( .A(n3219), .Y(n4691) );
BUFX3TS U6674 ( .A(n4691), .Y(n5447) );
NAND2X1TS U6675 ( .A(n4722), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .Y(n4454) );
NAND2X1TS U6676 ( .A(n4723), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .Y(n4453) );
NAND2X1TS U6677 ( .A(n4724), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .Y(n4452) );
NAND2X1TS U6678 ( .A(n4706), .B(n3238), .Y(n4451) );
NAND4X1TS U6679 ( .A(n4454), .B(n4453), .C(n4452), .D(n4451), .Y(n4634) );
INVX2TS U6680 ( .A(n4488), .Y(n4841) );
NAND2X1TS U6681 ( .A(n4634), .B(n4841), .Y(n4457) );
INVX2TS U6682 ( .A(n3943), .Y(n4765) );
NAND2X1TS U6683 ( .A(n4765), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .Y(n4456) );
NAND2X1TS U6684 ( .A(n5374), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .Y(n4455) );
NAND2X1TS U6685 ( .A(n3213), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .Y(n4464) );
NAND2X1TS U6686 ( .A(n3205), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .Y(n4463) );
BUFX3TS U6687 ( .A(n4724), .Y(n4672) );
AOI22X1TS U6688 ( .A0(n4672), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]), .B0(n4718), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .Y(n4460) );
BUFX3TS U6689 ( .A(n4552), .Y(n4707) );
AOI22X1TS U6690 ( .A0(n4707), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .B0(n4598), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .Y(n4459) );
NAND2X1TS U6691 ( .A(n4460), .B(n4459), .Y(n4540) );
INVX2TS U6692 ( .A(n4785), .Y(n4843) );
NAND2X1TS U6693 ( .A(inst_FPU_PIPELINED_FPADDSUB_shift_value_SHT2_EWR[5]),
.B(inst_FPU_PIPELINED_FPADDSUB_bit_shift_SHT2), .Y(n5990) );
AOI21X1TS U6694 ( .A0(n4540), .A1(n4843), .B0(n4461), .Y(n4462) );
NOR2X2TS U6695 ( .A(n4466), .B(n4465), .Y(n5379) );
AOI2BB2X1TS U6696 ( .B0(result_add_subt[5]), .B1(n5447), .A0N(n3302), .A1N(
n5379), .Y(n4467) );
NAND2X1TS U6697 ( .A(n4722), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .Y(n4471) );
NAND2X1TS U6698 ( .A(n4723), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]), .Y(n4470) );
NAND2X1TS U6699 ( .A(n4724), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .Y(n4469) );
NAND2X1TS U6700 ( .A(n4719), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .Y(n4468) );
NAND4X1TS U6701 ( .A(n4471), .B(n4470), .C(n4469), .D(n4468), .Y(n4801) );
INVX2TS U6702 ( .A(n4647), .Y(n5987) );
NAND2X1TS U6703 ( .A(n4801), .B(n3208), .Y(n4472) );
NAND2X1TS U6704 ( .A(n4472), .B(n4763), .Y(n4834) );
INVX2TS U6705 ( .A(n4834), .Y(n5401) );
OAI22X1TS U6706 ( .A0(n5370), .A1(n6667), .B0(n4750), .B1(n6735), .Y(n4479)
);
AOI22X1TS U6707 ( .A0(n4707), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .B0(n4716), .B1(n3239), .Y(n4475) );
BUFX3TS U6708 ( .A(n4473), .Y(n4704) );
AOI22X1TS U6709 ( .A0(n4706), .A1(n3240), .B0(n4704), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .Y(n4474) );
NAND2X1TS U6710 ( .A(n4475), .B(n4474), .Y(n4807) );
AOI21X1TS U6711 ( .A0(n4843), .A1(n4807), .B0(n4461), .Y(n4478) );
NAND2X1TS U6712 ( .A(n3205), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .Y(n4477) );
NAND2X1TS U6713 ( .A(n3213), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .Y(n4476) );
NAND2X1TS U6714 ( .A(n4722), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]), .Y(n4482) );
NAND2X1TS U6715 ( .A(n4716), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .Y(n4481) );
NAND2X1TS U6716 ( .A(n4706), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .Y(n4480) );
NAND4X1TS U6717 ( .A(n4590), .B(n4482), .C(n4481), .D(n4480), .Y(n4805) );
NOR2X2TS U6718 ( .A(n4484), .B(n4483), .Y(n5400) );
AOI2BB2X1TS U6719 ( .B0(result_add_subt[12]), .B1(n5447), .A0N(n3302), .A1N(
n5400), .Y(n4485) );
NAND2X1TS U6720 ( .A(n4805), .B(n3209), .Y(n4487) );
CLKBUFX2TS U6721 ( .A(n4486), .Y(n4837) );
INVX2TS U6722 ( .A(n4488), .Y(n4776) );
NAND2X1TS U6723 ( .A(n4801), .B(n4776), .Y(n4491) );
NAND2X1TS U6724 ( .A(n4765), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .Y(n4490) );
NAND2X1TS U6725 ( .A(n5374), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .Y(n4489) );
NAND2X1TS U6726 ( .A(n5371), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .Y(n4496) );
NAND2X1TS U6727 ( .A(n3206), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .Y(n4495) );
AOI22X1TS U6728 ( .A0(n4672), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]), .B0(n4718), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .Y(n4493) );
AOI22X1TS U6729 ( .A0(n4707), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .B0(n4719), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .Y(n4492) );
NAND2X1TS U6730 ( .A(n4493), .B(n4492), .Y(n4802) );
AOI21X1TS U6731 ( .A0(n5985), .A1(n4802), .B0(n4461), .Y(n4494) );
NOR2X2TS U6732 ( .A(n4498), .B(n4497), .Y(n5383) );
AOI2BB2X1TS U6733 ( .B0(result_add_subt[6]), .B1(n5447), .A0N(n3302), .A1N(
n5383), .Y(n4499) );
NAND2X1TS U6734 ( .A(n4722), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]), .Y(n4502) );
NAND2X1TS U6735 ( .A(n4598), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .Y(n4501) );
NAND2X1TS U6736 ( .A(n4705), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .Y(n4500) );
NAND4X1TS U6737 ( .A(n4590), .B(n4502), .C(n4501), .D(n4500), .Y(n4738) );
NAND2X1TS U6738 ( .A(n4738), .B(n5987), .Y(n4503) );
NAND2X1TS U6739 ( .A(n4722), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .Y(n4507) );
NAND2X1TS U6740 ( .A(n4723), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]), .Y(n4506) );
NAND2X1TS U6741 ( .A(n4705), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .Y(n4505) );
NAND2X1TS U6742 ( .A(n4598), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .Y(n4504) );
NAND4X1TS U6743 ( .A(n4507), .B(n4506), .C(n4505), .D(n4504), .Y(n4742) );
NAND2X1TS U6744 ( .A(n4742), .B(n4776), .Y(n4510) );
NAND2X1TS U6745 ( .A(n4765), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .Y(n4509) );
NAND2X1TS U6746 ( .A(n5374), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .Y(n4508) );
NAND2X1TS U6747 ( .A(n5371), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .Y(n4515) );
NAND2X1TS U6748 ( .A(n3206), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .Y(n4514) );
AOI22X1TS U6749 ( .A0(n4706), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]), .B0(n4704), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .Y(n4512) );
AOI22X1TS U6750 ( .A0(n4707), .A1(n3239), .B0(n4716), .B1(n3240), .Y(n4511)
);
NAND2X1TS U6751 ( .A(n4512), .B(n4511), .Y(n4743) );
AOI21X1TS U6752 ( .A0(n4733), .A1(n4743), .B0(n4461), .Y(n4513) );
NOR2X2TS U6753 ( .A(n4517), .B(n4516), .Y(n5388) );
AOI2BB2X1TS U6754 ( .B0(result_add_subt[8]), .B1(n5447), .A0N(n3302), .A1N(
n5388), .Y(n4518) );
NAND2X1TS U6755 ( .A(n4725), .B(n6712), .Y(n4519) );
NAND2X1TS U6756 ( .A(n4669), .B(n4519), .Y(n4686) );
INVX2TS U6757 ( .A(n4837), .Y(n5359) );
NOR2X2TS U6758 ( .A(n4520), .B(n5359), .Y(n5382) );
NAND2X1TS U6759 ( .A(n4724), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]), .Y(n4522) );
NAND2X1TS U6760 ( .A(n4598), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .Y(n4521) );
NAND2X1TS U6761 ( .A(n3224), .B(n4839), .Y(n4525) );
NAND2X1TS U6762 ( .A(n3213), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .Y(n4524) );
NAND2X1TS U6763 ( .A(n3206), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .Y(n4523) );
NAND2X1TS U6764 ( .A(n4765), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .Y(n4532) );
AOI22X1TS U6765 ( .A0(n4717), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]), .B0(n4719), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .Y(n4527) );
AOI22X1TS U6766 ( .A0(n4672), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .B0(n4718), .B1(n3240), .Y(n4526) );
NAND2X1TS U6767 ( .A(n4527), .B(n4526), .Y(n4568) );
AOI22X1TS U6768 ( .A0(n4672), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .B0(n4706), .B1(n3239), .Y(n4529) );
AOI22X1TS U6769 ( .A0(n4717), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .B0(n4718), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .Y(n4528) );
NAND2X1TS U6770 ( .A(n4529), .B(n4528), .Y(n4622) );
AOI22X1TS U6771 ( .A0(n4843), .A1(n4568), .B0(n5367), .B1(n4622), .Y(n4531)
);
NAND2X1TS U6772 ( .A(n5374), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]), .Y(n4530) );
NOR2X2TS U6773 ( .A(n4534), .B(n4533), .Y(n5381) );
AOI2BB2X1TS U6774 ( .B0(result_add_subt[0]), .B1(n5447), .A0N(n3302), .A1N(
n5381), .Y(n4535) );
AOI222X1TS U6775 ( .A0(n4954), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[55]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[55]), .B1(n6572), .C0(n4536),
.C1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .Y(n4537) );
INVX2TS U6776 ( .A(n4537), .Y(n2188) );
AOI22X1TS U6777 ( .A0(n4851), .A1(n3193), .B0(result_add_subt[51]), .B1(
n5447), .Y(n4538) );
NAND2X1TS U6778 ( .A(n4634), .B(n5985), .Y(n4542) );
AOI21X1TS U6779 ( .A0(n3208), .A1(n4540), .B0(n3214), .Y(n4541) );
NAND2X1TS U6780 ( .A(n4542), .B(n4541), .Y(n4659) );
INVX2TS U6781 ( .A(n4659), .Y(n5416) );
NAND2X1TS U6782 ( .A(n4641), .B(n5363), .Y(n4546) );
AOI22X1TS U6783 ( .A0(n4598), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .B0(n4704), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .Y(n4544) );
AOI22X1TS U6784 ( .A0(n4552), .A1(n3238), .B0(n4716), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .Y(n4543) );
NAND2X1TS U6785 ( .A(n4544), .B(n4543), .Y(n4638) );
AOI21X1TS U6786 ( .A0(n3209), .A1(n4638), .B0(n4806), .Y(n4545) );
INVX2TS U6787 ( .A(n5417), .Y(n4547) );
AOI22X1TS U6788 ( .A0(n4830), .A1(n4547), .B0(result_add_subt[29]), .B1(
n3218), .Y(n4548) );
NAND2X1TS U6789 ( .A(n4742), .B(n3208), .Y(n4549) );
NAND2X1TS U6790 ( .A(n4549), .B(n4763), .Y(n4774) );
INVX2TS U6791 ( .A(n4774), .Y(n5393) );
NAND2X1TS U6792 ( .A(n4738), .B(n4776), .Y(n4560) );
AOI22X1TS U6793 ( .A0(n4552), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .B0(n4725), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]), .Y(n4554) );
AOI22X1TS U6794 ( .A0(n4705), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .B0(n4704), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .Y(n4553) );
NAND2X1TS U6795 ( .A(n4554), .B(n4553), .Y(n4739) );
INVX2TS U6796 ( .A(n4461), .Y(n4753) );
OAI2BB1X1TS U6797 ( .A0N(n4739), .A1N(n4843), .B0(n4753), .Y(n4556) );
NAND2X1TS U6798 ( .A(n5371), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .Y(n4557) );
NAND4X1TS U6799 ( .A(n4560), .B(n4559), .C(n4558), .D(n4557), .Y(n4773) );
BUFX3TS U6800 ( .A(n4691), .Y(n4850) );
AOI22X1TS U6801 ( .A0(n4851), .A1(n4773), .B0(result_add_subt[10]), .B1(
n4850), .Y(n4561) );
NOR2X1TS U6802 ( .A(n4686), .B(n4785), .Y(n4567) );
NAND2X1TS U6803 ( .A(n4723), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .Y(n4565) );
NAND2X1TS U6804 ( .A(n4722), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .Y(n4564) );
NAND2X1TS U6805 ( .A(n4724), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .Y(n4563) );
NAND2X1TS U6806 ( .A(n4719), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .Y(n4562) );
NAND4X1TS U6807 ( .A(n4565), .B(n4564), .C(n4563), .D(n4562), .Y(n4683) );
NOR3X2TS U6808 ( .A(n4567), .B(n3214), .C(n4566), .Y(n5409) );
NAND2X1TS U6809 ( .A(n3224), .B(n4776), .Y(n4570) );
INVX2TS U6810 ( .A(n4785), .Y(n4733) );
AOI22X1TS U6811 ( .A0(n5363), .A1(n4622), .B0(n5987), .B1(n4568), .Y(n4569)
);
AOI22X1TS U6812 ( .A0(n4861), .A1(n4828), .B0(result_add_subt[16]), .B1(
n4850), .Y(n4571) );
NAND2X1TS U6813 ( .A(n4705), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .Y(n4574) );
NAND2X1TS U6814 ( .A(n4717), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .Y(n4573) );
NAND2X1TS U6815 ( .A(n4706), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .Y(n4572) );
NAND4X1TS U6816 ( .A(n4590), .B(n4574), .C(n4573), .D(n4572), .Y(n5986) );
NAND2X1TS U6817 ( .A(n5986), .B(n3209), .Y(n4575) );
NOR3X1TS U6818 ( .A(n4577), .B(n4576), .C(n4461), .Y(n4584) );
NAND2X1TS U6819 ( .A(n4717), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .Y(n4581) );
NAND2X1TS U6820 ( .A(n4723), .B(n3238), .Y(n4580) );
NAND2X1TS U6821 ( .A(n4705), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .Y(n4579) );
NAND2X1TS U6822 ( .A(n4706), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]), .Y(n4578) );
NAND2X1TS U6823 ( .A(n5988), .B(n4733), .Y(n4583) );
NAND2X1TS U6824 ( .A(n5986), .B(n4841), .Y(n4582) );
NAND4X1TS U6825 ( .A(n4585), .B(n4584), .C(n4583), .D(n4582), .Y(n4795) );
AOI22X1TS U6826 ( .A0(n4851), .A1(n4795), .B0(result_add_subt[9]), .B1(n4850), .Y(n4586) );
NAND2X1TS U6827 ( .A(n4722), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]), .Y(n4589) );
NAND2X1TS U6828 ( .A(n4705), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .Y(n4588) );
NAND2X1TS U6829 ( .A(n4719), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .Y(n4587) );
NAND4X1TS U6830 ( .A(n4590), .B(n4589), .C(n4588), .D(n4587), .Y(n4749) );
NAND2X1TS U6831 ( .A(n4749), .B(n5360), .Y(n4591) );
AOI22X1TS U6832 ( .A0(n4672), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]), .B0(n4704), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .Y(n4593) );
AOI22X1TS U6833 ( .A0(n4707), .A1(n3241), .B0(n4598), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .Y(n4592) );
NAND2X1TS U6834 ( .A(n4593), .B(n4592), .Y(n4693) );
OAI2BB1X1TS U6835 ( .A0N(n4693), .A1N(n5363), .B0(n4753), .Y(n4595) );
NAND2X1TS U6836 ( .A(n4722), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .Y(n4602) );
NAND2X1TS U6837 ( .A(n4723), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]), .Y(n4601) );
NAND2X1TS U6838 ( .A(n4705), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .Y(n4600) );
NAND2X1TS U6839 ( .A(n4719), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .Y(n4599) );
NAND4X1TS U6840 ( .A(n4602), .B(n4601), .C(n4600), .D(n4599), .Y(n4747) );
NAND2X1TS U6841 ( .A(n4747), .B(n4776), .Y(n4604) );
NAND2X1TS U6842 ( .A(n5371), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .Y(n4603) );
NAND4X1TS U6843 ( .A(n4606), .B(n4605), .C(n4604), .D(n4603), .Y(n4798) );
AOI22X1TS U6844 ( .A0(n4851), .A1(n4798), .B0(result_add_subt[7]), .B1(n4850), .Y(n4607) );
NAND2X1TS U6845 ( .A(n4719), .B(n6713), .Y(n4608) );
NAND2X1TS U6846 ( .A(n4650), .B(n4733), .Y(n4612) );
AOI22X1TS U6847 ( .A0(n4725), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .B0(n4718), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .Y(n4610) );
AOI22X1TS U6848 ( .A0(n4717), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .B0(n4716), .B1(n3238), .Y(n4609) );
NAND2X1TS U6849 ( .A(n4610), .B(n4609), .Y(n4651) );
AOI21X1TS U6850 ( .A0(n5360), .A1(n4651), .B0(n4806), .Y(n4611) );
NAND2X1TS U6851 ( .A(n4650), .B(n4776), .Y(n4617) );
AOI22X1TS U6852 ( .A0(n4672), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .B0(n4719), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .Y(n4614) );
AOI22X1TS U6853 ( .A0(n4717), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]), .B0(n4718), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .Y(n4613) );
NAND2X1TS U6854 ( .A(n4614), .B(n4613), .Y(n4652) );
AOI22X1TS U6855 ( .A0(n4733), .A1(n4651), .B0(n4836), .B1(n4652), .Y(n4615)
);
NAND2X1TS U6856 ( .A(n4617), .B(n4616), .Y(n4619) );
AOI22X1TS U6857 ( .A0(n4861), .A1(n4619), .B0(result_add_subt[17]), .B1(
n4850), .Y(n4618) );
INVX2TS U6858 ( .A(n4619), .Y(n5412) );
INVX2TS U6859 ( .A(n5413), .Y(n4620) );
AOI22X1TS U6860 ( .A0(n4830), .A1(n4620), .B0(result_add_subt[33]), .B1(
n3218), .Y(n4621) );
NAND2X1TS U6861 ( .A(n3224), .B(n5985), .Y(n4624) );
AOI21X1TS U6862 ( .A0(n5987), .A1(n4622), .B0(n4806), .Y(n4623) );
AOI22X1TS U6863 ( .A0(n4672), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .B0(n4718), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .Y(n4626) );
AOI22X1TS U6864 ( .A0(n4717), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]), .B0(n4598), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .Y(n4625) );
NAND2X1TS U6865 ( .A(n4626), .B(n4625), .Y(n4688) );
AOI21X1TS U6866 ( .A0(n4688), .A1(n5987), .B0(n4461), .Y(n4628) );
NAND2X1TS U6867 ( .A(n4683), .B(n5985), .Y(n4627) );
BUFX3TS U6868 ( .A(n4691), .Y(n4859) );
AOI22X1TS U6869 ( .A0(n4861), .A1(n4631), .B0(result_add_subt[18]), .B1(
n4859), .Y(n4630) );
INVX2TS U6870 ( .A(n4631), .Y(n5395) );
INVX2TS U6871 ( .A(n5396), .Y(n4632) );
AOI22X1TS U6872 ( .A0(n4830), .A1(n4632), .B0(result_add_subt[32]), .B1(
n3218), .Y(n4633) );
NAND2X1TS U6873 ( .A(n4634), .B(n5360), .Y(n4635) );
NAND2X1TS U6874 ( .A(n4635), .B(n4837), .Y(n4813) );
INVX2TS U6875 ( .A(n4813), .Y(n5399) );
OAI2BB1X1TS U6876 ( .A0N(n4638), .A1N(n5363), .B0(n4753), .Y(n4640) );
NAND2X1TS U6877 ( .A(n5371), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .Y(n4643) );
NAND2X1TS U6878 ( .A(n4641), .B(n5367), .Y(n4642) );
NAND4X1TS U6879 ( .A(n4645), .B(n4644), .C(n4643), .D(n4642), .Y(n4812) );
AOI22X1TS U6880 ( .A0(n4851), .A1(n4812), .B0(result_add_subt[13]), .B1(
n4850), .Y(n4646) );
INVX2TS U6881 ( .A(n4650), .Y(n4648) );
NOR2X2TS U6882 ( .A(n4649), .B(n5359), .Y(n5432) );
NAND2X1TS U6883 ( .A(n4650), .B(n4839), .Y(n4657) );
AOI22X1TS U6884 ( .A0(n4843), .A1(n4652), .B0(n4841), .B1(n4651), .Y(n4653)
);
OA21XLTS U6885 ( .A0(n5370), .A1(n6738), .B0(n4653), .Y(n4656) );
NAND2X1TS U6886 ( .A(n5374), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]), .Y(n4654) );
NAND4X1TS U6887 ( .A(n4657), .B(n4656), .C(n4655), .D(n4654), .Y(n4937) );
AOI22X1TS U6888 ( .A0(n4851), .A1(n4937), .B0(result_add_subt[1]), .B1(n4850), .Y(n4658) );
AOI22X1TS U6889 ( .A0(n4861), .A1(n4659), .B0(result_add_subt[21]), .B1(
n4859), .Y(n4660) );
NAND2X1TS U6890 ( .A(n4724), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]), .Y(n4663) );
NAND2X1TS U6891 ( .A(n4706), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .Y(n4662) );
NAND2X1TS U6892 ( .A(n3225), .B(n4733), .Y(n4667) );
AOI22X1TS U6893 ( .A0(n4672), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .B0(n4704), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .Y(n4665) );
AOI22X1TS U6894 ( .A0(n4707), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .B0(n4725), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[31]), .Y(n4664) );
NAND2X1TS U6895 ( .A(n4665), .B(n4664), .Y(n5366) );
AOI21X1TS U6896 ( .A0(n5987), .A1(n5366), .B0(n4806), .Y(n4666) );
NAND2X1TS U6897 ( .A(n4598), .B(n6714), .Y(n4668) );
NAND2X1TS U6898 ( .A(n5361), .B(n4776), .Y(n4677) );
AOI22X1TS U6899 ( .A0(n4672), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .B0(n4718), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .Y(n4671) );
AOI22X1TS U6900 ( .A0(n4707), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .B0(n4725), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .Y(n4670) );
NAND2X1TS U6901 ( .A(n4671), .B(n4670), .Y(n4840) );
AOI22X1TS U6902 ( .A0(n4672), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]), .B0(n4725), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[22]), .Y(n4674) );
AOI22X1TS U6903 ( .A0(n4707), .A1(n3240), .B0(n4704), .B1(n3239), .Y(n4673)
);
NAND2X1TS U6904 ( .A(n4674), .B(n4673), .Y(n4842) );
AOI22X1TS U6905 ( .A0(n5363), .A1(n4840), .B0(n4836), .B1(n4842), .Y(n4675)
);
NAND2X1TS U6906 ( .A(n4677), .B(n4676), .Y(n4825) );
AOI22X1TS U6907 ( .A0(n4861), .A1(n4825), .B0(result_add_subt[20]), .B1(
n4859), .Y(n4678) );
INVX2TS U6908 ( .A(n5384), .Y(n4679) );
BUFX3TS U6909 ( .A(n4691), .Y(n4928) );
AOI22X1TS U6910 ( .A0(n4856), .A1(n4679), .B0(result_add_subt[44]), .B1(
n4928), .Y(n4680) );
NAND2X1TS U6911 ( .A(n3224), .B(n3209), .Y(n4682) );
NAND2X1TS U6912 ( .A(n4683), .B(n4841), .Y(n4690) );
INVX2TS U6913 ( .A(n4839), .Y(n5365) );
AOI22X1TS U6914 ( .A0(n3213), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .B0(n4765), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .Y(n4685) );
AOI22X1TS U6915 ( .A0(n3205), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .B0(n5374), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .Y(n4684) );
AOI21X1TS U6916 ( .A0(n5985), .A1(n4688), .B0(n4687), .Y(n4689) );
NAND2X1TS U6917 ( .A(n4690), .B(n4689), .Y(n4934) );
AOI22X1TS U6918 ( .A0(n4851), .A1(n4934), .B0(result_add_subt[2]), .B1(n3289), .Y(n4692) );
NAND2X1TS U6919 ( .A(n4747), .B(n5985), .Y(n4695) );
AOI21X1TS U6920 ( .A0(n3208), .A1(n4693), .B0(n3214), .Y(n4694) );
NAND2X1TS U6921 ( .A(n4695), .B(n4694), .Y(n4817) );
INVX2TS U6922 ( .A(n4817), .Y(n5414) );
NAND2X1TS U6923 ( .A(n4749), .B(n5363), .Y(n4699) );
AOI22X1TS U6924 ( .A0(n4705), .A1(n3241), .B0(n4725), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]), .Y(n4697) );
AOI22X1TS U6925 ( .A0(n4707), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .B0(n4704), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .Y(n4696) );
NAND2X1TS U6926 ( .A(n4697), .B(n4696), .Y(n4754) );
AOI21X1TS U6927 ( .A0(n3209), .A1(n4754), .B0(n4806), .Y(n4698) );
INVX2TS U6928 ( .A(n5415), .Y(n4700) );
AOI22X1TS U6929 ( .A0(n4830), .A1(n4700), .B0(result_add_subt[27]), .B1(
n4859), .Y(n4701) );
NAND2X1TS U6930 ( .A(n5361), .B(n5985), .Y(n4703) );
AOI21X1TS U6931 ( .A0(n5360), .A1(n4840), .B0(n3214), .Y(n4702) );
NAND2X1TS U6932 ( .A(n3225), .B(n4776), .Y(n4714) );
NAND2X1TS U6933 ( .A(n4843), .B(n5366), .Y(n4711) );
AOI22X1TS U6934 ( .A0(n4705), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .B0(n4704), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]), .Y(n4709) );
AOI22X1TS U6935 ( .A0(n4707), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[24]), .B0(n4706), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .Y(n4708) );
NAND2X1TS U6936 ( .A(n4709), .B(n4708), .Y(n5362) );
NAND2X1TS U6937 ( .A(n4836), .B(n5362), .Y(n4710) );
NAND2X1TS U6938 ( .A(n4711), .B(n4710), .Y(n4712) );
NAND2X1TS U6939 ( .A(n4714), .B(n4713), .Y(n4854) );
AOI22X1TS U6940 ( .A0(n4861), .A1(n4854), .B0(result_add_subt[14]), .B1(
n4850), .Y(n4715) );
AOI22X1TS U6941 ( .A0(n4717), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]), .B0(n4716), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[25]), .Y(n4721) );
AOI22X1TS U6942 ( .A0(n4719), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .B0(n4718), .B1(n3241), .Y(n4720) );
NAND2X1TS U6943 ( .A(n4721), .B(n4720), .Y(n4769) );
AOI21X1TS U6944 ( .A0(n4769), .A1(n3208), .B0(n4461), .Y(n4731) );
NAND2X1TS U6945 ( .A(n4722), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .Y(n4729) );
NAND2X1TS U6946 ( .A(n4723), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .Y(n4728) );
NAND2X1TS U6947 ( .A(n4724), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .Y(n4727) );
NAND2X1TS U6948 ( .A(n4598), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .Y(n4726) );
NAND4X1TS U6949 ( .A(n4729), .B(n4728), .C(n4727), .D(n4726), .Y(n4787) );
NAND2X1TS U6950 ( .A(n4787), .B(n5985), .Y(n4730) );
INVX2TS U6951 ( .A(n4822), .Y(n5419) );
NAND2X1TS U6952 ( .A(n4777), .B(n5363), .Y(n4735) );
AOI21X1TS U6953 ( .A0(n3209), .A1(n4778), .B0(n4806), .Y(n4734) );
INVX2TS U6954 ( .A(n5421), .Y(n4736) );
AOI22X1TS U6955 ( .A0(n4830), .A1(n4736), .B0(result_add_subt[31]), .B1(
n3218), .Y(n4737) );
NAND2X1TS U6956 ( .A(n4738), .B(n4733), .Y(n4741) );
AOI21X1TS U6957 ( .A0(n5987), .A1(n4739), .B0(n4806), .Y(n4740) );
NAND2X1TS U6958 ( .A(n4742), .B(n4733), .Y(n4745) );
AOI21X1TS U6959 ( .A0(n5987), .A1(n4743), .B0(n3214), .Y(n4744) );
NAND2X1TS U6960 ( .A(n4745), .B(n4744), .Y(n4792) );
AOI22X1TS U6961 ( .A0(n4830), .A1(n4792), .B0(result_add_subt[24]), .B1(
n4859), .Y(n4746) );
NAND2X1TS U6962 ( .A(n4747), .B(n3208), .Y(n4748) );
NAND2X1TS U6963 ( .A(n4748), .B(n4837), .Y(n4820) );
INVX2TS U6964 ( .A(n4820), .Y(n5403) );
NAND2X1TS U6965 ( .A(n4749), .B(n5367), .Y(n4761) );
OAI2BB1X1TS U6966 ( .A0N(n4754), .A1N(n4843), .B0(n4753), .Y(n4757) );
NAND2X1TS U6967 ( .A(n5371), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .Y(n4758) );
NAND4X1TS U6968 ( .A(n4761), .B(n4760), .C(n4759), .D(n4758), .Y(n4819) );
AOI22X1TS U6969 ( .A0(n4851), .A1(n4819), .B0(result_add_subt[11]), .B1(
n4850), .Y(n4762) );
NAND2X1TS U6970 ( .A(n4777), .B(n5360), .Y(n4764) );
NAND2X1TS U6971 ( .A(n4787), .B(n5367), .Y(n4771) );
AOI22X1TS U6972 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .A1(
n3205), .B0(n4765), .B1(inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .Y(n4767) );
AOI22X1TS U6973 ( .A0(n3213), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]), .B1(n5374), .Y(n4766)
);
AOI21X1TS U6974 ( .A0(n4733), .A1(n4769), .B0(n4768), .Y(n4770) );
NAND2X1TS U6975 ( .A(n4771), .B(n4770), .Y(n4922) );
AOI22X1TS U6976 ( .A0(n4851), .A1(n4922), .B0(result_add_subt[3]), .B1(n3289), .Y(n4772) );
INVX2TS U6977 ( .A(n4773), .Y(n5392) );
AOI22X1TS U6978 ( .A0(n4856), .A1(n4774), .B0(result_add_subt[40]), .B1(
n3218), .Y(n4775) );
NAND2X1TS U6979 ( .A(n4777), .B(n4776), .Y(n4784) );
NAND2X1TS U6980 ( .A(n4843), .B(n4778), .Y(n4781) );
NAND2X1TS U6981 ( .A(n4836), .B(n4779), .Y(n4780) );
NAND2X1TS U6982 ( .A(n4781), .B(n4780), .Y(n4782) );
NAND2X1TS U6983 ( .A(n4784), .B(n4783), .Y(n4860) );
INVX2TS U6984 ( .A(n4860), .Y(n5424) );
NOR3X2TS U6985 ( .A(n4789), .B(n3214), .C(n4788), .Y(n5426) );
INVX2TS U6986 ( .A(n5426), .Y(n4790) );
AOI22X1TS U6987 ( .A0(n4856), .A1(n4790), .B0(result_add_subt[35]), .B1(
n4691), .Y(n4791) );
INVX2TS U6988 ( .A(n4792), .Y(n5404) );
INVX2TS U6989 ( .A(n5405), .Y(n4793) );
AOI22X1TS U6990 ( .A0(n4830), .A1(n4793), .B0(result_add_subt[26]), .B1(
n4859), .Y(n4794) );
INVX2TS U6991 ( .A(n4795), .Y(n5390) );
INVX2TS U6992 ( .A(n5391), .Y(n4796) );
AOI22X1TS U6993 ( .A0(n4856), .A1(n4796), .B0(result_add_subt[41]), .B1(
n4928), .Y(n4797) );
INVX2TS U6994 ( .A(n4798), .Y(n5386) );
INVX2TS U6995 ( .A(n5387), .Y(n4799) );
AOI22X1TS U6996 ( .A0(n4856), .A1(n4799), .B0(result_add_subt[43]), .B1(
n4928), .Y(n4800) );
NAND2X1TS U6997 ( .A(n4801), .B(n5363), .Y(n4804) );
AOI21X1TS U6998 ( .A0(n5360), .A1(n4802), .B0(n3214), .Y(n4803) );
NAND2X1TS U6999 ( .A(n4804), .B(n4803), .Y(n4815) );
INVX2TS U7000 ( .A(n4815), .Y(n5406) );
NAND2X1TS U7001 ( .A(n4805), .B(n5985), .Y(n4809) );
AOI21X1TS U7002 ( .A0(n5360), .A1(n4807), .B0(n3214), .Y(n4808) );
INVX2TS U7003 ( .A(n5407), .Y(n4810) );
AOI22X1TS U7004 ( .A0(n4830), .A1(n4810), .B0(result_add_subt[28]), .B1(
n3218), .Y(n4811) );
INVX2TS U7005 ( .A(n4812), .Y(n5398) );
AOI22X1TS U7006 ( .A0(n4856), .A1(n4813), .B0(result_add_subt[37]), .B1(
n4928), .Y(n4814) );
AOI22X1TS U7007 ( .A0(n4861), .A1(n4815), .B0(result_add_subt[22]), .B1(
n4859), .Y(n4816) );
AOI22X1TS U7008 ( .A0(n4861), .A1(n4817), .B0(result_add_subt[23]), .B1(
n4859), .Y(n4818) );
INVX2TS U7009 ( .A(n4819), .Y(n5402) );
AOI22X1TS U7010 ( .A0(n4856), .A1(n4820), .B0(result_add_subt[39]), .B1(
n4928), .Y(n4821) );
AOI22X1TS U7011 ( .A0(n4861), .A1(n4822), .B0(result_add_subt[19]), .B1(
n4859), .Y(n4823) );
INVX2TS U7012 ( .A(n4825), .Y(n5410) );
INVX2TS U7013 ( .A(n5411), .Y(n4826) );
AOI22X1TS U7014 ( .A0(n4830), .A1(n4826), .B0(result_add_subt[30]), .B1(
n3218), .Y(n4827) );
INVX2TS U7015 ( .A(n4828), .Y(n5408) );
INVX2TS U7016 ( .A(n5409), .Y(n4829) );
AOI22X1TS U7017 ( .A0(n4830), .A1(n4829), .B0(result_add_subt[34]), .B1(
n3218), .Y(n4831) );
INVX2TS U7018 ( .A(n5389), .Y(n4832) );
AOI22X1TS U7019 ( .A0(n4856), .A1(n4832), .B0(result_add_subt[42]), .B1(
n4928), .Y(n4833) );
AOI22X1TS U7020 ( .A0(n4856), .A1(n4834), .B0(result_add_subt[38]), .B1(
n4928), .Y(n4835) );
NAND2X1TS U7021 ( .A(n3225), .B(n5987), .Y(n4838) );
NAND2X1TS U7022 ( .A(n5361), .B(n4839), .Y(n4849) );
AOI22X1TS U7023 ( .A0(n4843), .A1(n4842), .B0(n4841), .B1(n4840), .Y(n4844)
);
OA21XLTS U7024 ( .A0(n5370), .A1(n6725), .B0(n4844), .Y(n4848) );
NAND2X1TS U7025 ( .A(n5374), .B(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .Y(n4846) );
NAND4X1TS U7026 ( .A(n4849), .B(n4848), .C(n4847), .D(n4846), .Y(n4931) );
AOI22X1TS U7027 ( .A0(n4851), .A1(n4931), .B0(result_add_subt[4]), .B1(n4850), .Y(n4852) );
INVX2TS U7028 ( .A(n4854), .Y(n5428) );
INVX2TS U7029 ( .A(n5429), .Y(n4855) );
AOI22X1TS U7030 ( .A0(n4856), .A1(n4855), .B0(result_add_subt[36]), .B1(
n4691), .Y(n4857) );
AOI22X1TS U7031 ( .A0(n4861), .A1(n4860), .B0(result_add_subt[15]), .B1(
n4859), .Y(n4862) );
BUFX4TS U7032 ( .A(n4872), .Y(n4908) );
AOI22X1TS U7033 ( .A0(n4908), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[14]), .B1(n4907), .Y(n4864) );
BUFX4TS U7034 ( .A(n4872), .Y(n4916) );
AOI22X1TS U7035 ( .A0(n4916), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[39]), .B1(n4915), .Y(n4865) );
AOI22X1TS U7036 ( .A0(n4916), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[12]), .B1(n4896), .Y(n4866) );
AOI22X1TS U7037 ( .A0(n4916), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[13]), .B1(n4881), .Y(n4867) );
AOI22X1TS U7038 ( .A0(n4916), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[31]), .B1(n4896), .Y(n4868) );
AOI22X1TS U7039 ( .A0(n4916), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[15]), .B1(n4896), .Y(n4869) );
BUFX4TS U7040 ( .A(n4872), .Y(n4919) );
AOI22X1TS U7041 ( .A0(n4919), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[62]), .B1(n4950), .Y(n4870) );
AOI22X1TS U7042 ( .A0(n4919), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[3]), .B1(n4915), .Y(n4871) );
AOI22X1TS U7043 ( .A0(n4953), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[23]), .B1(n4912), .Y(n4873) );
AOI22X1TS U7044 ( .A0(n4919), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[60]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[60]), .B1(n4950), .Y(n4874) );
AOI22X1TS U7045 ( .A0(n4919), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[58]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[58]), .B1(n4950), .Y(n4875) );
AOI22X1TS U7046 ( .A0(n4919), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[59]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[59]), .B1(n4950), .Y(n4876) );
AOI22X1TS U7047 ( .A0(n4908), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[7]), .B1(n4902), .Y(n4878) );
AOI22X1TS U7048 ( .A0(n4908), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[5]), .B1(n4902), .Y(n4879) );
AOI22X1TS U7049 ( .A0(n4919), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[61]), .B1(n4918), .Y(n4880) );
AOI22X1TS U7050 ( .A0(n4953), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[4]), .B1(n4881), .Y(n4882) );
AOI22X1TS U7051 ( .A0(n4916), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[37]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[37]), .B1(n4896), .Y(n4883) );
AOI22X1TS U7052 ( .A0(n4908), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[6]), .B1(n4902), .Y(n4884) );
AOI22X1TS U7053 ( .A0(n4953), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[22]), .B1(n4912), .Y(n4885) );
AOI22X1TS U7054 ( .A0(n4908), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[19]), .B1(n4907), .Y(n4886) );
AOI22X1TS U7055 ( .A0(n4908), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[10]), .B1(n4907), .Y(n4887) );
AOI22X1TS U7056 ( .A0(n4953), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[27]), .B1(n4912), .Y(n4888) );
AOI22X1TS U7057 ( .A0(n4919), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[56]), .B1(n4918), .Y(n4889) );
AOI22X1TS U7058 ( .A0(n4536), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[25]), .B1(n4893), .Y(n4890) );
AOI22X1TS U7059 ( .A0(n4916), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[45]), .B1(n4915), .Y(n4891) );
AOI22X1TS U7060 ( .A0(n4908), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[18]), .B1(n4907), .Y(n4892) );
AOI22X1TS U7061 ( .A0(n4872), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[24]), .B1(n4893), .Y(n4894) );
AOI22X1TS U7062 ( .A0(n4916), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[17]), .B1(n4896), .Y(n4897) );
AOI22X1TS U7063 ( .A0(n4953), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[11]), .B1(n4912), .Y(n4898) );
AOI22X1TS U7064 ( .A0(n4536), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[26]), .B1(n4912), .Y(n4899) );
AOI22X1TS U7065 ( .A0(n4908), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[20]), .B1(n4902), .Y(n4900) );
AOI22X1TS U7066 ( .A0(n4908), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[16]), .B1(n4907), .Y(n4901) );
AOI22X1TS U7067 ( .A0(n4536), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]),
.B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[8]), .B1(n4902), .Y(n4903) );
AOI22X1TS U7068 ( .A0(n4919), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[50]), .B1(n4918), .Y(n4904) );
AOI22X1TS U7069 ( .A0(n4919), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[57]), .B0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[57]), .B1(n4950), .Y(n4905) );
AOI22X1TS U7070 ( .A0(n4908), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[29]), .B1(n4907), .Y(n4909) );
AOI22X1TS U7071 ( .A0(n4916), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[41]), .B1(n4915), .Y(n4911) );
AOI22X1TS U7072 ( .A0(n4872), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[21]), .B1(n4912), .Y(n4913) );
AOI22X1TS U7073 ( .A0(n4916), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[35]), .B1(n4915), .Y(n4917) );
AOI22X1TS U7074 ( .A0(n4919), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .B0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[33]), .B1(n4918), .Y(n4920) );
INVX2TS U7075 ( .A(n4922), .Y(n5442) );
INVX2TS U7076 ( .A(n5444), .Y(n4923) );
AOI22X1TS U7077 ( .A0(n4939), .A1(n4923), .B0(result_add_subt[47]), .B1(
n4928), .Y(n4924) );
INVX2TS U7078 ( .A(n5380), .Y(n4925) );
AOI22X1TS U7079 ( .A0(n4939), .A1(n4925), .B0(result_add_subt[45]), .B1(
n4928), .Y(n4926) );
INVX2TS U7080 ( .A(n5382), .Y(n4929) );
AOI22X1TS U7081 ( .A0(n4939), .A1(n4929), .B0(result_add_subt[50]), .B1(
n4928), .Y(n4930) );
INVX2TS U7082 ( .A(n4931), .Y(n5436) );
INVX2TS U7083 ( .A(n5437), .Y(n4932) );
AOI22X1TS U7084 ( .A0(n4939), .A1(n4932), .B0(result_add_subt[46]), .B1(
n5447), .Y(n4933) );
INVX2TS U7085 ( .A(n4934), .Y(n5438) );
INVX2TS U7086 ( .A(n5439), .Y(n4935) );
AOI22X1TS U7087 ( .A0(n4939), .A1(n4935), .B0(result_add_subt[48]), .B1(
n5447), .Y(n4936) );
INVX2TS U7088 ( .A(n4937), .Y(n5431) );
INVX2TS U7089 ( .A(n5432), .Y(n4938) );
AOI22X1TS U7090 ( .A0(n4939), .A1(n4938), .B0(result_add_subt[49]), .B1(
n5447), .Y(n4940) );
INVX2TS U7091 ( .A(n4942), .Y(n4943) );
AND2X4TS U7092 ( .A(n4945), .B(n4944), .Y(n4958) );
INVX4TS U7093 ( .A(n4958), .Y(n5320) );
INVX2TS U7094 ( .A(n5127), .Y(n5183) );
INVX2TS U7095 ( .A(n5057), .Y(n5184) );
NAND2X1TS U7096 ( .A(n4184), .B(n6758), .Y(n4946) );
NAND2X1TS U7097 ( .A(n4947), .B(n4946), .Y(n5277) );
AOI21X1TS U7098 ( .A0(n5323), .A1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[50]), .B0(n5147), .Y(n4948)
);
INVX2TS U7099 ( .A(n4949), .Y(n2257) );
AOI222X1TS U7100 ( .A0(n4954), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[53]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[53]), .B1(n4950), .C0(n4953),
.C1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .Y(n4951) );
INVX2TS U7101 ( .A(n4951), .Y(n2190) );
AOI222X1TS U7102 ( .A0(n4954), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[54]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[54]), .B1(n6572), .C0(n4953),
.C1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .Y(n4952) );
INVX2TS U7103 ( .A(n4952), .Y(n2189) );
INVX2TS U7104 ( .A(n4955), .Y(n2191) );
AOI22X1TS U7105 ( .A0(n4184), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[26]), .B0(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[26]), .B1(n6559), .Y(
n4956) );
CLKINVX1TS U7106 ( .A(n4957), .Y(n5020) );
BUFX3TS U7107 ( .A(n5336), .Y(n5295) );
INVX2TS U7108 ( .A(n5127), .Y(n5098) );
CLKBUFX2TS U7109 ( .A(n5057), .Y(n5053) );
NAND2X1TS U7110 ( .A(n5137), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[28]), .Y(n4960) );
NAND2X1TS U7111 ( .A(n6932), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[24]), .Y(n4959) );
NAND3X1TS U7112 ( .A(n4961), .B(n4960), .C(n4959), .Y(n5217) );
NAND2X1TS U7113 ( .A(n5099), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]), .Y(n4963) );
NAND2X1TS U7114 ( .A(n6932), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[23]), .Y(n4962) );
NAND3X1TS U7115 ( .A(n4964), .B(n4963), .C(n4962), .Y(n5215) );
INVX2TS U7116 ( .A(n5215), .Y(n5340) );
OAI22X1TS U7117 ( .A0(n5301), .A1(n5340), .B0(n6668), .B1(n3181), .Y(n4965)
);
AOI21X1TS U7118 ( .A0(n5295), .A1(n5217), .B0(n4965), .Y(n4966) );
NAND2X1TS U7119 ( .A(n5208), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[36]), .Y(n4969) );
NAND2X1TS U7120 ( .A(n5202), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n4968) );
NAND2X1TS U7121 ( .A(n5185), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n4967) );
NAND2X1TS U7122 ( .A(n5208), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[34]), .Y(n4972) );
NAND2X1TS U7123 ( .A(n5127), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n4971) );
INVX2TS U7124 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n5203) );
NAND2X1TS U7125 ( .A(n5203), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n4970) );
BUFX3TS U7126 ( .A(n5164), .Y(n5181) );
NAND2X1TS U7127 ( .A(n5099), .B(n6756), .Y(n4974) );
NAND3X1TS U7128 ( .A(n4975), .B(n4974), .C(n4973), .Y(n5169) );
OA22X1TS U7129 ( .A0(n5298), .A1(n5181), .B0(n5169), .B1(n5278), .Y(n4980)
);
BUFX4TS U7130 ( .A(n5336), .Y(n5347) );
NAND2X1TS U7131 ( .A(n5137), .B(n6826), .Y(n4977) );
INVX2TS U7132 ( .A(n3181), .Y(n5262) );
AOI22X1TS U7133 ( .A0(n5347), .A1(n5292), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[18]), .B1(n5256), .Y(n4979)
);
NAND2X1TS U7134 ( .A(n5184), .B(n6843), .Y(n4982) );
CLKBUFX2TS U7135 ( .A(n5133), .Y(n5209) );
NAND3X1TS U7136 ( .A(n4983), .B(n4982), .C(n4981), .Y(n5221) );
NAND2X1TS U7137 ( .A(n5047), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[50]), .Y(n4986) );
NAND2X1TS U7138 ( .A(n5147), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n4985) );
NAND2X1TS U7139 ( .A(n5185), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n4984) );
NAND2X1TS U7140 ( .A(n5047), .B(n3253), .Y(n4989) );
NAND2X1TS U7141 ( .A(n5147), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n4988) );
NAND2X1TS U7142 ( .A(n5185), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n4987) );
OA22X1TS U7143 ( .A0(n5301), .A1(n5287), .B0(n5288), .B1(n5181), .Y(n4994)
);
NAND2X1TS U7144 ( .A(n4184), .B(n6664), .Y(n4991) );
BUFX3TS U7145 ( .A(n5133), .Y(n6011) );
AOI22X1TS U7146 ( .A0(n5347), .A1(n5286), .B0(n5262), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[4]), .Y(n4993) );
NAND2X1TS U7147 ( .A(n4184), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[40]), .Y(n4997) );
NAND2X1TS U7148 ( .A(n5202), .B(n3274), .Y(n4996) );
NAND2X1TS U7149 ( .A(n5185), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n4995) );
BUFX4TS U7150 ( .A(n5350), .Y(n5119) );
NAND2X1TS U7151 ( .A(n5184), .B(n6827), .Y(n4999) );
AOI22X1TS U7152 ( .A0(n5303), .A1(n5293), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[14]), .B1(n5305), .Y(n5008)
);
NAND2X1TS U7153 ( .A(n4184), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[38]), .Y(n5003) );
NAND2X1TS U7154 ( .A(n5202), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n5002) );
NAND2X1TS U7155 ( .A(n5203), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n5001) );
OR2X1TS U7156 ( .A(n5058), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[15]), .Y(n5006) );
NAND2X1TS U7157 ( .A(n5184), .B(n6701), .Y(n5005) );
OA22X1TS U7158 ( .A0(n5181), .A1(n5166), .B0(n5285), .B1(n3220), .Y(n5007)
);
INVX4TS U7159 ( .A(n5291), .Y(n5345) );
NAND2X1TS U7160 ( .A(n5047), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n5010) );
NAND2X1TS U7161 ( .A(n5185), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[51]), .Y(n5009) );
AOI22X1TS U7162 ( .A0(n5345), .A1(n5322), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[49]), .B1(n5305), .Y(n5012)
);
NAND2X1TS U7163 ( .A(n5208), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30]), .Y(n5016) );
NAND2X1TS U7164 ( .A(n6932), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n5015) );
INVX2TS U7165 ( .A(n3181), .Y(n5314) );
NAND2X1TS U7166 ( .A(n5336), .B(n5215), .Y(n5018) );
OA22X1TS U7167 ( .A0(n5166), .A1(n5278), .B0(n5285), .B1(n5181), .Y(n5025)
);
OR2X1TS U7168 ( .A(n5183), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .Y(n5023) );
NAND2X1TS U7169 ( .A(n5184), .B(n6655), .Y(n5022) );
NAND3X1TS U7170 ( .A(n5023), .B(n5022), .C(n5021), .Y(n5069) );
INVX2TS U7171 ( .A(n5069), .Y(n5268) );
AOI22X1TS U7172 ( .A0(n5345), .A1(n5268), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[13]), .B1(n5323), .Y(n5024)
);
BUFX3TS U7173 ( .A(n5350), .Y(n5339) );
OAI22X1TS U7174 ( .A0(n5053), .A1(n6640), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .B1(n6822), .Y(
n5027) );
NOR2X1TS U7175 ( .A(n5058), .B(n6665), .Y(n5026) );
NOR2X2TS U7176 ( .A(n5027), .B(n5026), .Y(n5270) );
OA22X1TS U7177 ( .A0(n5339), .A1(n5267), .B0(n5270), .B1(n3220), .Y(n5032)
);
INVX4TS U7178 ( .A(n5291), .Y(n5272) );
NAND2X1TS U7179 ( .A(n5184), .B(n6824), .Y(n5029) );
NAND3X1TS U7180 ( .A(n5030), .B(n5029), .C(n5028), .Y(n5068) );
INVX2TS U7181 ( .A(n5068), .Y(n5192) );
AOI22X1TS U7182 ( .A0(n5272), .A1(n5192), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[11]), .B1(n5341), .Y(n5031)
);
NAND2X1TS U7183 ( .A(n5137), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n5034) );
NAND2X1TS U7184 ( .A(n6581), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[34]), .Y(n5033) );
INVX2TS U7185 ( .A(n5111), .Y(n5254) );
NAND2X1TS U7186 ( .A(n5099), .B(n6699), .Y(n5037) );
NAND3X1TS U7187 ( .A(n5038), .B(n5037), .C(n5036), .Y(n5249) );
NAND2X1TS U7188 ( .A(n5099), .B(n6819), .Y(n5040) );
OR2X1TS U7189 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[33]), .Y(n5039) );
NAND3X1TS U7190 ( .A(n5041), .B(n5040), .C(n5039), .Y(n5115) );
OA22X1TS U7191 ( .A0(n5339), .A1(n5249), .B0(n5115), .B1(n3220), .Y(n5046)
);
NAND2X1TS U7192 ( .A(n5137), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n5043) );
NAND2X1TS U7193 ( .A(n6932), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[32]), .Y(n5042) );
AOI22X1TS U7194 ( .A0(n5263), .A1(n5110), .B0(n5256), .B1(n3239), .Y(n5045)
);
NAND2X1TS U7195 ( .A(n5047), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[46]), .Y(n5050) );
NAND2X1TS U7196 ( .A(n5202), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n5049) );
NAND2X1TS U7197 ( .A(n5185), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n5048) );
OA22X1TS U7198 ( .A0(n5220), .A1(n5339), .B0(n5221), .B1(n5181), .Y(n5052)
);
AOI22X1TS U7199 ( .A0(n5345), .A1(n5286), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[5]), .B1(n5305), .Y(n5051)
);
OAI22X1TS U7200 ( .A0(n5053), .A1(n6641), .B0(n6010), .B1(n6823), .Y(n5055)
);
OA22X1TS U7201 ( .A0(n5339), .A1(n5270), .B0(n5224), .B1(n3221), .Y(n5062)
);
OAI22X1TS U7202 ( .A0(n5057), .A1(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[45]), .B0(n5056), .B1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n5060) );
NOR2X2TS U7203 ( .A(n5060), .B(n5059), .Y(n5240) );
AOI22X1TS U7204 ( .A0(n5272), .A1(n5240), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[9]), .B1(n5341), .Y(n5061)
);
NAND2X1TS U7205 ( .A(n5336), .B(n5322), .Y(n5067) );
NAND2X1TS U7206 ( .A(n4184), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n5064) );
NAND2X1TS U7207 ( .A(n5185), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[50]), .Y(n5063) );
AOI22X1TS U7208 ( .A0(n5345), .A1(n5324), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[48]), .B1(n5341), .Y(n5066)
);
OA22X1TS U7209 ( .A0(n5339), .A1(n5069), .B0(n5068), .B1(n3221), .Y(n5071)
);
INVX2TS U7210 ( .A(n5224), .Y(n5191) );
AOI22X1TS U7211 ( .A0(n5345), .A1(n5191), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[10]), .B1(n5341), .Y(n5070)
);
NAND2X1TS U7212 ( .A(n5099), .B(n6638), .Y(n5073) );
OR2X1TS U7213 ( .A(n6010), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n5072) );
NAND2X1TS U7214 ( .A(n5099), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[32]), .Y(n5077) );
NAND2X1TS U7215 ( .A(n5202), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n5076) );
NAND2X1TS U7216 ( .A(n5203), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n5075) );
OA22X1TS U7217 ( .A0(n5181), .A1(n5266), .B0(n5169), .B1(n3221), .Y(n5079)
);
INVX2TS U7218 ( .A(n5298), .Y(n5260) );
AOI22X1TS U7219 ( .A0(n5263), .A1(n5260), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[20]), .B1(n5314), .Y(n5078)
);
NAND2X1TS U7220 ( .A(n5137), .B(n6821), .Y(n5081) );
OR2X1TS U7221 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[31]), .Y(n5080) );
INVX4TS U7222 ( .A(n5119), .Y(n5317) );
NAND2X1TS U7223 ( .A(n5137), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n5084) );
NAND2X1TS U7224 ( .A(n6932), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[30]), .Y(n5083) );
AOI22X1TS U7225 ( .A0(n5317), .A1(n5110), .B0(n5295), .B1(n5106), .Y(n5090)
);
NAND2X1TS U7226 ( .A(n5099), .B(n6761), .Y(n5087) );
OR2X1TS U7227 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[29]), .Y(n5086) );
INVX2TS U7228 ( .A(n5105), .Y(n5161) );
AOI22X1TS U7229 ( .A0(n5263), .A1(n5161), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[30]), .B1(n5314), .Y(n5089)
);
INVX2TS U7230 ( .A(n5110), .Y(n5094) );
INVX2TS U7231 ( .A(n5115), .Y(n5250) );
BUFX4TS U7232 ( .A(n5336), .Y(n5281) );
INVX2TS U7233 ( .A(n5091), .Y(n5112) );
AOI22X1TS U7234 ( .A0(n5317), .A1(n5250), .B0(n5281), .B1(n5112), .Y(n5093)
);
NAND2X1TS U7235 ( .A(n5208), .B(n6675), .Y(n5096) );
OR2X1TS U7236 ( .A(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[1]), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[28]), .Y(n5095) );
INVX2TS U7237 ( .A(n5165), .Y(n5311) );
AOI22X1TS U7238 ( .A0(n5317), .A1(n5106), .B0(n5281), .B1(n5311), .Y(n5104)
);
NAND2X1TS U7239 ( .A(n5208), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n5101) );
NAND2X1TS U7240 ( .A(n6932), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[27]), .Y(n5100) );
AOI22X1TS U7241 ( .A0(n5263), .A1(n5316), .B0(n5262), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[29]), .Y(n5103) );
INVX2TS U7242 ( .A(n5106), .Y(n5109) );
AOI22X1TS U7243 ( .A0(n5317), .A1(n5112), .B0(n5281), .B1(n5161), .Y(n5108)
);
AOI22X1TS U7244 ( .A0(n5263), .A1(n5311), .B0(n5262), .B1(n3240), .Y(n5107)
);
AOI22X1TS U7245 ( .A0(n5317), .A1(n5111), .B0(n5281), .B1(n5110), .Y(n5114)
);
AOI22X1TS U7246 ( .A0(n5263), .A1(n5112), .B0(n5256), .B1(n3241), .Y(n5113)
);
NAND2X1TS U7247 ( .A(n5099), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n5118) );
NAND2X1TS U7248 ( .A(n5127), .B(n3253), .Y(n5117) );
NAND2X1TS U7249 ( .A(n6581), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[46]), .Y(n5116) );
INVX4TS U7250 ( .A(n5119), .Y(n5282) );
OR2X1TS U7251 ( .A(n5207), .B(n3256), .Y(n5122) );
NAND2X1TS U7252 ( .A(n5137), .B(n6688), .Y(n5121) );
INVX2TS U7253 ( .A(n5229), .Y(n5126) );
NAND2X1TS U7254 ( .A(n5099), .B(n6724), .Y(n5124) );
NAND3X1TS U7255 ( .A(n5125), .B(n5124), .C(n5123), .Y(n5146) );
INVX2TS U7256 ( .A(n5146), .Y(n5151) );
AOI22X1TS U7257 ( .A0(n5282), .A1(n5126), .B0(n5281), .B1(n5151), .Y(n5132)
);
NAND2X1TS U7258 ( .A(n5208), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n5130) );
NAND2X1TS U7259 ( .A(n5127), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[46]), .Y(n5129) );
NAND2X1TS U7260 ( .A(n5203), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[44]), .Y(n5128) );
INVX2TS U7261 ( .A(n5143), .Y(n5154) );
AOI22X1TS U7262 ( .A0(n5263), .A1(n5154), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[42]), .B1(n5256), .Y(n5131)
);
NAND2X1TS U7263 ( .A(n5099), .B(n6676), .Y(n5135) );
NAND3X1TS U7264 ( .A(n5136), .B(n5135), .C(n5134), .Y(n5160) );
OA22X1TS U7265 ( .A0(n5339), .A1(n5146), .B0(n5160), .B1(n3220), .Y(n5142)
);
NAND2X1TS U7266 ( .A(n5137), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n5139) );
NAND2X1TS U7267 ( .A(n6581), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[42]), .Y(n5138) );
AOI22X1TS U7268 ( .A0(n5272), .A1(n5230), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[40]), .B1(n5323), .Y(n5141)
);
OA22X1TS U7269 ( .A0(n5339), .A1(n5182), .B0(n5143), .B1(n3220), .Y(n5145)
);
INVX2TS U7270 ( .A(n5160), .Y(n5198) );
AOI22X1TS U7271 ( .A0(n5272), .A1(n5198), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[41]), .B1(n5314), .Y(n5144)
);
NAND2X1TS U7272 ( .A(n4184), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n5150) );
NAND2X1TS U7273 ( .A(n5147), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[50]), .Y(n5149) );
NAND2X1TS U7274 ( .A(n5185), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[48]), .Y(n5148) );
OA22X1TS U7275 ( .A0(n5339), .A1(n5226), .B0(n5182), .B1(n3221), .Y(n5153)
);
AOI22X1TS U7276 ( .A0(n5272), .A1(n5151), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[43]), .B1(n5314), .Y(n5152)
);
AOI22X1TS U7277 ( .A0(n5282), .A1(n5154), .B0(n5347), .B1(n5230), .Y(n5159)
);
NAND2X1TS U7278 ( .A(n5208), .B(n6820), .Y(n5156) );
INVX2TS U7279 ( .A(n5239), .Y(n5231) );
AOI22X1TS U7280 ( .A0(n5272), .A1(n5231), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[39]), .B1(n5256), .Y(n5158)
);
INVX2TS U7281 ( .A(n5291), .Y(n5334) );
AOI22X1TS U7282 ( .A0(n5282), .A1(n5161), .B0(n5334), .B1(n5315), .Y(n5163)
);
AOI22X1TS U7283 ( .A0(n5347), .A1(n5316), .B0(n5262), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[28]), .Y(n5162) );
AOI22X1TS U7284 ( .A0(n5282), .A1(n5292), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[16]), .B1(n3942), .Y(n5168)
);
INVX2TS U7285 ( .A(n5166), .Y(n5280) );
AOI22X1TS U7286 ( .A0(n5295), .A1(n5293), .B0(n5345), .B1(n5280), .Y(n5167)
);
AOI22X1TS U7287 ( .A0(n5282), .A1(n5331), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[21]), .B1(n5256), .Y(n5171)
);
INVX2TS U7288 ( .A(n5266), .Y(n5333) );
INVX2TS U7289 ( .A(n5169), .Y(n5261) );
AOI22X1TS U7290 ( .A0(n5295), .A1(n5333), .B0(n5334), .B1(n5261), .Y(n5170)
);
NAND2X1TS U7291 ( .A(n5208), .B(n6689), .Y(n5174) );
AOI22X1TS U7292 ( .A0(n5282), .A1(n5342), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[33]), .B1(n5323), .Y(n5180)
);
NAND2X1TS U7293 ( .A(n5137), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n5178) );
NAND2X1TS U7294 ( .A(n5202), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[38]), .Y(n5177) );
NAND2X1TS U7295 ( .A(n6581), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[36]), .Y(n5176) );
OA22X1TS U7296 ( .A0(n5181), .A1(n5251), .B0(n5249), .B1(n3221), .Y(n5179)
);
OA22X1TS U7297 ( .A0(n5301), .A1(n5182), .B0(n5226), .B1(n5181), .Y(n5190)
);
NAND2X1TS U7298 ( .A(n5047), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n5187) );
NAND2X1TS U7299 ( .A(n5185), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[49]), .Y(n5186) );
AOI22X1TS U7300 ( .A0(n5282), .A1(n5327), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[44]), .B1(n5305), .Y(n5189)
);
AOI22X1TS U7301 ( .A0(n5303), .A1(n5192), .B0(n5216), .B1(n5191), .Y(n5194)
);
AOI22X1TS U7302 ( .A0(n5336), .A1(n5240), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[8]), .B1(n5341), .Y(n5193)
);
NAND2X1TS U7303 ( .A(n5208), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .Y(n5196) );
NAND2X1TS U7304 ( .A(n5203), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[40]), .Y(n5195) );
INVX2TS U7305 ( .A(n5235), .Y(n5201) );
AOI22X1TS U7306 ( .A0(n5295), .A1(n5231), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[38]), .B1(n5314), .Y(n5199)
);
NAND2X1TS U7307 ( .A(n5208), .B(n3274), .Y(n5206) );
NAND2X1TS U7308 ( .A(n5202), .B(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[40]), .Y(n5205) );
NAND2X1TS U7309 ( .A(n6581), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SHT1_SW[38]), .Y(n5204) );
NAND2X1TS U7310 ( .A(n5137), .B(n6762), .Y(n5211) );
INVX2TS U7311 ( .A(n5259), .Y(n5236) );
AOI22X1TS U7312 ( .A0(n5282), .A1(n5235), .B0(n5216), .B1(n5236), .Y(n5214)
);
AOI22X1TS U7313 ( .A0(n5272), .A1(n5342), .B0(n3238), .B1(n5262), .Y(n5213)
);
AOI22X1TS U7314 ( .A0(n5317), .A1(n5217), .B0(n5216), .B1(n5215), .Y(n5219)
);
AOI22X1TS U7315 ( .A0(n5336), .A1(n5331), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[23]), .B1(n5262), .Y(n5218)
);
INVX4TS U7316 ( .A(n5225), .Y(n5325) );
INVX2TS U7317 ( .A(n5220), .Y(n5242) );
AOI22X1TS U7318 ( .A0(n5325), .A1(n5240), .B0(n5281), .B1(n5242), .Y(n5223)
);
INVX2TS U7319 ( .A(n5221), .Y(n5243) );
AOI22X1TS U7320 ( .A0(n5272), .A1(n5243), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[7]), .B1(n5341), .Y(n5222)
);
INVX4TS U7321 ( .A(n5225), .Y(n5343) );
INVX2TS U7322 ( .A(n5226), .Y(n5326) );
AOI22X1TS U7323 ( .A0(n5343), .A1(n5327), .B0(n5281), .B1(n5326), .Y(n5228)
);
AOI22X1TS U7324 ( .A0(n5282), .A1(n5324), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[45]), .B1(n5341), .Y(n5227)
);
INVX2TS U7325 ( .A(n5230), .Y(n5234) );
AOI22X1TS U7326 ( .A0(n5343), .A1(n5231), .B0(n5347), .B1(n5235), .Y(n5233)
);
AOI22X1TS U7327 ( .A0(n5272), .A1(n5236), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[37]), .B1(n5262), .Y(n5232)
);
INVX2TS U7328 ( .A(n5351), .Y(n5255) );
AOI22X1TS U7329 ( .A0(n5325), .A1(n5235), .B0(n5345), .B1(n5255), .Y(n5238)
);
AOI22X1TS U7330 ( .A0(n5347), .A1(n5236), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[36]), .B1(n5305), .Y(n5237)
);
INVX2TS U7331 ( .A(n5240), .Y(n5246) );
INVX2TS U7332 ( .A(n5288), .Y(n5241) );
AOI22X1TS U7333 ( .A0(n5325), .A1(n5242), .B0(n5345), .B1(n5241), .Y(n5245)
);
AOI22X1TS U7334 ( .A0(n5347), .A1(n5243), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[6]), .B1(n5341), .Y(n5244)
);
INVX2TS U7335 ( .A(n5287), .Y(n5302) );
AOI22X1TS U7336 ( .A0(n5325), .A1(n5302), .B0(n5334), .B1(n5299), .Y(n5248)
);
AOI22X1TS U7337 ( .A0(n5303), .A1(n5286), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[2]), .B1(n5341), .Y(n5247)
);
INVX2TS U7338 ( .A(n5249), .Y(n5344) );
AOI22X1TS U7339 ( .A0(n5325), .A1(n5344), .B0(n5334), .B1(n5250), .Y(n5253)
);
INVX2TS U7340 ( .A(n5251), .Y(n5346) );
AOI22X1TS U7341 ( .A0(n5317), .A1(n5346), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[32]), .B1(n5314), .Y(n5252)
);
AOI22X1TS U7342 ( .A0(n5343), .A1(n5255), .B0(n5334), .B1(n5346), .Y(n5258)
);
AOI22X1TS U7343 ( .A0(n5336), .A1(n5342), .B0(n5262), .B1(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[35]), .Y(n5257) );
AOI22X1TS U7344 ( .A0(n5343), .A1(n5261), .B0(n5281), .B1(n5260), .Y(n5265)
);
AOI22X1TS U7345 ( .A0(n5263), .A1(n5292), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[19]), .B1(n5256), .Y(n5264)
);
INVX2TS U7346 ( .A(n5267), .Y(n5269) );
AOI22X1TS U7347 ( .A0(n5325), .A1(n5269), .B0(n5281), .B1(n5268), .Y(n5274)
);
INVX2TS U7348 ( .A(n5270), .Y(n5271) );
AOI22X1TS U7349 ( .A0(n5272), .A1(n5271), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[12]), .B1(n5305), .Y(n5273)
);
AOI22X1TS U7350 ( .A0(n5325), .A1(n5322), .B0(n5345), .B1(n5327), .Y(n5276)
);
AOI22X1TS U7351 ( .A0(n5347), .A1(n5324), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[47]), .B1(n5341), .Y(n5275)
);
INVX2TS U7352 ( .A(n5279), .Y(n5294) );
AOI22X1TS U7353 ( .A0(n5282), .A1(n5294), .B0(n5281), .B1(n5280), .Y(n5284)
);
AOI22X1TS U7354 ( .A0(n5325), .A1(n5293), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[15]), .B1(n5323), .Y(n5283)
);
AOI22X1TS U7355 ( .A0(n5325), .A1(n5286), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[3]), .B1(n5323), .Y(n5290)
);
OA22X1TS U7356 ( .A0(n5339), .A1(n5288), .B0(n5287), .B1(n3220), .Y(n5289)
);
AOI22X1TS U7357 ( .A0(n5343), .A1(n5292), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[17]), .B1(n3942), .Y(n5297)
);
AOI22X1TS U7358 ( .A0(n5295), .A1(n5294), .B0(n5334), .B1(n5293), .Y(n5296)
);
INVX2TS U7359 ( .A(n5299), .Y(n5310) );
INVX2TS U7360 ( .A(n5304), .Y(n5306) );
AOI22X1TS U7361 ( .A0(n5343), .A1(n5306), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[1]), .B1(n5305), .Y(n5307)
);
AOI22X1TS U7362 ( .A0(n5343), .A1(n5316), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[27]), .B1(n5262), .Y(n5313)
);
NAND2X1TS U7363 ( .A(n5317), .B(n5311), .Y(n5312) );
AOI22X1TS U7364 ( .A0(n5343), .A1(n5315), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[26]), .B1(n5256), .Y(n5319)
);
NAND2X1TS U7365 ( .A(n5317), .B(n5316), .Y(n5318) );
INVX2TS U7366 ( .A(n5322), .Y(n5330) );
AOI22X1TS U7367 ( .A0(n5325), .A1(n5324), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[46]), .B1(n5323), .Y(n5329)
);
AOI22X1TS U7368 ( .A0(n5347), .A1(n5327), .B0(n5334), .B1(n5326), .Y(n5328)
);
INVX2TS U7369 ( .A(n5332), .Y(n5335) );
AOI22X1TS U7370 ( .A0(n5336), .A1(n5335), .B0(n5334), .B1(n5333), .Y(n5337)
);
AOI22X1TS U7371 ( .A0(n5343), .A1(n5342), .B0(
inst_FPU_PIPELINED_FPADDSUB_Data_array_SWR[34]), .B1(n5323), .Y(n5349)
);
AOI22X1TS U7372 ( .A0(n5347), .A1(n5346), .B0(n5345), .B1(n5344), .Y(n5348)
);
NOR3XLTS U7373 ( .A(n6670), .B(n6673), .C(n5352), .Y(n5355) );
OAI21XLTS U7374 ( .A0(n5355), .A1(n5354), .B0(n5353), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
NOR3X1TS U7375 ( .A(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .C(
n6671), .Y(n6058) );
AOI31XLTS U7376 ( .A0(n5356), .A1(n6057), .A2(n6766), .B0(n6058), .Y(n5357)
);
OAI21XLTS U7377 ( .A0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
n5358), .B0(n5357), .Y(n3172) );
AOI21X1TS U7378 ( .A0(n5361), .A1(n5987), .B0(n5359), .Y(n5377) );
BUFX3TS U7379 ( .A(n6476), .Y(n6475) );
INVX2TS U7380 ( .A(n5394), .Y(n5397) );
NAND2X1TS U7381 ( .A(n5363), .B(n5362), .Y(n5369) );
OAI222X1TS U7382 ( .A0(n5430), .A1(n5382), .B0(n3245), .B1(n5381), .C0(n6812), .C1(n5452), .Y(n1736) );
NOR3X2TS U7383 ( .A(n5375), .B(n6053), .C(ready_add_subt), .Y(n6063) );
OAI21XLTS U7384 ( .A0(n6063), .A1(n6642), .B0(cont_var_out[1]), .Y(n5376) );
INVX2TS U7385 ( .A(n5394), .Y(n5425) );
INVX2TS U7386 ( .A(n5385), .Y(n5441) );
OAI222X1TS U7387 ( .A0(n5443), .A1(n5387), .B0(n5397), .B1(n5386), .C0(n6808), .C1(n5418), .Y(n1729) );
OAI222X1TS U7388 ( .A0(n5427), .A1(n5380), .B0(n5425), .B1(n5379), .C0(n6809), .C1(n5418), .Y(n1731) );
OAI222X1TS U7389 ( .A0(n5443), .A1(n5384), .B0(n5440), .B1(n5383), .C0(n6784), .C1(n3211), .Y(n1730) );
INVX2TS U7390 ( .A(n6475), .Y(n5418) );
INVX2TS U7391 ( .A(n5394), .Y(n5435) );
OAI222X1TS U7392 ( .A0(n5423), .A1(n5380), .B0(n5427), .B1(n5379), .C0(n6789), .C1(n6578), .Y(n1691) );
INVX2TS U7393 ( .A(n6475), .Y(n5433) );
OAI222X1TS U7394 ( .A0(n5427), .A1(n5391), .B0(n3245), .B1(n5390), .C0(n6807), .C1(n5422), .Y(n1727) );
OAI222X1TS U7395 ( .A0(n5434), .A1(n5389), .B0(n5425), .B1(n5388), .C0(n6783), .C1(n5418), .Y(n1728) );
OAI222X1TS U7396 ( .A0(n5434), .A1(n5393), .B0(n5435), .B1(n5392), .C0(n6782), .C1(n6478), .Y(n1726) );
INVX2TS U7397 ( .A(n5394), .Y(n5423) );
OAI222X1TS U7398 ( .A0(n5440), .A1(n5396), .B0(n5443), .B1(n5395), .C0(n6771), .C1(n5448), .Y(n1704) );
OAI222X1TS U7399 ( .A0(n5423), .A1(n5399), .B0(n5427), .B1(n5398), .C0(n6794), .C1(n5448), .Y(n1699) );
OAI222X1TS U7400 ( .A0(n5435), .A1(n5405), .B0(n5427), .B1(n5404), .C0(n6774), .C1(n6478), .Y(n1710) );
OAI222X1TS U7401 ( .A0(n5423), .A1(n5407), .B0(n5434), .B1(n5406), .C0(n6773), .C1(n5448), .Y(n1708) );
OAI222X1TS U7402 ( .A0(n5397), .A1(n5411), .B0(n5443), .B1(n5410), .C0(n6772), .C1(n3210), .Y(n1706) );
OAI222X1TS U7403 ( .A0(n5425), .A1(n5413), .B0(n5427), .B1(n5412), .C0(n6796), .C1(n6578), .Y(n1703) );
OAI222X1TS U7404 ( .A0(n5440), .A1(n5415), .B0(n5434), .B1(n5414), .C0(n6799), .C1(n5448), .Y(n1709) );
OAI222X1TS U7405 ( .A0(n5423), .A1(n5421), .B0(n5443), .B1(n5419), .C0(n6797), .C1(n3210), .Y(n1705) );
OAI222X1TS U7406 ( .A0(n5430), .A1(n5432), .B0(n5423), .B1(n5431), .C0(n6811), .C1(n5449), .Y(n1735) );
OAI222X1TS U7407 ( .A0(n5445), .A1(n5432), .B0(n5434), .B1(n5431), .C0(n6787), .C1(n6578), .Y(n1687) );
OAI222X1TS U7408 ( .A0(n5443), .A1(n5437), .B0(n3245), .B1(n5436), .C0(n6785), .C1(n5454), .Y(n1732) );
OAI222X1TS U7409 ( .A0(n5445), .A1(n5444), .B0(n5434), .B1(n5442), .C0(n6788), .C1(n6578), .Y(n1689) );
MXI2X1TS U7410 ( .A(n6593), .B(n6590), .S0(n6059), .Y(n3169) );
MXI2X1TS U7411 ( .A(n6932), .B(n5447), .S0(n6059), .Y(n3165) );
BUFX3TS U7412 ( .A(n6590), .Y(n6592) );
NAND2X1TS U7413 ( .A(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[56]), .B(
intadd_44_n1), .Y(n5456) );
OAI21X1TS U7414 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[56]), .A1(
intadd_44_n1), .B0(n5456), .Y(n5457) );
NOR2X1TS U7415 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[56]), .B(n5457),
.Y(n5980) );
AOI21X1TS U7416 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[56]), .A1(
n5457), .B0(n5980), .Y(n5458) );
AOI21X1TS U7417 ( .A0(n5787), .A1(n5461), .B0(n5460), .Y(n5772) );
NAND2X1TS U7418 ( .A(n5464), .B(n5463), .Y(n5468) );
INVX2TS U7419 ( .A(n5468), .Y(n5465) );
INVX2TS U7420 ( .A(n5788), .Y(n5467) );
AOI21X1TS U7421 ( .A0(n5793), .A1(n5789), .B0(n5467), .Y(n5469) );
XOR2X1TS U7422 ( .A(n5469), .B(n5468), .Y(n5470) );
BUFX3TS U7423 ( .A(n5766), .Y(n6002) );
AOI22X1TS U7424 ( .A0(n5470), .A1(n6002), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[19]), .B1(n5492), .Y(
n5471) );
OAI2BB1X1TS U7425 ( .A0N(n5978), .A1N(n5472), .B0(n5471), .Y(n2061) );
NAND2X1TS U7426 ( .A(n5475), .B(n5474), .Y(n5478) );
INVX2TS U7427 ( .A(n5478), .Y(n5476) );
XNOR2X1TS U7428 ( .A(n5477), .B(n5476), .Y(n5482) );
XOR2X1TS U7429 ( .A(n5479), .B(n5478), .Y(n5480) );
AOI22X1TS U7430 ( .A0(n5480), .A1(n6008), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[45]), .B1(n5492), .Y(
n5481) );
OAI2BB1X1TS U7431 ( .A0N(n5553), .A1N(n5482), .B0(n5481), .Y(n2035) );
NAND2X1TS U7432 ( .A(n5485), .B(n5484), .Y(n5490) );
INVX2TS U7433 ( .A(n5490), .Y(n5486) );
XNOR2X1TS U7434 ( .A(n5491), .B(n5490), .Y(n5493) );
AOI22X1TS U7435 ( .A0(n5493), .A1(n5644), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[44]), .B1(n5492), .Y(
n5494) );
OAI2BB1X1TS U7436 ( .A0N(n5553), .A1N(n5495), .B0(n5494), .Y(n2036) );
NAND2X1TS U7437 ( .A(n5497), .B(n5496), .Y(n5500) );
INVX2TS U7438 ( .A(n5500), .Y(n5498) );
XNOR2X1TS U7439 ( .A(n5501), .B(n5500), .Y(n5502) );
AOI22X1TS U7440 ( .A0(n5502), .A1(n6008), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[50]), .B1(n5580), .Y(
n5503) );
OAI2BB1X1TS U7441 ( .A0N(n5553), .A1N(n5504), .B0(n5503), .Y(n2030) );
INVX2TS U7442 ( .A(n5506), .Y(n5508) );
NAND2X1TS U7443 ( .A(n5508), .B(n5507), .Y(n5510) );
INVX2TS U7444 ( .A(n5510), .Y(n5509) );
XNOR2X1TS U7445 ( .A(n5505), .B(n5509), .Y(n5514) );
XOR2X1TS U7446 ( .A(n5511), .B(n5510), .Y(n5512) );
AOI22X1TS U7447 ( .A0(n5512), .A1(n5644), .B0(n3256), .B1(n5580), .Y(n5513)
);
OAI2BB1X1TS U7448 ( .A0N(n5553), .A1N(n5514), .B0(n5513), .Y(n2031) );
NAND2X1TS U7449 ( .A(n5516), .B(n5515), .Y(n5519) );
INVX2TS U7450 ( .A(n5519), .Y(n5517) );
XNOR2X1TS U7451 ( .A(n5520), .B(n5519), .Y(n5521) );
AOI22X1TS U7452 ( .A0(n5521), .A1(n6008), .B0(n3253), .B1(n5580), .Y(n5522)
);
OAI2BB1X1TS U7453 ( .A0N(n5553), .A1N(n5523), .B0(n5522), .Y(n2032) );
INVX2TS U7454 ( .A(n5524), .Y(n5526) );
NAND2X1TS U7455 ( .A(n5526), .B(n5525), .Y(n5529) );
INVX2TS U7456 ( .A(n5529), .Y(n5527) );
XNOR2X1TS U7457 ( .A(n5528), .B(n5527), .Y(n5533) );
XOR2X1TS U7458 ( .A(n5530), .B(n5529), .Y(n5531) );
AOI22X1TS U7459 ( .A0(n5531), .A1(n5644), .B0(n3237), .B1(n5580), .Y(n5532)
);
OAI2BB1X1TS U7460 ( .A0N(n5553), .A1N(n5533), .B0(n5532), .Y(n2029) );
NAND2X1TS U7461 ( .A(n5535), .B(n5534), .Y(n5538) );
INVX2TS U7462 ( .A(n5538), .Y(n5536) );
XNOR2X1TS U7463 ( .A(n5539), .B(n5538), .Y(n5540) );
AOI22X1TS U7464 ( .A0(n5540), .A1(n6008), .B0(n3257), .B1(n5580), .Y(n5541)
);
OAI2BB1X1TS U7465 ( .A0N(n5553), .A1N(n5542), .B0(n5541), .Y(n2028) );
INVX2TS U7466 ( .A(n5544), .Y(n5546) );
NAND2X1TS U7467 ( .A(n5546), .B(n5545), .Y(n5548) );
INVX2TS U7468 ( .A(n5548), .Y(n5547) );
XNOR2X1TS U7469 ( .A(n5543), .B(n5547), .Y(n5552) );
XOR2X1TS U7470 ( .A(n5549), .B(n5548), .Y(n5550) );
AOI22X1TS U7471 ( .A0(n5550), .A1(n5644), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[47]), .B1(n5580), .Y(
n5551) );
OAI2BB1X1TS U7472 ( .A0N(n5553), .A1N(n5552), .B0(n5551), .Y(n2033) );
BUFX3TS U7473 ( .A(n5703), .Y(n5702) );
INVX2TS U7474 ( .A(n5554), .Y(n5557) );
INVX2TS U7475 ( .A(n5555), .Y(n5556) );
OAI21X1TS U7476 ( .A0(n5618), .A1(n5557), .B0(n5556), .Y(n5577) );
INVX2TS U7477 ( .A(n5559), .Y(n5560) );
AOI21X1TS U7478 ( .A0(n5577), .A1(n5561), .B0(n5560), .Y(n5564) );
NAND2X1TS U7479 ( .A(n5683), .B(n5681), .Y(n5569) );
INVX2TS U7480 ( .A(n5569), .Y(n5563) );
INVX2TS U7481 ( .A(n5565), .Y(n5568) );
INVX1TS U7482 ( .A(n5566), .Y(n5567) );
OAI21X1TS U7483 ( .A0(n5625), .A1(n5568), .B0(n5567), .Y(n5684) );
XNOR2X1TS U7484 ( .A(n5684), .B(n5569), .Y(n5570) );
AOI22X1TS U7485 ( .A0(n5570), .A1(n5644), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[36]), .B1(n5580), .Y(
n5571) );
OAI2BB1X1TS U7486 ( .A0N(n5702), .A1N(n5572), .B0(n5571), .Y(n2044) );
NAND2X1TS U7487 ( .A(n5575), .B(n5574), .Y(n5578) );
INVX2TS U7488 ( .A(n5578), .Y(n5576) );
XNOR2X1TS U7489 ( .A(n5577), .B(n5576), .Y(n5583) );
XNOR2X1TS U7490 ( .A(n5579), .B(n5578), .Y(n5581) );
AOI22X1TS U7491 ( .A0(n5581), .A1(n5644), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[35]), .B1(n5580), .Y(
n5582) );
OAI2BB1X1TS U7492 ( .A0N(n5702), .A1N(n5583), .B0(n5582), .Y(n2045) );
OAI21X1TS U7493 ( .A0(n5618), .A1(n5585), .B0(n5584), .Y(n5666) );
INVX2TS U7494 ( .A(n5666), .Y(n5680) );
INVX2TS U7495 ( .A(n5586), .Y(n5589) );
INVX2TS U7496 ( .A(n5587), .Y(n5588) );
OAI21X1TS U7497 ( .A0(n5680), .A1(n5589), .B0(n5588), .Y(n5606) );
NAND2X1TS U7498 ( .A(n5592), .B(n5591), .Y(n5597) );
INVX2TS U7499 ( .A(n5597), .Y(n5593) );
XNOR2X1TS U7500 ( .A(n5606), .B(n5593), .Y(n5601) );
INVX2TS U7501 ( .A(n5667), .Y(n5595) );
AOI21X1TS U7502 ( .A0(n5596), .A1(n5668), .B0(n5595), .Y(n5598) );
XOR2X1TS U7503 ( .A(n5598), .B(n5597), .Y(n5599) );
AOI22X1TS U7504 ( .A0(n5599), .A1(n5644), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[39]), .B1(n5698), .Y(
n5600) );
OAI2BB1X1TS U7505 ( .A0N(n5702), .A1N(n5601), .B0(n5600), .Y(n2041) );
INVX2TS U7506 ( .A(n5603), .Y(n5604) );
AOI21X1TS U7507 ( .A0(n5606), .A1(n5605), .B0(n5604), .Y(n5610) );
NAND2X1TS U7508 ( .A(n5608), .B(n5607), .Y(n5611) );
INVX2TS U7509 ( .A(n5611), .Y(n5609) );
XNOR2X1TS U7510 ( .A(n5612), .B(n5611), .Y(n5613) );
AOI22X1TS U7511 ( .A0(n5613), .A1(n5752), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[40]), .B1(n5698), .Y(
n5614) );
OAI2BB1X1TS U7512 ( .A0N(n5702), .A1N(n5615), .B0(n5614), .Y(n2040) );
NAND2X1TS U7513 ( .A(n5621), .B(n5620), .Y(n5624) );
INVX2TS U7514 ( .A(n5624), .Y(n5622) );
XNOR2X1TS U7515 ( .A(n5623), .B(n5622), .Y(n5628) );
XOR2X1TS U7516 ( .A(n5625), .B(n5624), .Y(n5626) );
AOI22X1TS U7517 ( .A0(n5626), .A1(n5644), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[34]), .B1(n5698), .Y(
n5627) );
OAI2BB1X1TS U7518 ( .A0N(n5702), .A1N(n5628), .B0(n5627), .Y(n2046) );
INVX2TS U7519 ( .A(n5629), .Y(n5632) );
INVX2TS U7520 ( .A(n5630), .Y(n5631) );
AOI21X1TS U7521 ( .A0(n5729), .A1(n5632), .B0(n5631), .Y(n5744) );
INVX2TS U7522 ( .A(n5744), .Y(n5708) );
AOI21X1TS U7523 ( .A0(n5708), .A1(n5634), .B0(n5633), .Y(n5694) );
NAND2X1TS U7524 ( .A(n5639), .B(n5638), .Y(n5642) );
INVX2TS U7525 ( .A(n5642), .Y(n5640) );
XNOR2X1TS U7526 ( .A(n5641), .B(n5640), .Y(n5647) );
XOR2X1TS U7527 ( .A(n5643), .B(n5642), .Y(n5645) );
AOI22X1TS U7528 ( .A0(n5645), .A1(n5644), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[32]), .B1(n5698), .Y(
n5646) );
OAI2BB1X1TS U7529 ( .A0N(n5702), .A1N(n5647), .B0(n5646), .Y(n2048) );
INVX2TS U7530 ( .A(n5649), .Y(n5650) );
AOI21X1TS U7531 ( .A0(n5652), .A1(n5651), .B0(n5650), .Y(n5656) );
NAND2X1TS U7532 ( .A(n5654), .B(n5653), .Y(n5657) );
INVX2TS U7533 ( .A(n5657), .Y(n5655) );
XNOR2X1TS U7534 ( .A(n5658), .B(n5657), .Y(n5659) );
AOI22X1TS U7535 ( .A0(n5659), .A1(n5752), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[42]), .B1(n5698), .Y(
n5660) );
OAI2BB1X1TS U7536 ( .A0N(n5702), .A1N(n5661), .B0(n5660), .Y(n2038) );
INVX2TS U7537 ( .A(n5663), .Y(n5664) );
AOI21X1TS U7538 ( .A0(n5666), .A1(n5665), .B0(n5664), .Y(n5670) );
NAND2X1TS U7539 ( .A(n5668), .B(n5667), .Y(n5671) );
INVX2TS U7540 ( .A(n5671), .Y(n5669) );
XOR2X1TS U7541 ( .A(n5672), .B(n5671), .Y(n5673) );
AOI22X1TS U7542 ( .A0(n5673), .A1(n5752), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[38]), .B1(n5698), .Y(
n5674) );
OAI2BB1X1TS U7543 ( .A0N(n5702), .A1N(n5675), .B0(n5674), .Y(n2042) );
NAND2X1TS U7544 ( .A(n5678), .B(n5677), .Y(n5685) );
INVX2TS U7545 ( .A(n5685), .Y(n5679) );
AOI21X1TS U7546 ( .A0(n5684), .A1(n5683), .B0(n5682), .Y(n5686) );
XOR2X1TS U7547 ( .A(n5686), .B(n5685), .Y(n5687) );
AOI22X1TS U7548 ( .A0(n5687), .A1(n5752), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[37]), .B1(n5698), .Y(
n5688) );
OAI2BB1X1TS U7549 ( .A0N(n5702), .A1N(n5689), .B0(n5688), .Y(n2043) );
NAND2X1TS U7550 ( .A(n5692), .B(n5691), .Y(n5696) );
INVX2TS U7551 ( .A(n5696), .Y(n5693) );
XNOR2X1TS U7552 ( .A(n5697), .B(n5696), .Y(n5699) );
AOI22X1TS U7553 ( .A0(n5699), .A1(n5752), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[31]), .B1(n5698), .Y(
n5700) );
OAI2BB1X1TS U7554 ( .A0N(n5702), .A1N(n5701), .B0(n5700), .Y(n2049) );
BUFX3TS U7555 ( .A(n5703), .Y(n6006) );
NAND2X1TS U7556 ( .A(n5706), .B(n5705), .Y(n5711) );
INVX2TS U7557 ( .A(n5711), .Y(n5707) );
XNOR2X1TS U7558 ( .A(n5708), .B(n5707), .Y(n5715) );
AOI21X1TS U7559 ( .A0(n5723), .A1(n5710), .B0(n5709), .Y(n5738) );
XNOR2X1TS U7560 ( .A(n5712), .B(n5711), .Y(n5713) );
AOI22X1TS U7561 ( .A0(n5713), .A1(n5752), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[29]), .B1(n5822), .Y(
n5714) );
OAI2BB1X1TS U7562 ( .A0N(n6006), .A1N(n5715), .B0(n5714), .Y(n2051) );
NAND2X1TS U7563 ( .A(n5719), .B(n5997), .Y(n5722) );
INVX2TS U7564 ( .A(n5722), .Y(n5720) );
XNOR2X1TS U7565 ( .A(n5721), .B(n5720), .Y(n5726) );
XNOR2X1TS U7566 ( .A(n5723), .B(n5722), .Y(n5724) );
AOI22X1TS U7567 ( .A0(n5724), .A1(n5752), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[26]), .B1(n5822), .Y(
n5725) );
OAI2BB1X1TS U7568 ( .A0N(n6006), .A1N(n5726), .B0(n5725), .Y(n2054) );
AOI21X1TS U7569 ( .A0(n5729), .A1(n5728), .B0(n5727), .Y(n5996) );
NAND2X1TS U7570 ( .A(n5734), .B(n5733), .Y(n5737) );
INVX2TS U7571 ( .A(n5737), .Y(n5735) );
XNOR2X1TS U7572 ( .A(n5736), .B(n5735), .Y(n5741) );
XOR2X1TS U7573 ( .A(n5738), .B(n5737), .Y(n5739) );
AOI22X1TS U7574 ( .A0(n5739), .A1(n5752), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[28]), .B1(n5822), .Y(
n5740) );
OAI2BB1X1TS U7575 ( .A0N(n6006), .A1N(n5741), .B0(n5740), .Y(n2052) );
NAND2X1TS U7576 ( .A(n5747), .B(n5746), .Y(n5750) );
INVX2TS U7577 ( .A(n5750), .Y(n5748) );
XNOR2X1TS U7578 ( .A(n5749), .B(n5748), .Y(n5755) );
XNOR2X1TS U7579 ( .A(n5751), .B(n5750), .Y(n5753) );
AOI22X1TS U7580 ( .A0(n5753), .A1(n5752), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[30]), .B1(n5822), .Y(
n5754) );
OAI2BB1X1TS U7581 ( .A0N(n6006), .A1N(n5755), .B0(n5754), .Y(n2050) );
NAND2X1TS U7582 ( .A(n5761), .B(n5760), .Y(n5764) );
INVX2TS U7583 ( .A(n5764), .Y(n5762) );
XNOR2X1TS U7584 ( .A(n5763), .B(n5762), .Y(n5769) );
XOR2X1TS U7585 ( .A(n5765), .B(n5764), .Y(n5767) );
BUFX3TS U7586 ( .A(n5766), .Y(n5891) );
AOI22X1TS U7587 ( .A0(n5767), .A1(n5891), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[24]), .B1(n5822), .Y(
n5768) );
OAI2BB1X1TS U7588 ( .A0N(n6006), .A1N(n5769), .B0(n5768), .Y(n2056) );
NAND2X1TS U7589 ( .A(n5775), .B(n5774), .Y(n5778) );
INVX2TS U7590 ( .A(n5778), .Y(n5776) );
XNOR2X1TS U7591 ( .A(n5777), .B(n5776), .Y(n5782) );
XOR2X1TS U7592 ( .A(n5779), .B(n5778), .Y(n5780) );
AOI22X1TS U7593 ( .A0(n5780), .A1(n5891), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[20]), .B1(n5822), .Y(
n5781) );
OAI2BB1X1TS U7594 ( .A0N(n6006), .A1N(n5782), .B0(n5781), .Y(n2060) );
INVX2TS U7595 ( .A(n5783), .Y(n5786) );
INVX2TS U7596 ( .A(n5784), .Y(n5785) );
AOI21X1TS U7597 ( .A0(n5787), .A1(n5786), .B0(n5785), .Y(n5791) );
NAND2X1TS U7598 ( .A(n5789), .B(n5788), .Y(n5792) );
INVX2TS U7599 ( .A(n5792), .Y(n5790) );
XNOR2X1TS U7600 ( .A(n5793), .B(n5792), .Y(n5794) );
AOI22X1TS U7601 ( .A0(n5794), .A1(n5891), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[18]), .B1(n5822), .Y(
n5795) );
OAI2BB1X1TS U7602 ( .A0N(n6006), .A1N(n5796), .B0(n5795), .Y(n2062) );
INVX2TS U7603 ( .A(n5798), .Y(n5799) );
AOI21X1TS U7604 ( .A0(n5801), .A1(n5800), .B0(n5799), .Y(n5805) );
NAND2X1TS U7605 ( .A(n5803), .B(n5802), .Y(n5806) );
INVX2TS U7606 ( .A(n5806), .Y(n5804) );
XNOR2X1TS U7607 ( .A(n5807), .B(n5806), .Y(n5808) );
AOI22X1TS U7608 ( .A0(n5808), .A1(n5891), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[16]), .B1(n5822), .Y(
n5809) );
OAI2BB1X1TS U7609 ( .A0N(n5947), .A1N(n5810), .B0(n5809), .Y(n2064) );
INVX2TS U7610 ( .A(n5812), .Y(n5813) );
AOI21X1TS U7611 ( .A0(n5815), .A1(n5814), .B0(n5813), .Y(n5819) );
NAND2X1TS U7612 ( .A(n5817), .B(n5816), .Y(n5820) );
INVX2TS U7613 ( .A(n5820), .Y(n5818) );
XOR2X1TS U7614 ( .A(n5821), .B(n5820), .Y(n5823) );
AOI22X1TS U7615 ( .A0(n5823), .A1(n5891), .B0(n3274), .B1(n5822), .Y(n5824)
);
OAI2BB1X1TS U7616 ( .A0N(n6006), .A1N(n5825), .B0(n5824), .Y(n2066) );
INVX2TS U7617 ( .A(n5826), .Y(n5829) );
INVX2TS U7618 ( .A(n5827), .Y(n5828) );
OAI21X1TS U7619 ( .A0(n5885), .A1(n5829), .B0(n5828), .Y(n5843) );
NAND2X1TS U7620 ( .A(n5832), .B(n5831), .Y(n5834) );
INVX2TS U7621 ( .A(n5834), .Y(n5833) );
XNOR2X1TS U7622 ( .A(n5843), .B(n5833), .Y(n5838) );
XNOR2X1TS U7623 ( .A(n5835), .B(n5834), .Y(n5836) );
AOI22X1TS U7624 ( .A0(n5836), .A1(n5891), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n5932), .Y(
n5837) );
OAI2BB1X1TS U7625 ( .A0N(n5947), .A1N(n5838), .B0(n5837), .Y(n2069) );
INVX2TS U7626 ( .A(n5840), .Y(n5841) );
AOI21X1TS U7627 ( .A0(n5843), .A1(n5842), .B0(n5841), .Y(n5846) );
NAND2X1TS U7628 ( .A(n5862), .B(n5860), .Y(n5851) );
INVX2TS U7629 ( .A(n5851), .Y(n5845) );
INVX2TS U7630 ( .A(n5847), .Y(n5850) );
OAI21X1TS U7631 ( .A0(n5877), .A1(n5850), .B0(n5849), .Y(n5863) );
XNOR2X1TS U7632 ( .A(n5863), .B(n5851), .Y(n5852) );
AOI22X1TS U7633 ( .A0(n5852), .A1(n5891), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n5932), .Y(
n5853) );
OAI2BB1X1TS U7634 ( .A0N(n5947), .A1N(n5854), .B0(n5853), .Y(n2068) );
NAND2X1TS U7635 ( .A(n5857), .B(n5856), .Y(n5864) );
INVX2TS U7636 ( .A(n5864), .Y(n5858) );
AOI21X1TS U7637 ( .A0(n5863), .A1(n5862), .B0(n5861), .Y(n5865) );
XOR2X1TS U7638 ( .A(n5865), .B(n5864), .Y(n5866) );
AOI22X1TS U7639 ( .A0(n5866), .A1(n5891), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[13]), .B1(n5932), .Y(
n5867) );
OAI2BB1X1TS U7640 ( .A0N(n5947), .A1N(n5868), .B0(n5867), .Y(n2067) );
NAND2X1TS U7641 ( .A(n5873), .B(n5872), .Y(n5876) );
INVX2TS U7642 ( .A(n5876), .Y(n5874) );
XNOR2X1TS U7643 ( .A(n5875), .B(n5874), .Y(n5880) );
XOR2X1TS U7644 ( .A(n5877), .B(n5876), .Y(n5878) );
AOI22X1TS U7645 ( .A0(n5878), .A1(n5891), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n5932), .Y(
n5879) );
OAI2BB1X1TS U7646 ( .A0N(n5947), .A1N(n5880), .B0(n5879), .Y(n2070) );
INVX2TS U7647 ( .A(n5881), .Y(n5883) );
NAND2X1TS U7648 ( .A(n5883), .B(n5882), .Y(n5889) );
INVX2TS U7649 ( .A(n5889), .Y(n5884) );
INVX2TS U7650 ( .A(n5886), .Y(n5931) );
AOI21X1TS U7651 ( .A0(n5931), .A1(n5888), .B0(n5887), .Y(n5906) );
XNOR2X1TS U7652 ( .A(n5890), .B(n5889), .Y(n5892) );
AOI22X1TS U7653 ( .A0(n5892), .A1(n5891), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n5932), .Y(n5893) );
OAI2BB1X1TS U7654 ( .A0N(n5947), .A1N(n5894), .B0(n5893), .Y(n2071) );
INVX2TS U7655 ( .A(n5895), .Y(n5940) );
AOI21X1TS U7656 ( .A0(n5940), .A1(n5897), .B0(n5896), .Y(n5914) );
NAND2X1TS U7657 ( .A(n5902), .B(n5901), .Y(n5905) );
INVX2TS U7658 ( .A(n5905), .Y(n5903) );
XNOR2X1TS U7659 ( .A(n5904), .B(n5903), .Y(n5909) );
XOR2X1TS U7660 ( .A(n5906), .B(n5905), .Y(n5907) );
AOI22X1TS U7661 ( .A0(n5907), .A1(n6002), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n5932), .Y(n5908) );
OAI2BB1X1TS U7662 ( .A0N(n5947), .A1N(n5909), .B0(n5908), .Y(n2072) );
NAND2X1TS U7663 ( .A(n5912), .B(n5911), .Y(n5917) );
INVX2TS U7664 ( .A(n5917), .Y(n5913) );
AOI21X1TS U7665 ( .A0(n5931), .A1(n5927), .B0(n5916), .Y(n5918) );
XOR2X1TS U7666 ( .A(n5918), .B(n5917), .Y(n5919) );
AOI22X1TS U7667 ( .A0(n5919), .A1(n6002), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[7]), .B1(n5932), .Y(n5920) );
OAI2BB1X1TS U7668 ( .A0N(n5947), .A1N(n5921), .B0(n5920), .Y(n2073) );
INVX2TS U7669 ( .A(n5922), .Y(n5925) );
INVX2TS U7670 ( .A(n5923), .Y(n5924) );
AOI21X1TS U7671 ( .A0(n5940), .A1(n5925), .B0(n5924), .Y(n5929) );
NAND2X1TS U7672 ( .A(n5927), .B(n5926), .Y(n5930) );
INVX2TS U7673 ( .A(n5930), .Y(n5928) );
XNOR2X1TS U7674 ( .A(n5931), .B(n5930), .Y(n5933) );
AOI22X1TS U7675 ( .A0(n5933), .A1(n6002), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n5932), .Y(n5934) );
OAI2BB1X1TS U7676 ( .A0N(n5978), .A1N(n5935), .B0(n5934), .Y(n2074) );
INVX2TS U7677 ( .A(n5936), .Y(n5938) );
NAND2X1TS U7678 ( .A(n5938), .B(n5937), .Y(n5942) );
INVX2TS U7679 ( .A(n5942), .Y(n5939) );
XNOR2X1TS U7680 ( .A(n5940), .B(n5939), .Y(n5946) );
XNOR2X1TS U7681 ( .A(n5943), .B(n5942), .Y(n5944) );
BUFX3TS U7682 ( .A(n6473), .Y(n6579) );
AOI22X1TS U7683 ( .A0(n5944), .A1(n6002), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[5]), .B1(n6579), .Y(n5945) );
OAI2BB1X1TS U7684 ( .A0N(n5947), .A1N(n5946), .B0(n5945), .Y(n2075) );
INVX2TS U7685 ( .A(n5948), .Y(n5959) );
INVX2TS U7686 ( .A(n5949), .Y(n5951) );
NAND2X1TS U7687 ( .A(n5951), .B(n5950), .Y(n5953) );
INVX2TS U7688 ( .A(n5953), .Y(n5952) );
XOR2X1TS U7689 ( .A(n5953), .B(n5970), .Y(n5954) );
AOI22X1TS U7690 ( .A0(n5954), .A1(n6002), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[3]), .B1(n6579), .Y(n5955) );
OAI2BB1X1TS U7691 ( .A0N(n5978), .A1N(n5956), .B0(n5955), .Y(n2077) );
NAND2X1TS U7692 ( .A(n5962), .B(n5961), .Y(n5965) );
INVX2TS U7693 ( .A(n5965), .Y(n5963) );
XNOR2X1TS U7694 ( .A(n5964), .B(n5963), .Y(n5969) );
XOR2X1TS U7695 ( .A(n5966), .B(n5965), .Y(n5967) );
AOI22X1TS U7696 ( .A0(n5967), .A1(n6002), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[4]), .B1(n6579), .Y(n5968) );
OAI2BB1X1TS U7697 ( .A0N(n6006), .A1N(n5969), .B0(n5968), .Y(n2076) );
OR2X1TS U7698 ( .A(n3263), .B(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n5971) );
AOI22X1TS U7699 ( .A0(n5973), .A1(n6002), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n6579), .Y(n5974) );
OAI2BB1X1TS U7700 ( .A0N(n5978), .A1N(n5975), .B0(n5974), .Y(n2078) );
XNOR2X1TS U7701 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[1]), .B(
n5979), .Y(n5977) );
AOI22X1TS U7702 ( .A0(n6002), .A1(
inst_FPU_PIPELINED_FPADDSUB_DmP_mant_SFG_SWR[1]), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n6579), .Y(n5976) );
OAI2BB1X1TS U7703 ( .A0N(n5978), .A1N(n5977), .B0(n5976), .Y(n2079) );
MXI2X1TS U7704 ( .A(n6758), .B(n5979), .S0(n3216), .Y(n2080) );
AOI21X1TS U7705 ( .A0(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[56]), .A1(
intadd_44_n1), .B0(n5980), .Y(n5981) );
XOR2X1TS U7706 ( .A(n5981), .B(inst_FPU_PIPELINED_FPADDSUB_DMP_EXP_EWSW[57]),
.Y(n5982) );
XOR2X1TS U7707 ( .A(inst_FPU_PIPELINED_FPADDSUB_DmP_EXP_EWSW[57]), .B(n5982),
.Y(n5983) );
NAND2X1TS U7708 ( .A(n5986), .B(n4733), .Y(n5991) );
NAND2X1TS U7709 ( .A(n5988), .B(n5360), .Y(n5989) );
NAND2X1TS U7710 ( .A(n5994), .B(n5993), .Y(n6000) );
INVX2TS U7711 ( .A(n6000), .Y(n5995) );
XNOR2X1TS U7712 ( .A(n6001), .B(n6000), .Y(n6003) );
AOI22X1TS U7713 ( .A0(n6003), .A1(n6002), .B0(
inst_FPU_PIPELINED_FPADDSUB_Raw_mant_NRM_SWR[27]), .B1(n6579), .Y(
n6004) );
OAI2BB1X1TS U7714 ( .A0N(n6006), .A1N(n6005), .B0(n6004), .Y(n2053) );
OAI2BB1X1TS U7715 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_LZD_output_NRM2_EW[0]),
.A1N(n6559), .B0(n6016), .Y(n2023) );
AND3X2TS U7716 ( .A(n6695), .B(n6642), .C(ready_add_subt), .Y(n6466) );
BUFX3TS U7717 ( .A(n6466), .Y(n6462) );
OA22X1TS U7718 ( .A0(n6029), .A1(n6024), .B0(n6846), .B1(result_add_subt[52]), .Y(n2268) );
OA22X1TS U7719 ( .A0(n6029), .A1(n6025), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(
result_add_subt[54]), .Y(n2266) );
OA22X1TS U7720 ( .A0(n6029), .A1(n6026), .B0(n6846), .B1(result_add_subt[58]), .Y(n2262) );
OA22X1TS U7721 ( .A0(n6029), .A1(n6027), .B0(n3219), .B1(result_add_subt[59]), .Y(n2261) );
OA22X1TS U7722 ( .A0(n6029), .A1(n6028), .B0(n6846), .B1(result_add_subt[61]), .Y(n2259) );
NOR2BX1TS U7723 ( .AN(n6037), .B(
inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n6031) );
OAI22X1TS U7724 ( .A0(n6031), .A1(n6030), .B0(n3219), .B1(n6818), .Y(n2087)
);
AND3X2TS U7725 ( .A(n6695), .B(cont_var_out[0]), .C(ready_add_subt), .Y(
n6328) );
BUFX3TS U7726 ( .A(n6328), .Y(n6330) );
OA22X1TS U7727 ( .A0(n6479), .A1(n6038), .B0(n3219), .B1(result_add_subt[53]), .Y(n2267) );
OA22X1TS U7728 ( .A0(n6479), .A1(n6039), .B0(n6846), .B1(result_add_subt[55]), .Y(n2265) );
OA22X1TS U7729 ( .A0(n6479), .A1(n6040), .B0(n6846), .B1(result_add_subt[56]), .Y(n2264) );
OA22X1TS U7730 ( .A0(n6479), .A1(n6041), .B0(n6846), .B1(result_add_subt[57]), .Y(n2263) );
OA22X1TS U7731 ( .A0(n6479), .A1(n6042), .B0(n3219), .B1(result_add_subt[60]), .Y(n2260) );
BUFX3TS U7732 ( .A(n6044), .Y(n6329) );
INVX2TS U7733 ( .A(n6044), .Y(n6170) );
NOR2BX1TS U7734 ( .AN(n6051), .B(n6059), .Y(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
NOR2BX1TS U7735 ( .AN(beg_fsm_cordic), .B(n6052), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
INVX2TS U7736 ( .A(n6256), .Y(n6321) );
OAI2BB2XLTS U7737 ( .B0(n6055), .B1(n6054), .A0N(n6056), .A1N(n6170), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U7738 ( .AN(n6056), .B(n6046), .Y(inst_CORDIC_FSM_v3_state_next[6]) );
AO21XLTS U7739 ( .A0(inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .A1(
n6059), .B0(
inst_FPU_PIPELINED_FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .Y(
n3171) );
INVX2TS U7740 ( .A(n6059), .Y(n6060) );
BUFX3TS U7741 ( .A(n6591), .Y(n6480) );
AOI22X1TS U7742 ( .A0(n6060), .A1(n6560), .B0(n6480), .B1(n6059), .Y(n3170)
);
AOI21X1TS U7743 ( .A0(n6670), .A1(n6061), .B0(n6062), .Y(n3163) );
XNOR2X1TS U7744 ( .A(cont_var_out[0]), .B(n6063), .Y(n3160) );
AOI31X1TS U7745 ( .A0(cont_iter_out[1]), .A1(n3217), .A2(n6064), .B0(n6217),
.Y(n6072) );
OA21XLTS U7746 ( .A0(n6321), .A1(d_ff3_LUT_out[53]), .B0(n6065), .Y(n3155)
);
AOI22X1TS U7747 ( .A0(n6829), .A1(n6217), .B0(n6071), .B1(n6067), .Y(n3151)
);
OAI2BB1X1TS U7748 ( .A0N(d_ff3_LUT_out[42]), .A1N(n3876), .B0(n6068), .Y(
n3149) );
OA22X1TS U7749 ( .A0(n6457), .A1(d_ff3_LUT_out[39]), .B0(n6069), .B1(n6080),
.Y(n3147) );
AOI22X1TS U7750 ( .A0(n6830), .A1(n6217), .B0(n6073), .B1(n6072), .Y(n3140)
);
NAND2X1TS U7751 ( .A(n6074), .B(n6670), .Y(n6094) );
OA22X1TS U7752 ( .A0(n6457), .A1(d_ff3_LUT_out[28]), .B0(cont_iter_out[3]),
.B1(n6094), .Y(n3139) );
AOI22X1TS U7753 ( .A0(n3187), .A1(n6075), .B0(d_ff3_LUT_out[27]), .B1(n6110),
.Y(n6077) );
AOI32X1TS U7754 ( .A0(n6091), .A1(n6077), .A2(n6113), .B0(n6076), .B1(n6077),
.Y(n3138) );
OAI2BB1X1TS U7755 ( .A0N(d_ff3_LUT_out[26]), .A1N(n6271), .B0(n6078), .Y(
n3137) );
AOI22X1TS U7756 ( .A0(n6093), .A1(n6079), .B0(d_ff3_LUT_out[25]), .B1(n6217),
.Y(n6081) );
AOI32X1TS U7757 ( .A0(n6091), .A1(n6081), .A2(n6080), .B0(n3297), .B1(n6081),
.Y(n3136) );
OAI2BB1X1TS U7758 ( .A0N(d_ff3_LUT_out[22]), .A1N(n3876), .B0(n6084), .Y(
n3133) );
OAI2BB1X1TS U7759 ( .A0N(d_ff3_LUT_out[20]), .A1N(n3876), .B0(n6083), .Y(
n3131) );
NAND2X1TS U7760 ( .A(n6085), .B(n6095), .Y(n3130) );
NOR3X1TS U7761 ( .A(n3217), .B(n6087), .C(n6086), .Y(n6098) );
OAI2BB1X1TS U7762 ( .A0N(d_ff3_LUT_out[16]), .A1N(n6271), .B0(n6090), .Y(
n3127) );
AOI21X1TS U7763 ( .A0(d_ff3_LUT_out[9]), .A1(n6185), .B0(n6098), .Y(n6100)
);
OAI21X1TS U7764 ( .A0(n6670), .A1(n6103), .B0(n6102), .Y(n6116) );
OAI2BB1X1TS U7765 ( .A0N(n6106), .A1N(n6105), .B0(n6104), .Y(n3116) );
AOI21X1TS U7766 ( .A0(d_ff3_LUT_out[4]), .A1(n6110), .B0(n6107), .Y(n6108)
);
OAI2BB1X1TS U7767 ( .A0N(n6109), .A1N(n6321), .B0(n6108), .Y(n3115) );
AOI22X1TS U7768 ( .A0(n6112), .A1(n6111), .B0(d_ff3_LUT_out[2]), .B1(n6110),
.Y(n6115) );
OAI2BB2XLTS U7769 ( .B0(n6117), .B1(n6116), .A0N(d_ff3_LUT_out[0]), .A1N(
n6256), .Y(n3111) );
BUFX3TS U7770 ( .A(n6126), .Y(n6131) );
INVX2TS U7771 ( .A(n6131), .Y(n6118) );
INVX2TS U7772 ( .A(n6126), .Y(n6120) );
BUFX3TS U7773 ( .A(n6126), .Y(n6124) );
BUFX3TS U7774 ( .A(n6122), .Y(n6132) );
INVX2TS U7775 ( .A(n6126), .Y(n6121) );
BUFX3TS U7776 ( .A(n6124), .Y(n6123) );
INVX2TS U7777 ( .A(n6122), .Y(n6125) );
BUFX3TS U7778 ( .A(n6124), .Y(n6127) );
INVX2TS U7779 ( .A(n6126), .Y(n6128) );
BUFX3TS U7780 ( .A(n6122), .Y(n6129) );
INVX2TS U7781 ( .A(n6131), .Y(n6130) );
INVX2TS U7782 ( .A(n6131), .Y(n6133) );
OA22X1TS U7783 ( .A0(n6239), .A1(d_ff2_X[0]), .B0(d_ff_Xn[0]), .B1(n6135),
.Y(n2881) );
INVX2TS U7784 ( .A(n6256), .Y(n6311) );
BUFX3TS U7785 ( .A(n6175), .Y(n6134) );
BUFX3TS U7786 ( .A(n6148), .Y(n6265) );
INVX2TS U7787 ( .A(n6265), .Y(n6291) );
INVX2TS U7788 ( .A(n6260), .Y(n6294) );
BUFX3TS U7789 ( .A(n6239), .Y(n6188) );
INVX2TS U7790 ( .A(n6188), .Y(n6200) );
INVX2TS U7791 ( .A(n6256), .Y(n6136) );
OA22X1TS U7792 ( .A0(n6143), .A1(d_ff2_X[3]), .B0(d_ff_Xn[3]), .B1(n3937),
.Y(n2875) );
INVX2TS U7793 ( .A(n6135), .Y(n6147) );
INVX2TS U7794 ( .A(n6135), .Y(n6292) );
INVX2TS U7795 ( .A(n6260), .Y(n6180) );
OA22X1TS U7796 ( .A0(n6143), .A1(d_ff2_X[6]), .B0(d_ff_Xn[6]), .B1(n3937),
.Y(n2869) );
BUFX3TS U7797 ( .A(n6256), .Y(n6137) );
INVX2TS U7798 ( .A(n6175), .Y(n6139) );
INVX2TS U7799 ( .A(n6135), .Y(n6138) );
INVX2TS U7800 ( .A(n6188), .Y(n6463) );
BUFX3TS U7801 ( .A(n6175), .Y(n6140) );
INVX2TS U7802 ( .A(n6175), .Y(n6141) );
INVX2TS U7803 ( .A(n6175), .Y(n6145) );
CLKBUFX2TS U7804 ( .A(n6456), .Y(n6158) );
BUFX3TS U7805 ( .A(n6158), .Y(n6142) );
INVX2TS U7806 ( .A(n6194), .Y(n6191) );
OA22X1TS U7807 ( .A0(n6143), .A1(d_ff2_X[35]), .B0(d_ff_Xn[35]), .B1(n6148),
.Y(n2811) );
OA22X1TS U7808 ( .A0(n6143), .A1(d_ff2_X[36]), .B0(d_ff_Xn[36]), .B1(n3937),
.Y(n2809) );
OA22X1TS U7809 ( .A0(n6143), .A1(d_ff2_X[39]), .B0(d_ff_Xn[39]), .B1(n3937),
.Y(n2803) );
INVX2TS U7810 ( .A(n6188), .Y(n6235) );
BUFX3TS U7811 ( .A(n6158), .Y(n6146) );
OA22X1TS U7812 ( .A0(n6143), .A1(d_ff2_X[41]), .B0(d_ff_Xn[41]), .B1(n3937),
.Y(n2799) );
INVX2TS U7813 ( .A(n6175), .Y(n6160) );
OA22X1TS U7814 ( .A0(n6144), .A1(d_ff2_X[43]), .B0(d_ff_Xn[43]), .B1(n6148),
.Y(n2795) );
OA22X1TS U7815 ( .A0(n6143), .A1(d_ff2_X[45]), .B0(d_ff_Xn[45]), .B1(n6148),
.Y(n2791) );
OA22X1TS U7816 ( .A0(n6144), .A1(d_ff2_X[46]), .B0(d_ff_Xn[46]), .B1(n6148),
.Y(n2789) );
OA22X1TS U7817 ( .A0(n6150), .A1(d_ff2_X[48]), .B0(d_ff_Xn[48]), .B1(n6148),
.Y(n2785) );
OA22X1TS U7818 ( .A0(n6150), .A1(d_ff2_X[49]), .B0(d_ff_Xn[49]), .B1(n6148),
.Y(n2783) );
OA22X1TS U7819 ( .A0(n6150), .A1(d_ff2_X[53]), .B0(d_ff_Xn[53]), .B1(n3937),
.Y(n2776) );
OA22X1TS U7820 ( .A0(n6150), .A1(d_ff2_X[54]), .B0(d_ff_Xn[54]), .B1(n6148),
.Y(n2775) );
OA22X1TS U7821 ( .A0(n6150), .A1(d_ff2_X[55]), .B0(d_ff_Xn[55]), .B1(n6149),
.Y(n2774) );
OA22X1TS U7822 ( .A0(n6239), .A1(d_ff2_X[56]), .B0(d_ff_Xn[56]), .B1(n6194),
.Y(n2773) );
OA22X1TS U7823 ( .A0(n6188), .A1(d_ff2_X[57]), .B0(d_ff_Xn[57]), .B1(n6265),
.Y(n2772) );
OA22X1TS U7824 ( .A0(n6188), .A1(d_ff2_X[59]), .B0(d_ff_Xn[59]), .B1(n6194),
.Y(n2770) );
OA22X1TS U7825 ( .A0(n6260), .A1(n3235), .B0(n3233), .B1(n3937), .Y(n2768)
);
NOR2X1TS U7826 ( .A(d_ff2_X[56]), .B(intadd_46_n1), .Y(n6154) );
AOI21X1TS U7827 ( .A0(intadd_46_n1), .A1(d_ff2_X[56]), .B0(n6154), .Y(n6153)
);
INVX2TS U7828 ( .A(n6154), .Y(n6155) );
AOI21X1TS U7829 ( .A0(d_ff2_X[57]), .A1(n6155), .B0(n6157), .Y(n6156) );
BUFX3TS U7830 ( .A(n6158), .Y(n6266) );
AOI21X1TS U7831 ( .A0(d_ff2_X[59]), .A1(n6162), .B0(n6161), .Y(n6163) );
NOR2X1TS U7832 ( .A(n3235), .B(n6164), .Y(n6166) );
AOI21X1TS U7833 ( .A0(n3235), .A1(n6164), .B0(n6166), .Y(n6165) );
XOR2X1TS U7834 ( .A(d_ff2_X[62]), .B(n6166), .Y(n6167) );
AOI22X1TS U7835 ( .A0(n6451), .A1(d_ff2_Y[63]), .B0(d_ff2_Z[63]), .B1(n6181),
.Y(n6169) );
AOI22X1TS U7836 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[63]), .A1(n6458), .B0(n6452), .B1(d_ff2_X[63]), .Y(n6168) );
NAND2X1TS U7837 ( .A(n6169), .B(n6168), .Y(n2753) );
AOI22X1TS U7838 ( .A0(n6446), .A1(d_ff3_sh_y_out[0]), .B0(n6181), .B1(
d_ff3_LUT_out[0]), .Y(n6172) );
AOI22X1TS U7839 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .A1(n6458),
.B0(n6407), .B1(d_ff3_sh_x_out[0]), .Y(n6171) );
NAND2X1TS U7840 ( .A(n6172), .B(n6171), .Y(n2748) );
AOI22X1TS U7841 ( .A0(n6452), .A1(d_ff3_sh_y_out[1]), .B0(n6181), .B1(
d_ff3_LUT_out[1]), .Y(n6174) );
AOI22X1TS U7842 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]), .A1(n6458),
.B0(n6201), .B1(d_ff3_sh_x_out[1]), .Y(n6173) );
NAND2X1TS U7843 ( .A(n6174), .B(n6173), .Y(n2745) );
INVX2TS U7844 ( .A(n6175), .Y(n6206) );
AOI22X1TS U7845 ( .A0(n6182), .A1(d_ff3_sh_y_out[2]), .B0(n6181), .B1(
d_ff3_LUT_out[2]), .Y(n6177) );
AOI22X1TS U7846 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]), .A1(n6458),
.B0(n6201), .B1(d_ff3_sh_x_out[2]), .Y(n6176) );
NAND2X1TS U7847 ( .A(n6177), .B(n6176), .Y(n2742) );
BUFX3TS U7848 ( .A(n6232), .Y(n6226) );
AOI22X1TS U7849 ( .A0(n6451), .A1(d_ff3_sh_x_out[3]), .B0(n6226), .B1(
d_ff3_LUT_out[3]), .Y(n6179) );
CLKINVX3TS U7850 ( .A(n6460), .Y(n6211) );
BUFX3TS U7851 ( .A(n6250), .Y(n6420) );
AOI22X1TS U7852 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]), .A1(n6211),
.B0(n6420), .B1(d_ff3_sh_y_out[3]), .Y(n6178) );
NAND2X1TS U7853 ( .A(n6179), .B(n6178), .Y(n2739) );
INVX2TS U7854 ( .A(n6194), .Y(n6253) );
AOI22X1TS U7855 ( .A0(n6182), .A1(d_ff3_sh_y_out[5]), .B0(n6181), .B1(
d_ff3_LUT_out[5]), .Y(n6184) );
AOI22X1TS U7856 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .A1(n6211),
.B0(n6201), .B1(d_ff3_sh_x_out[5]), .Y(n6183) );
NAND2X1TS U7857 ( .A(n6184), .B(n6183), .Y(n2733) );
AOI22X1TS U7858 ( .A0(n6451), .A1(d_ff3_sh_x_out[6]), .B0(n6226), .B1(
d_ff3_LUT_out[6]), .Y(n6187) );
AOI22X1TS U7859 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .A1(n6211),
.B0(n6420), .B1(d_ff3_sh_y_out[6]), .Y(n6186) );
NAND2X1TS U7860 ( .A(n6187), .B(n6186), .Y(n2730) );
INVX2TS U7861 ( .A(n6188), .Y(n6289) );
BUFX3TS U7862 ( .A(n6217), .Y(n6214) );
AOI22X1TS U7863 ( .A0(n6250), .A1(d_ff3_sh_y_out[7]), .B0(n6201), .B1(
d_ff3_sh_x_out[7]), .Y(n6190) );
BUFX3TS U7864 ( .A(n4043), .Y(n6447) );
AOI22X1TS U7865 ( .A0(d_ff3_LUT_out[7]), .A1(n6447), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .B1(n6458), .Y(n6189) );
NAND2X1TS U7866 ( .A(n6190), .B(n6189), .Y(n2727) );
AOI22X1TS U7867 ( .A0(n6451), .A1(d_ff3_sh_x_out[8]), .B0(n6226), .B1(
d_ff3_LUT_out[8]), .Y(n6193) );
AOI22X1TS U7868 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .A1(n6211),
.B0(n6420), .B1(d_ff3_sh_y_out[8]), .Y(n6192) );
NAND2X1TS U7869 ( .A(n6193), .B(n6192), .Y(n2724) );
INVX2TS U7870 ( .A(n6194), .Y(n6221) );
AOI22X1TS U7871 ( .A0(n6250), .A1(d_ff3_sh_y_out[9]), .B0(n6226), .B1(
d_ff3_LUT_out[9]), .Y(n6196) );
AOI22X1TS U7872 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .A1(n6211),
.B0(n6201), .B1(d_ff3_sh_x_out[9]), .Y(n6195) );
NAND2X1TS U7873 ( .A(n6196), .B(n6195), .Y(n2721) );
BUFX3TS U7874 ( .A(n6197), .Y(n6240) );
AOI22X1TS U7875 ( .A0(n6268), .A1(d_ff3_sh_y_out[10]), .B0(n6240), .B1(
d_ff3_sh_x_out[10]), .Y(n6199) );
BUFX3TS U7876 ( .A(n6232), .Y(n6262) );
AOI22X1TS U7877 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .A1(n6211), .B0(n6262), .B1(d_ff3_LUT_out[10]), .Y(n6198) );
NAND2X1TS U7878 ( .A(n6199), .B(n6198), .Y(n2718) );
AOI22X1TS U7879 ( .A0(d_ff3_LUT_out[11]), .A1(n6447), .B0(n6420), .B1(
d_ff3_sh_y_out[11]), .Y(n6203) );
AOI22X1TS U7880 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .A1(n6211), .B0(n6201), .B1(d_ff3_sh_x_out[11]), .Y(n6202) );
NAND2X1TS U7881 ( .A(n6203), .B(n6202), .Y(n2715) );
INVX2TS U7882 ( .A(n6256), .Y(n6249) );
AOI22X1TS U7883 ( .A0(n6451), .A1(d_ff3_sh_x_out[12]), .B0(n6226), .B1(
d_ff3_LUT_out[12]), .Y(n6205) );
AOI22X1TS U7884 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .A1(n6211), .B0(n6452), .B1(d_ff3_sh_y_out[12]), .Y(n6204) );
NAND2X1TS U7885 ( .A(n6205), .B(n6204), .Y(n2712) );
INVX2TS U7886 ( .A(n6260), .Y(n6231) );
AOI22X1TS U7887 ( .A0(n6343), .A1(d_ff3_sh_y_out[13]), .B0(n6240), .B1(
d_ff3_sh_x_out[13]), .Y(n6208) );
AOI22X1TS U7888 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .A1(n6211), .B0(n6262), .B1(d_ff3_LUT_out[13]), .Y(n6207) );
NAND2X1TS U7889 ( .A(n6208), .B(n6207), .Y(n2709) );
AOI22X1TS U7890 ( .A0(n6452), .A1(d_ff3_sh_y_out[14]), .B0(n6226), .B1(
d_ff3_LUT_out[14]), .Y(n6210) );
CLKINVX3TS U7891 ( .A(n6460), .Y(n6241) );
AOI22X1TS U7892 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .A1(n6241), .B0(n6240), .B1(d_ff3_sh_x_out[14]), .Y(n6209) );
NAND2X1TS U7893 ( .A(n6210), .B(n6209), .Y(n2706) );
AOI22X1TS U7894 ( .A0(d_ff3_LUT_out[15]), .A1(n6447), .B0(n6420), .B1(
d_ff3_sh_y_out[15]), .Y(n6213) );
AOI22X1TS U7895 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .A1(n6211), .B0(n6240), .B1(d_ff3_sh_x_out[15]), .Y(n6212) );
NAND2X1TS U7896 ( .A(n6213), .B(n6212), .Y(n2703) );
AOI22X1TS U7897 ( .A0(n6275), .A1(d_ff3_sh_y_out[16]), .B0(n6240), .B1(
d_ff3_sh_x_out[16]), .Y(n6216) );
AOI22X1TS U7898 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .A1(n6241), .B0(n6226), .B1(d_ff3_LUT_out[16]), .Y(n6215) );
NAND2X1TS U7899 ( .A(n6216), .B(n6215), .Y(n2700) );
BUFX3TS U7900 ( .A(n6217), .Y(n6246) );
AOI22X1TS U7901 ( .A0(n6428), .A1(d_ff3_sh_x_out[17]), .B0(n6226), .B1(
d_ff3_LUT_out[17]), .Y(n6220) );
AOI22X1TS U7902 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .A1(n6241), .B0(n6398), .B1(d_ff3_sh_y_out[17]), .Y(n6219) );
NAND2X1TS U7903 ( .A(n6220), .B(n6219), .Y(n2697) );
AOI22X1TS U7904 ( .A0(n6268), .A1(d_ff3_sh_y_out[18]), .B0(n6262), .B1(
d_ff3_LUT_out[18]), .Y(n6223) );
AOI22X1TS U7905 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .A1(n6241), .B0(n6240), .B1(d_ff3_sh_x_out[18]), .Y(n6222) );
NAND2X1TS U7906 ( .A(n6223), .B(n6222), .Y(n2694) );
AOI22X1TS U7907 ( .A0(n6268), .A1(d_ff3_sh_y_out[19]), .B0(n6226), .B1(
d_ff3_LUT_out[19]), .Y(n6225) );
AOI22X1TS U7908 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .A1(n6241), .B0(n6240), .B1(d_ff3_sh_x_out[19]), .Y(n6224) );
NAND2X1TS U7909 ( .A(n6225), .B(n6224), .Y(n2691) );
INVX2TS U7910 ( .A(n6265), .Y(n6274) );
INVX2TS U7911 ( .A(n6256), .Y(n6267) );
AOI22X1TS U7912 ( .A0(n6250), .A1(d_ff3_sh_y_out[20]), .B0(n6240), .B1(
d_ff3_sh_x_out[20]), .Y(n6228) );
AOI22X1TS U7913 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .A1(n6241), .B0(n6226), .B1(d_ff3_LUT_out[20]), .Y(n6227) );
NAND2X1TS U7914 ( .A(n6228), .B(n6227), .Y(n2688) );
AOI22X1TS U7915 ( .A0(n6275), .A1(d_ff3_sh_y_out[21]), .B0(n6240), .B1(
d_ff3_sh_x_out[21]), .Y(n6230) );
AOI22X1TS U7916 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .A1(n6241), .B0(n6262), .B1(d_ff3_LUT_out[21]), .Y(n6229) );
NAND2X1TS U7917 ( .A(n6230), .B(n6229), .Y(n2685) );
BUFX3TS U7918 ( .A(n6232), .Y(n6298) );
AOI22X1TS U7919 ( .A0(n6428), .A1(d_ff3_sh_x_out[22]), .B0(n6298), .B1(
d_ff3_LUT_out[22]), .Y(n6234) );
AOI22X1TS U7920 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .A1(n6241), .B0(n6446), .B1(d_ff3_sh_y_out[22]), .Y(n6233) );
NAND2X1TS U7921 ( .A(n6234), .B(n6233), .Y(n2682) );
AOI22X1TS U7922 ( .A0(n6236), .A1(d_ff3_sh_y_out[23]), .B0(n6262), .B1(
d_ff3_LUT_out[23]), .Y(n6238) );
AOI22X1TS U7923 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .A1(n6241), .B0(n6261), .B1(d_ff3_sh_x_out[23]), .Y(n6237) );
NAND2X1TS U7924 ( .A(n6238), .B(n6237), .Y(n2679) );
INVX2TS U7925 ( .A(n6239), .Y(n6259) );
AOI22X1TS U7926 ( .A0(n6268), .A1(d_ff3_sh_y_out[24]), .B0(n6240), .B1(
d_ff3_sh_x_out[24]), .Y(n6243) );
AOI22X1TS U7927 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .A1(n6241), .B0(n6262), .B1(d_ff3_LUT_out[24]), .Y(n6242) );
NAND2X1TS U7928 ( .A(n6243), .B(n6242), .Y(n2676) );
AOI22X1TS U7929 ( .A0(n6428), .A1(d_ff3_sh_x_out[25]), .B0(n6262), .B1(
d_ff3_LUT_out[25]), .Y(n6245) );
CLKINVX3TS U7930 ( .A(n6460), .Y(n6278) );
AOI22X1TS U7931 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .A1(n6278), .B0(n6446), .B1(d_ff3_sh_y_out[25]), .Y(n6244) );
NAND2X1TS U7932 ( .A(n6245), .B(n6244), .Y(n2673) );
AOI22X1TS U7933 ( .A0(d_ff3_LUT_out[26]), .A1(n6447), .B0(n6261), .B1(
d_ff3_sh_x_out[26]), .Y(n6248) );
AOI22X1TS U7934 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .A1(n6278), .B0(n6420), .B1(d_ff3_sh_y_out[26]), .Y(n6247) );
NAND2X1TS U7935 ( .A(n6248), .B(n6247), .Y(n2670) );
AOI22X1TS U7936 ( .A0(n6250), .A1(d_ff3_sh_y_out[27]), .B0(n6261), .B1(
d_ff3_sh_x_out[27]), .Y(n6252) );
AOI22X1TS U7937 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .A1(n6278), .B0(n6298), .B1(d_ff3_LUT_out[27]), .Y(n6251) );
NAND2X1TS U7938 ( .A(n6252), .B(n6251), .Y(n2667) );
AOI22X1TS U7939 ( .A0(n6428), .A1(d_ff3_sh_x_out[29]), .B0(n6262), .B1(
d_ff3_LUT_out[29]), .Y(n6255) );
AOI22X1TS U7940 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .A1(n6278), .B0(n6420), .B1(d_ff3_sh_y_out[29]), .Y(n6254) );
NAND2X1TS U7941 ( .A(n6255), .B(n6254), .Y(n2661) );
INVX2TS U7942 ( .A(n6256), .Y(n6290) );
AOI22X1TS U7943 ( .A0(n6268), .A1(d_ff3_sh_y_out[31]), .B0(n6261), .B1(
d_ff3_sh_x_out[31]), .Y(n6258) );
AOI22X1TS U7944 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .A1(n6278), .B0(n6262), .B1(d_ff3_LUT_out[31]), .Y(n6257) );
NAND2X1TS U7945 ( .A(n6258), .B(n6257), .Y(n2655) );
INVX2TS U7946 ( .A(n6260), .Y(n6281) );
AOI22X1TS U7947 ( .A0(n6275), .A1(d_ff3_sh_y_out[33]), .B0(n6261), .B1(
d_ff3_sh_x_out[33]), .Y(n6264) );
AOI22X1TS U7948 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .A1(n6278), .B0(n6262), .B1(d_ff3_LUT_out[33]), .Y(n6263) );
NAND2X1TS U7949 ( .A(n6264), .B(n6263), .Y(n2649) );
INVX2TS U7950 ( .A(n6265), .Y(n6286) );
AOI22X1TS U7951 ( .A0(n6268), .A1(d_ff3_sh_y_out[35]), .B0(n6283), .B1(
d_ff3_sh_x_out[35]), .Y(n6270) );
AOI22X1TS U7952 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .A1(n6278), .B0(n6298), .B1(d_ff3_LUT_out[35]), .Y(n6269) );
NAND2X1TS U7953 ( .A(n6270), .B(n6269), .Y(n2643) );
BUFX3TS U7954 ( .A(n6271), .Y(n6282) );
AOI22X1TS U7955 ( .A0(n6275), .A1(d_ff3_sh_y_out[37]), .B0(n6283), .B1(
d_ff3_sh_x_out[37]), .Y(n6273) );
AOI22X1TS U7956 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[37]), .A1(n6278), .B0(n6298), .B1(d_ff3_LUT_out[37]), .Y(n6272) );
NAND2X1TS U7957 ( .A(n6273), .B(n6272), .Y(n2637) );
AOI22X1TS U7958 ( .A0(n6275), .A1(d_ff3_sh_y_out[39]), .B0(n6283), .B1(
d_ff3_sh_x_out[39]), .Y(n6277) );
AOI22X1TS U7959 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .A1(n6278), .B0(n6298), .B1(d_ff3_LUT_out[39]), .Y(n6276) );
NAND2X1TS U7960 ( .A(n6277), .B(n6276), .Y(n2631) );
AOI22X1TS U7961 ( .A0(n6364), .A1(d_ff3_sh_y_out[41]), .B0(n6283), .B1(
d_ff3_sh_x_out[41]), .Y(n6280) );
AOI22X1TS U7962 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .A1(n6278), .B0(n6298), .B1(d_ff3_LUT_out[41]), .Y(n6279) );
NAND2X1TS U7963 ( .A(n6280), .B(n6279), .Y(n2625) );
AOI22X1TS U7964 ( .A0(n6364), .A1(d_ff3_sh_y_out[45]), .B0(n6283), .B1(
d_ff3_sh_x_out[45]), .Y(n6285) );
AOI22X1TS U7965 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]), .A1(n6334), .B0(n6298), .B1(d_ff3_LUT_out[45]), .Y(n6284) );
NAND2X1TS U7966 ( .A(n6285), .B(n6284), .Y(n2613) );
AOI22X1TS U7967 ( .A0(n6407), .A1(d_ff3_sh_x_out[50]), .B0(n6298), .B1(
d_ff3_LUT_out[50]), .Y(n6288) );
AOI22X1TS U7968 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .A1(n6334), .B0(n6446), .B1(d_ff3_sh_y_out[50]), .Y(n6287) );
NAND2X1TS U7969 ( .A(n6288), .B(n6287), .Y(n2598) );
AOI22X1TS U7970 ( .A0(n3901), .A1(d_ff3_sh_y_out[52]), .B0(n6298), .B1(
d_ff3_LUT_out[52]), .Y(n6297) );
AOI22X1TS U7971 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .A1(n6334), .B0(n6301), .B1(d_ff3_sh_x_out[52]), .Y(n6296) );
NAND2X1TS U7972 ( .A(n6297), .B(n6296), .Y(n2582) );
AOI22X1TS U7973 ( .A0(n6343), .A1(d_ff3_sh_y_out[53]), .B0(n6301), .B1(
d_ff3_sh_x_out[53]), .Y(n6300) );
AOI22X1TS U7974 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .A1(n6334), .B0(n6298), .B1(d_ff3_LUT_out[53]), .Y(n6299) );
NAND2X1TS U7975 ( .A(n6300), .B(n6299), .Y(n2580) );
AOI22X1TS U7976 ( .A0(n6343), .A1(d_ff3_sh_y_out[54]), .B0(n6301), .B1(
d_ff3_sh_x_out[54]), .Y(n6303) );
AOI22X1TS U7977 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .A1(n6334), .B0(n6344), .B1(d_ff3_LUT_out[54]), .Y(n6302) );
NAND2X1TS U7978 ( .A(n6303), .B(n6302), .Y(n2578) );
AOI22X1TS U7979 ( .A0(n6451), .A1(d_ff3_sh_x_out[55]), .B0(n6344), .B1(
d_ff3_LUT_out[55]), .Y(n6305) );
AOI22X1TS U7980 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .A1(n6334), .B0(n6446), .B1(d_ff3_sh_y_out[55]), .Y(n6304) );
NAND2X1TS U7981 ( .A(n6305), .B(n6304), .Y(n2576) );
NOR2X1TS U7982 ( .A(d_ff2_Y[56]), .B(intadd_45_n1), .Y(n6309) );
AOI21X1TS U7983 ( .A0(intadd_45_n1), .A1(d_ff2_Y[56]), .B0(n6309), .Y(n6306)
);
AOI22X1TS U7984 ( .A0(n6407), .A1(d_ff3_sh_x_out[56]), .B0(n6344), .B1(
d_ff3_LUT_out[56]), .Y(n6308) );
AOI22X1TS U7985 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .A1(n6334), .B0(n6398), .B1(d_ff3_sh_y_out[56]), .Y(n6307) );
NAND2X1TS U7986 ( .A(n6308), .B(n6307), .Y(n2574) );
INVX2TS U7987 ( .A(n6309), .Y(n6310) );
AOI21X1TS U7988 ( .A0(d_ff2_Y[57]), .A1(n6310), .B0(n6313), .Y(n6312) );
NOR2X2TS U7989 ( .A(d_ff2_Y[59]), .B(n6316), .Y(n6318) );
AOI21X1TS U7990 ( .A0(d_ff2_Y[59]), .A1(n6316), .B0(n6318), .Y(n6317) );
NAND2X1TS U7991 ( .A(n6318), .B(n6752), .Y(n6320) );
NOR2X1TS U7992 ( .A(d_ff2_Y[61]), .B(n6320), .Y(n6324) );
AOI21X1TS U7993 ( .A0(n3255), .A1(n6320), .B0(n6324), .Y(n6322) );
XOR2X1TS U7994 ( .A(n3232), .B(n6324), .Y(n6325) );
INVX2TS U7995 ( .A(n6044), .Y(n6331) );
INVX2TS U7996 ( .A(n6330), .Y(n6461) );
INVX2TS U7997 ( .A(n6466), .Y(n6465) );
AOI22X1TS U7998 ( .A0(n6407), .A1(d_ff2_Y[0]), .B0(n6344), .B1(d_ff2_Z[0]),
.Y(n6333) );
AOI22X1TS U7999 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[0]), .A1(n6334),
.B0(n6398), .B1(d_ff2_X[0]), .Y(n6332) );
NAND2X1TS U8000 ( .A(n6333), .B(n6332), .Y(n2473) );
AOI22X1TS U8001 ( .A0(n6407), .A1(d_ff2_Y[1]), .B0(n6344), .B1(d_ff2_Z[1]),
.Y(n6336) );
AOI22X1TS U8002 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[1]), .A1(n6334),
.B0(n6446), .B1(d_ff2_X[1]), .Y(n6335) );
NAND2X1TS U8003 ( .A(n6336), .B(n6335), .Y(n2471) );
AOI22X1TS U8004 ( .A0(n3901), .A1(d_ff2_X[2]), .B0(n6349), .B1(d_ff2_Y[2]),
.Y(n6338) );
CLKINVX3TS U8005 ( .A(n6460), .Y(n6404) );
AOI22X1TS U8006 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[2]), .A1(n6404),
.B0(n6344), .B1(d_ff2_Z[2]), .Y(n6337) );
NAND2X1TS U8007 ( .A(n6338), .B(n6337), .Y(n2469) );
AOI22X1TS U8008 ( .A0(n6236), .A1(d_ff2_X[3]), .B0(n6349), .B1(d_ff2_Y[3]),
.Y(n6340) );
AOI22X1TS U8009 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[3]), .A1(n6404),
.B0(n6344), .B1(d_ff2_Z[3]), .Y(n6339) );
NAND2X1TS U8010 ( .A(n6340), .B(n6339), .Y(n2467) );
AOI22X1TS U8011 ( .A0(n6407), .A1(d_ff2_Y[4]), .B0(n6344), .B1(d_ff2_Z[4]),
.Y(n6342) );
AOI22X1TS U8012 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .A1(n6404),
.B0(n6398), .B1(d_ff2_X[4]), .Y(n6341) );
NAND2X1TS U8013 ( .A(n6342), .B(n6341), .Y(n2465) );
AOI22X1TS U8014 ( .A0(n6343), .A1(d_ff2_X[5]), .B0(n6344), .B1(d_ff2_Z[5]),
.Y(n6346) );
AOI22X1TS U8015 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[5]), .A1(n6404),
.B0(n6349), .B1(d_ff2_Y[5]), .Y(n6345) );
NAND2X1TS U8016 ( .A(n6346), .B(n6345), .Y(n2463) );
AOI22X1TS U8017 ( .A0(n6182), .A1(d_ff2_X[6]), .B0(n6349), .B1(d_ff2_Y[6]),
.Y(n6348) );
BUFX3TS U8018 ( .A(n6387), .Y(n6450) );
AOI22X1TS U8019 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[6]), .A1(n6404),
.B0(n6450), .B1(d_ff2_Z[6]), .Y(n6347) );
NAND2X1TS U8020 ( .A(n6348), .B(n6347), .Y(n2461) );
AOI22X1TS U8021 ( .A0(n6182), .A1(d_ff2_X[7]), .B0(n6450), .B1(d_ff2_Z[7]),
.Y(n6351) );
AOI22X1TS U8022 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[7]), .A1(n6404),
.B0(n6349), .B1(d_ff2_Y[7]), .Y(n6350) );
NAND2X1TS U8023 ( .A(n6351), .B(n6350), .Y(n2459) );
AOI22X1TS U8024 ( .A0(n6182), .A1(d_ff2_X[8]), .B0(n6371), .B1(d_ff2_Y[8]),
.Y(n6353) );
AOI22X1TS U8025 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[8]), .A1(n6404),
.B0(n6450), .B1(d_ff2_Z[8]), .Y(n6352) );
NAND2X1TS U8026 ( .A(n6353), .B(n6352), .Y(n2457) );
AOI22X1TS U8027 ( .A0(n6182), .A1(d_ff2_X[9]), .B0(n6450), .B1(d_ff2_Z[9]),
.Y(n6355) );
AOI22X1TS U8028 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .A1(n6404),
.B0(n6371), .B1(d_ff2_Y[9]), .Y(n6354) );
NAND2X1TS U8029 ( .A(n6355), .B(n6354), .Y(n2455) );
AOI22X1TS U8030 ( .A0(n6428), .A1(d_ff2_Y[10]), .B0(n6450), .B1(d_ff2_Z[10]),
.Y(n6357) );
AOI22X1TS U8031 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[10]), .A1(n6404), .B0(n6398), .B1(d_ff2_X[10]), .Y(n6356) );
NAND2X1TS U8032 ( .A(n6357), .B(n6356), .Y(n2453) );
AOI22X1TS U8033 ( .A0(n6182), .A1(d_ff2_X[11]), .B0(n6376), .B1(d_ff2_Y[11]),
.Y(n6359) );
CLKINVX3TS U8034 ( .A(n6460), .Y(n6380) );
AOI22X1TS U8035 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[11]), .A1(n6380), .B0(n6450), .B1(d_ff2_Z[11]), .Y(n6358) );
NAND2X1TS U8036 ( .A(n6359), .B(n6358), .Y(n2451) );
AOI22X1TS U8037 ( .A0(n6343), .A1(d_ff2_X[12]), .B0(n6450), .B1(d_ff2_Z[12]),
.Y(n6361) );
AOI22X1TS U8038 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[12]), .A1(n6380), .B0(n6371), .B1(d_ff2_Y[12]), .Y(n6360) );
NAND2X1TS U8039 ( .A(n6361), .B(n6360), .Y(n2449) );
AOI22X1TS U8040 ( .A0(n6343), .A1(d_ff2_X[13]), .B0(n6376), .B1(d_ff2_Y[13]),
.Y(n6363) );
AOI22X1TS U8041 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[13]), .A1(n6380), .B0(n6450), .B1(d_ff2_Z[13]), .Y(n6362) );
NAND2X1TS U8042 ( .A(n6363), .B(n6362), .Y(n2447) );
AOI22X1TS U8043 ( .A0(n6364), .A1(d_ff2_X[14]), .B0(n6450), .B1(d_ff2_Z[14]),
.Y(n6366) );
AOI22X1TS U8044 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[14]), .A1(n6380), .B0(n6371), .B1(d_ff2_Y[14]), .Y(n6365) );
NAND2X1TS U8045 ( .A(n6366), .B(n6365), .Y(n2445) );
AOI22X1TS U8046 ( .A0(n6343), .A1(d_ff2_X[15]), .B0(n6376), .B1(d_ff2_Y[15]),
.Y(n6368) );
AOI22X1TS U8047 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[15]), .A1(n6380), .B0(n6377), .B1(d_ff2_Z[15]), .Y(n6367) );
NAND2X1TS U8048 ( .A(n6368), .B(n6367), .Y(n2443) );
AOI22X1TS U8049 ( .A0(n6343), .A1(d_ff2_X[16]), .B0(n6403), .B1(d_ff2_Y[16]),
.Y(n6370) );
AOI22X1TS U8050 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[16]), .A1(n6380), .B0(n6377), .B1(d_ff2_Z[16]), .Y(n6369) );
NAND2X1TS U8051 ( .A(n6370), .B(n6369), .Y(n2441) );
AOI22X1TS U8052 ( .A0(n6390), .A1(d_ff2_X[17]), .B0(n6371), .B1(d_ff2_Y[17]),
.Y(n6373) );
AOI22X1TS U8053 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[17]), .A1(n6380), .B0(n6387), .B1(d_ff2_Z[17]), .Y(n6372) );
NAND2X1TS U8054 ( .A(n6373), .B(n6372), .Y(n2439) );
AOI22X1TS U8055 ( .A0(n6390), .A1(d_ff2_X[18]), .B0(n6403), .B1(d_ff2_Y[18]),
.Y(n6375) );
AOI22X1TS U8056 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[18]), .A1(n6380), .B0(n6387), .B1(d_ff2_Z[18]), .Y(n6374) );
NAND2X1TS U8057 ( .A(n6375), .B(n6374), .Y(n2437) );
AOI22X1TS U8058 ( .A0(n6390), .A1(d_ff2_X[19]), .B0(n6376), .B1(d_ff2_Y[19]),
.Y(n6379) );
AOI22X1TS U8059 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[19]), .A1(n6380), .B0(n6377), .B1(d_ff2_Z[19]), .Y(n6378) );
NAND2X1TS U8060 ( .A(n6379), .B(n6378), .Y(n2435) );
AOI22X1TS U8061 ( .A0(n6390), .A1(d_ff2_X[20]), .B0(n6403), .B1(d_ff2_Y[20]),
.Y(n6382) );
AOI22X1TS U8062 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[20]), .A1(n6380), .B0(n6387), .B1(d_ff2_Z[20]), .Y(n6381) );
NAND2X1TS U8063 ( .A(n6382), .B(n6381), .Y(n2433) );
AOI22X1TS U8064 ( .A0(n6390), .A1(d_ff2_X[21]), .B0(n6403), .B1(d_ff2_Y[21]),
.Y(n6384) );
AOI22X1TS U8065 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[21]), .A1(n6393), .B0(n6387), .B1(d_ff2_Z[21]), .Y(n6383) );
NAND2X1TS U8066 ( .A(n6384), .B(n6383), .Y(n2431) );
AOI22X1TS U8067 ( .A0(n6390), .A1(d_ff2_X[22]), .B0(n6387), .B1(d_ff2_Z[22]),
.Y(n6386) );
AOI22X1TS U8068 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[22]), .A1(n6393), .B0(n6403), .B1(d_ff2_Y[22]), .Y(n6385) );
NAND2X1TS U8069 ( .A(n6386), .B(n6385), .Y(n2429) );
AOI22X1TS U8070 ( .A0(n6451), .A1(d_ff2_Y[24]), .B0(n6387), .B1(d_ff2_Z[24]),
.Y(n6389) );
AOI22X1TS U8071 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[24]), .A1(n6393), .B0(n6398), .B1(d_ff2_X[24]), .Y(n6388) );
NAND2X1TS U8072 ( .A(n6389), .B(n6388), .Y(n2425) );
AOI22X1TS U8073 ( .A0(n6390), .A1(d_ff2_X[27]), .B0(n3903), .B1(d_ff2_Z[27]),
.Y(n6392) );
AOI22X1TS U8074 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[27]), .A1(n6393), .B0(n6431), .B1(d_ff2_Y[27]), .Y(n6391) );
NAND2X1TS U8075 ( .A(n6392), .B(n6391), .Y(n2419) );
AOI22X1TS U8076 ( .A0(n6407), .A1(d_ff2_Y[29]), .B0(n3903), .B1(d_ff2_Z[29]),
.Y(n6395) );
AOI22X1TS U8077 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[29]), .A1(n6393), .B0(n6398), .B1(d_ff2_X[29]), .Y(n6394) );
NAND2X1TS U8078 ( .A(n6395), .B(n6394), .Y(n2415) );
AOI22X1TS U8079 ( .A0(n6428), .A1(d_ff2_Y[33]), .B0(n3903), .B1(d_ff2_Z[33]),
.Y(n6397) );
AOI22X1TS U8080 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[33]), .A1(n6410), .B0(n6398), .B1(d_ff2_X[33]), .Y(n6396) );
NAND2X1TS U8081 ( .A(n6397), .B(n6396), .Y(n2407) );
AOI22X1TS U8082 ( .A0(n6428), .A1(d_ff2_Y[35]), .B0(n6377), .B1(d_ff2_Z[35]),
.Y(n6400) );
AOI22X1TS U8083 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[35]), .A1(n6410), .B0(n6398), .B1(d_ff2_X[35]), .Y(n6399) );
NAND2X1TS U8084 ( .A(n6400), .B(n6399), .Y(n2403) );
AOI22X1TS U8085 ( .A0(n6407), .A1(d_ff2_Y[36]), .B0(n4043), .B1(d_ff2_Z[36]),
.Y(n6402) );
AOI22X1TS U8086 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[36]), .A1(n6410), .B0(n6420), .B1(d_ff2_X[36]), .Y(n6401) );
NAND2X1TS U8087 ( .A(n6402), .B(n6401), .Y(n2401) );
AOI22X1TS U8088 ( .A0(n6413), .A1(d_ff2_X[37]), .B0(n4043), .B1(d_ff2_Z[37]),
.Y(n6406) );
AOI22X1TS U8089 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[37]), .A1(n6404), .B0(n6403), .B1(d_ff2_Y[37]), .Y(n6405) );
NAND2X1TS U8090 ( .A(n6406), .B(n6405), .Y(n2399) );
AOI22X1TS U8091 ( .A0(n6407), .A1(d_ff2_Y[38]), .B0(n6232), .B1(d_ff2_Z[38]),
.Y(n6409) );
AOI22X1TS U8092 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[38]), .A1(n6410), .B0(n6420), .B1(d_ff2_X[38]), .Y(n6408) );
NAND2X1TS U8093 ( .A(n6409), .B(n6408), .Y(n2397) );
AOI22X1TS U8094 ( .A0(n6413), .A1(d_ff2_X[40]), .B0(n6232), .B1(d_ff2_Z[40]),
.Y(n6412) );
AOI22X1TS U8095 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[40]), .A1(n6410), .B0(n6218), .B1(d_ff2_Y[40]), .Y(n6411) );
NAND2X1TS U8096 ( .A(n6412), .B(n6411), .Y(n2393) );
AOI22X1TS U8097 ( .A0(n6413), .A1(d_ff2_X[42]), .B0(n6377), .B1(d_ff2_Z[42]),
.Y(n6415) );
AOI22X1TS U8098 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[42]), .A1(n6425), .B0(n6431), .B1(d_ff2_Y[42]), .Y(n6414) );
NAND2X1TS U8099 ( .A(n6415), .B(n6414), .Y(n2389) );
AOI22X1TS U8100 ( .A0(n6428), .A1(d_ff2_Y[44]), .B0(n6232), .B1(d_ff2_Z[44]),
.Y(n6417) );
AOI22X1TS U8101 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[44]), .A1(n6425), .B0(n6452), .B1(d_ff2_X[44]), .Y(n6416) );
NAND2X1TS U8102 ( .A(n6417), .B(n6416), .Y(n2385) );
AOI22X1TS U8103 ( .A0(n6434), .A1(d_ff2_X[47]), .B0(n6443), .B1(d_ff2_Z[47]),
.Y(n6419) );
AOI22X1TS U8104 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[47]), .A1(n6425), .B0(n6218), .B1(d_ff2_Y[47]), .Y(n6418) );
NAND2X1TS U8105 ( .A(n6419), .B(n6418), .Y(n2379) );
AOI22X1TS U8106 ( .A0(n6428), .A1(d_ff2_Y[49]), .B0(n6443), .B1(d_ff2_Z[49]),
.Y(n6422) );
AOI22X1TS U8107 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[49]), .A1(n6425), .B0(n6420), .B1(d_ff2_X[49]), .Y(n6421) );
NAND2X1TS U8108 ( .A(n6422), .B(n6421), .Y(n2375) );
AOI22X1TS U8109 ( .A0(n6434), .A1(d_ff2_X[50]), .B0(n6443), .B1(d_ff2_Z[50]),
.Y(n6424) );
AOI22X1TS U8110 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[50]), .A1(n6425), .B0(n6218), .B1(d_ff2_Y[50]), .Y(n6423) );
NAND2X1TS U8111 ( .A(n6424), .B(n6423), .Y(n2373) );
AOI22X1TS U8112 ( .A0(n6434), .A1(n3251), .B0(n6443), .B1(d_ff2_Z[51]), .Y(
n6427) );
AOI22X1TS U8113 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[51]), .A1(n6425), .B0(n6431), .B1(n3249), .Y(n6426) );
NAND2X1TS U8114 ( .A(n6427), .B(n6426), .Y(n2371) );
AOI22X1TS U8115 ( .A0(n6428), .A1(d_ff2_Y[52]), .B0(n6443), .B1(d_ff2_Z[52]),
.Y(n6430) );
AOI22X1TS U8116 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[52]), .A1(n6453), .B0(n6452), .B1(d_ff2_X[52]), .Y(n6429) );
NAND2X1TS U8117 ( .A(n6430), .B(n6429), .Y(n2369) );
AOI22X1TS U8118 ( .A0(n6434), .A1(d_ff2_X[53]), .B0(n6447), .B1(d_ff2_Z[53]),
.Y(n6433) );
AOI22X1TS U8119 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[53]), .A1(n6453), .B0(n6431), .B1(d_ff2_Y[53]), .Y(n6432) );
NAND2X1TS U8120 ( .A(n6433), .B(n6432), .Y(n2367) );
AOI22X1TS U8121 ( .A0(n6434), .A1(d_ff2_X[55]), .B0(n6447), .B1(d_ff2_Z[55]),
.Y(n6436) );
AOI22X1TS U8122 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[55]), .A1(n6453), .B0(n6218), .B1(d_ff2_Y[55]), .Y(n6435) );
NAND2X1TS U8123 ( .A(n6436), .B(n6435), .Y(n2363) );
AOI22X1TS U8124 ( .A0(n6451), .A1(d_ff2_Y[56]), .B0(n6447), .B1(d_ff2_Z[56]),
.Y(n6438) );
AOI22X1TS U8125 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[56]), .A1(n6453), .B0(d_ff2_X[56]), .B1(n6452), .Y(n6437) );
NAND2X1TS U8126 ( .A(n6438), .B(n6437), .Y(n2361) );
AOI22X1TS U8127 ( .A0(n6451), .A1(d_ff2_Y[57]), .B0(n6447), .B1(d_ff2_Z[57]),
.Y(n6440) );
AOI22X1TS U8128 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[57]), .A1(n6453), .B0(d_ff2_X[57]), .B1(n6452), .Y(n6439) );
NAND2X1TS U8129 ( .A(n6440), .B(n6439), .Y(n2359) );
AOI22X1TS U8130 ( .A0(d_ff2_X[58]), .A1(n6446), .B0(n6447), .B1(d_ff2_Z[58]),
.Y(n6442) );
AOI22X1TS U8131 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[58]), .A1(n6453), .B0(n6201), .B1(d_ff2_Y[58]), .Y(n6441) );
NAND2X1TS U8132 ( .A(n6442), .B(n6441), .Y(n2357) );
AOI22X1TS U8133 ( .A0(d_ff2_X[59]), .A1(n6446), .B0(n6443), .B1(d_ff2_Z[59]),
.Y(n6445) );
AOI22X1TS U8134 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[59]), .A1(n6453), .B0(n6201), .B1(d_ff2_Y[59]), .Y(n6444) );
NAND2X1TS U8135 ( .A(n6445), .B(n6444), .Y(n2355) );
AOI22X1TS U8136 ( .A0(d_ff2_X[60]), .A1(n6446), .B0(n6197), .B1(d_ff2_Y[60]),
.Y(n6449) );
AOI22X1TS U8137 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[60]), .A1(n6453), .B0(n6447), .B1(d_ff2_Z[60]), .Y(n6448) );
NAND2X1TS U8138 ( .A(n6449), .B(n6448), .Y(n2353) );
AOI22X1TS U8139 ( .A0(n6451), .A1(n3255), .B0(n6450), .B1(d_ff2_Z[61]), .Y(
n6455) );
AOI22X1TS U8140 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]), .A1(n6453), .B0(n3235), .B1(n6452), .Y(n6454) );
NAND2X1TS U8141 ( .A(n6455), .B(n6454), .Y(n2351) );
AOI2BB2XLTS U8142 ( .B0(cont_var_out[0]), .B1(d_ff3_sign_out), .A0N(
d_ff3_sign_out), .A1N(cont_var_out[0]), .Y(n6459) );
AOI22X1TS U8143 ( .A0(n6468), .A1(d_ff_Xn[63]), .B0(d_ff_Yn[63]), .B1(n6467),
.Y(n6470) );
XNOR2X1TS U8144 ( .A(n6470), .B(n6469), .Y(n6471) );
CLKBUFX2TS U8145 ( .A(n6763), .Y(n6586) );
CLKBUFX2TS U8146 ( .A(n6586), .Y(n6565) );
INVX2TS U8147 ( .A(n6595), .Y(n6576) );
OA21XLTS U8148 ( .A0(n6846), .A1(underflow_flag), .B0(n6479), .Y(n2185) );
BUFX3TS U8149 ( .A(n6584), .Y(n6481) );
INVX2TS U8150 ( .A(n6565), .Y(n6482) );
BUFX3TS U8151 ( .A(n6584), .Y(n6563) );
INVX2TS U8152 ( .A(n6565), .Y(n6564) );
BUFX3TS U8153 ( .A(n6565), .Y(n6568) );
CLKXOR2X2TS U8154 ( .A(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[63]), .B(
inst_FPU_PIPELINED_FPADDSUB_intAS), .Y(n6562) );
AOI22X1TS U8155 ( .A0(n6612), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[3]),
.B0(n6693), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[62]), .Y(n6483)
);
AOI221X1TS U8156 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[9]), .A1(n6696), .B0(n6663), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[9]), .C0(n6484), .Y(
n6498) );
OAI22X1TS U8157 ( .A0(n6633), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[50]), .B0(n6625), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[41]), .Y(n6485) );
OAI22X1TS U8158 ( .A0(n6632), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[51]), .B0(n6661), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[32]), .Y(n6486) );
AOI221X1TS U8159 ( .A0(n6632), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[51]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[32]), .B1(n6661), .C0(n6486),
.Y(n6496) );
AOI22X1TS U8160 ( .A0(n6609), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[20]), .B0(n6647), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[58]), .Y(n6487) );
AOI22X1TS U8161 ( .A0(n6602), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[29]), .B0(n6607), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[31]), .Y(n6488) );
AOI22X1TS U8162 ( .A0(n6599), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[42]), .B0(n6682), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[40]), .Y(n6489) );
AOI22X1TS U8163 ( .A0(n6606), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[26]), .B0(n6604), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[25]), .Y(n6490) );
NOR4X1TS U8164 ( .A(n6494), .B(n6493), .C(n6492), .D(n6491), .Y(n6495) );
OAI22X1TS U8165 ( .A0(n6622), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[23]), .B0(n6613), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[4]), .Y(n6499) );
OAI22X1TS U8166 ( .A0(n6618), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .B0(n6628), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .Y(n6500) );
AOI221X1TS U8167 ( .A0(n6618), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[21]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[33]), .B1(n6628), .C0(n6500),
.Y(n6505) );
OAI22X1TS U8168 ( .A0(n6658), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[1]),
.B0(n6630), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[53]), .Y(n6501)
);
OAI22X1TS U8169 ( .A0(n6629), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[35]), .B0(n6656), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[0]), .Y(n6502) );
OAI22X1TS U8170 ( .A0(n6659), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[37]), .B0(n6627), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[36]), .Y(n6507) );
AOI221X1TS U8171 ( .A0(n6659), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[37]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[36]), .B1(n6627), .C0(n6507),
.Y(n6514) );
OAI22X1TS U8172 ( .A0(n6694), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[44]), .B0(n6616), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[8]), .Y(n6508) );
OAI22X1TS U8173 ( .A0(n6657), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .B0(n6598), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[46]), .Y(n6509) );
AOI221X1TS U8174 ( .A0(n6657), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[16]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[46]), .B1(n6598), .C0(n6509),
.Y(n6512) );
OAI22X1TS U8175 ( .A0(n6596), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .B0(n6660), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[48]), .Y(n6510) );
AOI221X1TS U8176 ( .A0(n6596), .A1(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[54]), .B0(
inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[48]), .B1(n6660), .C0(n6510),
.Y(n6511) );
AOI22X1TS U8177 ( .A0(n6680), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[38]), .B0(n6650), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[56]), .Y(n6515) );
AOI22X1TS U8178 ( .A0(n6646), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[39]), .B0(n6610), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[14]), .Y(n6516) );
AOI22X1TS U8179 ( .A0(n6619), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[17]), .B0(n6648), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[60]), .Y(n6517) );
AOI22X1TS U8180 ( .A0(n6623), .A1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[61]), .B0(n6677), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[10]), .Y(n6518) );
NOR4X1TS U8181 ( .A(n6522), .B(n6521), .C(n6520), .D(n6519), .Y(n6550) );
AOI22X1TS U8182 ( .A0(n6605), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[27]), .B0(n6617), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[15]), .Y(n6523) );
AOI22X1TS U8183 ( .A0(n6603), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[28]), .B0(n6643), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[57]), .Y(n6524) );
AOI22X1TS U8184 ( .A0(n6600), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[34]), .B0(n6681), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[47]), .Y(n6525) );
AOI22X1TS U8185 ( .A0(n6626), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[43]), .B0(n6649), .B1(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[59]), .Y(n6526) );
NOR4X1TS U8186 ( .A(n6530), .B(n6529), .C(n6528), .D(n6527), .Y(n6549) );
AOI22X1TS U8187 ( .A0(n6645), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[2]),
.B0(n6679), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[7]), .Y(n6531)
);
AOI22X1TS U8188 ( .A0(n6620), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[19]), .B0(n6621), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[18]), .Y(n6532) );
AOI22X1TS U8189 ( .A0(n6685), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[52]), .B0(n6608), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[22]), .Y(n6533) );
AOI22X1TS U8190 ( .A0(n6615), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[11]), .B0(n6678), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[6]), .Y(n6534) );
NOR4X1TS U8191 ( .A(n6538), .B(n6537), .C(n6536), .D(n6535), .Y(n6548) );
AOI22X1TS U8192 ( .A0(n6631), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[49]), .B0(n6651), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[5]), .Y(n6539) );
AOI22X1TS U8193 ( .A0(n6611), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[12]), .B0(n6601), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[30]), .Y(n6540) );
AOI22X1TS U8194 ( .A0(n6634), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[55]), .B0(n6614), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[13]), .Y(n6541) );
AOI22X1TS U8195 ( .A0(n6644), .A1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[24]), .B0(n6624), .B1(inst_FPU_PIPELINED_FPADDSUB_intDY_EWSW[45]), .Y(n6542) );
NOR4X1TS U8196 ( .A(n6546), .B(n6545), .C(n6544), .D(n6543), .Y(n6547) );
NOR4X1TS U8197 ( .A(n6554), .B(n6553), .C(n6552), .D(n6551), .Y(n6573) );
OAI211XLTS U8198 ( .A0(n6556), .A1(n6562), .B0(
inst_FPU_PIPELINED_FPADDSUB_Shift_reg_FLAGS_7_6), .C0(n6555), .Y(n6557) );
OAI2BB1X1TS U8199 ( .A0N(inst_FPU_PIPELINED_FPADDSUB_SIGN_FLAG_EXP), .A1N(
n6572), .B0(n6557), .Y(n2093) );
INVX2TS U8200 ( .A(n6562), .Y(n6561) );
AOI221X1TS U8201 ( .A0(inst_FPU_PIPELINED_FPADDSUB_intDX_EWSW[63]), .A1(
n6562), .B0(n6765), .B1(n6561), .C0(n6560), .Y(n6574) );
AO21XLTS U8202 ( .A0(inst_FPU_PIPELINED_FPADDSUB_OP_FLAG_EXP), .A1(n6572),
.B0(n6574), .Y(n2086) );
INVX2TS U8203 ( .A(n6595), .Y(n6589) );
BUFX3TS U8204 ( .A(n6586), .Y(n6566) );
INVX2TS U8205 ( .A(n6565), .Y(n6567) );
BUFX3TS U8206 ( .A(n6763), .Y(n6570) );
BUFX3TS U8207 ( .A(n6763), .Y(n6571) );
AO22XLTS U8208 ( .A0(n5056), .A1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_NRM),
.B0(n5203), .B1(inst_FPU_PIPELINED_FPADDSUB_ZERO_FLAG_SHT1SHT2), .Y(
n1862) );
INVX2TS U8209 ( .A(n6586), .Y(n6582) );
BUFX3TS U8210 ( .A(n6584), .Y(n6583) );
INVX2TS U8211 ( .A(n6586), .Y(n6585) );
BUFX3TS U8212 ( .A(n6595), .Y(n6587) );
BUFX3TS U8213 ( .A(n6584), .Y(n6588) );
INVX2TS U8214 ( .A(n6586), .Y(n6594) );
initial $sdf_annotate("CORDIC_Arch3_syn.sdf");
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module limbus_nios2_qsys_0_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
limbus_nios2_qsys_0_jtag_debug_module_tck the_limbus_nios2_qsys_0_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
limbus_nios2_qsys_0_jtag_debug_module_sysclk the_limbus_nios2_qsys_0_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic limbus_nios2_qsys_0_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam limbus_nios2_qsys_0_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// limbus_nios2_qsys_0_jtag_debug_module_phy.sld_instance_index = 0,
// limbus_nios2_qsys_0_jtag_debug_module_phy.sld_ir_width = 2,
// limbus_nios2_qsys_0_jtag_debug_module_phy.sld_mfg_id = 70,
// limbus_nios2_qsys_0_jtag_debug_module_phy.sld_sim_action = "",
// limbus_nios2_qsys_0_jtag_debug_module_phy.sld_sim_n_scan = 0,
// limbus_nios2_qsys_0_jtag_debug_module_phy.sld_sim_total_length = 0,
// limbus_nios2_qsys_0_jtag_debug_module_phy.sld_type_id = 34,
// limbus_nios2_qsys_0_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
/*88888888 8888888 8888888888 .d88888b. .d8888b. 8888888b. 8888888
888 888 888 d88P" "Y88b d88P Y88b 888 Y88b 888
888 888 888 888 888 Y88b. 888 888 888
8888888 888 8888888 888 888 "Y888b. 888 d88P 888
888 888 888 888 888 "Y88b. 8888888P" 888
888 888 888 888 888 "888 888 888
888 888 888 Y88b. .d88P Y88b d88P 888 888
888 8888888 888 "Y88888P" 88888888 "Y8888P" 888 88888*/
/////////////////////////////////////////////////////////////////////
// This module realise the connexion and control between a fifo
// and a SPI module.
// workflow: It accepts 32 bits data in, and store them in a fifo.
// at the moment the fifo reach 255 data in, the spi module start
// to output these 255 data plus 1 word (end frame data).
//
// FUTURE WORK: Implement a SPI block signal that will block
// the SPI. Meanwhile, we keep putting the "data in"
// in the fifo until the SPI unblock and transmitt data.
// Implement a fifo overflow signal
/////////////////////////////////////////////////////////////////////
`include "timescale.v"
module fifo_spi_dpram (clk, nrst, we, din, dout, sck, ss);
input clk;
input nrst;
input we;
input [31:0] din;
output dout;
output sck;
output reg ss;
// States
parameter state_rst = 4'd0;
parameter state_wait = 4'd1;
parameter state_start = 4'd2;
parameter state_get_data = 4'd3;
parameter state_send = 4'd4;
parameter state_cnt = 4'd5;
parameter state_get_last = 4'd6;
parameter state_send_lf = 4'd7;
// Frame cnt
parameter total_frame = 255;
parameter last_frame_data = 32'h0000_1234;
/*8 888 8888888 8888888b. 8888888888 .d8888b.
888 o 888 888 888 Y88b 888 d88P Y88b
888 d8b 888 888 888 888 888 Y88b.
888 d888b 888 888 888 d88P 8888888 "Y888b.
888d88888b888 888 8888888P" 888 "Y88b.
88888P Y88888 888 888 T88b 888 "888
8888P Y8888 888 888 T88b 888 Y88b d88P
888P Y888 8888888 888 T88b 8888888888 "Y8888*/
// General
wire clk;
// SPI
wire spi_mlb;
wire spi_cdiv;
wire spi_din;
wire spi_ss_not_connected;
wire spi_sck;
wire spi_dout;
wire spi_done;
wire [31:0] spi_transmit_dat;
wire [31:0] spi_transmit_dat_LSB;
wire [31:0] rdata;
reg spi_start;
reg spi_start_reg;
// Fifo
wire fifo_clr;
wire fifo_we;
wire fifo_full;
wire fifo_empty;
wire fifo_full_r;
wire fifo_empty_r;
wire fifo_full_n;
wire fifo_empty_n;
wire fifo_full_n_r;
wire fifo_empty_n_r;
wire fifo_ready;
wire [1:0] fifo_level;
wire [31:0] fifo_din;
wire [31:0] fifo_dout;
reg fifo_re;
// Data line
reg [31:0] data_out_reg;
// Frame cnt
wire [8:0] frame_cnt_plus_one;
reg [8:0] frame_cnt_next;
reg [8:0] frame_cnt_reg;
// State machine
reg [3:0] current_state;
reg [3:0] next_state;
/*8b d888 .d88888b. 8888888b. 888 888 888 8888888888
8888b d8888 d88P" "Y88b 888 "Y88b 888 888 888 888
88888b.d88888 888 888 888 888 888 888 888 888
888Y88888P888 888 888 888 888 888 888 888 8888888
888 Y888P 888 888 888 888 888 888 888 888 888
888 Y8P 888 888 888 888 888 888 888 888 888
888 " 888 Y88b. .d88P 888 .d88P Y88b. .d88P 888 888
888 888 "Y88888P" 8888888P" "Y88888P" 88888888 88888888*/
spi_master spi (
.rstb (nrst), .clk (clk),
.mlb (spi_mlb), .start (spi_start),
.tdat (spi_transmit_dat), .cdiv (spi_cdiv),
.din (spi_din), .ss (spi_ss_not_connected),
.sck (spi_sck), .dout (spi_dout),
.done_r (spi_done), .rdata (rdata)
);
generic_fifo_sc_a fifo (
.clk (clk), .rst (nrst),
.clr (fifo_clr), .din (fifo_din),
.we (fifo_we), .dout (fifo_dout),
.re (fifo_re), .full (fifo_full),
.empty (fifo_empty), .full_r (fifo_full_r),
.empty_r (fifo_empty_r), .full_n (fifo_full_n),
.empty_n (fifo_empty_n), .full_n_r (fifo_full_n_r),
.empty_n_r (fifo_empty_n_r), .level (fifo_level)
);
defparam fifo.dw = 32;
defparam fifo.aw = 10;
defparam fifo.n = 1000;
/*888 .d8888b. .d8888b. 8888888 .d8888b. 888b 888
d88888 d88P Y88b d88P Y88b 888 d88P Y88b 8888b 888
d88P888 Y88b. Y88b. 888 888 888 88888b 888
d88P 888 "Y888b. "Y888b. 888 888 888Y88b 888
d88P 888 "Y88b. "Y88b. 888 888 88888 888 Y88b888
d88P 888 "888 "888 888 888 888 888 Y88888
d8888888888 Y88b d88P Y88b d88P 888 Y88b d88P 888 Y8888
d88P 888 "Y8888P" "Y8888P" 8888888 "Y8888P88 888 Y8*/
// Frame cnt
assign frame_cnt_plus_one = frame_cnt_reg + 1'b1;
// SPI
assign spi_mlb = 1'b1;
assign spi_cdiv = 1'b0;
assign spi_transmit_dat = data_out_reg;
// assign spi_transmit_dat_LSB = data_out_reg;
// assign spi_transmit_dat = {{spi_transmit_dat_LSB[7:0]}, {spi_transmit_dat_LSB[15:8]},
// {spi_transmit_dat_LSB[23:16]}, {spi_transmit_dat_LSB[31:24]} };
// FIFO
assign fifo_din = din; // data for the fifo
assign fifo_we = we; // write enable for the fifo
assign fifo_ready = (fifo_level > 2'b1) ? 1'b1 : 1'b0; // Control: is there at least 255 words in the fifo ?
assign fifo_clr = 0;
// output
assign dout = spi_dout;
assign sck = spi_sck;
/*88888888 .d8888b. 888b d888
888 d88P Y88b 8888b d8888
888 Y88b. 88888b.d88888
8888888 "Y888b. 888Y88888P888
888 "Y88b. 888 Y888P 888
888 "888 888 Y8P 888
888 Y88b d88P 888 " 888
888 "Y8888P" 888 8*/
// State register and related register
always @ (negedge clk or negedge nrst) begin
if (!nrst) begin
current_state <= state_rst;
frame_cnt_reg <= 9'd0;
data_out_reg <= 32'd0;
end
else begin
current_state <= next_state;
frame_cnt_reg <= frame_cnt_next;
if (current_state == state_get_data)
data_out_reg <= fifo_dout;
else if (current_state == state_get_last)
data_out_reg <= last_frame_data;
else
data_out_reg <= data_out_reg;
end
end
// FSM combinationnal in/out
always @ (*) begin
ss = 1'b0;
fifo_re = 1'b0;
spi_start = 1'b0;
frame_cnt_next = 9'b0;
next_state = current_state;
case (current_state)
state_rst : begin
ss = 1'b1;
next_state = state_wait;
end
// Wait we got 255 word data is in the fifo
state_wait : begin
if (fifo_ready) next_state = state_start;
ss = 1'b1;
end
// Start the sending of the 255 word data packet
state_start : begin
fifo_re = 1'b1;
next_state = state_get_data;
end
// Get one word data
state_get_data: begin
frame_cnt_next = frame_cnt_plus_one;
next_state = state_send;
end
// Send it through the SPI
state_send : begin
if (!spi_done) begin
spi_start = 1'b1;
frame_cnt_next = frame_cnt_reg;
end
else begin
frame_cnt_next = frame_cnt_reg;
next_state = state_cnt;
end
end
// Check: Did we send all the 255 data ?
state_cnt : begin
if (frame_cnt_reg < total_frame) begin
frame_cnt_next = frame_cnt_reg;
fifo_re = 1'b1;
next_state = state_get_data;
end
else begin
next_state = state_get_last;
end
end
// We send the End data (control) word
state_get_last: begin
next_state = state_send_lf;
end
// Check: did the last data has been sent ?
state_send_lf : begin
if (!spi_done) begin
spi_start = 1'b1;
next_state = state_send_lf;
end
else begin
next_state = state_wait;
end
end
default : next_state = state_rst;
endcase
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EBUFN_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__EBUFN_PP_BLACKBOX_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EBUFN_PP_BLACKBOX_V
|
module hex_to_7seg
(
input i_Clk,
input [3:0] i_Value,
output o_Segment_A,
output o_Segment_B,
output o_Segment_C,
output o_Segment_D,
output o_Segment_E,
output o_Segment_F,
output o_Segment_G
);
reg [6:0] out = 7'b0000000;
always @(posedge i_Clk)
begin
case (i_Value)
4'b0000 : out <= 7'b0000001;
4'b0001 : out <= 7'b1001111;
4'b0010 : out <= 7'b0010010;
4'b0011 : out <= 7'b0000110;
4'b0100 : out <= 7'b1001100;
4'b0101 : out <= 7'b0100100;
4'b0110 : out <= 7'b0100000;
4'b0111 : out <= 7'b0001111;
4'b1000 : out <= 7'b0000000;
4'b1001 : out <= 7'b0000100;
4'b1010 : out <= 7'b0001000;
4'b1011 : out <= 7'b1100000;
4'b1100 : out <= 7'b0110001;
4'b1101 : out <= 7'b1000010;
4'b1110 : out <= 7'b0110000;
4'b1111 : out <= 7'b0111000;
endcase
end
assign o_Segment_A = out[6];
assign o_Segment_B = out[5];
assign o_Segment_C = out[4];
assign o_Segment_D = out[3];
assign o_Segment_E = out[2];
assign o_Segment_F = out[1];
assign o_Segment_G = out[0];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A32OI_BEHAVIORAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX4_PP_SYMBOL_V
`define SKY130_FD_SC_LS__MUX4_PP_SYMBOL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__mux4 (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
input A2 ,
input A3 ,
output X ,
//# {{control|Control Signals}}
input S0 ,
input S1 ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX4_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A222OI_TB_V
`define SKY130_FD_SC_HDLL__A222OI_TB_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a222oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg C2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
C2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 C2 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A1 = 1'b1;
#240 A2 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 C1 = 1'b1;
#320 C2 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A1 = 1'b0;
#440 A2 = 1'b0;
#460 B1 = 1'b0;
#480 B2 = 1'b0;
#500 C1 = 1'b0;
#520 C2 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 C2 = 1'b1;
#720 C1 = 1'b1;
#740 B2 = 1'b1;
#760 B1 = 1'b1;
#780 A2 = 1'b1;
#800 A1 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 C2 = 1'bx;
#920 C1 = 1'bx;
#940 B2 = 1'bx;
#960 B1 = 1'bx;
#980 A2 = 1'bx;
#1000 A1 = 1'bx;
end
sky130_fd_sc_hdll__a222oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A222OI_TB_V
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module fast_cycle(
input CLK_24M,
input LSPC_12M,
input LSPC_6M,
input LSPC_3M,
input LSPC_1_5M,
input RESETP,
input nVRAM_WRITE_REQ,
input [15:0] VRAM_ADDR,
input [15:0] VRAM_WRITE,
input REG_VRAMADDR_MSB,
input FLIP, nFLIP,
input [8:0] PIXELC,
input [8:0] RASTERC,
input P50_CO,
output nCPU_WR_HIGH,
output [3:0] HSHRINK,
output [15:0] PIPE_C,
output [15:0] VRAM_HIGH_READ,
output [7:0] ACTIVE_RD,
output R91_Q,
output R91_nQ,
input T140_Q,
input T58A_OUT,
input T73A_OUT,
input U129A_Q,
input T125A_OUT,
output CLK_ACTIVE_RD,
output ACTIVE_RD_PRE8,
output [8:0] SPR_Y,
output [7:0] YSHRINK,
output SPR_SIZE0,
output SPR_SIZE5,
output O159_QB
);
wire [10:0] C;
wire [15:0] F;
wire [8:0] PARSE_Y;
wire [5:0] PARSE_SIZE;
wire [15:0] F_OUT_MUX;
wire [3:0] J102_Q;
wire [3:0] E175_Q;
wire [7:0] ACTIVE_RD_PRE;
wire [3:0] J127_Q;
wire [8:0] PARSE_INDEX;
wire [3:0] T102_Q;
wire [7:0] PARSE_LOOKAHEAD;
wire [8:0] PARSE_ADD_Y;
wire [5:0] PARSE_ADD_SIZE;
wire [7:0] ACTIVE_RD_ADDR; // Bit 7 unused
wire [15:0] PIPE_A;
wire [15:0] PIPE_B;
wire [3:0] O141_Q;
wire [3:0] G152_Q;
wire [3:0] G152_Q_DELAYED;
wire [3:0] J87_Q;
wire [3:0] J87_Q_DELAYED;
wire [7:0] ACTIVE_WR_ADDR; // Bit 7 unused
wire [10:0] A_TOP;
wire [10:0] B_TOP;
wire [10:0] C_TOP;
wire [10:0] D_TOP;
wire [10:0] A_BOT;
wire [10:0] B_BOT;
wire [10:0] C_BOT;
wire [10:0] D_BOT;
// CPU read
// L251 L269 L233 K249
FDS16bit L251(~CLK_CPU_READ_HIGH, F, VRAM_HIGH_READ);
// Y parsing read
// N214 M214 M178 L190
FDS16bit N214(O109A_OUT, F, {PARSE_Y, PARSE_CHAIN, PARSE_SIZE});
// Y Rendering read
FDSCell M250(N98_QC, F[15:12], SPR_Y[8:5]);
FDSCell M269(N98_QC, F[11:8], SPR_Y[4:1]);
FDSCell M233(N98_QC, {F[7:5], F[0]}, {SPR_Y[0], SPR_CHAIN, SPR_SIZE5, SPR_SIZE0});
// Active list read
FDSCell J117(H125A_OUT, F[7:4], ACTIVE_RD_PRE[7:4]);
FDSCell J178(H125A_OUT, F[3:0], ACTIVE_RD_PRE[3:0]);
// Next step
FDSCell I32(CLK_ACTIVE_RD, ACTIVE_RD_PRE[7:4], ACTIVE_RD[7:4]);
FDSCell H165(CLK_ACTIVE_RD, ACTIVE_RD_PRE[3:0], ACTIVE_RD[3:0]);
// Shrink read
FDSCell O141(N98_QB, F[11:8], O141_Q);
FDSCell O123(N98_QB, F[7:4], YSHRINK[7:4]);
FDSCell K178(N98_QB, F[3:0], YSHRINK[3:0]);
// Data output
// O171B O171A O173B O173A
// B178B B173B B171B C180B
// C146B C144B C142B C149B
// E207B E207A E209B E209A
assign F_OUT_MUX = CLK_CPU_READ_HIGH ? VRAM_WRITE : {7'b0000000, J194_Q, J102_Q, E175_Q};
assign F = CWE ? 16'bzzzzzzzzzzzzzzzz : F_OUT_MUX;
assign O112B_OUT = O109A_OUT; // 2x inverter
FDSCell G152(PARSE_INDEX_INC_CLK, PARSE_INDEX[3:0], G152_Q);
assign #5 G152_Q_DELAYED = G152_Q; // 4x BD3
FDSCell J87(PARSE_INDEX_INC_CLK, PARSE_INDEX[7:4], J87_Q);
assign #5 J87_Q_DELAYED = J87_Q; // 4x BD3
FDRCell E175(O109A_OUT, G152_Q_DELAYED, nPARSING_DONE, E175_Q);
FDRCell J102(O109A_OUT, J87_Q_DELAYED, nPARSING_DONE, J102_Q);
FDM J231(PARSE_INDEX_INC_CLK, PARSE_INDEX[8], J231_Q, );
BD3 J235A(J231_Q, J231_Q_DELAYED);
FDPCell J194(O112B_OUT, J231_Q_DELAYED, 1'b1, nPARSING_DONE, J194_Q, );
// CWE output
assign O107A_OUT = VRAM_HIGH_ADDR_SB & nCPU_WR_HIGH; // OK
assign T146A_OUT = ~|{T129A_nQ, T148_Q};
assign CWE = O107A_OUT | T146A_OUT; // OK
// O103A
assign VRAM_HIGH_ADDR_SB = ~&{WR_ACTIVE, O98_Q};
BD3 O84A(N98_QD, N98_QD_DELAYED);
FDPCell O98(T125A_OUT, N98_QD_DELAYED, 1'b1, RESETP, O98_Q, CLK_CPU_READ_HIGH);
FDPCell N93(N98_QD, F58A_OUT, CLK_CPU_READ_HIGH, 1'b1, nCPU_WR_HIGH, );
assign F58A_OUT = ~REG_VRAMADDR_MSB | nVRAM_WRITE_REQ;
FDM I148(H125A_OUT, F[8], ACTIVE_RD_PRE8, );
assign H125A_OUT = CLK_ACTIVE_RD;
// Parsing end detection
assign I145_OUT = ~&{PARSE_INDEX[6:1], PARSE_INDEX[8]};
assign R113A_OUT = I145_OUT & nPARSING_DONE;
FDPCell R109(O109A_OUT, R113A_OUT, nNEW_LINE, 1'b1, nPARSING_DONE, );
// Active list full detection
assign S109B_OUT = S111_Q & nACTIVE_FULL;
FDPCell S111(O109A_OUT, S109B_OUT, nNEW_LINE, 1'b1, S111_Q, S111_nQ);
assign S109A_OUT = S111_Q & nNEW_LINE;
// Write to fast VRAM enable
assign T95A_OUT = IS_ACTIVE & T102_Q[0];
assign R107A_OUT = nPARSING_DONE | S111_nQ;
FDPCell R103(O109A_OUT, T95A_OUT, R107A_OUT, S109A_OUT, WR_ACTIVE, );
FD2 T129A(CLK_24M, T126B_OUT, , T129A_nQ);
assign T126B_OUT = ~&{T66_Q, T140_Q};
FDM T66(LSPC_12M, T58A_OUT, T66_Q, );
assign P49A_OUT = PIXELC[8];
FDM S67(LSPC_3M, P49A_OUT, , S67_nQ);
assign S70B_OUT = ~&{S67_nQ, P49A_OUT};
BD3 S71A(S70B_OUT, S71A_OUT);
FDM S74(LSPC_6M, S71A_OUT, S74_Q, );
// S107A Used for test mode
assign nNEW_LINE = 1'b1 & S74_Q;
FDM T148(CLK_24M, T128B_OUT, T148_Q, );
assign T128B_OUT = ~&{T73A_OUT, U129A_Q};
// T181A
assign IS_ACTIVE = PARSE_CHAIN ? T90A_OUT : M176A_OUT;
assign M176A_OUT = PARSE_MATCH | PARSE_SIZE[5];
BD3 S105(VRAM_HIGH_ADDR_SB, S105_OUT);
FDRCell T102(O109A_OUT, {1'b0, T102_Q[1], T102_Q[0], S105_OUT}, nNEW_LINE, T102_Q);
assign T94_OUT = ~&{T102_Q[1:0], O102B_OUT};
assign T92_OUT = ~&{~T102_Q[2], ~T102_Q[1], T102_Q[0], VRAM_HIGH_ADDR_SB};
assign T90A_OUT = ~&{T94_OUT, T92_OUT};
C43 H198(O110B_OUT, 4'b0000, 1'b1, 1'b1, 1'b1, nNEW_LINE, ACTIVE_WR_ADDR[3:0], H198_CO);
// Used for test mode
assign H222A_OUT = H198_CO | 1'b0;
C43 I189(O110B_OUT, 4'b0000, 1'b1, 1'b1, H222A_OUT, nNEW_LINE, ACTIVE_WR_ADDR[7:4], );
assign nACTIVE_FULL = ~&{ACTIVE_WR_ADDR[6:5]}; // J100B
assign O110B_OUT = O109A_OUT | VRAM_HIGH_ADDR_SB;
FS3 N98(T125A_OUT, 4'b0000, R91_nQ, RESETP, {N98_QD, N98_QC, N98_QB, N98_QA});
assign CLK_ACTIVE_RD = ~K131B_OUT;
FDM R91(LSPC_12M, LSPC_1_5M, R91_Q, R91_nQ);
// Address mux
// I213 I218 G169A G164 G182A G194A G200 G205A I175A I182A
// J62 J72A I104 I109A J205A J200 J49 J54A H28A H34 I13 I18A
assign A_TOP = {N98_QC, J36_OUT, ACTIVE_RD_PRE8, ACTIVE_RD_PRE};
assign B_TOP = {3'b110, H293B_OUT, ACTIVE_RD_ADDR[6:0]};
assign C_TOP = {3'b110, H293B_OUT, ACTIVE_RD_ADDR[6:0]};
assign D_TOP = {N98_QC, J36_OUT, ACTIVE_RD_PRE8, ACTIVE_RD_PRE};
assign A_BOT = {3'b110, I237A_OUT, ACTIVE_WR_ADDR[6:0]};
assign B_BOT = VRAM_ADDR[10:0];
assign C_BOT = VRAM_ADDR[10:0];
assign D_BOT = {2'b01, PARSE_INDEX};
// L110B_OUT A
// ~VRAM_HIGH_ADDR_SB B
// M95B_OUT C
// ABC:
assign C = M95B_OUT ?
~VRAM_HIGH_ADDR_SB ?
L110B_OUT ? C_TOP : A_TOP // 111 - 110
:
L110B_OUT ? B_TOP : D_TOP // 101 - 100
:
~VRAM_HIGH_ADDR_SB ?
L110B_OUT ? C_BOT : A_BOT // 011 - 010
:
L110B_OUT ? B_BOT : D_BOT; // 001 - 000
/*
assign C = L110B_OUT ?
~VRAM_HIGH_ADDR_SB ?
M95B_OUT ? C_TOP : A_TOP // 111 - 110
:
M95B_OUT ? B_TOP : D_TOP // 101 - 100
:
~VRAM_HIGH_ADDR_SB ?
M95B_OUT ? C_BOT : A_BOT // 011 - 010
:
M95B_OUT ? B_BOT : D_BOT; // 001 - 000
*/
assign K131B_OUT = ~N98_QA;
assign M95B_OUT = ~|{N98_QD, O98_Q};
assign L110B_OUT = ~|{L110A_OUT, O98_Q};
assign L110A_OUT = ~|{K131B_OUT, N98_QD};
assign I237A_OUT = FLIP;
assign K260B_OUT = FLIP;
assign H293B_OUT = nFLIP;
assign J36_OUT = N98_QB ^ N98_QC;
// Active list read counter
assign #1 P39A_OUT = ~PIXELC[8];
assign nRELOAD_RD_ACTIVE = ~&{PIXELC[6], P50_CO, P39A_OUT}; // O55A
C43 I151(CLK_ACTIVE_RD, 4'b0000, nRELOAD_RD_ACTIVE, 1'b1, 1'b1, 1'b1, ACTIVE_RD_ADDR[3:0], I151_CO);
assign J176A_OUT = I151_CO | 1'b0; // Used for test mode
C43 J151(CLK_ACTIVE_RD, 4'b0000, nRELOAD_RD_ACTIVE, 1'b1, J176A_OUT, 1'b1, ACTIVE_RD_ADDR[7:4], );
// Parsing counter
assign PARSE_INDEX_INC_CLK = O102B_OUT | O109A_OUT; // O105B
C43 H127(PARSE_INDEX_INC_CLK, 4'b0000, 1'b1, 1'b1, 1'b1, nNEW_LINE, PARSE_INDEX[3:0], H127_CO);
assign H125B_OUT = H127_CO | 1'b0; // Used for test mode
C43 I121(PARSE_INDEX_INC_CLK, 4'b0000, 1'b1, H125B_OUT, 1'b1, nNEW_LINE, PARSE_INDEX[7:4], I121_CO);
C43 J127(PARSE_INDEX_INC_CLK, 4'b0000, 1'b1, H125B_OUT, I121_CO, nNEW_LINE, J127_Q, );
assign PARSE_INDEX[8] = J127_Q[0];
assign O109A_OUT = T125A_OUT | CLK_CPU_READ_HIGH;
assign O102B_OUT = WR_ACTIVE & O98_Q;
// Y parse matching
// L200 O200
assign PARSE_LOOKAHEAD = 8'd2 + {RASTERC[7:1], K260B_OUT};
// M190 N190
assign PARSE_ADD_Y = PARSE_LOOKAHEAD + PARSE_Y[7:0];
assign N186_OUT = ~^{PARSE_ADD_Y[8], PARSE_Y[8]};
// K195 M151
assign PARSE_ADD_SIZE = {N186_OUT, ~PARSE_ADD_Y[7:4]} + PARSE_SIZE[4:0];
assign PARSE_MATCH = PARSE_ADD_SIZE[5];
// Pipe for x position and h-shrink
// O159 P131 O87 N131
FDS16bit O159(N98_QD, {2'b00, SPR_CHAIN, O141_Q, F[15:7]}, PIPE_A);
assign O159_QB = PIPE_A[13];
// P165 P121 P87 N121
FDS16bit P165(N98_QD, PIPE_A, PIPE_B);
// P155 P141 P104 N141
FDS16bit P155(N98_QD, PIPE_B, PIPE_C);
assign HSHRINK = PIPE_C[12:9];
vram_fast_u VRAMUU(C, F[15:8], 1'b0, 1'b0, CWE);
vram_fast_l VRAMUL(C, F[7:0], 1'b0, 1'b0, CWE);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:00:44 04/13/2016
// Design Name:
// Module Name: MAIN
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MAIN(
input clk,
input clkb,
input Reset,
input Write_Reg,
input Mem_Write, // Disable
input [15:0] offset, // 16 bit (offset)
input [2:0] ALU_OP,
// input [5:0] STORAGE_Addr_R,
input wire [4:0] W_Addr,
input wire [4:0] RS,
input wire [4:0] RT, // Disable
output wire [31:0] A,
output wire [31:0] Data_Bus, // set A, Data_Bus for debuging
output wire [31:0] Result, // ALU Reslut
output OF, ZF
);
wire [31:0] B;
register REG (
.clk(clk),
.Reset(Reset),
.R_Addr_A(RS),
.R_Addr_B(RT),
.W_Addr(W_Addr),
.W_Data(Data_Bus),
.Write_Reg(Write_Reg),
.R_Data_A(A),
.R_Data_B(B)
);
ALU ALUP (
.A(A),
.B({{16{1'b0}}, offset}),
.ZF(ZF),
.OF(OF),
.F(Result),
.ALU_OP(ALU_OP)
);
RAM_B STORAGEM (
.clka(clkb), // input clka 100M
.wea(Mem_Write), // input [0 : 0] wea Meanless at this
.addra(Result[7:2]), // input [5 : 0] addra
.dina(B), // input [31 : 0] dina Meanless at this
.douta(Data_Bus) // output [31 : 0] douta
);
endmodule
module TESTSTORAGE(
input [5:0] Mem_Addr,
input [1:0] CS,
input Mem_Write,
input Clk,
output reg [7:0] LED
);
wire [31:0] F;
reg [31:0] dina;
RAM_B STORAGE (
.clka(Clk), // input clka
.wea(Mem_Write), // input [0 : 0] wea
.addra(Mem_Addr), // input [5 : 0] addra
.dina(dina), // input [31 : 0] dina
.douta(F) // output [31 : 0] douta
);
always@(*)
begin
if(!Mem_Write)
begin
case(CS)
2'd0:begin
LED <= F[7:0];
end
2'd1:begin
LED <= F[15:8];
end
2'd2:begin
LED <= F[23:16];
end
2'd3:begin
LED <= F[31:24];
end
default:
begin
LED <= F[7:0];
end
endcase
end
else
begin
case(CS)
2'b00: dina= 32'h1234_5678;
2'b01: dina= 32'h89AB_CDEF;
2'b10: dina= 32'h7FFF_FFFF;
2'b11: dina= 32'hFFFF_FFFF;
endcase
end
end
endmodule
module register(clk, Reset, R_Addr_A, R_Addr_B, W_Addr, W_Data, Write_Reg, R_Data_A, R_Data_B
);
input clk;
input Reset;
input Write_Reg;
input [4:0] R_Addr_A, R_Addr_B, W_Addr;
input [31:0] W_Data;
output [31:0] R_Data_A;
output [31:0] R_Data_B;
reg [31:0] REGISTERS[31:0];
integer i;
assign R_Data_A = REGISTERS[R_Addr_A];
assign R_Data_B = REGISTERS[R_Addr_B];
always @(*)
begin
if(Reset)
begin
for(i=0; i<=31; i=i+1)
begin
REGISTERS[i]<=32'h0000_0000;
end
end
else
begin
if(Write_Reg)
begin
REGISTERS[W_Addr]<=W_Data;
end
else
begin
REGISTERS[W_Addr]<=REGISTERS[W_Addr];
end
end
end
endmodule
module ALU(A, B, ZF, OF, F, ALU_OP);
input [2:0] ALU_OP;
input [31:0] A, B;
output reg [31:0] F;
output reg ZF, OF;
reg C32;
always @(*)
begin
case(ALU_OP)
3'd0:begin //and
F = A&B;
OF = 0;
end
3'd1:begin //or
F = A|B;
OF = 0;
end
3'd2:begin //xor
F = A^B;
OF = 0;
end
3'd3:begin //nor
F = ~(A|B);
OF = 0;
end
3'd4:begin //add
{C32, F} = A + B;
OF = A[31]^B[31]^F[31]^C32;
end
3'd5:begin //sub
{C32, F} = A - B;
OF = A[31]^B[31]^F[31]^C32;
end
3'd6:begin //slt
if (A<B)
begin
F = 32'd1;
end
else
begin
F = 32'd0;
end
OF = 0;
end
3'd7:begin //sll
F=B<<A;
OF=0;
end
default:begin
F=A;
OF = 0;
end
endcase
if (F == 32'd0)
begin
ZF = 1;
end
else
begin
ZF = 0;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DIODE_BEHAVIORAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DIODE_BEHAVIORAL_PP_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ucb_flow_spi.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: ucb_flow_spi
// Description: Unit Control Block
// - supports 1B/2B/4B/8B read with flow control
// - supports 1B/2B/4B/8B write with flow control
// - supports 4B ifill request
// - supports interrupt return to IO Bridge
// - provides 1+2 deep buffer for incoming requests
// from the IO Bridge
// - provides single buffer for returns going back
// to the IO Bridge
//
// This module is customized for the SPI.
//
// Data bus width to and from the IO Bridge is
// configured through parameters UCB_IOB_WIDTH and
// IOB_UCB_WIDTH. Supported widths are:
//
// IOB_UCB_WIDTH UCB_IOB_WIDTH
// ----------------------------
// 32 8
// 16 8
// 8 8
// 4 4
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which
// contains the time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`define UCB_BUF_DEPTH 2
`define UCB_BUF_WIDTH 64+(`UCB_ADDR_HI-`UCB_ADDR_LO+1)+(`UCB_SIZE_HI-`UCB_SIZE_LO+1)+(`UCB_BUF_HI-`UCB_BUF_LO+1)+(`UCB_THR_HI-`UCB_THR_LO+1)+1+1+1
module ucb_flow_spi (/*AUTOARG*/
// Outputs
ucb_iob_stall, rd_req_vld, wr_req_vld, ifill_req_vld, thr_id_in,
buf_id_in, size_in, addr_in, data_in, ack_busy, int_busy,
ucb_iob_vld, ucb_iob_data,
// Inputs
clk, rst_l, iob_ucb_vld, iob_ucb_data, req_acpted, rd_ack_vld,
rd_nack_vld, ifill_ack_vld, ifill_nack_vld, thr_id_out,
buf_id_out, data128, data_out, int_vld, int_typ, int_thr_id,
dev_id, int_stat, int_vec, iob_ucb_stall
);
// synopsys template
parameter IOB_UCB_WIDTH = 32; // data bus width from IOB to UCB
parameter UCB_IOB_WIDTH = 8; // data bus width from UCB to IOB
parameter REG_WIDTH = 64; // please do not change this parameter
// Globals
input clk;
input rst_l;
// Request from IO Bridge
input iob_ucb_vld;
input [IOB_UCB_WIDTH-1:0] iob_ucb_data;
output ucb_iob_stall;
// Request to local unit
output rd_req_vld;
output wr_req_vld;
output ifill_req_vld;
output [`UCB_THR_HI-`UCB_THR_LO:0] thr_id_in;
output [`UCB_BUF_HI-`UCB_BUF_LO:0] buf_id_in;
output [`UCB_SIZE_HI-`UCB_SIZE_LO:0] size_in; // only pertinent to JBI and SPI
output [`UCB_ADDR_HI-`UCB_ADDR_LO:0] addr_in;
output [`UCB_DATA_HI-`UCB_DATA_LO:0] data_in;
input req_acpted;
// Ack/Nack from local unit
input rd_ack_vld;
input rd_nack_vld;
input ifill_ack_vld;
input ifill_nack_vld;
input [`UCB_THR_HI-`UCB_THR_LO:0] thr_id_out;
input [`UCB_BUF_HI-`UCB_BUF_LO:0] buf_id_out;
input data128; // set to 1 if data returned is 128 bit
input [REG_WIDTH-1:0] data_out;
output ack_busy;
// Interrupt from local unit
input int_vld;
input [`UCB_PKT_HI-`UCB_PKT_LO:0] int_typ; // interrupt type
input [`UCB_THR_HI-`UCB_THR_LO:0] int_thr_id; // interrupt thread ID
input [`UCB_INT_DEV_HI-`UCB_INT_DEV_LO:0] dev_id; // interrupt device ID
input [`UCB_INT_STAT_HI-`UCB_INT_STAT_LO:0] int_stat; // interrupt status
input [`UCB_INT_VEC_HI-`UCB_INT_VEC_LO:0] int_vec; // interrupt vector
output int_busy;
// Output to IO Bridge
output ucb_iob_vld;
output [UCB_IOB_WIDTH-1:0] ucb_iob_data;
input iob_ucb_stall;
// Local signals
wire indata_buf_vld;
wire [127:0] indata_buf;
wire ucb_iob_stall_a1;
wire read_pending;
wire write_pending;
wire ifill_pending;
wire rd_buf;
wire [`UCB_BUF_DEPTH-1:0] buf_head_next;
wire [`UCB_BUF_DEPTH-1:0] buf_head;
wire wr_buf;
wire [`UCB_BUF_DEPTH-1:0] buf_tail_next;
wire [`UCB_BUF_DEPTH-1:0] buf_tail;
wire buf_full_next;
wire buf_full;
wire buf_empty_next;
wire buf_empty;
wire [`UCB_BUF_WIDTH-1:0] req_in;
wire buf0_en;
wire [`UCB_BUF_WIDTH-1:0] buf0;
wire buf1_en;
wire [`UCB_BUF_WIDTH-1:0] buf1;
wire [`UCB_BUF_WIDTH-1:0] req_out;
wire rd_req_vld_nq;
wire wr_req_vld_nq;
wire ifill_req_vld_nq;
wire ack_buf_rd;
wire ack_buf_wr;
wire ack_buf_vld;
wire ack_buf_vld_next;
wire ack_buf_is_nack;
wire ack_buf_is_data128;
wire [`UCB_PKT_HI-`UCB_PKT_LO:0] ack_typ_out;
wire [REG_WIDTH+`UCB_BUF_HI-`UCB_PKT_LO:0] ack_buf_in;
wire [REG_WIDTH+`UCB_BUF_HI-`UCB_PKT_LO:0] ack_buf;
wire [(REG_WIDTH+64)/UCB_IOB_WIDTH-1:0] ack_buf_vec;
wire int_buf_rd;
wire int_buf_wr;
wire int_buf_vld;
wire int_buf_vld_next;
wire [`UCB_INT_VEC_HI-`UCB_PKT_LO:0] int_buf_in;
wire [`UCB_INT_VEC_HI-`UCB_PKT_LO:0] int_buf;
wire [(REG_WIDTH+64)/UCB_IOB_WIDTH-1:0] int_buf_vec;
wire int_last_rd;
wire outdata_buf_busy;
wire outdata_buf_wr;
wire [REG_WIDTH+63:0] outdata_buf_in;
wire [(REG_WIDTH+64)/UCB_IOB_WIDTH-1:0] outdata_vec_in;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
/************************************************************
* Inbound Data
************************************************************/
// Register size is hardcoded to 64 bits here
ucb_bus_in #(IOB_UCB_WIDTH,64) ucb_bus_in (.rst_l(rst_l),
.clk(clk),
.vld(iob_ucb_vld),
.data(iob_ucb_data),
.stall(ucb_iob_stall),
.indata_buf_vld(indata_buf_vld),
.indata_buf(indata_buf),
.stall_a1(ucb_iob_stall_a1));
/************************************************************
* Decode inbound packet type
************************************************************/
assign read_pending = (indata_buf[`UCB_PKT_HI:`UCB_PKT_LO] ==
`UCB_READ_REQ) &
indata_buf_vld;
assign write_pending = (indata_buf[`UCB_PKT_HI:`UCB_PKT_LO] ==
`UCB_WRITE_REQ) &
indata_buf_vld;
assign ifill_pending = (indata_buf[`UCB_PKT_HI:`UCB_PKT_LO] ==
`UCB_IFILL_REQ) &
indata_buf_vld;
assign ucb_iob_stall_a1 = (read_pending | write_pending | ifill_pending) & buf_full;
/************************************************************
* Inbound buffer
************************************************************/
// Head pointer
assign rd_buf = req_acpted;
assign buf_head_next = ~rst_l ? `UCB_BUF_DEPTH'b01 :
rd_buf ? {buf_head[`UCB_BUF_DEPTH-2:0],
buf_head[`UCB_BUF_DEPTH-1]} :
buf_head;
dff_ns #(`UCB_BUF_DEPTH) buf_head_ff (.din(buf_head_next),
.clk(clk),
.q(buf_head));
// Tail pointer
assign wr_buf = (read_pending |
write_pending |
ifill_pending) &
~buf_full;
assign buf_tail_next = ~rst_l ? `UCB_BUF_DEPTH'b01 :
wr_buf ? {buf_tail[`UCB_BUF_DEPTH-2:0],
buf_tail[`UCB_BUF_DEPTH-1]} :
buf_tail;
dff_ns #(`UCB_BUF_DEPTH) buf_tail_ff (.din(buf_tail_next),
.clk(clk),
.q(buf_tail));
// Buffer full
assign buf_full_next = (buf_head_next == buf_tail_next) &
wr_buf;
dffrle_ns #(1) buf_full_ff (.din(buf_full_next),
.rst_l(rst_l),
.en(rd_buf|wr_buf),
.clk(clk),
.q(buf_full));
// Buffer empty
assign buf_empty_next = ((buf_head_next == buf_tail_next) &
rd_buf) | ~rst_l;
dffe_ns #(1) buf_empty_ff (.din(buf_empty_next),
.en(rd_buf|wr_buf|~rst_l),
.clk(clk),
.q(buf_empty));
assign req_in = {indata_buf[`UCB_DATA_HI:`UCB_DATA_LO],
indata_buf[`UCB_ADDR_HI:`UCB_ADDR_LO],
indata_buf[`UCB_SIZE_HI:`UCB_SIZE_LO],
indata_buf[`UCB_BUF_HI:`UCB_BUF_LO],
indata_buf[`UCB_THR_HI:`UCB_THR_LO],
ifill_pending,
write_pending,
read_pending};
// Buffer 0
assign buf0_en = buf_tail[0] & wr_buf;
dffe_ns #(`UCB_BUF_WIDTH) buf0_ff (.din(req_in),
.en(buf0_en),
.clk(clk),
.q(buf0));
// Buffer 1
assign buf1_en = buf_tail[1] & wr_buf;
dffe_ns #(`UCB_BUF_WIDTH) buf1_ff (.din(req_in),
.en(buf1_en),
.clk(clk),
.q(buf1));
assign req_out = buf_head[0] ? buf0 :
buf_head[1] ? buf1 :
{`UCB_BUF_WIDTH{1'b0}};
/************************************************************
* Inbound interface to local unit
************************************************************/
assign {data_in,
addr_in,
size_in,
buf_id_in,
thr_id_in,
ifill_req_vld_nq,
wr_req_vld_nq,
rd_req_vld_nq} = req_out;
assign rd_req_vld = rd_req_vld_nq & ~buf_empty;
assign wr_req_vld = wr_req_vld_nq & ~buf_empty;
assign ifill_req_vld = ifill_req_vld_nq & ~buf_empty;
/************************************************************
* Outbound Ack/Nack
************************************************************/
assign ack_buf_wr = rd_ack_vld | rd_nack_vld | ifill_ack_vld | ifill_nack_vld;
assign ack_buf_vld_next = ack_buf_wr ? 1'b1 :
ack_buf_rd ? 1'b0 :
ack_buf_vld;
dffrl_ns #(1) ack_buf_vld_ff (.din(ack_buf_vld_next),
.clk(clk),
.rst_l(rst_l),
.q(ack_buf_vld));
dffe_ns #(1) ack_buf_is_nack_ff (.din(rd_nack_vld|ifill_nack_vld),
.en(ack_buf_wr),
.clk(clk),
.q(ack_buf_is_nack));
dffe_ns #(1) ack_buf_is_data128_ff (.din(data128),
.en(ack_buf_wr),
.clk(clk),
.q(ack_buf_is_data128));
assign ack_typ_out = rd_ack_vld ? `UCB_READ_ACK:
rd_nack_vld ? `UCB_READ_NACK:
ifill_ack_vld ? `UCB_IFILL_ACK:
`UCB_IFILL_NACK;
assign ack_buf_in = {data_out,
buf_id_out,
thr_id_out,
ack_typ_out};
dffe_ns #(REG_WIDTH+`UCB_BUF_HI-`UCB_PKT_LO+1) ack_buf_ff (.din(ack_buf_in),
.en(ack_buf_wr),
.clk(clk),
.q(ack_buf));
assign ack_buf_vec = ack_buf_is_nack ? {{REG_WIDTH/UCB_IOB_WIDTH{1'b0}},
{64/UCB_IOB_WIDTH{1'b1}}} :
ack_buf_is_data128 ? {(REG_WIDTH+64)/UCB_IOB_WIDTH{1'b1}} :
{(64+64)/UCB_IOB_WIDTH{1'b1}};
assign ack_busy = ack_buf_vld;
/************************************************************
* Outbound Interrupt
************************************************************/
// Assertion: int_buf_wr shoudn't be asserted if int_buf_busy
assign int_buf_wr = int_vld;
assign int_buf_vld_next = int_buf_wr ? 1'b1 :
int_buf_rd ? 1'b0 :
int_buf_vld;
dffrl_ns #(1) int_buf_vld_ff (.din(int_buf_vld_next),
.clk(clk),
.rst_l(rst_l),
.q(int_buf_vld));
assign int_buf_in = {int_vec,
int_stat,
dev_id,
int_thr_id,
int_typ};
dffe_ns #(`UCB_INT_VEC_HI-`UCB_PKT_LO+1) int_buf_ff (.din(int_buf_in),
.en(int_buf_wr),
.clk(clk),
.q(int_buf));
assign int_buf_vec = {{REG_WIDTH/UCB_IOB_WIDTH{1'b0}},
{64/UCB_IOB_WIDTH{1'b1}}};
assign int_busy = int_buf_vld;
/************************************************************
* Outbound ack/interrupt Arbitration
************************************************************/
dffrle_ns #(1) int_last_rd_ff (.din(int_buf_rd),
.en(ack_buf_rd|int_buf_rd),
.rst_l(rst_l),
.clk(clk),
.q(int_last_rd));
assign ack_buf_rd = ~outdata_buf_busy & ack_buf_vld &
(~int_buf_vld | int_last_rd);
assign int_buf_rd = ~outdata_buf_busy & int_buf_vld &
(~ack_buf_vld | ~int_last_rd);
assign outdata_buf_wr = ack_buf_rd | int_buf_rd;
assign outdata_buf_in = ack_buf_rd ? {ack_buf[REG_WIDTH+`UCB_BUF_HI:`UCB_BUF_HI+1],
{(`UCB_RSV_HI-`UCB_RSV_LO+1){1'b0}},
{(`UCB_ADDR_HI-`UCB_ADDR_LO+1){1'b0}},
{(`UCB_SIZE_HI-`UCB_SIZE_LO+1){1'b0}},
ack_buf[`UCB_BUF_HI:`UCB_BUF_LO],
ack_buf[`UCB_THR_HI:`UCB_THR_LO],
ack_buf[`UCB_PKT_HI:`UCB_PKT_LO]}:
{{REG_WIDTH{1'b0}},
{(`UCB_INT_RSV_HI-`UCB_INT_RSV_LO+1){1'b0}},
int_buf[`UCB_INT_VEC_HI:`UCB_INT_VEC_LO],
int_buf[`UCB_INT_STAT_HI:`UCB_INT_STAT_LO],
int_buf[`UCB_INT_DEV_HI:`UCB_INT_DEV_LO],
int_buf[`UCB_THR_HI:`UCB_THR_LO],
int_buf[`UCB_PKT_HI:`UCB_PKT_LO]};
assign outdata_vec_in = ack_buf_rd ? ack_buf_vec :
int_buf_vec;
ucb_bus_out #(UCB_IOB_WIDTH, REG_WIDTH) ucb_bus_out (.rst_l(rst_l),
.clk(clk),
.outdata_buf_wr(outdata_buf_wr),
.outdata_buf_in(outdata_buf_in),
.outdata_vec_in(outdata_vec_in),
.outdata_buf_busy(outdata_buf_busy),
.vld(ucb_iob_vld),
.data(ucb_iob_data),
.stall(iob_ucb_stall));
`undef UCB_BUF_WIDTH
endmodule // ucb_flow_spi
// Local Variables:
// verilog-library-directories:(".")
// End:
|
// ddr3_s4_uniphy_example_if0.v
// This file was auto-generated from alt_mem_if_ddr3_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using SOPC Builder version 11.0sp1 208 at 2011.09.28.12:48:48
`timescale 1 ps / 1 ps
module ddr3_s4_uniphy_example_if0 (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire afi_clk, // afi_clk.clk
output wire afi_half_clk, // afi_half_clk.clk
output wire afi_reset_n, // afi_reset.reset_n
output wire [12:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire [1:0] mem_dm, // .mem_dm
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [15:0] mem_dq, // .mem_dq
inout wire [1:0] mem_dqs, // .mem_dqs
inout wire [1:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire avl_ready, // avl.waitrequest_n
input wire avl_burstbegin, // .beginbursttransfer
input wire [23:0] avl_addr, // .address
output wire avl_rdata_valid, // .readdatavalid
output wire [63:0] avl_rdata, // .readdata
input wire [63:0] avl_wdata, // .writedata
input wire [7:0] avl_be, // .byteenable
input wire avl_read_req, // .read
input wire avl_write_req, // .write
input wire [2:0] avl_size, // .burstcount
output wire local_init_done, // status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
input wire oct_rdn, // oct.rdn
input wire oct_rup, // .rup
output wire local_powerdn_ack, // local_powerdown.local_powerdn_ack
input wire local_powerdn_req // .local_powerdn_req
);
wire [25:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire c0_afi_afi_cal_req; // c0:afi_cal_req -> p0:afi_cal_req
wire [5:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire [1:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire [1:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [1:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [5:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [63:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [1:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [1:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [1:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [5:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire [63:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [3:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [3:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [7:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
ddr3_s4_uniphy_example_if0_c0 c0 (
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.local_powerdn_ack (local_powerdn_ack), // local_powerdown.local_powerdn_ack
.local_powerdn_req (local_powerdn_req), // .local_powerdn_req
.avl_ready (avl_ready), // avl.waitrequest_n
.avl_burstbegin (avl_burstbegin), // .beginbursttransfer
.avl_addr (avl_addr), // .address
.avl_rdata_valid (avl_rdata_valid), // .readdatavalid
.avl_rdata (avl_rdata), // .readdata
.avl_wdata (avl_wdata), // .writedata
.avl_be (avl_be), // .byteenable
.avl_read_req (avl_read_req), // .read
.avl_write_req (avl_write_req), // .write
.avl_size (avl_size) // .burstcount
);
ddr3_s4_uniphy_example_if0_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.oct_rdn (oct_rdn), // oct.rdn
.oct_rup (oct_rup), // .rup
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.dll_delayctrl (), // (terminated)
.seriesterminationcontrol (), // (terminated)
.parallelterminationcontrol () // (terminated)
);
endmodule
|
module sound (switches, clock50, clock2_50, key, fpga_i2c_sclk, fpga_i2c_sdat, aud_xck,
aud_daclrck, aud_adclrck, aud_bclk, aud_adcdat, aud_dacdat);
input clock50, clock2_50;
input [3:0] switches;
input [0:0] key;
// I2C Audio/Video config interface
output fpga_i2c_sclk;
inout fpga_i2c_sdat;
// Audio CODEC
output aud_xck;
input aud_daclrck, aud_adclrck, aud_bclk;
input aud_adcdat;
output aud_dacdat;
// Local wires.
wire read_ready, write_ready, write, read;
wire [23:0] readdata_left, readdata_right;
wire [23:0] writedata_left, writedata_right;
wire reset = ~key[0];
// wire [7:0] counter;
//frequency wires
wire [3:0] frequency;
control cg(
.clock(clock50),
.reset(reset),
.switches(switches),
.write_ready(write_ready),
.write(write),
.writedata_left(writedata_left),
.writedata_right(writedata_right)
// .frequency(frequency),
// .counter(counter)
);
/////////////////////////////////////////////////////////////////////////////////
// Audio CODEC interface.
//
// The interface consists of the following wires:
// read_ready, write_ready - CODEC ready for read/write operation
// readdata_left, readdata_right - left and right channel data from the CODEC
// read - send data from the CODEC (both channels)
// writedata_left, writedata_right - left and right channel data to the CODEC
// write - send data to the CODEC (both channels)
// AUD_* - should connect to top-level entity I/O of the same name.
// These signals go directly to the Audio CODEC
// I2C_* - should connect to top-level entity I/O of the same name.
// These signals go directly to the Audio/Video Config module
/////////////////////////////////////////////////////////////////////////////////
clock_generator my_clock_gen(
// inputs
clock2_50,
reset,
// outputs
aud_xck
);
audio_and_video_config cfg(
// Inputs
clock50,
reset,
// Bidirectionals
fpga_i2c_sdat,
fpga_i2c_sclk
);
audio_codec codec(
// Inputs
clock50,
reset,
read, write,
writedata_left, writedata_right,
aud_adcdat,
// Bidirectionals
aud_bclk,
aud_adclrck,
aud_daclrck,
// Outputs
read_ready, write_ready,
readdata_left, readdata_right,
aud_dacdat
);
endmodule
module control(clock, reset, write_ready, write, frequency,
writedata_left, writedata_right);
input clock, reset, write_ready;
input [3:0] switches;
output reg write;
output reg [23:0] writedata_left, writedata_right;
// output reg [3:0] frequency;
reg [7:0] counter;
// reg [2:0] current_state, next_state;
/*
localparam NO_SOUND = 3'b000,
FREQ_ONE = 3'b001,
FREQ_TWO = 3'b010,
FREQ_THREE = 3'b011,
FREQ_FOUR = 3'b100;
*/
always @(posedge clock) begin
if (!reset) begin
// current_state <= NO_SOUND;
counter <= 8'b0;
end
else begin
// current_state <= next_state;
if (write_ready) begin
write <= 1'b1;
counter[7:0] <= counter[7:0] + 1'b1;
if (switches == 4'b0000) begin
writedata_left[23] <= counter[0];
writedata_right[23] <= counter[0];
end
else if (switches == 4'b0001) begin
writedata_left[23] <= counter[4];
writedata_right[23] <= counter[4];
end
else if (switches == 4'b0010) begin
writedata_left[23] <= counter[5];
writedata_right[23] <= counter[5];
end
else if (switches == 4'b0100) begin
writedata_left[23] <= counter[6];
writedata_right[23] <= counter[6];
end
else if (switches == 4'b1000) begin
writedata_left[23] <= counter[7];
writedata_right[23] <= counter[7];
end
end
end
end
/*
always @(*)
begin: state_table
case(current_state)
NO_SOUND:
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD2_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD2_PP_BLACKBOX_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv5sd2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD2_PP_BLACKBOX_V
|
// $Id: vcr_ip_ctrl_mac.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// input port controller
//==============================================================================
module vcr_ip_ctrl_mac
(clk, reset, router_address, channel_in, route_ivc_op, route_ivc_orc,
allocated_ivc, flit_valid_ivc, flit_head_ivc, flit_tail_ivc,
free_nonspec_ivc, vc_gnt_ivc, vc_sel_ivc_ovc, sw_gnt, sw_sel_ivc, sw_gnt_op,
almost_full_op_ovc, full_op_ovc, flit_data, flow_ctrl_out, error);
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
// total buffer size per port in flits
parameter buffer_size = 32;
// number of message classes (e.g. request, reply)
parameter num_message_classes = 2;
// number of resource classes (e.g. minimal, adaptive)
parameter num_resource_classes = 2;
// width required to select individual resource class
localparam resource_class_idx_width = clogb(num_resource_classes);
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs per class
parameter num_vcs_per_class = 1;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// width required to select individual VC
localparam vc_idx_width = clogb(num_vcs);
// number of routers in each dimension
parameter num_routers_per_dim = 4;
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// number of dimensions in network
parameter num_dimensions = 2;
// width required to select individual router in entire network
localparam router_addr_width = num_dimensions * dim_addr_width;
// number of nodes per router (a.k.a. consentration factor)
parameter num_nodes_per_router = 1;
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// width of global addresses
localparam addr_width = router_addr_width + node_addr_width;
// connectivity within each dimension
parameter connectivity = `CONNECTIVITY_LINE;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// select packet format
parameter packet_format = `PACKET_FORMAT_EXPLICIT_LENGTH;
// select type of flow control
parameter flow_ctrl_type = `FLOW_CTRL_TYPE_CREDIT;
// width of flow control signals
localparam flow_ctrl_width
= (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
-1;
// maximum payload length (in flits)
// (note: only used if packet_format==`PACKET_FORMAT_EXPLICIT_LENGTH)
parameter max_payload_length = 4;
// minimum payload length (in flits)
// (note: only used if packet_format==`PACKET_FORMAT_EXPLICIT_LENGTH)
parameter min_payload_length = 1;
// number of bits required to represent all possible payload sizes
localparam payload_length_width
= clogb(max_payload_length-min_payload_length+1);
// enable link power management
parameter enable_link_pm = 1;
// width of link management signals
localparam link_ctrl_width = enable_link_pm ? 1 : 0;
// width of flit control signals
localparam flit_ctrl_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(1 + vc_idx_width + 1 + 1) :
(packet_format == `PACKET_FORMAT_TAIL_ONLY) ?
(1 + vc_idx_width + 1) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(1 + vc_idx_width + 1) :
-1;
// width of flit payload data
parameter flit_data_width = 64;
// channel width
localparam channel_width
= link_ctrl_width + flit_ctrl_width + flit_data_width;
// filter out illegal destination ports
// (the intent is to allow synthesis to optimize away the logic associated
// with such turns)
parameter restrict_turns = 1;
// width required for lookahead routing information
localparam lar_info_width = port_idx_width + resource_class_idx_width;
// select routing function type
parameter routing_type = `ROUTING_TYPE_PHASED_DOR;
// total number of bits required for storing routing information
localparam dest_info_width
= (routing_type == `ROUTING_TYPE_PHASED_DOR) ?
(num_resource_classes * router_addr_width + node_addr_width) :
-1;
// total number of bits required for routing-related information
localparam route_info_width = lar_info_width + dest_info_width;
// total number of bits of header information encoded in header flit payload
localparam header_info_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
route_info_width :
(packet_format == `PACKET_FORMAT_TAIL_ONLY) ?
route_info_width :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(route_info_width + payload_length_width) :
-1;
// select order of dimension traversal
parameter dim_order = `DIM_ORDER_ASCENDING;
// select implementation variant for flit buffer register file
parameter fb_regfile_type = `REGFILE_TYPE_FF_2D;
// select flit buffer management scheme
parameter fb_mgmt_type = `FB_MGMT_TYPE_STATIC;
// improve timing for peek access
parameter fb_fast_peek = 1;
// use explicit pipeline register between flit buffer and crossbar?
parameter explicit_pipeline_register = 0;
// gate flit buffer write port if bypass succeeds
// (requires explicit pipeline register; may increase cycle time)
parameter gate_buffer_write = 0;
// enable speculative switch allocation
parameter sw_alloc_spec = 1;
// select whether to exclude full or non-empty VCs from VC allocation
parameter elig_mask = `ELIG_MASK_NONE;
// VC allocation is atomic
localparam atomic_vc_allocation = (elig_mask == `ELIG_MASK_USED);
// configure error checking logic
parameter error_capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;
// ID of current input port
parameter port_id = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// current router's address
input [0:router_addr_width-1] router_address;
// incoming channel
input [0:channel_width-1] channel_in;
// destination port
output [0:num_vcs*num_ports-1] route_ivc_op;
wire [0:num_vcs*num_ports-1] route_ivc_op;
// select next resource class
output [0:num_vcs*num_resource_classes-1] route_ivc_orc;
wire [0:num_vcs*num_resource_classes-1] route_ivc_orc;
// VC has an output VC allocated to it
output [0:num_vcs-1] allocated_ivc;
wire [0:num_vcs-1] allocated_ivc;
// VC has a flit available
output [0:num_vcs-1] flit_valid_ivc;
wire [0:num_vcs-1] flit_valid_ivc;
// flit is head flit
output [0:num_vcs-1] flit_head_ivc;
wire [0:num_vcs-1] flit_head_ivc;
// flit is tail flit
output [0:num_vcs-1] flit_tail_ivc;
wire [0:num_vcs-1] flit_tail_ivc;
// credit availability if output VC has been allocated
output [0:num_vcs-1] free_nonspec_ivc;
wire [0:num_vcs-1] free_nonspec_ivc;
// VC allocation successful
input [0:num_vcs-1] vc_gnt_ivc;
// granted output VC
input [0:num_vcs*num_vcs-1] vc_sel_ivc_ovc;
// switch grant
input sw_gnt;
// select VC for switch grant
input [0:num_vcs-1] sw_sel_ivc;
// switch grant for output ports
input [0:num_ports-1] sw_gnt_op;
// which output VC have only a single credit left?
input [0:num_ports*num_vcs-1] almost_full_op_ovc;
// which output VC have no credit left?
input [0:num_ports*num_vcs-1] full_op_ovc;
// outgoing flit data
output [0:flit_data_width-1] flit_data;
wire [0:flit_data_width-1] flit_data;
// outgoing flow control signals
output [0:flow_ctrl_width-1] flow_ctrl_out;
wire [0:flow_ctrl_width-1] flow_ctrl_out;
// internal error condition detected
output error;
wire error;
//---------------------------------------------------------------------------
// input stage
//---------------------------------------------------------------------------
wire fb_full;
wire input_stage_active;
assign input_stage_active = ~fb_full;
wire flit_valid_in;
wire flit_head_in;
wire [0:num_vcs-1] flit_head_in_ivc;
wire flit_tail_in;
wire [0:num_vcs-1] flit_tail_in_ivc;
wire [0:flit_data_width-1] flit_data_in;
wire [0:num_vcs-1] flit_sel_in_ivc;
rtr_channel_input
#(.num_vcs(num_vcs),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.route_info_width(route_info_width),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.reset_type(reset_type))
chi
(.clk(clk),
.reset(reset),
.active(input_stage_active),
.channel_in(channel_in),
.flit_valid_out(flit_valid_in),
.flit_head_out(flit_head_in),
.flit_head_out_ivc(flit_head_in_ivc),
.flit_tail_out(flit_tail_in),
.flit_tail_out_ivc(flit_tail_in_ivc),
.flit_data_out(flit_data_in),
.flit_sel_out_ivc(flit_sel_in_ivc));
wire [0:header_info_width-1] header_info_in;
assign header_info_in = flit_data_in[0:header_info_width-1];
//---------------------------------------------------------------------------
// switch allocation
//---------------------------------------------------------------------------
wire [0:num_vcs-1] free_spec_ivc;
wire flit_sent;
generate
if(sw_alloc_spec)
begin
wire [0:num_vcs-1] spec_mask_ivc;
if(elig_mask == `ELIG_MASK_NONE)
assign spec_mask_ivc
= allocated_ivc | (vc_gnt_ivc & free_spec_ivc);
else
assign spec_mask_ivc = allocated_ivc | vc_gnt_ivc;
wire spec_mask;
c_select_1ofn
#(.num_ports(num_vcs),
.width(1))
spec_mask_sel
(.select(sw_sel_ivc),
.data_in(spec_mask_ivc),
.data_out(spec_mask));
assign flit_sent = sw_gnt & spec_mask;
end
else
assign flit_sent = sw_gnt;
endgenerate
//---------------------------------------------------------------------------
// input vc controllers
//---------------------------------------------------------------------------
wire [0:num_vcs-1] fb_pop_tail_ivc;
wire [0:header_info_width-1] fb_pop_next_header_info;
wire [0:num_vcs-1] fb_almost_empty_ivc;
wire [0:num_vcs-1] fb_empty_ivc;
wire [0:num_vcs*lar_info_width-1] next_lar_info_ivc;
wire [0:num_vcs*3-1] ivcc_errors_ivc;
genvar ivc;
generate
for(ivc = 0; ivc < num_vcs; ivc = ivc + 1)
begin:ivcs
//-------------------------------------------------------------------
// connect inputs
//-------------------------------------------------------------------
wire flit_sel_in;
assign flit_sel_in = flit_sel_in_ivc[ivc];
wire flit_head_in;
assign flit_head_in = flit_head_in_ivc[ivc];
wire flit_tail_in;
assign flit_tail_in = flit_tail_in_ivc[ivc];
wire vc_gnt;
assign vc_gnt = vc_gnt_ivc[ivc];
wire [0:num_vcs-1] vc_sel_ovc;
assign vc_sel_ovc = vc_sel_ivc_ovc[ivc*num_vcs:(ivc+1)*num_vcs-1];
wire sw_sel;
assign sw_sel = sw_sel_ivc[ivc];
wire fb_pop_tail;
assign fb_pop_tail = fb_pop_tail_ivc[ivc];
wire fb_almost_empty;
assign fb_almost_empty = fb_almost_empty_ivc[ivc];
//-------------------------------------------------------------------
// input VC controller
//-------------------------------------------------------------------
wire fb_empty;
assign fb_empty = fb_empty_ivc[ivc];
wire [0:num_ports-1] route_op;
wire [0:num_resource_classes-1] route_orc;
wire flit_valid;
wire flit_head;
wire flit_tail;
wire [0:lar_info_width-1] next_lar_info;
wire allocated;
wire free_nonspec;
wire free_spec;
wire [0:2] ivcc_errors;
vcr_ivc_ctrl
#(.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.restrict_turns(restrict_turns),
.routing_type(routing_type),
.dim_order(dim_order),
.elig_mask(elig_mask),
.sw_alloc_spec(sw_alloc_spec),
.fb_mgmt_type(fb_mgmt_type),
.explicit_pipeline_register(explicit_pipeline_register),
.vc_id(ivc),
.port_id(port_id),
.reset_type(reset_type))
ivcc
(.clk(clk),
.reset(reset),
.router_address(router_address),
.flit_valid_in(flit_valid_in),
.flit_head_in(flit_head_in),
.flit_tail_in(flit_tail_in),
.flit_sel_in(flit_sel_in),
.header_info_in(header_info_in),
.fb_pop_tail(fb_pop_tail),
.fb_pop_next_header_info(fb_pop_next_header_info),
.almost_full_op_ovc(almost_full_op_ovc),
.full_op_ovc(full_op_ovc),
.route_op(route_op),
.route_orc(route_orc),
.vc_gnt(vc_gnt),
.vc_sel_ovc(vc_sel_ovc),
.sw_gnt(sw_gnt),
.sw_sel(sw_sel),
.sw_gnt_op(sw_gnt_op),
.flit_valid(flit_valid),
.flit_head(flit_head),
.flit_tail(flit_tail),
.next_lar_info(next_lar_info),
.fb_almost_empty(fb_almost_empty),
.fb_empty(fb_empty),
.allocated(allocated),
.free_nonspec(free_nonspec),
.free_spec(free_spec),
.errors(ivcc_errors));
//-------------------------------------------------------------------
// connect outputs
//-------------------------------------------------------------------
assign route_ivc_op[ivc*num_ports:(ivc+1)*num_ports-1] = route_op;
assign route_ivc_orc[ivc*num_resource_classes:
(ivc+1)*num_resource_classes-1] = route_orc;
assign flit_valid_ivc[ivc] = flit_valid;
assign flit_head_ivc[ivc] = flit_head;
assign flit_tail_ivc[ivc] = flit_tail;
assign next_lar_info_ivc[ivc*lar_info_width:(ivc+1)*lar_info_width-1]
= next_lar_info;
assign allocated_ivc[ivc] = allocated;
assign free_nonspec_ivc[ivc] = free_nonspec;
assign free_spec_ivc[ivc] = free_spec;
assign ivcc_errors_ivc[ivc*3:(ivc+1)*3-1] = ivcc_errors;
end
endgenerate
//---------------------------------------------------------------------------
// flit buffer
//---------------------------------------------------------------------------
wire fb_push_active;
assign fb_push_active = flit_valid_in;
wire fb_push_valid;
assign fb_push_valid = flit_valid_in;
wire fb_push_head;
assign fb_push_head = flit_head_in;
wire fb_push_tail;
assign fb_push_tail = flit_tail_in;
wire [0:num_vcs-1] fb_push_sel_ivc;
assign fb_push_sel_ivc = flit_sel_in_ivc;
wire [0:flit_data_width-1] fb_push_data;
assign fb_push_data = flit_data_in;
wire alloc_active;
assign alloc_active = flit_valid_in | ~&fb_empty_ivc;
wire fb_pop_active;
assign fb_pop_active = alloc_active;
wire fb_pop_valid;
assign fb_pop_valid = flit_sent;
wire [0:num_vcs-1] fb_pop_sel_ivc;
assign fb_pop_sel_ivc = sw_sel_ivc;
wire [0:flit_data_width-1] fb_pop_data;
wire [0:num_vcs*2-1] fb_errors_ivc;
rtr_flit_buffer
#(.num_vcs(num_vcs),
.buffer_size(buffer_size),
.flit_data_width(flit_data_width),
.header_info_width(header_info_width),
.regfile_type(fb_regfile_type),
.mgmt_type(fb_mgmt_type),
.fast_peek(fb_fast_peek),
.explicit_pipeline_register(explicit_pipeline_register),
.gate_buffer_write(gate_buffer_write),
.atomic_vc_allocation(atomic_vc_allocation),
.enable_bypass(1),
.reset_type(reset_type))
fb
(.clk(clk),
.reset(reset),
.push_active(fb_push_active),
.push_valid(fb_push_valid),
.push_head(fb_push_head),
.push_tail(fb_push_tail),
.push_sel_ivc(fb_push_sel_ivc),
.push_data(fb_push_data),
.pop_active(fb_pop_active),
.pop_valid(fb_pop_valid),
.pop_sel_ivc(fb_pop_sel_ivc),
.pop_data(fb_pop_data),
.pop_tail_ivc(fb_pop_tail_ivc),
.pop_next_header_info(fb_pop_next_header_info),
.almost_empty_ivc(fb_almost_empty_ivc),
.empty_ivc(fb_empty_ivc),
.full(fb_full),
.errors_ivc(fb_errors_ivc));
//---------------------------------------------------------------------------
// update lookahead routing info
//---------------------------------------------------------------------------
wire [0:lar_info_width-1] next_lar_info;
c_select_1ofn
#(.num_ports(num_vcs),
.width(lar_info_width))
netx_lar_info_sel
(.select(sw_sel_ivc),
.data_in(next_lar_info_ivc),
.data_out(next_lar_info));
wire flit_head;
wire [0:lar_info_width-1] lar_info_s, lar_info_q;
assign lar_info_s = flit_head ? next_lar_info : lar_info_q;
c_dff
#(.width(lar_info_width),
.reset_type(reset_type))
lar_infoq
(.clk(clk),
.reset(1'b0),
.active(alloc_active),
.d(lar_info_s),
.q(lar_info_q));
wire flit_head_prev;
assign flit_data[0:lar_info_width-1]
= flit_head_prev ? lar_info_q : fb_pop_data[0:lar_info_width-1];
assign flit_data[lar_info_width:flit_data_width-1]
= fb_pop_data[lar_info_width:flit_data_width-1];
//---------------------------------------------------------------------------
// generate signals to crossbar module
//---------------------------------------------------------------------------
// NOTE: Because we need to clear it in the cycle after a flit / credit has
// been transmitted, this register cannot be included in any of the other
// clock gating domains. If we could change things such that flits are
// transmitted using edge-based signaling (i.e., transitions), they could be
// included in the clock gating domain controlled by alloc_active.
// Alternatively, we could include the flit_sent_prev term in alloc_active;
// this would allow us to include flit_validq in the gating domain at
// the cost of some unnecessary activity. As synthesis will probably not
// create a clock gating domain for just these two registers, they currently
// will most likely end up being free-running, so this may be a reasonable
// tradeoff.
wire flit_sent_prev;
wire flit_valid_active;
assign flit_valid_active = alloc_active | flit_sent_prev;
wire flit_valid_s, flit_valid_q;
assign flit_valid_s = flit_sent;
c_dff
#(.width(1),
.reset_type(reset_type))
flit_validq
(.clk(clk),
.reset(reset),
.active(flit_valid_active),
.d(flit_valid_s),
.q(flit_valid_q));
assign flit_sent_prev = flit_valid_q;
c_select_1ofn
#(.num_ports(num_vcs),
.width(1))
flit_head_sel
(.select(sw_sel_ivc),
.data_in(flit_head_ivc),
.data_out(flit_head));
wire flit_head_s, flit_head_q;
assign flit_head_s = flit_head;
c_dff
#(.width(1),
.reset_type(reset_type))
flit_headq
(.clk(clk),
.reset(1'b0),
.active(alloc_active),
.d(flit_head_s),
.q(flit_head_q));
assign flit_head_prev = flit_head_q;
//---------------------------------------------------------------------------
// generate outgoing flow control signals
//---------------------------------------------------------------------------
rtr_flow_ctrl_output
#(.num_vcs(num_vcs),
.flow_ctrl_type(flow_ctrl_type),
.reset_type(reset_type))
fco
(.clk(clk),
.reset(reset),
.active(alloc_active),
.fc_event_valid_in(flit_sent),
.fc_event_sel_in_ivc(sw_sel_ivc),
.flow_ctrl_out(flow_ctrl_out));
//---------------------------------------------------------------------------
// error checking
//---------------------------------------------------------------------------
generate
if(error_capture_mode != `ERROR_CAPTURE_MODE_NONE)
begin
wire [0:num_vcs*3+num_vcs*2-1] errors_s, errors_q;
assign errors_s = {ivcc_errors_ivc, fb_errors_ivc};
c_err_rpt
#(.num_errors(num_vcs*3+num_vcs*2),
.capture_mode(error_capture_mode),
.reset_type(reset_type))
chk
(.clk(clk),
.reset(reset),
.active(1'b1),
.errors_in(errors_s),
.errors_out(errors_q));
assign error = |errors_q;
end
else
assign error = 1'bx;
endgenerate
endmodule
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module m_download(//input
clk,
rst,
IN_flit_mem,
v_IN_flit_mem,
In_flit_ctrl,
mem_done_access,
//output
v_m_download,
m_download_flits,
m_download_state
);
//input
input clk;
input rst;
input [15:0] IN_flit_mem;
input v_IN_flit_mem;
input [1:0] In_flit_ctrl;
input mem_done_access;
//output
output v_m_download;
output [175:0] m_download_flits;
output [1:0] m_download_state;
//
reg [1:0] m_download_nstate;
reg [1:0] m_download_cstate;
parameter m_download_idle=2'b00;
parameter m_download_busy=2'b01;
parameter m_download_rdy=2'b10;
reg [15:0] flit_reg1;
reg [15:0] flit_reg2;
reg [15:0] flit_reg3;
reg [15:0] flit_reg4;
reg [15:0] flit_reg5;
reg [15:0] flit_reg6;
reg [15:0] flit_reg7;
reg [15:0] flit_reg8;
reg [15:0] flit_reg9;
reg [15:0] flit_reg10;
reg [15:0] flit_reg11;
assign m_download_state=m_download_cstate;
assign m_download_flits={flit_reg11,flit_reg10,flit_reg9,flit_reg8,flit_reg7,flit_reg6,flit_reg5,flit_reg4,flit_reg3,flit_reg2,flit_reg1};
reg v_m_download;
reg en_flit_m;
reg inc_cnt;
reg fsm_rst;
/// fsm of ic_download
always@(*)
begin
//default values
m_download_nstate=m_download_cstate;
v_m_download=1'b0;
en_flit_m=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
case(m_download_cstate)
m_download_idle:
begin
if(v_IN_flit_mem)
begin
m_download_nstate=m_download_busy;
en_flit_m=1'b1;
end
end
m_download_busy:
begin
if(v_IN_flit_mem)
begin
if(In_flit_ctrl==2'b11)
begin
en_flit_m=1'b1;
m_download_nstate=m_download_rdy;
end
en_flit_m=1'b1;
inc_cnt=1'b1;
end
end
m_download_rdy:
begin
v_m_download=1'b1;
if(mem_done_access)
begin
m_download_nstate=m_download_idle;
fsm_rst=1'b1;
end
end
endcase
end
reg [3:0] cnt;
reg [10:0] en_flits;
// select right inst_word_in
always@(*)
begin
case(cnt)
4'b0000:en_flits=11'b00000000001;
4'b0001:en_flits=11'b00000000010;
4'b0010:en_flits=11'b00000000100;
4'b0011:en_flits=11'b00000001000;
4'b0100:en_flits=11'b00000010000;
4'b0101:en_flits=11'b00000100000;
4'b0110:en_flits=11'b00001000000;
4'b0111:en_flits=11'b00010000000;
4'b1000:en_flits=11'b00100000000;
4'b1001:en_flits=11'b01000000000;
4'b1010:en_flits=11'b10000000000;
default:en_flits=11'b00000000000;
endcase
end
// 1st flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg1<=16'h0000;
else if(en_flits[0]&&en_flit_m)
flit_reg1<=IN_flit_mem;
end
//2ed flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg2<=16'h0000;
else if(en_flits[1]&&en_flit_m)
flit_reg2<=IN_flit_mem;
end
// 3rd flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg3<=16'h0000;
else if(en_flits[2]&&en_flit_m)
flit_reg3<=IN_flit_mem;
end
//4th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg4<=16'h0000;
else if(en_flits[3]&&en_flit_m)
flit_reg4<=IN_flit_mem;
end
//5th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg5<=16'h0000;
else if(en_flits[4]&&en_flit_m)
flit_reg5<=IN_flit_mem;
end
//6th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg6<=16'h0000;
else if(en_flits[5]&&en_flit_m)
flit_reg6<=IN_flit_mem;
end
//7th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg7<=16'h0000;
else if(en_flits[6]&&en_flit_m)
flit_reg7<=IN_flit_mem;
end
//8th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg8<=16'h0000;
else if(en_flits[7]&&en_flit_m)
flit_reg8<=IN_flit_mem;
end
//9th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg9<=16'h0000;
else if(en_flits[8]&&en_flit_m)
flit_reg9<=IN_flit_mem;
end
//10th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg10<=16'h0000;
else if(en_flits[9]&&en_flit_m)
flit_reg10<=IN_flit_mem;
end
//11th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg11<=16'h0000;
else if(en_flits[10]&&en_flit_m)
flit_reg11<=IN_flit_mem;
end
// fsm regs
always@(posedge clk)
begin
if(rst)
m_download_cstate<=2'b00;
else
m_download_cstate<=m_download_nstate;
end
//counter reg
always@(posedge clk)
begin
if(rst||fsm_rst)
cnt<=3'b000;
else if(inc_cnt)
cnt<=cnt+3'b001;
end
endmodule |
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 1999-2008 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose : synthesizable CRC function
// * polynomial: x^5 + x^2 + 1
// * data width: 5
//
// Info : [email protected]
// http://www.easics.com
////////////////////////////////////////////////////////////////////////////////
module CRC5_D5(
nextCRC5_D5,
Data,
crc
);
// polynomial: x^5 + x^2 + 1
// data width: 5
// convention: t he first serial bit is D[4]
output [4:0] nextCRC5_D5;
input [4:0] Data;
input [4:0] crc;
reg [4:0] d;
reg [4:0] c;
reg [4:0] newcrc;
begin
d = Data;
c = crc;
newcrc[0] = d[3] ^ d[0] ^ c[0] ^ c[3];
newcrc[1] = d[4] ^ d[1] ^ c[1] ^ c[4];
newcrc[2] = d[3] ^ d[2] ^ d[0] ^ c[0] ^ c[2] ^ c[3];
newcrc[3] = d[4] ^ d[3] ^ d[1] ^ c[1] ^ c[3] ^ c[4];
newcrc[4] = d[4] ^ d[2] ^ c[2] ^ c[4];
nextCRC5_D5 = newcrc;
end
endfunction
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_ram
(
data,
rdaddress,
wraddress,
wren, clock,
q
);
parameter DATA_WIDTH=36;
parameter ADDR_WIDTH=8;
input [(DATA_WIDTH-1):0] data;
input [(ADDR_WIDTH-1):0] rdaddress, wraddress;
input wren, clock;
output reg [(DATA_WIDTH-1):0] q;
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @ (posedge clock)
begin
if (wren)
ram[wraddress] <= data[DATA_WIDTH-1:0];
q <= ram[rdaddress];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NOR2_FUNCTIONAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_FUNCTIONAL_PP_V |
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